include/configs/aev.h

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2005
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  20 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  21 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  22 #undef CONFIG_TQM5200_REV100            /*  define for revision 100 modules */
  23 #define CONFIG_STK52XX          1       /* ... on a STK52XX base board */
  24 #define CONFIG_STK52XX_REV100   1       /*  define for revision 100 baseboards */
  25 #define CONFIG_AEVFIFO          1
  26 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  27
  28 /*
  29  * Valid values for CONFIG_SYS_TEXT_BASE are:
  30  * 0xFC000000   boot low (standard configuration with room for
  31  *              max 64 MByte Flash ROM)
  32  * 0xFFF00000   boot high (for a backup copy of U-Boot)
  33  * 0x00100000   boot from RAM (for testing only)
  34  */
  35 #ifndef CONFIG_SYS_TEXT_BASE
  36 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  37 #endif
  38
  39 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  40
  41 /*
  42  * Serial console configuration
  43  */
  44 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  45 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  46 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  47
  48 /*
  49  * PCI Mapping:
  50  * 0x40000000 - 0x4fffffff - PCI Memory
  51  * 0x50000000 - 0x50ffffff - PCI IO Space
  52  */
  53 #ifdef CONFIG_AEVFIFO
  54 #define CONFIG_PCI              1
  55 #define CONFIG_PCI_PNP          1
  56 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  57 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE         1
  58
  59 #define CONFIG_PCI_MEM_BUS      0x40000000
  60 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  61 #define CONFIG_PCI_MEM_SIZE     0x10000000
  62
  63 #define CONFIG_PCI_IO_BUS       0x50000000
  64 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  65 #define CONFIG_PCI_IO_SIZE      0x01000000
  66
  67 #define CONFIG_EEPRO100         1
  68 #define CONFIG_SYS_RX_ETH_BUFFER        8  /* use 8 rx buffer on eepro100  */
  69 #define CONFIG_NS8382X          1
  70 #endif  /* CONFIG_AEVFIFO */
  71
  72 /* Partitions */
  73 #define CONFIG_MAC_PARTITION
  74 #define CONFIG_DOS_PARTITION
  75 #define CONFIG_ISO_PARTITION
  76
  77 /* POST support */
  78 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY   | \
  79                                  CONFIG_SYS_POST_CPU       | \
  80                                  CONFIG_SYS_POST_I2C)
  81
  82 #ifdef CONFIG_POST
  83 /* preserve space for the post_word at end of on-chip SRAM */
  84 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
  85 #endif
  86
  87
  88 /*
  89  * BOOTP options
  90  */
  91 #define CONFIG_BOOTP_BOOTFILESIZE
  92 #define CONFIG_BOOTP_BOOTPATH
  93 #define CONFIG_BOOTP_GATEWAY
  94 #define CONFIG_BOOTP_HOSTNAME
  95
  96
  97 /*
  98  * Command line configuration.
  99  */
 100 #include <config_cmd_default.h>
 101
 102 #define CONFIG_CMD_ASKENV
 103 #define CONFIG_CMD_DATE
 104 #define CONFIG_CMD_DHCP
 105 #define CONFIG_CMD_ECHO
 106 #define CONFIG_CMD_EEPROM
 107 #define CONFIG_CMD_I2C
 108 #define CONFIG_CMD_MII
 109 #define CONFIG_CMD_NFS
 110 #define CONFIG_CMD_PCI
 111 #define CONFIG_CMD_PING
 112 #define CONFIG_CMD_REGINFO
 113 #define CONFIG_CMD_SNTP
 114
 115 #ifdef CONFIG_POST
 116 #define CONFIG_CMD_DIAG
 117 #endif
 118
 119
 120 #define CONFIG_TIMESTAMP                /* display image timestamps */
 121
 122 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000)                /* Boot low */
 123 #   define CONFIG_SYS_LOWBOOT           1
 124 #endif
 125
 126 /*
 127  * Autobooting
 128  */
 129 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 130
 131 #define CONFIG_PREBOOT  "echo;" \
 132         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 133         "echo"
 134
 135 #undef  CONFIG_BOOTARGS
 136
 137 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 138         "netdev=eth0\0"                                                 \
 139         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 140         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 141         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 142                 "nfsroot=${serverip}:${rootpath} "                      \
 143                 "console=ttyS0,${baudrate}\0"                           \
 144         "addip=setenv bootargs ${bootargs} "                            \
 145                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 146                 ":${hostname}:${netdev}:off panic=1\0"                  \
 147         "flash_self=run ramargs addip;"                                 \
 148                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 149         "flash_nfs=run nfsargs addip;"                                  \
 150                 "bootm ${kernel_addr}\0"                                \
 151         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 152         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 153         "load=tftp 200000 ${u-boot}\0"                                  \
 154         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 155         "update=protect off FC000000 FC05FFFF;"                         \
 156                 "erase FC000000 FC05FFFF;"                              \
 157                 "cp.b 200000 FC000000 ${filesize};"                     \
 158                 "protect on FC000000 FC05FFFF\0"                        \
 159         ""
 160
 161 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 162
 163 /*
 164  * IPB Bus clocking configuration.
 165  */
 166 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 167
 168 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 169 /*
 170  * PCI Bus clocking configuration
 171  *
 172  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 173  * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 174  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 175  */
 176 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2    /* define for 66MHz speed */
 177 #endif
 178
 179 /*
 180  * I2C configuration
 181  */
 182 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 183 #ifdef CONFIG_TQM5200_REV100
 184 #define CONFIG_SYS_I2C_MODULE           1       /* Select I2C module #1 for rev. 100 board */
 185 #else
 186 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 for all other revs */
 187 #endif
 188
 189 /*
 190  * I2C clock frequency
 191  *
 192  * Please notice, that the resulting clock frequency could differ from the
 193  * configured value. This is because the I2C clock is derived from system
 194  * clock over a frequency divider with only a few divider values. U-boot
 195  * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 196  * approximation allways lies below the configured value, never above.
 197  */
 198 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 199 #define CONFIG_SYS_I2C_SLAVE            0x7F
 200
 201 /*
 202  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 203  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 204  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 205  * same configuration could be used.
 206  */
 207 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 208 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 209 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write */
 210 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 211
 212 /*
 213  * Flash configuration
 214  */
 215 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
 216
 217 /* use CFI flash driver if no module variant is spezified */
 218 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 219 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 220 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_BOOTCS_START }
 221 #define CONFIG_SYS_FLASH_EMPTY_INFO
 222 #define CONFIG_SYS_FLASH_SIZE           0x04000000 /* 64 MByte */
 223 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 224 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* not supported yet for AMD */
 225
 226 #if !defined(CONFIG_SYS_LOWBOOT)
 227 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
 228 #else   /* CONFIG_SYS_LOWBOOT */
 229 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 230 #endif  /* CONFIG_SYS_LOWBOOT */
 231 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 232                                            (= chip selects) */
 233 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 234 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 235
 236
 237 /*
 238  * Environment settings
 239  */
 240 #define CONFIG_ENV_IS_IN_FLASH  1
 241 #define CONFIG_ENV_SIZE         0x10000
 242 #define CONFIG_ENV_SECT_SIZE    0x20000
 243 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 244 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 245
 246 /*
 247  * Memory map
 248  */
 249 #define CONFIG_SYS_MBAR         0xF0000000
 250 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 251 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 252
 253 /* Use ON-Chip SRAM until RAM will be available */
 254 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 255 #ifdef CONFIG_POST
 256 /* preserve space for the post_word at end of on-chip SRAM */
 257 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 258 #else
 259 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 260 #endif
 261
 262
 263 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 264 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 265
 266 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 267 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 268 #   define CONFIG_SYS_RAMBOOT           1
 269 #endif
 270
 271 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384 kB for Monitor   */
 272 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 273 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 274
 275 /*
 276  * Ethernet configuration
 277  */
 278 #define CONFIG_MPC5xxx_FEC      1
 279 #define CONFIG_MPC5xxx_FEC_MII100
 280 /*
 281  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 282  */
 283 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 284 #define CONFIG_PHY_ADDR         0x00
 285
 286 /*
 287  * GPIO configuration
 288  *
 289  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 290  *      Bit 0 (mask: 0x80000000): 1
 291  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 292  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 293  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 294  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 295  *            (because, there I2C1 is used as I2C bus)
 296  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 297  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 298  *      000 -> All PSC2 pins are GIOPs
 299  *      001 -> CAN1/2 on PSC2 pins
 300  *             Use for REV100 STK52xx boards
 301  * use PSC6:
 302  *   on STK52xx:
 303  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 304  *      Bits 9:11 (mask: 0x00700000):
 305  *         101 -> PSC6 : Extended POST test is not available
 306  *   on MINI-FAP and TQM5200_IB:
 307  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 308  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 309  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 310  *   tests.
 311  */
 312 #define CONFIG_SYS_GPS_PORT_CONFIG      0x81500014
 313
 314 /*
 315  * RTC configuration
 316  */
 317 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 318
 319 /*
 320  * Miscellaneous configurable options
 321  */
 322 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 323 #if defined(CONFIG_CMD_KGDB)
 324 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 325 #else
 326 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 327 #endif
 328 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 329 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 330 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 331
 332 /* Enable an alternate, more extensive memory test */
 333 #define CONFIG_SYS_ALT_MEMTEST
 334
 335 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 336 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 337
 338 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 339
 340 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 341 #if defined(CONFIG_CMD_KGDB)
 342 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 343 #endif
 344
 345 /*
 346  * Enable loopw command.
 347  */
 348 #define CONFIG_LOOPW
 349
 350 /*
 351  * Various low-level settings
 352  */
 353 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 354 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 355
 356 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 357 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 358 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 359 #define CONFIG_SYS_BOOTCS_CFG           0x0008DF30 /* for pci_clk  = 66 MHz */
 360 #else
 361 #define CONFIG_SYS_BOOTCS_CFG           0x0004DF30 /* for pci_clk = 33 MHz */
 362 #endif
 363 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 364 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 365
 366 #define CONFIG_LAST_STAGE_INIT
 367
 368 /*
 369  * SRAM - Do not map below 2 GB in address space, because this area is used
 370  * for SDRAM autosizing.
 371  */
 372 #define CONFIG_SYS_CS2_START            0xE5000000
 373 #define CONFIG_SYS_CS2_SIZE             0x80000         /* 512 kByte */
 374 #define CONFIG_SYS_CS2_CFG              0x0004D930
 375
 376 /*
 377  * Grafic controller - Do not map below 2 GB in address space, because this
 378  * area is used for SDRAM autosizing.
 379  */
 380 #define SM501_FB_BASE           0xE0000000
 381 #define CONFIG_SYS_CS1_START           (SM501_FB_BASE)
 382 #define CONFIG_SYS_CS1_SIZE            0x4000000       /* 64 MByte */
 383 #define CONFIG_SYS_CS1_CFG             0x8F48FF70
 384 #define SM501_MMIO_BASE         CONFIG_SYS_CS1_START + 0x03E00000
 385
 386 #define CONFIG_SYS_CS_BURST            0x00000000
 387 #define CONFIG_SYS_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
 388
 389 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 390
 391 #endif /* __CONFIG_H */