include/configs/atngw100mkii.h

   1 /*
   2  * Copyright (C) 2006 Atmel Corporation
   3  *
   4  * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
   5  *
   6  * Configuration settings for the AVR32 Network Gateway
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <asm/arch/hardware.h>
  14
  15 #define CONFIG_AVR32
  16 #define CONFIG_AT32AP
  17 #define CONFIG_AT32AP7000
  18 #define CONFIG_ATNGW100MKII
  19
  20 /*
  21  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  22  * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
  23  * and the PBA bus to run at 1/4 the PLL frequency.
  24  */
  25 #define CONFIG_PLL
  26 #define CONFIG_SYS_POWER_MANAGER
  27 #define CONFIG_SYS_OSC0_HZ              20000000
  28 #define CONFIG_SYS_PLL0_DIV             1
  29 #define CONFIG_SYS_PLL0_MUL             7
  30 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
  31 /*
  32  * Set the CPU running at:
  33  * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
  34  */
  35 #define CONFIG_SYS_CLKDIV_CPU           0
  36 /*
  37  * Set the HSB running at:
  38  * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
  39  */
  40 #define CONFIG_SYS_CLKDIV_HSB           1
  41 /*
  42  * Set the PBA running at:
  43  * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
  44  */
  45 #define CONFIG_SYS_CLKDIV_PBA           2
  46 /*
  47  * Set the PBB running at:
  48  * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
  49  */
  50 #define CONFIG_SYS_CLKDIV_PBB           1
  51
  52 /* Reserve VM regions for NOR flash, NAND flash and SDRAM */
  53 #define CONFIG_SYS_NR_VM_REGIONS        3
  54
  55 /*
  56  * The PLLOPT register controls the PLL like this:
  57  *   icp = PLLOPT<2>
  58  *   ivco = PLLOPT<1:0>
  59  *
  60  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  61  */
  62 #define CONFIG_SYS_PLL0_OPT             0x04
  63
  64 #define CONFIG_USART_BASE               ATMEL_BASE_USART1
  65 #define CONFIG_USART_ID                 1
  66
  67 /* User serviceable stuff */
  68 #define CONFIG_DOS_PARTITION
  69
  70 #define CONFIG_CMDLINE_TAG
  71 #define CONFIG_SETUP_MEMORY_TAGS
  72 #define CONFIG_INITRD_TAG
  73
  74 #define CONFIG_STACKSIZE                (2048)
  75
  76 #define CONFIG_BAUDRATE                 115200
  77 #define CONFIG_BOOTARGS                                                 \
  78         "root=mtd:main rootfstype=jffs2"
  79 #define CONFIG_BOOTCOMMAND                                              \
  80         "fsload 0x10400000 /uImage; bootm"
  81
  82 /*
  83  * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
  84  * data on the serial line may interrupt the boot sequence.
  85  */
  86 #define CONFIG_BOOTDELAY                1
  87 #define CONFIG_AUTOBOOT
  88 #define CONFIG_AUTOBOOT_KEYED
  89 #define CONFIG_AUTOBOOT_PROMPT          \
  90         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
  91 #define CONFIG_AUTOBOOT_DELAY_STR       "d"
  92 #define CONFIG_AUTOBOOT_STOP_STR        " "
  93
  94 /*
  95  * After booting the board for the first time, new ethernet addresses
  96  * should be generated and assigned to the environment variables
  97  * "ethaddr" and "eth1addr". This is normally done during production.
  98  */
  99 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 100 #define CONFIG_NET_MULTI
 101
 102 /*
 103  * BOOTP/DHCP options
 104  */
 105 #define CONFIG_BOOTP_SUBNETMASK
 106 #define CONFIG_BOOTP_GATEWAY
 107
 108 /*
 109  * Command line configuration.
 110  */
 111 #include <config_cmd_default.h>
 112
 113 #define CONFIG_CMD_ASKENV
 114 #define CONFIG_CMD_DHCP
 115 #define CONFIG_CMD_EXT2
 116 #define CONFIG_CMD_FAT
 117 #define CONFIG_CMD_JFFS2
 118 #define CONFIG_CMD_MMC
 119 #define CONFIG_CMD_SF
 120 #define CONFIG_CMD_SPI
 121 #define CONFIG_CMD_MII
 122
 123 #undef CONFIG_CMD_FPGA
 124 #undef CONFIG_CMD_SETGETDCR
 125 #undef CONFIG_CMD_XIMG
 126
 127 #define CONFIG_ATMEL_USART
 128 #define CONFIG_MACB
 129 #define CONFIG_PORTMUX_PIO
 130 #define CONFIG_SYS_NR_PIOS              5
 131 #define CONFIG_SYS_HSDRAMC
 132 #define CONFIG_MMC
 133 #define CONFIG_GENERIC_ATMEL_MCI
 134 #define CONFIG_GENERIC_MMC
 135 #define CONFIG_ATMEL_SPI
 136
 137 #define CONFIG_SPI_FLASH
 138 #define CONFIG_SPI_FLASH_ATMEL
 139
 140 #define CONFIG_SYS_DCACHE_LINESZ        32
 141 #define CONFIG_SYS_ICACHE_LINESZ        32
 142
 143 #define CONFIG_NR_DRAM_BANKS            1
 144
 145 #define CONFIG_SYS_FLASH_CFI
 146 #define CONFIG_FLASH_CFI_DRIVER
 147 #define CONFIG_SYS_FLASH_PROTECTION
 148
 149 #define CONFIG_SYS_FLASH_BASE           0x00000000
 150 #define CONFIG_SYS_FLASH_SIZE           0x800000
 151 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 152 #define CONFIG_SYS_MAX_FLASH_SECT       135
 153
 154 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 155
 156 #define CONFIG_SYS_INTRAM_BASE          INTERNAL_SRAM_BASE
 157 #define CONFIG_SYS_INTRAM_SIZE          INTERNAL_SRAM_SIZE
 158 #define CONFIG_SYS_SDRAM_BASE           EBI_SDRAM_BASE
 159
 160 #define CONFIG_ENV_IS_IN_FLASH
 161 #define CONFIG_ENV_SIZE                 65536
 162 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 163
 164 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 165
 166 #define CONFIG_SYS_MALLOC_LEN           (256*1024)
 167 #define CONFIG_SYS_DMA_ALLOC_LEN        (16384)
 168
 169 /* Allow 4MB for the kernel run-time image */
 170 #define CONFIG_SYS_LOAD_ADDR            (EBI_SDRAM_BASE + 0x00400000)
 171 #define CONFIG_SYS_BOOTPARAMS_LEN       (16 * 1024)
 172
 173 /* Other configuration settings that shouldn't have to change all that often */
 174 #define CONFIG_SYS_PROMPT               "U-Boot> "
 175 #define CONFIG_SYS_CBSIZE               256
 176 #define CONFIG_SYS_MAXARGS              16
 177 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 178 #define CONFIG_SYS_LONGHELP
 179
 180 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 181 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + 0x1f00000)
 182
 183 #define CONFIG_MTD_DEVICE
 184 #define CONFIG_MTD_PARTITIONS
 185
 186 #endif /* __CONFIG_H */