include/configs/cogent_mpc8xx.h

   1 /*
   2  * (C) Copyright 2000-2010
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * Config header file for Cogent platform using an MPC8xx CPU module
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1       /* This is an MPC860 CPU        */
  21 #define CONFIG_COGENT           1       /* using Cogent Modular Architecture */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  24
  25 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  26 #define CONFIG_MISC_INIT_R              /* Use misc_init_r()            */
  27
  28 /* Cogent Modular Architecture options */
  29 #define CONFIG_CMA286_60_OLD    1       /* ...on an old CMA286-60 CPU module */
  30 #define CONFIG_CMA102           1       /* ...on a CMA102 motherboard   */
  31 #define CONFIG_CMA302           1       /* ...with a CMA302 flash I/O module */
  32
  33 /* serial console configuration */
  34 #undef  CONFIG_8xx_CONS_SMC1
  35 #undef  CONFIG_8xx_CONS_SMC2
  36 #define CONFIG_8xx_CONS_NONE    /* not on 8xx serial ports (eg on cogent m/b) */
  37
  38 #if defined(CONFIG_CMA286_60_OLD)
  39 #define CONFIG_8xx_GCLK_FREQ    33333000 /* define if cant use get_gclk_freq */
  40 #endif
  41
  42 #define CONFIG_BAUDRATE         230400
  43
  44 #define CONFIG_HARD_I2C         /* I2C with hardware support */
  45 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
  46 #define CONFIG_SYS_I2C_SLAVE            0x7F
  47
  48
  49 /*
  50  * BOOTP options
  51  */
  52 #define CONFIG_BOOTP_BOOTFILESIZE
  53 #define CONFIG_BOOTP_BOOTPATH
  54 #define CONFIG_BOOTP_GATEWAY
  55 #define CONFIG_BOOTP_HOSTNAME
  56
  57
  58 /*
  59  * Command line configuration.
  60  */
  61 #include <config_cmd_default.h>
  62
  63 #define CONFIG_CMD_KGDB
  64 #define CONFIG_CMD_I2C
  65
  66 #undef CONFIG_CMD_NET
  67 #undef CONFIG_CMD_NFS
  68
  69 #if 0
  70 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  71 #else
  72 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  73 #endif
  74 #define CONFIG_BOOTCOMMAND      "bootm 04080000 04200000" /* autoboot command*/
  75
  76 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
  77
  78 #if defined(CONFIG_CMD_KGDB)
  79 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
  80 #undef  CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
  81 #define CONFIG_KGDB_NONE                /* define if kgdb on something else */
  82 #define CONFIG_KGDB_INDEX       2       /* which SMC/SCC channel for kgdb */
  83 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
  84 #endif
  85
  86 #define CONFIG_WATCHDOG                 /* turn on platform specific watchdog */
  87
  88 /*
  89  * Miscellaneous configurable options
  90  */
  91 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  92 #if defined(CONFIG_CMD_KGDB)
  93 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  94 #else
  95 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  96 #endif
  97 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  98 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  99 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 100
 101 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
 102 #define CONFIG_SYS_MEMTEST_END          0x01c00000      /* 4 ... 28 MB in DRAM  */
 103
 104 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 105
 106 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 107
 108 #define CONFIG_SYS_ALLOC_DPRAM
 109
 110 /*
 111  * Low Level Configuration Settings
 112  * (address mappings, register initial values, etc.)
 113  * You should know what you are doing if you make changes here.
 114  */
 115
 116 /*-----------------------------------------------------------------------
 117  * Low Level Cogent settings
 118  * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
 119  * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 120  * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 121  * (second 2 for CMA120 only)
 122  */
 123 #define CONFIG_SYS_CMA_MB_BASE          0x00000000      /* base of m/b address space */
 124
 125 #include <configs/cogent_common.h>
 126
 127 #define CONFIG_SYS_CMA_CONS_SERIAL      /* use Cogent motherboard serial for console */
 128 #define CONFIG_CONS_INDEX       1
 129 #define CONFIG_SYS_CMA_LCD_HEARTBEAT    /* define for sec rotator in lcd corner */
 130 #define CONFIG_SHOW_ACTIVITY
 131 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
 132 /*
 133  * flash exists on the motherboard
 134  * set these four according to TOP dipsw:
 135  * TOP on  => ..._FLLOW_...     (boot EPROM space is high so FLASH is low )
 136  * TOP off => ..._FLHIGH_...    (boot EPROM space is low  so FLASH is high)
 137  */
 138 #define CMA_MB_FLASH_EXEC_BASE  CMA_MB_FLLOW_EXEC_BASE
 139 #define CMA_MB_FLASH_EXEC_SIZE  CMA_MB_FLLOW_EXEC_SIZE
 140 #define CMA_MB_FLASH_RDWR_BASE  CMA_MB_FLLOW_RDWR_BASE
 141 #define CMA_MB_FLASH_RDWR_SIZE  CMA_MB_FLLOW_RDWR_SIZE
 142 #endif
 143 #define CMA_MB_FLASH_BASE       CMA_MB_FLASH_EXEC_BASE
 144 #define CMA_MB_FLASH_SIZE       CMA_MB_FLASH_EXEC_SIZE
 145
 146 /*-----------------------------------------------------------------------
 147  * Internal Memory Mapped Register
 148  */
 149 #define CONFIG_SYS_IMMR         0xFF000000
 150
 151 /*-----------------------------------------------------------------------
 152  * Definitions for initial stack pointer and data area (in DPRAM)
 153  */
 154 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 155 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 156 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 157 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 158
 159 /*-----------------------------------------------------------------------
 160  * Start addresses for the final memory configuration
 161  * (Set up by the startup code)
 162  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 163  */
 164 #define CONFIG_SYS_SDRAM_BASE           CMA_MB_RAM_BASE
 165 #ifdef CONFIG_CMA302
 166 #define CONFIG_SYS_FLASH_BASE           CMA_MB_SLOT2_BASE       /* cma302 in slot 2 */
 167 #else
 168 #define CONFIG_SYS_FLASH_BASE           CMA_MB_FLASH_BASE       /* flash on m/b */
 169 #endif
 170 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 171 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 172 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 173
 174 /*
 175  * For booting Linux, the board info and command line data
 176  * have to be in the first 8 MB of memory, since this is
 177  * the maximum mapped by the Linux kernel during initialization.
 178  */
 179 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 180 /*-----------------------------------------------------------------------
 181  * FLASH organization
 182  */
 183 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 184 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip    */
 185
 186 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 187 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 188
 189 #define CONFIG_ENV_IS_IN_FLASH  1
 190 #define CONFIG_ENV_ADDR         CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
 191 #ifdef CONFIG_CMA302
 192 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector     */
 193 #define CONFIG_ENV_SECT_SIZE    (512*1024) /* see README - env sect real size */
 194 #else
 195 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 196 #endif
 197 /*-----------------------------------------------------------------------
 198  * Cache Configuration
 199  */
 200 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 201 #if defined(CONFIG_CMD_KGDB)
 202 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 203 #endif
 204
 205
 206 /*-----------------------------------------------------------------------
 207  * SYPCR - System Protection Control                            11-9
 208  * SYPCR can only be written once after reset!
 209  *-----------------------------------------------------------------------
 210  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 211  */
 212 #if defined(CONFIG_WATCHDOG)
 213 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 214                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 215 #else
 216 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 217 #endif  /* CONFIG_WATCHDOG */
 218
 219 /*-----------------------------------------------------------------------
 220  * SIUMCR - SIU Module Configuration                            11-6
 221  *-----------------------------------------------------------------------
 222  * PCMCIA config., multi-function pin tri-state
 223  */
 224 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 225
 226 /*-----------------------------------------------------------------------
 227  * TBSCR - Time Base Status and Control                         11-26
 228  *-----------------------------------------------------------------------
 229  * Clear Reference Interrupt Status, Timebase freezing enabled
 230  */
 231 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 232
 233 /*-----------------------------------------------------------------------
 234  * PISCR - Periodic Interrupt Status and Control                11-31
 235  *-----------------------------------------------------------------------
 236  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 237  */
 238 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 239
 240 /*-----------------------------------------------------------------------
 241  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 242  *-----------------------------------------------------------------------
 243  * Reset PLL lock status sticky bit, timer expired status bit and timer
 244  * interrupt status bit - leave PLL multiplication factor unchanged !
 245  */
 246 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 247
 248 /*-----------------------------------------------------------------------
 249  * SCCR - System Clock and reset Control Register               15-27
 250  *-----------------------------------------------------------------------
 251  * Set clock output, timebase and RTC source and divider,
 252  * power management and some other internal clocks
 253  */
 254 #define SCCR_MASK       SCCR_EBDF11
 255 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 256                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 257                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 258                          SCCR_DFALCD00)
 259
 260 /*-----------------------------------------------------------------------
 261  * PCMCIA stuff
 262  *-----------------------------------------------------------------------
 263  *
 264  */
 265 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 266 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 267 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 268 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 269 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 270 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 271 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 272 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 273
 274 /*-----------------------------------------------------------------------
 275  *
 276  *-----------------------------------------------------------------------
 277  *
 278  */
 279 /*#define       CONFIG_SYS_DER  0x2002000F*/
 280 #define CONFIG_SYS_DER  0
 281
 282 #if defined(CONFIG_CMA286_60_OLD)
 283
 284 /*
 285  * Init Memory Controller:
 286  *
 287  * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
 288  * they are actually the final settings for this cpu/board, because the
 289  * flash and RAM are on the motherboard, accessed via the CMAbus, and the
 290  * mappings are pretty much fixed.
 291  *
 292  * (the *_SIZE vars must be a power of 2)
 293  */
 294
 295 #define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE            /* EPROM */
 296 #define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
 297 #define CONFIG_SYS_CMA_CS1_BASE CMA_MB_RAM_BASE         /* RAM + I/O SLOT 1 */
 298 #define CONFIG_SYS_CMA_CS1_SIZE (64 << 20)
 299 #define CONFIG_SYS_CMA_CS2_BASE CMA_MB_SLOT2_BASE       /* I/O SLOTS 2 + 3 */
 300 #define CONFIG_SYS_CMA_CS2_SIZE (64 << 20)
 301 #define CONFIG_SYS_CMA_CS3_BASE CMA_MB_ROMLOW_BASE      /* M/B I/O */
 302 #define CONFIG_SYS_CMA_CS3_SIZE (32 << 20)
 303
 304 /*
 305  * CS0 maps the EPROM on the cpu module
 306  * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
 307  *
 308  * Note: We must have already transferred control to the final location
 309  * of the EPROM before these are used, because when BR0/OR0 are set, the
 310  * mirror of the eprom at any other addresses will disappear.
 311  */
 312
 313 /* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
 314 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
 315 /* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
 316 #define CONFIG_SYS_OR0_PRELIM   ((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
 317
 318 /*
 319  * CS1 maps motherboard DRAM and motherboard I/O slot 1
 320  * (each 32Mbyte in size)
 321  */
 322
 323 /* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
 324 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
 325 /* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
 326 #define CONFIG_SYS_OR1_PRELIM   ((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
 327
 328 /*
 329  * CS2 maps motherboard I/O slots 2 and 3
 330  * (each 32Mbyte in size)
 331  */
 332
 333 /* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
 334 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
 335 /* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
 336 #define CONFIG_SYS_OR2_PRELIM   ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
 337
 338 /*
 339  * CS3 maps motherboard I/O
 340  * (32Mbyte in size)
 341  */
 342
 343 /* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
 344 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
 345 /* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
 346 #define CONFIG_SYS_OR3_PRELIM   ((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
 347
 348 #endif
 349 #endif  /* __CONFIG_H */