include/configs/cpci5200.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6
   7  */
   8
   9 /*************************************************************************
  10  * (c) 2005 esd gmbh Hannover
  11  *
  12  *
  13  * from IceCube.h file
  14  * by Reinhard Arlt reinhard.arlt@esd-electronics.com
  15  *
  16  *************************************************************************/
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /*
  22  * High Level Configuration Options
  23  * (easy to change)
  24  */
  25
  26 #define CONFIG_MPC5200          1       /* This is an MPC5xxx CPU */
  27 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  28 #define CONFIG_ICECUBE          1       /* ... on IceCube board   */
  29 #define CONFIG_CPCI5200         1       /* ... on CPCI5200  board */
  30 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM        */
  31
  32 #ifndef CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_SYS_TEXT_BASE    0xFFF00000      /* Standard: boot high */
  34 #endif
  35
  36 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* ... running at 33.000000MHz */
  37
  38 #define CONFIG_HIGH_BATS        1       /* High BATs supported    */
  39
  40 /*
  41  * Serial console configuration
  42  */
  43 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  44 #define CONFIG_BAUDRATE         9600    /* ... at 115200 bps */
  45 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  46
  47 /*
  48  * PCI Mapping:
  49  * 0x40000000 - 0x4fffffff - PCI Memory
  50  * 0x50000000 - 0x50ffffff - PCI IO Space
  51  */
  52 #if 1
  53 #define CONFIG_PCI              1
  54 #if 1
  55 #define CONFIG_PCI_PNP          1
  56 #endif
  57 #define CONFIG_PCI_SCAN_SHOW    1
  58 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  59
  60 #define CONFIG_PCI_MEM_BUS      0x40000000
  61 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  62 #define CONFIG_PCI_MEM_SIZE     0x10000000
  63
  64 #define CONFIG_PCI_IO_BUS       0x50000000
  65 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  66 #define CONFIG_PCI_IO_SIZE      0x01000000
  67 #endif
  68
  69 #define CONFIG_MII
  70 #if 0                           /* test-only !!! */
  71 #define CONFIG_EEPRO100         1
  72 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
  73 #define CONFIG_NS8382X          1
  74 #endif
  75
  76 /* Partitions */
  77 #define CONFIG_MAC_PARTITION
  78 #define CONFIG_DOS_PARTITION
  79
  80 /* USB */
  81 #if 0
  82 #define CONFIG_USB_OHCI
  83 #define CONFIG_USB_STORAGE
  84 #endif
  85
  86 /*
  87  * BOOTP options
  88  */
  89 #define CONFIG_BOOTP_BOOTFILESIZE
  90 #define CONFIG_BOOTP_BOOTPATH
  91 #define CONFIG_BOOTP_GATEWAY
  92 #define CONFIG_BOOTP_HOSTNAME
  93
  94
  95 /*
  96  * Command line configuration.
  97  */
  98 #include <config_cmd_default.h>
  99
 100 #if defined(CONFIG_PCI)
 101 #define CONFIG_CMD_PCI
 102 #endif
 103
 104 #define CONFIG_CMD_EEPROM
 105 #define CONFIG_CMD_FAT
 106 #define CONFIG_CMD_IDE
 107 #define CONFIG_CMD_I2C
 108 #define CONFIG_CMD_BSP
 109 #define CONFIG_CMD_ELF
 110 #define CONFIG_CMD_EXT2
 111 #define CONFIG_CMD_DATE
 112
 113 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)        /* Boot low with 16 MB Flash */
 114 #   define CONFIG_SYS_LOWBOOT           1
 115 #   define CONFIG_SYS_LOWBOOT16 1
 116 #endif
 117 #if (CONFIG_SYS_TEXT_BASE == 0xFF800000)        /* Boot low with  8 MB Flash */
 118 #   define CONFIG_SYS_LOWBOOT           1
 119 #   define CONFIG_SYS_LOWBOOT08 1
 120 #endif
 121
 122 /*
 123  * Autobooting
 124  */
 125 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 126
 127 #define CONFIG_PREBOOT  "echo;" \
 128         "echo Welcome to esd CPU CPCI/5200;" \
 129         "echo"
 130
 131 #undef  CONFIG_BOOTARGS
 132
 133 #define CONFIG_EXTRA_ENV_SETTINGS \
 134         "netdev=eth0\0" \
 135         "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
 136         "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
 137         "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
 138         "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
 139         "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
 140         "loadaddr=01000000\0" \
 141         "serverip=192.168.2.99\0" \
 142         "gatewayip=10.0.0.79\0" \
 143         "user=mu\0" \
 144         "target=cpci5200.esd\0" \
 145         "script=cpci5200.bat\0" \
 146         "image=/tftpboot/vxWorks_cpci5200\0" \
 147         "ipaddr=10.0.13.196\0" \
 148         "netmask=255.255.0.0\0" \
 149         ""
 150
 151 #define CONFIG_BOOTCOMMAND      "run flash_vxworks0"
 152
 153 #define CONFIG_RTC_M48T35A      1       /* ST Electronics M48 timekeeper */
 154 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xfd010000
 155 #define CONFIG_SYS_NVRAM_SIZE           32*1024
 156
 157 /*
 158  * IPB Bus clocking configuration.
 159  */
 160 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 161 /*
 162  * I2C configuration
 163  */
 164 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 165 #define CONFIG_SYS_I2C_MODULE           1       /* Select I2C module #1 or #2 */
 166
 167 #define CONFIG_SYS_I2C_SPEED            86000   /* 100 kHz */
 168 #define CONFIG_SYS_I2C_SLAVE            0x7F
 169
 170 /*
 171  * EEPROM configuration
 172  */
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 177 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1
 178 /*
 179  * Flash configuration
 180  */
 181
 182 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant           */
 183 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 184 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 185 #define CONFIG_SYS_FLASH_INCREMENT      0x01000000
 186 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00000000)
 187 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 188 #define CONFIG_SYS_MAX_FLASH_SECT       128
 189
 190 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware protection           */
 191 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)  */
 192
 193 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 194 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 195
 196 /*
 197  * Environment settings
 198  */
 199 #if 1                           /* test-only */
 200 #define CONFIG_ENV_IS_IN_FLASH  1
 201 #define CONFIG_ENV_SIZE         0x20000
 202 #define CONFIG_ENV_SECT_SIZE    0x20000
 203 #define CONFIG_ENV_OVERWRITE    1
 204 #else
 205 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 206 #define CONFIG_ENV_OFFSET               0x0000  /* environment starts at the beginning of the EEPROM */
 207 #define CONFIG_ENV_SIZE         0x0400  /* 8192 bytes may be used for env vars */
 208                                    /* total size of a CAT24WC32 is 8192 bytes */
 209 #define CONFIG_ENV_OVERWRITE    1
 210 #endif
 211
 212 /*
 213  * Memory map
 214  */
 215 #define CONFIG_SYS_MBAR         0xF0000000
 216 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 217 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 218
 219 /* Use SRAM until RAM will be available */
 220 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 221 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 222
 223 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 224 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 225
 226 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 227 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 228 #   define CONFIG_SYS_RAMBOOT           1
 229 #endif
 230
 231 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 232 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 233 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 234
 235 /*
 236  * Ethernet configuration
 237  */
 238 #define CONFIG_MPC5xxx_FEC      1
 239 #define CONFIG_MPC5xxx_FEC_MII100
 240 /*
 241  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 242  */
 243 /* #define CONFIG_FEC_10MBIT 1 */
 244 #define CONFIG_PHY_ADDR         0x00
 245 #define CONFIG_UDP_CHECKSUM     1
 246
 247 /*
 248  * GPIO configuration
 249  */
 250 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01052444
 251
 252 /*
 253  * Miscellaneous configurable options
 254  */
 255 #define CONFIG_SYS_LONGHELP             /* undef to save memory     */
 256 #if defined(CONFIG_CMD_KGDB)
 257 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 258 #else
 259 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 260 #endif
 261 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 262 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 263 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 264
 265 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 266 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 267
 268 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 269
 270 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x00000000      /* Pass Ethernet MAC to VxWorks */
 271
 272 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 273 #if defined(CONFIG_CMD_KGDB)
 274 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 275 #endif
 276
 277 /*
 278  * Various low-level settings
 279  */
 280 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 281 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 282
 283 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 284 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 285 #define CONFIG_SYS_BOOTCS_CFG           0x0004DD00
 286
 287 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 288 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 289
 290 #define CONFIG_SYS_CS1_START            0xfd000000
 291 #define CONFIG_SYS_CS1_SIZE             0x00010000
 292 #define CONFIG_SYS_CS1_CFG              0x10101410
 293
 294 #define CONFIG_SYS_CS3_START            0xfd010000
 295 #define CONFIG_SYS_CS3_SIZE             0x00010000
 296 #define CONFIG_SYS_CS3_CFG              0x10109410
 297
 298 #define CONFIG_SYS_CS_BURST             0x00000000
 299 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 300
 301 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 302
 303 /*-----------------------------------------------------------------------
 304  * USB stuff
 305  *-----------------------------------------------------------------------
 306  */
 307 #define CONFIG_USB_CLOCK        0x0001BBBB
 308 #define CONFIG_USB_CONFIG       0x00001000
 309
 310 /*-----------------------------------------------------------------------
 311  * IDE/ATA stuff Supports IDE harddisk
 312  *-----------------------------------------------------------------------
 313  */
 314
 315 #undef  CONFIG_IDE_8xx_PCCARD   /* Use IDE with PC Card Adapter */
 316
 317 #undef  CONFIG_IDE_8xx_DIRECT   /* Direct IDE    not supported  */
 318 #undef  CONFIG_IDE_LED          /* LED   for ide not supported  */
 319
 320 #define CONFIG_IDE_RESET        /* reset for ide supported      */
 321 #define CONFIG_IDE_PREINIT
 322
 323 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 324 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 325
 326 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 327
 328 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 329
 330 /* Offset for data I/O                  */
 331 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 332
 333 /* Offset for normal register accesses  */
 334 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 335
 336 /* Offset for alternate registers       */
 337 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 338
 339 /* Interval between registers                                                */
 340 #define CONFIG_SYS_ATA_STRIDE           4
 341
 342 /*-----------------------------------------------------------------------
 343  * CPLD stuff
 344  */
 345 #define CONFIG_SYS_FPGA_XC95XL          1       /* using Xilinx XC95XL CPLD      */
 346 #define CONFIG_SYS_FPGA_MAX_SIZE        32*1024 /* 32kByte is enough for CPLD    */
 347
 348 /* CPLD program pin configuration */
 349 #define CONFIG_SYS_FPGA_PRG             0x20000000      /* JTAG TMS pin (ppc output)           */
 350 #define CONFIG_SYS_FPGA_CLK             0x10000000      /* JTAG TCK pin (ppc output)           */
 351 #define CONFIG_SYS_FPGA_DATA            0x20000000      /* JTAG TDO->TDI data pin (ppc output) */
 352 #define CONFIG_SYS_FPGA_DONE            0x10000000      /* JTAG TDI->TDO pin (ppc input)       */
 353
 354 #define JTAG_GPIO_ADDR_TMS      (CONFIG_SYS_MBAR + 0xB10)       /* JTAG TMS pin (GPS data out value reg.)      */
 355 #define JTAG_GPIO_ADDR_TCK      (CONFIG_SYS_MBAR + 0xC0C)       /* JTAG TCK pin (GPW data out value reg.)      */
 356 #define JTAG_GPIO_ADDR_TDI      (CONFIG_SYS_MBAR + 0xC0C)       /* JTAG TDO->TDI pin (GPW data out value reg.) */
 357 #define JTAG_GPIO_ADDR_TDO      (CONFIG_SYS_MBAR + 0xB14)       /* JTAG TDI->TDO pin (GPS data in value reg.)  */
 358
 359 #define JTAG_GPIO_ADDR_CFG      (CONFIG_SYS_MBAR + 0xB00)
 360 #define JTAG_GPIO_CFG_SET       0x00000000
 361 #define JTAG_GPIO_CFG_RESET     0x00F00000
 362
 363 #define JTAG_GPIO_ADDR_EN_TMS   (CONFIG_SYS_MBAR + 0xB04)
 364 #define JTAG_GPIO_TMS_EN_SET    0x20000000      /* Enable for GPIO */
 365 #define JTAG_GPIO_TMS_EN_RESET  0x00000000
 366 #define JTAG_GPIO_ADDR_DDR_TMS  (CONFIG_SYS_MBAR + 0xB0C)
 367 #define JTAG_GPIO_TMS_DDR_SET   0x20000000      /* Set as output   */
 368 #define JTAG_GPIO_TMS_DDR_RESET 0x00000000
 369
 370 #define JTAG_GPIO_ADDR_EN_TCK   (CONFIG_SYS_MBAR + 0xC00)
 371 #define JTAG_GPIO_TCK_EN_SET    0x20000000      /* Enable for GPIO */
 372 #define JTAG_GPIO_TCK_EN_RESET  0x00000000
 373 #define JTAG_GPIO_ADDR_DDR_TCK  (CONFIG_SYS_MBAR + 0xC08)
 374 #define JTAG_GPIO_TCK_DDR_SET   0x20000000      /* Set as output   */
 375 #define JTAG_GPIO_TCK_DDR_RESET 0x00000000
 376
 377 #define JTAG_GPIO_ADDR_EN_TDI   (CONFIG_SYS_MBAR + 0xC00)
 378 #define JTAG_GPIO_TDI_EN_SET    0x10000000      /* Enable as GPIO  */
 379 #define JTAG_GPIO_TDI_EN_RESET  0x00000000
 380 #define JTAG_GPIO_ADDR_DDR_TDI  (CONFIG_SYS_MBAR + 0xC08)
 381 #define JTAG_GPIO_TDI_DDR_SET   0x10000000      /* Set as output   */
 382 #define JTAG_GPIO_TDI_DDR_RESET 0x00000000
 383
 384 #define JTAG_GPIO_ADDR_EN_TDO   (CONFIG_SYS_MBAR + 0xB04)
 385 #define JTAG_GPIO_TDO_EN_SET    0x10000000      /* Enable as GPIO  */
 386 #define JTAG_GPIO_TDO_EN_RESET  0x00000000
 387 #define JTAG_GPIO_ADDR_DDR_TDO  (CONFIG_SYS_MBAR + 0xB0C)
 388 #define JTAG_GPIO_TDO_DDR_SET   0x00000000
 389 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000      /* Set as input    */
 390
 391 #endif                          /* __CONFIG_H */