include/configs/cpuat91.h

   1 /*
   2  * CPUAT91 by (C) Copyright 2006-2010 Eric Benard
   3  * eric@eukrea.com
   4  *
   5  * Configuration settings for the CPUAT91 board.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _CONFIG_CPUAT91_H
  11 #define _CONFIG_CPUAT91_H
  12
  13 #include <asm/sizes.h>
  14
  15 #ifdef CONFIG_RAMBOOT
  16 #define CONFIG_SKIP_LOWLEVEL_INIT
  17 #define CONFIG_SYS_TEXT_BASE            0x21F00000
  18 #else
  19 #define CONFIG_BOOTDELAY                1
  20 #define CONFIG_SYS_TEXT_BASE            0
  21 #endif
  22
  23 #define AT91C_XTAL_CLOCK                18432000
  24 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  25 #define AT91C_MAIN_CLOCK                ((AT91C_XTAL_CLOCK / 4) * 39)
  26 #define AT91C_MASTER_CLOCK              (AT91C_MAIN_CLOCK / 3)
  27 #define CONFIG_SYS_HZ_CLOCK             (AT91C_MASTER_CLOCK / 2)
  28
  29 #define CONFIG_ARM920T
  30 #define CONFIG_AT91RM9200
  31 #define CONFIG_CPUAT91
  32 #define USE_920T_MMU
  33
  34 #include <asm/hardware.h>       /* needed for port definitions */
  35
  36 #define CONFIG_CMDLINE_TAG
  37 #define CONFIG_SETUP_MEMORY_TAGS
  38 #define CONFIG_INITRD_TAG
  39 #define CONFIG_BOARD_EARLY_INIT_F
  40
  41 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  42 #define CONFIG_SYS_USE_MAIN_OSCILLATOR
  43 /* flash */
  44 #define CONFIG_SYS_MC_PUIA_VAL  0x00000000
  45 #define CONFIG_SYS_MC_PUP_VAL   0x00000000
  46 #define CONFIG_SYS_MC_PUER_VAL  0x00000000
  47 #define CONFIG_SYS_MC_ASR_VAL   0x00000000
  48 #define CONFIG_SYS_MC_AASR_VAL  0x00000000
  49 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  50 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  51
  52 /* clocks */
  53 #define CONFIG_SYS_PLLAR_VAL    0x20263E04 /* 179.712000 MHz for PCK */
  54 #define CONFIG_SYS_PLLBR_VAL    0x10483E0E /* 48.054857 MHz for USB */
  55 #define CONFIG_SYS_MCKR_VAL     0x00000202 /* PCK/3 = MCK Master Clock */
  56
  57 /* sdram */
  58 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */
  59 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  60 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  61 #define CONFIG_SYS_EBI_CSA_VAL  0x00000002 /* CS1=SDRAM */
  62 #define CONFIG_SYS_SDRC_CR_VAL  0x2188C155 /* set up the SDRAM */
  63 #define CONFIG_SYS_SDRAM        0x20000000 /* address of the SDRAM */
  64 #define CONFIG_SYS_SDRAM1       0x20000080 /* address of the SDRAM */
  65 #define CONFIG_SYS_SDRAM_VAL    0x00000000 /* value written to SDRAM */
  66 #define CONFIG_SYS_SDRC_MR_VAL  0x00000002 /* Precharge All */
  67 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  68 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  69 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  70 #define CONFIG_SYS_SDRC_TR_VAL  0x000002E0 /* Write refresh rate */
  71 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
  72
  73 #define CONFIG_ATMEL_USART
  74 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
  75 #define CONFIG_USART_ID         0/* ignored in arm */
  76
  77 #undef CONFIG_HARD_I2C
  78 #define AT91_PIN_SDA                    (1<<25)
  79 #define AT91_PIN_SCL                    (1<<26)
  80
  81 #define CONFIG_SYS_I2C_INIT_BOARD
  82 #define CONFIG_SYS_I2C_SPEED            50000
  83 #define CONFIG_SYS_I2C_SLAVE            0
  84
  85 #define I2C_INIT        i2c_init_board();
  86 #define I2C_ACTIVE      writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
  87 #define I2C_TRISTATE    writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
  88 #define I2C_READ        ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
  89 #define I2C_SDA(bit)                                            \
  90         if (bit)                                                \
  91                 writel(AT91_PMX_AA_TWD, &pio->pioa.sodr);       \
  92         else                                                    \
  93                 writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
  94 #define I2C_SCL(bit)                                            \
  95         if (bit)                                                \
  96                 writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr);      \
  97         else                                                    \
  98                 writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
  99
 100 #define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SPEED)
 101
 102 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 103 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 104 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     1
 105 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 106
 107 #define CONFIG_BOOTP_BOOTFILESIZE
 108 #define CONFIG_BOOTP_BOOTPATH
 109 #define CONFIG_BOOTP_GATEWAY
 110 #define CONFIG_BOOTP_HOSTNAME
 111
 112 #include <config_cmd_default.h>
 113
 114 #define CONFIG_CMD_PING
 115 #define CONFIG_CMD_MII
 116 #define CONFIG_CMD_CACHE
 117 #undef CONFIG_CMD_USB
 118 #undef CONFIG_CMD_FPGA
 119 #undef CONFIG_CMD_IMI
 120 #undef CONFIG_CMD_LOADS
 121 #undef CONFIG_CMD_NFS
 122 #undef CONFIG_CMD_DHCP
 123
 124 #ifdef CONFIG_SYS_I2C_SOFT
 125 #define CONFIG_CMD_EEPROM
 126 #define CONFIG_CMD_I2C
 127 #endif
 128
 129 #define CONFIG_NR_DRAM_BANKS                    1
 130 #define CONFIG_SYS_SDRAM_BASE                   0x20000000
 131 #define CONFIG_SYS_SDRAM_SIZE                   (32 * 1024 * 1024)
 132
 133 #define CONFIG_SYS_MEMTEST_START                CONFIG_SYS_SDRAM_BASE
 134 #define CONFIG_SYS_MEMTEST_END                  \
 135         (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
 136
 137 #define CONFIG_DRIVER_AT91EMAC
 138 #define CONFIG_SYS_RX_ETH_BUFFER        16
 139 #define CONFIG_RMII
 140 #define CONFIG_MII
 141 #define CONFIG_DRIVER_AT91EMAC_PHYADDR  1
 142 #define CONFIG_NET_RETRY_COUNT                  20
 143 #define CONFIG_KS8721_PHY
 144
 145 #define CONFIG_SYS_FLASH_CFI
 146 #define CONFIG_FLASH_CFI_DRIVER
 147 #define CONFIG_SYS_FLASH_EMPTY_INFO
 148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 149 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 150 #define CONFIG_SYS_FLASH_PROTECTION
 151 #define PHYS_FLASH_1                            0x10000000
 152 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 153 #define CONFIG_SYS_MAX_FLASH_SECT               128
 154 #define CONFIG_SYS_FLASH_CFI_WIDTH              FLASH_CFI_16BIT
 155 #define CONFIG_SYS_MONITOR_BASE                 PHYS_FLASH_1
 156 #define PHYS_FLASH_SIZE                         (16 * 1024 * 1024)
 157 #define CONFIG_SYS_FLASH_BANKS_LIST             \
 158                 { PHYS_FLASH_1 }
 159
 160 #if defined(CONFIG_CMD_USB)
 161 #define CONFIG_USB_ATMEL
 162 #define CONFIG_USB_OHCI_NEW
 163 #define CONFIG_USB_STORAGE
 164 #define CONFIG_DOS_PARTITION
 165 #define CONFIG_AT91C_PQFP_UHPBU
 166 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 167 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 168 #define CONFIG_SYS_USB_OHCI_REGS_BASE           AT91_USB_HOST_BASE
 169 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 170 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 171 #endif
 172
 173 #define CONFIG_ENV_IS_IN_FLASH
 174 #define CONFIG_ENV_ADDR                         (PHYS_FLASH_1 + 128 * 1024)
 175 #define CONFIG_ENV_SIZE                         (128 * 1024)
 176 #define CONFIG_ENV_SECT_SIZE            (128 * 1024)
 177
 178 #define CONFIG_SYS_LOAD_ADDR            0x21000000
 179
 180 #define CONFIG_BAUDRATE                 115200
 181
 182 #define CONFIG_SYS_PROMPT               "CPUAT91=> "
 183 #define CONFIG_SYS_CBSIZE               256
 184 #define CONFIG_SYS_MAXARGS              32
 185 #define CONFIG_SYS_PBSIZE               \
 186         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 187 #define CONFIG_CMDLINE_EDITING
 188
 189 #define CONFIG_SYS_MALLOC_LEN           \
 190                         ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)
 191
 192 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
 193                                 GENERATED_GBL_DATA_SIZE)
 194
 195 #define CONFIG_DEVICE_NULLDEV
 196 #define CONFIG_SILENT_CONSOLE
 197
 198 #define CONFIG_AUTOBOOT_KEYED
 199 #define CONFIG_AUTOBOOT_PROMPT          \
 200         "Press SPACE to abort autoboot\n"
 201 #define CONFIG_AUTOBOOT_STOP_STR        " "
 202 #define CONFIG_AUTOBOOT_DELAY_STR       "d"
 203
 204 #define CONFIG_VERSION_VARIABLE
 205
 206 #define MTDIDS_DEFAULT                  "nor0=physmap-flash.0"
 207 #define MTDPARTS_DEFAULT                \
 208         "mtdparts=physmap-flash.0:"     \
 209                 "128k(u-boot)ro,"       \
 210                 "128k(u-boot-env),"     \
 211                 "1792k(kernel),"        \
 212                 "-(rootfs)"
 213
 214 #define CONFIG_BOOTARGS                 \
 215         "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"
 216
 217 #define CONFIG_BOOTCOMMAND              "run flashboot"
 218
 219 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 220         "mtdid=" MTDIDS_DEFAULT "\0"                                    \
 221         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 222         "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 "  \
 223                 "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 "     \
 224                 "10000000 ${filesize}\0"                                \
 225         "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 "      \
 226                 "1019ffff; erase 10040000 101fffff; cp.b 21000000 "     \
 227                 "10040000 ${filesize}\0"                                \
 228         "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off "        \
 229                 "10200000 10ffffff; erase 10200000 10ffffff; cp.b "     \
 230                 "21000000 10200000 ${filesize}\0"                       \
 231         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"             \
 232         "flashboot=run ramargs;bootm 10040000\0"                        \
 233         "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;"         \
 234                 "bootm 21000000\0"
 235 #endif  /* _CONFIG_CPUAT91_H */