include/configs/csb472.h

   1 /*
   2  * (C) Copyright 2004
   3  * Tolunay Orkun, Nextio Inc., torkun@nextio.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405GP CPU       */
  21 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22 #define CONFIG_CSB472           1       /* on a Cogent CSB472 board     */
  23 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f()    */
  24 #define CONFIG_LAST_STAGE_INIT  1       /* Call last_stage_init()       */
  25 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  26
  27 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  28
  29 /*
  30  * OS Bootstrap configuration
  31  *
  32  */
  33
  34 #if 0
  35 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled */
  36 #else
  37 #define CONFIG_BOOTDELAY        3       /* autoboot after X seconds     */
  38 #endif
  39
  40 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check keypress when bootdelay = 0 */
  41
  42 #if 1
  43 #undef  CONFIG_BOOTARGS
  44 #define CONFIG_BOOTCOMMAND \
  45         "setenv bootargs console=ttyS0,38400 debug " \
  46         "root=/dev/ram rw ramdisk_size=4096 " \
  47         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  48         "bootm ff800000 ff900000"
  49 #endif
  50
  51 #if 0
  52 #undef  CONFIG_BOOTARGS
  53 #define CONFIG_BOOTCOMMAND \
  54         "bootp; " \
  55         "setenv bootargs console=ttyS0,38400 debug " \
  56         "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  57         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  58         "bootm"
  59 #endif
  60
  61 /*
  62  * BOOTP options
  63  */
  64 #define CONFIG_BOOTP_SUBNETMASK
  65 #define CONFIG_BOOTP_GATEWAY
  66 #define CONFIG_BOOTP_HOSTNAME
  67 #define CONFIG_BOOTP_BOOTPATH
  68 #define CONFIG_BOOTP_BOOTFILESIZE
  69 #define CONFIG_BOOTP_DNS2
  70
  71
  72 /*
  73  * Command line configuration.
  74  */
  75 #include <config_cmd_default.h>
  76
  77 #define CONFIG_CMD_ASKENV
  78 #define CONFIG_CMD_BEDBUG
  79 #define CONFIG_CMD_ELF
  80 #define CONFIG_CMD_IRQ
  81 #define CONFIG_CMD_I2C
  82 #define CONFIG_CMD_PCI
  83 #define CONFIG_CMD_DATE
  84 #define CONFIG_CMD_MII
  85 #define CONFIG_CMD_PING
  86 #define CONFIG_CMD_DHCP
  87
  88 /*
  89  * Serial download configuration
  90  *
  91  */
  92 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  93 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  94
  95 /*
  96  * KGDB Configuration
  97  *
  98  */
  99 #if defined(CONFIG_CMD_KGDB)
 100 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 101 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 102 #endif
 103
 104 /*
 105  * Miscellaneous configurable options
 106  *
 107  */
 108 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser */
 109
 110 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 111 #if defined(CONFIG_CMD_KGDB)
 112 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 113 #else
 114 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 115 #endif
 116 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 117 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 118 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 119
 120 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on */
 121 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM */
 122
 123 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_info (bd_t) */
 124 #define CONFIG_SYS_LOAD_ADDR            0x100000 /* default load address */
 125
 126 /*
 127  * For booting Linux, the board info and command line data
 128  * have to be in the first 8 MB of memory, since this is
 129  * the maximum mapped by the Linux kernel during initialization.
 130  */
 131 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 132
 133 /*
 134  * watchdog configuration
 135  *
 136  */
 137 #undef  CONFIG_WATCHDOG                 /* watchdog disabled */
 138
 139 /*
 140  * UART configuration
 141  *
 142  */
 143 #define CONFIG_CONS_INDEX               1       /* Use UART0            */
 144 #define CONFIG_SYS_NS16550
 145 #define CONFIG_SYS_NS16550_SERIAL
 146 #define CONFIG_SYS_NS16550_REG_SIZE     1
 147 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 148
 149 #undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* use internal serial clock */
 150 #define CONFIG_SYS_BASE_BAUD            691200
 151 #define CONFIG_BAUDRATE         38400   /* Default baud rate */
 152 #define CONFIG_SYS_BAUDRATE_TABLE      \
 153     { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
 154
 155 /*
 156  * I2C configuration
 157  *
 158  */
 159 #define CONFIG_SYS_I2C
 160 #define CONFIG_SYS_I2C_PPC4XX
 161 #define CONFIG_SYS_I2C_PPC4XX_CH0
 162 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 163 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F    /* I2C slave address */
 164
 165 /*
 166  * MII PHY configuration
 167  *
 168  */
 169 #define CONFIG_PPC4xx_EMAC
 170 #define CONFIG_MII              1       /* MII PHY management           */
 171 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
 172 #define CONFIG_PHY_CMD_DELAY    40      /* PHY COMMAND delay            */
 173                                         /* 32usec min. for LXT971A      */
 174 #define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
 175
 176 /*
 177  * RTC configuration
 178  *
 179  * Note that DS1307 RTC is limited to 100Khz I2C bus.
 180  *
 181  */
 182 #define CONFIG_RTC_DS1307               /* Use Dallas 1307 RTC          */
 183
 184 /*
 185  * PCI stuff
 186  *
 187  */
 188 #define CONFIG_PCI                      /* include pci support          */
 189 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 190 #define PCI_HOST_ADAPTER        0       /* configure ar pci adapter     */
 191 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 192 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 193
 194 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 195 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 196                                         /* resource configuration       */
 197 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 198 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 199
 200 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 201 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 202 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 203 #define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 204 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 205 #define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
 206 #define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
 207 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 208
 209 /*
 210  * IDE stuff
 211  *
 212  */
 213 #undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
 214 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 215 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 216
 217 /*
 218  * Environment configuration
 219  *
 220  */
 221 #define CONFIG_ENV_IS_IN_FLASH  1       /* environment is in FLASH      */
 222 #undef CONFIG_ENV_IS_IN_NVRAM
 223 #undef CONFIG_ENV_IS_IN_EEPROM
 224
 225 /*
 226  * General Memory organization
 227  *
 228  * Start addresses for the final memory configuration
 229  * (Set up by the startup code)
 230  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 231  */
 232 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 233 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 234 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 235 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 236 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 KB for Monitor */
 237 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* Reserve 128 KB for malloc() */
 238
 239 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
 240 #define CONFIG_SYS_RAMSTART
 241 #endif
 242
 243 #if defined(CONFIG_ENV_IS_IN_FLASH)
 244 #define CONFIG_ENV_IN_OWN_SECTOR        1          /* Give Environment own sector */
 245 #define CONFIG_ENV_ADDR         0xFFF00000 /* Address of Environment Sector */
 246 #define CONFIG_ENV_SIZE         0x00001000 /* Size of Environment */
 247 #define CONFIG_ENV_SECT_SIZE    0x00040000 /* Size of Environment Sector */
 248 #endif
 249
 250 /*
 251  * FLASH Device configuration
 252  *
 253  */
 254 #define CONFIG_SYS_FLASH_CFI            1       /* flash is CFI conformant      */
 255 #define CONFIG_FLASH_CFI_DRIVER 1       /* use common cfi driver        */
 256 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 257 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max # of memory banks        */
 258 #define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank       */
 259 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* max # of sectors on one chip */
 260 #define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection    */
 261 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 262
 263 /*
 264  * On Chip Memory location/size
 265  *
 266  */
 267 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 268 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 269
 270 /*
 271  * Global info and initial stack
 272  *
 273  */
 274 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
 275 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
 276 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 277 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 278
 279 /*
 280  * Miscellaneous board specific definitions
 281  *
 282  */
 283 #define CONFIG_I2CFAST          1       /* enable "i2cfast" env. setting     */
 284
 285 #endif  /* __CONFIG_H */