include/configs/davinci_sonata.h

   1 /*
   2  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * Define this to make U-Boot skip low level initialization when loaded
  12  * by initial bootloader. Not required by NAND U-Boot version but IS
  13  * required for a NOR version used to burn the real NOR U-Boot into
  14  * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
  15  * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
  16  * NOR U-Boot is loaded directly from Flash so it must perform all the
  17  * low level initialization itself. NAND version is loaded by an initial
  18  * bootloader (UBL in TI-ese) that performs such an initialization so it's
  19  * skipped in NAND version. The third DaVinci boot mode loads a bootloader
  20  * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
  21  * performing low level init prior to loading. All that means we can NOT use
  22  * NAND version to put U-Boot into NOR because it doesn't have NOR support and
  23  * we can NOT use NOR version because it performs low level initialization
  24  * effectively destroying itself in DDR memory. That's why a separate NOR
  25  * version with this define is needed. It is loaded via UART, then one uses
  26  * it to somehow download a proper NOR version built WITHOUT this define to
  27  * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
  28  * NOR support into the initial bootloader so it won't be needed but DaVinci
  29  * static RAM might be too small for this (I have something like 2Kbytes left
  30  * as of now, without NOR support) so this might've not happened...
  31  *
  32 #define CONFIG_NOR_UART_BOOT
  33  */
  34
  35 /*=======*/
  36 /* Board */
  37 /*=======*/
  38 #define SONATA_BOARD
  39 #define CONFIG_SYS_NAND_SMALLPAGE
  40 #define CONFIG_SYS_USE_NOR
  41 #define MACH_TYPE_SONATA 1254
  42 #define CONFIG_MACH_TYPE MACH_TYPE_SONATA
  43 /*===================*/
  44 /* SoC Configuration */
  45 /*===================*/
  46 #define CONFIG_ARM926EJS                        /* arm926ejs CPU core */
  47 #define CONFIG_SYS_TIMERBASE            0x01c21400      /* use timer 0 */
  48 #define CONFIG_SYS_HZ_CLOCK             27000000        /* Timer Input clock freq */
  49 #define CONFIG_SOC_DM644X
  50 /*====================================================*/
  51 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
  52 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
  53 /*====================================================*/
  54 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
  55 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
  56 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
  57 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
  58 /*=============*/
  59 /* Memory Info */
  60 /*=============*/
  61 #define CONFIG_SYS_MALLOC_LEN           (0x10000 + 128*1024)    /* malloc() len */
  62 #define CONFIG_SYS_MEMTEST_START        0x80000000      /* memtest start address */
  63 #define CONFIG_SYS_MEMTEST_END          0x81000000      /* 16MB RAM test */
  64 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
  65 #define PHYS_SDRAM_1            0x80000000      /* DDR Start */
  66 #define PHYS_SDRAM_1_SIZE       0x08000000      /* DDR size 128MB */
  67 #define DDR_4BANKS                              /* 4-bank DDR2 (128MB) */
  68 /*====================*/
  69 /* Serial Driver info */
  70 /*====================*/
  71 #define CONFIG_SYS_NS16550
  72 #define CONFIG_SYS_NS16550_SERIAL
  73 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size, byteorder */
  74 #define CONFIG_SYS_NS16550_COM1 0x01c20000      /* Base address of UART0 */
  75 #define CONFIG_SYS_NS16550_CLK  CONFIG_SYS_HZ_CLOCK     /* Input clock to NS16550 */
  76 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
  77 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
  78 /*===================*/
  79 /* I2C Configuration */
  80 /*===================*/
  81 #define CONFIG_HARD_I2C
  82 #define CONFIG_DRIVER_DAVINCI_I2C
  83 #define CONFIG_SYS_I2C_SPEED            80000   /* 100Kbps won't work, silicon bug */
  84 #define CONFIG_SYS_I2C_SLAVE            10      /* Bogus, master-only in U-Boot */
  85 /*==================================*/
  86 /* Network & Ethernet Configuration */
  87 /*==================================*/
  88 #define CONFIG_DRIVER_TI_EMAC
  89 #define CONFIG_MII
  90 #define CONFIG_BOOTP_DNS
  91 #define CONFIG_BOOTP_DNS2
  92 #define CONFIG_BOOTP_SEND_HOSTNAME
  93 #define CONFIG_NET_RETRY_COUNT  10
  94 /*=====================*/
  95 /* Flash & Environment */
  96 /*=====================*/
  97 #ifdef CONFIG_SYS_USE_NAND
  98 #define CONFIG_NAND_DAVINCI
  99 #define CONFIG_SYS_NAND_CS              2
 100 #undef CONFIG_ENV_IS_IN_FLASH
 101 #define CONFIG_SYS_NO_FLASH
 102 #define CONFIG_ENV_OVERWRITE            /* instead if obsoleted forceenv() */
 103 #define CONFIG_ENV_IS_IN_NAND           /* U-Boot env in NAND Flash  */
 104 #define CONFIG_ENV_SECT_SIZE    512     /* Env sector Size */
 105 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
 106 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is loaded by a bootloader */
 107 #define CONFIG_SYS_NAND_BASE            0x02000000
 108 #define CONFIG_SYS_NAND_HW_ECC
 109 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices */
 110 #define CONFIG_ENV_OFFSET               0x0     /* Block 0--not used by bootcode */
 111 #elif defined(CONFIG_SYS_USE_NOR)
 112 #ifdef CONFIG_NOR_UART_BOOT
 113 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is loaded by a bootloader */
 114 #else
 115 #undef CONFIG_SKIP_LOWLEVEL_INIT
 116 #endif
 117 #define CONFIG_ENV_IS_IN_FLASH
 118 #undef CONFIG_SYS_NO_FLASH
 119 #define CONFIG_FLASH_CFI_DRIVER
 120 #define CONFIG_SYS_FLASH_CFI
 121 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* max number of flash banks */
 122 #define CONFIG_SYS_FLASH_SECT_SZ        0x20000         /* 128KB sect size AMD Flash */
 123 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ*2)
 124 #define CONFIG_ENV_SIZE         CONFIG_SYS_FLASH_SECT_SZ
 125 #define PHYS_FLASH_1            0x02000000      /* CS2 Base address      */
 126 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1    /* Flash Base for U-Boot */
 127 #define PHYS_FLASH_SIZE         0x2000000       /* Flash size 32MB       */
 128 #define CONFIG_SYS_MAX_FLASH_SECT       (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
 129 #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_FLASH_SECT_SZ        /* Env sector Size */
 130 #endif
 131 /*==============================*/
 132 /* U-Boot general configuration */
 133 /*==============================*/
 134 #define CONFIG_MISC_INIT_R
 135 #undef CONFIG_BOOTDELAY
 136 #define CONFIG_BOOTFILE         "uImage"        /* Boot file name */
 137 #define CONFIG_SYS_PROMPT               "U-Boot > "     /* Monitor Command Prompt */
 138 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size  */
 139 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print buffer sz */
 140 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 141 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 142 #define CONFIG_SYS_LOAD_ADDR            0x80700000      /* default Linux kernel load address */
 143 #define CONFIG_VERSION_VARIABLE
 144 #define CONFIG_AUTO_COMPLETE            /* Won't work with hush so far, may be later */
 145 #define CONFIG_SYS_HUSH_PARSER
 146 #define CONFIG_CMDLINE_EDITING
 147 #define CONFIG_SYS_LONGHELP
 148 #define CONFIG_CRC32_VERIFY
 149 #define CONFIG_MX_CYCLIC
 150 /*===================*/
 151 /* Linux Information */
 152 /*===================*/
 153 #define LINUX_BOOT_PARAM_ADDR   0x80000100
 154 #define CONFIG_CMDLINE_TAG
 155 #define CONFIG_SETUP_MEMORY_TAGS
 156 #define CONFIG_BOOTARGS         "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
 157 #define CONFIG_BOOTCOMMAND      "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
 158 /*=================*/
 159 /* U-Boot commands */
 160 /*=================*/
 161 #include <config_cmd_default.h>
 162 #define CONFIG_CMD_ASKENV
 163 #define CONFIG_CMD_DHCP
 164 #define CONFIG_CMD_DIAG
 165 #define CONFIG_CMD_I2C
 166 #define CONFIG_CMD_MII
 167 #define CONFIG_CMD_PING
 168 #define CONFIG_CMD_SAVES
 169 #define CONFIG_CMD_EEPROM
 170 #undef CONFIG_CMD_BDI
 171 #undef CONFIG_CMD_FPGA
 172 #undef CONFIG_CMD_SETGETDCR
 173 #ifdef CONFIG_SYS_USE_NAND
 174 #undef CONFIG_CMD_FLASH
 175 #undef CONFIG_CMD_IMLS
 176 #define CONFIG_CMD_NAND
 177 #elif defined(CONFIG_SYS_USE_NOR)
 178 #define CONFIG_CMD_JFFS2
 179 #else
 180 #error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
 181 #endif
 182
 183 #ifdef CONFIG_CMD_BDI
 184 #define CONFIG_CLOCKS
 185 #endif
 186
 187 #define CONFIG_MAX_RAM_BANK_SIZE        (256 << 20)     /* 256 MB */
 188
 189 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 190 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 191 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + \
 192                                          CONFIG_SYS_INIT_RAM_SIZE - \
 193                                          GENERATED_GBL_DATA_SIZE)
 194
 195 #endif /* __CONFIG_H */