include/configs/ep8248.h

   1 /*
   2  * Copyright (C) 2004 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * U-Boot configuration for Embedded Planet EP8248 boards.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_MPC8248
  14 #define CPU_ID_STR              "MPC8248"
  15
  16 #define CONFIG_EP8248                   /* Embedded Planet EP8248 board */
  17
  18 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  19
  20 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  21
  22 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  23 #define CONFIG_ENV_OVERWRITE
  24
  25 /*
  26  * Select serial console configuration
  27  *
  28  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  29  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  30  * for SCC).
  31  */
  32 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  33 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  34 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  35 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  36
  37 #define CONFIG_SYS_BCSR         0xFA000000
  38
  39 /* Pass open firmware flat device tree */
  40 #define CONFIG_OF_LIBFDT        1
  41 #define CONFIG_OF_BOARD_SETUP   1
  42
  43 #define OF_TBCLK        (bd->bi_busfreq / 4)
  44 #define OF_STDOUT_PATH  "/soc/cpm/serial <at> 11a80"
  45
  46 /* Select ethernet configuration */
  47 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  48 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  49 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  50
  51 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  52 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  53
  54 #define CONFIG_HAS_ETH0
  55 #define CONFIG_ETHER_ON_FCC1            1
  56 /* - Rx clock is CLK10
  57  * - Tx clock is CLK11
  58  * - BDs/buffers on 60x bus
  59  * - Full duplex
  60  */
  61 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  62 #define CONFIG_SYS_CMXFCR_VALUE1        (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
  63
  64 #define CONFIG_HAS_ETH1
  65 #define CONFIG_ETHER_ON_FCC2            1
  66 /* - Rx clock is CLK13
  67  * - Tx clock is CLK14
  68  * - BDs/buffers on 60x bus
  69  * - Full duplex
  70  */
  71 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  72 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  73
  74 #define CONFIG_MII                      /* MII PHY management        */
  75 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
  76 /*
  77  * GPIO pins used for bit-banged MII communications
  78  */
  79 #define MDIO_PORT               0       /* Not used - implemented in BCSR */
  80
  81 #define MDIO_ACTIVE             (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
  82 #define MDIO_TRISTATE           (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
  83 #define MDIO_READ               (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
  84
  85 #define MDIO(bit)               if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
  86                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
  87
  88 #define MDC(bit)                if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
  89                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
  90
  91 #define MIIDELAY                udelay(1)
  92
  93 #ifndef CONFIG_8260_CLKIN
  94 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
  95 #endif
  96
  97 #define CONFIG_BAUDRATE         38400
  98
  99
 100 /*
 101  * BOOTP options
 102  */
 103 #define CONFIG_BOOTP_BOOTFILESIZE
 104 #define CONFIG_BOOTP_BOOTPATH
 105 #define CONFIG_BOOTP_GATEWAY
 106 #define CONFIG_BOOTP_HOSTNAME
 107
 108
 109 /*
 110  * Command line configuration.
 111  */
 112 #include <config_cmd_default.h>
 113
 114 #define CONFIG_CMD_DHCP
 115 #define CONFIG_CMD_ECHO
 116 #define CONFIG_CMD_I2C
 117 #define CONFIG_CMD_IMMAP
 118 #define CONFIG_CMD_MII
 119 #define CONFIG_CMD_PING
 120
 121
 122 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 123 #define CONFIG_BOOTCOMMAND      "bootm FF860000"        /* autoboot command */
 124 #define CONFIG_BOOTARGS         "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
 125
 126 #if defined(CONFIG_CMD_KGDB)
 127 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 128 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 129 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 130 #define CONFIG_KGDB_INDEX       1       /* which serial channel for kgdb */
 131 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 132 #endif
 133
 134 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 135 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 136
 137 /*
 138  * Miscellaneous configurable options
 139  */
 140 #define CONFIG_SYS_HUSH_PARSER
 141 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 142 #if defined(CONFIG_CMD_KGDB)
 143 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 144 #else
 145 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 146 #endif
 147 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 148 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 149 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 150
 151 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 152 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 153
 154 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 155
 156 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 157
 158 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 159 #define CONFIG_SYS_FLASH_CFI
 160 #define CONFIG_FLASH_CFI_DRIVER
 161 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 162 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 163
 164 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 165
 166 #if defined(CONFIG_CMD_JFFS2)
 167 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 168 #define CONFIG_SYS_JFFS2_NUM_BANKS      CONFIG_SYS_MAX_FLASH_BANKS
 169 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
 170 #define CONFIG_SYS_JFFS2_LAST_SECTOR   62
 171 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 172 #define CONFIG_SYS_JFFS_CUSTOM_PART
 173 #endif
 174
 175 #if defined(CONFIG_CMD_I2C)
 176 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 177 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed                    */
 178 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* I2C slave address            */
 179 #endif
 180
 181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 182 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 183 #define CONFIG_SYS_RAMBOOT
 184 #endif
 185
 186 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256KB for Monitor */
 187
 188 #define CONFIG_ENV_IS_IN_FLASH
 189
 190 #ifdef CONFIG_ENV_IS_IN_FLASH
 191 #define CONFIG_ENV_SECT_SIZE    0x20000
 192 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 193 #endif /* CONFIG_ENV_IS_IN_FLASH */
 194
 195 #define CONFIG_SYS_DEFAULT_IMMR 0x00010000
 196
 197 #define CONFIG_SYS_IMMR         0xF0000000
 198
 199 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 200 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM   */
 201 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 202 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 203
 204 /* Hard reset configuration word */
 205 #define CONFIG_SYS_HRCW_MASTER          0x0C40025A /* Not used - provided by FPGA */
 206 /* No slaves */
 207 #define CONFIG_SYS_HRCW_SLAVE1          0
 208 #define CONFIG_SYS_HRCW_SLAVE2          0
 209 #define CONFIG_SYS_HRCW_SLAVE3          0
 210 #define CONFIG_SYS_HRCW_SLAVE4          0
 211 #define CONFIG_SYS_HRCW_SLAVE5          0
 212 #define CONFIG_SYS_HRCW_SLAVE6          0
 213 #define CONFIG_SYS_HRCW_SLAVE7          0
 214
 215 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 216 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 217
 218 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 219 #if defined(CONFIG_CMD_KGDB)
 220 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 221 #endif
 222
 223 #define CONFIG_SYS_HID0_INIT            0
 224 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 225
 226 #define CONFIG_SYS_HID2         0
 227
 228 #define CONFIG_SYS_SIUMCR               0x01240200
 229 #define CONFIG_SYS_SYPCR                0xFFFF0683
 230 #define CONFIG_SYS_BCR                  0x00000000
 231 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 232
 233 #define CONFIG_SYS_RMR                  RMR_CSRE
 234 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 235 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 236 #define CONFIG_SYS_RCCR         0
 237
 238 #define CONFIG_SYS_MPTPR                0x1300
 239 #define CONFIG_SYS_PSDMR                0x82672522
 240 #define CONFIG_SYS_PSRT         0x4B
 241
 242 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 243 #define CONFIG_SYS_SDRAM_BR             (CONFIG_SYS_SDRAM_BASE | 0x00001841)
 244 #define CONFIG_SYS_SDRAM_OR             0xFF0030C0
 245
 246 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001801)
 247 #define CONFIG_SYS_OR0_PRELIM           0xFF8008C2
 248 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_BCSR | 0x00000801)
 249 #define CONFIG_SYS_OR2_PRELIM           0xFFF00864
 250
 251 #define CONFIG_SYS_RESET_ADDRESS        0xC0000000
 252
 253 #endif /* __CONFIG_H */