include/configs/ls1043a_common.h

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043A_COMMON_H
   8 #define __LS1043A_COMMON_H
   9
  10 /* SPL build */
  11 #ifdef CONFIG_SPL_BUILD
  12 #define SPL_NO_FMAN
  13 #define SPL_NO_DSPI
  14 #define SPL_NO_PCIE
  15 #define SPL_NO_ENV
  16 #define SPL_NO_MISC
  17 #define SPL_NO_USB
  18 #define SPL_NO_SATA
  19 #define SPL_NO_QE
  20 #define SPL_NO_EEPROM
  21 #endif
  22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
  23 #define SPL_NO_MMC
  24 #endif
  25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
  26 #define SPL_NO_IFC
  27 #endif
  28
  29 #define CONFIG_REMAKE_ELF
  30 #define CONFIG_FSL_LAYERSCAPE
  31 #define CONFIG_LS1043A
  32 #define CONFIG_MP
  33 #define CONFIG_GICV2
  34
  35 #include <asm/arch/stream_id_lsch2.h>
  36 #include <asm/arch/config.h>
  37
  38 /* Link Definitions */
  39 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  40
  41 #define CONFIG_SUPPORT_RAW_INITRD
  42
  43 #define CONFIG_SKIP_LOWLEVEL_INIT
  44
  45 #define CONFIG_VERY_BIG_RAM
  46 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  47 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  48 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  49 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  50
  51 #define CPU_RELEASE_ADDR               secondary_boot_func
  52
  53 /* Generic Timer Definitions */
  54 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  55
  56 /* Size of malloc() pool */
  57 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  58
  59 /* Serial Port */
  60 #define CONFIG_CONS_INDEX               1
  61 #define CONFIG_SYS_NS16550_SERIAL
  62 #define CONFIG_SYS_NS16550_REG_SIZE     1
  63 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
  64
  65 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  66
  67 /* SD boot SPL */
  68 #ifdef CONFIG_SD_BOOT
  69 #define CONFIG_SPL_FRAMEWORK
  70 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  71 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  72
  73 #define CONFIG_SPL_TEXT_BASE            0x10000000
  74 #define CONFIG_SPL_MAX_SIZE             0x17000
  75 #define CONFIG_SPL_STACK                0x1001e000
  76 #define CONFIG_SPL_PAD_TO               0x1d000
  77
  78 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  79                                         CONFIG_SYS_MONITOR_LEN)
  80 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  81 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  82 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  83
  84 #ifdef CONFIG_SECURE_BOOT
  85 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  86 /*
  87  * HDR would be appended at end of image and copied to DDR along
  88  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  89  * size increases then increase this size in case of secure boot as
  90  * it uses raw u-boot image instead of fit image.
  91  */
  92 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  93 #else
  94 #define CONFIG_SYS_MONITOR_LEN          0x100000
  95 #endif /* ifdef CONFIG_SECURE_BOOT */
  96 #endif
  97
  98 /* NAND SPL */
  99 #ifdef CONFIG_NAND_BOOT
 100 #define CONFIG_SPL_PBL_PAD
 101 #define CONFIG_SPL_FRAMEWORK
 102 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
 103 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 104 #define CONFIG_SPL_TEXT_BASE            0x10000000
 105 #define CONFIG_SPL_MAX_SIZE             0x1a000
 106 #define CONFIG_SPL_STACK                0x1001d000
 107 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 108 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 109 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 110 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 111 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 112 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 113
 114 #ifdef CONFIG_SECURE_BOOT
 115 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
 116 #endif /* ifdef CONFIG_SECURE_BOOT */
 117
 118 #ifdef CONFIG_U_BOOT_HDR_SIZE
 119 /*
 120  * HDR would be appended at end of image and copied to DDR along
 121  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 122  * size increases then increase this size in case of secure boot as
 123  * it uses raw u-boot image instead of fit image.
 124  */
 125 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 126 #else
 127 #define CONFIG_SYS_MONITOR_LEN          0x100000
 128 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 129
 130 #endif
 131
 132 /* IFC */
 133 #ifndef SPL_NO_IFC
 134 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 135 #define CONFIG_FSL_IFC
 136 /*
 137  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 138  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 139  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 140  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 141  */
 142 #define CONFIG_SYS_FLASH_BASE                   0x60000000
 143 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 144 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 145
 146 #ifdef CONFIG_MTD_NOR_FLASH
 147 #define CONFIG_FLASH_CFI_DRIVER
 148 #define CONFIG_SYS_FLASH_CFI
 149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 150 #define CONFIG_SYS_FLASH_QUIET_TEST
 151 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 152 #endif
 153 #endif
 154 #endif
 155
 156 /* I2C */
 157 #define CONFIG_SYS_I2C
 158 #define CONFIG_SYS_I2C_MXC
 159 #define CONFIG_SYS_I2C_MXC_I2C1
 160 #define CONFIG_SYS_I2C_MXC_I2C2
 161 #define CONFIG_SYS_I2C_MXC_I2C3
 162 #define CONFIG_SYS_I2C_MXC_I2C4
 163
 164 /* PCIe */
 165 #ifndef SPL_NO_PCIE
 166 #define CONFIG_PCIE1            /* PCIE controller 1 */
 167 #define CONFIG_PCIE2            /* PCIE controller 2 */
 168 #define CONFIG_PCIE3            /* PCIE controller 3 */
 169
 170 #ifdef CONFIG_PCI
 171 #define CONFIG_NET_MULTI
 172 #define CONFIG_PCI_SCAN_SHOW
 173 #define CONFIG_CMD_PCI
 174 #endif
 175 #endif
 176
 177 /* Command line configuration */
 178 #ifndef SPL_NO_ENV
 179 #define CONFIG_CMD_ENV
 180 #endif
 181
 182 /*  MMC  */
 183 #ifndef SPL_NO_MMC
 184 #ifdef CONFIG_MMC
 185 #define CONFIG_FSL_ESDHC
 186 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 187 #endif
 188 #endif
 189
 190 /*  DSPI  */
 191 #ifndef SPL_NO_DSPI
 192 #define CONFIG_FSL_DSPI
 193 #ifdef CONFIG_FSL_DSPI
 194 #define CONFIG_DM_SPI_FLASH
 195 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
 196 #define CONFIG_SPI_FLASH_SST            /* cs1 */
 197 #define CONFIG_SPI_FLASH_EON            /* cs2 */
 198 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 199 #define CONFIG_SF_DEFAULT_BUS           1
 200 #define CONFIG_SF_DEFAULT_CS            0
 201 #endif
 202 #endif
 203 #endif
 204
 205 /* FMan ucode */
 206 #ifndef SPL_NO_FMAN
 207 #define CONFIG_SYS_DPAA_FMAN
 208 #ifdef CONFIG_SYS_DPAA_FMAN
 209 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 210
 211 #ifdef CONFIG_NAND_BOOT
 212 /* Store Fman ucode at offeset 0x160000(11 blocks). */
 213 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 214 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 215 #elif defined(CONFIG_SD_BOOT)
 216 /*
 217  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 218  * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 219  * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
 220  */
 221 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 222 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 223 #elif defined(CONFIG_QSPI_BOOT)
 224 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 225 #define CONFIG_SYS_FMAN_FW_ADDR         0x400d0000
 226 #define CONFIG_ENV_SPI_BUS              0
 227 #define CONFIG_ENV_SPI_CS               0
 228 #define CONFIG_ENV_SPI_MAX_HZ           1000000
 229 #define CONFIG_ENV_SPI_MODE             0x03
 230 #else
 231 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 232 /* FMan fireware Pre-load address */
 233 #define CONFIG_SYS_FMAN_FW_ADDR         0x60300000
 234 #endif
 235 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 236 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 237 #endif
 238 #endif
 239
 240 /* Miscellaneous configurable options */
 241 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 242
 243 #define CONFIG_HWCONFIG
 244 #define HWCONFIG_BUFFER_SIZE            128
 245
 246 #ifndef SPL_NO_MISC
 247 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 248 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
 249                         "5m(kernel),1m(dtb),9m(file_system)"
 250 #else
 251 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
 252                         "2m@0x100000(nor_bank0_uboot),"\
 253                         "40m@0x1100000(nor_bank0_fit)," \
 254                         "7m(nor_bank0_user)," \
 255                         "2m@0x4100000(nor_bank4_uboot)," \
 256                         "40m@0x5100000(nor_bank4_fit),"\
 257                         "-(nor_bank4_user);" \
 258                         "7e800000.flash:" \
 259                         "1m(nand_uboot),1m(nand_uboot_env)," \
 260                         "20m(nand_fit);spi0.0:1m(uboot)," \
 261                         "5m(kernel),1m(dtb),9m(file_system)"
 262 #endif
 263
 264 /* Initial environment variables */
 265 #define CONFIG_EXTRA_ENV_SETTINGS               \
 266         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 267         "loadaddr=0x80100000\0"                 \
 268         "fdt_high=0xffffffffffffffff\0"         \
 269         "initrd_high=0xffffffffffffffff\0"      \
 270         "kernel_start=0x61100000\0"             \
 271         "kernel_load=0xa0000000\0"              \
 272         "kernel_size=0x2800000\0"               \
 273         "console=ttyS0,115200\0"                \
 274         "mtdparts=" MTDPARTS_DEFAULT "\0"
 275
 276 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 root=/dev/ram0 " \
 277                                         "earlycon=uart8250,mmio,0x21c0500 "    \
 278                                         MTDPARTS_DEFAULT
 279
 280 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 281 #define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
 282                                         "e0000 f00000 && bootm $kernel_load"
 283 #else
 284 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 285                                         "$kernel_size && bootm $kernel_load"
 286 #endif
 287 #endif
 288
 289 /* Monitor Command Prompt */
 290 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 291 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 292                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 293 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 294 #define CONFIG_SYS_LONGHELP
 295
 296 #ifndef SPL_NO_MISC
 297 #define CONFIG_CMDLINE_EDITING          1
 298 #endif
 299
 300 #define CONFIG_AUTO_COMPLETE
 301 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 302
 303 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 304
 305 /* Hash command with SHA acceleration supported in hardware */
 306 #ifdef CONFIG_FSL_CAAM
 307 #define CONFIG_CMD_HASH
 308 #define CONFIG_SHA_HW_ACCEL
 309 #endif
 310
 311 #endif /* __LS1043A_COMMON_H */