include/configs/lwmon5.h

   1 /*
   2  * (C) Copyright 2007-2013
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * lwmon5.h - configuration for lwmon5 board
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * Liebherr extra version info
  16  */
  17 #define CONFIG_IDENT_STRING     " - v2.0"
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22 #define CONFIG_LWMON5           1               /* Board is lwmon5      */
  23 #define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  24 #define CONFIG_440              1               /* ... PPC440 family    */
  25 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  26
  27 #ifdef CONFIG_LCD4_LWMON5
  28 #define CONFIG_SYS_TEXT_BASE    0x01000000 /* SPL U-Boot TEXT_BASE */
  29 #define CONFIG_HOSTNAME         lcd4_lwmon5
  30 #else
  31 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  32 #define CONFIG_HOSTNAME         lwmon5
  33 #endif
  34
  35 #define CONFIG_SYS_CLK_FREQ     33300000        /* external freq to pll */
  36
  37 #define CONFIG_4xx_DCACHE               /* enable cache in SDRAM        */
  38
  39 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_early_init_f      */
  40 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_early_init_r      */
  41 #define CONFIG_BOARD_POSTCLK_INIT       /* Call board_postclk_init      */
  42 #define CONFIG_MISC_INIT_R              /* Call misc_init_r             */
  43 #define CONFIG_BOARD_RESET              /* Call board_reset             */
  44
  45 /*
  46  * Base addresses -- Note these are effective addresses where the
  47  * actual resources get mapped (not physical addresses)
  48  */
  49 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of U-Boot      */
  50 #define CONFIG_SYS_MONITOR_LEN          0x80000
  51 #define CONFIG_SYS_MALLOC_LEN           (1 << 20)       /* Reserved for malloc  */
  52
  53 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  54 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  55 #define CONFIG_SYS_FLASH_BASE           0xf8000000      /* start of FLASH       */
  56 #define CONFIG_SYS_LIME_BASE_0          0xc0000000
  57 #define CONFIG_SYS_LIME_BASE_1          0xc1000000
  58 #define CONFIG_SYS_LIME_BASE_2          0xc2000000
  59 #define CONFIG_SYS_LIME_BASE_3          0xc3000000
  60 #define CONFIG_SYS_FPGA_BASE_0          0xc4000000
  61 #define CONFIG_SYS_FPGA_BASE_1          0xc4200000
  62 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  63 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  64 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  65 #define CONFIG_SYS_PCI_MEMBASE1         (CONFIG_SYS_PCI_MEMBASE  + 0x10000000)
  66 #define CONFIG_SYS_PCI_MEMBASE2         (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
  67 #define CONFIG_SYS_PCI_MEMBASE3         (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
  68
  69 #ifndef CONFIG_LCD4_LWMON5
  70 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  71 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  72 #define CONFIG_SYS_USB_HOST             0xe0000400
  73 #endif
  74
  75 /*
  76  * Initial RAM & stack pointer
  77  *
  78  * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
  79  * the POST_WORD from OCM to a 440EPx register that preserves it's
  80  * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
  81  * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
  82  */
  83 #ifndef CONFIG_LCD4_LWMON5
  84 #define CONFIG_SYS_INIT_RAM_DCACHE      1               /* d-cache as init ram  */
  85 #define CONFIG_SYS_INIT_RAM_ADDR        0x70000000              /* DCache       */
  86 #define CONFIG_SYS_INIT_RAM_SIZE                (4 << 10)
  87 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  88                                          GENERATED_GBL_DATA_SIZE)
  89 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  90 #else
  91 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE
  92 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  93 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  94                                          GENERATED_GBL_DATA_SIZE)
  95 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  96 #endif
  97 /* unused GPT0 COMP reg */
  98 #define CONFIG_SYS_POST_WORD_ADDR       (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
  99 #define CONFIG_SYS_OCM_SIZE             (16 << 10)
 100 /* 440EPx errata CHIP 11: don't use last 4kbytes */
 101 #define CONFIG_SYS_MEM_TOP_HIDE         (4 << 10)
 102
 103 /* Additional registers for watchdog timer post test */
 104 #define CONFIG_SYS_WATCHDOG_TIME_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
 105 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR  (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
 106 #define CONFIG_SYS_DSPIC_TEST_ADDR      CONFIG_SYS_WATCHDOG_FLAGS_ADDR
 107 #define CONFIG_SYS_OCM_STATUS_ADDR      CONFIG_SYS_WATCHDOG_FLAGS_ADDR
 108 #define CONFIG_SYS_WATCHDOG_MAGIC       0x12480000
 109 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK  0xFFFF0000
 110 #define CONFIG_SYS_DSPIC_TEST_MASK      0x00000001
 111 #define CONFIG_SYS_OCM_STATUS_OK        0x00009A00
 112 #define CONFIG_SYS_OCM_STATUS_FAIL      0x0000A300
 113 #define CONFIG_SYS_OCM_STATUS_MASK      0x0000FF00
 114
 115 /*
 116  * Serial Port
 117  */
 118 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 119 #define CONFIG_SYS_NS16550
 120 #define CONFIG_SYS_NS16550_SERIAL
 121 #define CONFIG_SYS_NS16550_REG_SIZE     1
 122 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 123 #undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* no external clock provided   */
 124 #define CONFIG_BAUDRATE         115200
 125
 126 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
 127         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 128
 129 /*
 130  * Environment
 131  */
 132 #define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environment vars       */
 133
 134 /*
 135  * FLASH related
 136  */
 137 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 138 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 139
 140 #define CONFIG_SYS_FLASH0               0xFC000000
 141 #define CONFIG_SYS_FLASH1               0xF8000000
 142 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 143
 144 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2     /* max number of memory banks           */
 145 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 146
 147 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 148 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 149
 150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* use buffered writes (20x faster)     */
 151 #define CONFIG_SYS_FLASH_PROTECTION             /* use hardware flash protection        */
 152
 153 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 154 #define CONFIG_SYS_FLASH_QUIET_TEST             /* don't warn upon unknown flash        */
 155
 156 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector          */
 157 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
 158 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 159
 160 /* Address and size of Redundant Environment Sector     */
 161 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 162 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 163
 164 /*
 165  * DDR SDRAM
 166  */
 167 #define CONFIG_SYS_MBYTES_SDRAM         256
 168 #define CONFIG_SYS_DDR_CACHED_ADDR      0x40000000      /* setup 2nd TLB cached here    */
 169 #define CONFIG_DDR_DATA_EYE                     /* use DDR2 optimization        */
 170 #ifndef CONFIG_LCD4_LWMON5
 171 #define CONFIG_DDR_ECC                          /* enable ECC                   */
 172 #endif
 173
 174 #ifndef CONFIG_LCD4_LWMON5
 175 /* POST support */
 176 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 177                                  CONFIG_SYS_POST_CPU            | \
 178                                  CONFIG_SYS_POST_ECC            | \
 179                                  CONFIG_SYS_POST_ETHER          | \
 180                                  CONFIG_SYS_POST_FPU            | \
 181                                  CONFIG_SYS_POST_I2C            | \
 182                                  CONFIG_SYS_POST_MEMORY         | \
 183                                  CONFIG_SYS_POST_OCM            | \
 184                                  CONFIG_SYS_POST_RTC            | \
 185                                  CONFIG_SYS_POST_SPR            | \
 186                                  CONFIG_SYS_POST_UART           | \
 187                                  CONFIG_SYS_POST_SYSMON         | \
 188                                  CONFIG_SYS_POST_WATCHDOG       | \
 189                                  CONFIG_SYS_POST_DSP            | \
 190                                  CONFIG_SYS_POST_BSPEC1         | \
 191                                  CONFIG_SYS_POST_BSPEC2         | \
 192                                  CONFIG_SYS_POST_BSPEC3         | \
 193                                  CONFIG_SYS_POST_BSPEC4         | \
 194                                  CONFIG_SYS_POST_BSPEC5)
 195
 196 /* Define here the base-addresses of the UARTs to test in POST */
 197 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 198                         CONFIG_SYS_NS16550_COM2 }
 199
 200 #define CONFIG_POST_UART  {                             \
 201         "UART test",                                    \
 202         "uart",                                         \
 203         "This test verifies the UART operation.",       \
 204         POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL,   \
 205         &uart_post_test,                                \
 206         NULL,                                           \
 207         NULL,                                           \
 208         CONFIG_SYS_POST_UART                            \
 209         }
 210
 211 #define CONFIG_POST_WATCHDOG  {                         \
 212         "Watchdog timer test",                          \
 213         "watchdog",                                     \
 214         "This test checks the watchdog timer.",         \
 215         POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
 216         &lwmon5_watchdog_post_test,                     \
 217         NULL,                                           \
 218         NULL,                                           \
 219         CONFIG_SYS_POST_WATCHDOG                        \
 220         }
 221
 222 #define CONFIG_POST_BSPEC1    {                         \
 223         "dsPIC init test",                              \
 224         "dspic_init",                                   \
 225         "This test returns result of dsPIC READY test run earlier.",    \
 226         POST_RAM | POST_ALWAYS,                         \
 227         &dspic_init_post_test,                          \
 228         NULL,                                           \
 229         NULL,                                           \
 230         CONFIG_SYS_POST_BSPEC1                          \
 231         }
 232
 233 #define CONFIG_POST_BSPEC2    {                         \
 234         "dsPIC test",                                   \
 235         "dspic",                                        \
 236         "This test gets result of dsPIC POST and dsPIC version.",       \
 237         POST_RAM | POST_ALWAYS,                         \
 238         &dspic_post_test,                               \
 239         NULL,                                           \
 240         NULL,                                           \
 241         CONFIG_SYS_POST_BSPEC2                          \
 242         }
 243
 244 #define CONFIG_POST_BSPEC3    {                         \
 245         "FPGA test",                                    \
 246         "fpga",                                         \
 247         "This test checks FPGA registers and memory.",  \
 248         POST_RAM | POST_ALWAYS | POST_MANUAL,           \
 249         &fpga_post_test,                                \
 250         NULL,                                           \
 251         NULL,                                           \
 252         CONFIG_SYS_POST_BSPEC3                          \
 253         }
 254
 255 #define CONFIG_POST_BSPEC4    {                         \
 256         "GDC test",                                     \
 257         "gdc",                                          \
 258         "This test checks GDC registers and memory.",   \
 259         POST_RAM | POST_ALWAYS | POST_MANUAL,\
 260         &gdc_post_test,                                 \
 261         NULL,                                           \
 262         NULL,                                           \
 263         CONFIG_SYS_POST_BSPEC4                          \
 264         }
 265
 266 #define CONFIG_POST_BSPEC5    {                         \
 267         "SYSMON1 test",                                 \
 268         "sysmon1",                                      \
 269         "This test checks GPIO_62_EPX pin indicating power failure.",   \
 270         POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST,   \
 271         &sysmon1_post_test,                             \
 272         NULL,                                           \
 273         NULL,                                           \
 274         CONFIG_SYS_POST_BSPEC5                          \
 275         }
 276
 277 #define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000 /* free virtual address      */
 278 #define CONFIG_LOGBUFFER
 279 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
 280 #define CONFIG_ALT_LH_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
 281 #define CONFIG_ALT_LB_ADDR      (CONFIG_SYS_OCM_BASE)
 282 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 283 #endif
 284
 285 /*
 286  * I2C
 287  */
 288 #define CONFIG_SYS_I2C
 289 #define CONFIG_SYS_I2C_PPC4XX
 290 #define CONFIG_SYS_I2C_PPC4XX_CH0
 291 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 292 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 293
 294 #define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* RTC                          */
 295 #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR  0x52    /* EEPROM          (CPU Modul)  */
 296 #define CONFIG_SYS_I2C_EEPROM_MB_ADDR   0x53    /* EEPROM AT24C128 (MainBoard)  */
 297 #define CONFIG_SYS_I2C_DSPIC_ADDR       0x54    /* dsPIC                        */
 298 #define CONFIG_SYS_I2C_DSPIC_2_ADDR     0x55    /* dsPIC                        */
 299 #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR  0x56    /* dsPIC                        */
 300 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR    0x57    /* dsPIC                        */
 301
 302 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2        /* Bytes of address             */
 303 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel AT24C128 has       */
 304                                         /* 64 byte page write mode using*/
 305                                         /* last 6 bits of the address   */
 306 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 307 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 308
 309 #define CONFIG_RTC_PCF8563                      /* enable Philips PCF8563 RTC   */
 310 #define CONFIG_SYS_I2C_RTC_ADDR         0x51    /* Philips PCF8563 RTC address  */
 311 #define CONFIG_SYS_I2C_KEYBD_ADDR       0x56    /* PIC LWE keyboard             */
 312 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR    0x57    /* PIC I/O addr               */
 313
 314 #define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_RTC_ADDR,       \
 315                                          CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
 316                                          CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
 317                                          CONFIG_SYS_I2C_DSPIC_ADDR,     \
 318                                          CONFIG_SYS_I2C_DSPIC_2_ADDR,   \
 319                                          CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
 320                                          CONFIG_SYS_I2C_DSPIC_IO_ADDR }
 321
 322 /*
 323  * Pass open firmware flat tree
 324  */
 325 #define CONFIG_OF_LIBFDT
 326 #define CONFIG_OF_BOARD_SETUP
 327 /* Update size in "reg" property of NOR FLASH device tree nodes */
 328 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 329
 330 #define CONFIG_FIT                      /* enable FIT image support     */
 331
 332 #define CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
 333
 334 #define CONFIG_PREBOOT          "setenv bootdelay 15"
 335
 336 #undef  CONFIG_BOOTARGS
 337
 338 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 339         "hostname=lwmon5\0"                                             \
 340         "netdev=eth0\0"                                                 \
 341         "unlock=yes\0"                                                  \
 342         "logversion=2\0"                                                \
 343         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 344                 "nfsroot=${serverip}:${rootpath}\0"                     \
 345         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 346         "addip=setenv bootargs ${bootargs} "                            \
 347                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 348                 ":${hostname}:${netdev}:off panic=1\0"                  \
 349         "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
 350         "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
 351         "flash_nfs=run nfsargs addip addtty addmisc;"                   \
 352                 "bootm ${kernel_addr}\0"                                \
 353         "flash_self=run ramargs addip addtty addmisc;"                  \
 354                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 355         "net_nfs=tftp 200000 ${bootfile};"                              \
 356                 "run nfsargs addip addtty addmisc;bootm\0"              \
 357         "rootpath=/opt/eldk/ppc_4xxFP\0"                                \
 358         "bootfile=/tftpboot/lwmon5/uImage\0"                            \
 359         "kernel_addr=FC000000\0"                                        \
 360         "ramdisk_addr=FC180000\0"                                       \
 361         "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"           \
 362         "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"   \
 363                 "cp.b 200000 FFF80000 80000\0"                          \
 364         "upd=run load update\0"                                         \
 365         "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;"       \
 366                 "autoscr 200000\0"                                      \
 367         ""
 368 #define CONFIG_BOOTCOMMAND      "run flash_self"
 369
 370 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 371
 372 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 373 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 374
 375 #define CONFIG_PPC4xx_EMAC
 376 #define CONFIG_IBM_EMAC4_V4     1
 377 #define CONFIG_MII              1       /* MII PHY management           */
 378 #define CONFIG_PHY_ADDR         3       /* PHY address, See schematics  */
 379
 380 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 381 #define CONFIG_PHY_RESET_DELAY  300
 382
 383 #define CONFIG_HAS_ETH0
 384 #define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 385
 386 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 387 #define CONFIG_PHY1_ADDR        1
 388
 389 /* Video console */
 390 #define CONFIG_VIDEO
 391 #define CONFIG_VIDEO_MB862xx
 392 #define CONFIG_VIDEO_MB862xx_ACCEL
 393 #define CONFIG_CFB_CONSOLE
 394 #define CONFIG_VIDEO_LOGO
 395 #define CONFIG_CONSOLE_EXTRA_INFO
 396 #define VIDEO_FB_16BPP_PIXEL_SWAP
 397 #define VIDEO_FB_16BPP_WORD_SWAP
 398
 399 #define CONFIG_VGA_AS_SINGLE_DEVICE
 400 #define CONFIG_VIDEO_SW_CURSOR
 401 #define CONFIG_SPLASH_SCREEN
 402
 403 #ifndef CONFIG_LCD4_LWMON5
 404 /*
 405  * USB/EHCI
 406  */
 407 #define CONFIG_USB_EHCI                 /* Enable EHCI USB support      */
 408 #define CONFIG_USB_EHCI_PPC4XX          /* on PPC4xx platform           */
 409 #define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 410 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 411 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 412 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
 413 #define CONFIG_USB_STORAGE
 414
 415 /* Partitions */
 416 #define CONFIG_MAC_PARTITION
 417 #define CONFIG_DOS_PARTITION
 418 #define CONFIG_ISO_PARTITION
 419 #endif
 420
 421 /*
 422  * BOOTP options
 423  */
 424 #define CONFIG_BOOTP_BOOTFILESIZE
 425 #define CONFIG_BOOTP_BOOTPATH
 426 #define CONFIG_BOOTP_GATEWAY
 427 #define CONFIG_BOOTP_HOSTNAME
 428
 429 /*
 430  * Command line configuration.
 431  */
 432 #include <config_cmd_default.h>
 433
 434 #define CONFIG_CMD_ASKENV
 435 #define CONFIG_CMD_DATE
 436 #define CONFIG_CMD_DHCP
 437 #define CONFIG_CMD_DIAG
 438 #define CONFIG_CMD_EEPROM
 439 #define CONFIG_CMD_ELF
 440 #define CONFIG_CMD_FAT
 441 #define CONFIG_CMD_I2C
 442 #define CONFIG_CMD_IRQ
 443 #define CONFIG_CMD_MII
 444 #define CONFIG_CMD_NET
 445 #define CONFIG_CMD_NFS
 446 #define CONFIG_CMD_PING
 447 #define CONFIG_CMD_REGINFO
 448 #define CONFIG_CMD_SDRAM
 449
 450 #ifdef CONFIG_VIDEO
 451 #define CONFIG_CMD_BMP
 452 #endif
 453
 454 #ifndef CONFIG_LCD4_LWMON5
 455 #ifdef CONFIG_440EPX
 456 #define CONFIG_CMD_USB
 457 #endif
 458 #endif
 459
 460 /*
 461  * Miscellaneous configurable options
 462  */
 463 #define CONFIG_SUPPORT_VFAT
 464
 465 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 466
 467 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 468
 469 #if defined(CONFIG_CMD_KGDB)
 470 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 471 #else
 472 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 473 #endif
 474 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 475 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 476 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 477
 478 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 479 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 480
 481 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 482 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 483
 484 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 485 #define CONFIG_LOOPW            1       /* enable loopw command         */
 486 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 487 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 488
 489 #define CONFIG_SYS_CONSOLE_INFO_QUIET   /* don't print console @ startup*/
 490
 491 #ifndef CONFIG_LCD4_LWMON5
 492 #ifndef DEBUG
 493 #define CONFIG_HW_WATCHDOG      1       /* Use external HW-Watchdog     */
 494 #endif
 495 #define CONFIG_WD_PERIOD        40000   /* in usec */
 496 #define CONFIG_WD_MAX_RATE      66600   /* in ticks */
 497 #endif
 498
 499 /*
 500  * For booting Linux, the board info and command line data
 501  * have to be in the first 16 MB of memory, since this is
 502  * the maximum mapped by the 40x Linux kernel during initialization.
 503  */
 504 #define CONFIG_SYS_BOOTMAPSZ            (16 << 20) /* Initial Memory map for Linux */
 505 #define CONFIG_SYS_BOOTM_LEN            (16 << 20) /* Increase max gunzip size */
 506
 507 /*
 508  * External Bus Controller (EBC) Setup
 509  */
 510 #define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 511
 512 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 513 #define CONFIG_SYS_EBC_PB0AP            0x03000280
 514 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH | 0xfc000)
 515
 516 /* Memory Bank 1 (Lime) initialization                                          */
 517 #define CONFIG_SYS_EBC_PB1AP            0x01004380
 518 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
 519
 520 /* Memory Bank 2 (FPGA) initialization                                          */
 521 #define CONFIG_SYS_EBC_PB2AP            0x01004400
 522 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
 523
 524 /* Memory Bank 3 (FPGA2) initialization                                         */
 525 #define CONFIG_SYS_EBC_PB3AP            0x01004400
 526 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
 527
 528 #define CONFIG_SYS_EBC_CFG              0xb8400000
 529
 530 /*
 531  * Graphics (Fujitsu Lime)
 532  */
 533 /* SDRAM Clock frequency adjustment register */
 534 #define CONFIG_SYS_LIME_SDRAM_CLOCK     0xC1FC0038
 535 #if 1 /* 133MHz is not tested enough, use 100MHz for now */
 536 /* Lime Clock frequency is to set 100MHz */
 537 #define CONFIG_SYS_LIME_CLOCK_100MHZ    0x00000
 538 #else
 539 /* Lime Clock frequency for 133MHz */
 540 #define CONFIG_SYS_LIME_CLOCK_133MHZ    0x10000
 541 #endif
 542
 543 /* SDRAM Parameter register */
 544 #define CONFIG_SYS_LIME_MMR             0xC1FCFFFC
 545 /*
 546  * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
 547  * and pixel flare on display when 133MHz was configured. According to
 548  * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
 549  * Grade
 550  */
 551 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
 552 #define CONFIG_SYS_MB862xx_MMR  0x414FB7F3
 553 #define CONFIG_SYS_MB862xx_CCF  CONFIG_SYS_LIME_CLOCK_133MHZ
 554 #else
 555 #define CONFIG_SYS_MB862xx_MMR  0x414FB7F2
 556 #define CONFIG_SYS_MB862xx_CCF  CONFIG_SYS_LIME_CLOCK_100MHZ
 557 #endif
 558
 559 /*
 560  * GPIO Setup
 561  */
 562 #define CONFIG_SYS_GPIO_PHY1_RST        12
 563 #define CONFIG_SYS_GPIO_FLASH_WP        14
 564 #define CONFIG_SYS_GPIO_PHY0_RST        22
 565 #define CONFIG_SYS_GPIO_PERM_VOLT_FEED  49
 566 #define CONFIG_SYS_GPIO_DSPIC_READY     51
 567 #define CONFIG_SYS_GPIO_CAN_ENABLE      53
 568 #define CONFIG_SYS_GPIO_LSB_ENABLE      54
 569 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP   55
 570 #define CONFIG_SYS_GPIO_HIGHSIDE        56
 571 #define CONFIG_SYS_GPIO_EEPROM_INT_WP   57
 572 #define CONFIG_SYS_GPIO_BOARD_RESET     58
 573 #define CONFIG_SYS_GPIO_LIME_S          59
 574 #define CONFIG_SYS_GPIO_LIME_RST        60
 575 #define CONFIG_SYS_GPIO_SYSMON_STATUS   62
 576 #define CONFIG_SYS_GPIO_WATCHDOG        63
 577
 578 /* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
 579 #ifdef CONFIG_LCD4_LWMON5
 580 #define GPIO49_VAL      0
 581 #else
 582 #define GPIO49_VAL      1
 583 #endif
 584
 585 /*
 586  * PPC440 GPIO Configuration
 587  */
 588 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 589 {                                                                                       \
 590 /* GPIO Core 0 */                                                                       \
 591 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 592 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 593 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 594 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 595 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 596 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 597 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 598 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 599 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 600 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 601 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 602 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 603 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 604 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 605 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14                                */      \
 606 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15                                */      \
 607 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)                      */      \
 608 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)                      */      \
 609 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)                      */      \
 610 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)                      */      \
 611 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 612 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 613 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 614 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 615 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)                      */      \
 616 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)                      */      \
 617 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 618 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 619 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28                USB2D_TXVALID   */      \
 620 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 621 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 622 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 623 },                                                                                      \
 624 {                                                                                       \
 625 /* GPIO Core 1 */                                                                       \
 626 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 627 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 628 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 629 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 630 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)   UART3_SIN*/ \
 631 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 632 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 633 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 634 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 635 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 636 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 637 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 638 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 639 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 640 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 641 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 642 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 643 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 644 {GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 645 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 646 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 647 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 648 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 649 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 650 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 651 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 652 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 653 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 654 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 655 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 656 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 657 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 658 }                                                                                       \
 659 }
 660
 661 #if defined(CONFIG_CMD_KGDB)
 662 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 663 #define CONFIG_KGDB_SER_INDEX   2           /* which serial port to use */
 664 #endif
 665
 666 /*
 667  * SPL related defines
 668  */
 669 #ifdef CONFIG_LCD4_LWMON5
 670 #define CONFIG_SPL
 671 #define CONFIG_SPL_FRAMEWORK
 672 #define CONFIG_SPL_BOARD_INIT
 673 #define CONFIG_SPL_NOR_SUPPORT
 674 #define CONFIG_SPL_TEXT_BASE            0xffff0000 /* last 64 KiB for SPL */
 675 #define CONFIG_SYS_SPL_MAX_LEN          (64 << 10)
 676 #define CONFIG_UBOOT_PAD_TO             458752  /* decimal for 'dd' */
 677 #define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
 678 #define CONFIG_SPL_LDSCRIPT     "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
 679 #define CONFIG_SPL_LIBCOMMON_SUPPORT    /* image.c */
 680 #define CONFIG_SPL_LIBGENERIC_SUPPORT   /* string.c */
 681 #define CONFIG_SPL_SERIAL_SUPPORT
 682
 683 /* Place BSS for SPL near end of SDRAM */
 684 #define CONFIG_SPL_BSS_START_ADDR       ((256 - 1) << 20)
 685 #define CONFIG_SPL_BSS_MAX_SIZE         (64 << 10)
 686
 687 #define CONFIG_SPL_OS_BOOT
 688 /* Place patched DT blob (fdt) at this address */
 689 #define CONFIG_SYS_SPL_ARGS_ADDR        0x01800000
 690
 691 #define CONFIG_SPL_TARGET               "u-boot-img-spl-at-end.bin"
 692
 693 /* Settings for real U-Boot to be loaded from NOR flash */
 694 #define CONFIG_SYS_UBOOT_BASE           (-CONFIG_SYS_MONITOR_LEN)
 695 #define CONFIG_SYS_UBOOT_START          0x01002100
 696
 697 #define CONFIG_SYS_OS_BASE              0xf8000000
 698 #define CONFIG_SYS_FDT_BASE             0xf87c0000
 699 #endif
 700
 701 #endif  /* __CONFIG_H */