include/configs/rsdproto.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Configuation settings for the R&S Protocol Board board.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU       */
  39 #define CONFIG_RSD_PROTO        1       /* on a R&S Protocol Board      */
  40
  41 /*
  42  * select serial console configuration
  43  *
  44  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  45  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  46  * for SCC).
  47  *
  48  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  49  * defined elsewhere.
  50  */
  51 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  52 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  53 #undef  CONFIG_CONS_NONE                /* define if console on neither */
  54 #define CONFIG_CONS_INDEX       1       /* which SMC/SCC channel for console */
  55
  56 /*
  57  * select ethernet configuration
  58  *
  59  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  60  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  61  * for FCC)
  62  *
  63  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  64  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  65  * from CONFIG_COMMANDS to remove support for networking.
  66  */
  67 #undef  CONFIG_ETHER_ON_SCC             /* define if ethernet on SCC    */
  68 #define CONFIG_ETHER_ON_FCC             /* define if ethernet on FCC    */
  69 #undef  CONFIG_ETHER_NONE               /* define if ethernet on neither */
  70 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
  71
  72 #if (CONFIG_ETHER_INDEX == 2)
  73
  74 /*
  75  * - Rx-CLK is CLK13
  76  * - Tx-CLK is CLK14
  77  * - Select bus for bd/buffers (see 28-13)
  78  * - Enable Full Duplex in FSMR
  79  */
  80 # define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  81 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  82 # define CFG_CPMFCR_RAMTYPE     (0)
  83 # define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
  84
  85 #endif /* CONFIG_ETHER_INDEX */
  86
  87
  88 /* allow to overwrite serial and ethaddr */
  89 #define CONFIG_ENV_OVERWRITE
  90
  91 /* enable I2C */
  92 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
  93 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
  94 #define CFG_I2C_SLAVE           0x7F
  95
  96
  97 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  98 #define CONFIG_8260_CLKIN       50000000        /* in Hz */
  99
 100 #define CONFIG_BAUDRATE         115200
 101
 102 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
 103
 104 /* Define this if you want to boot from 0x00000100. If you don't define
 105  * this, you will need to program the bootloader to 0xfff00000, and
 106  * get the hardware reset config words at 0xfe000000. The simplest
 107  * way to do that is to program the bootloader at both addresses.
 108  * It is suggested that you just let U-Boot live at 0x00000000.
 109  */
 110 #define CFG_RSD_BOOT_LOW 1
 111
 112 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 113 #include <cmd_confdefs.h>
 114
 115 #define CONFIG_BOOTDELAY        5
 116 #define CONFIG_BOOTARGS         "devfs=mount root=ramfs"
 117 #define CONFIG_ETHADDR          08:00:3e:26:0a:5a
 118 #define CONFIG_NETMASK          255.255.0.0
 119
 120 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 121 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 122 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 123 #endif
 124
 125 /*
 126  * Miscellaneous configurable options
 127  */
 128 #define CFG_LONGHELP                            /* undef to save memory         */
 129 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
 130 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 131 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
 132 #else
 133 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 134 #endif
 135 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 136 #define CFG_MAXARGS             16              /* max number of command args   */
 137 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 138
 139 #define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
 140 #define CFG_MEMTEST_END         0x01c00000      /* 4 ... 28 MB in DRAM  */
 141
 142 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 143
 144 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 145
 146                                                 /* valid baudrates */
 147 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 148
 149 /*
 150  * Low Level Configuration Settings
 151  * (address mappings, register initial values, etc.)
 152  * You should know what you are doing if you make changes here.
 153  */
 154
 155 /*-----------------------------------------------------------------------
 156  * Physical Memory Map
 157  */
 158 #define PHYS_SDRAM_60X          0x00000000 /* SDRAM (60x Bus) */
 159 #define PHYS_SDRAM_60X_SIZE     0x08000000 /* 128 MB */
 160
 161 #define PHYS_SDRAM_LOCAL        0x40000000 /* SDRAM (Local Bus) */
 162 #define PHYS_SDRAM_LOCAL_SIZE   0x04000000 /* 64 MB */
 163
 164 #define PHYS_DPRAM_PCI          0xE8000000 /* DPRAM PPC/PCI */
 165 #define PHYS_DPRAM_PCI_SIZE     0x00020000 /* 128 KB */
 166
 167 /*#define PHYS_DPRAM_PCI_SEM    0x04020000 / * DPRAM PPC/PCI Semaphore */
 168 /*#define PHYS_DPRAM_PCI_SEM_SIZE       0x00000001 / * 1 Byte */
 169
 170 #define PHYS_DPRAM_SHARC        0xE8100000 /* DPRAM PPC/Sharc */
 171 #define PHYS_DPRAM_SHARC_SIZE   0x00040000 /* 256 KB */
 172
 173 /*#define PHYS_DPRAM_SHARC_SEM  0x04140000 / * DPRAM PPC/Sharc Semaphore */
 174 /*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
 175
 176 #define PHYS_VIRTEX_REGISTER    0xE8300000 /* FPGA implemented register */
 177 #define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
 178
 179 #define PHYS_USB                0x04200000 /* USB Controller (60x Bus) */
 180 #define PHYS_USB_SIZE           0x00000002 /* 2 Bytes */
 181
 182 #define PHYS_IMMR               0xF0000000 /* Internal Memory Mapped Reg. */
 183
 184 #define PHYS_FLASH              0xFF000000 /* Flash (60x Bus) */
 185 #define PHYS_FLASH_SIZE         0x01000000 /* 16 MB */
 186
 187 #define CFG_IMMR                PHYS_IMMR
 188
 189 /*-----------------------------------------------------------------------
 190  * Reset Address
 191  *
 192  * In order to reset the CPU, U-Boot jumps to a special address which
 193  * causes a machine check exception. The default address for this is
 194  * CFG_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
 195  * testing the monitor in RAM using a JTAG debugger.
 196  *
 197  * Just set CFG_RESET_ADDRESS to an address that you know is sure to
 198  * cause a bus error on your hardware.
 199  */
 200 #define CFG_RESET_ADDRESS       0x20000000
 201
 202 /*-----------------------------------------------------------------------
 203  * Hard Reset Configuration Words
 204  */
 205
 206 #if defined(CFG_RSD_BOOT_LOW)
 207 #  define  CFG_RSD_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 208 #else
 209 #  define  CFG_RSD_HRCW_BOOT_FLAGS  (0)
 210 #endif /* defined(CFG_RSD_BOOT_LOW) */
 211
 212 /* get the HRCW ISB field from CFG_IMMR */
 213 #define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
 214                             ((CFG_IMMR & 0x01000000) >> 7)  |\
 215                             ((CFG_IMMR & 0x00100000) >> 4) )
 216
 217 #define CFG_HRCW_MASTER (HRCW_L2CPC10 | \
 218                          HRCW_DPPC11 | \
 219                          CFG_RSD_HRCW_IMMR |\
 220                          HRCW_MMR00 | \
 221                          HRCW_APPC10 | \
 222                          HRCW_CS10PC00 | \
 223                          HRCW_MODCK_H0000 |\
 224                          CFG_RSD_HRCW_BOOT_FLAGS)
 225
 226 /* no slaves */
 227 #define CFG_HRCW_SLAVE1 0
 228 #define CFG_HRCW_SLAVE2 0
 229 #define CFG_HRCW_SLAVE3 0
 230 #define CFG_HRCW_SLAVE4 0
 231 #define CFG_HRCW_SLAVE5 0
 232 #define CFG_HRCW_SLAVE6 0
 233 #define CFG_HRCW_SLAVE7 0
 234
 235 /*-----------------------------------------------------------------------
 236  * Definitions for initial stack pointer and data area (in DPRAM)
 237  */
 238 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 239 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 240 #define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
 241 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 242 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 243
 244 /*-----------------------------------------------------------------------
 245  * Start addresses for the final memory configuration
 246  * (Set up by the startup code)
 247  * Please note that CFG_SDRAM_BASE _must_ start at 0
 248  * Note also that the logic that sets CFG_RAMBOOT is platform dependend.
 249  */
 250 #define CFG_SDRAM_BASE          PHYS_SDRAM_60X
 251 #define CFG_FLASH_BASE          PHYS_FLASH
 252 /*#define       CFG_MONITOR_BASE        0x200000 */
 253 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 254 #if CFG_MONITOR_BASE < CFG_FLASH_BASE
 255 #define CFG_RAMBOOT
 256 #endif
 257 #define CFG_MONITOR_LEN         (160 << 10)     /* Reserve 160 kB for Monitor   */
 258 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 259
 260 /*
 261  * For booting Linux, the board info and command line data
 262  * have to be in the first 8 MB of memory, since this is
 263  * the maximum mapped by the Linux kernel during initialization.
 264  */
 265 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 266
 267 /*-----------------------------------------------------------------------
 268  * FLASH and environment organization
 269  */
 270 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 271 #define CFG_MAX_FLASH_SECT      63      /* max number of sectors on one chip    */
 272
 273 #define CFG_FLASH_ERASE_TOUT    12000   /* Timeout for Flash Erase (in ms)      */
 274 #define CFG_FLASH_WRITE_TOUT    3000    /* Timeout for Flash Write (in ms)      */
 275
 276 /* turn off NVRAM env feature */
 277 #undef CONFIG_NVRAM_ENV
 278
 279 #define CFG_ENV_IS_IN_FLASH     1
 280 #define CFG_ENV_ADDR    (PHYS_FLASH + 0x28000)  /* Addr of Environment Sector   */
 281 #define CFG_ENV_SECT_SIZE       0x8000  /* Total Size of Environment Sector     */
 282
 283 /*-----------------------------------------------------------------------
 284  * Cache Configuration
 285  */
 286 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU                      */
 287 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 288 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 289 #endif
 290
 291 /*-----------------------------------------------------------------------
 292  * HIDx - Hardware Implementation-dependent Registers                    2-11
 293  *-----------------------------------------------------------------------
 294  * HID0 also contains cache control - initially enable both caches and
 295  * invalidate contents, then the final state leaves only the instruction
 296  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 297  * but Soft reset does not.
 298  *
 299  * HID1 has only read-only information - nothing to set.
 300  */
 301 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
 302 #define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
 303 #define CFG_HID2        0
 304
 305 /*-----------------------------------------------------------------------
 306  * RMR - Reset Mode Register
 307  *-----------------------------------------------------------------------
 308  */
 309 #define CFG_RMR         0
 310
 311 /*-----------------------------------------------------------------------
 312  * BCR - Bus Configuration                                       4-25
 313  *-----------------------------------------------------------------------
 314  */
 315 #define CFG_BCR         0x100c0000
 316
 317 /*-----------------------------------------------------------------------
 318  * SIUMCR - SIU Module Configuration                             4-31
 319  *-----------------------------------------------------------------------
 320  */
 321
 322 #define CFG_SIUMCR      (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
 323                                          SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
 324
 325 /*-----------------------------------------------------------------------
 326  * SYPCR - System Protection Control                            11-9
 327  * SYPCR can only be written once after reset!
 328  *-----------------------------------------------------------------------
 329  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 330  */
 331 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
 332                          SYPCR_SWRI | SYPCR_SWP)
 333
 334 /*-----------------------------------------------------------------------
 335  * TMCNTSC - Time Counter Status and Control                     4-40
 336  *-----------------------------------------------------------------------
 337  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 338  * and enable Time Counter
 339  */
 340 #define CFG_TMCNTSC     (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
 341
 342 /*-----------------------------------------------------------------------
 343  * PISCR - Periodic Interrupt Status and Control                 4-42
 344  *-----------------------------------------------------------------------
 345  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 346  * Periodic timer
 347  */
 348 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 349
 350 /*-----------------------------------------------------------------------
 351  * SCCR - System Clock Control                                   9-8
 352  *-----------------------------------------------------------------------
 353  */
 354 #define CFG_SCCR        0x00000000
 355
 356 /*-----------------------------------------------------------------------
 357  * RCCR - RISC Controller Configuration                         13-7
 358  *-----------------------------------------------------------------------
 359  */
 360 #define CFG_RCCR        0
 361
 362 /*
 363  * Init Memory Controller:
 364  */
 365
 366 #define CFG_PSDMR       0x494D2452
 367 #define CFG_LSDMR       0x49492552
 368
 369 /* Flash */
 370 #define CFG_BR0_PRELIM  (PHYS_FLASH | BRx_V)
 371 #define CFG_OR0_PRELIM  (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
 372                          ORxG_BCTLD | \
 373                          ORxG_SCY_5_CLK)
 374
 375 /* DPRAM to the PCI BUS on the protocol board */
 376 #define CFG_BR1_PRELIM  (PHYS_DPRAM_PCI | BRx_V)
 377 #define CFG_OR1_PRELIM  (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
 378                          ORxG_ACS_DIV4)
 379
 380 /* 60x Bus SDRAM */
 381 #define CFG_BR2_PRELIM  (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
 382 #define CFG_OR2_PRELIM  (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
 383                          ORxS_BPD_4 | \
 384                          ORxS_ROWST_PBI1_A2 | \
 385                          ORxS_NUMR_13 | \
 386                          ORxS_IBID)
 387
 388 /* Virtex-FPGA - Register */
 389 #define CFG_BR3_PRELIM  (PHYS_VIRTEX_REGISTER | BRx_V)
 390 #define CFG_OR3_PRELIM  (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
 391                          ORxG_SCY_1_CLK | \
 392                          ORxG_ACS_DIV2 | \
 393                          ORxG_CSNT )
 394
 395 /* local bus SDRAM */
 396 #define CFG_BR4_PRELIM  (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
 397 #define CFG_OR4_PRELIM  (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
 398                          ORxS_BPD_4 | \
 399                          ORxS_ROWST_PBI1_A4 | \
 400                          ORxS_NUMR_13)
 401
 402 /* DPRAM to the Sharc-Bus on the protocol board */
 403 #define CFG_BR5_PRELIM  (PHYS_DPRAM_SHARC | BRx_V)
 404 #define CFG_OR5_PRELIM  (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
 405                          ORxG_ACS_DIV4)
 406
 407 /*
 408  * Internal Definitions
 409  *
 410  * Boot Flags
 411  */
 412 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 413 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 414
 415 #endif  /* __CONFIG_H */