include/configs/sama5d3xek.h

   1 /*
   2  * Configuation settings for the SAMA5D3xEK board.
   3  *
   4  * Copyright (C) 2012 - 2013 Atmel
   5  *
   6  * based on at91sam9m10g45ek.h by:
   7  * Stelian Pop <stelian@popies.net>
   8  * Lead Tech Design <www.leadtechdesign.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #include <asm/hardware.h>
  17
  18 #define CONFIG_SYS_TEXT_BASE            0x26f00000
  19
  20 /* ARM asynchronous clock */
  21 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  22 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  23
  24 #define CONFIG_AT91FAMILY
  25 #define CONFIG_ARCH_CPU_INIT
  26
  27 #define CONFIG_SKIP_LOWLEVEL_INIT
  28 #define CONFIG_BOARD_EARLY_INIT_F
  29 #define CONFIG_DISPLAY_CPUINFO
  30
  31 #define CONFIG_CMD_BOOTZ
  32 #define CONFIG_OF_LIBFDT                /* Device Tree support */
  33
  34 /* general purpose I/O */
  35 #define CONFIG_AT91_GPIO
  36
  37 /* serial console */
  38 #define CONFIG_ATMEL_USART
  39 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  40 #define CONFIG_USART_ID                 ATMEL_ID_DBGU
  41
  42 /*
  43  * This needs to be defined for the OHCI code to work but it is defined as
  44  * ATMEL_ID_UHPHS in the CPU specific header files.
  45  */
  46 #define ATMEL_ID_UHP                    ATMEL_ID_UHPHS
  47
  48 /*
  49  * Specify the clock enable bit in the PMC_SCER register.
  50  */
  51 #define ATMEL_PMC_UHP                   AT91SAM926x_PMC_UHP
  52
  53 /* LCD */
  54 #define CONFIG_LCD
  55 #define LCD_BPP                         LCD_COLOR16
  56 #define LCD_OUTPUT_BPP                  24
  57 #define CONFIG_LCD_LOGO
  58 #define CONFIG_LCD_INFO
  59 #define CONFIG_LCD_INFO_BELOW_LOGO
  60 #define CONFIG_SYS_WHITE_ON_BLACK
  61 #define CONFIG_ATMEL_HLCD
  62 #define CONFIG_ATMEL_LCD_RGB565
  63 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  64
  65 /* board specific (not enough SRAM) */
  66 #define CONFIG_SAMA5D3_LCD_BASE         0x23E00000
  67
  68 #define CONFIG_BOOTDELAY                3
  69
  70 /*
  71  * BOOTP options
  72  */
  73 #define CONFIG_BOOTP_BOOTFILESIZE
  74 #define CONFIG_BOOTP_BOOTPATH
  75 #define CONFIG_BOOTP_GATEWAY
  76 #define CONFIG_BOOTP_HOSTNAME
  77
  78 /* No NOR flash */
  79 #define CONFIG_SYS_NO_FLASH
  80
  81 /*
  82  * Command line configuration.
  83  */
  84 #include <config_cmd_default.h>
  85 #undef CONFIG_CMD_FPGA
  86 #undef CONFIG_CMD_IMI
  87 #undef CONFIG_CMD_LOADS
  88 #define CONFIG_CMD_PING
  89 #define CONFIG_CMD_DHCP
  90
  91 /* SDRAM */
  92 #define CONFIG_NR_DRAM_BANKS            1
  93 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
  94 #define CONFIG_SYS_SDRAM_SIZE           0x20000000
  95
  96 #define CONFIG_SYS_INIT_SP_ADDR \
  97         (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
  98
  99 /* SerialFlash */
 100 #define CONFIG_CMD_SF
 101
 102 #ifdef CONFIG_CMD_SF
 103 #define CONFIG_ATMEL_SPI
 104 #define CONFIG_SPI_FLASH
 105 #define CONFIG_SPI_FLASH_ATMEL
 106 #define CONFIG_SF_DEFAULT_SPEED         30000000
 107 #endif
 108
 109 /* NAND flash */
 110 #define CONFIG_CMD_NAND
 111
 112 #ifdef CONFIG_CMD_NAND
 113 #define CONFIG_NAND_ATMEL
 114 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 115 #define CONFIG_SYS_NAND_BASE            ATMEL_BASE_CS3
 116 /* our ALE is AD21 */
 117 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
 118 /* our CLE is AD22 */
 119 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
 120 #define CONFIG_SYS_NAND_ONFI_DETECTION
 121 /* PMECC & PMERRLOC */
 122 #define CONFIG_ATMEL_NAND_HWECC
 123 #define CONFIG_ATMEL_NAND_HW_PMECC
 124 #define CONFIG_PMECC_CAP                4
 125 #define CONFIG_PMECC_SECTOR_SIZE        512
 126 #define CONFIG_CMD_NAND_TRIMFFS
 127 #endif
 128
 129 /* Ethernet Hardware */
 130 #define CONFIG_MACB
 131 #define CONFIG_RMII
 132 #define CONFIG_NET_RETRY_COUNT          20
 133 #define CONFIG_MACB_SEARCH_PHY
 134 #define CONFIG_RGMII
 135 #define CONFIG_CMD_MII
 136 #define CONFIG_PHYLIB
 137 #define CONFIG_PHY_MICREL
 138 #define CONFIG_PHY_MICREL_KSZ9021
 139
 140 /* MMC */
 141 #define CONFIG_CMD_MMC
 142
 143 #ifdef CONFIG_CMD_MMC
 144 #define CONFIG_MMC
 145 #define CONFIG_GENERIC_MMC
 146 #define CONFIG_GENERIC_ATMEL_MCI
 147 #define ATMEL_BASE_MMCI                 ATMEL_BASE_MCI0
 148 #endif
 149
 150 /* USB */
 151 #define CONFIG_CMD_USB
 152
 153 #ifdef CONFIG_CMD_USB
 154 #define CONFIG_USB_ATMEL
 155 #define CONFIG_USB_OHCI_NEW
 156 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 157 #define CONFIG_SYS_USB_OHCI_REGS_BASE           ATMEL_BASE_OHCI
 158 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "sama5d3"
 159 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      3
 160 #define CONFIG_DOS_PARTITION
 161 #define CONFIG_USB_STORAGE
 162 #endif
 163
 164 /* USB device */
 165 #define CONFIG_USB_GADGET
 166 #define CONFIG_USB_GADGET_DUALSPEED
 167 #define CONFIG_USB_GADGET_ATMEL_USBA
 168 #define CONFIG_USB_ETHER
 169 #define CONFIG_USB_ETH_RNDIS
 170 #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D3xEK"
 171
 172 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
 173 #define CONFIG_CMD_FAT
 174 #endif
 175
 176 #define CONFIG_SYS_LOAD_ADDR                    0x22000000 /* load address */
 177
 178 #ifdef CONFIG_SYS_USE_SERIALFLASH
 179 /* bootstrap + u-boot + env + linux in serial flash */
 180 #define CONFIG_ENV_IS_IN_SPI_FLASH
 181 #define CONFIG_ENV_OFFSET       0x5000
 182 #define CONFIG_ENV_SIZE         0x3000
 183 #define CONFIG_ENV_SECT_SIZE    0x1000
 184 #define CONFIG_BOOTCOMMAND      "sf probe 0; " \
 185                                 "sf read 0x22000000 0x42000 0x300000; " \
 186                                 "bootm 0x22000000"
 187 #elif CONFIG_SYS_USE_NANDFLASH
 188 /* bootstrap + u-boot + env in nandflash */
 189 #define CONFIG_ENV_IS_IN_NAND
 190 #define CONFIG_ENV_OFFSET               0xc0000
 191 #define CONFIG_ENV_OFFSET_REDUND        0x100000
 192 #define CONFIG_ENV_SIZE                 0x20000
 193 #define CONFIG_BOOTCOMMAND      "nand read 0x21000000 0x180000 0x80000;" \
 194                                 "nand read 0x22000000 0x200000 0x600000;" \
 195                                 "bootm 0x22000000 - 0x21000000"
 196 #elif CONFIG_SYS_USE_MMC
 197 /* bootstrap + u-boot + env in sd card */
 198 #define CONFIG_ENV_IS_IN_MMC
 199 #define CONFIG_ENV_OFFSET       0x2000
 200 #define CONFIG_ENV_SIZE         0x1000
 201 #define CONFIG_BOOTCOMMAND      "fatload mmc 0:1 0x21000000 dtb; " \
 202                                 "fatload mmc 0:1 0x22000000 uImage; " \
 203                                 "bootm 0x22000000 - 0x21000000"
 204 #define CONFIG_SYS_MMC_ENV_DEV  0
 205 #else
 206 #define CONFIG_ENV_IS_NOWHERE
 207 #endif
 208
 209 #ifdef CONFIG_SYS_USE_MMC
 210 #define CONFIG_BOOTARGS                                                 \
 211         "console=ttyS0,115200 earlyprintk "                             \
 212         "root=/dev/mmcblk0p2 rw rootwait"
 213 #else
 214 #define CONFIG_BOOTARGS                                                 \
 215         "console=ttyS0,115200 earlyprintk "                             \
 216         "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"          \
 217         "256K(env),256k(evn_redundent),256k(spare),"                    \
 218         "512k(dtb),6M(kernel)ro,-(rootfs) "                             \
 219         "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
 220 #endif
 221
 222 #define CONFIG_BAUDRATE                 115200
 223
 224 #define CONFIG_SYS_PROMPT               "U-Boot> "
 225 #define CONFIG_SYS_CBSIZE               256
 226 #define CONFIG_SYS_MAXARGS              16
 227 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 228                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 229 #define CONFIG_SYS_LONGHELP
 230 #define CONFIG_CMDLINE_EDITING
 231 #define CONFIG_AUTO_COMPLETE
 232 #define CONFIG_SYS_HUSH_PARSER
 233
 234 /* Size of malloc() pool */
 235 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 236
 237 #endif