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1 /*
2 * (C) Copyright 2001
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * board/config.h - configuration options, board specific
9 */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
19 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
20 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
21 #define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
22
23 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
24
25 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
26 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
27
28 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
29
30 #define CONFIG_BAUDRATE 9600
31
32 #define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
33
34 #define CONFIG_RAMBOOT \
35 "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
36 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
37 "bootm ffc00000 ffca0000"
38 #define CONFIG_NFSBOOT \
39 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
40 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
41 "bootm ffc00000"
42
43 #undef CONFIG_BOOTARGS
44 #define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
45
46
47 #define CONFIG_PPC4xx_EMAC
48 #define CONFIG_MII 1 /* MII PHY management */
49 #define CONFIG_PHY_ADDR 0 /* PHY address */
50 #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
51
52 #define CONFIG_EXTRA_ENV_SETTINGS \
53 "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
54 "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
55 "f=0x08 tn=sbc405 o=emac \0" \
56 "env_startaddr=FF000000\0" \
57 "env_endaddr=FF03FFFF\0" \
58 "loadfile=vxWorks.st\0" \
59 "loadaddr=0x01000000\0" \
60 "net_load=tftpboot ${loadaddr} ${loadfile}\0" \
61 "uboot_startaddr=FFFC0000\0" \
62 "uboot_endaddr=FFFFFFFF\0" \
63 "update=tftp ${loadaddr} u-boot.bin;" \
64 "protect off ${uboot_startaddr} ${uboot_endaddr};" \
65 "era ${uboot_startaddr} ${uboot_endaddr};" \
66 "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
67 "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
68 "zapenv=protect off ${env_startaddr} ${env_endaddr};" \
69 "era ${env_startaddr} ${env_endaddr};" \
70 "protect on ${env_startaddr} ${env_endaddr}\0"
71
72 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
73
74 /*
75 * BOOTP options
76 */
77 #define CONFIG_BOOTP_SUBNETMASK
78 #define CONFIG_BOOTP_GATEWAY
79 #define CONFIG_BOOTP_HOSTNAME
80 #define CONFIG_BOOTP_BOOTPATH
81 #define CONFIG_BOOTP_BOOTFILESIZE
82
83
84 #define CONFIG_ENV_OVERWRITE
85
86
87 /*
88 * Command line configuration.
89 */
90 #include <config_cmd_default.h>
91
92 #define CONFIG_CMD_BSP
93 #define CONFIG_CMD_ELF
94 #define CONFIG_CMD_I2C
95 #define CONFIG_CMD_IRQ
96 #define CONFIG_CMD_MII
97 #define CONFIG_CMD_PCI
98 #define CONFIG_CMD_PING
99 #define CONFIG_CMD_SDRAM
100
101
102 #undef CONFIG_WATCHDOG /* watchdog disabled */
103
104 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
105
106 #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
107 #define CONFIG_IPADDR 192.168.193.102
108 #define CONFIG_NETMASK 255.255.255.224
109 #define CONFIG_SERVERIP 192.168.193.119
110 #define CONFIG_GATEWAYIP 192.168.193.97
111
112 /*
113 * Miscellaneous configurable options
114 */
115 #define CONFIG_SYS_LONGHELP /* undef to save memory */
116
117 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
118
119 #if defined(CONFIG_CMD_KGDB)
120 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
121 #else
122 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
123 #endif
124 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
127
128 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
129 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
130
131 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
132 #define CONFIG_SYS_NS16550
133 #define CONFIG_SYS_NS16550_SERIAL
134 #define CONFIG_SYS_NS16550_REG_SIZE 1
135 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
136
137 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
138 #define CONFIG_SYS_BASE_BAUD 691200
139
140 /* The following table includes the supported baudrates */
141 #define CONFIG_SYS_BAUDRATE_TABLE \
142 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
143 57600, 115200, 230400, 460800, 921600 }
144
145 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
146 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
147
148 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
149
150 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
151
152 #define CONFIG_SYS_I2C
153 #define CONFIG_SYS_I2C_PPC4XX
154 #define CONFIG_SYS_I2C_PPC4XX_CH0
155 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
156 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
157
158 /*-----------------------------------------------------------------------
159 * PCI stuff
160 *-----------------------------------------------------------------------
161 */
162 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
163 #define PCI_HOST_FORCE 1 /* configure as pci host */
164 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
165
166 #define CONFIG_PCI /* include pci support */
167 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
168 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
169 #define CONFIG_PCI_PNP /* do pci plug-and-play */
170 /* resource configuration */
171
172 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
173
174 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
175 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
176 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
177 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
178 #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
179 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
180 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
181 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
182 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
183
184 /*-----------------------------------------------------------------------
185 * Start addresses for the final memory configuration
186 * (Set up by the startup code)
187 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
188 */
189 #define CONFIG_SYS_SDRAM_BASE 0x00000000
190 #define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
191 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
192 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
193
194 /*
195 * For booting Linux, the board info and command line data
196 * have to be in the first 8 MB of memory, since this is
197 * the maximum mapped by the Linux kernel during initialization.
198 */
199 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
200
201 /*-----------------------------------------------------------------------
202 * FLASH organization
203 */
204 #define CONFIG_SYS_FLASH_BASE 0xFF000000
205 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
206 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
207 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
208 #define CONFIG_SYS_FLASH_INCREMENT 0x01000000
209 #undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
210 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
212 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
213 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
214
215 /*-----------------------------------------------------------------------
216 * Environment Variable setup
217 */
218 #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* starting right at the beginning */
219 #define CONFIG_ENV_IS_IN_FLASH 1
220 #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
221 #define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
222 #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
223
224 /*-----------------------------------------------------------------------
225 * External Bus Controller (EBC) Setup
226 */
227 #define FLASH0_BA CONFIG_SYS_FLASH_BASE /* FLASH 0 Base Address */
228
229 /* Memory Bank 0 (Flash Bank 0) initialization */
230 #define CONFIG_SYS_EBC_PB0AP 0x92015480
231 #define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
232
233 /*-----------------------------------------------------------------------
234 * Definitions for initial stack pointer and data area (in data cache)
235 */
236
237 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
238 #define CONFIG_SYS_TEMP_STACK_OCM 1
239
240 /* On Chip Memory location */
241 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
242 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
243
244 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
245 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
246 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
247 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
248
249 /*-----------------------------------------------------------------------
250 * Definitions for Serial Presence Detect EEPROM address
251 * (to get SDRAM settings)
252 */
253 #define SPD_EEPROM_ADDRESS 0x50
254 #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
255
256 #endif /* __CONFIG_H */