include/configs/socfpga_cyclone5.h

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 #include <asm/arch/socfpga_base_addrs.h>
  10 #include "../../board/altera/socfpga/pinmux_config.h"
  11
  12 /*
  13  * High level configuration
  14  */
  15 /* Virtual target or real hardware */
  16 #define CONFIG_SOCFPGA_VIRTUAL_TARGET
  17
  18 #define CONFIG_ARMV7
  19 #define CONFIG_L2_OFF
  20 #define CONFIG_SYS_DCACHE_OFF
  21 #undef CONFIG_USE_IRQ
  22
  23 #define CONFIG_MISC_INIT_R
  24 #define CONFIG_SINGLE_BOOTLOADER
  25 #define CONFIG_SOCFPGA
  26
  27 /* base address for .text section */
  28 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  29 #define CONFIG_SYS_TEXT_BASE            0x08000040
  30 #else
  31 #define CONFIG_SYS_TEXT_BASE            0x01000040
  32 #endif
  33 #define CONFIG_SYS_LOAD_ADDR            0x7fc0
  34
  35 /* Console I/O Buffer Size */
  36 #define CONFIG_SYS_CBSIZE               256
  37 /* Monitor Command Prompt */
  38 #define CONFIG_SYS_PROMPT               "SOCFPGA_CYCLONE5 # "
  39 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  40                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  41
  42 /*
  43  * Display CPU and Board Info
  44  */
  45 #define CONFIG_DISPLAY_CPUINFO
  46 #define CONFIG_DISPLAY_BOARDINFO
  47
  48 /*
  49  * Enable early stage initialization at C environment
  50  */
  51 #define CONFIG_BOARD_EARLY_INIT_F
  52
  53 /* flat device tree */
  54 #define CONFIG_OF_LIBFDT
  55 /* skip updating the FDT blob */
  56 #define CONFIG_FDT_BLOB_SKIP_UPDATE
  57 /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
  58 #define CONFIG_SYS_BOOTMAPSZ            ((256*1024*1024) - (4*1024))
  59
  60 #define CONFIG_SPL_RAM_DEVICE
  61 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
  62 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
  63 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
  64
  65 /*
  66  * Memory allocation (MALLOC)
  67  */
  68 /* Room required on the stack for the environment data */
  69 #define CONFIG_ENV_SIZE                 1024
  70 /* Size of DRAM reserved for malloc() use */
  71 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128*1024)
  72
  73 /* SP location before relocation, must use scratch RAM */
  74 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  75 /* Reserving 0x100 space at back of scratch RAM for debug info */
  76 #define CONFIG_SYS_INIT_RAM_SIZE        (0x10000 - 0x100)
  77 /* Stack pointer prior relocation, must situated at on-chip RAM */
  78 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
  79                                          CONFIG_SYS_INIT_RAM_SIZE - \
  80                                          GENERATED_GBL_DATA_SIZE)
  81
  82
  83 /*
  84  * Command line configuration.
  85  */
  86 #define CONFIG_SYS_NO_FLASH
  87 #include <config_cmd_default.h>
  88 /* FAT file system support */
  89 #define CONFIG_CMD_FAT
  90
  91
  92 /*
  93  * Misc
  94  */
  95 #define CONFIG_DOS_PARTITION            1
  96
  97 #ifdef CONFIG_SPL_BUILD
  98 #undef CONFIG_PARTITIONS
  99 #endif
 100
 101 /*
 102  * Environment setup
 103  */
 104
 105 /* Delay before automatically booting the default image */
 106 #define CONFIG_BOOTDELAY                3
 107 /* Enable auto completion of commands using TAB */
 108 #define CONFIG_AUTO_COMPLETE
 109 /* use "hush" command parser */
 110 #define CONFIG_SYS_HUSH_PARSER
 111 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 112 #define CONFIG_CMD_RUN
 113
 114 #define CONFIG_BOOTCOMMAND "run ramboot"
 115
 116 /*
 117  * arguments passed to the bootm command. The value of
 118  * CONFIG_BOOTARGS goes into the environment value "bootargs".
 119  * Do note the value will overide also the chosen node in FDT blob.
 120  */
 121 #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
 122
 123 #define CONFIG_EXTRA_ENV_SETTINGS \
 124         "verify=n\0" \
 125         "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 126         "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 127                 "bootm ${loadaddr} - ${fdt_addr}\0" \
 128         "bootimage=uImage\0" \
 129         "fdt_addr=100\0" \
 130         "fsloadcmd=ext2load\0" \
 131                 "bootm ${loadaddr} - ${fdt_addr}\0" \
 132         "qspiroot=/dev/mtdblock0\0" \
 133         "qspirootfstype=jffs2\0" \
 134         "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
 135                 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 136                 "bootm ${loadaddr} - ${fdt_addr}\0"
 137
 138 /* using environment setting for stdin, stdout, stderr */
 139 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 140 /* Enable the call to overwrite_console() */
 141 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 142 /* Enable overwrite of previous console environment settings */
 143 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 144
 145 /* max number of command args    */
 146 #define CONFIG_SYS_MAXARGS              16
 147
 148
 149 /*
 150  * Hardware drivers
 151  */
 152
 153 /*
 154  * SDRAM Memory Map
 155  */
 156 /* We have 1 bank of DRAM */
 157 #define CONFIG_NR_DRAM_BANKS            1
 158 /* SDRAM Bank #1 */
 159 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 160 /* SDRAM memory size */
 161 #define PHYS_SDRAM_1_SIZE               0x40000000
 162
 163 #define PHYS_SDRAM_1                    CONFIG_SYS_SDRAM_BASE
 164 #define CONFIG_SYS_MEMTEST_START        0x00000000
 165 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
 166
 167 /*
 168  * NS16550 Configuration
 169  */
 170 #define UART0_BASE                      SOCFPGA_UART0_ADDRESS
 171 #define CONFIG_SYS_NS16550
 172 #define CONFIG_SYS_NS16550_SERIAL
 173 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 174 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
 175 #define CONFIG_CONS_INDEX               1
 176 #define CONFIG_SYS_NS16550_COM1         UART0_BASE
 177 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
 178 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 179 #define V_NS16550_CLK                   1000000
 180 #else
 181 #define V_NS16550_CLK                   100000000
 182 #endif
 183 #define CONFIG_BAUDRATE                 115200
 184
 185 /*
 186  * FLASH
 187  */
 188 #define CONFIG_SYS_NO_FLASH
 189
 190 /*
 191  * L4 OSC1 Timer 0
 192  */
 193 /* This timer use eosc1 where the clock frequency is fixed
 194  * throughout any condition */
 195 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 196 /* reload value when timer count to zero */
 197 #define TIMER_LOAD_VAL                  0xFFFFFFFF
 198 /* Timer info */
 199 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 200 #define CONFIG_TIMER_CLOCK_KHZ          2400
 201 #else
 202 #define CONFIG_TIMER_CLOCK_KHZ          25000
 203 #endif
 204
 205 #define CONFIG_ENV_IS_NOWHERE
 206
 207 /*
 208  * SPL "Second Program Loader" aka Initial Software
 209  */
 210
 211 /* Enable building of SPL globally */
 212 #define CONFIG_SPL
 213 #define CONFIG_SPL_FRAMEWORK
 214
 215 /* TEXT_BASE for linking the SPL binary */
 216 #define CONFIG_SPL_TEXT_BASE            0xFFFF0000
 217
 218 /* Stack size for SPL */
 219 #define CONFIG_SPL_STACK_SIZE           (4 * 1024)
 220
 221 /* MALLOC size for SPL */
 222 #define CONFIG_SPL_MALLOC_SIZE          (5 * 1024)
 223
 224 #define CONFIG_SPL_SERIAL_SUPPORT
 225 #define CONFIG_SPL_BOARD_INIT
 226
 227 #define CHUNKSZ_CRC32                   (1 * 1024)
 228
 229 #define CONFIG_CRC32_VERIFY
 230
 231 /* Linker script for SPL */
 232 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
 233
 234 /* Support for common/libcommon.o in SPL binary */
 235 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 236 /* Support for lib/libgeneric.o in SPL binary */
 237 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 238
 239 #endif  /* __CONFIG_H */