include/configs/t4qds.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __T4QDS_H
  11 #define __T4QDS_H
  12
  13 #define CONFIG_CMD_REGINFO
  14
  15 /* High Level Configuration Options */
  16 #define CONFIG_BOOKE
  17 #define CONFIG_E500                     /* BOOKE e500 family */
  18 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  19 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  20 #define CONFIG_MPC85xx                  /* MPC85xx/PQ3 platform */
  21 #define CONFIG_MP                       /* support multiple processors */
  22
  23 #ifndef CONFIG_SYS_TEXT_BASE
  24 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  25 #endif
  26
  27 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  29 #endif
  30
  31 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  32 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  33 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  34 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  35 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  36 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  37 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  38 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  39 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  40
  41 #define CONFIG_SYS_SRIO
  42 #define CONFIG_SRIO1                    /* SRIO port 1 */
  43 #define CONFIG_SRIO2                    /* SRIO port 2 */
  44
  45 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  46
  47 #define CONFIG_ENV_OVERWRITE
  48
  49 /*
  50  * These can be toggled for performance analysis, otherwise use default.
  51  */
  52 #define CONFIG_SYS_CACHE_STASHING
  53 #define CONFIG_BTB                      /* toggle branch predition */
  54 #ifdef CONFIG_DDR_ECC
  55 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  56 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  57 #endif
  58
  59 #define CONFIG_ENABLE_36BIT_PHYS
  60
  61 #define CONFIG_ADDR_MAP
  62 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  63
  64 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  65 #define CONFIG_SYS_MEMTEST_END          0x00400000
  66 #define CONFIG_SYS_ALT_MEMTEST
  67 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  68
  69 /*
  70  *  Config the L3 Cache as L3 SRAM
  71  */
  72 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  73
  74 #define CONFIG_SYS_DCSRBAR              0xf0000000
  75 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  76
  77 /*
  78  * DDR Setup
  79  */
  80 #define CONFIG_VERY_BIG_RAM
  81 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  82 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  83
  84 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
  85 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  86 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  87 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  88
  89 #define CONFIG_DDR_SPD
  90 #define CONFIG_FSL_DDR3
  91
  92
  93 /*
  94  * IFC Definitions
  95  */
  96 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  97 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  98
  99
 100 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 101
 102 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 103 #define CONFIG_MISC_INIT_R
 104
 105 #define CONFIG_HWCONFIG
 106
 107 /* define to use L1 as initial stack */
 108 #define CONFIG_L1_INIT_RAM
 109 #define CONFIG_SYS_INIT_RAM_LOCK
 110 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 111 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 112 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 113 /* The assembler doesn't like typecast */
 114 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 115         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 116           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 117 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 118
 119 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 120                                         GENERATED_GBL_DATA_SIZE)
 121 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 122
 123 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 124 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 125
 126 /* Serial Port - controlled on board with jumper J8
 127  * open - index 2
 128  * shorted - index 1
 129  */
 130 #define CONFIG_CONS_INDEX       1
 131 #define CONFIG_SYS_NS16550
 132 #define CONFIG_SYS_NS16550_SERIAL
 133 #define CONFIG_SYS_NS16550_REG_SIZE     1
 134 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 135
 136 #define CONFIG_SYS_BAUDRATE_TABLE       \
 137         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 138
 139 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 140 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 141 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 142 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 143
 144 /* Use the HUSH parser */
 145 #define CONFIG_SYS_HUSH_PARSER
 146 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 147
 148 /* pass open firmware flat tree */
 149 #define CONFIG_OF_LIBFDT
 150 #define CONFIG_OF_BOARD_SETUP
 151 #define CONFIG_OF_STDOUT_VIA_ALIAS
 152
 153 /* new uImage format support */
 154 #define CONFIG_FIT
 155 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 156
 157 /* I2C */
 158 #define CONFIG_SYS_I2C
 159 #define CONFIG_SYS_I2C_FSL
 160 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 161 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 162 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 163 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 164
 165 /*
 166  * RapidIO
 167  */
 168 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 169 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 170 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 171
 172 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 173 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 174 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 175
 176 /*
 177  * General PCI
 178  * Memory space is mapped 1-1, but I/O space must start from 0.
 179  */
 180
 181 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 182 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 183 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 184 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 185 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 186 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 187 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 188 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 189 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 190
 191 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 192 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 193 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 194 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 195 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 196 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 197 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 198 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 199 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 200
 201 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 202 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 203 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 204 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 205 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 206 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 207 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 208 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 209 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 210
 211 /* controller 4, Base address 203000 */
 212 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 213 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 214 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 215 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 216 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 217 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 218
 219 #ifdef CONFIG_PCI
 220 #define CONFIG_PCI_INDIRECT_BRIDGE
 221 #define CONFIG_NET_MULTI
 222 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 223 #define CONFIG_E1000
 224
 225 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 226 #define CONFIG_DOS_PARTITION
 227 #endif  /* CONFIG_PCI */
 228
 229 /* SATA */
 230 #ifdef CONFIG_FSL_SATA_V2
 231 #define CONFIG_LIBATA
 232 #define CONFIG_FSL_SATA
 233
 234 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 235 #define CONFIG_SATA1
 236 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 237 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 238 #define CONFIG_SATA2
 239 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 240 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 241
 242 #define CONFIG_LBA48
 243 #define CONFIG_CMD_SATA
 244 #define CONFIG_DOS_PARTITION
 245 #define CONFIG_CMD_EXT2
 246 #endif
 247
 248 #ifdef CONFIG_FMAN_ENET
 249 #define CONFIG_MII              /* MII PHY management */
 250 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 251 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 252 #endif
 253
 254 /*
 255  * Environment
 256  */
 257 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 258 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 259
 260 /*
 261  * Command line configuration.
 262  */
 263 #include <config_cmd_default.h>
 264
 265 #define CONFIG_CMD_DHCP
 266 #define CONFIG_CMD_ELF
 267 #define CONFIG_CMD_ERRATA
 268 #define CONFIG_CMD_GREPENV
 269 #define CONFIG_CMD_IRQ
 270 #define CONFIG_CMD_I2C
 271 #define CONFIG_CMD_MII
 272 #define CONFIG_CMD_PING
 273 #define CONFIG_CMD_SETEXPR
 274
 275 #ifdef CONFIG_PCI
 276 #define CONFIG_CMD_PCI
 277 #define CONFIG_CMD_NET
 278 #endif
 279
 280 /*
 281  * Miscellaneous configurable options
 282  */
 283 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 284 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 285 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 286 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 287 #ifdef CONFIG_CMD_KGDB
 288 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 289 #else
 290 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 291 #endif
 292 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 293 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 294 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 295
 296 /*
 297  * For booting Linux, the board info and command line data
 298  * have to be in the first 64 MB of memory, since this is
 299  * the maximum mapped by the Linux kernel during initialization.
 300  */
 301 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 302 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 303
 304 #ifdef CONFIG_CMD_KGDB
 305 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 306 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 307 #endif
 308
 309 /*
 310  * Environment Configuration
 311  */
 312 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 313 #define CONFIG_BOOTFILE         "uImage"
 314 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 315
 316 /* default location for tftp and bootm */
 317 #define CONFIG_LOADADDR         1000000
 318
 319
 320 #define CONFIG_BAUDRATE 115200
 321
 322 #define CONFIG_HVBOOT                           \
 323  "setenv bootargs config-addr=0x60000000; "     \
 324  "bootm 0x01000000 - 0x00f00000"
 325
 326 #endif  /* __CONFIG_H */