gcplus SA1100
Wolfgang Denk <wd@denx.de>
+ imx27lite i.MX27
qong i.MX31
Thomas Elste <info@elste.org>
omap1610h2 ARM926EJS
+Frederik Kriewitz <frederik@kriewitz.eu>
+
+ devkit8000 ARM CORTEX-A8 (OMAP3530 SoC)
+
Sergey Kubushyn <ksi@koi8.net>
DV-EVM ARM926EJS
B2 ARM7TDMI (S3C44B0X)
+Albin Tonnerre <albin.tonnerre@free-electrons.com>
+
+ sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC)
+ tny_a9260 ARM926EJS (AT91SAM9260 SoC)
+ tny_a9g20 ARM926EJS (AT91SAM9G20 SoC)
+
Greg Ungerer <greg.ungerer@opengear.com>
cm4008 ks8695p
cp926ejs \
cp946es \
cp966 \
+ imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
mx1ads \
## ARM Cortex-A8 Systems
#########################################################################
LIST_ARM_CORTEX_A8=" \
+ devkit8000 \
omap3_beagle \
omap3_overo \
omap3_evm \
m501sk \
pm9261 \
pm9263 \
+ SBC35_A9G20 \
+ TNY_A9260 \
+ TNY_A9G20 \
"
#########################################################################
pm9263_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
+SBC35_A9G20_NANDFLASH_config \
+SBC35_A9G20_EEPROM_config \
+SBC35_A9G20_config : unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
+ @$(MKCONFIG) -a sbc35_a9g20 arm arm926ejs sbc35_a9g20 calao at91
+
+TNY_A9G20_NANDFLASH_config \
+TNY_A9G20_EEPROM_config \
+TNY_A9G20_config \
+TNY_A9260_NANDFLASH_config \
+TNY_A9260_EEPROM_config \
+TNY_A9260_config : unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
+ @$(MKCONFIG) -a tny_a9260 arm arm926ejs tny_a9260 calao at91
+
########################################################################
## ARM Integrator boards - see doc/README-integrator for more info.
integratorap_config \
davinci_dm355evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm355evm davinci davinci
+davinci_dm365evm_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs dm365evm davinci davinci
+
+imx27lite_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
+
lpd7a400_config \
lpd7a404_config: unconfig
@$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x
@$(MKCONFIG) -a nhk8815 arm arm926ejs nhk8815 st nomadik
omap1510inn_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
+ @$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn ti
xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))
echo "#define CONFIG_CS3_BOOT" >> $(obj)include/config.h ; \
$(XECHO) "... configured for CS3 boot"; \
fi;
- @$(MKCONFIG) -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap
+ @$(MKCONFIG) -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn ti omap
omap5912osk_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk ti omap
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
echo "#define CONFIG_CS3_BOOT" >> $(obj)include/config.h ; \
$(XECHO) "... configured for CS3 boot"; \
fi;
- @$(MKCONFIG) -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
+ @$(MKCONFIG) -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 ti omap
rd6281a_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
## ARM CORTEX Systems
#########################################################################
+devkit8000_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
+
omap3_beagle_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle omap3 omap3
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle ti omap3
omap3_overo_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo omap3 omap3
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo NULL omap3
omap3_evm_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm omap3 omap3
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm ti omap3
omap3_pandora_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora omap3 omap3
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora NULL omap3
omap3_zoom1_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 omap3 omap3
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 logicpd omap3
omap3_zoom2_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 omap3 omap3
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
#########################################################################
## XScale Systems
@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
imx31_litekit_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
+ @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit logicpd mx31
imx31_phycore_eet_config \
imx31_phycore_config : unconfig
@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
omap2420h4_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
+ @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
qong_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 qong davedenx mx31
#ifdef CONFIG_CMD_NAND
afeb9260_nand_hw_init();
#endif
- at91_spi0_hw_init((1 << 0) || (1 << 1));
+ at91_spi0_hw_init((1 << 0) | (1 << 1));
#ifdef CONFIG_MACB
afeb9260_macb_hw_init();
#endif
at91sam9260ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
- at91_spi0_hw_init((1 << 0) || (1 << 1));
+ at91_spi0_hw_init((1 << 0) | (1 << 1));
#endif
#ifdef CONFIG_MACB
at91sam9260ek_macb_hw_init();
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += sbc35_a9g20.o
+COBJS-$(CONFIG_ATMEL_SPI) += spi.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x23f00000
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void sbc35_a9g20_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_DBW_8 |
+#endif
+ AT91_SMC_TDF_(2));
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void sbc35_a9g20_macb_hw_init(void)
+{
+ unsigned long rstc;
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+ rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
+ /* Need to reset PHY -> 500ms reset */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ (AT91_RSTC_ERSTL & (0x0D << 8)) |
+ AT91_RSTC_URSTEN);
+
+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+ /* Wait for end hardware reset */
+ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+ /* Restore NRST value */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ (rstc) |
+ AT91_RSTC_URSTEN);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+ at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91_serial_hw_init();
+ sbc35_a9g20_nand_hw_init();
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 4 | 1 << 5);
+#endif
+#ifdef CONFIG_MACB
+ sbc35_a9g20_macb_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
+ return -1;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
--- /dev/null
+/*
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/gpio.h>
+#include <spi.h>
+
+#define SBC_A9260_CS0_PIN AT91_PIN_PA3
+#define SBC_A9260_CS1_PIN AT91_PIN_PC11
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && (cs == 1 || cs == 0);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ if(slave->cs == 0)
+ at91_set_gpio_value(SBC_A9260_CS0_PIN, 0);
+ else if(slave->cs == 1)
+ at91_set_gpio_value(SBC_A9260_CS1_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ if(slave->cs == 0)
+ at91_set_gpio_value(SBC_A9260_CS0_PIN, 1);
+ else if(slave->cs == 1)
+ at91_set_gpio_value(SBC_A9260_CS1_PIN, 1);
+}
+
+void spi_init_f(void)
+{
+ /* everything done in board_init */
+}
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += tny_a9260.o
+COBJS-$(CONFIG_ATMEL_SPI) += spi.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x23f00000
--- /dev/null
+/*
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/gpio.h>
+#include <spi.h>
+
+#define TNY_A9260_CS_PIN AT91_PIN_PC11
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TNY_A9260_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TNY_A9260_CS_PIN, 1);
+}
+
+void spi_init_f(void)
+{
+ /* everything done in board_init */
+}
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void tny_a9260_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_DBW_8 |
+#endif
+ AT91_SMC_TDF_(2));
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+#if defined(CONFIG_TNY_A9260)
+ gd->bd->bi_arch_number = MACH_TYPE_TNY_A9260;
+#elif defined(CONFIG_TNY_A9G20)
+ gd->bd->bi_arch_number = MACH_TYPE_TNY_A9G20;
+#endif
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91_serial_hw_init();
+ tny_a9260_nand_hw_init();
+ at91_spi0_hw_init(1 << 5);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
+ return -1;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Spectrum Digital DM365 EVM board
+# DM365 EVM board has 1 bank of 128 MB DDR RAM
+# Physical Address: 8000'0000 to 8800'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000
--- /dev/null
+/*
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <linux/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/nand_defs.h>
+#include "../common/misc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_NAND_DAVINCI
+static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *this = mtd->priv;
+ u32 wbase = (u32) this->IO_ADDR_W;
+ u32 rbase = (u32) this->IO_ADDR_R;
+
+ if (chip == 1) {
+ __set_bit(14, &wbase);
+ __set_bit(14, &rbase);
+ } else {
+ __clear_bit(14, &wbase);
+ __clear_bit(14, &rbase);
+ }
+ this->IO_ADDR_W = (void *)wbase;
+ this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+ nand->select_chip = nand_dm365evm_select_chip;
+ return 0;
+}
+#endif
--- /dev/null
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := imx27lite.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
--- /dev/null
+TEXT_BASE = 0xA7F00000
--- /dev/null
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+
+ gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#ifdef CONFIG_MXC_UART
+ mx27_uart_init_pins();
+#endif
+#ifdef CONFIG_FEC_MXC
+ mx27_fec_init_pins();
+ imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
+ writel(readl(®s->port[PORTC].dr) | (1 << 31),
+ ®s->port[PORTC].dr);
+#endif
+#ifdef CONFIG_MXC_MMC
+ mx27_sd2_init_pins();
+#endif
+
+ return 0;
+}
+
+int dram_init (void)
+{
+
+#if CONFIG_NR_DRAM_BANKS > 0
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+#endif
+#if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("LogicPD imx27lite\n");
+ return 0;
+}
--- /dev/null
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
+ * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
+SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
+SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
+SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
+SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
+ ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
+ ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
+ ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
+
+.macro init_aipi
+ /*
+ * setup AIPI1 and AIPI2
+ */
+ write32 AIPI1_PSR0, AIPI1_PSR0_VAL
+ write32 AIPI1_PSR1, AIPI1_PSR1_VAL
+ write32 AIPI2_PSR0, AIPI2_PSR0_VAL
+ write32 AIPI2_PSR1, AIPI2_PSR1_VAL
+
+.endm /* init_aipi */
+
+.macro init_clock
+ ldr r0, =CSCR
+ /* disable MPLL/SPLL first */
+ ldr r1, [r0]
+ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
+ str r1, [r0]
+
+ write32 MPCTL0, MPCTL0_VAL
+ write32 SPCTL0, SPCTL0_VAL
+
+ write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
+
+ /*
+ * add some delay here
+ */
+ wait_timer 0x1000
+
+ /* peripheral clock divider */
+ write32 PCDR0, PCDR0_VAL
+ write32 PCDR1, PCDR1_VAL
+
+ /* Configure PCCR0 and PCCR1 */
+ write32 PCCR0, PCCR0_VAL
+ write32 PCCR1, PCCR1_VAL
+
+.endm /* init_clock */
+
+.macro sdram_init
+ ldr r0, SOC_ESDCTL_BASE_W
+ mov r2, #PHYS_SDRAM_1
+
+ /* Do initial reset */
+ mov r1, #ESDMISC_MDDR_DL_RST
+ str r1, [r0, #ESDMISC_ROF]
+
+ /* Hold for more than 200ns */
+ wait_timer 0x10000
+
+ /* Activate LPDDR iface */
+ mov r1, #ESDMISC_MDDREN
+ str r1, [r0, #ESDMISC_ROF]
+
+ /* Check The chip version TO1 or TO2 */
+ ldr r1, SOC_SI_ID_REG_W
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+ /* add Latency on CAS only for TO2 */
+ ldreq r1, SDRAM_ESDCFG_T2_W
+ ldrne r1, SDRAM_ESDCFG_T1_W
+ str r1, [r0, #ESDCFG0_ROF]
+
+ /* Run initialization sequence */
+ ldr r1, SDRAM_PRECHARGE_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_AUTOREF_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_LOADMODE_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+ ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+ add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r1, [r3]
+
+ ldr r1, SDRAM_NORMAL_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+
+#if (CONFIG_NR_DRAM_BANKS > 1)
+ /* 2nd sdram */
+ mov r2, #PHYS_SDRAM_2
+
+ /* Check The chip version TO1 or TO2 */
+ ldr r1, SOC_SI_ID_REG_W
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+ /* add Latency on CAS only for TO2 */
+ ldreq r1, SDRAM_ESDCFG_T2_W
+ ldrne r1, SDRAM_ESDCFG_T1_W
+ str r1, [r0, #ESDCFG1_ROF]
+
+ /* Run initialization sequence */
+ ldr r1, SDRAM_PRECHARGE_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_AUTOREF_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_LOADMODE_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+ ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+ add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r1, [r3]
+
+ ldr r1, SDRAM_NORMAL_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+#endif /* CONFIG_NR_DRAM_BANKS > 1 */
+
+.endm /* sdram_init */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ init_aipi
+
+ init_clock
+
+ sdram_init
+
+ mov pc,r10
return 0;
}
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
+
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009
+# Frederik Kriewitz <frederik@kriewitz.eu>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := devkit8000.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# (C) Copyright 2009
+# Frederik Kriewitz <frederik@kriewitz.eu>
+#
+# DevKit8000 uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
--- /dev/null
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/mach-types.h>
+#include "devkit8000.h"
+#ifdef CONFIG_DRIVER_DM9000
+#include <net.h>
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+#ifdef CONFIG_DRIVER_DM9000
+ uchar enetaddr[6];
+ u32 die_id_0;
+#endif
+
+ twl4030_power_init();
+#ifdef CONFIG_TWL4030_LED
+ twl4030_led_init();
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+ /* Configure GPMC registers for DM9000 */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[6].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[6].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[6].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[6].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[6].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[6].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[6].config7);
+
+ /* Use OMAP DIE_ID as MAC address */
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ printf("ethaddr not set, using Die ID\n");
+ die_id_0 = readl(&id_base->die_id_0);
+ enetaddr[0] = 0x02; /* locally administered */
+ enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
+ enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
+ enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
+ enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
+ enetaddr[5] = (die_id_0 & 0x000000ff);
+ eth_setenv_enetaddr("ethaddr", enetaddr);
+ }
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DEVKIT8000();
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+/*
+ * Routine: board_eth_init
+ * Description: Setting up the Ethernet hardware.
+ */
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DEVKIT8000_H_
+#define _DEVKIT8000_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 DevKit8000",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+#define MUX_DEVKIT8000() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0 NAND*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6 DM9000*/\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /* Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /* MMC Slot */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+ /* Expansion Header */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
+ MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*GPIO_148*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*GPIO_151*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*GPIO_152*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*GPIO_153*/\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*GPIO_154*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*GPIO_155*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*GPIO_160*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /* Serial Interface */\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | EN | M4)) /*GPIO_163 - LED2*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164 - LED3*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ /* Host USB0 */\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IDIS | PTU | DIS | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | DIS | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | DIS | M0)) /*MCSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | EN | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | EN | M4)) /*GPIO_186 - LED1*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | EN | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTU | EN | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | EN | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | EN | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /*GPIO_29*/\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*D2D_MCAD1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*D2D_MCAD2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*D2D_MCAD3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*D2D_MCAD4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*D2D_MCAD5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*D2D_MCAD6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*D2D_MCAD7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*D2D_MCAD8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*D2D_MCAD9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*D2D_MCAD10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*D2D_MCAD11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*D2D_MCAD12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*D2D_MCAD13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*D2D_MCAD14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*D2D_MCAD15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*D2D_MCAD16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*D2D_MCAD17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*D2D_MCAD18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*D2D_MCAD19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*D2D_MCAD20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*D2D_MCAD21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*D2D_MCAD22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*D2D_MCAD23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*D2D_MCAD24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*D2D_MCAD25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*D2D_MCAD26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*D2D_MCAD27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*D2D_MCAD28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*D2D_MCAD29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*D2D_MCAD30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*D2D_MCAD31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*D2D_MCAD32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*D2D_MCAD33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*D2D_MCAD34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*D2D_MCAD35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*D2D_MCAD36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*D2D_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*D2D_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*D2D_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*D2D_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*D2D_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*D2D_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*D2D_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*D2D_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*D2D_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*D2D_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*D2D_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*D2D_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*D2D_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*D2D_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*D2D_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*D2D_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*D2D_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*D2D_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*D2D_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*D2D_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*D2D_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*D2D_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*D2D_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*D2D_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+
+#endif
#endif
}
-#ifdef CONFIG_HAS_DATAFLASH
+#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
COBJS-y += cpu.o timer.o psc.o
COBJS-$(CONFIG_SOC_DM355) += dm355.o
+COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o
--- /dev/null
+/*
+ * SoC-specific code for tms320dm365 and similar chips
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+void davinci_enable_uart0(void)
+{
+ lpsc_on(DAVINCI_LPSC_UART0);
+}
+
+#ifdef CONFIG_DRIVER_DAVINCI_I2C
+void davinci_enable_i2c(void)
+{
+ lpsc_on(DAVINCI_LPSC_I2C);
+}
+#endif
return 0;
}
+/*
+ * SYSRSTn Duration Counter Support
+ *
+ * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
+ * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
+ * The SYSRSTn duration counter is useful for implementing a manufacturer
+ * or factory reset. Upon a long reset assertion that is greater than a
+ * pre-configured environment variable value for sysrstdelay,
+ * The counter value is stored in the SYSRSTn Length Counter Register
+ * The counter is based on the 25-MHz reference clock (40ns)
+ * It is a 29-bit counter, yielding a maximum counting duration of
+ * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
+ * it remains at this value until counter reset is triggered by setting
+ * bit 31 of KW_REG_SYSRST_CNT
+ */
+static void kw_sysrst_action(void)
+{
+ int ret;
+ char *s = getenv("sysrstcmd");
+
+ if (!s) {
+ debug("Error.. %s failed, check sysrstcmd\n",
+ __FUNCTION__);
+ return;
+ }
+
+ debug("Starting %s process...\n", __FUNCTION__);
+#if !defined(CONFIG_SYS_HUSH_PARSER)
+ ret = run_command (s, 0);
+#else
+ ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON
+ | FLAG_EXIT_FROM_LOOP);
+#endif
+ if (ret < 0)
+ debug("Error.. %s failed\n", __FUNCTION__);
+ else
+ debug("%s process finished\n", __FUNCTION__);
+}
+
+static void kw_sysrst_check(void)
+{
+ u32 sysrst_cnt, sysrst_dly;
+ char *s;
+
+ /*
+ * no action if sysrstdelay environment variable is not defined
+ */
+ s = getenv("sysrstdelay");
+ if (s == NULL)
+ return;
+
+ /* read sysrstdelay value */
+ sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
+
+ /* read SysRst Length counter register (bits 28:0) */
+ sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
+ debug("H/w Rst hold time: %d.%d secs\n",
+ sysrst_cnt / SYSRST_CNT_1SEC_VAL,
+ sysrst_cnt % SYSRST_CNT_1SEC_VAL);
+
+ /* clear the counter for next valid read*/
+ writel(1 << 31, KW_REG_SYSRST_CNT);
+
+ /*
+ * sysrst_action:
+ * if H/w Reset key is pressed and hold for time
+ * more than sysrst_dly in seconds
+ */
+ if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
+ kw_sysrst_action();
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
temp = get_cr();
set_cr(temp & ~CR_V);
+ /* checks and execute resset to factory event */
+ kw_sysrst_check();
+
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
®s->port[port].iconfb2);
}
}
+
+#ifdef CONFIG_MXC_UART
+void mx27_uart_init_pins(void)
+{
+ int i;
+ unsigned int mode[] = {
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mode); i++)
+ imx_gpio_mode(mode[i]);
+
+}
+#endif /* CONFIG_MXC_UART */
+
+#ifdef CONFIG_FEC_MXC
+void mx27_fec_init_pins(void)
+{
+ int i;
+ unsigned int mode[] = {
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC | GPIO_PUEN,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_CLR,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mode); i++)
+ imx_gpio_mode(mode[i]);
+}
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_MXC_MMC
+void mx27_sd2_init_pins(void)
+{
+ int i;
+ unsigned int mode[] = {
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mode); i++)
+ imx_gpio_mode(mode[i]);
+
+}
+#endif /* CONFIG_MXC_MMC */
+
--- /dev/null
+DevKit8000
+==========
+
+The OMAP3 DevKit8000 from Embest/Timll is a clone of the OMAP3 beagle board
+with Ethernet and Touch Screen controller on board.
+
+For more information go to:
+http://www.embedinfo.com/English/Product/devkit8000.asp
+
+There's no real MAC address available.
+If ethaddr is not set, 5 Bytes of the OMAP Die ID will be used.
+
+Build:
+make devkit8000_config
+make
((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
+#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
+#define SYSRST_CNT_1SEC_VAL (25*1000000)
#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
enum memory_bank {
extern void imx_gpio_mode (int gpio_mode);
+#ifdef CONFIG_MXC_UART
+extern void mx27_uart_init_pins(void);
+#endif /* CONFIG_MXC_UART */
+
+#ifdef CONFIG_FEC_MXC
+extern void mx27_fec_init_pins(void);
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_MXC_MMC
+extern void mx27_sd2_init_pins(void);
+#endif /* CONFIG_MXC_MMC */
+
/* AIPI */
struct aipi_regs {
u32 psr0;
#include <linux/config.h>
-#define set_cr(x) \
- __asm__ __volatile__( \
- "mcr p15, 0, %0, c1, c0 @ set CR" \
- : : "r" (x))
-
-#define CR_M (1 << 0) /* MMU enable */
-#define CR_A (1 << 1) /* Alignment abort enable */
-#define CR_C (1 << 2) /* Dcache enable */
-#define CR_W (1 << 3) /* Write buffer enable */
-#define CR_P (1 << 4) /* 32-bit exception handler */
-#define CR_D (1 << 5) /* 32-bit data address range */
-#define CR_L (1 << 6) /* Implementation defined */
-#define CD_B (1 << 7) /* Big endian */
-#define CR_S (1 << 8) /* System MMU protection */
-#define CD_R (1 << 9) /* ROM MMU protection */
-#define CR_F (1 << 10) /* Implementation defined */
-#define CR_Z (1 << 11) /* Implementation defined */
-#define CR_I (1 << 12) /* Icache enable */
-#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
-#define CR_RR (1 << 14) /* Round Robin cache replacement */
-
-extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
-extern unsigned long cr_alignment; /* defined in entry-armv.S */
-
-#if __LINUX_ARM_ARCH__ >= 4
-#define vectors_base() ((cr_alignment & CR_V) ? 0xffff0000 : 0)
-#else
-#define vectors_base() (0)
-#endif
-
/*
* Save the current interrupt enable state & disable IRQs
*/
--- /dev/null
+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/* Spectrum Digital TMS320DM365 EVM board */
+#define DAVINCI_DM365EVM
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS /* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SOC_DM365
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE SZ_128M
+
+/* Serial Driver info: UART0 for console */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 0x01c20000
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* EEPROM definitions for EEPROM on DM365 EVM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 2
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SAVEENV
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "DM365 EVM # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE SZ_256K
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x3C0000
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTCOMMAND \
+ "dhcp;bootm"
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200n8 " \
+ "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* U-Boot memory configuration */
+#define CONFIG_STACKSIZE SZ_256K /* regular stack */
+#define CONFIG_SYS_MALLOC_LEN SZ_1M /* malloc() arena */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
+#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
+#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
+
+
+/* NAND configuration issocketed with two chipselects just like the DM355 EVM.
+ * It normally comes with a 2GByte SLC part with 2KB pages
+ * (and 128KB erase blocks); other
+ * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
+ * pretty much demands the 4-bit ECC support.) You can of course swap in
+ * other parts, including small page ones.
+ */
+#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+/* Use same layout for 128K/256K blocks; allow some bad blocks */
+#define PART_BOOT "2m(bootloader)ro,"
+#else
+/* Assume 16K erase blocks; allow a few bad ones. */
+#define PART_BOOT "512k(bootloader)ro,"
+#endif
+
+#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
+#define PART_REST "-(filesystem)"
+
+#define MTDPARTS_DEFAULT \
+ "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * Configuration settings for the DevKit8000 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Display CPU and Board information */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/* Size of malloc() pool */
+#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
+ /* initial data */
+
+/* Hardware drivers */
+
+/* DM9000 */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x2c000000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
+#define CONFIG_DM9000_USE_16BIT 1
+#define CONFIG_DM9000_NO_SROM 1
+#undef CONFIG_DM9000_DEBUG
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/* MMC */
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/* TWL4030 */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
+/* Board NAND Info */
+#define CONFIG_SYS_NO_FLASH /* no NOR flash */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:" \
+ "512k(x-loader)," \
+ "1920k(u-boot)," \
+ "128k(u-boot-env)," \
+ "4m(kernel)," \
+ "-(fs)"
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+ /* devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
+ /* partition */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP /* DHCP support */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
+
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+
+/* BOOTP/DHCP options */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+#undef CONFIG_BOOTP_VENDOREX
+
+/* Environment information */
+#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+ "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
+ "kernelopts=rw\0" \
+ "commonargs=" \
+ "setenv bootargs console=${console} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapdss.def_disp=${defaultdisplay}\0" \
+ "mmcargs=" \
+ "run commonargs; " \
+ "setenv bootargs ${bootargs} " \
+ "root=/dev/mmcblk0p2 " \
+ "${kernelopts}\0" \
+ "nandargs=" \
+ "run commonargs; " \
+ "setenv bootargs ${bootargs} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=/dev/mtdblock4 " \
+ "rootfstype=jffs2 " \
+ "${kernelopts}\0" \
+ "netargs=" \
+ "run commonargs; " \
+ "setenv bootargs ${bootargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
+ "${kernelopts} " \
+ "dnsip1=${dnsip} " \
+ "dnsip2=${dnsip2}\0" \
+ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+ "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 280000 400000; " \
+ "bootm ${loadaddr}\0" \
+ "netboot=echo Booting from network ...; " \
+ "dhcp ${loadaddr}; " \
+ "run netargs; " \
+ "bootm ${loadaddr}\0" \
+ "autoboot=if mmc init 0; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi\0"
+
+
+#define CONFIG_BOOTCOMMAND "run autoboot"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ 0x01000000) /* 16MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/* The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE SZ_128K /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE SZ_128M /* at least 128 meg */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/* NAND and environment organization */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
+
+#define CONFIG_ENV_IS_IN_NAND 1
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_ENV_OFFSET boot_flash_off
+
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_MX27
+#define CONFIG_IMX27LITE
+#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Lowlevel configuration
+ */
+#define SDRAM_ESDCFG_REGISTER_VAL(cas) \
+ (ESDCFG_TRC(10) | \
+ ESDCFG_TRCD(3) | \
+ ESDCFG_TCAS(cas) | \
+ ESDCFG_TRRD(1) | \
+ ESDCFG_TRAS(5) | \
+ ESDCFG_TWR | \
+ ESDCFG_TMRD(2) | \
+ ESDCFG_TRP(2) | \
+ ESDCFG_TXP(3))
+
+#define SDRAM_ESDCTL_REGISTER_VAL \
+ (ESDCTL_PRCT(0) | \
+ ESDCTL_BL | \
+ ESDCTL_PWDT(0) | \
+ ESDCTL_SREFR(3) | \
+ ESDCTL_DSIZ_32 | \
+ ESDCTL_COL10 | \
+ ESDCTL_ROW13 | \
+ ESDCTL_SDE)
+
+#define SDRAM_ALL_VAL 0xf00
+
+#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
+#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
+
+#define MPCTL0_VAL 0x1ef15d5
+
+#define SPCTL0_VAL 0x043a1c09
+
+#define CSCR_VAL 0x33f08107
+
+#define PCDR0_VAL 0x120470c3
+#define PCDR1_VAL 0x03030303
+#define PCCR0_VAL 0xffffffff
+#define PCCR1_VAL 0xfffffffc
+
+#define AIPI1_PSR0_VAL 0x20040304
+#define AIPI1_PSR1_VAL 0xdffbfcfb
+#define AIPI2_PSR0_VAL 0x07ffc200
+#define AIPI2_PSR1_VAL 0xffffffff
+
+/*
+ * Memory Info
+ */
+/* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024)
+/* reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+/* memtest start address */
+#define CONFIG_SYS_MEMTEST_START 0xA0000000
+#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
+#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX27_UART1
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */
+/* end of flash */
+#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000)
+/* CS2 Base address */
+#define PHYS_FLASH_1 0xc0000000
+/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+/* Flash size 2MB */
+#define PHYS_FLASH_SIZE 0x200000
+#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
+ CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR 0x1f
+#define CONFIG_MII
+#define CONFIG_NET_MULTI
+
+/*
+ * MTD
+ */
+#define CONFIG_MTD_DEVICE
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0xd8000000
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
+#define CONFIG_DOS_PARTITION
+
+/*
+ * MTD partitions
+ */
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=" \
+ "physmap-flash.0:" \
+ "256k(U-Boot)," \
+ "1664k(user)," \
+ "64k(env1)," \
+ "64k(env2);" \
+ "mxc_nand.0:" \
+ "128k(IPL-SPL)," \
+ "4m(kernel)," \
+ "22m(rootfs)," \
+ "-(userfs)"
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addmisc=setenv bootargs ${bootargs}\0" \
+ "u-boot=imx27/u-boot.bin\0" \
+ "kernel_addr_r=a0800000\0" \
+ "hostname=imx27\0" \
+ "bootfile=imx27/uImage\0" \
+ "rootpath=/opt/eldk-4.2-arm/arm\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm\0" \
+ "bootcmd=run net_nfs\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};cp.b ${fileaddr} " \
+ xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "upd=run load update\0" \
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * Configuation settings for the Calao SBC35-A9G20 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
+#define CONFIG_SBC35_A9G20
+#endif
+
+#define CONFIG_AT91SAM9G20
+
+#if defined(CONFIG_SBC35_A9G20_NANDFLASH)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_EEPROM
+#endif
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#undef CONFIG_USART3
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_USB 1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* SPI EEPROM */
+#define CONFIG_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SPI_M95XXX
+#define CONFIG_SYS_EEPROM_SIZE 0x10000
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+
+/* SPI RTC */
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_M41T94
+#define CONFIG_M41T94_SPI_BUS 0
+#define CONFIG_M41T94_SPI_CS 0
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+#define CONFIG_MACB_SEARCH_PHY 1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_CMD_FAT 1
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END 0x23e00000
+
+/* Env in EEPROM, bootstrap + u-boot in NAND*/
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET 0x20
+#define CONFIG_ENV_SIZE 0x1000
+#endif
+
+/* Env, bootstrap and u-boot in NAND */
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SIZE 0x20000
+#endif
+
+#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock1 " \
+ "mtdparts=atmel_nand:16M(kernel)ro," \
+ "120M(rootfs),-(other) " \
+ "rw rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * Configuation settings for the Calao TNY-A9260 and TNY-A9G20 boards
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM)
+#define CONFIG_TNY_A9260
+#elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)
+#define CONFIG_TNY_A9G20
+#endif
+
+#ifdef CONFIG_TNY_A9260
+#define CONFIG_AT91SAM9260
+#else
+#define CONFIG_AT91SAM9G20
+#endif
+
+#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_EEPROM
+#endif
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* SPI EEPROM */
+#define CONFIG_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SPI_M95XXX
+#define CONFIG_SYS_EEPROM_SIZE 0x10000
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH 1
+
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_CMD_FAT 1
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END 0x23e00000
+
+/* Env in EEPROM, bootstrap + u-boot in NAND*/
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET 0x20
+#define CONFIG_ENV_SIZE 0x1000
+#endif
+
+/* Env, bootstrap and u-boot in NAND */
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SIZE 0x20000
+#endif
+
+#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock1 " \
+ "mtdparts=atmel_nand:16M(kernel)ro," \
+ "120M(rootfs),-(other) " \
+ "rw rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
projects / people / ms / u-boot.git / commitdiff
