if (!dev_stor_is_valid(type, dd))
return 0;
+#ifdef CONFIG_BLK
+ return blk_dread(dd, start, len, buf);
+#else
if ((dd->block_read) == NULL) {
debugf("no block_read() for device 0x%08x\n", cookie);
return 0;
}
return dd->block_read(dd, start, len, buf);
+#endif /* defined(CONFIG_BLK) */
}
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
- -j .u_boot_list -j .rela.dyn
+ -j .u_boot_list -j .rela.dyn -j .got -j .got.plt
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
#include <common.h>
-#ifdef CONFIG_USE_IRQ
-void do_irq (struct pt_regs *pt_regs)
-{
-}
-#endif
-
#if defined(CONFIG_TEGRA)
static ulong timestamp;
static ulong lastdec;
extra-y = start.o
obj-y += cpu.o
-obj-$(CONFIG_USE_IRQ) += interrupts.o
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_USE_IRQ) += interrupts.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-y += speed.o
obj-y += timer.o
#
extra-y := start.o
-obj-y += cpu.o
-
+obj-y += cpu.o cache.o
obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
--- /dev/null
+/*
+ * (C) Copyright 2017
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/armv7m.h>
+#include <asm/io.h>
+
+/* Cache maintenance operation registers */
+
+#define V7M_CACHE_REG_ICIALLU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x00))
+#define INVAL_ICACHE_POU 0
+#define V7M_CACHE_REG_ICIMVALU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x08))
+#define V7M_CACHE_REG_DCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x0C))
+#define V7M_CACHE_REG_DCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x10))
+#define V7M_CACHE_REG_DCCMVAU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x14))
+#define V7M_CACHE_REG_DCCMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x18))
+#define V7M_CACHE_REG_DCCSW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x1C))
+#define V7M_CACHE_REG_DCCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x20))
+#define V7M_CACHE_REG_DCCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x24))
+#define WAYS_SHIFT 30
+#define SETS_SHIFT 5
+
+/* armv7m processor feature registers */
+
+#define V7M_PROC_REG_CLIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x00))
+#define V7M_PROC_REG_CTR ((u32 *)(V7M_PROC_FTR_BASE + 0x04))
+#define V7M_PROC_REG_CCSIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x08))
+#define MASK_NUM_WAYS GENMASK(12, 3)
+#define MASK_NUM_SETS GENMASK(27, 13)
+#define CLINE_SIZE_MASK GENMASK(2, 0)
+#define NUM_WAYS_SHIFT 3
+#define NUM_SETS_SHIFT 13
+#define V7M_PROC_REG_CSSELR ((u32 *)(V7M_PROC_FTR_BASE + 0x0C))
+#define SEL_I_OR_D BIT(0)
+
+enum cache_type {
+ DCACHE,
+ ICACHE,
+};
+
+/* PoU : Point of Unification, Poc: Point of Coherency */
+enum cache_action {
+ INVALIDATE_POU, /* i-cache invalidate by address */
+ INVALIDATE_POC, /* d-cache invalidate by address */
+ INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
+ FLUSH_POU, /* d-cache clean by address to the PoU */
+ FLUSH_POC, /* d-cache clean by address to the PoC */
+ FLUSH_SET_WAY, /* d-cache clean by sets/ways */
+ FLUSH_INVAL_POC, /* d-cache clean & invalidate by addr to PoC */
+ FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
+};
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+struct dcache_config {
+ u32 ways;
+ u32 sets;
+};
+
+static void get_cache_ways_sets(struct dcache_config *cache)
+{
+ u32 cache_size_id = readl(V7M_PROC_REG_CCSIDR);
+
+ cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+ cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
+}
+
+/*
+ * Return the io register to perform required cache action like clean or clean
+ * & invalidate by sets/ways.
+ */
+static u32 *get_action_reg_set_ways(enum cache_action action)
+{
+ switch (action) {
+ case INVALIDATE_SET_WAY:
+ return V7M_CACHE_REG_DCISW;
+ case FLUSH_SET_WAY:
+ return V7M_CACHE_REG_DCCSW;
+ case FLUSH_INVAL_SET_WAY:
+ return V7M_CACHE_REG_DCCISW;
+ default:
+ break;
+ };
+
+ return NULL;
+}
+
+/*
+ * Return the io register to perform required cache action like clean or clean
+ * & invalidate by adddress or range.
+ */
+static u32 *get_action_reg_range(enum cache_action action)
+{
+ switch (action) {
+ case INVALIDATE_POU:
+ return V7M_CACHE_REG_ICIMVALU;
+ case INVALIDATE_POC:
+ return V7M_CACHE_REG_DCIMVAC;
+ case FLUSH_POU:
+ return V7M_CACHE_REG_DCCMVAU;
+ case FLUSH_POC:
+ return V7M_CACHE_REG_DCCMVAC;
+ case FLUSH_INVAL_POC:
+ return V7M_CACHE_REG_DCCIMVAC;
+ default:
+ break;
+ }
+
+ return NULL;
+}
+
+static u32 get_cline_size(enum cache_type type)
+{
+ u32 size;
+
+ if (type == DCACHE)
+ clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
+ else if (type == ICACHE)
+ setbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
+ /* Make sure cache selection is effective for next memory access */
+ dsb();
+
+ size = readl(V7M_PROC_REG_CCSIDR) & CLINE_SIZE_MASK;
+ /* Size enocoded as 2 less than log(no_of_words_in_cache_line) base 2 */
+ size = 1 << (size + 2);
+ debug("cache line size is %d\n", size);
+
+ return size;
+}
+
+/* Perform the action like invalidate/clean on a range of cache addresses */
+static int action_cache_range(enum cache_action action, u32 start_addr,
+ int64_t size)
+{
+ u32 cline_size;
+ u32 *action_reg;
+ enum cache_type type;
+
+ action_reg = get_action_reg_range(action);
+ if (!action_reg)
+ return -EINVAL;
+ if (action == INVALIDATE_POU)
+ type = ICACHE;
+ else
+ type = DCACHE;
+
+ /* Cache line size is minium size for the cache action */
+ cline_size = get_cline_size(type);
+ /* Align start address to cache line boundary */
+ start_addr &= ~(cline_size - 1);
+ debug("total size for cache action = %llx\n", size);
+ do {
+ writel(start_addr, action_reg);
+ size -= cline_size;
+ start_addr += cline_size;
+ } while (size > cline_size);
+
+ /* Make sure cache action is effective for next memory access */
+ dsb();
+ isb(); /* Make sure instruction stream sees it */
+ debug("cache action on range done\n");
+
+ return 0;
+}
+
+/* Perform the action like invalidate/clean on all cached addresses */
+static int action_dcache_all(enum cache_action action)
+{
+ struct dcache_config cache;
+ u32 *action_reg;
+ int i, j;
+
+ action_reg = get_action_reg_set_ways(action);
+ if (!action_reg)
+ return -EINVAL;
+
+ clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
+ /* Make sure cache selection is effective for next memory access */
+ dsb();
+
+ get_cache_ways_sets(&cache); /* Get number of ways & sets */
+ debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1);
+ for (i = cache.sets; i >= 0; i--) {
+ for (j = cache.ways; j >= 0; j--) {
+ writel((j << WAYS_SHIFT) | (i << SETS_SHIFT),
+ action_reg);
+ }
+ }
+
+ /* Make sure cache action is effective for next memory access */
+ dsb();
+ isb(); /* Make sure instruction stream sees it */
+
+ return 0;
+}
+
+void dcache_enable(void)
+{
+ if (dcache_status()) /* return if cache already enabled */
+ return;
+
+ if (action_dcache_all(INVALIDATE_SET_WAY)) {
+ printf("ERR: D-cache not enabled\n");
+ return;
+ }
+
+ setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
+
+ /* Make sure cache action is effective for next memory access */
+ dsb();
+ isb(); /* Make sure instruction stream sees it */
+}
+
+void dcache_disable(void)
+{
+ if (!dcache_status())
+ return;
+
+ /* if dcache is enabled-> dcache disable & then flush */
+ if (action_dcache_all(FLUSH_SET_WAY)) {
+ printf("ERR: D-cache not flushed\n");
+ return;
+ }
+
+ clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
+
+ /* Make sure cache action is effective for next memory access */
+ dsb();
+ isb(); /* Make sure instruction stream sees it */
+}
+
+int dcache_status(void)
+{
+ return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_DCACHE)) != 0;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (action_cache_range(INVALIDATE_POC, start, stop - start)) {
+ printf("ERR: D-cache not invalidated\n");
+ return;
+ }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (action_cache_range(FLUSH_POC, start, stop - start)) {
+ printf("ERR: D-cache not flushed\n");
+ return;
+ }
+}
+#else
+void dcache_enable(void)
+{
+ return;
+}
+
+void dcache_disable(void)
+{
+ return;
+}
+
+int dcache_status(void)
+{
+ return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+
+void invalidate_icache_all(void)
+{
+ writel(INVAL_ICACHE_POU, V7M_CACHE_REG_ICIALLU);
+
+ /* Make sure cache action is effective for next memory access */
+ dsb();
+ isb(); /* Make sure instruction stream sees it */
+}
+
+void icache_enable(void)
+{
+ if (icache_status())
+ return;
+
+ invalidate_icache_all();
+ setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
+
+ /* Make sure cache action is effective for next memory access */
+ dsb();
+ isb(); /* Make sure instruction stream sees it */
+}
+
+int icache_status(void)
+{
+ return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0;
+}
+
+void icache_disable(void)
+{
+ if (!icache_status())
+ return;
+
+ isb(); /* flush pipeline */
+ clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
+ isb(); /* subsequent instructions fetch see cache disable effect */
+}
+#else
+void icache_enable(void)
+{
+ return;
+}
+
+void icache_disable(void)
+{
+ return;
+}
+
+int icache_status(void)
+{
+ return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
default y
config SPL_MMC_SUPPORT
- default y
+ default y if MMC_SDHCI_ZYNQ
config SPL_SERIAL_SUPPORT
default y
#include <asm/system.h>
#include <asm/io.h>
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
static void cache_flush(void);
int cleanup_before_linux (void)
.thumb
#endif
-#define V7M_SCB_BASE 0xE000ED00
-#define V7M_MPU_BASE 0xE000ED90
+/* armv7m fixed base addresses */
+#define V7M_SCS_BASE 0xE000E000
+#define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100)
+#define V7M_SCB_BASE (V7M_SCS_BASE + 0x0D00)
+#define V7M_PROC_FTR_BASE (V7M_SCS_BASE + 0x0D78)
+#define V7M_MPU_BASE (V7M_SCS_BASE + 0x0D90)
+#define V7M_FPU_BASE (V7M_SCS_BASE + 0x0F30)
+#define V7M_CACHE_MAINT_BASE (V7M_SCS_BASE + 0x0F50)
+#define V7M_ACCESS_CNTL_BASE (V7M_SCS_BASE + 0x0F90)
#define V7M_SCB_VTOR 0x08
uint32_t icsr; /* Interrupt Control and State Register */
uint32_t vtor; /* Vector Table Offset Register */
uint32_t aircr; /* App Interrupt and Reset Control Register */
+ uint32_t scr; /* offset 0x10: System Control Register */
+ uint32_t ccr; /* offset 0x14: Config and Control Register */
+ uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */
+ uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */
+ uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */
+ uint32_t shcrs; /* offset 0x24: System Handler Control State */
+ uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */
+ uint32_t hfsr; /* offset 0x2C: HardFault Status Register */
+ uint32_t res; /* offset 0x30: reserved */
+ uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */
+ uint32_t bfar; /* offset 0x38: BusFault Address Reg */
+ uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */
};
#define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE)
#define V7M_ICSR_VECTACT_MSK 0xFF
+#define V7M_CCR_DCACHE 16
+#define V7M_CCR_ICACHE 17
+
struct v7m_mpu {
uint32_t type; /* Type Register */
uint32_t ctrl; /* Control Register */
obj-y += cache.o
ifndef CONFIG_ARM64
+ifndef CONFIG_CPU_V7M
obj-y += cache-cp15.o
endif
+endif
obj-y += psci-dt.o
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_USE_IRQ
-int interrupt_init (void)
-{
- unsigned long cpsr;
-
- /*
- * setup up stacks if necessary
- */
- IRQ_STACK_START = gd->irq_sp - 4;
- IRQ_STACK_START_IN = gd->irq_sp + 8;
- FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-
-
- __asm__ __volatile__("mrs %0, cpsr\n"
- : "=r" (cpsr)
- :
- : "memory");
-
- __asm__ __volatile__("msr cpsr_c, %0\n"
- "mov sp, %1\n"
- :
- : "r" (IRQ_MODE | I_BIT | F_BIT | (cpsr & ~FIQ_MODE)),
- "r" (IRQ_STACK_START)
- : "memory");
-
- __asm__ __volatile__("msr cpsr_c, %0\n"
- "mov sp, %1\n"
- :
- : "r" (FIQ_MODE | I_BIT | F_BIT | (cpsr & ~IRQ_MODE)),
- "r" (FIQ_STACK_START)
- : "memory");
-
- __asm__ __volatile__("msr cpsr_c, %0"
- :
- : "r" (cpsr)
- : "memory");
-
- return arch_interrupt_init();
-}
-
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
- unsigned long temp;
- __asm__ __volatile__("mrs %0, cpsr\n"
- "bic %0, %0, #0x80\n"
- "msr cpsr_c, %0"
- : "=r" (temp)
- :
- : "memory");
-}
-
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
- unsigned long old,temp;
- __asm__ __volatile__("mrs %0, cpsr\n"
- "orr %1, %0, #0xc0\n"
- "msr cpsr_c, %1"
- : "=r" (old), "=r" (temp)
- :
- : "memory");
- return (old & 0x80) == 0;
-}
-#else
int interrupt_init (void)
{
/*
{
return 0;
}
-#endif
-
void bad_mode (void)
{
bad_mode ();
}
-#ifndef CONFIG_USE_IRQ
void do_irq (struct pt_regs *pt_regs)
{
efi_restore_gd();
show_regs (pt_regs);
bad_mode ();
}
-#endif
gd->irq_sp = gd->start_addr_sp;
# if !defined(CONFIG_ARM64)
-# ifdef CONFIG_USE_IRQ
- gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
- debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
- CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);
-
- /* 8-byte alignment for ARM ABI compliance */
- gd->start_addr_sp &= ~0x07;
-# endif
/* leave 3 words for abort-stack, plus 1 for alignment */
gd->start_addr_sp -= 16;
# endif
IRQ_STACK_START_IN:
.word 0x0badc0de
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-
-#endif /* CONFIG_USE_IRQ */
-
@
@ IRQ stack frame.
@
bad_save_user_regs
bl do_not_used
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
.align 5
irq:
bad_save_user_regs
bl do_fiq
-#endif /* CONFIG_USE_IRQ */
-
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_DRIVER_TI_EMAC */
#if defined(CONFIG_SOC_DA8XX)
-#ifndef CONFIG_USE_IRQ
void irq_init(void)
{
/*
writel(0xffffffff, &davinci_aintc_regs->ecr2);
writel(0xffffffff, &davinci_aintc_regs->ecr3);
}
-#endif
/*
* Enable PSC for various peripherals.
DECLARE_GLOBAL_DATA_PTR;
#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
+#define STACKSIZE (512 << 10) /* 512 KiB */
#define DDR_REMAP_ADDR 0x80000000
#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
- CONFIG_STACKSIZE) >> 17) - 2)
+ STACKSIZE) >> 17) - 2)
#define DDR_TEST_BURST_SIZE 1024
(V7M_MPU_RASR_XN_ENABLE
| V7M_MPU_RASR_AP_RW_RW
| 0x01 << V7M_MPU_RASR_TEX_SHIFT
+ | 0x01 << V7M_MPU_RASR_B_SHIFT
+ | 0x01 << V7M_MPU_RASR_C_SHIFT
| V7M_MPU_RASR_SIZE_8MB
| V7M_MPU_RASR_EN)
, &V7M_MPU->rasr
DECLARE_GLOBAL_DATA_PTR;
+#define STACKSIZE 2048
+
static const char * const cpu_modes[8] = {
"Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
"Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
printf("CPU Mode: %s\n", cpu_modes[mode]);
/* Avoid exception loops */
- if (regs->sp < (gd->start_addr_sp - CONFIG_STACKSIZE) ||
+ if (regs->sp < (gd->start_addr_sp - STACKSIZE) ||
regs->sp >= gd->start_addr_sp)
printf("\nStack pointer seems bogus, won't do stack dump\n");
else
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
int board_init(void)
{
-#ifndef CONFIG_USE_IRQ
irq_init();
-#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
int board_init(void)
{
-#ifndef CONFIG_USE_IRQ
irq_init();
-#endif
#ifdef CONFIG_NAND_DAVINCI
/*
int board_init(void)
{
-#ifndef CONFIG_USE_IRQ
irq_init();
-#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
/* Set LCD_B_PWR low to power down LCD Backlight*/
gpio_direction_output(102, 0);
-#ifndef CONFIG_USE_IRQ
irq_init();
-#endif
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
int board_init(void)
{
-#ifndef CONFIG_USE_IRQ
irq_init();
-#endif
/* arch number of the board */
/* LEGO didn't register for a unique number and uses da850evm */
{
int val;
-#ifndef CONFIG_USE_IRQ
irq_init();
-#endif
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
return 0;
}
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
int board_init(void)
{
return 0;
config IDENT_STRING
default " Allwinner Technology"
+# FIXME: Should not redefine these Kconfig symbols
config PRE_CONSOLE_BUFFER
default y
default y
config SPL_MMC_SUPPORT
+ depends on SPL && GENERIC_MMC
default y
config SPL_POWER_SUPPORT
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char *name = NULL;
+ if (board_is_bone_lt()) {
+ /* BeagleBoard.org BeagleBone Black Wireless: */
+ if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
+ name = "BBBW";
+ }
+ /* SeeedStudio BeagleBone Green Wireless */
+ if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
+ name = "BBGW";
+ }
+ /* BeagleBoard.org BeagleBone Blue */
+ if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
+ name = "BBBL";
+ }
+ }
+
if (board_is_bbg1())
name = "BBG1";
set_board_info_env(name);
{MCASP5_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */
{MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */
{MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
- {MMC1_CLK, (M0 | PIN_OUTPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
{GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
{GPIO6_11, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
- {MMC3_CLK, (M0 | PIN_OUTPUT_PULLUP | MANUAL_MODE)}, /* mmc3_clk.mmc3_clk */
+ {MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_clk.mmc3_clk */
{MMC3_CMD, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_cmd.mmc3_cmd */
{MMC3_DAT0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat0.mmc3_dat0 */
{MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat1.mmc3_dat1 */
config BOOTSTAGE_STASH_SIZE
hex "Size of boot timing stash region"
- default 4096
+ default 0x1000
help
This should be large enough to hold the bootstage stash. A value of
4096 (4KiB) is normally plenty.
text_base, bss_start, bss_end);
#endif
-#ifdef CONFIG_USE_IRQ
- debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
- debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
-#endif
-
return 0;
}
int dev = mmc_get_env_dev();
int ret = 0;
-#ifdef CONFIG_SPL_BUILD
- dev = 0;
-#endif
-
env_mmc_orig_hwpart = mmc_get_blk_desc(mmc)->hwpart;
ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part);
if (ret)
#ifdef CONFIG_SYS_MMC_ENV_PART
int dev = mmc_get_env_dev();
-#ifdef CONFIG_SPL_BUILD
- dev = 0;
-#endif
blk_select_hwpart_devnum(IF_TYPE_MMC, dev, env_mmc_orig_hwpart);
#endif
}
ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env1, 1);
ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env2, 1);
-#ifdef CONFIG_SPL_BUILD
- dev = 0;
-#endif
-
mmc = find_mmc_device(dev);
errmsg = init_mmc_for_env(mmc);
int dev = mmc_get_env_dev();
const char *errmsg;
-#ifdef CONFIG_SPL_BUILD
- dev = 0;
-#endif
-
mmc = find_mmc_device(dev);
errmsg = init_mmc_for_env(mmc);
goto err;
}
}
- fdt_fixup_ethernet(blob);
/* Delete the old LMB reservation */
if (lmb)
config SPL_MMC_SUPPORT
bool "Support MMC"
- depends on SPL
+ depends on SPL && GENERIC_MMC
help
Enable support for MMC (Multimedia Card) within SPL. This enables
the MMC protocol implementation and allows any enabled drivers to
{
spl_image->size = CONFIG_SYS_MONITOR_LEN;
spl_image->entry_point = CONFIG_SYS_UBOOT_START;
+#ifdef CONFIG_CPU_V7M
+ spl_image->entry_point |= 0x1;
+#endif
spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
#define CAN 0x18
#define EOF 0x1A /* ^Z for DOS officionados */
-#define USE_YMODEM_LENGTH
-
/* Data & state local to the protocol */
static struct
{
-#ifdef REDBOOT
- hal_virtual_comm_table_t *__chan;
-#else
int *__chan;
-#endif
unsigned char pkt[1024], *bufp;
unsigned char blk, cblk, crc1, crc2;
unsigned char next_blk; /* Expected block */
int len, mode, total_retries;
int total_SOH, total_STX, total_CAN;
bool crc_mode, at_eof, tx_ack;
-#ifdef USE_YMODEM_LENGTH
unsigned long file_length, read_length;
-#endif
} xyz;
#define xyzModem_CHAR_TIMEOUT 2000 /* 2 seconds */
#define xyzModem_CAN_COUNT 3 /* Wait for 3 CAN before quitting */
-#ifndef REDBOOT /*SB */
typedef int cyg_int32;
static int
CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
if (_is_hex (c) && ((digit = _from_hex (c)) < radix))
{
/* Valid digit */
-#ifdef CYGPKG_HAL_MIPS
- /* FIXME: tx49 compiler generates 0x2539018 for MUL which */
- /* isn't any good. */
- if (16 == radix)
- result = result << 4;
- else
- result = 10 * result;
- result += digit;
-#else
result = (result * radix) + digit;
-#endif
}
else
{
return true;
}
-#endif
-#define USE_SPRINTF
#ifdef DEBUG
-#ifndef USE_SPRINTF
-/*
- * Note: this debug setup only works if the target platform has two serial ports
- * available so that the other one (currently only port 1) can be used for debug
- * messages.
- */
-static int
-zm_dprintf (char *fmt, ...)
-{
- int cur_console;
- va_list args;
-
- va_start (args, fmt);
-#ifdef REDBOOT
- cur_console =
- CYGACC_CALL_IF_SET_CONSOLE_COMM
- (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
- CYGACC_CALL_IF_SET_CONSOLE_COMM (1);
-#endif
- diag_vprintf (fmt, args);
-#ifdef REDBOOT
- CYGACC_CALL_IF_SET_CONSOLE_COMM (cur_console);
-#endif
-}
-
-static void
-zm_flush (void)
-{
-}
-
-#else
/*
* Note: this debug setup works by storing the strings in a fixed buffer
*/
-#define FINAL
-#ifdef FINAL
-static char *zm_out = (char *) 0x00380000;
-static char *zm_out_start = (char *) 0x00380000;
-#else
-static char zm_buf[8192];
-static char *zm_out = zm_buf;
-static char *zm_out_start = zm_buf;
+static char zm_debug_buf[8192];
+static char *zm_out = zm_debug_buf;
+static char *zm_out_start = zm_debug_buf;
-#endif
static int
zm_dprintf (char *fmt, ...)
{
static void
zm_flush (void)
{
-#ifdef REDBOOT
- char *p = zm_out_start;
- while (*p)
- mon_write_char (*p++);
-#endif
zm_out = zm_out_start;
}
-#endif
static void
zm_dump_buf (void *buf, int len)
{
-#ifdef REDBOOT
- diag_vdump_buf_with_offset (zm_dprintf, buf, len, 0);
-#else
-#endif
}
static unsigned char zm_buf[2048];
int
xyzModem_stream_open (connection_info_t * info, int *err)
{
-#ifdef REDBOOT
- int console_chan;
-#endif
int stat = 0;
int retries = xyzModem_MAX_RETRIES;
int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC;
}
#endif
-#ifdef REDBOOT
- /* Set up the I/O channel. Note: this allows for using a different port in the future */
- console_chan =
- CYGACC_CALL_IF_SET_CONSOLE_COMM
- (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
- if (info->chan >= 0)
- {
- CYGACC_CALL_IF_SET_CONSOLE_COMM (info->chan);
- }
- else
- {
- CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan);
- }
- xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS ();
-
- CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan);
- CYGACC_COMM_IF_CONTROL (*xyz.__chan, __COMMCTL_SET_TIMEOUT,
- xyzModem_CHAR_TIMEOUT);
-#else
/* TODO: CHECK ! */
int dummy = 0;
xyz.__chan = &dummy;
-#endif
xyz.len = 0;
xyz.crc_mode = true;
xyz.at_eof = false;
xyz.total_SOH = 0;
xyz.total_STX = 0;
xyz.total_CAN = 0;
-#ifdef USE_YMODEM_LENGTH
xyz.read_length = 0;
xyz.file_length = 0;
-#endif
CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
/* Y-modem file information header */
if (xyz.blk == 0)
{
-#ifdef USE_YMODEM_LENGTH
/* skip filename */
while (*xyz.bufp++);
/* get the length */
parse_num ((char *) xyz.bufp, &xyz.file_length, NULL, " ");
-#endif
/* The rest of the file name data block quietly discarded */
xyz.tx_ack = true;
}
("ACK block %d (%d)\n", xyz.blk, __LINE__));
xyz.next_blk = (xyz.next_blk + 1) & 0xFF;
-#if defined(xyzModem_zmodem) || defined(USE_YMODEM_LENGTH)
if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0)
{
-#else
- if (1)
- {
-#endif
/* Data blocks can be padded with ^Z (EOF) characters */
/* This code tries to detect and remove them */
if ((xyz.bufp[xyz.len - 1] == EOF) &&
}
}
-#ifdef USE_YMODEM_LENGTH
/*
* See if accumulated length exceeds that of the file.
* If so, reduce size (i.e., cut out pad bytes)
xyz.len -= (xyz.read_length - xyz.file_length);
}
}
-#endif
break;
}
else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF))
/*
* RedBoot interface
*/
-#if 0 /* SB */
-GETC_IO_FUNCS (xyzModem_io, xyzModem_stream_open, xyzModem_stream_close,
- xyzModem_stream_terminate, xyzModem_stream_read,
- xyzModem_error);
-RedBoot_load (xmodem, xyzModem_io, false, false, xyzModem_xmodem);
-RedBoot_load (ymodem, xyzModem_io, false, false, xyzModem_ymodem);
-#endif
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_ALT=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_BLANCHE=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_GOSE=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_KOELSCH=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_LAGER=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_PORTER=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SILK=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_STOUT=y
-CONFIG_BOOTSTAGE_USER_COUNT=0x20
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
u8 eir_reg;
u8 pkt_cnt;
-#ifdef CONFIG_USE_IRQ
- /* clear global interrupt enable bit in enc28j60 */
- enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
(void)enc_r8(enc, CTL_REG_ESTAT);
eir_reg = enc_r8(enc, CTL_REG_EIR);
if (eir_reg & ENC_EIR_TXIF) {
printf("%s: tx error\n", enc->dev->name);
enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
}
-#ifdef CONFIG_USE_IRQ
- /* set global interrupt enable bit in enc28j60 */
- enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
}
/*
/* Reset PDPXMD-bit => half duplex */
enc_phy_write(enc, PHY_REG_PHCON1, 0);
-#ifdef CONFIG_USE_IRQ
- /* enable interrupts */
- enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE);
- enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE);
- enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE);
- enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE);
- enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
-
return 0;
}
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE (128 * 1024)
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
"setenv fdtfile am335x-bone.dtb; fi; " \
"if test $board_name = A335BNLT; then " \
"setenv fdtfile am335x-boneblack.dtb; fi; " \
+ "if test $board_name = BBBW; then " \
+ "setenv fdtfile am335x-boneblack-wireless.dtb; fi; " \
"if test $board_name = BBG1; then " \
"setenv fdtfile am335x-bonegreen.dtb; fi; " \
+ "if test $board_name = BBGW; then " \
+ "setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \
+ "if test $board_name = BBBL; then " \
+ "setenv fdtfile am335x-boneblue.dtb; fi; " \
"if test $board_name = A33515BB; then " \
"setenv fdtfile am335x-evm.dtb; fi; " \
"if test $board_name = A335X_SK; then " \
"1m(uboot),256k(environment),"\
"-(filesystem)"
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
/* SPL */
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-#define CONFIG_STACKSIZE (128 * 1024)
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_STACKSIZE (2048)
-
#define CONFIG_BOOTARGS \
"console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
#define CONFIG_BOOTCOMMAND \
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_STACKSIZE (2048)
-
#define CONFIG_BOOTARGS \
"root=mtd:main rootfstype=jffs2"
#define CONFIG_BOOTCOMMAND \
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_STACKSIZE (2048)
-
#define CONFIG_BOOTARGS \
"console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */
-#define CONFIG_STACKSIZE SZ_256K
/* GPIO Driver */
#define CONFIG_KONA_GPIO
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */
-#define CONFIG_STACKSIZE SZ_256K
/* GPIO Driver */
#define CONFIG_KONA_GPIO
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_STACKSIZE (256 * 1024)
/* Some commands use this as the default load address */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SERIAL_TAG
/* misc */
-#define CONFIG_STACKSIZE (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM (0x80000000)
#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */
#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
-#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
/* Monitor configuration */
#undef CONFIG_CMD_DATE
/* Run-time memory allocatons */
#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_STACKSIZE (128 * 1024)
-
-#if defined(CONFIG_USE_IRQ)
-#define CONFIG_STACKSIZE_IRQ (4 * 1024)
-#define CONFIG_STACKSIZE_FIQ (4 * 1024)
-#endif
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
#define CONFIG_SYS_MEMTEST_END 0x10800000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-#define CONFIG_STACKSIZE (128 * 1024)
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-#define CONFIG_STACKSIZE (128 * 1024)
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE (128 * 1024)
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_STACKSIZE (2048)
-
-
/*
* After booting the board for the first time, new ethernet addresses
* should be generated and assigned to the environment variables
#ifndef __CONFIG_K2E_EVM_H
#define __CONFIG_K2E_EVM_H
+#include <environment/ti/spi.h>
+
/* Platform type */
#define CONFIG_SOC_K2E
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_TEXT_BASE 0x0c100000
+
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_2K
#ifndef __CONFIG_K2G_EVM_H
#define __CONFIG_K2G_EVM_H
+#include <environment/ti/spi.h>
+
/* Platform type */
#define CONFIG_SOC_K2G
#define CONFIG_BOUNCE_BUFFER
#endif
+#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS
#endif /* __CONFIG_K2G_EVM_H */
#ifndef __CONFIG_K2HK_EVM_H
#define __CONFIG_K2HK_EVM_H
+#include <environment/ti/spi.h>
+
/* Platform type */
#define CONFIG_SOC_K2HK
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_TEXT_BASE 0x0c200000
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_2K
#ifndef __CONFIG_K2L_EVM_H
#define __CONFIG_K2L_EVM_H
+#include <environment/ti/spi.h>
+
/* Platform type */
#define CONFIG_SOC_K2L
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_TEXT_BASE 0x0c100000
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_4K
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_LS102XA_STREAM_ID
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (30 * 1024)
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
#define CONFIG_LS102XA_STREAM_ID
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (30 * 1024)
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
#define CONFIG_LS102XA_STREAM_ID
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (30 * 1024)
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (30 * 1024)
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (30 * 1024)
-
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-#define CONFIG_STACKSIZE (128 * 1024)
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M)
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE SZ_8K
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*
* Physical Memory Map
*/
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM (0x80000000)
#define CONFIG_SYS_SDRAM_BASE 0x88000000
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10)
-#define CONFIG_STACKSIZE (4 << 10) /* regular stack */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR)
#endif
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
#if 0
/* Configure PXE */
#define CONFIG_BOOTP_PXE
# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
#endif /* SPI support */
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_PHY_GIGE
#define CONFIG_SYS_MALLOC_LEN (2 << 20)
-#define CONFIG_STACKSIZE (64 << 10)
-
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
#define CONFIG_BOOTCOMMAND \
#define CONFIG_SYS_INIT_SP_ADDR 0x20050000
#define CONFIG_SYS_TEXT_BASE 0x08000000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-
/*
* Configuration of the external SDRAM memory
*/
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-#define CONFIG_STACKSIZE (256 * 1024)
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CMD_MEM
+#define CONFIG_CMD_CACHE
#endif /* __CONFIG_H */
/* standalone support */
#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR
-/* baudrate */
-
-/* The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
-
/* FLASH and environment organization */
#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*
* Physical Memory Map
*/
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
/* Ethernet */
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
#endif
"fit_loadaddr=0x88000000\0" \
"fit_bootfile=fitImage.itb\0" \
"update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \
- "args_fit=setenv bootargs console=${console} \0" \
- "loadfit=run args_fit; bootm ${loadaddr}#${fdtfile};\0" \
+ "loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \
/*
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
-#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \
GENERATED_GBL_DATA_SIZE)
/* EDMA3 */
#define CONFIG_TI_EDMA3
+#define KERNEL_MTD_PARTS \
+ "mtdparts=" \
+ SPI_MTD_PARTS
+
#define DEFAULT_FW_INITRAMFS_BOOT_ENV \
"name_fw_rd=k2-fw-initrd.cpio.gz\0" \
"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \
"sf write ${loadaddr} 0 ${filesize}\0" \
"burn_uboot_nand=nand erase 0 0x100000; " \
"nand write ${loadaddr} 0 ${filesize}\0" \
- "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
+ "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 " \
+ KERNEL_MTD_PARTS \
"args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
"${nfs_options} ip=dhcp\0" \
"panicboot=echo No boot device !!! reset\0" \
TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \
-#define CONFIG_STACKSIZE (128u * SZ_1K)
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
-#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MEMTEST_START 0x80010000
#define CONFIG_SYS_MEMTEST_END 0x87C00000
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM (0x80000000)
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M)
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*
* Physical Memory Map
*/
# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
#endif
-#define CONFIG_SYS_STACKSIZE (512 << 10) /* stack 512KB */
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */
/* Linux boot param area in RAM (used only when booting linux) */
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* Keep it simple, poll only */
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_MISC_INIT_R
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for SPI on TI boards.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TI_SPI_H
+#define __TI_SPI_H
+
+#define KEYSTONE_SPI0_MTD_PARTS "spi0.0:1m(u-boot-spl)ro,-(misc);\0"
+#define KEYSTONE_SPI1_MTD_PARTS "spi1.0:1m(u-boot-spl)ro,-(misc);\0"
+
+#endif
#define xyzModem_abort 2
-#ifdef REDBOOT
-extern getc_io_funcs_t xyzModem_io;
-#else
#define CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT
#define CYGACC_CALL_IF_SET_CONSOLE_COMM(x)
char *filename;
int mode;
int chan;
-#ifdef CYGPKG_REDBOOT_NETWORKING
- struct sockaddr_in *server;
-#endif
} connection_info_t;
-#endif
int xyzModem_stream_open(connection_info_t *info, int *err);
CONFIG_SSP2_BASE
CONFIG_SSP3_BASE
CONFIG_STACKBASE
-CONFIG_STACKSIZE
-CONFIG_STACKSIZE_FIQ
-CONFIG_STACKSIZE_IRQ
CONFIG_STANDALONE_LOAD_ADDR
CONFIG_STATIC_BOARD_REV
CONFIG_STATIC_RELA
CONFIG_SYS_SSD_BASE_PHYS
CONFIG_SYS_SST_SECT
CONFIG_SYS_SST_SECTSZ
-CONFIG_SYS_STACKSIZE
CONFIG_SYS_STACK_LENGTH
CONFIG_SYS_STACK_SIZE
CONFIG_SYS_STATUS_C
CONFIG_USER_LOWLEVEL_INIT
CONFIG_USE_FDT
CONFIG_USE_INTERRUPT
-CONFIG_USE_IRQ
CONFIG_USE_NAND
CONFIG_USE_NETDEV
CONFIG_USE_NOR
projects / people / ms / u-boot.git / commitdiff
