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5cf618e)
* Rely on default pulse polarity value
* Don't mess with "multicore" value as it doesn't affect execution
In essence we now do a bare minimal stuff:
1) Select HS38x2_1 with CORE_SEL=1 bits
2) Select "manual" core start (via CREG) with START_MODE=0
3) Generate cpu_start pulse with START=1
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
{
/* CPU start CREG */
#define AXC003_CREG_CPU_START 0xF0001400
{
/* CPU start CREG */
#define AXC003_CREG_CPU_START 0xF0001400
/* Bits positions in CPU start CREG */
#define BITS_START 0
/* Bits positions in CPU start CREG */
#define BITS_START 0
+#define BITS_START_MODE 4
-#define BITS_MULTICORE 12
-
-#define CMD (1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
- (1 << BITS_POLARITY) | (1 << BITS_START)
- writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
+ int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
+ cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
+ cmd &= ~(1 << BITS_START_MODE);
+ writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);