#define UART4_BASE 0x43FB0000
#define UART5_BASE 0x43FB4000
+#define I2C1_BASE_ADDR 0x43f80000
+#define I2C1_CLK_OFFSET 26
+#define I2C2_BASE_ADDR 0x43F98000
+#define I2C2_CLK_OFFSET 28
+#define I2C3_BASE_ADDR 0x43f84000
+#define I2C3_CLK_OFFSET 30
+
#define ESDCTL_SDE (1 << 31)
#define ESDCTL_CMD_RW (0 << 28)
#define ESDCTL_CMD_PRECHARGE (1 << 28)
#define MAX_BASE_ADDR 0x43F04000
#define EVTMON_BASE_ADDR 0x43F08000
#define CLKCTL_BASE_ADDR 0x43F0C000
-#define I2C_BASE_ADDR 0x43F80000
+#define I2C1_BASE_ADDR 0x43F80000
#define I2C3_BASE_ADDR 0x43F84000
#define ATA_BASE_ADDR 0x43F8C000
#define UART1_BASE 0x43F90000
MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_SS0__SSP2_D3 |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
};
#define HW_DRAM_CTL29 (0x74 >> 2)
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+iomux_v3_cfg_t i2c3_pads[] = {
+ MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
iomux_v3_cfg_t usdhc3_pads[] = {
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
+ imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
#ifdef CONFIG_CMD_SATA
setup_sata();
#define I2SR_IIF (1 << 1)
#define I2SR_RX_NO_AK (1 << 0)
-#if defined(CONFIG_SYS_I2C_MX31_PORT1)
-#define I2C_BASE 0x43f80000
-#define I2C_CLK_OFFSET 26
-#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
-#define I2C_BASE 0x43f98000
-#define I2C_CLK_OFFSET 28
-#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
-#define I2C_BASE 0x43f84000
-#define I2C_CLK_OFFSET 30
-#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
-#define I2C_BASE I2C1_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
-#define I2C_BASE I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
-#define I2C_BASE I2C_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
-#define I2C_BASE I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
-#define I2C_BASE I2C3_BASE_ADDR
+#ifdef CONFIG_SYS_I2C_BASE
+#define I2C_BASE CONFIG_SYS_I2C_BASE
#else
-#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
+#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
#endif
#define I2C_MAX_TIMEOUT 10000
(struct clock_control_regs *)CCM_BASE;
/* start the required I2C clock */
- writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
+ writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
&sc_regs->cgr0);
#endif
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
unsigned int temp = 0;
int result;
- int speed = i2c_get_bus_speed();
- u8 clk_idx = i2c_imx_get_clk(speed);
- u8 idx = i2c_clk_div[clk_idx][1];
-
- /* Store divider value */
- writeb(idx, &i2c_regs->ifdr);
/* Enable I2C controller */
writeb(0, &i2c_regs->i2sr);
for (i = 0; i < alen; i++) {
data >>= 8;
- data |= ((char *)&addr)[i] << 24;
+ data |= ((char *)&addr)[alen - i - 1] << 24;
if ((i & 3) == 2)
writel(data, &i2c_regs->hw_i2c_data);
}
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_MXC_SPI
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX31_PORT2
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_MXC_UART
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_I2C
/*
* Memory configurations
#define CONFIG_USB_STORAGE
#endif
+/* I2C */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
/*
* SPI
*/
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT1
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2 1
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Configs */
/* I2C Configs */
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT1
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Controller */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#endif
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC