]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
Merge branch 'master' of git://git.denx.de/u-boot-i2c
authorWolfgang Denk <wd@denx.de>
Thu, 12 Jul 2012 06:17:29 +0000 (08:17 +0200)
committerWolfgang Denk <wd@denx.de>
Thu, 12 Jul 2012 06:17:29 +0000 (08:17 +0200)
* 'master' of git://git.denx.de/u-boot-i2c:
  mx28evk: Add I2C support
  mxs-i2c: Fix internal address byte order
  mxc_i2c: remove setting speed at each start
  mx6qsabrelite: add i2c support
  mxc_i2c: specify i2c base address in config file

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 files changed:
arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/imx-regs.h
board/freescale/mx28evk/iomux.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
drivers/i2c/mxc_i2c.c
drivers/i2c/mxs_i2c.c
include/configs/flea3.h
include/configs/imx31_phycore.h
include/configs/mx28evk.h
include/configs/mx35pdk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h
include/configs/mx6qsabrelite.h

index 6454acbd42c2cddd1db3b84963ebe988cd77cda2..7ddbbd627c1a3488ee1ec65d310c6979c8897765 100644 (file)
@@ -606,6 +606,13 @@ struct esdc_regs {
 #define UART4_BASE     0x43FB0000
 #define UART5_BASE     0x43FB4000
 
+#define I2C1_BASE_ADDR          0x43f80000
+#define I2C1_CLK_OFFSET                26
+#define I2C2_BASE_ADDR          0x43F98000
+#define I2C2_CLK_OFFSET                28
+#define I2C3_BASE_ADDR          0x43f84000
+#define I2C3_CLK_OFFSET                30
+
 #define ESDCTL_SDE                     (1 << 31)
 #define ESDCTL_CMD_RW                  (0 << 28)
 #define ESDCTL_CMD_PRECHARGE           (1 << 28)
index e570ad1e36e965dbaf26990707758d594f374d36..314600621c8e0977a9ec994ba34c14b8da9fe472 100644 (file)
@@ -39,7 +39,7 @@
 #define MAX_BASE_ADDR           0x43F04000
 #define EVTMON_BASE_ADDR        0x43F08000
 #define CLKCTL_BASE_ADDR        0x43F0C000
-#define I2C_BASE_ADDR           0x43F80000
+#define I2C1_BASE_ADDR         0x43F80000
 #define I2C3_BASE_ADDR          0x43F84000
 #define ATA_BASE_ADDR           0x43F8C000
 #define UART1_BASE             0x43F90000
index 00cc0cc2fa292395b7dbceb6f87eccaecaebe5ce..40d8cf60976785b2e94f515ff4216601999ba93e 100644 (file)
@@ -159,6 +159,9 @@ const iomux_cfg_t iomux_setup[] = {
        MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
        MX28_PAD_SSP2_SS0__SSP2_D3 |
                (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+       /* I2C */
+       MX28_PAD_I2C0_SCL__I2C0_SCL,
+       MX28_PAD_I2C0_SDA__I2C0_SDA,
 };
 
 #define HW_DRAM_CTL29  (0x74 >> 2)
index 29cbfed120b4f092701dcecd60dbea87bea15fd5..0eae96d3a377601f5c8489b7e470e2b845f808d7 100644 (file)
@@ -55,6 +55,11 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
        PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL   (PAD_CTL_PKE | PAD_CTL_PUE |            \
+       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+       PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
+       PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -72,6 +77,11 @@ iomux_v3_cfg_t uart2_pads[] = {
        MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+iomux_v3_cfg_t i2c3_pads[] = {
+       MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+       MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
 iomux_v3_cfg_t usdhc3_pads[] = {
        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -336,6 +346,7 @@ int board_init(void)
 #ifdef CONFIG_MXC_SPI
        setup_spi();
 #endif
+       imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 
 #ifdef CONFIG_CMD_SATA
        setup_sata();
index c88ac7cf98b318e5c6706c1dbcd6febf4bce1d94..fc68062b1183340a1d2427b6576d31fd0ba7f411 100644 (file)
@@ -59,27 +59,10 @@ struct mxc_i2c_regs {
 #define I2SR_IIF       (1 << 1)
 #define I2SR_RX_NO_AK  (1 << 0)
 
-#if defined(CONFIG_SYS_I2C_MX31_PORT1)
-#define I2C_BASE       0x43f80000
-#define I2C_CLK_OFFSET 26
-#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
-#define I2C_BASE       0x43f98000
-#define I2C_CLK_OFFSET 28
-#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
-#define I2C_BASE       0x43f84000
-#define I2C_CLK_OFFSET 30
-#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
-#define I2C_BASE        I2C1_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
-#define I2C_BASE        I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
-#define I2C_BASE       I2C_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
-#define I2C_BASE       I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
-#define I2C_BASE       I2C3_BASE_ADDR
+#ifdef CONFIG_SYS_I2C_BASE
+#define I2C_BASE       CONFIG_SYS_I2C_BASE
 #else
-#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
+#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
 #endif
 
 #define I2C_MAX_TIMEOUT                10000
@@ -114,7 +97,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate)
                (struct clock_control_regs *)CCM_BASE;
 
        /* start the required I2C clock */
-       writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
+       writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
                &sc_regs->cgr0);
 #endif
 
@@ -248,12 +231,6 @@ int i2c_imx_start(void)
        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
        unsigned int temp = 0;
        int result;
-       int speed = i2c_get_bus_speed();
-       u8 clk_idx = i2c_imx_get_clk(speed);
-       u8 idx = i2c_clk_div[clk_idx][1];
-
-       /* Store divider value */
-       writeb(idx, &i2c_regs->ifdr);
 
        /* Enable I2C controller */
        writeb(0, &i2c_regs->i2sr);
index c8fea32355439f39a0e3ad6fdef56aa1bd5dedb6..48aaaa626848d79b31d2ba3567bc6df794dd38f0 100644 (file)
@@ -97,7 +97,7 @@ void mxs_i2c_write(uchar chip, uint addr, int alen,
 
        for (i = 0; i < alen; i++) {
                data >>= 8;
-               data |= ((char *)&addr)[i] << 24;
+               data |= ((char *)&addr)[alen - i - 1] << 24;
                if ((i & 3) == 2)
                        writel(data, &i2c_regs->hw_i2c_data);
        }
index 6c5fcac6c1d4484c328634e3d375eaecfbfad52a..e8e3c6a03d4ace3bfc39b3e1ef4efd58da346bda 100644 (file)
@@ -66,7 +66,7 @@
  */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_BASE            I2C3_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_SYS_I2C_SLAVE           0xfe
 #define CONFIG_MXC_SPI
index acbd6701c753aec3a4106855b98d43ea9ca6f2dc..a412cf61eefce91a814b1f3660e09bc0f254a1fe 100644 (file)
@@ -54,7 +54,8 @@
 
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX31_PORT2
+#define CONFIG_SYS_I2C_BASE            I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_CLK_OFFSET      I2C2_CLK_OFFSET
 #define CONFIG_SYS_I2C_SPEED           100000
 
 #define CONFIG_MXC_UART
index 8f60496d355009c203975976d0abec2286364b8e..54d21e687a9c3c24e10c1eeff929b3a0928735fc 100644 (file)
@@ -68,6 +68,7 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_I2C
 
 /*
  * Memory configurations
 #define        CONFIG_USB_STORAGE
 #endif
 
+/* I2C */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED   400000
+#endif
+
 /*
  * SPI
  */
index ebbd371165c56d30558a2489417a34179d05735a..f930ed0a671b07211b34872cc2055b3e5b5f3809 100644 (file)
@@ -57,7 +57,7 @@
  */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT1
+#define CONFIG_SYS_I2C_BASE            I2C1_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
index ffc799cd7fe817a08a8bc8bffa2c51c515c4dbe6..0a928afc82c0d5a199e7307631f2d5e26b1ec6c3 100644 (file)
@@ -50,7 +50,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE            I2C2_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* MMC Configs */
index 8f2c03f1a039e3fc071601b48be53fed6d32a6ee..67def93f63f09c76580e1b6973ededf89841699d 100644 (file)
@@ -53,7 +53,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2       1
+#define CONFIG_SYS_I2C_BASE            I2C2_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* PMIC Configs */
index e71148dee60c8aae3922c592aa68cee885b21c94..61ecd02e4cdcfbb13b098e31174668e93d04249d 100644 (file)
@@ -89,7 +89,7 @@
 /* I2C Configs */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT1
+#define CONFIG_SYS_I2C_BASE            I2C1_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED           100000
 
 /* PMIC Controller */
index 1df20faf6b42a35dc07fddc0607c36e642d16f29..760014fce508f26aa069585d393a5aae71a48e3c 100644 (file)
@@ -50,7 +50,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE            I2C2_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* MMC Configs */
index fd25fafeabd38af69a9d3c59e0b4f8102cb0e36c..fbd10d670f8c80d1ea1748b37d717807dc88bc56 100644 (file)
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE            I2C3_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED            100000
+#define CONFIG_SYS_I2C_SLAVE            0xfe
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC