serial_mxc: Fix setup of UARTx_UFCR register

This patch writes the default values for TXTL and RXTL to UARTx_UFCR.
Without this patch some older kernel versions crash as UARTx_UFCR was
not always correctly initialized.

Signed-off-by: Maximilian Schwerin <maximilian.schwerin@tigris.de>

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index d6cf1d874a60c72c747489849bf58cffc915e57c..51485c0d095685a213e22cb70609e3a7459bcbae 100644 (file)
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -75,6 +75,7 @@
 #define  UCR4_DREN      (1<<0)  /* Recv data ready interrupt enable */
 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 #define  UCR4_DREN      (1<<0)  /* Recv data ready interrupt enable */
 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */

+#define  UFCR_RFDIV_SHF  7      /* Reference freq divider shift */

 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 #define  USR1_RTSS      (1<<14) /* RTS pin status */
 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 #define  USR1_RTSS      (1<<14) /* RTS pin status */


@@ -135,6 +136,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
 
 DECLARE_GLOBAL_DATA_PTR;
 

+#define TXTL  2 /* reset default */
+#define RXTL  1 /* reset default */
+#define RFDIV 4 /* divide input clock by 2 */
+

 static void mxc_serial_setbrg(void)
 {
        u32 clk = imx_get_uartclk();
 static void mxc_serial_setbrg(void)
 {
        u32 clk = imx_get_uartclk();


@@ -142,7 +147,9 @@ static void mxc_serial_setbrg(void)
        if (!gd->baudrate)
                gd->baudrate = CONFIG_BAUDRATE;
 
        if (!gd->baudrate)
                gd->baudrate = CONFIG_BAUDRATE;
 

-       __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
+       __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
+               | (TXTL << UFCR_TXTL_SHF)
+               | (RXTL << UFCR_RXTL_SHF);

        __REG(UART_PHYS + UBIR) = 0xf;
        __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
 
        __REG(UART_PHYS + UBIR) = 0xf;
        __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);