armv8: layerscape: Update early MMU for DDR after initialization

In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d82f6d1b82b8d17fae842bdf21999283fd573232..7e66ee08b56d70573505f1f9e6e72437cc66017b 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -753,3 +753,79 @@ void efi_add_known_memory(void)
        }
 }
 #endif
+
+/*
+ * Before DDR size is known, early MMU table have DDR mapped as device memory
+ * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
+ * needs to be set for these mappings.
+ * If a special case configures DDR with holes in the mapping, the holes need
+ * to be marked as invalid. This is not implemented in this function.
+ */
+void update_early_mmu_table(void)
+{
+       if (!gd->arch.tlb_addr)
+               return;
+
+       if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
+               mmu_change_region_attr(
+                                       CONFIG_SYS_SDRAM_BASE,
+                                       gd->ram_size,
+                                       PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
+                                       PTE_BLOCK_OUTER_SHARE           |
+                                       PTE_BLOCK_NS                    |
+                                       PTE_TYPE_VALID);
+       } else {
+               mmu_change_region_attr(
+                                       CONFIG_SYS_SDRAM_BASE,
+                                       CONFIG_SYS_DDR_BLOCK1_SIZE,
+                                       PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
+                                       PTE_BLOCK_OUTER_SHARE           |
+                                       PTE_BLOCK_NS                    |
+                                       PTE_TYPE_VALID);
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
+#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
+#endif
+               if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
+                   CONFIG_SYS_DDR_BLOCK2_SIZE) {
+                       mmu_change_region_attr(
+                                       CONFIG_SYS_DDR_BLOCK2_BASE,
+                                       CONFIG_SYS_DDR_BLOCK2_SIZE,
+                                       PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
+                                       PTE_BLOCK_OUTER_SHARE           |
+                                       PTE_BLOCK_NS                    |
+                                       PTE_TYPE_VALID);
+                       mmu_change_region_attr(
+                                       CONFIG_SYS_DDR_BLOCK3_BASE,
+                                       gd->ram_size -
+                                       CONFIG_SYS_DDR_BLOCK1_SIZE -
+                                       CONFIG_SYS_DDR_BLOCK2_SIZE,
+                                       PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
+                                       PTE_BLOCK_OUTER_SHARE           |
+                                       PTE_BLOCK_NS                    |
+                                       PTE_TYPE_VALID);
+               } else
+#endif
+               {
+                       mmu_change_region_attr(
+                                       CONFIG_SYS_DDR_BLOCK2_BASE,
+                                       gd->ram_size -
+                                       CONFIG_SYS_DDR_BLOCK1_SIZE,
+                                       PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
+                                       PTE_BLOCK_OUTER_SHARE           |
+                                       PTE_BLOCK_NS                    |
+                                       PTE_TYPE_VALID);
+               }
+       }
+}
+
+__weak int dram_init(void)
+{
+       gd->ram_size = initdram(0);
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+       /* This will break-before-make MMU for DDR */
+       update_early_mmu_table();
+#endif
+
+       return 0;
+}

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 4ea4aeaf4c238886da0d8389eba131ab539ec4e3..bcf3e3863e6f08e1dc39b1e4dc3f8ec1fff61fa2 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -115,7 +115,11 @@ static struct mm_region early_map[] = {
        },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
          PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else  /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
        /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
@@ -130,7 +134,7 @@ static struct mm_region early_map[] = {
        },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
          CONFIG_SYS_FSL_DRAM_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
 #elif defined(CONFIG_FSL_LSCH2)
@@ -158,12 +162,16 @@ static struct mm_region early_map[] = {
        },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
          PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else  /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
          CONFIG_SYS_FSL_DRAM_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
 #endif

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
index d54eacd4a038044518407870eeb4351b0fe195a4..d232bec1e4d8c60eedd79fb952ba3918670ab905 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
@@ -6,5 +6,5 @@
 
 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
 #define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
-#include <asm/arch-armv8/mmu.h>
+void update_early_mmu_table(void);
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */

diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 1f3adc1e882d8ea8a4fb762b9faab3ac2fbab2cf..25d22d25bf80ca7857a050c79af52ade7c8e1a82 100644 (file)
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -12,6 +12,7 @@
 #ifdef CONFIG_FSL_LS_PPA
 #include <asm/arch/ppa.h>
 #endif
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
 #include <environment.h>
@@ -48,6 +49,10 @@ int dram_init(void)
        mmdc_init(&mparam);
 
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+       /* This will break-before-make MMU for DDR */
+       update_early_mmu_table();
+#endif
 
        return 0;
 }

diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index fbda504c0445f34898ca85b3a182b29bd0569c5d..97ab3400ad211fe0a2b2cc52a56032156b3842ac 100644 (file)
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -14,6 +14,7 @@
 #include <asm/arch/ppa.h>
 #endif
 #include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <ahci.h>
 #include <hwconfig.h>
@@ -76,6 +77,10 @@ int dram_init(void)
        mmdc_init(&mparam);
 
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+       /* This will break-before-make MMU for DDR */
+       update_early_mmu_table();
+#endif
 
        return 0;
 }

diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 2a85a1f8f7919df9f124912ab7f26fb9cc7ec1e6..a23a23be1f0218cdbd5d11c4e31073c82165106f 100644 (file)
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -12,6 +12,7 @@
 #ifdef CONFIG_FSL_LS_PPA
 #include <asm/arch/ppa.h>
 #endif
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
 #include <ahci.h>
@@ -80,6 +81,10 @@ int dram_init(void)
        mmdc_init(&mparam);
 
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+       /* This will break-before-make MMU for DDR */
+       update_early_mmu_table();
+#endif
 
        return 0;
 }

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 8835a49bb508193a66559aa9412e36fb9f0198e8..6507c0914342de4a99ddd33af787e5143eee6ad7 100644 (file)
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -11,6 +11,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <ahci.h>
 #include <hwconfig.h>
@@ -153,6 +154,10 @@ int dram_init(void)
         */
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
        gd->ram_size = initdram(0);
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+       /* This will break-before-make MMU for DDR */
+       update_early_mmu_table();
+#endif
 
        return 0;
 }

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index e213128c1b9c270c96080f138d9d634fc27bd10f..2333843958fdb614940fcccff212cbcbc8447403 100644 (file)
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -67,13 +67,6 @@ int checkboard(void)
        return 0;
 }
 
-int dram_init(void)
-{
-       gd->ram_size = initdram(0);
-
-       return 0;
-}
-
 int board_early_init_f(void)
 {
        fsl_lsch2_early_init_f();

diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 552365b9d88854afd9d529e21739a8d828352675..af3f70a38b70089177632b0c6c15a7d5d9cb7fde 100644 (file)
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -11,6 +11,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <ahci.h>
 #include <hwconfig.h>
@@ -149,6 +150,10 @@ int dram_init(void)
         */
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
        gd->ram_size = initdram(0);
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+       /* This will break-before-make MMU for DDR */
+       update_early_mmu_table();
+#endif
 
        return 0;
 }

diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 33a58cf4404e223ca727c74756ce4139effdfc55..02b6c4c3752240afe210c0d0c793efe891970edb 100644 (file)
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -56,13 +56,6 @@ int checkboard(void)
        return 0;
 }
 
-int dram_init(void)
-{
-       gd->ram_size = initdram(0);
-
-       return 0;
-}
-
 int board_early_init_f(void)
 {
        fsl_lsch2_early_init_f();

diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
index 21ea70bd4d9a6273b79b28b986d916444cf506d8..9e7701d81ff517edddacf08e046b204e62393bbe 100644 (file)
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -49,13 +49,6 @@ void detail_board_ddr_info(void)
 #endif
 }
 
-int dram_init(void)
-{
-       gd->ram_size = initdram(0);
-
-       return 0;
-}
-
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index ec53992bcc5eddc04c8ef32b5f7320d4dbf7b00c..8abf64add8c60ff4064532c9947624b67441b36a 100644 (file)
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -254,13 +254,6 @@ void detail_board_ddr_info(void)
 #endif
 }
 
-int dram_init(void)
-{
-       gd->ram_size = initdram(0);
-
-       return 0;
-}
-
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 7a4c6a3a5c5d25d8961a9421c4daa24c46fc1cd6..4c01f560bcde815006decb1fa2c6ea68a6b85b61 100644 (file)
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -17,6 +17,7 @@
 #include <environment.h>
 #include <efi_loader.h>
 #include <i2c.h>
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <fsl_sec.h>
 
@@ -219,13 +220,6 @@ void detail_board_ddr_info(void)
 #endif
 }
 
-int dram_init(void)
-{
-       gd->ram_size = initdram(0);
-
-       return 0;
-}
-
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {