board: stm32f429-discovery: switch to DM STM32 sdram driver

Use available DM stm32_sdram.c driver instead of board
SDRAM initialization.
For that, enable OF_CONTROL, OF_EMBED and STM32_SDRAM flags.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index 1c34a8efe14e314b68cfbe9953b2409c7b34baad..7e8df8eaef4e2ec1b066bf9cf31b935b92c9b29d 100644 (file)
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -15,10 +15,8 @@
 #include <dm.h>
 #include <stm32_rcc.h>
 #include <asm/io.h>
-#include <asm/armv7m.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/fmc.h>
 #include <dm/platform_data/serial_stm32.h>
 #include <asm/arch/stm32_periph.h>
 #include <asm/arch/stm32_defs.h>
@@ -140,56 +138,10 @@ out:
  */
 #define STM32_RCC_ENR_FMC      (1 << 0)        /* FMC module clock  */
 
-static inline u32 _ns2clk(u32 ns, u32 freq)
-{
-       u32 tmp = freq/1000000;
-       return (tmp * ns) / 1000;
-}
-
-#define NS2CLK(ns) (_ns2clk(ns, freq))
-
-/*
- * Following are timings for IS42S16400J, from corresponding datasheet
- */
-#define SDRAM_CAS      3       /* 3 cycles */
-#define SDRAM_NB       1       /* Number of banks */
-#define SDRAM_MWID     1       /* 16 bit memory */
-
-#define SDRAM_NR       0x1     /* 12-bit row */
-#define SDRAM_NC       0x0     /* 8-bit col */
-#define SDRAM_RBURST   0x1     /* Single read requests always as bursts */
-#define SDRAM_RPIPE    0x0     /* No HCLK clock cycle delay */
-
-#define SDRAM_TRRD     (NS2CLK(14) - 1)
-#define SDRAM_TRCD     (NS2CLK(15) - 1)
-#define SDRAM_TRP      (NS2CLK(15) - 1)
-#define SDRAM_TRAS     (NS2CLK(42) - 1)
-#define SDRAM_TRC      (NS2CLK(63) - 1)
-#define SDRAM_TRFC     (NS2CLK(63) - 1)
-#define SDRAM_TCDL     (1 - 1)
-#define SDRAM_TRDL     (2 - 1)
-#define SDRAM_TBDL     (1 - 1)
-#define SDRAM_TREF     1386
-#define SDRAM_TCCD     (1 - 1)
-
-#define SDRAM_TXSR     (NS2CLK(70) - 1)/* Row cycle time after precharge */
-#define SDRAM_TMRD     (3 - 1)         /* Page 10, Mode Register Set */
-
-/* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */
-#define SDRAM_TWR      max(\
-       (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \
-       (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\
-)
-
-#define SDRAM_MODE_BL_SHIFT    0
-#define SDRAM_MODE_CAS_SHIFT   4
-#define SDRAM_MODE_BL          0
-#define SDRAM_MODE_CAS         SDRAM_CAS
-
 int dram_init(void)
 {
-       u32 freq;
        int rv;
+       struct udevice *dev;
 
        rv = fmc_setup_gpio();
        if (rv)
@@ -197,83 +149,23 @@ int dram_init(void)
 
        setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
 
-       /*
-        * Get frequency for NS2CLK calculation.
-        */
-       freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
-
-       writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
-               | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
-               | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
-               &STM32_SDRAM_FMC->sdcr1);
-
-       writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
-               | SDRAM_CAS << FMC_SDCR_CAS_SHIFT
-               | SDRAM_NB << FMC_SDCR_NB_SHIFT
-               | SDRAM_MWID << FMC_SDCR_MWID_SHIFT
-               | SDRAM_NR << FMC_SDCR_NR_SHIFT
-               | SDRAM_NC << FMC_SDCR_NC_SHIFT
-               | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
-               | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
-               &STM32_SDRAM_FMC->sdcr2);
-
-       writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT
-               | SDRAM_TRC << FMC_SDTR_TRC_SHIFT,
-               &STM32_SDRAM_FMC->sdtr1);
-
-       writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
-               | SDRAM_TRP << FMC_SDTR_TRP_SHIFT
-               | SDRAM_TWR << FMC_SDTR_TWR_SHIFT
-               | SDRAM_TRC << FMC_SDTR_TRC_SHIFT
-               | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
-               | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
-               | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
-               &STM32_SDRAM_FMC->sdtr2);
-
-       writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK,
-              &STM32_SDRAM_FMC->sdcmr);
-
-       udelay(200);    /* 200 us delay, page 10, "Power-Up" */
-       FMC_BUSY_WAIT();
-
-       writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE,
-              &STM32_SDRAM_FMC->sdcmr);
-
-       udelay(100);
-       FMC_BUSY_WAIT();
-
-       writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH
-               | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
-
-       udelay(100);
-       FMC_BUSY_WAIT();
-
-       writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
-               | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
-               << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
-               &STM32_SDRAM_FMC->sdcmr);
-
-       udelay(100);
-
-       FMC_BUSY_WAIT();
-
-       writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL,
-              &STM32_SDRAM_FMC->sdcmr);
-
-       FMC_BUSY_WAIT();
+       rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (rv) {
+               debug("DRAM init failed: %d\n", rv);
+               return rv;
+       }
 
-       /* Refresh timer */
-       writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
+       if (fdtdec_setup_memory_size() != 0)
+               rv = -EINVAL;
 
-       /*
-        * Fill in global info with description of SRAM configuration
-        */
-       gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
-       gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
+       return rv;
+}
 
-       gd->ram_size = CONFIG_SYS_RAM_SIZE;
+int dram_init_banksize(void)
+{
+       fdtdec_setup_memory_banksize();
 
-       return rv;
+       return 0;
 }
 
 static const struct stm32_serial_platdata serial_platdata = {

diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 9339e3670b636e5cdc79f673557581b1898cd04f..1cf3b6af9c3989907223ab652fa779688d84b304 100644 (file)
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_STM32=y
 CONFIG_STM32F4=y
 CONFIG_TARGET_STM32F429_DISCOVERY=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
@@ -14,7 +15,10 @@ CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_CMD_IMLS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIMER=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FLASH=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
-CONFIG_OF_LIBFDT=y
+CONFIG_RAM=y
+CONFIG_STM32_SDRAM=y

diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 024d75af3b12151c25441e6792fcda3c9e685c17..317b9344a1f4ae37ca19033dc186e5422bb04a79 100644 (file)
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -24,7 +24,6 @@
  * Configuration of the external SDRAM memory
  */
 #define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_SYS_RAM_SIZE            (8 << 20)
 #define CONFIG_SYS_RAM_CS              1
 #define CONFIG_SYS_RAM_FREQ_DIV                2
 #define CONFIG_SYS_RAM_BASE            0xD0000000