ATM the rx and tx descriptors are handled as cached memory while they
lie in a dedicated RAM of the SoCs, which is an uncached area.
Removing the said dcache ops, while optimizing the logic and clarifying
the code, also gets rid of most of the check_cache_range() incurred
warnings:
CACHE: Misaligned operation at range
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
-static inline void davinci_flush_rx_descs(void)
-{
- /* flush the whole RX descs area */
- flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
- EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
-}
-
-static inline void davinci_invalidate_rx_descs(void)
-{
- /* invalidate the whole RX descs area */
- invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
- EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
-}
-
-static inline void davinci_flush_desc(emac_desc *desc)
-{
- flush_dcache_range((unsigned long)desc,
- (unsigned long)desc + sizeof(*desc));
-}
-
static int davinci_eth_set_mac_addr(struct eth_device *dev)
{
unsigned long mac_hi;
static int davinci_eth_set_mac_addr(struct eth_device *dev)
{
unsigned long mac_hi;
emac_rx_active_tail = rx_desc;
emac_rx_queue_active = 1;
emac_rx_active_tail = rx_desc;
emac_rx_queue_active = 1;
- davinci_flush_rx_descs();
-
/* Enable TX/RX */
writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
writel(0, &adap_emac->RXBUFFEROFFSET);
/* Enable TX/RX */
writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
writel(0, &adap_emac->RXBUFFEROFFSET);
flush_dcache_range((unsigned long)packet,
(unsigned long)packet + length);
flush_dcache_range((unsigned long)packet,
(unsigned long)packet + length);
- davinci_flush_desc(emac_tx_desc);
/* Send the packet */
writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
/* Send the packet */
writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
volatile emac_desc *tail_desc;
int status, ret = -1;
volatile emac_desc *tail_desc;
int status, ret = -1;
- davinci_invalidate_rx_descs();
-
rx_curr_desc = emac_rx_active_head;
if (!rx_curr_desc)
return 0;
rx_curr_desc = emac_rx_active_head;
if (!rx_curr_desc)
return 0;
rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
rx_curr_desc->next = 0;
rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
rx_curr_desc->next = 0;
- davinci_flush_desc(rx_curr_desc);
if (emac_rx_active_head == 0) {
printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
if (emac_rx_active_head == 0) {
printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
tail_desc->next = BD_TO_HW((ulong) curr_desc);
status = tail_desc->pkt_flag_len;
if (status & EMAC_CPPI_EOQ_BIT) {
tail_desc->next = BD_TO_HW((ulong) curr_desc);
status = tail_desc->pkt_flag_len;
if (status & EMAC_CPPI_EOQ_BIT) {
- davinci_flush_desc(tail_desc);
writel(BD_TO_HW((ulong)curr_desc),
&adap_emac->RX0HDP);
status &= ~EMAC_CPPI_EOQ_BIT;
tail_desc->pkt_flag_len = status;
}
writel(BD_TO_HW((ulong)curr_desc),
&adap_emac->RX0HDP);
status &= ~EMAC_CPPI_EOQ_BIT;
tail_desc->pkt_flag_len = status;
}
- davinci_flush_desc(tail_desc);