install:
# install U-Boot build dependencies
- - sudo apt-get install -qq cppcheck sloccount sparse bc libsdl-dev gcc-arm-linux-gnueabi gcc-arm-linux-gnueabihf
+ - sudo apt-get install -qq cppcheck sloccount sparse bc libsdl-dev build-essential
# install latest device tree compiler
- git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
- make -j4 -C /tmp/dtc
- export BUILDMAN_ROOT="root:"
- export BUILDMAN_MIPS="mips:"
- export BUILDMAN_PPC="ppc:"
- - echo -e "[toolchain]\\n${BUILDMAN_ROOT} /\n" > ~/.buildman
- - echo -e "${BUILDMAN_MIPS} /opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/" >> ~/.buildman
- - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/" >> ~/.buildman
+ - export BUILDMAN_ARM="arm:"
+ - export BUILDMAN_SANDBOX="sandbox:"
+ - echo -e "[toolchain]\n${BUILDMAN_ROOT} /\n" > ~/.buildman
+ - echo -e "${BUILDMAN_MIPS} /opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ARM} /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_SANDBOX} /usr/bin/gcc\n" >> ~/.buildman
- export BUILDMAN_ALIAS="x86:"
- - echo -e "[toolchain-alias]\\n${BUILDMAN_ALIAS} i386" >> ~/.buildman
+ - export BUILDMAN_ALIAS_ARM="arm:"
+ - echo -e "\n\n[toolchain-alias]\n${BUILDMAN_ALIAS} i386\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ALIAS_ARM} armv5te\n" >> ~/.buildman
- cat ~/.buildman
env:
before_script:
# install toolchains based on INSTALL_TOOLCHAIN} variable
- - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi
- - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *arm* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *arm* ]]; then sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *arm* ]]; then ls -al /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *i386* ]]; then ./tools/buildman/buildman sandbox --fetch-arch i386 ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
- if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/mips/eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh ; fi
- if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then sh eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh -y ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
script:
# the execution sequence for each test
# each env setting here is a dedicated build
- env:
- TEST_CMD="./MAKEALL -a arm -v atmel"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CMD="./MAKEALL -a arm -v denx"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CMD="./MAKEALL -a arm -v freescale"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CMD="./MAKEALL -a arm -v siemens"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CMD="./MAKEALL -a arm -v ti"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CONFIG_CMD="make sandbox_defconfig"
TEST_CMD="make -j4"
INSTALL_TOOLCHAIN="mips"
CROSS_COMPILE="/opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/mips-linux-"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards atmel"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards arm1136"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards arm1176"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards arm720t"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards arm920t"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards atmel -x avr32"
+ INSTALL_TOOLCHAIN="arm"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards denx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards avr32"
+ INSTALL_TOOLCHAIN="avr32"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards freescale arm"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards davinci"
+ INSTALL_TOOLCHAIN="arm"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards siemens"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards denx"
+ INSTALL_TOOLCHAIN="arm"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards ti"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards freescale -x powerpc,m68k,aarch64"
+ INSTALL_TOOLCHAIN="arm"
- env:
- - TEST_CMD="tools/buildman/buildman mips"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards freescale -x arm,m68k,aarch64"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards sandbox x86"
+ INSTALL_TOOLCHAIN="i386"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards kirkwood"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards m68k"
+ INSTALL_TOOLCHAIN="m68k"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mips"
INSTALL_TOOLCHAIN="mips"
- env:
- - TEST_CMD="tools/buildman/buildman mpc5xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc512x"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc8xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc5xx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc5xxx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc5xxx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc512x"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc8260"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc8260"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc83xx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc83xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc85xx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc85xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc86xx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc86xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc8xx"
INSTALL_TOOLCHAIN="ppc"
-
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards sandbox x86"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards siemens"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards ti"
+ INSTALL_TOOLCHAIN="arm"
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
initial serial device and any others that are needed.
menuconfig EXPERT
- bool "Configure standard U-Boot features (expert users)"
- help
- This option allows certain base U-Boot options and settings
- to be disabled or tweaked. This is for specialized
- environments which can tolerate a "non-standard" U-Boot.
- Only use this if you really know what you are doing.
-
+ bool "Configure standard U-Boot features (expert users)"
+ default y
+ help
+ This option allows certain base U-Boot options and settings
+ to be disabled or tweaked. This is for specialized
+ environments which can tolerate a "non-standard" U-Boot.
+ Only use this if you really know what you are doing.
+
+if EXPERT
+ config SYS_MALLOC_CLEAR_ON_INIT
+ bool "Init with zeros the memory reserved for malloc (slow)"
+ default y
+ help
+ This setting is enabled by default. The reserved malloc
+ memory is initialized with zeros, so first malloc calls
+ will return the pointer to the zeroed memory. But this
+ slows the boot time.
+
+ It is recommended to disable it, when CONFIG_SYS_MALLOC_LEN
+ value, has more than few MiB, e.g. when uses bzip2 or bmp logo.
+ Then the boot time can be significantly reduced.
+ Warning:
+ When disabling this, please check if malloc calls, maybe
+ should be replaced by calloc - if expects zeroed memory.
+endif
endmenu # General setup
menu "Boot images"
F: arch/arm/include/asm/ti-common/
ARM UNIPHIER
-M: Masahiro Yamada <yamada.m@jp.panasonic.com>
+M: Masahiro Yamada <yamada.masahiro@socionext.com>
S: Maintained
T: git git://git.denx.de/u-boot-uniphier.git
F: arch/arm/mach-uniphier/
DRIVER MODEL
M: Simon Glass <sjg@chromium.org>
S: Maintained
+T: git git://git.denx.de/u-boot-dm.git
F: drivers/core/
F: include/dm/
F: test/dm/
RC=1
fi
+ OBJS=${output_dir}/u-boot
+ if [ -e ${output_dir}/spl/u-boot-spl ]; then
+ OBJS="${OBJS} ${output_dir}/spl/u-boot-spl"
+ fi
+
+ ${CROSS_COMPILE}size ${OBJS} | tee -a ${LOG_DIR}/$target.MAKELOG
+
if [ $BUILD_MANY == 1 ] ; then
trap - TERM
fi
fi
- OBJS=${output_dir}/u-boot
- if [ -e ${output_dir}/spl/u-boot-spl ]; then
- OBJS="${OBJS} ${output_dir}/spl/u-boot-spl"
- fi
-
- ${CROSS_COMPILE}size ${OBJS} | tee -a ${LOG_DIR}/$target.MAKELOG
-
[ -e "${LOG_DIR}/${target}.ERR" ] && cat "${LOG_DIR}/${target}.ERR"
touch "${donep}${build_idx}"
VERSION = 2015
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
-- Driver Model
- Driver model is a new framework for devices in U-Boot
- introduced in early 2014. U-Boot is being progressively
- moved over to this. It offers a consistent device structure,
- supports grouping devices into classes and has built-in
- handling of platform data and device tree.
-
- To enable transition to driver model in a relatively
- painful fashion, each subsystem can be independently
- switched between the legacy/ad-hoc approach and the new
- driver model using the options below. Also, many uclass
- interfaces include compatibility features which may be
- removed once the conversion of that subsystem is complete.
- As a result, the API provided by the subsystem may in fact
- not change with driver model.
-
- See doc/driver-model/README.txt for more information.
-
- CONFIG_DM
-
- Enable driver model. This brings in the core support,
- including scanning of platform data on start-up. If
- CONFIG_OF_CONTROL is enabled, the device tree will be
- scanned also when available.
-
- CONFIG_CMD_DM
-
- Enable driver model test commands. These allow you to print
- out the driver model tree and the uclasses.
-
- CONFIG_DM_DEMO
-
- Enable some demo devices and the 'demo' command. These are
- really only useful for playing around while trying to
- understand driver model in sandbox.
-
- CONFIG_SPL_DM
-
- Enable driver model in SPL. You will need to provide a
- suitable malloc() implementation. If you are not using the
- full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
- consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
- must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
- In most cases driver model will only allocate a few uclasses
- and devices in SPL, so 1KB should be enable. See
- CONFIG_SYS_MALLOC_F_LEN for more details on how to enable
- it.
-
- CONFIG_DM_SERIAL
-
- Enable driver model for serial. This replaces
- drivers/serial/serial.c with the serial uclass, which
- implements serial_putc() etc. The uclass interface is
- defined in include/serial.h.
-
- CONFIG_DM_GPIO
-
- Enable driver model for GPIO access. The standard GPIO
- interface (gpio_get_value(), etc.) is then implemented by
- the GPIO uclass. Drivers provide methods to query the
- particular GPIOs that they provide. The uclass interface
- is defined in include/asm-generic/gpio.h.
-
- CONFIG_DM_SPI
-
- Enable driver model for SPI. The SPI slave interface
- (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
- the SPI uclass. Drivers provide methods to access the SPI
- buses that they control. The uclass interface is defined in
- include/spi.h. The existing spi_slave structure is attached
- as 'parent data' to every slave on each bus. Slaves
- typically use driver-private data instead of extending the
- spi_slave structure.
-
- CONFIG_DM_SPI_FLASH
-
- Enable driver model for SPI flash. This SPI flash interface
- (spi_flash_probe(), spi_flash_write(), etc.) is then
- implemented by the SPI flash uclass. There is one standard
- SPI flash driver which knows how to probe most chips
- supported by U-Boot. The uclass interface is defined in
- include/spi_flash.h, but is currently fully compatible
- with the old interface to avoid confusion and duplication
- during the transition parent. SPI and SPI flash must be
- enabled together (it is not possible to use driver model
- for one and not the other).
-
- CONFIG_DM_CROS_EC
-
- Enable driver model for the Chrome OS EC interface. This
- allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
- but otherwise makes few changes. Since cros_ec also supports
- I2C and LPC (which don't support driver model yet), a full
- conversion is not yet possible.
-
-
- ** Code size options: The following options are enabled by
- default except in SPL. Enable them explicitly to get these
- features in SPL.
-
- CONFIG_DM_WARN
-
- Enable the dm_warn() function. This can use up quite a bit
- of space for its strings.
-
- CONFIG_DM_STDIO
-
- Enable registering a serial device with the stdio library.
-
- CONFIG_DM_DEVICE_REMOVE
-
- Enable removing of devices.
-
+ NOTE: The following can be machine specific errata. These
+ do have ability to provide rudimentary version and machine
+ specific checks, but expect no product checks.
+ CONFIG_ARM_ERRATA_430973
+ CONFIG_ARM_ERRATA_454179
+ CONFIG_ARM_ERRATA_621766
+ CONFIG_ARM_ERRATA_798870
+
+- Tegra SoC options:
+ CONFIG_TEGRA_SUPPORT_NON_SECURE
+
+ Support executing U-Boot in non-secure (NS) mode. Certain
+ impossible actions will be skipped if the CPU is in NS mode,
+ such as ARM architectural timer initialization.
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_LINKAGE_H
+#define __ASM_ARC_LINKAGE_H
+
+#define ASM_NL ` /* use '`' to mark new line in macro */
+
+#endif /* __ASM_ARC_LINKAGE_H */
select CPU_V7
select SUPPORT_SPL
+config TARGET_BAV335X
+ bool "Support bav335x"
+ select CPU_V7
+ select SUPPORT_SPL
+ help
+ The BAV335x OEM Network Processor integrates all the functions of an
+ embedded network computer in a small, easy to use SODIMM module which
+ incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
+ processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
+ ethernet with simple connection to external connectors.
+
+ For more information, visit: http://birdland.com/oem
+
config TARGET_TI814X_EVM
bool "Support ti814x_evm"
select CPU_V7
select CPU_V7
select SUPPORT_SPL
+config TARGET_SOCFPGA_ARRIA5
+ bool "Support socfpga_arria5"
+ select CPU_V7
+ select SUPPORT_SPL
+
config TARGET_SOCFPGA_CYCLONE5
bool "Support socfpga_cyclone5"
select CPU_V7
config TARGET_LS2085A_EMU
bool "Support ls2085a_emu"
select ARM64
+ select ARMV8_MULTIENTRY
config TARGET_LS2085A_SIMU
bool "Support ls2085a_simu"
select ARM64
+ select ARMV8_MULTIENTRY
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
source "arch/arm/cpu/armv7/Kconfig"
+source "arch/arm/cpu/armv8/Kconfig"
+
source "board/aristainetos/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
+source "board/birdland/bav335x/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
--- /dev/null
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on:
+ *
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Based on omap-common/u-boot-spl.lds:
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ CPUDIR/start.o (.text)
+ *(.text*)
+ } > .nor
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } > .nor
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } > .bss
+}
obj-y += cache_v7.o
-obj-y += cpu.o
+obj-y += cpu.o cp15.o
obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
--- /dev/null
+/*
+ * (C) Copyright 2015 Texas Insturments
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * CP15 specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <asm/armv7.h>
+#include <linux/compiler.h>
+
+void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev)
+{
+ asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
+}
+
+void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
+{
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
+}
ifeq ($(CONFIG_OMAP34XX),)
obj-y += boot-common.o
-obj-y += lowlevel_init.o
endif
+obj-y += lowlevel_init.o
obj-y += mem-common.o
#include <asm/arch/spl.h>
#include <linux/linkage.h>
+#ifndef CONFIG_OMAP34XX
ENTRY(save_boot_params)
ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
b save_boot_params_ret
ENDPROC(save_boot_params)
+#endif
-ENTRY(set_pl310_ctrl_reg)
- PUSH {r4-r11, lr} @ save registers - ROM code may pollute
+ENTRY(omap_smc1)
+ PUSH {r4-r12, lr} @ save registers - ROM code may pollute
@ our registers
- LDR r12, =0x102 @ Set PL310 control register - value in R0
- .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
- @ call ROM Code API to set control register
- POP {r4-r11, pc}
-ENDPROC(set_pl310_ctrl_reg)
+ MOV r12, r0 @ Service
+ MOV r0, r1 @ Argument
+ DSB
+ DMB
+ .word 0xe1600070 @ SMC #0 - hand assembled for GCC versions
+ @ call ROM Code API for the service requested
+
+ POP {r4-r12, pc}
+ENDPROC(omap_smc1)
bool "Twister"
select SUPPORT_SPL
+config TARGET_OMAP3_CAIRO
+ bool "QUIPOS CAIRO"
+ select SUPPORT_SPL
+
endchoice
config DM
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
+source "board/quipos/cairo/Kconfig"
endif
/* Declarations */
extern omap3_sysinfo sysinfo;
-static void omap3_setup_aux_cr(void);
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif
try_unlock_memory();
- /* Errata workarounds */
- omap3_setup_aux_cr();
-
#ifndef CONFIG_SYS_L2CACHE_OFF
/* Invalidate L2-cache from secure mode */
omap3_invalidate_l2_cache_secure();
goto usage;
}
} else if (strncmp(argv[1], "sw", 2) == 0) {
- omap_nand_switch_ecc(0, 0);
+ if (argc == 2) {
+ omap_nand_switch_ecc(0, 1);
+ } else {
+ if (strncmp(argv[2], "hamming", 7) == 0)
+ omap_nand_switch_ecc(0, 1);
+ else if (strncmp(argv[2], "bch8", 4) == 0)
+ omap_nand_switch_ecc(0, 8);
+ else
+ goto usage;
+ }
} else {
goto usage;
}
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
+void __weak omap3_set_aux_cr_secure(u32 acr)
{
- u32 acr;
-
- /* Read ACR */
- asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
- acr &= ~clear_bits;
- acr |= set_bits;
+ struct emu_hal_params emu_romcode_params;
- if (get_device_type() == GP_DEVICE) {
- omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
- acr);
- } else {
- struct emu_hal_params emu_romcode_params;
- emu_romcode_params.num_params = 1;
- emu_romcode_params.param1 = acr;
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
- }
+ emu_romcode_params.num_params = 1;
+ emu_romcode_params.param1 = acr;
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
}
-static void omap3_setup_aux_cr(void)
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
{
- /* Workaround for Cortex-A8 errata: #454179 #430973
- * Set "IBE" bit
- * Set "Disable Branch Size Mispredicts" bit
- * Workaround for erratum #621766
- * Enable L1NEON bit
- * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
- */
- omap3_update_aux_cr_secure(0xE0, 0);
+ /* Write ACR - affects secure banked bits */
+ if (get_device_type() == GP_DEVICE)
+ omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
+ else
+ omap3_set_aux_cr_secure(acr);
+
+ /* Write ACR - affects non-secure banked bits - some erratas need it */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
+
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
+ v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
- /* Write ACR - affects non-secure banked bits */
- asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
if (get_device_type() == GP_DEVICE) {
- omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
- 0);
+ omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
} else {
struct emu_hal_params emu_romcode_params;
emu_romcode_params.num_params = 1;
void v7_outer_cache_enable(void)
{
- /* Set L2EN */
- omap3_update_aux_cr_secure(0x2, 0);
/*
+ * Set L2EN
* On some revisions L2EN bit is banked on some revisions it's not
* No harm in setting both banked bits(in fact this is required
* by an erratum)
void omap3_outer_cache_disable(void)
{
- /* Clear L2EN */
- omap3_update_aux_cr_secure(0, 0x2);
-
/*
+ * Clear L2EN
* On some revisions L2EN bit is banked on some revisions it's not
* No harm in clearing both banked bits(in fact this is required
* by an erratum)
ENDPROC(save_boot_params)
#endif
-ENTRY(omap3_gp_romcode_call)
- PUSH {r4-r12, lr} @ Save all registers from ROM code!
- MOV r12, r0 @ Copy the Service ID in R12
- MOV r0, r1 @ Copy parameter to R0
- mcr p15, 0, r0, c7, c10, 4 @ DSB
- mcr p15, 0, r0, c7, c10, 5 @ DMB
- .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
- @ because we use -march=armv5
- POP {r4-r12, pc}
-ENDPROC(omap3_gp_romcode_call)
-
/*
* Funtion for making PPA HAL API calls in secure devices
* Input:
#ifndef CONFIG_SYS_L2CACHE_OFF
void v7_outer_cache_enable(void)
{
- set_pl310_ctrl_reg(1);
+ omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
}
void v7_outer_cache_disable(void)
{
- set_pl310_ctrl_reg(0);
+ omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
(*ctrl)->control_emif2_sdram_config_ext);
}
+void init_cpu_configuration(void)
+{
+ u32 l2actlr;
+
+ asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
+ /*
+ * L2ACTLR: Ensure to enable the following:
+ * 3: Disable clean/evict push to external
+ * 4: Disable WriteUnique and WriteLineUnique transactions from master
+ * 8: Disable DVM/CMO message broadcast
+ */
+ l2actlr |= 0x118;
+ omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
+}
+
void init_omap_revision(void)
{
/*
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
+ init_cpu_configuration();
}
void reset_cpu(ulong ignored)
rst_val |= rst_time;
writel(rst_val, (*prcm)->prm_rsttime);
}
+
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev)
+{
+ omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
+}
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
- mov pc, lr @ back to my caller
+ mov r5, lr @ Store my Caller
+ mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
+ mov r3, r1, lsr #20 @ get variant field
+ and r3, r3, #0xf @ r3 has CPU variant
+ and r4, r1, #0xf @ r4 has CPU revision
+ mov r2, r3, lsl #4 @ shift variant field for combined value
+ orr r2, r4, r2 @ r2 has combined CPU variant + revision
+
+#ifdef CONFIG_ARM_ERRATA_798870
+ cmp r2, #0x30 @ Applies to lower than R3p0
+ bge skip_errata_798870 @ skip if not affected rev
+ cmp r2, #0x20 @ Applies to including and above R2p0
+ blt skip_errata_798870 @ skip if not affected rev
+
+ mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
+ orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_l2aux_ctrl
+ isb @ Recommended ISB after l2actlr update
+ pop {r1-r5} @ Restore the cpu info - fall through
+skip_errata_798870:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_454179
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_454179
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_454179:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_430973
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_430973
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x1 << 6) @ Set IBE bit
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_430973:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_621766
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_621766
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_621766:
+#endif
+
+ mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
return 0;
}
-int armv7_update_dt(void *fdt)
+int psci_update_dt(void *fdt)
{
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
if (!armv7_boot_nonsec())
return 0;
+#endif
#ifndef CONFIG_ARMV7_SECURE_BASE
/* secure code lives in RAM, keep it alive */
fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
for (i = 1; i <= itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
+ /*
+ * Relocate secure section before any cpu runs in secure ram.
+ * smp_kick_all_cpus may enable other cores and runs into secure
+ * ram, so need to relocate secure section before enabling other
+ * cores.
+ */
+ relocate_secure_section();
+
#ifndef CONFIG_ARMV7_PSCI
smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
smp_kick_all_cpus();
#endif
/* call the non-sec switching code on this CPU also */
- relocate_secure_section();
secure_ram_addr(_nonsec_init)();
return 0;
}
--- /dev/null
+if ARM64
+
+config ARMV8_MULTIENTRY
+ boolean "Enable multiple CPUs to enter into U-boot"
+
+endif
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
+ /* Apply ARM core specific erratas */
+ bl apply_core_errata
+
/*
* Cache/BPB/TLB Invalidate
* i-cache is invalidated before enabled in icache_enable()
/* Processor specific initialization */
bl lowlevel_init
+#ifdef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, master_cpu
/*
ldr x0, [x1]
cbz x0, slave_cpu
br x0 /* branch to the given address */
-
- /*
- * Master CPU
- */
master_cpu:
+ /* On the master CPU */
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
bl _main
/*-----------------------------------------------------------------------*/
+WEAK(apply_core_errata)
+
+ mov x29, lr /* Save LR */
+ /* For now, we support Cortex-A57 specific errata only */
+
+ /* Check if we are running on a Cortex-A57 core */
+ branch_if_a57_core x0, apply_a57_core_errata
+0:
+ mov lr, x29 /* Restore LR */
+ ret
+
+apply_a57_core_errata:
+
+#ifdef CONFIG_ARM_ERRATA_828024
+ mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
+ /* Disable non-allocate hint of w-b-n-a memory type */
+ mov x0, #0x1 << 49
+ /* Disable write streaming no L1-allocate threshold */
+ mov x0, #0x3 << 25
+ /* Disable write streaming no-allocate threshold */
+ mov x0, #0x3 << 27
+ msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_826974
+ mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
+ /* Disable speculative load execution ahead of a DMB */
+ mov x0, #0x1 << 59
+ msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_833069
+ mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
+ /* Disable Enable Invalidates of BTB bit */
+ and x0, x0, #0xE
+ msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+#endif
+ b 0b
+ENDPROC(apply_core_errata)
+
+/*-----------------------------------------------------------------------*/
+
WEAK(lowlevel_init)
mov x29, lr /* Save LR */
+#ifndef CONFIG_ARMV8_MULTIENTRY
+ /*
+ * For single-entry systems the lowlevel init is very simple.
+ */
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+
+#else /* CONFIG_ARMV8_MULTIENTRY is set */
+
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
bl armv8_switch_to_el1
#endif
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
2:
mov lr, x29 /* Restore LR */
ret
return id == CPU_VALUE_PXA27X;
}
+int cpu_is_pxa27xm(void)
+{
+ uint32_t id = pxa_get_cpuid();
+ return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) &&
+ ((id & CPU_MASK_PXA_REVID) == 8);
+}
+
uint32_t pxa_get_cpu_revision(void)
{
return pxa_get_cpuid() & CPU_MASK_PRODREV;
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
- if ((id == 5) || (id == 6) || (id > 7))
+ if ((id == 5) || (id == 6) || (id > 8))
return unknown;
/* Cap the special PXA270 C5 case. */
if (id == 7)
id = 5;
+ /* Cap the special PXA270M A1 case. */
+ if (id == 8)
+ id = 1;
+
return rev[id];
}
puts("Marvell PXA25x rev. ");
puts(pxa25x_get_revision());
} else if (cpu_is_pxa27x()) {
- puts("Marvell PXA27x rev. ");
+ puts("Marvell PXA27x");
+ if (cpu_is_pxa27xm()) puts("M");
+ puts(" rev. ");
puts(pxa27x_get_revision());
} else
return -EINVAL;
--- /dev/null
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+#define PIN(pin, f0, f1, f2, f3) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ PMUX_FUNC_##f2, \
+ PMUX_FUNC_##f3, \
+ }, \
+ }
+
+#define PIN_RESERVED {}
+
+static const struct pmux_pingrp_desc tegra210_pingroups[] = {
+ /* pin, f0, f1, f2, f3 */
+ /* Offset 0x3000 */
+ PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
+ PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
+ PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
+ PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
+ PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
+ PIN_RESERVED,
+ /* Offset 0x301c */
+ PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN_RESERVED,
+ /* Offset 0x3038 */
+ PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3),
+ PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3),
+ PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
+ PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3),
+ PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3),
+ PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3),
+ PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3),
+ PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3),
+ PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3),
+ PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3),
+ PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3),
+ PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3),
+ PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
+ PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN_RESERVED,
+ /* Offset 0x30a4 */
+ PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3),
+ PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3),
+ PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3),
+ PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3),
+ PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3),
+ PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3),
+ PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3),
+ PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3),
+ PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3),
+ PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3),
+ PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3),
+ PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3),
+ PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3),
+ PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3),
+ PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3),
+ PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3),
+ PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3),
+ PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3),
+ PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3),
+ PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3),
+ PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
+ PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
+ PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
+ PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
+ PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3),
+ PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3),
+ PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3),
+ PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3),
+ PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
+ PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
+ PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
+ PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
+ PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3),
+ PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3),
+ PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3),
+ PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3),
+ PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3),
+ PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3),
+ PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3),
+ PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3),
+ PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3),
+ PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3),
+ PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3),
+ PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3),
+ PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
+ PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
+ PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3),
+ PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3),
+ PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3),
+ PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3),
+ PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3),
+ PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3),
+ PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3),
+ PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3),
+ PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3),
+ PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3),
+ PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3),
+ PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3),
+ PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3),
+ PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3),
+ PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3),
+ PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3),
+ PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3),
+ PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3),
+ PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3),
+ PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3),
+ PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3),
+ PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3),
+ PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3),
+ PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3),
+ PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3),
+ PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3),
+ PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3),
+ PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3),
+ PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3),
+ PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1),
+ PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3),
+ PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(PA6, SATA, RSVD1, RSVD2, RSVD3),
+ PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3),
+ PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3),
+ PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3),
+ PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3),
+ PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3),
+ PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3),
+ PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3),
+ PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3),
+ PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3),
+ PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3),
+ PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
+ PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3),
+ PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
+ PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3),
+ PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
+ PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3),
+};
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;
zynq-zc770-xm013.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
-dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+dtb-$(CONFIG_SOCFPGA) += \
+ socfpga_arria5_socdk.dtb \
+ socfpga_cyclone5_socdk.dtb \
+ socfpga_cyclone5_socrates.dtb
targets += $(dtb-y)
--- /dev/null
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+ soc {
+ clkmgr@ffd04000 {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+
+ mmc0: dwmmc0@ff704000 {
+ num-slots = <1>;
+ broken-cd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ };
+
+ sysmgr@ffd08000 {
+ cpu1-start-addr = <0xffd080c4>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_arria5.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Arria V SoC Development Kit";
+ compatible = "altr,socfpga-arria5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+};
+
+&usb1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Cyclone V SoC Development Kit";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&mmc0 {
+ cd-gpios = <&portb 18 0>;
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+};
+
+&usb1 {
+ status = "okay";
+};
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000400";
sdhci2 = "/sdhci@78000000";
+ spi0 = "/spi@7000d400";
+ spi1 = "/spi@7000dc00";
+ spi2 = "/spi@7000de00";
+ spi3 = "/spi@7000da00";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d004000";
usb2 = "/usb@7d008000";
sdhci@78000000 {
status = "okay";
bus-width = <4>;
- cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
+ /* SD1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
};
sdhci@78000400 {
status = "okay";
bus-width = <8>;
- cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+ /* MMC1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
};
sdhci@78000600 {
usb@7d000000 {
status = "okay";
dr_mode = "peripheral";
+ /* USBO1_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
usb@7d004000 {
status = "okay";
+ /* USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
phy_type = "utmi";
};
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
usb@7d008000 {
status = "okay";
+ /* USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
};
sdhci@78000200 {
status = "okay";
bus-width = <4>;
- cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
};
sdhci@78000600 {
usb@7d004000 {
status = "okay";
phy_type = "utmi";
+ /* VBUS_LAN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
usb@7d008000 {
status = "okay";
+ /* USBH_PEN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
};
* Device Tree Source for UniPhier PH1-LD4 Reference Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "uniphier-ref-daughter.dtsi"
/ {
- model = "Panasonic UniPhier PH1-LD4 Reference Board";
- compatible = "panasonic,ph1-ld4-ref", "panasonic,ph1-ld4";
+ model = "UniPhier PH1-LD4 Reference Board";
+ compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4";
memory {
device_type = "memory";
* Device Tree Source for UniPhier PH1-LD4 SoC
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "skeleton.dtsi"
/ {
- compatible = "panasonic,ph1-ld4";
+ compatible = "socionext,ph1-ld4";
cpus {
#address-cells = <1>;
ranges;
uart0: serial@54006800 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x20>;
clock-frequency = <36864000>;
};
uart1: serial@54006900 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x20>;
clock-frequency = <36864000>;
};
uart2: serial@54006a00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x20>;
clock-frequency = <36864000>;
};
uart3: serial@54006b00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x20>;
clock-frequency = <36864000>;
};
i2c0: i2c@58400000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58400000 0x40>;
};
i2c1: i2c@58480000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58480000 0x40>;
};
i2c2: i2c@58500000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58500000 0x40>;
};
i2c3: i2c@58580000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58580000 0x40>;
};
usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
* Device Tree Source for UniPhier PH1-Pro4 Reference Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "uniphier-ref-daughter.dtsi"
/ {
- model = "Panasonic UniPhier PH1-Pro4 Reference Board";
- compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4";
+ model = "UniPhier PH1-Pro4 Reference Board";
+ compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4";
memory {
device_type = "memory";
* Device Tree Source for UniPhier PH1-Pro4 SoC
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "skeleton.dtsi"
/ {
- compatible = "panasonic,ph1-pro4";
+ compatible = "socionext,ph1-pro4";
cpus {
#address-cells = <1>;
ranges;
uart0: serial@54006800 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x20>;
clock-frequency = <73728000>;
};
uart1: serial@54006900 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x20>;
clock-frequency = <73728000>;
};
uart2: serial@54006a00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x20>;
clock-frequency = <73728000>;
};
uart3: serial@54006b00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x20>;
clock-frequency = <73728000>;
};
i2c0: i2c@58780000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58780000 0x80>;
};
i2c1: i2c@58781000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58781000 0x80>;
};
i2c2: i2c@58782000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58782000 0x80>;
};
i2c3: i2c@58783000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58783000 0x80>;
/* i2c4 does not exist */
i2c5: i2c@58785000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58785000 0x80>;
};
i2c6: i2c@58786000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58786000 0x80>;
};
usb2: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb3: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb0: usb@65a00000 {
- compatible = "panasonic,uniphier-xhci", "generic-xhci";
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
status = "disabled";
reg = <0x65a00000 0x100>;
};
usb1: usb@65c00000 {
- compatible = "panasonic,uniphier-xhci", "generic-xhci";
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
status = "disabled";
reg = <0x65c00000 0x100>;
};
* Device Tree Source for UniPhier PH1-sLD3 Reference Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "uniphier-ref-daughter.dtsi"
/ {
- model = "Panasonic UniPhier PH1-sLD3 Reference Board";
- compatible = "panasonic,ph1-sld3-ref", "panasonic,ph1-sld3";
+ model = "UniPhier PH1-sLD3 Reference Board";
+ compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3";
memory {
device_type = "memory";
* Device Tree Source for UniPhier PH1-sLD3 SoC
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "skeleton.dtsi"
/ {
- compatible = "panasonic,ph1-sld3";
+ compatible = "socionext,ph1-sld3";
cpus {
#address-cells = <1>;
ranges;
uart0: serial@54006800 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x20>;
clock-frequency = <36864000>;
};
uart1: serial@54006900 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x20>;
clock-frequency = <36864000>;
};
uart2: serial@54006a00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x20>;
clock-frequency = <36864000>;
};
i2c0: i2c@58400000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58400000 0x40>;
};
i2c1: i2c@58480000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58480000 0x40>;
};
i2c2: i2c@58500000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58500000 0x40>;
};
i2c3: i2c@58580000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58580000 0x40>;
};
usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
usb3: usb@5a830100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a830100 0x100>;
};
* Device Tree Source for UniPhier PH1-sLD8 Reference Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "uniphier-ref-daughter.dtsi"
/ {
- model = "Panasonic UniPhier PH1-sLD8 Reference Board";
- compatible = "panasonic,ph1-sld8-ref", "panasonic,ph1-sld8";
+ model = "UniPhier PH1-sLD8 Reference Board";
+ compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8";
memory {
device_type = "memory";
* Device Tree Source for UniPhier PH1-sLD8 SoC
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "skeleton.dtsi"
/ {
- compatible = "panasonic,ph1-sld8";
+ compatible = "socionext,ph1-sld8";
cpus {
#address-cells = <1>;
ranges;
uart0: serial@54006800 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x20>;
clock-frequency = <80000000>;
};
uart1: serial@54006900 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x20>;
clock-frequency = <80000000>;
};
uart2: serial@54006a00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x20>;
clock-frequency = <80000000>;
};
uart3: serial@54006b00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x20>;
clock-frequency = <80000000>;
};
i2c0: i2c@58400000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58400000 0x40>;
};
i2c1: i2c@58480000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58480000 0x40>;
};
i2c2: i2c@58500000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58500000 0x40>;
};
i2c3: i2c@58580000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58580000 0x40>;
};
usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
* Device Tree Source for UniPhier Reference Daughter Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
+#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
+#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_DCU_BE
+#define CONFIG_SYS_FSL_SEC_MON_LE
#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+#define CONFIG_FSL_ISBC_KEY_EXT
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_DM
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
+#endif
#define DCU_LAYER_MAX_NUM 16
void dieid_num_r(void);
void get_dieid(u32 *id);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
-void omap3_gp_romcode_call(u32 service_id, u32 parameter);
+void omap3_set_aux_cr_secure(u32 acr);
u32 warm_reset(void);
#endif
void set_muxconf_regs_essential(void);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
-void set_pl310_ctrl_reg(u32 val);
void setup_clocks_for_console(void);
void prcm_init(void);
void bypass_dpll(u32 const base);
u32 warm_reset(void);
void force_emif_self_refresh(void);
void setup_warmreset_time(void);
+
+#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102
+
#endif
{
return div_round_up(32768 * usec, 1000000);
}
+
+#define OMAP5_SERVICE_L2ACTLR_SET 0x104
+
#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NOR 1
{
}
#endif
+
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+bool tegra_cpu_is_non_secure(void);
+#endif
PMUX_TRI_TRISTATE = 1,
};
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
enum pmux_pin_io {
PMUX_PIN_OUTPUT = 0,
PMUX_PIN_INPUT = 1,
PMUX_PIN_NONE,
};
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
enum pmux_pin_lock {
PMUX_PIN_LOCK_DEFAULT = 0,
PMUX_PIN_LOCK_DISABLE,
PMUX_PIN_LOCK_ENABLE,
};
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
enum pmux_pin_od {
PMUX_PIN_OD_DEFAULT = 0,
PMUX_PIN_OD_DISABLE,
PMUX_PIN_OD_ENABLE,
};
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
enum pmux_pin_ioreset {
PMUX_PIN_IO_RESET_DEFAULT = 0,
PMUX_PIN_IO_RESET_DISABLE,
PMUX_PIN_IO_RESET_ENABLE,
};
+#endif
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
enum pmux_pin_rcv_sel {
PMUX_PIN_RCV_SEL_DEFAULT = 0,
PMUX_PIN_RCV_SEL_NORMAL,
PMUX_PIN_RCV_SEL_HIGH,
};
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+enum pmux_pin_e_io_hv {
+ PMUX_PIN_E_IO_HV_DEFAULT = 0,
+ PMUX_PIN_E_IO_HV_NORMAL,
+ PMUX_PIN_E_IO_HV_HIGH,
+};
+#endif
+
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
+/* Defines a pin group cfg's low-power mode select */
+enum pmux_lpmd {
+ PMUX_LPMD_X8 = 0,
+ PMUX_LPMD_X4,
+ PMUX_LPMD_X2,
+ PMUX_LPMD_X,
+ PMUX_LPMD_NONE = -1,
+};
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pmux_schmt {
+ PMUX_SCHMT_DISABLE = 0,
+ PMUX_SCHMT_ENABLE = 1,
+ PMUX_SCHMT_NONE = -1,
+};
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pmux_hsm {
+ PMUX_HSM_DISABLE = 0,
+ PMUX_HSM_ENABLE = 1,
+ PMUX_HSM_NONE = -1,
+};
+#endif
/*
* This defines the configuration for a pin, including the function assigned,
u32 func:8; /* function to assign PMUX_FUNC_... */
u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
u32 tristate:2; /* tristate or normal PMUX_TRI_... */
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
u32 io:2; /* input or output PMUX_PIN_... */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
u32 lock:2; /* lock enable/disable PMUX_PIN... */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
u32 od:2; /* open-drain or push-pull driver */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
u32 ioreset:2; /* input/output reset PMUX_PIN... */
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
u32 rcv_sel:2; /* select between High and Normal */
/* VIL/VIH receivers */
#endif
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+ u32 e_io_hv:2; /* select 3.3v tolerant receivers */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+ u32 schmt:2; /* schmitt enable */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+ u32 hsm:2; /* high-speed mode enable */
#endif
};
-#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
-/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
+#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
+/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
void pinmux_set_tristate_input_clamping(void);
+void pinmux_clear_tristate_input_clamping(void);
#endif
/* Set the mux function for a pin group */
/* Set a pin group to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pingrp pin);
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
/* Set a pin group as input or output */
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
#endif
void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
int len);
-#ifdef TEGRA_PMX_HAS_DRVGRPS
+#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
#define PMUX_SLWF_MIN 0
#define PMUX_SLWF_MAX 3
#define PMUX_DRVDN_MAX 127
#define PMUX_DRVDN_NONE -1
-/* Defines a pin group cfg's low-power mode select */
-enum pmux_lpmd {
- PMUX_LPMD_X8 = 0,
- PMUX_LPMD_X4,
- PMUX_LPMD_X2,
- PMUX_LPMD_X,
- PMUX_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pmux_schmt {
- PMUX_SCHMT_DISABLE = 0,
- PMUX_SCHMT_ENABLE = 1,
- PMUX_SCHMT_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pmux_hsm {
- PMUX_HSM_DISABLE = 0,
- PMUX_HSM_ENABLE = 1,
- PMUX_HSM_NONE = -1,
-};
-
/*
* This defines the configuration for a pin group's pad control config
*/
u32 slwr:3; /* rising edge slew */
u32 drvup:8; /* pull-up drive strength */
u32 drvdn:8; /* pull-down drive strength */
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
u32 lpmd:3; /* low-power mode selection */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
u32 schmt:2; /* schmidt enable */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
u32 hsm:2; /* high-speed mode enable */
+#endif
};
/**
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
int len);
-#endif /* TEGRA_PMX_HAS_DRVGRPS */
+#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
struct pmux_pingrp_desc {
u8 funcs[4];
PMUX_FUNC_COUNT,
};
-#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_RCV_SEL
-#define TEGRA_PMX_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
+#define TEGRA_PMX_PINS_HAVE_RCV_SEL
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA114_PINMUX_H_ */
PMUX_FUNC_COUNT,
};
-#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_RCV_SEL
-#define TEGRA_PMX_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
+#define TEGRA_PMX_PINS_HAVE_RCV_SEL
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA124_PINMUX_H_ */
PMUX_FUNC_COUNT,
};
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA20_PINMUX_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_PINMUX_H_
+#define _TEGRA210_PINMUX_H_
+
+enum pmux_pingrp {
+ PMUX_PINGRP_SDMMC1_CLK_PM0,
+ PMUX_PINGRP_SDMMC1_CMD_PM1,
+ PMUX_PINGRP_SDMMC1_DAT3_PM2,
+ PMUX_PINGRP_SDMMC1_DAT2_PM3,
+ PMUX_PINGRP_SDMMC1_DAT1_PM4,
+ PMUX_PINGRP_SDMMC1_DAT0_PM5,
+ PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4),
+ PMUX_PINGRP_SDMMC3_CMD_PP1,
+ PMUX_PINGRP_SDMMC3_DAT0_PP5,
+ PMUX_PINGRP_SDMMC3_DAT1_PP4,
+ PMUX_PINGRP_SDMMC3_DAT2_PP3,
+ PMUX_PINGRP_SDMMC3_DAT3_PP2,
+ PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4),
+ PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1,
+ PMUX_PINGRP_PEX_WAKE_N_PA2,
+ PMUX_PINGRP_PEX_L1_RST_N_PA3,
+ PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4,
+ PMUX_PINGRP_SATA_LED_ACTIVE_PA5,
+ PMUX_PINGRP_SPI1_MOSI_PC0,
+ PMUX_PINGRP_SPI1_MISO_PC1,
+ PMUX_PINGRP_SPI1_SCK_PC2,
+ PMUX_PINGRP_SPI1_CS0_PC3,
+ PMUX_PINGRP_SPI1_CS1_PC4,
+ PMUX_PINGRP_SPI2_MOSI_PB4,
+ PMUX_PINGRP_SPI2_MISO_PB5,
+ PMUX_PINGRP_SPI2_SCK_PB6,
+ PMUX_PINGRP_SPI2_CS0_PB7,
+ PMUX_PINGRP_SPI2_CS1_PDD0,
+ PMUX_PINGRP_SPI4_MOSI_PC7,
+ PMUX_PINGRP_SPI4_MISO_PD0,
+ PMUX_PINGRP_SPI4_SCK_PC5,
+ PMUX_PINGRP_SPI4_CS0_PC6,
+ PMUX_PINGRP_QSPI_SCK_PEE0,
+ PMUX_PINGRP_QSPI_CS_N_PEE1,
+ PMUX_PINGRP_QSPI_IO0_PEE2,
+ PMUX_PINGRP_QSPI_IO1_PEE3,
+ PMUX_PINGRP_QSPI_IO2_PEE4,
+ PMUX_PINGRP_QSPI_IO3_PEE5,
+ PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4),
+ PMUX_PINGRP_DMIC1_DAT_PE1,
+ PMUX_PINGRP_DMIC2_CLK_PE2,
+ PMUX_PINGRP_DMIC2_DAT_PE3,
+ PMUX_PINGRP_DMIC3_CLK_PE4,
+ PMUX_PINGRP_DMIC3_DAT_PE5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PJ1,
+ PMUX_PINGRP_GEN1_I2C_SDA_PJ0,
+ PMUX_PINGRP_GEN2_I2C_SCL_PJ2,
+ PMUX_PINGRP_GEN2_I2C_SDA_PJ3,
+ PMUX_PINGRP_GEN3_I2C_SCL_PF0,
+ PMUX_PINGRP_GEN3_I2C_SDA_PF1,
+ PMUX_PINGRP_CAM_I2C_SCL_PS2,
+ PMUX_PINGRP_CAM_I2C_SDA_PS3,
+ PMUX_PINGRP_PWR_I2C_SCL_PY3,
+ PMUX_PINGRP_PWR_I2C_SDA_PY4,
+ PMUX_PINGRP_UART1_TX_PU0,
+ PMUX_PINGRP_UART1_RX_PU1,
+ PMUX_PINGRP_UART1_RTS_PU2,
+ PMUX_PINGRP_UART1_CTS_PU3,
+ PMUX_PINGRP_UART2_TX_PG0,
+ PMUX_PINGRP_UART2_RX_PG1,
+ PMUX_PINGRP_UART2_RTS_PG2,
+ PMUX_PINGRP_UART2_CTS_PG3,
+ PMUX_PINGRP_UART3_TX_PD1,
+ PMUX_PINGRP_UART3_RX_PD2,
+ PMUX_PINGRP_UART3_RTS_PD3,
+ PMUX_PINGRP_UART3_CTS_PD4,
+ PMUX_PINGRP_UART4_TX_PI4,
+ PMUX_PINGRP_UART4_RX_PI5,
+ PMUX_PINGRP_UART4_RTS_PI6,
+ PMUX_PINGRP_UART4_CTS_PI7,
+ PMUX_PINGRP_DAP1_FS_PB0,
+ PMUX_PINGRP_DAP1_DIN_PB1,
+ PMUX_PINGRP_DAP1_DOUT_PB2,
+ PMUX_PINGRP_DAP1_SCLK_PB3,
+ PMUX_PINGRP_DAP2_FS_PAA0,
+ PMUX_PINGRP_DAP2_DIN_PAA2,
+ PMUX_PINGRP_DAP2_DOUT_PAA3,
+ PMUX_PINGRP_DAP2_SCLK_PAA1,
+ PMUX_PINGRP_DAP4_FS_PJ4,
+ PMUX_PINGRP_DAP4_DIN_PJ5,
+ PMUX_PINGRP_DAP4_DOUT_PJ6,
+ PMUX_PINGRP_DAP4_SCLK_PJ7,
+ PMUX_PINGRP_CAM1_MCLK_PS0,
+ PMUX_PINGRP_CAM2_MCLK_PS1,
+ PMUX_PINGRP_JTAG_RTCK,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_CLK_32K_OUT_PY5,
+ PMUX_PINGRP_BATT_BCL,
+ PMUX_PINGRP_CLK_REQ,
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_SHUTDOWN,
+ PMUX_PINGRP_CORE_PWR_REQ,
+ PMUX_PINGRP_AUD_MCLK_PBB0,
+ PMUX_PINGRP_DVFS_PWM_PBB1,
+ PMUX_PINGRP_DVFS_CLK_PBB2,
+ PMUX_PINGRP_GPIO_X1_AUD_PBB3,
+ PMUX_PINGRP_GPIO_X3_AUD_PBB4,
+ PMUX_PINGRP_PCC7,
+ PMUX_PINGRP_HDMI_CEC_PCC0,
+ PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1,
+ PMUX_PINGRP_SPDIF_OUT_PCC2,
+ PMUX_PINGRP_SPDIF_IN_PCC3,
+ PMUX_PINGRP_USB_VBUS_EN0_PCC4,
+ PMUX_PINGRP_USB_VBUS_EN1_PCC5,
+ PMUX_PINGRP_DP_HPD0_PCC6,
+ PMUX_PINGRP_WIFI_EN_PH0,
+ PMUX_PINGRP_WIFI_RST_PH1,
+ PMUX_PINGRP_WIFI_WAKE_AP_PH2,
+ PMUX_PINGRP_AP_WAKE_BT_PH3,
+ PMUX_PINGRP_BT_RST_PH4,
+ PMUX_PINGRP_BT_WAKE_AP_PH5,
+ PMUX_PINGRP_AP_WAKE_NFC_PH7,
+ PMUX_PINGRP_NFC_EN_PI0,
+ PMUX_PINGRP_NFC_INT_PI1,
+ PMUX_PINGRP_GPS_EN_PI2,
+ PMUX_PINGRP_GPS_RST_PI3,
+ PMUX_PINGRP_CAM_RST_PS4,
+ PMUX_PINGRP_CAM_AF_EN_PS5,
+ PMUX_PINGRP_CAM_FLASH_EN_PS6,
+ PMUX_PINGRP_CAM1_PWDN_PS7,
+ PMUX_PINGRP_CAM2_PWDN_PT0,
+ PMUX_PINGRP_CAM1_STROBE_PT1,
+ PMUX_PINGRP_LCD_TE_PY2,
+ PMUX_PINGRP_LCD_BL_PWM_PV0,
+ PMUX_PINGRP_LCD_BL_EN_PV1,
+ PMUX_PINGRP_LCD_RST_PV2,
+ PMUX_PINGRP_LCD_GPIO1_PV3,
+ PMUX_PINGRP_LCD_GPIO2_PV4,
+ PMUX_PINGRP_AP_READY_PV5,
+ PMUX_PINGRP_TOUCH_RST_PV6,
+ PMUX_PINGRP_TOUCH_CLK_PV7,
+ PMUX_PINGRP_MODEM_WAKE_AP_PX0,
+ PMUX_PINGRP_TOUCH_INT_PX1,
+ PMUX_PINGRP_MOTION_INT_PX2,
+ PMUX_PINGRP_ALS_PROX_INT_PX3,
+ PMUX_PINGRP_TEMP_ALERT_PX4,
+ PMUX_PINGRP_BUTTON_POWER_ON_PX5,
+ PMUX_PINGRP_BUTTON_VOL_UP_PX6,
+ PMUX_PINGRP_BUTTON_VOL_DOWN_PX7,
+ PMUX_PINGRP_BUTTON_SLIDE_SW_PY0,
+ PMUX_PINGRP_BUTTON_HOME_PY1,
+ PMUX_PINGRP_PA6,
+ PMUX_PINGRP_PE6,
+ PMUX_PINGRP_PE7,
+ PMUX_PINGRP_PH6,
+ PMUX_PINGRP_PK0,
+ PMUX_PINGRP_PK1,
+ PMUX_PINGRP_PK2,
+ PMUX_PINGRP_PK3,
+ PMUX_PINGRP_PK4,
+ PMUX_PINGRP_PK5,
+ PMUX_PINGRP_PK6,
+ PMUX_PINGRP_PK7,
+ PMUX_PINGRP_PL0,
+ PMUX_PINGRP_PL1,
+ PMUX_PINGRP_PZ0,
+ PMUX_PINGRP_PZ1,
+ PMUX_PINGRP_PZ2,
+ PMUX_PINGRP_PZ3,
+ PMUX_PINGRP_PZ4,
+ PMUX_PINGRP_PZ5,
+ PMUX_PINGRP_COUNT,
+};
+
+enum pmux_drvgrp {
+ PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4),
+ PMUX_DRVGRP_AP_READY,
+ PMUX_DRVGRP_AP_WAKE_BT,
+ PMUX_DRVGRP_AP_WAKE_NFC,
+ PMUX_DRVGRP_AUD_MCLK,
+ PMUX_DRVGRP_BATT_BCL,
+ PMUX_DRVGRP_BT_RST,
+ PMUX_DRVGRP_BT_WAKE_AP,
+ PMUX_DRVGRP_BUTTON_HOME,
+ PMUX_DRVGRP_BUTTON_POWER_ON,
+ PMUX_DRVGRP_BUTTON_SLIDE_SW,
+ PMUX_DRVGRP_BUTTON_VOL_DOWN,
+ PMUX_DRVGRP_BUTTON_VOL_UP,
+ PMUX_DRVGRP_CAM1_MCLK,
+ PMUX_DRVGRP_CAM1_PWDN,
+ PMUX_DRVGRP_CAM1_STROBE,
+ PMUX_DRVGRP_CAM2_MCLK,
+ PMUX_DRVGRP_CAM2_PWDN,
+ PMUX_DRVGRP_CAM_AF_EN,
+ PMUX_DRVGRP_CAM_FLASH_EN,
+ PMUX_DRVGRP_CAM_I2C_SCL,
+ PMUX_DRVGRP_CAM_I2C_SDA,
+ PMUX_DRVGRP_CAM_RST,
+ PMUX_DRVGRP_CLK_32K_IN,
+ PMUX_DRVGRP_CLK_32K_OUT,
+ PMUX_DRVGRP_CLK_REQ,
+ PMUX_DRVGRP_CORE_PWR_REQ,
+ PMUX_DRVGRP_CPU_PWR_REQ,
+ PMUX_DRVGRP_DAP1_DIN,
+ PMUX_DRVGRP_DAP1_DOUT,
+ PMUX_DRVGRP_DAP1_FS,
+ PMUX_DRVGRP_DAP1_SCLK,
+ PMUX_DRVGRP_DAP2_DIN,
+ PMUX_DRVGRP_DAP2_DOUT,
+ PMUX_DRVGRP_DAP2_FS,
+ PMUX_DRVGRP_DAP2_SCLK,
+ PMUX_DRVGRP_DAP4_DIN,
+ PMUX_DRVGRP_DAP4_DOUT,
+ PMUX_DRVGRP_DAP4_FS,
+ PMUX_DRVGRP_DAP4_SCLK,
+ PMUX_DRVGRP_DMIC1_CLK,
+ PMUX_DRVGRP_DMIC1_DAT,
+ PMUX_DRVGRP_DMIC2_CLK,
+ PMUX_DRVGRP_DMIC2_DAT,
+ PMUX_DRVGRP_DMIC3_CLK,
+ PMUX_DRVGRP_DMIC3_DAT,
+ PMUX_DRVGRP_DP_HPD0,
+ PMUX_DRVGRP_DVFS_CLK,
+ PMUX_DRVGRP_DVFS_PWM,
+ PMUX_DRVGRP_GEN1_I2C_SCL,
+ PMUX_DRVGRP_GEN1_I2C_SDA,
+ PMUX_DRVGRP_GEN2_I2C_SCL,
+ PMUX_DRVGRP_GEN2_I2C_SDA,
+ PMUX_DRVGRP_GEN3_I2C_SCL,
+ PMUX_DRVGRP_GEN3_I2C_SDA,
+ PMUX_DRVGRP_PA6,
+ PMUX_DRVGRP_PCC7,
+ PMUX_DRVGRP_PE6,
+ PMUX_DRVGRP_PE7,
+ PMUX_DRVGRP_PH6,
+ PMUX_DRVGRP_PK0,
+ PMUX_DRVGRP_PK1,
+ PMUX_DRVGRP_PK2,
+ PMUX_DRVGRP_PK3,
+ PMUX_DRVGRP_PK4,
+ PMUX_DRVGRP_PK5,
+ PMUX_DRVGRP_PK6,
+ PMUX_DRVGRP_PK7,
+ PMUX_DRVGRP_PL0,
+ PMUX_DRVGRP_PL1,
+ PMUX_DRVGRP_PZ0,
+ PMUX_DRVGRP_PZ1,
+ PMUX_DRVGRP_PZ2,
+ PMUX_DRVGRP_PZ3,
+ PMUX_DRVGRP_PZ4,
+ PMUX_DRVGRP_PZ5,
+ PMUX_DRVGRP_GPIO_X1_AUD,
+ PMUX_DRVGRP_GPIO_X3_AUD,
+ PMUX_DRVGRP_GPS_EN,
+ PMUX_DRVGRP_GPS_RST,
+ PMUX_DRVGRP_HDMI_CEC,
+ PMUX_DRVGRP_HDMI_INT_DP_HPD,
+ PMUX_DRVGRP_JTAG_RTCK,
+ PMUX_DRVGRP_LCD_BL_EN,
+ PMUX_DRVGRP_LCD_BL_PWM,
+ PMUX_DRVGRP_LCD_GPIO1,
+ PMUX_DRVGRP_LCD_GPIO2,
+ PMUX_DRVGRP_LCD_RST,
+ PMUX_DRVGRP_LCD_TE,
+ PMUX_DRVGRP_MODEM_WAKE_AP,
+ PMUX_DRVGRP_MOTION_INT,
+ PMUX_DRVGRP_NFC_EN,
+ PMUX_DRVGRP_NFC_INT,
+ PMUX_DRVGRP_PEX_L0_CLKREQ_N,
+ PMUX_DRVGRP_PEX_L0_RST_N,
+ PMUX_DRVGRP_PEX_L1_CLKREQ_N,
+ PMUX_DRVGRP_PEX_L1_RST_N,
+ PMUX_DRVGRP_PEX_WAKE_N,
+ PMUX_DRVGRP_PWR_I2C_SCL,
+ PMUX_DRVGRP_PWR_I2C_SDA,
+ PMUX_DRVGRP_PWR_INT_N,
+ PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4),
+ PMUX_DRVGRP_SATA_LED_ACTIVE,
+ PMUX_DRVGRP_SDMMC1,
+ PMUX_DRVGRP_SDMMC2,
+ PMUX_DRVGRP_SDMMC3 = (0x1dc / 4),
+ PMUX_DRVGRP_SDMMC4,
+ PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4),
+ PMUX_DRVGRP_SPDIF_IN,
+ PMUX_DRVGRP_SPDIF_OUT,
+ PMUX_DRVGRP_SPI1_CS0,
+ PMUX_DRVGRP_SPI1_CS1,
+ PMUX_DRVGRP_SPI1_MISO,
+ PMUX_DRVGRP_SPI1_MOSI,
+ PMUX_DRVGRP_SPI1_SCK,
+ PMUX_DRVGRP_SPI2_CS0,
+ PMUX_DRVGRP_SPI2_CS1,
+ PMUX_DRVGRP_SPI2_MISO,
+ PMUX_DRVGRP_SPI2_MOSI,
+ PMUX_DRVGRP_SPI2_SCK,
+ PMUX_DRVGRP_SPI4_CS0,
+ PMUX_DRVGRP_SPI4_MISO,
+ PMUX_DRVGRP_SPI4_MOSI,
+ PMUX_DRVGRP_SPI4_SCK,
+ PMUX_DRVGRP_TEMP_ALERT,
+ PMUX_DRVGRP_TOUCH_CLK,
+ PMUX_DRVGRP_TOUCH_INT,
+ PMUX_DRVGRP_TOUCH_RST,
+ PMUX_DRVGRP_UART1_CTS,
+ PMUX_DRVGRP_UART1_RTS,
+ PMUX_DRVGRP_UART1_RX,
+ PMUX_DRVGRP_UART1_TX,
+ PMUX_DRVGRP_UART2_CTS,
+ PMUX_DRVGRP_UART2_RTS,
+ PMUX_DRVGRP_UART2_RX,
+ PMUX_DRVGRP_UART2_TX,
+ PMUX_DRVGRP_UART3_CTS,
+ PMUX_DRVGRP_UART3_RTS,
+ PMUX_DRVGRP_UART3_RX,
+ PMUX_DRVGRP_UART3_TX,
+ PMUX_DRVGRP_UART4_CTS,
+ PMUX_DRVGRP_UART4_RTS,
+ PMUX_DRVGRP_UART4_RX,
+ PMUX_DRVGRP_UART4_TX,
+ PMUX_DRVGRP_USB_VBUS_EN0,
+ PMUX_DRVGRP_USB_VBUS_EN1,
+ PMUX_DRVGRP_WIFI_EN,
+ PMUX_DRVGRP_WIFI_RST,
+ PMUX_DRVGRP_WIFI_WAKE_AP,
+ PMUX_DRVGRP_COUNT,
+};
+
+enum pmux_func {
+ PMUX_FUNC_DEFAULT,
+ PMUX_FUNC_AUD,
+ PMUX_FUNC_BCL,
+ PMUX_FUNC_BLINK,
+ PMUX_FUNC_CCLA,
+ PMUX_FUNC_CEC,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_CLK,
+ PMUX_FUNC_CORE,
+ PMUX_FUNC_CPU,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYB,
+ PMUX_FUNC_DMIC1,
+ PMUX_FUNC_DMIC2,
+ PMUX_FUNC_DMIC3,
+ PMUX_FUNC_DP,
+ PMUX_FUNC_DTV,
+ PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
+ PMUX_FUNC_I2CPMU,
+ PMUX_FUNC_I2CVI,
+ PMUX_FUNC_I2S1,
+ PMUX_FUNC_I2S2,
+ PMUX_FUNC_I2S3,
+ PMUX_FUNC_I2S4A,
+ PMUX_FUNC_I2S4B,
+ PMUX_FUNC_I2S5A,
+ PMUX_FUNC_I2S5B,
+ PMUX_FUNC_IQC0,
+ PMUX_FUNC_IQC1,
+ PMUX_FUNC_JTAG,
+ PMUX_FUNC_PE,
+ PMUX_FUNC_PE0,
+ PMUX_FUNC_PE1,
+ PMUX_FUNC_PMI,
+ PMUX_FUNC_PWM0,
+ PMUX_FUNC_PWM1,
+ PMUX_FUNC_PWM2,
+ PMUX_FUNC_PWM3,
+ PMUX_FUNC_QSPI,
+ PMUX_FUNC_SATA,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SHUTDOWN,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_SOR0,
+ PMUX_FUNC_SOR1,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
+ PMUX_FUNC_SYS,
+ PMUX_FUNC_TOUCH,
+ PMUX_FUNC_UART,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_USB,
+ PMUX_FUNC_VGP1,
+ PMUX_FUNC_VGP2,
+ PMUX_FUNC_VGP3,
+ PMUX_FUNC_VGP4,
+ PMUX_FUNC_VGP5,
+ PMUX_FUNC_VGP6,
+ PMUX_FUNC_VIMCLK,
+ PMUX_FUNC_VIMCLK2,
+ PMUX_FUNC_RSVD0,
+ PMUX_FUNC_RSVD1,
+ PMUX_FUNC_RSVD2,
+ PMUX_FUNC_RSVD3,
+ PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_E_IO_HV
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA210_PINMUX_H_ */
PMUX_FUNC_COUNT,
};
-#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA30_PINMUX_H_ */
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
int armv7_init_nonsec(void);
-int armv7_update_dt(void *fdt);
bool armv7_boot_nonsec(void);
/* defined in assembly file */
#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev);
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev);
#endif /* ! __ASSEMBLY__ */
#endif
b.eq \el1_label
.endm
+/*
+ * Branch if current processor is a Cortex-A57 core.
+ */
+.macro branch_if_a57_core, xreg, a57_label
+ mrs \xreg, midr_el1
+ lsr \xreg, \xreg, #4
+ and \xreg, \xreg, #0x00000FFF
+ cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
+ b.eq \a57_label
+.endm
+
+/*
+ * Branch if current processor is a Cortex-A53 core.
+ */
+.macro branch_if_a53_core, xreg, a53_label
+ mrs \xreg, midr_el1
+ lsr \xreg, \xreg, #4
+ and \xreg, \xreg, #0x00000FFF
+ cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
+ b.eq \a53_label
+.endm
+
/*
* Branch if current processor is a slave,
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_slave, xreg, slave_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg, mpidr_el1
tst \xreg, #0xff /* Test Affinity 0 */
b.ne \slave_label
lsr \xreg, \xreg, #16
tst \xreg, #0xff /* Test Affinity 3 */
b.ne \slave_label
+#endif
.endm
/*
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_master, xreg1, xreg2, master_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg1, mpidr_el1
lsr \xreg2, \xreg1, #32
lsl \xreg1, \xreg1, #40
lsr \xreg1, \xreg1, #40
orr \xreg1, \xreg1, \xreg2
cbz \xreg1, \master_label
+#else
+ b \master_label
+#endif
.endm
.macro armv8_switch_to_el2_m, xreg1
void usb_fake_mac_from_die_id(u32 *id);
+void omap_smc1(u32 service, u32 val);
+
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
#define OMAP_ABB_FAST_OPP 1
#define ARM_PSCI_RET_INVAL (-2)
#define ARM_PSCI_RET_DENIED (-3)
+#ifndef __ASSEMBLY__
+int psci_update_dt(void *fdt);
+#endif /* ! __ASSEMBLY__ */
+
#endif /* __ARM_PSCI_H__ */
#include <common.h>
#include <fdt_support.h>
-#include <asm/armv7.h>
+#include <asm/psci.h>
DECLARE_GLOBAL_DATA_PTR;
if (ret)
return ret;
- ret = armv7_update_dt(blob);
+ ret = psci_update_dt(blob);
#endif
return ret;
}
movne sp, r0
# endif
ldr r0, =__bss_start /* this is auto-relocated! */
- ldr r1, =__bss_end /* this is auto-relocated! */
+#ifdef CONFIG_USE_ARCH_MEMSET
+ ldr r3, =__bss_end /* this is auto-relocated! */
+ mov r1, #0x00000000 /* prepare zero to clear BSS */
+
+ subs r2, r3, r0 /* r2 = memset len */
+ bl memset
+#else
+ ldr r1, =__bss_end /* this is auto-relocated! */
mov r2, #0x00000000 /* prepare zero to clear BSS */
clbss_l:cmp r0, r1 /* while not at end of BSS */
strlo r2, [r0] /* clear 32-bit BSS word */
addlo r0, r0, #4 /* move to next */
blo clbss_l
+#endif
#if ! defined(CONFIG_SPL_BUILD)
bl coloured_LED_init
flags = condition_codes (regs);
- printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
- "sp : %08lx ip : %08lx fp : %08lx\n",
- instruction_pointer (regs),
- regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+ printf("pc : [<%08lx>] lr : [<%08lx>]\n",
+ instruction_pointer(regs), regs->ARM_lr);
+ if (gd->flags & GD_FLG_RELOC) {
+ printf("reloc pc : [<%08lx>] lr : [<%08lx>]\n",
+ instruction_pointer(regs) - gd->reloc_off,
+ regs->ARM_lr - gd->reloc_off);
+ }
+ printf("sp : %08lx ip : %08lx fp : %08lx\n",
+ regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
config TARGET_EDMINIV2
bool "LaCie Ethernet Disk mini V2"
+ select SUPPORT_SPL
endchoice
/* Enable and invalidate L2 cache in write through mode */
invalidate_l2_cache();
+#ifdef CONFIG_SPL_BUILD
orion5x_config_adr_windows();
+#endif
return 0;
}
#endif
#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
-#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000
+#define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000
#endif
#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
/*
* Low-level init happens right after start.S has switched to SVC32,
* flushed and disabled caches and disabled MMU. We're still running
- * from the boot chip select, so the first thing we should do is set
- * up RAM for us to relocate into.
+ * from the boot chip select, so the first thing SPL should do is to
+ * set up the RAM to copy U-Boot into.
*/
.globl lowlevel_init
lowlevel_init:
+#ifdef CONFIG_SPL_BUILD
+
/* Use 'r4 as the base for internal register accesses */
ldr r4, =ORION5X_REGS_PHY_BASE
orr r2, r2, r6
str r2, [r3, #0x484]
+ /* enable for 2 GB DDR; detection should find out real amount */
+ sub r6, r6, r6
+ str r6, [r3, #0x500]
+ ldr r6, =0x7fff0001
+ str r6, [r3, #0x504]
+
+#endif /* CONFIG_SPL_BUILD */
+
/* Return to U-boot via saved link register */
mov pc, lr
#include <asm/arch/funcmux.h>
#include <asm/arch/mc.h>
#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/sys_proto.h>
UART_COUNT = 5,
};
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+#if !defined(CONFIG_TEGRA124)
+#error tegra_cpu_is_non_secure has only been validated on Tegra124
+#endif
+bool tegra_cpu_is_non_secure(void)
+{
+ /*
+ * This register reads 0xffffffff in non-secure mode. This register
+ * only implements bits 31:20, so the lower bits will always read 0 in
+ * secure mode. Thus, the lower bits are an indicator for secure vs.
+ * non-secure mode.
+ */
+ struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+ uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
+ return (mc_s_cfg0 & 1) == 1;
+}
+#endif
+
/* Read the RAM size directly from the memory controller */
unsigned int query_sdram_size(void)
{
struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
- u32 size_mb;
+ u32 emem_cfg, size_bytes;
- size_mb = readl(&mc->mc_emem_cfg);
+ emem_cfg = readl(&mc->mc_emem_cfg);
#if defined(CONFIG_TEGRA20)
- debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
- size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
+ debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
+ size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
#else
- debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
- size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
+ debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
+ /*
+ * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
+ * and will wrap. Clip the reported size to the maximum that a 32-bit
+ * variable can represent (rounded to a page).
+ */
+ if (emem_cfg >= 4096) {
+ size_bytes = U32_MAX & ~(0x1000 - 1);
+ } else {
+ /* RAM size EMC is programmed to. */
+ size_bytes = emem_cfg * 1024 * 1024;
+ /*
+ * If all RAM fits within 32-bits, it can be accessed without
+ * LPAE, so go test the RAM size. Otherwise, we can't access
+ * all the RAM, and get_ram_size() would get confused, so
+ * avoid using it. There's no reason we should need this
+ * validation step anyway.
+ */
+ if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
+ size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
+ size_bytes);
+ }
#endif
#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
/* External memory limited to 2047 MB due to IROM/HI-VEC */
- if (size_mb == SZ_2G) size_mb -= SZ_1M;
+ if (size_bytes == SZ_2G)
+ size_bytes -= SZ_1M;
#endif
- return size_mb;
+ return size_bytes;
}
int dram_init(void)
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/timer.h>
#include <div64.h>
debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
/* Do any special system timer/TSC setup */
- arch_timer_init();
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+ if (!tegra_cpu_is_non_secure())
+#endif
+ arch_timer_init();
}
static void set_avp_clock_source(u32 src)
#define pmux_pin_tristate_isvalid(tristate) \
(((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
/* return 1 if a pin_io_is in range */
#define pmux_pin_io_isvalid(io) \
(((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
/* return 1 if a pin_lock is in range */
#define pmux_pin_lock_isvalid(lock) \
(((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
/* return 1 if a pin_od is in range */
#define pmux_pin_od_isvalid(od) \
(((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
/* return 1 if a pin_ioreset_is in range */
#define pmux_pin_ioreset_isvalid(ioreset) \
(((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+#endif
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
/* return 1 if a pin_rcv_sel_is in range */
#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
(((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+/* return 1 if a pin_e_io_hv is in range */
+#define pmux_pin_e_io_hv_isvalid(e_io_hv) \
+ (((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \
+ ((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH))
+#endif
+
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
+#define pmux_lpmd_isvalid(lpm) \
+ (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
+#define pmux_schmt_isvalid(schmt) \
+ (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
+#define pmux_hsm_isvalid(hsm) \
+ (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
+#endif
#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
#endif /* CONFIG_TEGRA20 */
-#define DRV_REG(group) _R(0x868 + ((group) * 4))
+#define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
+/*
+ * We could force arch-tegraNN/pinmux.h to define all of these. However,
+ * that's a lot of defines, and for now it's manageable to just put a
+ * special case here. It's possible this decision will change with future
+ * SoCs.
+ */
+#ifdef CONFIG_TEGRA210
+#define IO_SHIFT 6
+#define LOCK_SHIFT 7
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+#define HSM_SHIFT 9
+#endif
+#define E_IO_HV_SHIFT 10
+#define OD_SHIFT 11
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+#define SCHMT_SHIFT 12
+#endif
+#else
#define IO_SHIFT 5
#define OD_SHIFT 6
#define LOCK_SHIFT 7
#define IO_RESET_SHIFT 8
#define RCV_SEL_SHIFT 9
+#endif
-#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
+#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
/* This register/field only exists on Tegra114 and later */
#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
#define CLAMP_INPUTS_WHEN_TRISTATED 1
void pinmux_set_tristate_input_clamping(void)
{
u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
- u32 val;
- val = readl(reg);
- val |= CLAMP_INPUTS_WHEN_TRISTATED;
- writel(val, reg);
+ setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
+}
+
+void pinmux_clear_tristate_input_clamping(void)
+{
+ u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
+
+ clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
}
#endif
pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
}
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
{
u32 *reg = REG(pin);
val &= ~(1 << IO_SHIFT);
writel(val, reg);
}
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
{
u32 *reg = REG(pin);
return;
}
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
{
u32 *reg = REG(pin);
return;
}
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
static void pinmux_set_ioreset(enum pmux_pingrp pin,
enum pmux_pin_ioreset ioreset)
{
return;
}
+#endif
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
enum pmux_pin_rcv_sel rcv_sel)
{
return;
}
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+static void pinmux_set_e_io_hv(enum pmux_pingrp pin,
+ enum pmux_pin_e_io_hv e_io_hv)
+{
+ u32 *reg = REG(pin);
+ u32 val;
+
+ if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT)
+ return;
+
+ /* Error check on pin and e_io_hv */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_e_io_hv_isvalid(e_io_hv));
+
+ val = readl(reg);
+ if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH)
+ val |= (1 << E_IO_HV_SHIFT);
+ else
+ val &= ~(1 << E_IO_HV_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
+{
+ u32 *reg = REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (schmt == PMUX_SCHMT_NONE)
+ return;
+
+ /* Error check pad */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_schmt_isvalid(schmt));
+
+ val = readl(reg);
+ if (schmt == PMUX_SCHMT_ENABLE)
+ val |= (1 << SCHMT_SHIFT);
+ else
+ val &= ~(1 << SCHMT_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm)
+{
+ u32 *reg = REG(grp);
+ u32 val;
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (hsm == PMUX_HSM_NONE)
+ return;
+
+ /* Error check pad */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_hsm_isvalid(hsm));
+
+ val = readl(reg);
+ if (hsm == PMUX_HSM_ENABLE)
+ val |= (1 << HSM_SHIFT);
+ else
+ val &= ~(1 << HSM_SHIFT);
+ writel(val, reg);
+
+ return;
+}
+#endif
static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
{
pinmux_set_func(pin, config->func);
pinmux_set_pullupdown(pin, config->pull);
pinmux_set_tristate(pin, config->tristate);
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
pinmux_set_io(pin, config->io);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
pinmux_set_lock(pin, config->lock);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
pinmux_set_od(pin, config->od);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
pinmux_set_ioreset(pin, config->ioreset);
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
pinmux_set_rcv_sel(pin, config->rcv_sel);
#endif
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+ pinmux_set_e_io_hv(pin, config->e_io_hv);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+ pinmux_set_schmt(pin, config->schmt);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+ pinmux_set_hsm(pin, config->hsm);
#endif
}
pinmux_config_pingrp(&config[i]);
}
-#ifdef TEGRA_PMX_HAS_DRVGRPS
+#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
#define pmux_drv_isvalid(drv) \
(((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
-#define pmux_lpmd_isvalid(lpm) \
- (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
-
-#define pmux_schmt_isvalid(schmt) \
- (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
-
-#define pmux_hsm_isvalid(hsm) \
- (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
-
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
#define HSM_SHIFT 2
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
#define SCHMT_SHIFT 3
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
#define LPMD_SHIFT 4
#define LPMD_MASK (3 << LPMD_SHIFT)
+#endif
+/*
+ * Note that the following DRV* and SLW* defines are accurate for many drive
+ * groups on many SoCs. We really need a per-group data structure to solve
+ * this, since the fields are in different positions/sizes in different
+ * registers (for different groups).
+ *
+ * On Tegra30/114/124, the DRV*_SHIFT values vary.
+ * On Tegra30, the SLW*_SHIFT values vary.
+ * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
+ * below are wide enough to cover the widest fields, and hopefully don't
+ * interfere with any other fields.
+ * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
+ * wide enough to cover all cases, since that would cause the field to
+ * overlap with other fields in the narrower cases.
+ */
#define DRVDN_SHIFT 12
#define DRVDN_MASK (0x7F << DRVDN_SHIFT)
#define DRVUP_SHIFT 20
return;
}
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
{
u32 *reg = DRV_REG(grp);
return;
}
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
{
u32 *reg = DRV_REG(grp);
return;
}
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
{
u32 *reg = DRV_REG(grp);
return;
}
+#endif
static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
{
pinmux_set_drvdn_slwr(grp, config->slwr);
pinmux_set_drvup(grp, config->drvup);
pinmux_set_drvdn(grp, config->drvdn);
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
pinmux_set_lpmd(grp, config->lpmd);
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
pinmux_set_schmt(grp, config->schmt);
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
pinmux_set_hsm(grp, config->hsm);
+#endif
}
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
config TARGET_M5485EVB
bool "Support M5485EVB"
+config TARGET_AMCORE
+ bool "Support AMCORE"
+
endchoice
source "board/BuS/eb_cpu5282/Kconfig"
source "board/freescale/m54455evb/Kconfig"
source "board/freescale/m547xevb/Kconfig"
source "board/freescale/m548xevb/Kconfig"
+source "board/sysam/amcore/Kconfig"
endmenu
CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
+# Support generic board on m68k
+__HAVE_ARCH_GENERIC_BOARD := y
+
PLATFORM_CPPFLAGS += -D__M68K__
PLATFORM_LDFLAGS += -n
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
--- /dev/null
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+extra-y = start.o
+obj-y = interrupts.o cpu.o speed.o cpu_init.o
+
--- /dev/null
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h
+is5307:=$(shell grep CONFIG_M5307 $(cfg))
+
+ifneq (,$(findstring CONFIG_M5307,$(is5307)))
+PLATFORM_CPPFLAGS += -mcpu=5307
+endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_M5307
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ /* enable watchdog/reset, set timeout to 0 and wait */
+ out_8(&sim->sypcr, SYPCR_SWE | SYPCR_SWRI);
+
+ /* wait for watchdog reset */
+ for (;;)
+ ;
+
+ /* we don't return! */
+ return 0;
+}
+
+int checkcpu(void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n",
+ strmhz(buf, CONFIG_SYS_CPU_CLK));
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_M5307)
+/*
+ * Simple mcf5307 chip select module init.
+ *
+ * Note: this chip has an issue reported in the device "errata":
+ * MCF5307ER Rev 4.2 reports @ section 35:
+ * Corrupted Return PC in Exception Stack Frame
+ * When processing an autovectored interrupt an error can occur that
+ * causes 0xFFFFFFFF to be written as the return PC value in the
+ * exception stack frame. The problem is caused by a conflict between
+ * an internal autovector access and a chip select mapped to the IACK
+ * address space (0xFFFFXXXX).
+ * Workaround:
+ * Set the C/I bit in the chip select mask register (CSMR) for the
+ * chip select that is mapped to 0xFFFFXXXX.
+ * This will prevent the chip select from asserting for IACK accesses.
+ */
+
+#define MCF5307_SP_ERR_FIX(cs_base, mask) \
+ do { \
+ if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \
+ 0xffff0000) \
+ setbits_be32(&mask, CSMR_CI); \
+ } while (0)
+
+void init_csm(void)
+{
+ csm_t *csm = (csm_t *)(MMAP_CSM);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
+ defined(CONFIG_SYS_CS0_CTRL))
+ out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
+ out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
+ defined(CONFIG_SYS_CS1_CTRL))
+ out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
+ defined(CONFIG_SYS_CS2_CTRL))
+ out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
+ defined(CONFIG_SYS_CS3_CTRL))
+ out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
+ defined(CONFIG_SYS_CS4_CTRL))
+ out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
+ out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
+ defined(CONFIG_SYS_CS5_CTRL))
+ out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
+ out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
+ defined(CONFIG_SYS_CS6_CTRL))
+ out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
+ out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
+ out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
+ defined(CONFIG_SYS_CS7_CTRL))
+ out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
+ out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
+ out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
+#endif
+}
+
+/*
+ * Set up the memory map and initialize registers
+ */
+void cpu_init_f(void)
+{
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ out_8(&sim->sypcr, 0x00);
+ out_8(&sim->swivr, 0x0f);
+ out_8(&sim->swsr, 0x00);
+ out_8(&sim->mpark, 0x00);
+
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ /* timer 2 not masked */
+ out_be32(&icr->imr, 0xfffffbff);
+
+ out_8(&icr->icr0, 0x00); /* sw watchdog */
+ out_8(&icr->icr1, 0x00); /* timer 1 */
+ out_8(&icr->icr2, 0x88); /* timer 2 */
+ out_8(&icr->icr3, 0x00); /* i2c */
+ out_8(&icr->icr4, 0x00); /* uart 0 */
+ out_8(&icr->icr5, 0x00); /* uart 1 */
+ out_8(&icr->icr6, 0x00); /* dma 0 */
+ out_8(&icr->icr7, 0x00); /* dma 1 */
+ out_8(&icr->icr8, 0x00); /* dma 2 */
+ out_8(&icr->icr9, 0x00); /* dma 3 */
+
+ /* Chipselect Init */
+ init_csm();
+
+ /* enable data/instruction cache now */
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return 0;
+}
+
+void uart_port_conf(void)
+{
+}
+
+void arch_preboot_os(void)
+{
+ /*
+ * OS can change interrupt offsets and are about to boot the OS so
+ * we need to make sure we disable all async interrupts.
+ */
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ out_8(&icr->icr1, 0x00); /* timer 1 */
+ out_8(&icr->icr2, 0x00); /* timer 2 */
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_M5307
+int interrupt_init(void)
+{
+ enable_interrupts();
+
+ return 0;
+}
+
+void dtimer_intr_setup(void)
+{
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ /* clearing TIMER2 mask, so enabling the related interrupt */
+ out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400);
+ /* set TIMER2 interrupt priority */
+ out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#if defined(CONFIG_M5307)
+ gd->bus_clk = CONFIG_SYS_CLK;
+ gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+#endif
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#define _START _start
+#define _FAULT _fault
+
+
+.macro SAVE_ALL
+ move.w #0x2700,%sr; /* disable intrs */
+ subl #60,%sp; /* space for 15 regs */
+ moveml %d0-%d7/%a0-%a6,%sp@
+.endm
+
+.macro RESTORE_ALL
+ moveml %sp@,%d0-%d7/%a0-%a6;
+ addl #60,%sp; /* space for 15 regs */
+ rte
+.endm
+
+/* If we come from a pre-loader we don't need an initial exception
+ * table.
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+
+.text
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+/* Flash offset is 0 until we setup CS0 */
+.long 0x00000000
+#if defined(CONFIG_M5307) && \
+ (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+.long _start - CONFIG_SYS_TEXT_BASE
+#else
+.long _START
+#endif
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+#endif
+
+ .text
+ .globl _start
+_start:
+ nop
+ nop
+ move.w #0x2700,%sr
+
+ /* set MBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.c %d0, %MBAR
+
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.c %d0, %RAMBAR
+
+ /* DS 4.8.2 (Cache Organization) invalidate and disable cache */
+ move.l #CF_CACR_CINVA, %d0
+ movec %d0, %CACR
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
+ /*
+ * if we come from a pre-loader we have no exception table and
+ * therefore no VBR to set
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
+ movec %d0, %VBR
+#endif
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(ICACHE_STATUS), %a1 /* icache */
+ move.l #(DCACHE_STATUS), %a2 /* dcache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+
+ /*
+ * set stackpointer to internal sram end - 80
+ * (global data struct size + some bytes)
+ * get some stackspace for the first c-code,
+ */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
+
+ /* run low-level CPU init code (from flash) */
+ bsr cpu_init_f
+
+ /* run low-level board init code (from flash) */
+ bsr board_init_f
+
+ /* board_init_f() does not return */
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+ .globl relocate_code
+relocate_code:
+ link.w %a6,#0
+ move.l 8(%a6), %sp /* set new stack pointer */
+ move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
+ move.l 16(%a6), %a0 /* Save copy of Destination Address */
+
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
+ move.l #__init_end, %a2
+ move.l %a0, %a3
+ /* copy the code to RAM */
+1:
+ move.l (%a1)+, (%a3)+
+ cmp.l %a1,%a2
+ bgt.s 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+ move.l %a0, %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+ jmp (%a1)
+
+in_ram:
+
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ move.l %a0, %a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE), %a1
+ move.l %a0, %d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE), %d1
+6:
+ clr.l (%a1)+
+ cmp.l %a1,%d1
+ bgt.s 6b
+
+ /*
+ * fix got table in RAM
+ */
+ move.l %a0, %a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE), %a1
+ /* * fix got pointer register a5 */
+ move.l %a1,%a5
+
+ move.l %a0, %a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE), %a2
+
+7:
+ move.l (%a1),%d1
+ sub.l #_start, %d1
+ add.l %a0,%d1
+ move.l %d1,(%a1)+
+ cmp.l %a2, %a1
+ bne 7b
+
+ /* calculate relative jump to board_init_r in ram */
+ move.l %a0, %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+ /* set parameters for board_init_r */
+ move.l %a0,-(%sp) /* dest_addr */
+ move.l %d0,-(%sp) /* gd */
+#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \
+ defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
+ halt
+#endif
+ jsr (%a1)
+
+/*--------------------------------------------------------------------------*/
+/* exception code */
+ .globl _fault
+_fault:
+ bra _fault
+
+ .globl _exc_handler
+_exc_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr exc_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+ .globl _int_handler
+_int_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr int_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+/*--------------------------------------------------------------------------*/
+
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
#define CONFIG_CF_V2
#endif
-#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
+#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
+ defined(CONFIG_MCF5301x)
#define CONFIG_CF_V3
#endif
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
#define CONFIG_NEEDS_MANUAL_RELOC
#define CONFIG_LMB
#endif
#endif /* CONFIG_M5282 */
+#ifdef CONFIG_M5307
+#include <asm/immap_5307.h>
+#include <asm/m5307.h>
+
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
+ (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
+ (CONFIG_SYS_INTR_BASE))->ipr)
+#define CONFIG_SYS_TMRINTR_NO (31)
+#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
+ MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5307 */
+
#if defined(CONFIG_MCF5301x)
#include <asm/immap_5301x.h>
#include <asm/m5301x.h>
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __IMMAP_5307__
+#define __IMMAP_5307__
+
+#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244)
+
+typedef struct sim {
+ u8 rsr;
+ u8 sypcr;
+ u8 swivr;
+ u8 swsr;
+ u16 par;
+ u8 irqpar;
+ u8 res1;
+ u8 pllcr;
+ u8 res2;
+ u16 res3;
+ u8 mpark;
+ u8 res4;
+ u16 res5;
+ u32 res6;
+} sim_t;
+
+typedef struct intctrl {
+ u32 ipr;
+ u32 imr;
+ u16 res7;
+ u8 res8;
+ u8 avr;
+ u8 icr0;
+ u8 icr1;
+ u8 icr2;
+ u8 icr3;
+ u8 icr4;
+ u8 icr5;
+ u8 icr6;
+ u8 icr7;
+ u8 icr8;
+ u8 icr9;
+ u16 res9;
+} intctrl_t;
+
+typedef struct csm {
+ u16 csar0; /* Chip-select Address */
+ u16 res1;
+ u32 csmr0; /* Chip-select Mask */
+ u16 res2;
+ u16 cscr0; /* Chip-select Control */
+ u16 csar1;
+ u16 res3;
+ u32 csmr1;
+ u16 res4;
+ u16 cscr1;
+ u16 csar2;
+ u16 res5;
+ u32 csmr2;
+ u16 res6;
+ u16 cscr2;
+ u16 csar3;
+ u16 res7;
+ u32 csmr3;
+ u16 res8;
+ u16 cscr3;
+ u16 csar4;
+ u16 res9;
+ u32 csmr4;
+ u16 res10;
+ u16 cscr4;
+ u16 csar5;
+ u16 res11;
+ u32 csmr5;
+ u16 res12;
+ u16 cscr5;
+ u16 csar6;
+ u16 res13;
+ u32 csmr6;
+ u16 res14;
+ u16 cscr6;
+ u16 csar7;
+ u16 res15;
+ u32 csmr7;
+ u16 res16;
+ u16 cscr7;
+} csm_t;
+
+typedef struct sdramctrl {
+ u16 dcr;
+ u16 res1;
+ u32 res2;
+ u32 dacr0;
+ u32 dmr0;
+ u32 dacr1;
+ u32 dmr1;
+} sdramctrl_t;
+
+typedef struct gpio {
+ u16 paddr;
+ u16 res1;
+ u16 padat;
+ u16 res2;
+} gpio_t;
+
+#endif /* __IMMAP_5307__ */
+
--- /dev/null
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef mcf5307_h
+#define mcf5307_h
+
+/*
+ * Size of internal RAM (RAMBAR)
+ */
+#define INT_RAM_SIZE 4096
+
+/* Bit definitions and macros for SYPCR */
+#define SYPCR_SWTAVAL 0x02
+#define SYPCR_SWTA 0x04
+#define SYPCR_SWT(x) ((x&0x3)<<3)
+#define SYPCR_SWP 0x20
+#define SYPCR_SWRI 0x40
+#define SYPCR_SWE 0x80
+
+/* Bit definitions and macros for CSMR */
+#define CSMR_V 0x01
+#define CSMR_UD 0x02
+#define CSMR_UC 0x04
+#define CSMR_SD 0x08
+#define CSMR_SC 0x10
+#define CSMR_CI 0x20
+#define CSMR_AM 0x40
+#define CSMR_WP 0x100
+
+/* Bit definitions and macros for DACR (SDRAM) */
+#define DACR_PM_CONTINUOUS 0x04
+#define DACR_IP_PRECHG_ALL 0x08
+#define DACR_PORT_SZ_32 0
+#define DACR_PORT_SZ_8 (1<<4)
+#define DACR_PORT_SZ_16 (2<<4)
+#define DACR_IMRS_INIT_CMD (1<<6)
+#define DACR_CMD_PIN(x) ((x&7)<<8)
+#define DACR_CASL(x) ((x&3)<<12)
+#define DACR_RE (1<<15)
+
+/* Bit definitions and macros for CSCR */
+#define CSCR_BSTW 0x08
+#define CSCR_BSTR 0x10
+#define CSCR_BEM 0x20
+#define CSCR_PS(x) ((x&0x3)<<6)
+#define CSCR_AA 0x100
+#define CSCR_WS ((x&0xf)<<10)
+
+/* Bit definitions for the ICR family of registers */
+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
+
+#endif /* mcf5307_h */
+
/****************************************************************************/
/* DMA Timer module registers */
typedef struct dtimer_ctrl {
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+ defined(CONFIG_M5272) || defined(CONFIG_M5307)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */
* include/asm-ppc/u-boot.h
*/
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#else
+
#ifndef __ASSEMBLY__
typedef struct bd_info {
#endif /* __ASSEMBLY__ */
+#endif /* !CONFIG_SYS_GENERIC_BOARD */
+
+
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_M68K
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += board.o
+ifndef CONFIG_SYS_GENERIC_BOARD
+obj-y += board.o
+endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += interrupts.o
config TARGET_A4M072
bool "Support a4m072"
-config TARGET_BC3450
- bool "Support BC3450"
-
config TARGET_CANMB
bool "Support canmb"
config TARGET_CM5200
bool "Support cm5200"
-config TARGET_GALAXY5200
- bool "Support galaxy5200"
-
config TARGET_INKA4X0
bool "Support inka4x0"
config TARGET_PCM030
bool "Support pcm030"
-config TARGET_AEV
- bool "Support aev"
-
config TARGET_CHARON
bool "Support charon"
-config TARGET_TB5200
- bool "Support TB5200"
-
config TARGET_TQM5200
bool "Support TQM5200"
source "board/a3m071/Kconfig"
source "board/a4m072/Kconfig"
-source "board/bc3450/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
-source "board/galaxy5200/Kconfig"
source "board/ifm/o2dnt2/Kconfig"
source "board/inka4x0/Kconfig"
source "board/intercontrol/digsy_mtc/Kconfig"
unsigned int i, core, nr_cores = cpu_numcores();
u32 mask = cpu_mask();
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
+ u32 dsp_mask = cpu_dsp_mask();
+#endif
+
svr = get_svr();
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
printf("CPU%d:%-4s MHz, ", core,
strmhz(buf1, sysinfo.freq_processor[core]));
}
+
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
+ if (!(j & 3))
+ printf("\n ");
+ printf("DSP CPU%d:%-4s MHz, ", j,
+ strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
+ }
+#endif
+
printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
printf("\n");
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
#endif
+#if defined(CONFIG_SYS_CPRI)
+ printf(" ");
+ printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
+#endif
+
+#if defined(CONFIG_SYS_MAPLE)
+ printf("\n ");
+ printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
+ printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
+ printf("MAPLE-eTVPE:%-4s MHz\n",
+ strmhz(buf1, sysinfo.freq_maple_etvpe));
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned int dsp_cpu;
+ uint rcw_tmp1, rcw_tmp2;
+#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif
else
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
}
+
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
* As per CHASSIS2 architeture total 12 clusters are posible and
sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
+
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
+ int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
+ u32 c_pll_sel = (in_be32
+ (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
+ & 0xf;
+ u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+ cplx_pll += cc_group[dsp_cluster] - 1;
+ sys_info->freq_processor_dsp[dsp_cpu] =
+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ }
+#endif
+
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL 0xe0000000
sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
#endif
+#if defined(CONFIG_SYS_MAPLE)
+#define CPRI_CLK_SEL 0x1C000000
+#define CPRI_CLK_SHIFT 26
+#define CPRI_ALT_CLK_SEL 0x00007000
+#define CPRI_ALT_CLK_SHIFT 12
+
+ rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
+ rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
+ /* For MAPLE and CPRI frequency */
+ switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
+ break;
+ case 2:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
+ break;
+ case 3:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
+ break;
+ case 4:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
+ break;
+ case 5:
+ if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
+ >> CPRI_ALT_CLK_SHIFT) == 6) {
+ sys_info->freq_maple =
+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
+ sys_info->freq_cpri =
+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
+ }
+ if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
+ >> CPRI_ALT_CLK_SHIFT) == 7) {
+ sys_info->freq_maple =
+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
+ sys_info->freq_cpri =
+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
+ }
+ break;
+ case 6:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
+ break;
+ case 7:
+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
+ break;
+ default:
+ printf("Error: Unknown MAPLE/CPRI clock select!\n");
+ }
+
+ /* For MAPLE ULB and eTVPE frequencies */
+#define ULB_CLK_SEL 0x00000038
+#define ULB_CLK_SHIFT 3
+#define ETVPE_CLK_SEL 0x00000007
+#define ETVPE_CLK_SHIFT 0
+
+ switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
+ break;
+ case 2:
+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
+ break;
+ case 3:
+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
+ break;
+ case 4:
+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
+ break;
+ case 5:
+ sys_info->freq_maple_ulb = sys_info->freq_systembus;
+ break;
+ case 6:
+ sys_info->freq_maple_ulb =
+ freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
+ break;
+ case 7:
+ sys_info->freq_maple_ulb =
+ freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
+ break;
+ default:
+ printf("Error: Unknown MAPLE ULB clock select!\n");
+ }
+
+ switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
+ break;
+ case 2:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
+ break;
+ case 3:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
+ break;
+ case 4:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
+ break;
+ case 5:
+ sys_info->freq_maple_etvpe = sys_info->freq_systembus;
+ break;
+ case 6:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
+ break;
+ case 7:
+ sys_info->freq_maple_etvpe =
+ freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
+ break;
+ default:
+ printf("Error: Unknown MAPLE eTVPE clock select!\n");
+ }
+
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_FM_PLAT_CLK_DIV
switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
return mask;
}
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+u32 compute_dsp_cpumask(void)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int i = CONFIG_DSP_CLUSTER_START, count = 0;
+ u32 cluster, type, dsp_mask = 0;
+
+ do {
+ int j;
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = init_type(cluster, j);
+ if (type) {
+ if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_SC)
+ dsp_mask |= 1 << count;
+ count++;
+ }
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+ return dsp_mask;
+}
+
+int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int count = 0, i = CONFIG_DSP_CLUSTER_START;
+ u32 cluster;
+
+ do {
+ int j;
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ if (init_type(cluster, j)) {
+ if (count == core)
+ return i;
+ count++;
+ }
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+ return -1; /* cannot identify the cluster */
+}
+#endif
+
int fsl_qoriq_core_to_cluster(unsigned int core)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
return cpu->mask;
}
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+__weak u32 cpu_dsp_mask(void)
+{
+ ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ /* better to query feature reporting register than just assume 1 */
+ if (cpu == &cpu_type_unknown)
+ return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
+ MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
+
+ if (cpu->dsp_num_cores == 0)
+ return compute_dsp_cpumask();
+
+ return cpu->dsp_mask;
+}
+
/*
- * Return the number of cores on this SOC.
+ * Return the number of SC/DSP cores on this SOC.
+ */
+__weak int cpu_num_dspcores(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ /*
+ * Report # of cores in terms of the cpu_mask if we haven't
+ * figured out how many there are yet
+ */
+ if (cpu->dsp_num_cores == 0)
+ return hweight32(cpu_dsp_mask());
+
+ return cpu->dsp_num_cores;
+}
+#endif
+
+/*
+ * Return the number of PPC cores on this SOC.
*/
__weak int cpu_numcores(void)
{
return cpu->num_cores;
}
+
/*
* Check if the given core ID is valid
*
cpu->num_cores = cpu_numcores();
}
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ if (cpu->dsp_num_cores == 0) {
+ cpu->dsp_mask = cpu_dsp_mask();
+ cpu->dsp_num_cores = cpu_num_dspcores();
+ }
+#endif
return 0;
}
config TARGET_CSB472
bool "Support csb472"
-config TARGET_JSE
- bool "Support JSE"
-
-config TARGET_KORAT
- bool "Support korat"
-
config TARGET_LWMON5
bool "Support lwmon5"
select SUPPORT_SPL
config TARGET_T3CORP
bool "Support t3corp"
-config TARGET_W7OLMC
- bool "Support W7OLMC"
-
-config TARGET_W7OLMG
- bool "Support W7OLMG"
-
config TARGET_ZEUS
bool "Support zeus"
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
-source "board/jse/Kconfig"
-source "board/korat/Kconfig"
source "board/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/sbc405/Kconfig"
source "board/sc3/Kconfig"
source "board/t3corp/Kconfig"
-source "board/w7o/Kconfig"
source "board/xes/xpedite1000/Kconfig"
source "board/xilinx/ml507/Kconfig"
source "board/xilinx/ppc405-generic/Kconfig"
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SEC_BE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SEC_MON_BE
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
#elif defined(CONFIG_P1013)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
+#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
+#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_MAPLE
+#define CONFIG_SYS_CPRI
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_CPRI_CLK 3
+#define CONFIG_SYS_ULB_CLK 4
+#define CONFIG_SYS_ETVPE_CLK 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#ifdef CONFIG_PPC_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_MAX_CPUS 4
+#define CONFIG_MAX_DSP_CPUS 12
+#define CONFIG_NUM_DSP_CPUS 6
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_FSL_SRIO_LIODN
#else
#define CONFIG_MAX_CPUS 2
+#define CONFIG_MAX_DSP_CPUS 2
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#ifndef __FSL_SECURE_BOOT_H
#define __FSL_SECURE_BOOT_H
+#include <asm/config_mpc85xx.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_DM
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
+#endif
#ifdef CONFIG_SECURE_BOOT
#if defined(CONFIG_FSL_CORENET)
defined(CONFIG_PPC_T1023) || \
defined(CONFIG_PPC_T1024)
#define CONFIG_SYS_CPC_REINIT_F
+#define CONFIG_KEY_REVOCATION
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
#endif
+#if defined(CONFIG_C29XPCIE)
+#define CONFIG_KEY_REVOCATION
+#endif
+
+#if defined(CONFIG_PPC_P3041) || \
+ defined(CONFIG_PPC_P4080) || \
+ defined(CONFIG_PPC_P5020) || \
+ defined(CONFIG_PPC_P5040) || \
+ defined(CONFIG_PPC_P2041)
+ #define CONFIG_FSL_TRUST_ARCH_v1
+#endif
+
+#if defined(CONFIG_FSL_CORENET)
+/* The key used for verification of next level images
+ * is picked up from an Extension Table which has
+ * been verified by the ISBC (Internal Secure boot Code)
+ * in boot ROM of the SoC
+ */
+#define CONFIG_FSL_ISBC_KEY_EXT
+#endif
+
#endif
#endif
#include <asm/fsl_i2c.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
+#include <fsl_sfp.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_fman.h>
#include <fsl_immap.h>
u8 res_f4[0xf0c];
};
#endif
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
-struct ccsr_sfp_regs {
- u32 ospr; /* 0x200 */
- u32 reserved0[14];
- u32 srk_hash[8]; /* 0x23c Super Root Key Hash */
- u32 oem_uid; /* 0x9c OEM Unique ID */
- u8 reserved2[0x04];
- u32 ovpr; /* 0xA4 Intent To Secure */
- u8 reserved4[0x08];
- u32 fsl_uid; /* 0xB0 FSL Unique ID */
- u8 reserved5[0x04];
- u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
- u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
-};
-#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
+#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
#endif
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
-#define CONFIG_SYS_SNVS_OFFSET 0xE6000
+#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
#define CONFIG_SYS_SFP_OFFSET 0xE7000
#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
#define CONFIG_SYS_SFP_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+#define CONFIG_SYS_SEC_MON_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
u32 soc_ver;
u32 num_cores;
u32 mask; /* which cpu(s) actually exist */
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ u32 dsp_num_cores;
+ u32 dsp_mask; /* which DSP cpu(s) actually exist */
+#endif
};
struct cpu_type *identify_cpu(u32 ver);
int fixup_cpu(void);
int fsl_qoriq_core_to_cluster(unsigned int core);
+int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define CPU_TYPE_ENTRY(n, v, nc) \
#ifndef _BUR_COMMON_H_
#define _BUR_COMMON_H_
+#include <../../../drivers/video/am335x-fb.h>
+
+int load_lcdtiming(struct am335x_lcdpanel *panel);
+void br_summaryscreen(void);
void blink(u32 blinks, u32 intervall, u32 pin);
void pmicsetup(u32 mpupll);
void enable_uart0_pin_mux(void);
* SPDX-License-Identifier: GPL-2.0+
*
*/
-
+#include <version.h>
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
+#include <lcd.h>
+#include <fs.h>
+#ifdef CONFIG_USE_FDT
+ #include <fdt_support.h>
+#endif
#include "bur_common.h"
+#include "../../../drivers/video/am335x-fb.h"
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USE_FDT
+ #define FDTPROP(a, b, c) fdt_getprop_u32_default((void *)a, b, c, ~0UL)
+ #define PATHTIM "/panel/display-timings/default"
+ #define PATHINF "/panel/panel-info"
+#endif
/* --------------------------------------------------------------------------*/
+#if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \
+ !defined(CONFIG_SPL_BUILD)
+int load_lcdtiming(struct am335x_lcdpanel *panel)
+{
+ struct am335x_lcdpanel pnltmp;
+#ifdef CONFIG_USE_FDT
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+ u32 dtbprop;
+
+ if (dtbaddr == ~0UL) {
+ puts("load_lcdtiming: failed to get 'dtbaddr' from env!\n");
+ return -1;
+ }
+ memcpy(&pnltmp, (void *)panel, sizeof(struct am335x_lcdpanel));
+
+ pnltmp.hactive = FDTPROP(dtbaddr, PATHTIM, "hactive");
+ pnltmp.vactive = FDTPROP(dtbaddr, PATHTIM, "vactive");
+ pnltmp.bpp = FDTPROP(dtbaddr, PATHINF, "bpp");
+ pnltmp.hfp = FDTPROP(dtbaddr, PATHTIM, "hfront-porch");
+ pnltmp.hbp = FDTPROP(dtbaddr, PATHTIM, "hback-porch");
+ pnltmp.hsw = FDTPROP(dtbaddr, PATHTIM, "hsync-len");
+ pnltmp.vfp = FDTPROP(dtbaddr, PATHTIM, "vfront-porch");
+ pnltmp.vbp = FDTPROP(dtbaddr, PATHTIM, "vback-porch");
+ pnltmp.vsw = FDTPROP(dtbaddr, PATHTIM, "vsync-len");
+ pnltmp.pup_delay = FDTPROP(dtbaddr, PATHTIM, "pupdelay");
+ pnltmp.pon_delay = FDTPROP(dtbaddr, PATHTIM, "pondelay");
+
+ /* calc. proper clk-divisor */
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "clock-frequency");
+ if (dtbprop != ~0UL)
+ pnltmp.pxl_clk_div = 192000000 / dtbprop;
+ else
+ pnltmp.pxl_clk_div = ~0UL;
+
+ /* check polarity of control-signals */
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "hsync-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= HSYNC_INVERT;
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "vsync-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= VSYNC_INVERT;
+ dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-ctrl");
+ if (dtbprop == 1)
+ pnltmp.pol |= HSVS_CONTROL;
+ dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-edge");
+ if (dtbprop == 1)
+ pnltmp.pol |= HSVS_RISEFALL;
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "pixelclk-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= PXCLK_INVERT;
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "de-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= DE_INVERT;
+#else
+ pnltmp.hactive = getenv_ulong("ds1_hactive", 10, ~0UL);
+ pnltmp.vactive = getenv_ulong("ds1_vactive", 10, ~0UL);
+ pnltmp.bpp = getenv_ulong("ds1_bpp", 10, ~0UL);
+ pnltmp.hfp = getenv_ulong("ds1_hfp", 10, ~0UL);
+ pnltmp.hbp = getenv_ulong("ds1_hbp", 10, ~0UL);
+ pnltmp.hsw = getenv_ulong("ds1_hsw", 10, ~0UL);
+ pnltmp.vfp = getenv_ulong("ds1_vfp", 10, ~0UL);
+ pnltmp.vbp = getenv_ulong("ds1_vbp", 10, ~0UL);
+ pnltmp.vsw = getenv_ulong("ds1_vsw", 10, ~0UL);
+ pnltmp.pxl_clk_div = getenv_ulong("ds1_pxlclkdiv", 10, ~0UL);
+ pnltmp.pol = getenv_ulong("ds1_pol", 16, ~0UL);
+ pnltmp.pup_delay = getenv_ulong("ds1_pupdelay", 10, ~0UL);
+ pnltmp.pon_delay = getenv_ulong("ds1_tondelay", 10, ~0UL);
+#endif
+ if (
+ ~0UL == (pnltmp.hactive) ||
+ ~0UL == (pnltmp.vactive) ||
+ ~0UL == (pnltmp.bpp) ||
+ ~0UL == (pnltmp.hfp) ||
+ ~0UL == (pnltmp.hbp) ||
+ ~0UL == (pnltmp.hsw) ||
+ ~0UL == (pnltmp.vfp) ||
+ ~0UL == (pnltmp.vbp) ||
+ ~0UL == (pnltmp.vsw) ||
+ ~0UL == (pnltmp.pxl_clk_div) ||
+ ~0UL == (pnltmp.pol) ||
+ ~0UL == (pnltmp.pup_delay) ||
+ ~0UL == (pnltmp.pon_delay)
+ ) {
+ puts("lcd-settings in env/dtb incomplete!\n");
+ printf("display-timings:\n"
+ "================\n"
+ "hactive: %d\n"
+ "vactive: %d\n"
+ "bpp : %d\n"
+ "hfp : %d\n"
+ "hbp : %d\n"
+ "hsw : %d\n"
+ "vfp : %d\n"
+ "vbp : %d\n"
+ "vsw : %d\n"
+ "pxlclk : %d\n"
+ "pol : 0x%08x\n"
+ "pondly : %d\n",
+ pnltmp.hactive, pnltmp.vactive, pnltmp.bpp,
+ pnltmp.hfp, pnltmp.hbp, pnltmp.hsw,
+ pnltmp.vfp, pnltmp.vbp, pnltmp.vsw,
+ pnltmp.pxl_clk_div, pnltmp.pol, pnltmp.pon_delay);
+
+ return -1;
+ }
+ debug("lcd-settings in env complete, taking over.\n");
+ memcpy((void *)panel,
+ (void *)&pnltmp,
+ sizeof(struct am335x_lcdpanel));
+
+ return 0;
+}
+
+#ifdef CONFIG_USE_FDT
+static int load_devicetree(void)
+{
+ char *dtbname = getenv("dtb");
+ char *dtbdev = getenv("dtbdev");
+ char *dtppart = getenv("dtbpart");
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+ loff_t dtbsize;
+
+ if (!dtbdev || !dtbdev) {
+ puts("load_devicetree: <dtbdev>/<dtbpart> missing.\n");
+ return -1;
+ }
+
+ if (fs_set_blk_dev(dtbdev, dtppart, FS_TYPE_EXT)) {
+ puts("load_devicetree: set_blk_dev failed.\n");
+ return -1;
+ }
+ if (dtbname && dtbaddr != ~0UL) {
+ if (fs_read(dtbname, dtbaddr, 0, 0, &dtbsize) == 0) {
+ gd->fdt_blob = (void *)dtbaddr;
+ gd->fdt_size = dtbsize;
+ debug("loaded %d bytes of dtb onto 0x%08x\n",
+ (u32)dtbsize, dtbaddr);
+ return dtbsize;
+ }
+ puts("load_devicetree: load dtb failed,file does not exist!\n");
+ }
+
+ puts("load_devicetree: <dtb>/<dtbaddr> missing!\n");
+ return -1;
+}
+
+static const char *dtbmacaddr(u32 ifno)
+{
+ int node, len;
+ char enet[16];
+ const char *mac;
+ const char *path;
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+
+ if (dtbaddr == ~0UL) {
+ puts("dtbmacaddr: failed to get 'dtbaddr' from env!\n");
+ return NULL;
+ }
+
+ node = fdt_path_offset((void *)dtbaddr, "/aliases");
+ if (node < 0)
+ return NULL;
+
+ sprintf(enet, "ethernet%d", ifno);
+ path = fdt_getprop((void *)dtbaddr, node, enet, NULL);
+ if (!path) {
+ printf("no alias for %s\n", enet);
+ return NULL;
+ }
+
+ node = fdt_path_offset((void *)dtbaddr, path);
+ mac = fdt_getprop((void *)dtbaddr, node, "mac-address", &len);
+ if (mac && is_valid_ether_addr((u8 *)mac))
+ return mac;
+
+ return NULL;
+}
+
+static void br_summaryscreen_printdtb(char *prefix,
+ char *name,
+ char *suffix)
+{
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+ char buf[32] = { 0 };
+ const char *nodep = buf;
+ char *mac = 0;
+ int nodeoffset;
+ int len;
+
+ if (dtbaddr == ~0UL) {
+ puts("br_summaryscreen: failed to get 'dtbaddr' from env!\n");
+ return;
+ }
+
+ if (strcmp(name, "brmac1") == 0) {
+ mac = (char *)dtbmacaddr(0);
+ if (mac)
+ sprintf(buf, "%pM", mac);
+ } else if (strcmp(name, "brmac2") == 0) {
+ mac = (char *)dtbmacaddr(1);
+ if (mac)
+ sprintf(buf, "%pM", mac);
+ } else {
+ nodeoffset = fdt_path_offset((void *)dtbaddr,
+ "/factory-settings");
+ if (nodeoffset < 0) {
+ puts("no 'factory-settings' in dtb!\n");
+ return;
+ }
+ nodep = fdt_getprop((void *)dtbaddr, nodeoffset, name, &len);
+ }
+ if (nodep && strlen(nodep) > 1)
+ lcd_printf("%s %s %s", prefix, nodep, suffix);
+ else
+ lcd_printf("\n");
+}
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int nodeoffset;
+
+ nodeoffset = fdt_path_offset(blob, "/factory-settings");
+ if (nodeoffset < 0) {
+ puts("set bootloader version 'factory-settings' not in dtb!\n");
+ return -1;
+ }
+ if (fdt_setprop(blob, nodeoffset, "bl-version",
+ PLAIN_VERSION, strlen(PLAIN_VERSION)) != 0) {
+ puts("set bootloader version 'bl-version' prop. not in dtb!\n");
+ return -1;
+ }
+ return 0;
+}
+#else
+
+static void br_summaryscreen_printenv(char *prefix,
+ char *name, char *altname,
+ char *suffix)
+{
+ char *envval = getenv(name);
+ if (0 != envval) {
+ lcd_printf("%s %s %s", prefix, envval, suffix);
+ } else if (0 != altname) {
+ envval = getenv(altname);
+ if (0 != envval)
+ lcd_printf("%s %s %s", prefix, envval, suffix);
+ } else {
+ lcd_printf("\n");
+ }
+}
+#endif
+void br_summaryscreen(void)
+{
+#ifdef CONFIG_USE_FDT
+ br_summaryscreen_printdtb(" - B&R -", "order-no", "-\n");
+ br_summaryscreen_printdtb(" Serial/Rev :", "serial-no", " /");
+ br_summaryscreen_printdtb(" ", "hw-revision", "\n");
+ br_summaryscreen_printdtb(" MAC (IF1) :", "brmac1", "\n");
+ br_summaryscreen_printdtb(" MAC (IF2) :", "brmac2", "\n");
+ lcd_puts(" Bootloader : " PLAIN_VERSION "\n");
+ lcd_puts("\n");
+#else
+ br_summaryscreen_printenv(" - B&R -", "br_orderno", 0, "-\n");
+ br_summaryscreen_printenv(" Serial/Rev :", "br_serial", 0, "\n");
+ br_summaryscreen_printenv(" MAC (IF1) :", "br_mac1", "ethaddr", "\n");
+ br_summaryscreen_printenv(" MAC (IF2) :", "br_mac2", 0, "\n");
+ lcd_puts(" Bootloader : " PLAIN_VERSION "\n");
+ lcd_puts("\n");
+#endif
+}
+
+void lcdpower(int on)
+{
+ u32 pin, swval, i;
+#ifdef CONFIG_USE_FDT
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+
+ if (dtbaddr == ~0UL) {
+ puts("lcdpower: failed to get 'dtbaddr' from env!\n");
+ return;
+ }
+ pin = FDTPROP(dtbaddr, PATHINF, "pwrpin");
+#else
+ pin = getenv_ulong("ds1_pwr", 16, ~0UL);
+#endif
+ if (pin == ~0UL) {
+ puts("no pwrpin in dtb/env, cannot powerup display!\n");
+ return;
+ }
+
+ for (i = 0; i < 3; i++) {
+ if (pin != 0) {
+ swval = pin & 0x80 ? 0 : 1;
+ if (on)
+ gpio_direction_output(pin & 0x7F, swval);
+ else
+ gpio_direction_output(pin & 0x7F, !swval);
+
+ debug("switched pin %d to %d\n", pin & 0x7F, swval);
+ }
+ pin >>= 8;
+ }
+}
+
+vidinfo_t panel_info = {
+ .vl_col = 1366, /*
+ * give full resolution for allocating enough
+ * memory
+ */
+ .vl_row = 768,
+ .vl_bpix = 5,
+ .priv = 0
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ struct am335x_lcdpanel lcd_panel;
+#ifdef CONFIG_USE_FDT
+ /* TODO: is there a better place to load the dtb ? */
+ load_devicetree();
+#endif
+ memset(&lcd_panel, 0, sizeof(struct am335x_lcdpanel));
+ if (load_lcdtiming(&lcd_panel) != 0)
+ return;
+
+ lcd_panel.panel_power_ctrl = &lcdpower;
+
+ if (0 != am335xfb_init(&lcd_panel))
+ printf("ERROR: failed to initialize video!");
+ /*
+ * modifiy panel info to 'real' resolution, to operate correct with
+ * lcd-framework.
+ */
+ panel_info.vl_col = lcd_panel.hactive;
+ panel_info.vl_row = lcd_panel.vactive;
+
+ lcd_set_flush_dcache(1);
+}
+
+void lcd_enable(void)
+{
+#ifdef CONFIG_USE_FDT
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+
+ if (dtbaddr == ~0UL) {
+ puts("lcdpower: failed to get 'dtbaddr' from env!\n");
+ return;
+ }
+ unsigned int driver = FDTPROP(dtbaddr, PATHINF, "brightdrv");
+ unsigned int bright = FDTPROP(dtbaddr, PATHINF, "brightdef");
+ unsigned int pwmfrq = FDTPROP(dtbaddr, PATHINF, "brightfdim");
+#else
+ unsigned int driver = getenv_ulong("ds1_bright_drv", 16, 0UL);
+ unsigned int bright = getenv_ulong("ds1_bright_def", 10, 50);
+ unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL);
+#endif
+ unsigned int tmp;
+ struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE;
+
+ bright = bright != ~0UL ? bright : 50;
+
+ switch (driver) {
+ case 0: /* PMIC LED-Driver */
+ /* brightness level */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL2, bright, 0xFF);
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x0A, 0xFF);
+ break;
+ case 1: /* PWM using timer6 */
+ if (pwmfrq != ~0UL) {
+ timerhw->tiocp_cfg = TCFG_RESET;
+ udelay(10);
+ while (timerhw->tiocp_cfg & TCFG_RESET)
+ ;
+ tmp = ~0UL-(V_OSCK/pwmfrq); /* bottom value */
+ timerhw->tldr = tmp;
+ timerhw->tcrr = tmp;
+ tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright;
+ timerhw->tmar = tmp;
+ timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) |
+ TCLR_CE | TCLR_AR | TCLR_ST);
+ } else {
+ puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n");
+ }
+ break;
+ default:
+ puts("no suitable backlightdriver in env/dtb!\n");
+ break;
+ }
+ br_summaryscreen();
+}
+#elif CONFIG_SPL_BUILD
+#else
+#error "LCD-support with a suitable FB-Driver is mandatory !"
+#endif /* CONFIG_LCD */
+
void blink(u32 blinks, u32 intervall, u32 pin)
{
gpio_direction_output(pin, 0);
gpio_set_value(pin, 0);
}
+
#ifdef CONFIG_SPL_BUILD
void pmicsetup(u32 mpupll)
{
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+ /* Set PWR_EN bit in Status Register */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_STATUS, TPS65217_PWR_OFF, TPS65217_PWR_OFF);
}
void set_uart_mux_conf(void)
int board_eth_init(bd_t *bis)
{
int rv = 0;
- uint8_t mac_addr[6];
+ char mac_addr[6];
+ const char *mac = 0;
uint32_t mac_hi, mac_lo;
-
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
-
- if (is_valid_ether_addr(mac_addr)) {
- printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
- mac_addr[0], mac_addr[1], mac_addr[2],
- mac_addr[3], mac_addr[4], mac_addr[5]
- );
- eth_setenv_enetaddr("ethaddr", mac_addr);
+ #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_FDT)
+ printf("<ethaddr> not set. trying DTB ... ");
+ mac = dtbmacaddr(0);
+ #endif
+ if (!mac) {
+ printf("<ethaddr> not set. validating E-fuse MAC ... ");
+ if (is_valid_ether_addr((const u8 *)mac_addr))
+ mac = (const char *)mac_addr;
+ }
+
+ if (mac) {
+ printf("using: %pM on ", mac);
+ eth_setenv_enetaddr("ethaddr", (const u8 *)mac);
}
}
writel(MII_MODE_ENABLE, &cdev->miisel);
return omap_mmc_init(1, 0, 0, -1, -1);
}
#endif
+int overwrite_console(void)
+{
+ return 1;
+}
#include <i2c.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
+#include <lcd.h>
/* -------------------------------------------------------------------------*/
/* -- defines for used GPIO Hardware -- */
-#define KEY (0+4)
-#define LCD_PWR (0+5)
-#define PUSH_KEY (0+31)
-#define USB2SD_NRST (32+29)
-#define USB2SD_PWR (96+13)
+#define ESC_KEY (0+19)
+#define LCD_PWR (0+5)
+#define PUSH_KEY (0+31)
/* -------------------------------------------------------------------------*/
/* -- PSOC Resetcontroller Register defines -- */
/* -- defines for RSTCTRL_CTRLREG -- */
#define RSTCTRL_FORCE_PWR_NEN 0x0404
+#define RSTCTRL_CAN_STB 0x4040
+
+#define VXWORKS_BOOTLINE 0x80001100
+#define DEFAULT_BOOTLINE "cpsw(0,0):pme/vxWorks"
+#define VXWORKS_USER "u=vxWorksFTP pw=vxWorks tn=vxtarget"
+
+DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
/* TODO: check ram-timing ! */
&cmper->epwmss0clkctrl,
&cmper->epwmss1clkctrl,
&cmper->epwmss2clkctrl,
+ &cmper->lcdclkctrl,
+ &cmper->lcdcclkstctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
-
+ /* setup LCD-Pixel Clock */
+ writel(0x2, CM_DPLL + 0x34);
/* power-OFF LCD-Display */
gpio_direction_output(LCD_PWR, 0);
/* power-ON 3V3 via Resetcontroller */
oldspeed = i2c_get_bus_speed();
if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
- buf = RSTCTRL_FORCE_PWR_NEN;
+ buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
(uint8_t *)&buf, sizeof(buf));
i2c_set_bus_speed(oldspeed);
puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
}
-#if defined(CONFIG_AM335X_USB0)
- /* power on USB2SD Controller */
- gpio_direction_output(USB2SD_PWR, 1);
- mdelay(1);
- /* give a reset Pulse to USB2SD Controller */
- gpio_direction_output(USB2SD_NRST, 0);
- mdelay(1);
- gpio_set_value(USB2SD_NRST, 1);
-#endif
pmicsetup(0);
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
- const unsigned int ton = 250;
const unsigned int toff = 1000;
unsigned int cnt = 3;
unsigned short buf = 0xAAAA;
+ unsigned char scratchreg = 0;
unsigned int oldspeed;
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
+ /* try to read out some boot-instruction from resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+ i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+ &scratchreg, sizeof(scratchreg));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+ }
- if (gpio_get_value(KEY)) {
+ if (gpio_get_value(ESC_KEY)) {
do {
- /* turn on light */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL1, 0x09, 0xFF);
- mdelay(ton);
- /* turn off light */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL1, 0x01, 0xFF);
+ lcd_position_cursor(1, 8);
+ switch (cnt) {
+ case 3:
+ lcd_puts(
+ "release ESC-KEY to enter SERVICE-mode.");
+ break;
+ case 2:
+ lcd_puts(
+ "release ESC-KEY to enter DIAGNOSE-mode.");
+ break;
+ case 1:
+ lcd_puts(
+ "release ESC-KEY to enter BOOT-mode. ");
+ break;
+ }
mdelay(toff);
cnt--;
- if (!gpio_get_value(KEY) &&
+ if (!gpio_get_value(ESC_KEY) &&
+ gpio_get_value(PUSH_KEY) && 2 == cnt) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "switching to network-console ... ");
+ setenv("bootcmd", "run netconsole");
+ cnt = 4;
+ break;
+ } else if (!gpio_get_value(ESC_KEY) &&
gpio_get_value(PUSH_KEY) && 1 == cnt) {
- puts("updating from USB ...\n");
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "updating U-BOOT from USB ... ");
setenv("bootcmd", "run usbupdate");
+ cnt = 4;
+ break;
+ } else if ((!gpio_get_value(ESC_KEY) &&
+ gpio_get_value(PUSH_KEY) && cnt == 0) ||
+ (gpio_get_value(ESC_KEY) &&
+ gpio_get_value(PUSH_KEY) && cnt == 0)) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting script from network ... ");
+ setenv("bootcmd", "run netscript");
+ cnt = 4;
break;
- } else if (!gpio_get_value(KEY)) {
+ } else if (!gpio_get_value(ESC_KEY)) {
break;
}
} while (cnt);
+ } else if (scratchreg == 0xCC) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting vxworks from network ... ");
+ setenv("bootcmd", "run netboot");
+ cnt = 4;
+ } else if (scratchreg == 0xCD) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting script from network ... ");
+ setenv("bootcmd", "run netscript");
+ cnt = 4;
+ } else if (scratchreg == 0xCE) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting AR from eMMC ... ");
+ setenv("bootcmd", "run mmcboot");
+ cnt = 4;
}
+ lcd_position_cursor(1, 8);
switch (cnt) {
case 0:
- puts("3 blinks ... entering BOOT mode.\n");
+ lcd_puts("entering BOOT-mode. ");
+ setenv("bootcmd", "run defaultAR");
buf = 0x0000;
break;
case 1:
- puts("2 blinks ... entering DIAGNOSE mode.\n");
+ lcd_puts("entering DIAGNOSE-mode. ");
buf = 0x0F0F;
break;
case 2:
- puts("1 blinks ... entering SERVICE mode.\n");
+ lcd_puts("entering SERVICE mode. ");
buf = 0xB4B4;
break;
case 3:
- puts("0 blinks ... entering RUN mode.\n");
+ lcd_puts("loading OS... ");
buf = 0x0404;
break;
}
- mdelay(ton);
- /* turn on light */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL1, 0x09, 0xFF);
/* write bootinfo into scratchregister of resetcontroller */
oldspeed = i2c_get_bus_speed();
if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
} else {
puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
}
+ /* setup vxworks bootline */
+ char *vxworksbootline = (char *)VXWORKS_BOOTLINE;
+
+ /* setup default IP, in case if there is nothing in environment */
+ if (!getenv("ipaddr")) {
+ setenv("ipaddr", "192.168.60.1");
+ setenv("netmask", "255.255.255.0");
+ setenv("serverip", "192.168.60.254");
+ setenv("gatewayip", "192.168.60.254");
+ puts("net: had no IP! made default setup.\n");
+ }
+
+ sprintf(vxworksbootline,
+ "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x",
+ DEFAULT_BOOTLINE,
+ getenv("serverip"),
+ getenv("ipaddr"), getenv("netmask"),
+ getenv("gatewayip"),
+ VXWORKS_USER,
+ (unsigned int) gd->fb_base-0x20,
+ (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
+ (u32)getenv_ulong("vx_romfsbase", 16, 0),
+ (u32)getenv_ulong("vx_romfssize", 16, 0));
+
/*
* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
* expect that vectors are there, original u-boot moves them to _start
#include <asm/io.h>
#include <i2c.h>
-static struct module_pin_mux usb0_pin_mux[] = {
- {OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
- /* USB0 DrvBus Receiver disable (from romcode 0x20) */
- {OFFSET(usb0_drvvbus), (MODE(0))},
- /* USB1 DrvBus as GPIO due to HW-Workaround */
- {OFFSET(usb1_drvvbus), (MODE(7))},
- {-1},
-};
-static struct module_pin_mux spi1_pin_mux[] = {
+static struct module_pin_mux spi0_pin_mux[] = {
/* SPI1_SCLK */
- {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
+ {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_D0 */
- {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
+ {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_D1 */
- {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
+ {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_CS0 */
- {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ /* SPI1_CS1 */
+ {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
};
static struct module_pin_mux gpios[] = {
- /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
- {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
- /* GPIO0_4 (SPI D1) - TA602 */
- {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
- /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */
- {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
/* GPIO0_7 (PWW0 OUT) - CAN TERM */
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
- /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
- {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
- /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
- {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO0_19 (DMA_INTR0) - TA602 */
+ {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
/* GPIO0_30 (GPMC_WAIT0) - TA601 */
{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+ /* GPIO1_29 (gpmc_csn0) - MMC nRST */
+ {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
/* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
/* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO2_4 (GPMC_nWE) - TST_BAST */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+ /* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */
+ {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
+ /* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
+ {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
+ {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
};
static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(usb0_pin_mux);
- configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(dcan0_pin_mux);
configure_module_pin_mux(dcan1_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
#include <i2c.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
+#include <lcd.h>
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
/* --------------------------------------------------------------------------*/
/* -- defines for GPIO -- */
-#define ETHLED_ORANGE (96+16) /* GPIO3_16 */
#define REPSWITCH (0+20) /* GPIO0_20 */
-
#if defined(CONFIG_SPL_BUILD)
/* TODO: check ram-timing ! */
static const struct ddr_data ddr3_data = {
int spl_start_uboot(void)
{
if (0 == gpio_get_value(REPSWITCH)) {
- blink(5, 125, ETHLED_ORANGE);
mdelay(1000);
printf("SPL: entering u-boot instead kernel image.\n");
return 1;
void am33xx_spl_board_init(void)
{
- pmicsetup(1000);
+ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+ /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
+ struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+
+ /*
+ * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
+ * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
+ * the source of timer6 clk to CLK_M_OSC
+ */
+ writel(0x01, &cmdpll->clktimer6clk);
+
+ /* enable additional clocks of modules which are accessed later */
+ u32 *const clk_domains[] = {
+ &cmper->lcdcclkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_tsspecific[] = {
+ &cmper->lcdclkctrl,
+ &cmper->timer5clkctrl,
+ &cmper->timer6clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
+
+ /* setup LCD-Pixel Clock */
+ writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */
+
+ pmicsetup(0);
}
const struct dpll_params *get_dpll_ddr_params(void)
/* Basic board specific setup. Pinmux has been handled already. */
int board_init(void)
{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND
gpmc_init();
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
- gpio_direction_output(ETHLED_ORANGE, 0);
-
if (0 == gpio_get_value(REPSWITCH)) {
- printf("\n\n\n"
- "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
- "!!!!!!! recovery switch activated !!!!!!!\n"
- "!!!!!!! running usbupdate !!!!!!!\n"
- "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
- setenv("bootcmd", "sleep 2; run netupdate;");
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "switching to network-console ... ");
+ setenv("bootcmd", "run netconsole");
}
-
- printf("turning on display power+backlight ... ");
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
- 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
- 0x62, TPS65217_MASK_ALL_BITS); /* 100% */
- printf("ok.\n");
-
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
+static struct module_pin_mux uart1_pin_mux[] = {
+ /* UART0_RXD */
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
#ifdef CONFIG_MMC
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
- /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
- {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */
+ /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
+ {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
+ /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
-
+#ifndef CONFIG_NAND
+ /* GPIO2_3 - NAND_OE */
+ {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+ /* GPIO2_4 - NAND_WEN */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+ /* GPIO2_5 - NAND_BE_CLE */
+ {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+#endif
{-1},
};
#endif
configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(uart1_pin_mux);
configure_module_pin_mux(gpIOs);
}
+++ /dev/null
-#
-# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# TEXT_BASE must equal the intended FLASH location of u-boot.
-CONFIG_SYS_TEXT_BASE = 0xfff90000
#include <miiphy.h>
#include <asm/arch/orion5x.h>
#include "../common/common.h"
+#include <spl.h>
+#include <ns16550.h>
DECLARE_GLOBAL_DATA_PTR;
-/*
- * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
- * which CFI does not properly detect, hence the LEGACY config.
- */
-#if defined(CONFIG_FLASH_CFI_LEGACY)
-#include <flash.h>
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
- int sect;
-
- if (base != CONFIG_SYS_FLASH_BASE)
- return 0;
-
- info->size = 0;
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- /* set each sector's start address and size based */
- for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
- info->start[sect] = base+info->size;
- info->size += sectsz[sect];
- }
- /* This flash must be accessed in 8-bits mode, no buffer. */
- info->flash_id = 0x01000000;
- info->portwidth = FLASH_CFI_8BIT;
- info->chipwidth = FLASH_CFI_BY8;
- info->buffer_size = 0;
- /* timings are derived from the Macronix datasheet. */
- info->erase_blk_tout = 1000;
- info->write_tout = 10;
- info->buffer_write_tout = 300;
- /* Commands and addresses are for AMD mode 8-bit access. */
- info->vendor = CFI_CMDSET_AMD_LEGACY;
- info->cmd_reset = 0xF0;
- info->interface = FLASH_CFI_X8;
- info->legacy_unlock = 0;
- info->ext_addr = 0;
- info->addr_unlock1 = 0x00000aaa;
- info->addr_unlock2 = 0x00000555;
- /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
- info->manufacturer_id = 0x22;
- info->device_id = 0xBA;
- info->device_id2 = 0;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x0000;
- info->name = "MX29LV400CB";
-
- return 1;
-}
-#endif /* CONFIG_SYS_FLASH_CFI */
-
int board_init(void)
{
/* arch number of board */
mv_phy_88e1116_init("egiga0", 8);
}
#endif /* CONFIG_RESET_PHY_R */
+
+/*
+ * SPL serial setup and NOR boot device selection
+ */
+
+#ifdef CONFIG_SPL_BUILD
+
+void spl_board_init(void)
+{
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NOR;
+}
+
+#endif /* CONFIG_SPL_BUILD */
default "socfpga_cyclone5"
endif
+
+if TARGET_SOCFPGA_ARRIA5
+
+config SYS_BOARD
+ default "socfpga"
+
+config SYS_VENDOR
+ default "altera"
+
+config SYS_SOC
+ default "socfpga"
+
+config SYS_CONFIG_NAME
+ default "socfpga_arria5"
+
+endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := socfpga_cyclone5.o
+obj-y := socfpga.o
obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
#include <iocsr_config.h>
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
const unsigned long iocsr_scan_chain0_table[((
CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
0x0000001F,
0x00004100,
};
+#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+const unsigned long iocsr_scan_chain0_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000060,
+ 0x00018060,
+ 0x06018060,
+ 0x00004000,
+ 0x0C0300C0,
+ 0x0C030000,
+ 0x00000030,
+ 0x00000000,
+ 0x00000000,
+ 0x00002000,
+ 0x00000000,
+ 0x00000000,
+ 0x06000000,
+ 0x00006018,
+ 0x01806018,
+ 0x00001000,
+ 0x0000C030,
+ 0x04000000,
+ 0x03000000,
+ 0x0000300C,
+ 0x00000000,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x01800000,
+ 0x00000006,
+ 0x00001806,
+ 0x00000400,
+ 0x0000300C,
+ 0x00C03000,
+ 0x00C00000,
+ 0x00000003,
+ 0x00000C03,
+ 0x00000200,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+ 0x00100000,
+ 0x300C0000,
+ 0x300000C0,
+ 0x000000C0,
+ 0x000300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x10000000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0000C030,
+ 0x0300C000,
+ 0x03000000,
+ 0x0000300C,
+ 0x0000300C,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x01800000,
+ 0x00000006,
+ 0x00002000,
+ 0x00000400,
+ 0x0000300C,
+ 0x01000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000C03,
+ 0x00000200,
+ 0x00001806,
+ 0x00800000,
+ 0x00000000,
+ 0x00000002,
+ 0x00000800,
+ 0x00000100,
+ 0x00001000,
+ 0x00400000,
+ 0xC0300000,
+ 0x00000000,
+ 0x00000400,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+ 0x00100000,
+ 0x40000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00040000,
+ 0x00008000,
+ 0x18060180,
+ 0x20000000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00002000,
+ 0x10038060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000020,
+ 0x01806018,
+ 0x00001000,
+ 0x00010000,
+ 0x04000000,
+ 0x03000000,
+ 0x0000801C,
+ 0x00004000,
+ 0x00000800,
+ 0x01806018,
+ 0x02000000,
+ 0x00000000,
+ 0x00000008,
+ 0x00002000,
+ 0x00000400,
+ 0x00C0300C,
+ 0x00C03000,
+ 0x00C00003,
+ 0x00000C03,
+ 0x00300C03,
+ 0x00000200,
+ 0x00601806,
+ 0x80601800,
+ 0x80600001,
+ 0x80000601,
+ 0x00180601,
+ 0x00000100,
+};
+
+const unsigned long iocsr_scan_chain3_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+ 0x2C820D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xE4400000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D0000,
+ 0x24906808,
+ 0x00A28340,
+ 0xD000001A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000FF0,
+ 0x72200000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x6A1C0000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x1A870001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00040,
+ 0xA20D0002,
+ 0x24906808,
+ 0x00A28340,
+ 0xD005141A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x04510680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00600391,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x8341D348,
+ 0x821A0124,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00481800,
+ 0x001A1A1A,
+ 0x085506A0,
+ 0x0000E1D4,
+ 0x045506A0,
+ 0x0000E1D4,
+ 0x085506A0,
+ 0x8000E1D4,
+ 0x00000200,
+ 0x00000004,
+ 0x04000000,
+ 0x00000009,
+ 0x00002410,
+ 0x00000040,
+ 0x41000000,
+ 0x00002082,
+ 0x00000350,
+ 0x000000DA,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x022A8350,
+ 0x000070EA,
+ 0x86000000,
+ 0x08000004,
+ 0x00000000,
+ 0x00482000,
+ 0x21800000,
+ 0x00101061,
+ 0x021541A8,
+ 0x00003875,
+ 0x011541A8,
+ 0x00003875,
+ 0x021541A8,
+ 0x20003875,
+ 0x00000080,
+ 0x00000001,
+ 0x41000000,
+ 0x00000002,
+ 0x00FF0904,
+ 0x00000000,
+ 0x90400000,
+ 0x00000820,
+ 0xC0000001,
+ 0xFFD602AF,
+ 0x86FFFFFF,
+ 0x0A0A78B4,
+ 0x000D020A,
+ 0x00006800,
+ 0x028A4320,
+ 0xEC2CB23D,
+ 0x8F5D1451,
+ 0xA47A88A2,
+ 0x0001A0E9,
+ 0x00410D00,
+ 0x40000068,
+ 0x3D000003,
+ 0x51EC2CB2,
+ 0xA28F5D14,
+ 0xE9A47A88,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000540,
+ 0x000003A8,
+ 0x08AA0D40,
+ 0x8001C3A8,
+ 0x0000007F,
+ 0x00000000,
+ 0x00004060,
+ 0xE1208000,
+ 0x0000001F,
+ 0x00004100,
+};
+#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
#ifndef _PRELOADER_IOCSR_CONFIG_H_
#define _PRELOADER_IOCSR_CONFIG_H_
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
+#endif
#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
#include "pinmux_config.h"
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
/* pin mux configuration data */
unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
- 0, /* EMACIO0 - Unused */
- 2, /* EMACIO1 - USB */
- 2, /* EMACIO2 - USB */
- 2, /* EMACIO3 - USB */
- 2, /* EMACIO4 - USB */
- 2, /* EMACIO5 - USB */
- 2, /* EMACIO6 - USB */
- 2, /* EMACIO7 - USB */
- 2, /* EMACIO8 - USB */
- 0, /* EMACIO9 - Unused */
- 2, /* EMACIO10 - USB */
- 2, /* EMACIO11 - USB */
- 2, /* EMACIO12 - USB */
- 2, /* EMACIO13 - USB */
- 0, /* EMACIO14 - N/A */
- 0, /* EMACIO15 - N/A */
- 0, /* EMACIO16 - N/A */
- 0, /* EMACIO17 - N/A */
- 0, /* EMACIO18 - N/A */
- 0, /* EMACIO19 - N/A */
- 3, /* FLASHIO0 - SDMMC */
- 3, /* FLASHIO1 - SDMMC */
- 3, /* FLASHIO2 - SDMMC */
- 3, /* FLASHIO3 - SDMMC */
- 0, /* FLASHIO4 - SDMMC */
- 0, /* FLASHIO5 - SDMMC */
- 0, /* FLASHIO6 - SDMMC */
- 0, /* FLASHIO7 - SDMMC */
- 0, /* FLASHIO8 - SDMMC */
- 3, /* FLASHIO9 - SDMMC */
- 3, /* FLASHIO10 - SDMMC */
- 3, /* FLASHIO11 - SDMMC */
- 3, /* GENERALIO0 - TRACE */
- 3, /* GENERALIO1 - TRACE */
- 3, /* GENERALIO2 - TRACE */
- 3, /* GENERALIO3 - TRACE */
- 3, /* GENERALIO4 - TRACE */
- 3, /* GENERALIO5 - TRACE */
- 3, /* GENERALIO6 - TRACE */
- 3, /* GENERALIO7 - TRACE */
- 3, /* GENERALIO8 - TRACE */
- 3, /* GENERALIO9 - SPIM0 */
- 3, /* GENERALIO10 - SPIM0 */
- 3, /* GENERALIO11 - SPIM0 */
- 3, /* GENERALIO12 - SPIM0 */
- 2, /* GENERALIO13 - CAN0 */
- 2, /* GENERALIO14 - CAN0 */
- 3, /* GENERALIO15 - I2C0 */
- 3, /* GENERALIO16 - I2C0 */
- 2, /* GENERALIO17 - UART0 */
- 2, /* GENERALIO18 - UART0 */
- 0, /* GENERALIO19 - N/A */
- 0, /* GENERALIO20 - N/A */
- 0, /* GENERALIO21 - N/A */
- 0, /* GENERALIO22 - N/A */
- 0, /* GENERALIO23 - N/A */
- 0, /* GENERALIO24 - N/A */
- 0, /* GENERALIO25 - N/A */
- 0, /* GENERALIO26 - N/A */
- 0, /* GENERALIO27 - N/A */
- 0, /* GENERALIO28 - N/A */
- 0, /* GENERALIO29 - N/A */
- 0, /* GENERALIO30 - N/A */
- 0, /* GENERALIO31 - N/A */
- 2, /* MIXED1IO0 - EMAC */
- 2, /* MIXED1IO1 - EMAC */
- 2, /* MIXED1IO2 - EMAC */
- 2, /* MIXED1IO3 - EMAC */
- 2, /* MIXED1IO4 - EMAC */
- 2, /* MIXED1IO5 - EMAC */
- 2, /* MIXED1IO6 - EMAC */
- 2, /* MIXED1IO7 - EMAC */
- 2, /* MIXED1IO8 - EMAC */
- 2, /* MIXED1IO9 - EMAC */
- 2, /* MIXED1IO10 - EMAC */
- 2, /* MIXED1IO11 - EMAC */
- 2, /* MIXED1IO12 - EMAC */
- 2, /* MIXED1IO13 - EMAC */
- 0, /* MIXED1IO14 - Unused */
- 3, /* MIXED1IO15 - QSPI */
- 3, /* MIXED1IO16 - QSPI */
- 3, /* MIXED1IO17 - QSPI */
- 3, /* MIXED1IO18 - QSPI */
- 3, /* MIXED1IO19 - QSPI */
- 3, /* MIXED1IO20 - QSPI */
- 0, /* MIXED1IO21 - GPIO */
- 0, /* MIXED2IO0 - N/A */
- 0, /* MIXED2IO1 - N/A */
- 0, /* MIXED2IO2 - N/A */
- 0, /* MIXED2IO3 - N/A */
- 0, /* MIXED2IO4 - N/A */
- 0, /* MIXED2IO5 - N/A */
- 0, /* MIXED2IO6 - N/A */
- 0, /* MIXED2IO7 - N/A */
+ 3, /* EMACIO0 */
+ 3, /* EMACIO1 */
+ 3, /* EMACIO2 */
+ 3, /* EMACIO3 */
+ 3, /* EMACIO4 */
+ 3, /* EMACIO5 */
+ 3, /* EMACIO6 */
+ 3, /* EMACIO7 */
+ 3, /* EMACIO8 */
+ 3, /* EMACIO9 */
+ 3, /* EMACIO10 */
+ 3, /* EMACIO11 */
+ 3, /* EMACIO12 */
+ 3, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 3, /* FLASHIO4 */
+ 3, /* FLASHIO5 */
+ 3, /* FLASHIO6 */
+ 3, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 0, /* GENERALIO3 */
+ 0, /* GENERALIO4 */
+ 1, /* GENERALIO5 */
+ 1, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 2, /* GENERALIO13 */
+ 2, /* GENERALIO14 */
+ 0, /* GENERALIO15 */
+ 0, /* GENERALIO16 */
+ 0, /* GENERALIO17 */
+ 0, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 0, /* MIXED1IO0 */
+ 1, /* MIXED1IO1 */
+ 1, /* MIXED1IO2 */
+ 1, /* MIXED1IO3 */
+ 1, /* MIXED1IO4 */
+ 0, /* MIXED1IO5 */
+ 0, /* MIXED1IO6 */
+ 0, /* MIXED1IO7 */
+ 1, /* MIXED1IO8 */
+ 1, /* MIXED1IO9 */
+ 1, /* MIXED1IO10 */
+ 1, /* MIXED1IO11 */
+ 0, /* MIXED1IO12 */
+ 0, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 1, /* MIXED1IO15 */
+ 1, /* MIXED1IO16 */
+ 1, /* MIXED1IO17 */
+ 1, /* MIXED1IO18 */
+ 0, /* MIXED1IO19 */
+ 0, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
0, /* GPLINMUX48 */
0, /* GPLINMUX49 */
0, /* GPLINMUX50 */
0, /* USB0USEFPGA */
0 /* SPIM0USEFPGA */
};
+#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+/* pin mux configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 3, /* EMACIO14 */
+ 3, /* EMACIO15 */
+ 3, /* EMACIO16 */
+ 3, /* EMACIO17 */
+ 3, /* EMACIO18 */
+ 3, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 3, /* GENERALIO0 */
+ 3, /* GENERALIO1 */
+ 3, /* GENERALIO2 */
+ 3, /* GENERALIO3 */
+ 3, /* GENERALIO4 */
+ 3, /* GENERALIO5 */
+ 3, /* GENERALIO6 */
+ 3, /* GENERALIO7 */
+ 3, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 0, /* GENERALIO13 */
+ 0, /* GENERALIO14 */
+ 3, /* GENERALIO15 */
+ 3, /* GENERALIO16 */
+ 2, /* GENERALIO17 */
+ 2, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 3, /* GENERALIO23 */
+ 3, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 0, /* MIXED1IO0 */
+ 0, /* MIXED1IO1 */
+ 0, /* MIXED1IO2 */
+ 0, /* MIXED1IO3 */
+ 0, /* MIXED1IO4 */
+ 0, /* MIXED1IO5 */
+ 0, /* MIXED1IO6 */
+ 0, /* MIXED1IO7 */
+ 0, /* MIXED1IO8 */
+ 0, /* MIXED1IO9 */
+ 0, /* MIXED1IO10 */
+ 0, /* MIXED1IO11 */
+ 0, /* MIXED1IO12 */
+ 0, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 3, /* MIXED2IO0 */
+ 3, /* MIXED2IO1 */
+ 3, /* MIXED2IO2 */
+ 3, /* MIXED2IO3 */
+ 3, /* MIXED2IO4 */
+ 3, /* MIXED2IO5 */
+ 3, /* MIXED2IO6 */
+ 3, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
* State of enabling for which IP connected out through the muxing.
* Value 1 mean the IP connection is muxed out
*/
-#define CONFIG_HPS_EMAC0 (0)
-#define CONFIG_HPS_EMAC1 (1)
+#define CONFIG_HPS_EMAC0 (1)
+#define CONFIG_HPS_EMAC1 (0)
#define CONFIG_HPS_USB0 (0)
#define CONFIG_HPS_USB1 (1)
#define CONFIG_HPS_NAND (0)
#define CONFIG_HPS_SDMMC (1)
-#define CONFIG_HPS_QSPI (1)
+#define CONFIG_HPS_QSPI (0)
#define CONFIG_HPS_UART0 (1)
#define CONFIG_HPS_UART1 (0)
-#define CONFIG_HPS_TRACE (1)
+#define CONFIG_HPS_TRACE (0)
#define CONFIG_HPS_I2C0 (1)
#define CONFIG_HPS_I2C1 (0)
#define CONFIG_HPS_I2C2 (0)
#define CONFIG_HPS_I2C3 (0)
-#define CONFIG_HPS_SPIM0 (1)
+#define CONFIG_HPS_SPIM0 (0)
#define CONFIG_HPS_SPIM1 (0)
#define CONFIG_HPS_SPIS0 (0)
#define CONFIG_HPS_SPIS1 (0)
#define CONFIG_HPS_CAN1 (0)
/* IP attribute value (which affected by pin muxing configuration) */
-#define CONFIG_HPS_SDMMC_BUSWIDTH (4)
+#define CONFIG_HPS_SDMMC_BUSWIDTH (8)
/* 1 if the pins are connected out */
-#define CONFIG_HPS_QSPI_CS0 (1)
+#define CONFIG_HPS_QSPI_CS0 (0)
#define CONFIG_HPS_QSPI_CS1 (0)
#define CONFIG_HPS_QSPI_CS2 (0)
#define CONFIG_HPS_QSPI_CS3 (0)
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
/* Peripheral PLL */
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
/*
* To tell where is the VCOs source:
* 0 = EOSC1
*/
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
/* SDRAM PLL */
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
- * This if..else... is not required if generated by tools */
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127)
-#else
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
/*
* To tell where is the VCOs source:
/* Info for driver */
#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
-#define CONFIG_HPS_CLK_OSC2_HZ 0
+#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000)
-#else
-#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
-#endif
+#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666)
#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
DECLARE_GLOBAL_DATA_PTR;
-/*
- * Print Board information
- */
-int checkboard(void)
-{
- puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
- return 0;
-}
-
-/*
- * Initialization function which happen at early stage of c code
- */
-int board_early_init_f(void)
-{
- return 0;
-}
-
/*
* Miscellaneous platform dependent initialisations
*/
int dram_init(void)
{
- /*
- * Clear spin table so that secondary processors
- * observe the correct value after waken up from wfe.
- */
- *(unsigned long *)CPU_RELEASE_ADDR = 0;
-
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
+++ /dev/null
-if TARGET_BC3450
-
-config SYS_BOARD
- default "bc3450"
-
-config SYS_CONFIG_NAME
- default "BC3450"
-
-endif
+++ /dev/null
-BC3450 BOARD
-#M: -
-S: Maintained
-F: board/bc3450/
-F: include/configs/BC3450.h
-F: configs/BC3450_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bc3450.o cmd_bc3450.o
+++ /dev/null
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * (C) Copyright 2006
- * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-
-#ifdef CONFIG_VIDEO_SM501
-#include <sm501.h>
-#endif
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m16a2-75.h"
-#endif
-
-#ifdef CONFIG_RTC_MPC5200
-#include <rtc.h>
-#endif
-
-#ifdef CONFIG_PS2MULT
-void ps2mult_early_init(void);
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
- hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
- hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
- hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
- hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
- __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
-
- /* find RAM size using SDRAM CS1 only */
- sdram_start(0);
- test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
- sdram_start(1);
- test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
- | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize;
-}
-
-int checkboard (void)
-{
-#if defined (CONFIG_TQM5200)
- puts ("Board: TQM5200 (TQ-Components GmbH)\n");
-#endif
-
-#if defined (CONFIG_BC3450)
- puts ("Dev: GERSYS BC3450\n");
-#endif
-
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
- }
-}
-#endif
-
-#ifdef CONFIG_POST
-/*
- * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
- * is left open, no keypress is detected.
- */
-int post_hotkeys_pressed(void)
-{
- struct mpc5xxx_gpio *gpio;
-
- gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
-
- /*
- * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
- * CODEC or UART mode. Consumer IrDA should still be possible.
- */
- gpio->port_config &= ~(0x07000000);
- gpio->port_config |= 0x03000000;
-
- /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
- gpio->simple_gpioe |= 0x20000000;
-
- /* Configure GPIO_IRDA_1 as input */
- gpio->simple_ddr &= ~(0x20000000);
-
- return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
-}
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_R
-int board_early_init_r (void)
-{
-#ifdef CONFIG_RTC_MPC5200
- struct rtc_time t;
-
- /* set to Wed Dec 31 19:00:00 1969 */
- t.tm_sec = t.tm_min = 0;
- t.tm_hour = 19;
- t.tm_mday = 31;
- t.tm_mon = 12;
- t.tm_year = 1969;
- t.tm_wday = 3;
-
- rtc_set(&t);
-#endif /* CONFIG_RTC_MPC5200 */
-
-#ifdef CONFIG_PS2MULT
- ps2mult_early_init();
-#endif /* CONFIG_PS2MULT */
- return (0);
-}
-#endif /* CONFIG_BOARD_EARLY_INIT_R */
-
-
-int last_stage_init (void)
-{
- /*
- * auto scan for really existing devices and re-set chip select
- * configuration.
- */
- u16 save, tmp;
- int restore;
-
- /*
- * Check for SRAM and SRAM size
- */
-
- /* save original SRAM content */
- save = *(volatile u16 *)CONFIG_SYS_CS2_START;
- restore = 1;
-
- /* write test pattern to SRAM */
- *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
- __asm__ volatile ("sync");
- /*
- * Put a different pattern on the data lines: otherwise they may float
- * long enough to read back what we wrote.
- */
- tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
- if (tmp == 0xA5A5)
- puts ("!! possible error in SRAM detection\n");
-
- if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
- /* no SRAM at all, disable cs */
- *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
- *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
- *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
- restore = 0;
- __asm__ volatile ("sync");
- } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
- /* make sure that we access a mirrored address */
- *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
- __asm__ volatile ("sync");
- if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
- /* SRAM size = 512 kByte */
- *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
- 0x80000);
- __asm__ volatile ("sync");
- puts ("SRAM: 512 kB\n");
- }
- else
- puts ("!! possible error in SRAM detection\n");
- } else {
- puts ("SRAM: 1 MB\n");
- }
- /* restore origianl SRAM content */
- if (restore) {
- *(volatile u16 *)CONFIG_SYS_CS2_START = save;
- __asm__ volatile ("sync");
- }
-
- /*
- * Check for Grafic Controller
- */
-
- /* save origianl FB content */
- save = *(volatile u16 *)CONFIG_SYS_CS1_START;
- restore = 1;
-
- /* write test pattern to FB memory */
- *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
- __asm__ volatile ("sync");
- /*
- * Put a different pattern on the data lines: otherwise they may float
- * long enough to read back what we wrote.
- */
- tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
- if (tmp == 0xA5A5)
- puts ("!! possible error in grafic controller detection\n");
-
- if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
- /* no grafic controller at all, disable cs */
- *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
- *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
- *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
- restore = 0;
- __asm__ volatile ("sync");
- } else {
- puts ("VGA: SMI501 (Voyager) with 8 MB\n");
- }
- /* restore origianl FB content */
- if (restore) {
- *(volatile u16 *)CONFIG_SYS_CS1_START = save;
- __asm__ volatile ("sync");
- }
-
- return 0;
-}
-
-#ifdef CONFIG_VIDEO_SM501
-
-#define DISPLAY_WIDTH 640
-#define DISPLAY_HEIGHT 480
-
-#ifdef CONFIG_VIDEO_SM501_8BPP
-#error CONFIG_VIDEO_SM501_8BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_8BPP */
-
-#ifdef CONFIG_VIDEO_SM501_16BPP
-#error CONFIG_VIDEO_SM501_16BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_16BPP */
-
-#ifdef CONFIG_VIDEO_SM501_32BPP
-static const SMI_REGS init_regs [] =
-{
-#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
- /* FP only */
- {0x00004, 0x0},
- {0x00048, 0x00021807},
- {0x0004C, 0x091a0a01},
- {0x00054, 0x1},
- {0x00040, 0x00021807},
- {0x00044, 0x091a0a01},
- {0x00054, 0x0},
- {0x80000, 0x01013106},
- {0x80004, 0xc428bb17},
- {0x80000, 0x03013106},
- {0x8000C, 0x00000000},
- {0x80010, 0x0a000a00},
- {0x80014, 0x02800000},
- {0x80018, 0x01e00000},
- {0x8001C, 0x00000000},
- {0x80020, 0x01e00280},
- {0x80024, 0x02fa027f},
- {0x80028, 0x004a028b},
- {0x8002C, 0x020c01df},
- {0x80030, 0x000201e9},
- {0x80200, 0x00010200},
- {0x80000, 0x0f013106},
-#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
- /* CRT only */
- {0x00004, 0x0},
- {0x00048, 0x00021807},
- {0x0004C, 0x10090a01},
- {0x00054, 0x1},
- {0x00040, 0x00021807},
- {0x00044, 0x10090a01},
- {0x00054, 0x0},
- {0x80200, 0x00010000},
- {0x80204, 0x0},
- {0x80208, 0x0A000A00},
- {0x8020C, 0x02fa027f},
- {0x80210, 0x004a028b},
- {0x80214, 0x020c01df},
- {0x80218, 0x000201e9},
- {0x80200, 0x00013306},
-#else /* panel + CRT */
- {0x00004, 0x0},
- {0x00048, 0x00021807},
- {0x0004C, 0x091a0a01},
- {0x00054, 0x1},
- {0x00040, 0x00021807},
- {0x00044, 0x091a0a01},
- {0x00054, 0x0},
- {0x80000, 0x0f013106},
- {0x80004, 0xc428bb17},
- {0x8000C, 0x00000000},
- {0x80010, 0x0a000a00},
- {0x80014, 0x02800000},
- {0x80018, 0x01e00000},
- {0x8001C, 0x00000000},
- {0x80020, 0x01e00280},
- {0x80024, 0x02fa027f},
- {0x80028, 0x004a028b},
- {0x8002C, 0x020c01df},
- {0x80030, 0x000201e9},
- {0x80200, 0x00010000},
-#endif
- {0, 0}
-};
-#endif /* CONFIG_VIDEO_SM501_32BPP */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
- if (line_number == 1) {
-#if defined (CONFIG_TQM5200)
- strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#else
-#error No supported board selected
-#endif /* CONFIG_TQM5200 */
-
-#if defined (CONFIG_BC3450)
- } else if (line_number == 2) {
- strcpy (info, " Dev: GERSYS BC3450");
-#endif /* CONFIG_BC3450 */
- }
- else {
- info [0] = '\0';
- }
-}
-#endif
-
-/*
- * Returns SM501 register base address. First thing called in the
- * driver. Checks if SM501 is physically present.
- */
-unsigned int board_video_init (void)
-{
- u16 save, tmp;
- int restore, ret;
-
- /*
- * Check for Grafic Controller
- */
-
- /* save origianl FB content */
- save = *(volatile u16 *)CONFIG_SYS_CS1_START;
- restore = 1;
-
- /* write test pattern to FB memory */
- *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
- __asm__ volatile ("sync");
- /*
- * Put a different pattern on the data lines: otherwise they may float
- * long enough to read back what we wrote.
- */
- tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
- if (tmp == 0xA5A5)
- puts ("!! possible error in grafic controller detection\n");
-
- if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
- /* no grafic controller found */
- restore = 0;
- ret = 0;
- } else {
- ret = SM501_MMIO_BASE;
- }
-
- if (restore) {
- *(volatile u16 *)CONFIG_SYS_CS1_START = save;
- __asm__ volatile ("sync");
- }
- return ret;
-}
-
-/*
- * Returns SM501 framebuffer address
- */
-unsigned int board_video_get_fb (void)
-{
- return SM501_FB_BASE;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen (unsigned int base)
-{
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs (void)
-{
- return init_regs;
-}
-
-int board_get_width (void)
-{
- return DISPLAY_WIDTH;
-}
-
-int board_get_height (void)
-{
- return DISPLAY_HEIGHT;
-}
-
-#endif /* CONFIG_VIDEO_SM501 */
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in FEC comes first */
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
- *
- * (C) Copyright 2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-
-/*
- * BC3450 specific commands
- */
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Definitions for DS1620 chip
- */
-#define THERM_START_CONVERT 0xee
-#define THERM_RESET 0xaf
-#define THERM_READ_CONFIG 0xac
-#define THERM_READ_TEMP 0xaa
-#define THERM_READ_TL 0xa2
-#define THERM_READ_TH 0xa1
-#define THERM_WRITE_CONFIG 0x0c
-#define THERM_WRITE_TL 0x02
-#define THERM_WRITE_TH 0x01
-
-#define CONFIG_SYS_1SHOT 1
-#define CONFIG_SYS_STANDALONE 0
-
-struct therm {
- int hi;
- int lo;
-};
-
-/*
- * SM501 Register
- */
-#define SM501_GPIO_CTRL_LOW 0x00000008UL /* gpio pins 0..31 */
-#define SM501_GPIO_CTRL_HIGH 0x0000000CUL /* gpio pins 32..63 */
-#define SM501_POWER_MODE0_GATE 0x00000040UL
-#define SM501_POWER_MODE1_GATE 0x00000048UL
-#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
-#define SM501_GPIO_DATA_LOW 0x00010000UL
-#define SM501_GPIO_DATA_HIGH 0x00010004UL
-#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL
-#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
-#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
-#define SM501_CRT_DISPLAY_CONTROL 0x00080200UL
-
-/* SM501 CRT Display Control Bits */
-#define SM501_CDC_SEL (1 << 9)
-#define SM501_CDC_TE (1 << 8)
-#define SM501_CDC_E (1 << 2)
-
-/* SM501 Panel Display Control Bits */
-#define SM501_PDC_FPEN (1 << 27)
-#define SM501_PDC_BIAS (1 << 26)
-#define SM501_PDC_DATA (1 << 25)
-#define SM501_PDC_VDDEN (1 << 24)
-
-/* SM501 GPIO Data LOW Bits */
-#define SM501_GPIO24 0x01000000
-#define SM501_GPIO25 0x02000000
-#define SM501_GPIO26 0x04000000
-#define SM501_GPIO27 0x08000000
-#define SM501_GPIO28 0x10000000
-#define SM501_GPIO29 0x20000000
-#define SM501_GPIO30 0x40000000
-#define SM501_GPIO31 0x80000000
-
-/* SM501 GPIO Data HIGH Bits */
-#define SM501_GPIO46 0x00004000
-#define SM501_GPIO47 0x00008000
-#define SM501_GPIO48 0x00010000
-#define SM501_GPIO49 0x00020000
-#define SM501_GPIO50 0x00040000
-#define SM501_GPIO51 0x00080000
-
-/* BC3450 GPIOs @ SM501 Data LOW */
-#define DIP (SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27)
-#define DS1620_DQ SM501_GPIO29 /* I/O */
-#define DS1620_CLK SM501_GPIO30 /* High active O/P */
-#define DS1620_RES SM501_GPIO31 /* Low active O/P */
-/* BC3450 GPIOs @ SM501 Data HIGH */
-#define BUZZER SM501_GPIO47 /* Low active O/P */
-#define DS1620_TLOW SM501_GPIO48 /* High active I/P */
-#define PWR_OFF SM501_GPIO49 /* Low active O/P */
-#define FP_DATA_TRI SM501_GPIO50 /* High active O/P */
-
-
-/*
- * Initialise GPIO on SM501
- *
- * This function may be called from several other functions.
- * Yet, the initialisation sequence is executed only the first
- * time the function is called.
- */
-int sm501_gpio_init (void)
-{
- static int init_done = 0;
-
- if (init_done) {
- debug("sm501_gpio_init: nothing to be done.\n");
- return 1;
- }
-
- /* enable SM501 GPIO control (in both power modes) */
- *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |=
- POWER_MODE_GATE_GPIO_PWM_I2C;
- *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |=
- POWER_MODE_GATE_GPIO_PWM_I2C;
-
- /* set up default O/Ps */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
- ~(DS1620_RES | DS1620_CLK);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
- ~(FP_DATA_TRI);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
- (BUZZER | PWR_OFF);
-
- /* configure directions for SM501 GPIO pins */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &=
- ~(0x3F << 14);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &=
- ~(DIP | DS1620_DQ);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |=
- (DS1620_RES | DS1620_CLK);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &=
- ~DS1620_TLOW;
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |=
- (PWR_OFF | BUZZER | FP_DATA_TRI);
-
- init_done = 1;
- debug("sm501_gpio_init: done.\n");
-
- return 0;
-}
-
-
-/*
- * dip - read Config Inputs
- *
- * read and prints the dip switch
- * and/or external config inputs (4bits) 0...0x0F
- */
-int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- vu_long rc = 0;
-
- sm501_gpio_init ();
-
- /* read dip switch */
- rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
- rc = ~rc;
- rc &= DIP;
- rc = (int) (rc >> 24);
-
- /* plausibility check */
- if (rc > 0x0F)
- return -1;
-
- printf ("0x%lx\n", rc);
- return 0;
-}
-
-U_BOOT_CMD (dip, 1, 1, cmd_dip,
- "read dip switch and config inputs",
- "\n"
- " - prints the state of the dip switch and/or\n"
- " external configuration inputs as hex value.\n"
- " - \"Config 1\" is the LSB");
-
-
-/*
- * buz - turns Buzzer on/off
- */
-#ifdef CONFIG_BC3450_BUZZER
-static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc != 2) {
- printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
- return 1;
- }
-
- sm501_gpio_init ();
-
- if (strncmp (argv[1], "on", 2) == 0) {
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
- ~(BUZZER);
- return 0;
- } else if (strncmp (argv[1], "off", 3) == 0) {
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
- BUZZER;
- return 0;
- }
- printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
- return 1;
-}
-
-U_BOOT_CMD (buz, 2, 1, cmd_buz,
- "turns buzzer on/off",
- "\n" "buz <on/off>\n" " - turns the buzzer on or off");
-#endif /* CONFIG_BC3450_BUZZER */
-
-
-/*
- * fp - front panel commands
- */
-static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- sm501_gpio_init ();
-
- if (strncmp (argv[1], "on", 2) == 0) {
- /* turn on VDD first */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN;
- udelay (1000);
- /* then put data on */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA;
- /* wait some time and enable backlight */
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
- return 0;
- } else if (strncmp (argv[1], "off", 3) == 0) {
- /* turn off the backlight first */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
- udelay (200000);
- /* wait some time, then remove data */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
- udelay (1000);
- /* and remove VDD last */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &=
- ~SM501_PDC_VDDEN;
- return 0;
- } else if (strncmp (argv[1], "bl", 2) == 0) {
- /* turn on/off backlight only */
- if (strncmp (argv[2], "on", 2) == 0) {
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |=
- SM501_PDC_BIAS;
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |=
- SM501_PDC_FPEN;
- return 0;
- } else if (strncmp (argv[2], "off", 3) == 0) {
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &=
- ~SM501_PDC_FPEN;
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &=
- ~SM501_PDC_BIAS;
- return 0;
- }
- }
-#ifdef CONFIG_BC3450_CRT
- else if (strncmp (argv[1], "crt", 3) == 0) {
- /* enables/disables the crt output (debug only) */
- if (strncmp (argv[2], "on", 2) == 0) {
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_CRT_DISPLAY_CONTROL) |=
- (SM501_CDC_TE | SM501_CDC_E);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_CRT_DISPLAY_CONTROL) &=
- ~SM501_CDC_SEL;
- return 0;
- } else if (strncmp (argv[2], "off", 3) == 0) {
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_CRT_DISPLAY_CONTROL) &=
- ~(SM501_CDC_TE | SM501_CDC_E);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_CRT_DISPLAY_CONTROL) |=
- SM501_CDC_SEL;
- return 0;
- }
- }
-#endif /* CONFIG_BC3450_CRT */
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
-}
-
-U_BOOT_CMD (fp, 3, 1, cmd_fp,
- "front panes access functions",
- "\n"
- "fp bl <on/off>\n"
- " - turns the CCFL backlight of the display on/off\n"
- "fp <on/off>\n" " - turns the whole display on/off"
-#ifdef CONFIG_BC3450_CRT
- "\n"
- "fp crt <on/off>\n"
- " - enables/disables the crt output (debug only)"
-#endif /* CONFIG_BC3450_CRT */
- );
-
-/*
- * temp - DS1620 thermometer
- */
-/* GERSYS BC3450 specific functions */
-static inline void bc_ds1620_set_clk (int clk)
-{
- if (clk)
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
- DS1620_CLK;
- else
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
- ~DS1620_CLK;
-}
-
-static inline void bc_ds1620_set_data (int dat)
-{
- if (dat)
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
- DS1620_DQ;
- else
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
- ~DS1620_DQ;
-}
-
-static inline int bc_ds1620_get_data (void)
-{
- vu_long rc;
-
- rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
- rc &= DS1620_DQ;
- if (rc != 0)
- rc = 1;
- return (int) rc;
-}
-
-static inline void bc_ds1620_set_data_dir (int dir)
-{
- if (dir) /* in */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
- else /* out */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ;
-}
-
-static inline void bc_ds1620_set_reset (int res)
-{
- if (res)
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES;
- else
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
-}
-
-/* hardware independent functions */
-static void ds1620_send_bits (int nr, int value)
-{
- int i;
-
- for (i = 0; i < nr; i++) {
- bc_ds1620_set_data (value & 1);
- bc_ds1620_set_clk (0);
- udelay (1);
- bc_ds1620_set_clk (1);
- udelay (1);
-
- value >>= 1;
- }
-}
-
-static unsigned int ds1620_recv_bits (int nr)
-{
- unsigned int value = 0, mask = 1;
- int i;
-
- bc_ds1620_set_data (0);
-
- for (i = 0; i < nr; i++) {
- bc_ds1620_set_clk (0);
- udelay (1);
-
- if (bc_ds1620_get_data ())
- value |= mask;
-
- mask <<= 1;
-
- bc_ds1620_set_clk (1);
- udelay (1);
- }
-
- return value;
-}
-
-static void ds1620_out (int cmd, int bits, int value)
-{
- bc_ds1620_set_clk (1);
- bc_ds1620_set_data_dir (0);
-
- bc_ds1620_set_reset (0);
- udelay (1);
- bc_ds1620_set_reset (1);
-
- udelay (1);
-
- ds1620_send_bits (8, cmd);
- if (bits)
- ds1620_send_bits (bits, value);
-
- udelay (1);
-
- /* go stand alone */
- bc_ds1620_set_data_dir (1);
- bc_ds1620_set_reset (0);
- bc_ds1620_set_clk (0);
-
- udelay (10000);
-}
-
-static unsigned int ds1620_in (int cmd, int bits)
-{
- unsigned int value;
-
- bc_ds1620_set_clk (1);
- bc_ds1620_set_data_dir (0);
-
- bc_ds1620_set_reset (0);
- udelay (1);
- bc_ds1620_set_reset (1);
-
- udelay (1);
-
- ds1620_send_bits (8, cmd);
-
- bc_ds1620_set_data_dir (1);
- value = ds1620_recv_bits (bits);
-
- /* go stand alone */
- bc_ds1620_set_data_dir (1);
- bc_ds1620_set_reset (0);
- bc_ds1620_set_clk (0);
-
- return value;
-}
-
-static int cvt_9_to_int (unsigned int val)
-{
- if (val & 0x100)
- val |= 0xfffffe00;
-
- return val;
-}
-
-/* set thermostate thresholds */
-static void ds1620_write_state (struct therm *therm)
-{
- ds1620_out (THERM_WRITE_TL, 9, therm->lo);
- ds1620_out (THERM_WRITE_TH, 9, therm->hi);
- ds1620_out (THERM_START_CONVERT, 0, 0);
-}
-
-static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
- struct therm therm;
-
- sm501_gpio_init ();
-
- /* print temperature */
- if (argc == 1) {
- i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9));
- printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
- return 0;
- }
-
- /* set to default operation */
- if (strncmp (argv[1], "set", 3) == 0) {
- if (strncmp (argv[2], "default", 3) == 0) {
- therm.hi = +88;
- therm.lo = -20;
- therm.hi <<= 1;
- therm.lo <<= 1;
- ds1620_write_state (&therm);
- ds1620_out (THERM_WRITE_CONFIG, 8, CONFIG_SYS_STANDALONE);
- return 0;
- }
- }
-
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
-}
-
-U_BOOT_CMD (temp, 3, 1, cmd_temp,
- "print current temperature",
- "\n" "temp\n" " - print current temperature");
-
-#ifdef CONFIG_BC3450_CAN
-/*
- * Initialise CAN interface
- *
- * return 1 on CAN initialization failure
- * return 0 if no failure
- */
-int can_init (void)
-{
- static int init_done = 0;
- int i;
- struct mpc5xxx_mscan *can1 =
- (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
- struct mpc5xxx_mscan *can2 =
- (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
-
- /* GPIO configuration of the CAN pins is done in BC3450.h */
-
- if (!init_done) {
- /* init CAN 1 */
- can1->canctl1 |= 0x80; /* CAN enable */
- udelay (100);
-
- i = 0;
- can1->canctl0 |= 0x02; /* sleep mode */
- /* wait until sleep mode reached */
- while (!(can1->canctl1 & 0x02)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN1 initialize error, "
- "can not enter sleep mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- i = 0;
- can1->canctl0 = 0x01; /* enter init mode */
- /* wait until init mode reached */
- while (!(can1->canctl1 & 0x01)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN1 initialize error, "
- "can not enter init mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- can1->canctl1 = 0x80;
- can1->canctl1 |= 0x40;
- can1->canbtr0 = 0x0F;
- can1->canbtr1 = 0x7F;
- can1->canidac &= ~(0x30);
- can1->canidar1 = 0x00;
- can1->canidar3 = 0x00;
- can1->canidar5 = 0x00;
- can1->canidar7 = 0x00;
- can1->canidmr0 = 0xFF;
- can1->canidmr1 = 0xFF;
- can1->canidmr2 = 0xFF;
- can1->canidmr3 = 0xFF;
- can1->canidmr4 = 0xFF;
- can1->canidmr5 = 0xFF;
- can1->canidmr6 = 0xFF;
- can1->canidmr7 = 0xFF;
-
- i = 0;
- can1->canctl0 &= ~(0x01); /* leave init mode */
- can1->canctl0 &= ~(0x02);
- /* wait until init and sleep mode left */
- while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN1 initialize error, "
- "can not leave init/sleep mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
-
- /* init CAN 2 */
- can2->canctl1 |= 0x80; /* CAN enable */
- udelay (100);
-
- i = 0;
- can2->canctl0 |= 0x02; /* sleep mode */
- /* wait until sleep mode reached */
- while (!(can2->canctl1 & 0x02)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN2 initialize error, "
- "can not enter sleep mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- i = 0;
- can2->canctl0 = 0x01; /* enter init mode */
- /* wait until init mode reached */
- while (!(can2->canctl1 & 0x01)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN2 initialize error, "
- "can not enter init mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- can2->canctl1 = 0x80;
- can2->canctl1 |= 0x40;
- can2->canbtr0 = 0x0F;
- can2->canbtr1 = 0x7F;
- can2->canidac &= ~(0x30);
- can2->canidar1 = 0x00;
- can2->canidar3 = 0x00;
- can2->canidar5 = 0x00;
- can2->canidar7 = 0x00;
- can2->canidmr0 = 0xFF;
- can2->canidmr1 = 0xFF;
- can2->canidmr2 = 0xFF;
- can2->canidmr3 = 0xFF;
- can2->canidmr4 = 0xFF;
- can2->canidmr5 = 0xFF;
- can2->canidmr6 = 0xFF;
- can2->canidmr7 = 0xFF;
- can2->canctl0 &= ~(0x01); /* leave init mode */
- can2->canctl0 &= ~(0x02);
-
- i = 0;
- /* wait until init mode left */
- while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN2 initialize error, "
- "can not leave init/sleep mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- init_done = 1;
- }
- return 0;
-}
-
-/*
- * Do CAN test
- * by sending message between CAN1 and CAN2
- *
- * return 1 on CAN failure
- * return 0 if no failure
- */
-int do_can (char * const argv[])
-{
- int i;
- struct mpc5xxx_mscan *can1 =
- (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
- struct mpc5xxx_mscan *can2 =
- (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
-
- /* send a message on CAN1 */
- can1->cantbsel = 0x01;
- can1->cantxfg.idr[0] = 0x55;
- can1->cantxfg.idr[1] = 0x00;
- can1->cantxfg.idr[1] &= ~0x8;
- can1->cantxfg.idr[1] &= ~0x10;
- can1->cantxfg.dsr[0] = 0xCC;
- can1->cantxfg.dlr = 1;
- can1->cantxfg.tbpr = 0;
- can1->cantflg = 0x01;
-
- i = 0;
- while ((can1->cantflg & 0x01) == 0) {
- i++;
- if (i == 10) {
- printf ("%s: CAN1 send timeout, "
- "can not send message!\n", __FUNCTION__);
- return 1;
- }
- udelay (1000);
- }
- udelay (1000);
-
- i = 0;
- while (!(can2->canrflg & 0x01)) {
- i++;
- if (i == 10) {
- printf ("%s: CAN2 receive timeout, "
- "no message received!\n", __FUNCTION__);
- return 1;
- }
- udelay (1000);
- }
-
- if (can2->canrxfg.dsr[0] != 0xCC) {
- printf ("%s: CAN2 receive error, "
- "data mismatch!\n", __FUNCTION__);
- return 1;
- }
-
- /* send a message on CAN2 */
- can2->cantbsel = 0x01;
- can2->cantxfg.idr[0] = 0x55;
- can2->cantxfg.idr[1] = 0x00;
- can2->cantxfg.idr[1] &= ~0x8;
- can2->cantxfg.idr[1] &= ~0x10;
- can2->cantxfg.dsr[0] = 0xCC;
- can2->cantxfg.dlr = 1;
- can2->cantxfg.tbpr = 0;
- can2->cantflg = 0x01;
-
- i = 0;
- while ((can2->cantflg & 0x01) == 0) {
- i++;
- if (i == 10) {
- printf ("%s: CAN2 send error, "
- "can not send message!\n", __FUNCTION__);
- return 1;
- }
- udelay (1000);
- }
- udelay (1000);
-
- i = 0;
- while (!(can1->canrflg & 0x01)) {
- i++;
- if (i == 10) {
- printf ("%s: CAN1 receive timeout, "
- "no message received!\n", __FUNCTION__);
- return 1;
- }
- udelay (1000);
- }
-
- if (can1->canrxfg.dsr[0] != 0xCC) {
- printf ("%s: CAN1 receive error 0x%02x\n",
- __FUNCTION__, (can1->canrxfg.dsr[0]));
- return 1;
- }
-
- return 0;
-}
-#endif /* CONFIG_BC3450_CAN */
-
-/*
- * test - BC3450 HW test routines
- */
-int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-#ifdef CONFIG_BC3450_CAN
- int rcode;
-
- can_init ();
-#endif /* CONFIG_BC3450_CAN */
-
- sm501_gpio_init ();
-
- if (argc != 2) {
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
- }
-
- if (strncmp (argv[1], "unit-off", 8) == 0) {
- printf ("waiting 2 seconds...\n");
- udelay (2000000);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
- ~PWR_OFF;
- return 0;
- }
-#ifdef CONFIG_BC3450_CAN
- else if (strncmp (argv[1], "can", 2) == 0) {
- rcode = do_can (argv);
- if (simple_strtoul (argv[2], NULL, 10) == 2) {
- if (rcode == 0)
- printf ("OK\n");
- else
- printf ("Error\n");
- }
- return rcode;
- }
-#endif /* CONFIG_BC3450_CAN */
-
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
-}
-
-U_BOOT_CMD (test, 2, 1, cmd_test, "unit test routines", "\n"
-#ifdef CONFIG_BC3450_CAN
- "test can\n"
- " - connect CAN1 (X8) with CAN2 (X9) for this test\n"
-#endif /* CONFIG_BC3450_CAN */
- "test unit-off\n"
- " - turns off the BC3450 unit\n"
- " WARNING: Unsaved environment variables will be lost!"
-);
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
-/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
-#define SDRAM_CONFIG2 0x8AD70000
-/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
--- /dev/null
+if TARGET_BAV335X
+
+config SYS_BOARD
+ default "bav335x"
+
+config SYS_VENDOR
+ default "birdland"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "bav335x"
+
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 1
+ help
+ The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+ in documentation, etc) available to it. Depending on your specific
+ board you may want something other than UART0 as for example the IDK
+ uses UART3 so enter 4 here.
+
+config BAV_VERSION
+ int "BAV335x Version (1=A, 2=B)"
+ range 1 2
+ help
+ The BAV335x has various version of the board. Rev.A (mostly obsolete)
+ used 10/100 Ethernet PHY while Rev.B uses a Gigabit Ethernet PHY.
+ Overwrite this if you have an older Rev.A and want ethernet support.
+
+endif
--- /dev/null
+BAV335x BOARD
+M: Gilles Gameiro <gilles@gigadevices.com>
+S: Maintained
+F: include/configs/bav335x.h
+F: board/birdland/bav335x/Kconfig
+F: board/birdland/bav335x/Makefile
+F: board/birdland/bav335x/README
+F: board/birdland/bav335x/board.c
+F: board/birdland/bav335x/board.h
+F: board/birdland/bav335x/mux.c
+F: board/birdland/bav335x/u-boot.lds
+F: configs/birdland_bav335a_defconfig
+F: configs/birdland_bav335b_defconfig
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2012-2014, Birdland Audio - http://birdland.com/oem
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
--- /dev/null
+Summary
+=======
+
+This document covers various features of the 'BAV335x' board build.
+For more information about this board, visit http://birdland.com/oem
+
+
+Hardware
+========
+
+The binary produced supports the bav335x Rev.A with 10/100 MB PHY
+and Rev.B (default) with GB ethernet PHY.
+If the BAV335x EEPROM is populated and programmed, the board will
+automatically detect the version and extract proper serial# and
+mac address from the EE.
+
+
+Customization
+=============
+
+The following blocks are required:
+- I2C, to talk with the PMIC and ensure that we do not run afoul of
+ errata 1.0.24.
+
+When removing options as part of customization,
+CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
+needs and to remove no longer relevant options as in some cases we
+define additional text blocks (such as for NAND or DFU strings). Also
+note that all of the SPL options are grouped together, rather than with
+the IP blocks, so both areas will need their choices updated to reflect
+the custom design.
--- /dev/null
+/*
+ * board.c
+ *
+ * Board functions for Birdland Audio BAV335x Network Processor
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN 7
+
+static __maybe_unused struct ctrl_dev *cdev =
+ (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct board_eeconfig *header)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
+ return -ENODEV;
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+ sizeof(struct board_eeconfig)))
+ return -EIO;
+
+ if (header->magic != BOARD_MAGIC) {
+ /* read the i2c eeprom again using only a 1 byte address */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+ sizeof(struct board_eeconfig)))
+ return -EIO;
+
+ if (header->magic != BOARD_MAGIC)
+ return -EINVAL;
+ }
+ return 0;
+}
+
+
+
+
+enum board_type get_board_type(bool debug)
+{
+ int ecode;
+ struct board_eeconfig header;
+
+ ecode = read_eeprom(&header);
+ if (ecode == 0) {
+ if (header.version[1] == 'A') {
+ if (debug)
+ puts("=== Detected Board model BAV335x Rev.A");
+ return BAV335A;
+ } else if (header.version[1] == 'B') {
+ if (debug)
+ puts("=== Detected Board model BAV335x Rev.B");
+ return BAV335B;
+ } else if (debug) {
+ puts("### Un-known board model in serial-EE\n");
+ }
+ } else if (debug) {
+ switch (ecode) {
+ case -ENODEV:
+ puts("### Board doesn't have a serial-EE\n");
+ break;
+ case -EINVAL:
+ puts("### Board serial-EE signature is incorrect.\n");
+ break;
+ default:
+ puts("### IO Error reading serial-EE.\n");
+ break;
+ }
+ }
+
+#if (CONFIG_BAV_VERSION == 1)
+ if (debug)
+ puts("### Selecting BAV335A as per config\n");
+ return BAV335A;
+#elif (CONFIG_BAV_VERSION == 2)
+ if (debug)
+ puts("### Selecting BAV335B as per config\n");
+ return BAV335B;
+#endif
+#if (NOT_DEFINED == 2)
+#error "SHOULD NEVER DISPLAY THIS"
+#endif
+
+ if (debug)
+ puts("### Defaulting to model BAV335x Rev.B\n");
+ return BAV335B;
+}
+
+
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static const struct ddr_data ddr3_bav335x_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+
+static struct emif_regs ddr3_bav335x_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ 266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+ 303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_bone_black = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ /* debug print detect status */
+ (void)get_board_type(true);
+
+ /* Get the frequency */
+ /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
+ dpll_mpu_opp100.m = MPUPLL_M_1000;
+
+ if (i2c_probe(TPS65217_CHIP_PM))
+ return;
+
+ /* Set the USB Current Limit */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+ TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
+ TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+ puts("! tps65217_reg_write: could not set USB limit\n");
+
+ /* Set the Core Voltage (DCDC3) to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("! tps65217_reg_write: could not set Core Voltage\n");
+ return;
+ }
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set the MPU Voltage (DCDC2) */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2,
+ TPS65217_DCDC_VOLT_SEL_1325MV)) {
+ puts("! tps65217_reg_write: could not set MPU Voltage\n");
+ return;
+ }
+
+ /*
+ * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
+ * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
+ */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
+ puts("! tps65217_reg_write: could not set LDO3\n");
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
+ TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
+ puts("! tps65217_reg_write: could not set LDO4\n");
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ return &dpll_ddr_bone_black;
+}
+
+void set_uart_mux_conf(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ enable_uart0_pin_mux();
+#elif CONFIG_CONS_INDEX == 2
+ enable_uart1_pin_mux();
+#elif CONFIG_CONS_INDEX == 3
+ enable_uart2_pin_mux();
+#elif CONFIG_CONS_INDEX == 4
+ enable_uart3_pin_mux();
+#elif CONFIG_CONS_INDEX == 5
+ enable_uart4_pin_mux();
+#elif CONFIG_CONS_INDEX == 6
+ enable_uart5_pin_mux();
+#endif
+}
+
+void set_mux_conf_regs(void)
+{
+ enum board_type board;
+
+ board = get_board_type(false);
+ enable_board_pin_mux(board);
+}
+
+const struct ctrl_ioregs ioregs_bonelt = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+
+void sdram_init(void)
+{
+ config_ddr(400, &ioregs_bonelt,
+ &ddr3_bav335x_data,
+ &ddr3_bav335x_cmd_ctrl_data,
+ &ddr3_bav335x_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+ gpmc_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "BAV335xB");
+ setenv("board_rev", "B"); /* Fix me, but why bother.. */
+#endif
+ return 0;
+}
+#endif
+
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif
+
+
+/*
+ * This function will:
+ * Perform fixups to the PHY present on certain boards. We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+ defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+ int ecode, rv, n;
+ uint8_t mac_addr[6];
+ struct board_eeconfig header;
+ __maybe_unused enum board_type board;
+
+ /* Default manufacturing address; used when no EE or invalid */
+ n = 0;
+ mac_addr[0] = 0;
+ mac_addr[1] = 0x20;
+ mac_addr[2] = 0x18;
+ mac_addr[3] = 0x1C;
+ mac_addr[4] = 0x00;
+ mac_addr[5] = 0x01;
+
+ ecode = read_eeprom(&header);
+ /* if we have a valid EE, get mac address from there */
+ if ((ecode == 0) &&
+ is_valid_ether_addr((const u8 *)&header.mac_addr[0][0])) {
+ memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
+ }
+
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+ board = get_board_type(false);
+
+ /* Rev.A uses 10/100 PHY in mii mode */
+ if (board == BAV335A) {
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
+ }
+ /* Rev.B (default) uses GB PHY in rmii mode */
+ else {
+ writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
+ = PHY_INTERFACE_MODE_RGMII;
+ }
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+
+#endif
+
+ return n;
+}
+#endif
--- /dev/null
+/*
+ * board.c
+ *
+ * Board functions for Birdland Audio BAV335x Network Processor
+ *
+ * Copyright (c) 2012-2014, Birdland Audio - http://birdland.com/oem
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/* Serial MagicE: AA 55 BA BE */
+#define BOARD_MAGIC 0xBEBA55AA
+enum board_type {UNKNOWN, BAV335A, BAV335B};
+
+
+/*
+ * The BAV335x may use a built-in read-only serial EEProm.
+ * The Evaluation board, disables the write-protect so the Serial-EE
+ * Can be programmed during manufacturing to store fields such as
+ * a board serial number, ethernet mac address and other user fields.
+ * Additionally, the Serial-EE can store the specific version of the
+ * board it runs on, and overwrite the defaults in _defconfig
+ */
+#define HDR_NO_OF_MAC_ADDR 3
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+
+struct board_eeconfig {
+ unsigned int magic;
+ char name[HDR_NAME_LEN]; /* BAV3354 */
+ char version[4]; /* 0B20 - Rev.B2 */
+ char serial[12];
+ char config[32];
+ char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+enum board_type get_board_type(bool verbose_debug_output);
+
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(enum board_type board);
+
+#endif
--- /dev/null
+/*
+ * mux.c
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+ {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
+ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+ configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR 0x35
+#define CFG_REG 0x10
+
+
+void enable_board_pin_mux(enum board_type board)
+{
+ configure_module_pin_mux(i2c1_pin_mux);
+ if (board == BAV335A)
+ configure_module_pin_mux(mii1_pin_mux); /* MII Mode: 10/100MB */
+ else
+ configure_module_pin_mux(rgmii1_pin_mux); /* RGMII Mode: GB */
+
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+}
--- /dev/null
+/*
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ *(.vectors)
+ CPUDIR/start.o (.text*)
+ board/birdland/bav335x/built-in.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ .hash : { *(.hash*) }
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .gnu.hash : { *(.gnu.hash) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+}
obj-$(CONFIG_P5040DS) += p_corenet/
obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o
+
+ifdef CONFIG_SECURE_BOOT
+obj-y += fsl_validate.o
+obj-$(CONFIG_CMD_ESBC_VALIDATE) += cmd_esbc_validate.o
+endif
+
endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fsl_validate.h>
+
+static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ return fsl_secboot_validate(cmdtp, flag, argc, argv);
+}
+
+/***************************************************/
+static char esbc_validate_help_text[] =
+ "esbc_validate hdr_addr <hash_val> - Validates signature using\n"
+ " RSA verification\n"
+ " $hdr_addr Address of header of the image\n"
+ " to be validated.\n"
+ " $hash_val -Optional\n"
+ " It provides Hash of public/srk key to be\n"
+ " used to verify signature.\n";
+
+U_BOOT_CMD(
+ esbc_validate, 3, 0, do_esbc_validate,
+ "Validates signature on a given image using RSA verification",
+ esbc_validate_help_text
+);
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_validate.h>
+#include <fsl_secboot_err.h>
+#include <fsl_sfp.h>
+#include <fsl_sec.h>
+#include <command.h>
+#include <malloc.h>
+#include <dm/uclass.h>
+#include <u-boot/rsa-mod-exp.h>
+#include <hash.h>
+#include <fsl_secboot_err.h>
+#ifndef CONFIG_MPC85xx
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#define SHA256_BITS 256
+#define SHA256_BYTES (256/8)
+#define SHA256_NIBBLES (256/4)
+#define NUM_HEX_CHARS (sizeof(ulong) * 2)
+
+/* This array contains DER value for SHA-256 */
+static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
+ 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00,
+ 0x04, 0x20
+ };
+
+static u8 hash_val[SHA256_BYTES];
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+
+void branch_to_self(void) __attribute__ ((noreturn));
+
+/*
+ * This function will put core in infinite loop.
+ * This will be called when the ESBC can not proceed further due
+ * to some unknown errors.
+ */
+void branch_to_self(void)
+{
+ printf("Core is in infinite loop due to errors.\n");
+self:
+ goto self;
+}
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+static u32 check_ie(struct fsl_secboot_img_priv *img)
+{
+ if (img->hdr.ie_flag)
+ return 1;
+
+ return 0;
+}
+
+/* This function returns the CSF Header Address of uboot
+ * For MPC85xx based platforms, the LAW mapping for NOR
+ * flash changes in uboot code. Hence the offset needs
+ * to be calculated and added to the new NOR flash base
+ * address
+ */
+#if defined(CONFIG_MPC85xx)
+int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
+ u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
+ ulong flash_addr, addr;
+ int found = 0;
+ int i = 0;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ flash_addr = flash_info[i].start[0];
+ addr = flash_info[i].start[0] + csf_flash_offset;
+ if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
+ debug("Barker found on addr %lx\n", addr);
+ found = 1;
+ break;
+ }
+ }
+
+ if (!found)
+ return -1;
+
+ *csf_addr = addr;
+ *flash_base_addr = flash_addr;
+
+ return 0;
+}
+#else
+/* For platforms like LS1020, correct flash address is present in
+ * the header. So the function reqturns flash base address as 0
+ */
+int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
+
+ if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN))
+ return -1;
+
+ *csf_addr = csf_hdr_addr;
+ *flash_base_addr = 0;
+ return 0;
+}
+#endif
+
+static int get_ie_info_addr(ulong *ie_addr)
+{
+ struct fsl_secboot_img_hdr *hdr;
+ struct fsl_secboot_sg_table *sg_tbl;
+ ulong flash_base_addr, csf_addr;
+
+ if (get_csf_base_addr(&csf_addr, &flash_base_addr))
+ return -1;
+
+ hdr = (struct fsl_secboot_img_hdr *)csf_addr;
+
+ /* For SoC's with Trust Architecture v1 with corenet bus
+ * the sg table field in CSF header has absolute address
+ * for sg table in memory. In other Trust Architecture,
+ * this field specifies the offset of sg table from the
+ * base address of CSF Header
+ */
+#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
+ sg_tbl = (struct fsl_secboot_sg_table *)
+ (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ flash_base_addr);
+#else
+ sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
+ (ulong)hdr->psgtable);
+#endif
+
+ /* IE Key Table is the first entry in the SG Table */
+#if defined(CONFIG_MPC85xx)
+ *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ flash_base_addr;
+#else
+ *ie_addr = sg_tbl->src_addr;
+#endif
+
+ debug("IE Table address is %lx\n", *ie_addr);
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_KEY_REVOCATION
+/* This function checks srk_table_flag in header and set/reset srk_flag.*/
+static u32 check_srk(struct fsl_secboot_img_priv *img)
+{
+ if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
+ return 1;
+
+ return 0;
+}
+
+/* This function returns ospr's key_revoc values.*/
+static u32 get_key_revoc(void)
+{
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
+ OSPR_KEY_REVOC_SHIFT;
+}
+
+/* This function checks if selected key is revoked or not.*/
+static u32 is_key_revoked(u32 keynum, u32 rev_flag)
+{
+ if (keynum == UNREVOCABLE_KEY)
+ return 0;
+
+ if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag)
+ return 1;
+
+ return 0;
+}
+
+/* It validates srk_table key lengths.*/
+static u32 validate_srk_tbl(struct srk_table *tbl, u32 num_entries)
+{
+ int i = 0;
+ for (i = 0; i < num_entries; i++) {
+ if (!((tbl[i].key_len == 2 * KEY_SIZE_BYTES/4) ||
+ (tbl[i].key_len == 2 * KEY_SIZE_BYTES/2) ||
+ (tbl[i].key_len == 2 * KEY_SIZE_BYTES)))
+ return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN;
+ }
+ return 0;
+}
+#endif
+
+/* This function return length of public key.*/
+static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
+{
+ return img->key_len;
+}
+
+/*
+ * Handles the ESBC uboot client header verification failure.
+ * This function handles all the errors which might occur in the
+ * parsing and checking of ESBC uboot client header. It will also
+ * set the error bits in the SEC_MON.
+ */
+static void fsl_secboot_header_verification_failure(void)
+{
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+
+ /* 29th bit of OSPR is ITS */
+ u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
+
+ /*
+ * Read the SEC_MON status register
+ * Read SSM_ST field
+ */
+ sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+ if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
+ if (its == 1)
+ change_sec_mon_state(HPSR_SSM_ST_TRUST,
+ HPSR_SSM_ST_SOFT_FAIL);
+ else
+ change_sec_mon_state(HPSR_SSM_ST_TRUST,
+ HPSR_SSM_ST_NON_SECURE);
+ }
+
+ printf("Generating reset request\n");
+ do_reset(NULL, 0, 0, NULL);
+}
+
+/*
+ * Handles the ESBC uboot client image verification failure.
+ * This function handles all the errors which might occur in the
+ * public key hash comparison and signature verification of
+ * ESBC uboot client image. It will also
+ * set the error bits in the SEC_MON.
+ */
+static void fsl_secboot_image_verification_failure(void)
+{
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+
+ u32 its = sfp_in32(&sfp_regs->ospr) & ITS_MASK >> ITS_BIT;
+
+ /*
+ * Read the SEC_MON status register
+ * Read SSM_ST field
+ */
+ sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+ if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
+ if (its == 1) {
+ change_sec_mon_state(HPSR_SSM_ST_TRUST,
+ HPSR_SSM_ST_SOFT_FAIL);
+
+ printf("Generating reset request\n");
+ do_reset(NULL, 0, 0, NULL);
+ } else {
+ change_sec_mon_state(HPSR_SSM_ST_TRUST,
+ HPSR_SSM_ST_NON_SECURE);
+ }
+ }
+}
+
+static void fsl_secboot_bootscript_parse_failure(void)
+{
+ fsl_secboot_header_verification_failure();
+}
+
+/*
+ * Handles the errors in esbc boot.
+ * This function handles all the errors which might occur in the
+ * esbc boot phase. It will call the appropriate api to log the
+ * errors and set the error bits in the SEC_MON.
+ */
+void fsl_secboot_handle_error(int error)
+{
+ const struct fsl_secboot_errcode *e;
+
+ for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX;
+ e++) {
+ if (e->errcode == error)
+ printf("ERROR :: %x :: %s\n", error, e->name);
+ }
+
+ switch (error) {
+ case ERROR_ESBC_CLIENT_HEADER_BARKER:
+ case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_LEN:
+ case ERROR_ESBC_CLIENT_HEADER_SIG_LEN:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2:
+ case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
+ case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
+ case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+#ifdef CONFIG_KEY_REVOCATION
+ case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM:
+ case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN:
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ /*@fallthrough@*/
+ case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM:
+ case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN:
+ case ERROR_IE_TABLE_NOT_FOUND:
+#endif
+ fsl_secboot_header_verification_failure();
+ break;
+ case ERROR_ESBC_SEC_RESET:
+ case ERROR_ESBC_SEC_DEQ:
+ case ERROR_ESBC_SEC_ENQ:
+ case ERROR_ESBC_SEC_DEQ_TO:
+ case ERROR_ESBC_SEC_JOBQ_STATUS:
+ case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY:
+ case ERROR_ESBC_CLIENT_HASH_COMPARE_EM:
+ fsl_secboot_image_verification_failure();
+ break;
+ case ERROR_ESBC_MISSING_BOOTM:
+ fsl_secboot_bootscript_parse_failure();
+ break;
+ case ERROR_ESBC_WRONG_CMD:
+ default:
+ branch_to_self();
+ break;
+ }
+}
+
+static void fsl_secblk_handle_error(int error)
+{
+ switch (error) {
+ case ERROR_ESBC_SEC_ENQ:
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ);
+ break;
+ case ERROR_ESBC_SEC_DEQ:
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ);
+ break;
+ case ERROR_ESBC_SEC_DEQ_TO:
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO);
+ break;
+ default:
+ printf("Job Queue Output status %x\n", error);
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS);
+ break;
+ }
+}
+
+/*
+ * Calculate hash of key obtained via offset present in ESBC uboot
+ * client hdr. This function calculates the hash of key which is obtained
+ * through offset present in ESBC uboot client header.
+ */
+static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
+{
+ struct hash_algo *algo;
+ void *ctx;
+ int i, srk = 0;
+ int ret = 0;
+ const char *algo_name = "sha256";
+
+ /* Calculate hash of the esbc key */
+ ret = hash_progressive_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ ret = algo->hash_init(algo, &ctx);
+ if (ret)
+ return ret;
+
+ /* Update hash for ESBC key */
+#ifdef CONFIG_KEY_REVOCATION
+ if (check_srk(img)) {
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
+ srk = 1;
+ }
+#endif
+ if (!srk)
+ ret = algo->hash_update(algo, ctx,
+ img->img_key, img->key_len, 1);
+ if (ret)
+ return ret;
+
+ /* Copy hash at destination buffer */
+ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < SHA256_BYTES; i++)
+ img->img_key_hash[i] = hash_val[i];
+
+ return 0;
+}
+
+/*
+ * Calculate hash of ESBC hdr and ESBC. This function calculates the
+ * single hash of ESBC header and ESBC image. If SG flag is on, all
+ * SG entries are also hashed alongwith the complete SG table.
+ */
+static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
+{
+ struct hash_algo *algo;
+ void *ctx;
+ int ret = 0;
+ int key_hash = 0;
+ const char *algo_name = "sha256";
+
+ /* Calculate the hash of the ESBC */
+ ret = hash_progressive_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ ret = algo->hash_init(algo, &ctx);
+ /* Copy hash at destination buffer */
+ if (ret)
+ return ret;
+
+ /* Update hash for CSF Header */
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0);
+ if (ret)
+ return ret;
+
+ /* Update the hash with that of srk table if srk flag is 1
+ * If IE Table is selected, key is not added in the hash
+ * If neither srk table nor IE key table available, add key
+ * from header in the hash calculation
+ */
+#ifdef CONFIG_KEY_REVOCATION
+ if (check_srk(img)) {
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0);
+ key_hash = 1;
+ }
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (!key_hash && check_ie(img))
+ key_hash = 1;
+#endif
+ if (!key_hash)
+ ret = algo->hash_update(algo, ctx,
+ img->img_key, img->hdr.key_len, 0);
+ if (ret)
+ return ret;
+
+ /* Update hash for actual Image */
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)img->hdr.pimg, img->hdr.img_size, 1);
+ if (ret)
+ return ret;
+
+ /* Copy hash at destination buffer */
+ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the
+ * pointers for padding, DER value and hash. And finally, constructs EM'
+ * which includes hash of complete CSF header and ESBC image. If SG flag
+ * is on, hash of SG table and entries is also included.
+ */
+static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img)
+{
+ /*
+ * RSA PKCSv1.5 encoding format for encoded message is below
+ * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash
+ * PS is Padding String
+ * DER is DER value for SHA-256
+ * Hash is SHA-256 hash
+ * *********************************************************
+ * representative points to first byte of EM initially and is
+ * filled with 0x0
+ * representative is incremented by 1 and second byte is filled
+ * with 0x1
+ * padding points to third byte of EM
+ * digest points to full length of EM - 32 bytes
+ * hash_id (DER value) points to 19 bytes before pDigest
+ * separator is one byte which separates padding and DER
+ */
+
+ size_t len;
+ u8 *representative;
+ u8 *padding, *digest;
+ u8 *hash_id, *separator;
+ int i;
+
+ len = (get_key_len(img) / 2) - 1;
+ representative = img->img_encoded_hash_second;
+ representative[0] = 0;
+ representative[1] = 1; /* block type 1 */
+
+ padding = &representative[2];
+ digest = &representative[1] + len - 32;
+ hash_id = digest - sizeof(hash_identifier);
+ separator = hash_id - 1;
+
+ /* fill padding area pointed by padding with 0xff */
+ memset(padding, 0xff, separator - padding);
+
+ /* fill byte pointed by separator */
+ *separator = 0;
+
+ /* fill SHA-256 DER value pointed by HashId */
+ memcpy(hash_id, hash_identifier, sizeof(hash_identifier));
+
+ /* fill hash pointed by Digest */
+ for (i = 0; i < SHA256_BYTES; i++)
+ digest[i] = hash_val[i];
+}
+
+/*
+ * Reads and validates the ESBC client header.
+ * This function reads key and signature from the ESBC client header.
+ * If Scatter/Gather flag is on, lengths and offsets of images
+ * present as SG entries are also read. This function also checks
+ * whether the header is valid or not.
+ */
+static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
+{
+ char buf[20];
+ struct fsl_secboot_img_hdr *hdr = &img->hdr;
+ void *esbc = (u8 *)img->ehdrloc;
+ u8 *k, *s;
+#ifdef CONFIG_KEY_REVOCATION
+ u32 ret;
+ u32 key_num, key_revoc_flag, size;
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ struct ie_key_info *ie_info;
+ u32 ie_num, ie_revoc_flag, ie_key_len;
+#endif
+ int key_found = 0;
+
+ /* check barker code */
+ if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
+ return ERROR_ESBC_CLIENT_HEADER_BARKER;
+
+ sprintf(buf, "%p", hdr->pimg);
+ setenv("img_addr", buf);
+
+ if (!hdr->img_size)
+ return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
+
+ /* Key checking*/
+#ifdef CONFIG_KEY_REVOCATION
+ if (check_srk(img)) {
+ if ((hdr->len_kr.num_srk == 0) ||
+ (hdr->len_kr.num_srk > MAX_KEY_ENTRIES))
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY;
+
+ key_num = hdr->len_kr.srk_sel;
+ if (key_num == 0 || key_num > hdr->len_kr.num_srk)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM;
+
+ /* Get revoc key from sfp */
+ key_revoc_flag = get_key_revoc();
+ ret = is_key_revoked(key_num, key_revoc_flag);
+ if (ret)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED;
+
+ size = hdr->len_kr.num_srk * sizeof(struct srk_table);
+
+ memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size);
+
+ ret = validate_srk_tbl(img->srk_tbl, hdr->len_kr.num_srk);
+
+ if (ret != 0)
+ return ret;
+
+ img->key_len = img->srk_tbl[key_num - 1].key_len;
+
+ memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey),
+ img->key_len);
+
+ key_found = 1;
+ }
+#endif
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (!key_found && check_ie(img)) {
+ if (get_ie_info_addr(&img->ie_addr))
+ return ERROR_IE_TABLE_NOT_FOUND;
+ ie_info = (struct ie_key_info *)img->ie_addr;
+ if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
+
+ ie_num = hdr->ie_key_sel;
+ if (ie_num == 0 || ie_num > ie_info->num_keys)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM;
+
+ ie_revoc_flag = ie_info->key_revok;
+ if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag)
+ return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED;
+
+ ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len;
+
+ if (!((ie_key_len == 2 * KEY_SIZE_BYTES / 4) ||
+ (ie_key_len == 2 * KEY_SIZE_BYTES / 2) ||
+ (ie_key_len == 2 * KEY_SIZE_BYTES)))
+ return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN;
+
+ memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey),
+ ie_key_len);
+
+ img->key_len = ie_key_len;
+ key_found = 1;
+ }
+#endif
+
+ if (key_found == 0) {
+ /* check key length */
+ if (!((hdr->key_len == 2 * KEY_SIZE_BYTES / 4) ||
+ (hdr->key_len == 2 * KEY_SIZE_BYTES / 2) ||
+ (hdr->key_len == 2 * KEY_SIZE_BYTES)))
+ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN;
+
+ memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len);
+
+ img->key_len = hdr->key_len;
+
+ key_found = 1;
+ }
+
+ /* check signaure */
+ if (get_key_len(img) == 2 * hdr->sign_len) {
+ /* check signature length */
+ if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) ||
+ (hdr->sign_len == KEY_SIZE_BYTES / 2) ||
+ (hdr->sign_len == KEY_SIZE_BYTES)))
+ return ERROR_ESBC_CLIENT_HEADER_SIG_LEN;
+ } else {
+ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN;
+ }
+
+ memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len);
+
+ /* No SG support */
+ if (hdr->sg_flag)
+ return ERROR_ESBC_CLIENT_HEADER_SG;
+
+ /* modulus most significant bit should be set */
+ k = (u8 *)&img->img_key;
+
+ if ((k[0] & 0x80) == 0)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1;
+
+ /* modulus value should be odd */
+ if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2;
+
+ /* Check signature value < modulus value */
+ s = (u8 *)&img->img_sign;
+
+ if (!(memcmp(s, k, hdr->sign_len) < 0))
+ return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD;
+
+ return ESBC_VALID_HDR;
+}
+
+static inline int str2longbe(const char *p, ulong *num)
+{
+ char *endptr;
+ ulong tmp;
+
+ if (!p) {
+ return 0;
+ } else {
+ tmp = simple_strtoul(p, &endptr, 16);
+ if (sizeof(ulong) == 4)
+ *num = cpu_to_be32(tmp);
+ else
+ *num = cpu_to_be64(tmp);
+ }
+
+ return *p != '\0' && *endptr == '\0';
+}
+
+int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ ulong hash[SHA256_BYTES/sizeof(ulong)];
+ char hash_str[NUM_HEX_CHARS + 1];
+ ulong addr = simple_strtoul(argv[1], NULL, 16);
+ struct fsl_secboot_img_priv *img;
+ struct fsl_secboot_img_hdr *hdr;
+ void *esbc;
+ int ret, i, hash_cmd = 0;
+ u32 srk_hash[8];
+ uint32_t key_len;
+ struct key_prop prop;
+#if !defined(USE_HOSTCC)
+ struct udevice *mod_exp_dev;
+#endif
+
+ if (argc == 3) {
+ char *cp = argv[2];
+ int i = 0;
+
+ if (*cp == '0' && *(cp + 1) == 'x')
+ cp += 2;
+
+ /* The input string expected is in hex, where
+ * each 4 bits would be represented by a hex
+ * sha256 hash is 256 bits long, which would mean
+ * num of characters = 256 / 4
+ */
+ if (strlen(cp) != SHA256_NIBBLES) {
+ printf("%s is not a 256 bits hex string as expected\n",
+ argv[2]);
+ return -1;
+ }
+
+ for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) {
+ strncpy(hash_str, cp + (i * NUM_HEX_CHARS),
+ NUM_HEX_CHARS);
+ hash_str[NUM_HEX_CHARS] = '\0';
+ if (!str2longbe(hash_str, &hash[i])) {
+ printf("%s is not a 256 bits hex string ",
+ argv[2]);
+ return -1;
+ }
+ }
+
+ hash_cmd = 1;
+ }
+
+ img = malloc(sizeof(struct fsl_secboot_img_priv));
+
+ if (!img)
+ return -1;
+
+ memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+
+ hdr = &img->hdr;
+ img->ehdrloc = addr;
+ esbc = (u8 *)img->ehdrloc;
+
+ memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
+
+ /* read and validate esbc header */
+ ret = read_validate_esbc_client_header(img);
+
+ if (ret != ESBC_VALID_HDR) {
+ fsl_secboot_handle_error(ret);
+ goto exit;
+ }
+
+ /* SRKH present in SFP */
+ for (i = 0; i < NUM_SRKH_REGS; i++)
+ srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]);
+
+ /*
+ * Calculate hash of key obtained via offset present in
+ * ESBC uboot client hdr
+ */
+ ret = calc_img_key_hash(img);
+ if (ret) {
+ fsl_secblk_handle_error(ret);
+ goto exit;
+ }
+
+ /* Compare hash obtained above with SRK hash present in SFP */
+ if (hash_cmd)
+ ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES);
+ else
+ ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES);
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (!hash_cmd && check_ie(img))
+ ret = 0;
+#endif
+
+ if (ret != 0) {
+ fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY);
+ goto exit;
+ }
+
+ ret = calc_esbchdr_esbc_hash(img);
+ if (ret) {
+ fsl_secblk_handle_error(ret);
+ goto exit;
+ }
+
+ /* Construct encoded hash EM' wrt PKCSv1.5 */
+ construct_img_encoded_hash_second(img);
+
+ /* Fill prop structure for public key */
+ memset(&prop, 0, sizeof(struct key_prop));
+ key_len = get_key_len(img) / 2;
+ prop.modulus = img->img_key;
+ prop.public_exponent = img->img_key + key_len;
+ prop.num_bits = key_len * 8;
+ prop.exp_len = key_len;
+
+ ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
+ if (ret) {
+ printf("RSA: Can't find Modular Exp implementation\n");
+ return -EINVAL;
+ }
+
+ ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len,
+ &prop, img->img_encoded_hash);
+ if (ret) {
+ fsl_secblk_handle_error(ret);
+ goto exit;
+ }
+
+ /*
+ * compare the encoded messages EM' and EM wrt RSA PKCSv1.5
+ * memcmp returns zero on success
+ * memcmp returns non-zero on failure
+ */
+ ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash,
+ img->hdr.sign_len);
+
+ if (ret) {
+ fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_EM);
+ goto exit;
+ }
+
+ printf("esbc_validate command successful\n");
+
+exit:
+ return 0;
+}
DECLARE_GLOBAL_DATA_PTR;
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "RAW timing DDR";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
#ifndef __DDR_H__
#define __DDR_H__
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 2,
- .rank_density = 2147483648u,
- .capacity = 4294967296u,
- .primary_sdram_width = 64,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2, /* ECC */
- .burst_lengths_bitmask = 0x0c,
- .tckmin_x_ps = 1071,
- .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 6000,
- .trp_ps = 13125,
- .tras_ps = 34000,
- .trc_ps = 48125,
- .trfc_ps = 260000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 35000,
-};
-
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
+++ /dev/null
-if TARGET_GALAXY5200
-
-config SYS_BOARD
- default "galaxy5200"
-
-config SYS_CONFIG_NAME
- default "galaxy5200"
-
-endif
+++ /dev/null
-GALAXY5200 BOARD
-#M: Eric Millbrandt <emillbrandt@dekaresearch.com>
-S: Orphan (since 2014-06)
-F: board/galaxy5200/
-F: include/configs/galaxy5200.h
-F: configs/galaxy5200_defconfig
-F: configs/galaxy5200_LOWBOOT_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := galaxy5200.o
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messtechnik GmbH
- *
- * (C) Copyright 2009
- * Eric Millbrandt, DEKA Research and Development Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/io.h>
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
- volatile struct mpc5xxx_cdm *cdm =
- (struct mpc5xxx_cdm *)MPC5XXX_CDM;
- volatile struct mpc5xxx_sdram *sdram =
- (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
-
- /* precharge all banks */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-#ifdef SDRAM_DDR
- /* set mode register: extended mode */
- out_be32 (&sdram->mode, (SDRAM_EMODE));
-
- /* set mode register: reset DLL */
- out_be32 (&sdram->mode, (SDRAM_MODE | 0x04000000));
-#endif
-
- /* precharge all banks */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
- /* auto refresh */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
-
- /* set mode register */
- out_be32 (&sdram->mode, (SDRAM_MODE));
-
- /* normal operation */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | hi_addr_bit));
-
- /* set CDM clock enable register, set MPC5200B SDRAM bus */
- /* to reduced driver strength */
- out_be32 (&cdm->clock_enable, (0x00CFFFFF));
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make
- * real use of CONFIG_SYS_SDRAM_BASE. The code does not
- * work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
- volatile struct mpc5xxx_mmap_ctl *mm =
- (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
- volatile struct mpc5xxx_sdram *sdram =
- (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
- ulong dramsize = 0;
- ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- /* 256MB at 0x0 */
- out_be32 (&mm->sdram0, 0x0000001b);
- /* disabled */
- out_be32 (&mm->sdram1, 0x10000000);
-
- /* setup config registers */
- out_be32 (&sdram->config1, SDRAM_CONFIG1);
- out_be32 (&sdram->config2, SDRAM_CONFIG2);
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
- sdram_start(1);
- test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else
- dramsize = test2;
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20))
- dramsize = 0;
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- out_be32 (&mm->sdram0,
- (0x13 + __builtin_ffs(dramsize >> 20) - 1));
- } else {
- /* disabled */
- out_be32 (&mm->sdram0, 0);
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = in_be32(&mm->sdram0) & 0xFF;
- if (dramsize >= 0x13)
- dramsize = (1 << (dramsize - 0x13)) << 20;
- else
- dramsize = 0;
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = in_be32(&mm->sdram1) & 0xFF;
- if (dramsize2 >= 0x13)
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- else
- dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize + dramsize2;
-}
-
-int checkboard(void)
-{
- puts("Board: galaxy5200\n");
- return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
- debug ("init_ide_reset\n");
-
- /* Configure TIMER_5 as GPIO output for ATA reset */
- /* Deassert reset */
- gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
-}
-
-void ide_set_reset (int idereset)
-{
- volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
- debug ("ide_reset(%d)\n", idereset);
-
- /* Configure TIMER_5 as GPIO output for ATA reset */
- if (idereset) {
- gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 | MPC5XXX_GPT_TMS_GPIO;
-
- /* Make a delay. MPC5200 spec says 25 usec min */
- udelay(50);
- } else {
- gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
- udelay(50);
- }
-}
-#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
+++ /dev/null
-if TARGET_JSE
-
-config SYS_BOARD
- default "jse"
-
-config SYS_CONFIG_NAME
- default "JSE"
-
-endif
+++ /dev/null
-JSE BOARD
-M: Stephen Williams <steve@icarus.com>
-S: Maintained
-F: board/jse/
-F: include/configs/JSE.h
-F: configs/JSE_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright 2004 Picture Elements, Inc.
-# Stephen Williams <steve@icarus.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = jse.o sdram.o flash.o host_bridge.o
-obj-y += init.o
+++ /dev/null
-JSE Configuration Details
-
-Memory Bank 0 -- Flash chip
----------------------------
-
-0xfff00000 - 0xffffffff
-
-The flash chip is really only 512Kbytes, but the high address bit of
-the 1Meg region is ignored, so the flash is replicated through the
-region. Thus, this is consistent with a flash base address 0xfff80000.
-
-The placement at the end is to be consistent with reset behavior,
-where the processor itself initially uses this bus to load the branch
-vector and start running.
-
-On-Chip Memory
---------------
-
-0xf4000000 - 0xf4000fff
-
-The 405GPr includes a 4K on-chip memory that can be placed however
-software chooses. I choose to place the memory at this address, to
-keep it out of the cachable areas.
-
-
-Memory Bank 1 -- SystemACE Controller
--------------------------------------
-
-0xf0000000 - 0xf00fffff
-
-The SystemACE chip is along on peripheral bank CS#1. We don't need
-much space, but 1Meg is the smallest we can configure the chip to
-allocate. We need it far away from the flash region, because this
-region is set to be non-cached.
-
-
-Internal Peripherals
---------------------
-
-0xef600300 - 0xef6008ff
-
-These are scattered various peripherals internal to the PPC405GPr
-chip.
-
-SDRAM
------
-
-0x00000000 - 0x07ffffff (128 MBytes)
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-#if CONFIG_SYS_MAX_FLASH_BANKS != 1
-#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1"
-#endif
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
-
- /* Init: no FLASHes known */
- flash_info[0].flash_id = FLASH_UNKNOWN;
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- /* Only one bank */
- /* Setup offsets */
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM,
- FLASH_BASE0_PRELIM + monitor_flash_len - 1,
- &flash_info[0]);
- flash_info[0].size = size_b0;
-
- return size_b0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-/*
- * This implementation assumes that the flash chips are uniform sector
- * devices. This is true for all likely JSE devices.
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- unsigned idx;
- unsigned long sector_size = info->size / info->sector_count;
-
- for (idx = 0; idx < info->sector_count; idx += 1) {
- info->start[idx] = base + (idx * sector_size);
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf ("FUJITSU ");
- break;
- case FLASH_MAN_SST:
- printf ("SST ");
- break;
- case FLASH_MAN_STM:
- printf ("ST Micro ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- /* (Reduced table of only parts expected in JSE boards.) */
- switch (info->flash_id) {
- case FLASH_MAN_AMD | FLASH_AM040:
- printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_MAN_STM | FLASH_AM040:
- printf ("MM29W040W (512 Kbit, uniform sector size)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *) info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ", info->protect[i] ? "RO " : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
-
- value = addr2[0];
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (FLASH_WORD_SIZE)STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- printf("Unknown flash manufacturer code: 0x%x\n", value);
- return (0); /* no or unknown flash */
- }
-
- value = addr2[1]; /* device ID */
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* Calculate the sector offsets (Use JSE Optimized code). */
- flash_get_offsets(base, info);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (FLASH_WORD_SIZE *) info->start[0];
- *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7 (flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr =
- (FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer (0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
- (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
- printf ("Erasing sector %p\n", addr2); /* CLH */
-
- if ((info->flash_id & FLASH_VENDMASK) ==
- FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay (1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7 (info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 =
- (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
+++ /dev/null
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve@icarus.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ident "$Id:$"
-
-# include <common.h>
-# include <pci.h>
-# include "jse_priv.h"
-
-/*
- * The JSE board has an Intel 21555 non-transparent bridge for
- * communication with the host. We need to render it harmless on the
- * JSE side, but leave it alone on the host (primary) side. Normally,
- * this will all be done before the host BIOS can gain access to the
- * board, due to the Primary Access Lockout bit.
- *
- * The host_bridge_init function is called as a late initialization
- * function, after most of the board is set up, including a PCI scan.
- */
-
-void host_bridge_init (void)
-{
- /* The bridge chip is at a fixed location. */
- pci_dev_t dev = PCI_BDF (0, 10, 0);
-
- /* Set PCI Class code --
- The primary side sees this class code at 0x08 in the
- primary config space. This must be something other then a
- bridge, or MS Windows starts doing weird stuff to me. */
- pci_write_config_dword (dev, 0x48, 0x04800000);
-
- /* Set subsystem ID --
- The primary side sees this value at 0x2c. We set it here so
- that the host can tell what sort of device this is:
- We are a Picture Elements [0x12c5] JSE [0x008a]. */
- pci_write_config_dword (dev, 0x6c, 0x008a12c5);
-
- /* Downstream (Primary-to-Secondary) BARs are set up mostly
- off. We need only the Memory-0 Bar so that the host can get
- at the CSR region to set up tables and the lot. */
-
- /* Downstream Memory 0 setup (4K for CSR) */
- pci_write_config_dword (dev, 0xac, 0xfffff000);
- /* Downstream Memory 1 setup (off) */
- pci_write_config_dword (dev, 0xb0, 0x00000000);
- /* Downstream Memory 2 setup (off) */
- pci_write_config_dword (dev, 0xb4, 0x00000000);
- /* Downstream Memory 3 setup (off) */
- pci_write_config_dword (dev, 0xb8, 0x00000000);
-
- /* Upstream (Secondary-to-Primary) BARs are used to get at
- host memory from the JSE card. Create two regions: a small
- one to manage individual word reads/writes, and a larger
- one for doing bulk frame moves. */
-
- /* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
- pci_write_config_dword (dev, 0xc4, 0xfffff000);
- /* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
- pci_write_config_dword (dev, 0xc8, 0xfffff000);
-
- /* Upstream Memory 2 (BAR4) uses page translation, and is set
- up in CCR1. Configure for 4K pages. */
-
- /* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
- bit as well, so we are done configuring after this
- point. Therefore, this must be the last step.
-
- CC1[15:12]= 0 (disable I2O message unit)
- CC1[11:8] = 0x5 (4K page size)
- CC0[11] = 1 (Secondary Clock Disable: disable clock)
- CC0[10] = 0 (Primary Access Lockout: allow primary access)
- */
- pci_write_config_dword (dev, 0xcc, 0x05000800);
-}
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* */
-/* */
-/* The layout for the PEI JSE board: */
-/* Bank 0 - Flash and SRAM */
-/* Bank 1 - SystemACE */
-/* Bank 2 - not used */
-/* Bank 3 - not used */
-/* Bank 4 - not used */
-/* Bank 5 - not used */
-/* Bank 6 - not used */
-/* Bank 7 - not used */
-/*------------------------------------------------------------------------- */
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 /* save link register */
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 10; used to prefetch */
- mtctr r4 /* 10 cache lines to fit this function */
- /* in cache (gives us 8x10=80 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 10 cache lines */
-
- /*----------------------------------------------------------------- */
- /* Delay to ensure all accesses to ROM are complete before changing */
- /* bank 0 timings. 200usec should be enough. */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*----------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*----------------------------------------------------------------- */
- /* Memory Bank 0 (Flash) initialization */
- /*----------------------------------------------------------------- */
-
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x9B01
- ori r4,r4,0x5480
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
- ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr EBC0_CFGDATA,r4
-
- blr
+++ /dev/null
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve@icarus.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-# include <common.h>
-# include <asm/ppc4xx.h>
-# include <asm/processor.h>
-# include <asm/io.h>
-# include "jse_priv.h"
-
-/*
- * This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
- * of being in the init_sequence array.
- *
- * The SDRAM has been initialized already -- start.S:start called
- * init.S:init_sdram early on -- but it is not yet being used for
- * anything, not even stack. So be careful.
- */
-int board_early_init_f (void)
-{
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the JSE board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED/UNUSED
- | IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive
- | IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive
- | IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive
- | IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high
- | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
- | IRQ 31 (EXT IRQ 6) (unused)
- +-------------------------------------------------------------------------*/
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /* Configure the interface to the SystemACE MCU port.
- The SystemACE is fast, but there is no reason to have
- excessivly tight timings. So the settings are slightly
- generous. */
-
- /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
- WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */
- mtdcr (EBC0_CFGADDR, PB1AP);
- mtdcr (EBC0_CFGDATA, 0x01011000);
-
- /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
- mtdcr (EBC0_CFGADDR, PB1CR);
- mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
-
- /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
- /* CPC0_CR1 |= PCIPW */
- mtdcr (0xb2, mfdcr (0xb2) | 0x00004000);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_PRE_INIT
-int board_pre_init (void)
-{
- return board_early_init_f ();
-}
-
-#endif
-
-/*
- * This function is also called by arch/powerpc/lib/board.c:board_init_f (it is
- * also in the init_sequence array) but later. Many more things are
- * configured, but we are still running from flash.
- */
-int checkboard (void)
-{
- unsigned vers, status;
-
- /* check that the SystemACE chip is alive. */
- printf ("ACE: ");
- vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16);
- printf ("SystemACE %u.%u (build %u)",
- (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
-
- status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
-#ifdef DEBUG
- printf (" STATUS=0x%08x", status);
-#endif
- /* If the flash card is present and there is an initial error,
- then force a restart of the program. */
- if (status & 0x00000010) {
- printf (" CFDETECT");
-
- if (status & 0x04) {
- /* CONTROLREG = CFGPROG */
- writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
- udelay (500);
- /* CONTROLREG = CFGRESET */
- writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
- udelay (500);
- writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
- /* CONTROLREG = CFGSTART */
- writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
-
- status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
- }
- }
-
- /* Wait for the SystemACE to program its chain of devices. */
- while ((status & 0x84) == 0x00) {
- udelay (500);
- status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
- }
-
- if (status & 0x04)
- printf (" CFG-ERROR");
- if (status & 0x80)
- printf (" CFGDONE");
-
- printf ("\n");
-
- /* Force /RTS to active. The board it not wired quite
- correctly to use cts/rtc flow control, so just force the
- /RST active and forget about it. */
- writeb (readb (0xef600404) | 0x03, 0xef600404);
-
- printf ("JSE: ready\n");
-
- return 0;
-}
-
-/* **** No more functions called by board_init_f. **** */
-
-/*
- * This function is called by arch/powerpc/lib/board.c:board_init_r. At this
- * point, basic setup is done, U-Boot has been moved into SDRAM and
- * PCI has been set up. From here we done late setup.
- */
-int misc_init_r (void)
-{
- host_bridge_init ();
- return 0;
-}
+++ /dev/null
-#ifndef __jse_priv_H
-#define __jse_prov_H
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve@icarus.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern void host_bridge_init(void);
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve@icarus.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-# define SDRAM_LEN 0x08000000
-
-/*
- * this is even after checkboard. It returns the size of the SDRAM
- * that we have installed. This function is called by board_init_f
- * in arch/powerpc/lib/board.c to initialize the memory and return what I
- * found.
- */
-phys_size_t initdram (int board_type)
-{
- /* Configure the SDRAMS */
-
- /* disable memory controller */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, 0x00000000);
-
- udelay (500);
-
- /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
- mtdcr (SDRAM0_CFGDATA, 0xffffffff);
-
- /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
- mtdcr (SDRAM0_CFGDATA, 0xffffffff);
-
- /* Clear SDRAM0_ECCCFG (disable ECC) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- mtdcr (SDRAM0_CFGDATA, 0x00000000);
-
- /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
- mtdcr (SDRAM0_CFGDATA, 0xffffffff);
-
- /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- mtdcr (SDRAM0_CFGDATA, 0x010a4016);
-
- /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- mtdcr (SDRAM0_CFGDATA, 0x00084001);
-
- /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- mtdcr (SDRAM0_CFGDATA, 0x04084001);
-
- /* Memory Bank 2 Config == BE=0 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- mtdcr (SDRAM0_CFGDATA, 0x00000000);
-
- /* Memory Bank 3 Config == BE=0 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- mtdcr (SDRAM0_CFGDATA, 0x00000000);
-
- /* refresh timer = 0x400 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- mtdcr (SDRAM0_CFGDATA, 0x04000000);
-
- /* Power management idle timer set to the default. */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
- mtdcr (SDRAM0_CFGDATA, 0x07c00000);
-
- udelay (500);
-
- /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, 0x80e00000);
-
- return SDRAM_LEN;
-}
-
-/*
- * The U-Boot core, as part of the initialization to prepare for
- * loading the monitor into SDRAM, requests of this function that the
- * memory be tested. Return 0 if the memory tests OK.
- */
-int testdram (void)
-{
- unsigned long idx;
- unsigned val;
- unsigned errors;
- volatile unsigned long *sdram;
-
-#ifdef DEBUG
- printf ("SDRAM Controller Registers --\n");
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_CFG : 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, 0x24);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_STATUS: 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_B0CR : 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_B1CR : 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_TR : 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_RTR : 0x%08x\n", val);
-#endif
-
- /* Wait for memory to be ready by testing MRSCMPbit
- bit. Really, there should already have been plenty of time,
- given it was started long ago. But, best to check. */
- for (idx = 0; idx < 1000000; idx += 1) {
- mtdcr (SDRAM0_CFGADDR, 0x24);
- val = mfdcr (SDRAM0_CFGDATA);
- if (val & 0x80000000)
- break;
- }
-
- if (!(val & 0x80000000)) {
- printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
- return 1;
- }
-
- /* Start memory test. */
- printf ("test: %u MB - ", SDRAM_LEN / 1048576);
-
- sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE;
-
- printf ("write - ");
- for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
- sdram[idx + 0] = idx;
- sdram[idx + 1] = ~idx;
- }
-
- printf ("read - ");
- errors = 0;
- for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
- if (sdram[idx + 0] != idx)
- errors += 1;
- if (sdram[idx + 1] != ~idx)
- errors += 1;
- if (errors > 0)
- break;
- }
-
- if (errors > 0) {
- printf ("NOT OK\n");
- printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
- sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);
- return 1;
- }
-
- printf ("ok\n");
- return 0;
-}
+++ /dev/null
-if TARGET_KORAT
-
-config SYS_BOARD
- default "korat"
-
-config SYS_CONFIG_NAME
- default "korat"
-
-endif
+++ /dev/null
-KORAT BOARD
-M: Larry Johnson <lrj@acm.org>
-S: Maintained
-F: board/korat/
-F: include/configs/korat.h
-F: configs/korat_defconfig
-F: configs/korat_perm_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = korat.o
-extra-y += init.o
+++ /dev/null
-The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to
-chip select 0 and 1, respectively. FLASH0 contains 16 MiB, and is mapped to
-addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2. FLASH1 contains
-from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash
-Bank #1 (with the starting address depending on the flash size detected at
-runtime). The write-enable pin on FLASH0 is disabled, so the contents of FLASH0
-cannot be modified in the field. This also prevents FLASH0 from executing
-commands to return chip information, so its configuration is hard-coded in
-U-Boot.
-
-There are two versions of U-Boot for Korat: "permanent" and "upgradable". The
-permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses
-0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size. The upgradable U-Boot is
-located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000
-for the current 384 KiB size. FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are
-used for the U-Boot environmental parameters, and addresses 0xF7FC0000 -
-0xF7FDFFFF are used for the redundant copy of the parameters. These locations
-are used by both versions of U-Boot.
-
-On booting, the permanent U-Boot in FLASH0 begins executing. After performing
-minimal setup, it monitors the state of the board's Reset switch (GPIO47). If
-the switch is sensed as open before a timeout period, then U-Boot branches to
-address 0xF7FBFFFC. This causes the upgradable U-Boot to execute from the
-beginning. If the switch remains closed thoughout the timeout period, the
-permanent U-Boot activates the on-board buzzer until the switch is sensed as
-opened. It then continues to execute without branching to FLASH1. The effect
-of this is that normally the Korat board boots its upgradable U-Boot, but, if
-this has been corrupted, the user can boot the permanent U-Boot, which can then
-be used to erase and reload FLASH1 as needed.
-
-Note that it is not necessary for the permanent U-Boot to have all the latest
-features, but only that it have sufficient functionality (working "tftp",
-"erase", "cp.b", etc.) to repair FLASH1. Also, the permanent U-Boot makes no
-assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is
-sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC.
-
-The build sequence:
-
- make korat_perm_config
- make all
-
-builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining
-preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build:
-
- make korat_config
- make all
-
-creates the upgradable U-Boot by selecting loader file "u-boot-F7FC.lds" and
-leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
-
-2008-02-22, Larry Johnson <lrj@acm.org>
-
-
-The CompactFlash(R) controller on the Korat board provides a hi-speed USB
-interface. This may be connected to either a dedicated port on the on-board
-USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot
-environment variable "korat_usbcf" can be used to specify which of these two
-USB host ports is used for CompactFlash. The valid setting for the variable are
-the strings "pci" and "ppc". If the variable defined and set to "ppc", then the
-PowerPC USB port is used. In all other cases the on-board USB controller is
-used, but if "korat_usbcf" is defined but is set to a string other than the two
-valid options, a warning is also issued.
-
-2009-01-28, Larry Johnson <lrj@acm.org>
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# Korat (PPC440EPx) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(emul),1)
-PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
-endif
-
-ifndef CONFIG_KORAT_PERMANENT
-LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds
-endif
+++ /dev/null
-/*
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
-
- /*
- * TLB entries for SDRAM are not needed on this platform. They are
- * generated dynamically in the SPD DDR2 detection routine.
- */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
- AC_RWX | SA_G )
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
-
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
-
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
-
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
-
- /* TLB-entry for EBC */
- tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
-
- /* TLB-entry for Internal Registers & OCM */
- /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
- tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
-
- /*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
-
- /* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
-
- /* TLB-entry PCI IO Space - from sr@denx.de */
- tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
-
- tlbtab_end
-
-#if defined(CONFIG_KORAT_PERMANENT)
- .globl korat_branch_absolute
-korat_branch_absolute:
- mtlr r3
- blr
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007-2010
- * Larry Johnson, lrj@acm.org
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <asm/ppc440.h>
-#include <asm/bitops.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-uic.h>
-#include <asm/processor.h>
-#include <asm/4xx_pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-ulong flash_get_size(ulong base, int banknum);
-
-#if defined(CONFIG_KORAT_PERMANENT)
-void korat_buzzer(int const on)
-{
- if (on) {
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80);
- } else {
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80);
- }
-}
-#endif
-
-int board_early_init_f(void)
-{
- uint32_t sdr0_pfc1, sdr0_pfc2;
- uint32_t reg;
- int eth;
-
-#if defined(CONFIG_KORAT_PERMANENT)
- unsigned mscount;
-
- extern void korat_branch_absolute(uint32_t addr);
-
- for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) {
- udelay(1000);
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) {
- /* This call does not return. */
- korat_branch_absolute(
- CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
- }
- }
- korat_buzzer(1);
- while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_))
- udelay(1000);
-
- korat_buzzer(0);
-#endif
-
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, 0xb8400000);
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /*
- * Take sim card reader and CF controller out of reset. Also enable PHY
- * auto-detect until board-specific PHY resets are available.
- */
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0);
-
- /* Configure the two Ethernet PHYs. For each PHY, configure for fiber
- * if the SFP module is present, and for copper if it is not present.
- */
- for (eth = 0; eth < 2; ++eth) {
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) {
- /* SFP module not present: configure PHY for copper. */
- /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) |
- 0x06 << (4 * eth));
- } else {
- /* SFP module present: configure PHY for fiber and
- enable output */
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0);
- }
- }
- /* enable Ethernet: set GPIO45 and GPIO46 to 1 */
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1);
-
- /* Wait 1 ms, then enable Fiber signal detect to PHYs. */
- udelay(1000);
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88);
-
- /* select Ethernet (and optionally IIC1) pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_4;
-#ifdef CONFIG_I2C_MULTI_BUS
- sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
-#endif
- mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_4;
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* PCI arbiter enabled */
- mfsdr(SDR0_PCI0, reg);
- mtsdr(SDR0_PCI0, 0x80000000 | reg);
-
- return 0;
-}
-
-/*
- * The boot flash on CS0 normally has its write-enable pin disabled, and so will
- * not respond to CFI commands. This routine therefore fills in the flash
- * information for the boot flash. (The flash at CS1 operates normally.)
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- uint32_t addr;
- int i;
-
- if (1 != banknum)
- return 0;
-
- info->size = CONFIG_SYS_FLASH0_SIZE;
- info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000;
- info->flash_id = 0x01000000;
- info->portwidth = 2;
- info->chipwidth = 2;
- info->buffer_size = 32;
- info->erase_blk_tout = 16384;
- info->write_tout = 2;
- info->buffer_write_tout = 5;
- info->vendor = 2;
- info->cmd_reset = 0x00F0;
- info->interface = 2;
- info->legacy_unlock = 0;
- info->manufacturer_id = 1;
- info->device_id = 0x007E;
-
-#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
- info->device_id2 = 0x2101;
-#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
- info->device_id2 = 0x2301;
-#else
-#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE
-#endif
-
- info->ext_addr = 0x0040;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x0055;
- info->addr_unlock1 = 0x00000555;
- info->addr_unlock2 = 0x000002AA;
- info->name = "CFI conformant";
- for (i = 0, addr = -info->size;
- i < info->sector_count;
- ++i, addr += 0x20000) {
- info->start[i] = addr;
- info->protect[i] = 0x00;
- }
- return 1;
-}
-
-static int man_data_read(unsigned int addr)
-{
- /*
- * Read an octet of data from address "addr" in the manufacturer's
- * information serial EEPROM, or -1 on error.
- */
- u8 data[2];
-
- if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
- 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
- debug("man_data_read(0x%02X) failed\n", addr);
- return -1;
- }
- debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
- return data[0];
-}
-
-static unsigned int man_data_field_addr(unsigned int const field)
-{
- /*
- * The manufacturer's information serial EEPROM contains a sequence of
- * zero-delimited fields. Return the starting address of field "field",
- * or 0 on error.
- */
- unsigned addr, i;
-
- if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
- /* Only format "A" is currently supported */
- return 0;
-
- for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
- if ('\0' == man_data_read(addr))
- ++i;
- }
- return (addr < 256) ? addr : 0;
-}
-
-static char *man_data_read_field(char s[], unsigned const field,
- unsigned const length)
-{
- /*
- * Place the null-terminated contents of field "field" of length
- * "length" from the manufacturer's information serial EEPROM into
- * string "s[length + 1]" and return a pointer to s, or return 0 on
- * error. In either case the original contents of s[] is not preserved.
- */
- unsigned addr, i;
-
- addr = man_data_field_addr(field);
- if (0 == addr || addr + length >= 255)
- return 0;
-
- for (i = 0; i < length; ++i) {
- int const c = man_data_read(addr++);
-
- if (c <= 0)
- return 0;
-
- s[i] = (char)c;
- }
- if (0 != man_data_read(addr))
- return 0;
-
- s[i] = '\0';
- return s;
-}
-
-static void set_serial_number(void)
-{
- /*
- * If the environmental variable "serial#" is not set, try to set it
- * from the manufacturer's information serial EEPROM.
- */
- char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
-
- if (getenv("serial#"))
- return;
-
- if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
- return;
-
- s[MAN_INFO_LENGTH] = '-';
- if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
- MAN_MAC_ADDR_LENGTH))
- return;
-
- setenv("serial#", s);
-}
-
-static void set_mac_addresses(void)
-{
- /*
- * If the environmental variables "ethaddr" and/or "eth1addr" are not
- * set, try to set them from the manufacturer's information serial
- * EEPROM.
- */
-
-#if MAN_MAC_ADDR_LENGTH % 2 != 0
-#error MAN_MAC_ADDR_LENGTH must be an even number
-#endif
-
- char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
- char *src;
- char *dst;
-
- if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
- return;
-
- if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
- MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
- return;
-
- for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
- *dst++ = *src++;
- *dst++ = *src++;
- *dst++ = ':';
- }
- if (0 == getenv("ethaddr"))
- setenv("ethaddr", s);
-
- if (0 == getenv("eth1addr")) {
- ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
- setenv("eth1addr", s);
- }
-}
-
-int misc_init_r(void)
-{
- uint32_t pbcr;
- int size_val;
- uint32_t reg;
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
- uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
- char const *const act = getenv("usbact");
- char const *const usbcf = getenv("korat_usbcf");
-
- /*
- * Re-do FLASH1 sizing and adjust flash start and offset.
- */
- gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
- gd->bd->bi_flashoffset = 0;
-
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(flash1_size) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
- /*
- * Re-do FLASH1 sizing and adjust flash offset to reserve space for
- * environment
- */
- gd->bd->bi_flashoffset =
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
-
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
-#if defined(CONFIG_KORAT_PERMANENT)
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- flash_info + 1);
-#else
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- flash_info);
-#endif
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- flash_info);
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- flash_info);
-
- /*
- * USB suff...
- */
- /*
- * Select the USB controller on the 440EPx ("ppc") or on the PCI bus
- * ("pci") for the CompactFlash.
- */
- if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) {
- /*
- * If environment variable "usbcf" is defined and set to "ppc",
- * then connect the CompactFlash controller to the PowerPC USB
- * port.
- */
- printf("Attaching CompactFlash controller to PPC USB\n");
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
- } else {
- if (usbcf != NULL && (strcmp(usbcf, "pci") != 0))
- printf("Warning: \"korat_usbcf\" is not set to a legal "
- "value (\"ppc\" or \"pci\")\n");
-
- printf("Attaching CompactFlash controller to PCI USB\n");
- }
- if (act == NULL || strcmp(act, "hostdev") == 0) {
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-
- /*
- * An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
-
- /*
- * To enable the USB 2.0 Device function
- * through the UTMI interface
- */
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /* clear resets */
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Host(int phy) Device(ext phy)\n");
-
- } else if (strcmp(act, "dev") == 0) {
- /*-------------------PATCH-------------------------------*/
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x672c6000);
-
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000080);
-
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x60206000);
-
- *(unsigned int *)(0xe0000350) = 0x00000001;
-
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x60306000);
- /*-------------------PATCH-------------------------------*/
-
- /* SDR Setting */
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_PFC1, sdr0_pfc1);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
-
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
-
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
-
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* clear resets */
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Device(int phy)\n");
- }
-
- mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
- reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
- mtsdr(SDR0_SRST1, reg);
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
- set_serial_number();
- set_mac_addresses();
- gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1);
-
- return 0;
-}
-
-int checkboard(void)
-{
- char const *const s = getenv("serial#");
- u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0);
-
- printf("Board: Korat, Rev. %X", rev);
- if (s)
- printf(", serial# %s", s);
-
- printf(".\n Ethernet PHY 0: ");
- if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL))
- printf("fiber");
- else
- printf("copper");
-
- printf(", PHY 1: ");
- if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL))
- printf("fiber");
- else
- printf("copper");
-
- printf(".\n");
-#if defined(CONFIG_KORAT_PERMANENT)
- printf(" Executing permanent copy of U-Boot.\n");
-#endif
- return 0;
-}
-
-#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
-/*
- * Assign interrupts to PCI devices.
- */
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
-}
-#endif
-
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /* First do 440EP(x) common setup */
- __pci_target_init(hose);
-
- /*
- * Set up Configuration registers for on-board NEC uPD720101 USB
- * controller.
- */
- pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- u32 val[4];
- int rc;
-
- ft_cpu_setup(blob, bd);
-
- /* Fixup NOR mapping */
- val[0] = 1; /* chip select number */
- val[1] = 0; /* always 0 */
- val[2] = gd->bd->bi_flashstart;
- val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
- rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
- val, sizeof(val), 1);
- if (rc)
- printf("Unable to update property NOR mapping, err=%s\n",
- fdt_strerror(rc));
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xF7FBFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xF7FBF000 :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
+void omap3_set_aux_cr_secure(u32 acr)
+{
+ struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+ emu_romcode_params.num_params = 2;
+ emu_romcode_params.param1 = acr;
+
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
+}
+
/*
* Routine: omap3_update_aux_cr_secure_rx51
* Description: Modify the contents Auxiliary Control Register.
*/
static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
{
- struct emu_hal_params_rx51 emu_romcode_params = { 0, };
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
-
- emu_romcode_params.num_params = 2;
- emu_romcode_params.param1 = acr;
-
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
+ omap3_set_aux_cr_secure(acr);
}
/*
#include <asm/arch/pwm.h>
#endif
#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#ifdef CONFIG_LCD
/* Make sure we finish initing the LCD */
tegra_lcd_check_next_stage(gd->fdt_blob, 1);
+#endif
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+ if (tegra_cpu_is_non_secure()) {
+ printf("CPU is in NS mode\n");
+ setenv("cpu_ns_mode", "1");
+ } else {
+ setenv("cpu_ns_mode", "");
+ }
#endif
return 0;
}
*/
void pinmux_init(void)
{
- pinmux_set_tristate_input_clamping();
+ pinmux_clear_tristate_input_clamping();
gpio_config_table(jetson_tk1_gpio_inits,
ARRAY_SIZE(jetson_tk1_gpio_inits));
/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
/* gpio, init_val */
- GPIO_INIT(C7, IN),
- GPIO_INIT(G0, OUT0),
- GPIO_INIT(G1, OUT0),
+ GPIO_INIT(G0, IN),
+ GPIO_INIT(G1, IN),
GPIO_INIT(G2, IN),
GPIO_INIT(G3, IN),
+ GPIO_INIT(G4, IN),
GPIO_INIT(H2, OUT0),
- GPIO_INIT(H3, OUT0),
GPIO_INIT(H4, IN),
- GPIO_INIT(H5, OUT0),
- GPIO_INIT(H6, IN),
- GPIO_INIT(H7, OUT0),
+ GPIO_INIT(H7, IN),
GPIO_INIT(I0, OUT0),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(I4, OUT0),
- GPIO_INIT(I5, IN),
+ GPIO_INIT(I1, IN),
GPIO_INIT(I6, IN),
GPIO_INIT(J0, IN),
- GPIO_INIT(J2, IN),
GPIO_INIT(K1, OUT0),
GPIO_INIT(K2, IN),
- GPIO_INIT(K3, IN),
GPIO_INIT(K4, OUT0),
- GPIO_INIT(K5, OUT0),
GPIO_INIT(K6, OUT0),
GPIO_INIT(N7, IN),
- GPIO_INIT(O0, IN),
GPIO_INIT(O1, IN),
- GPIO_INIT(O2, IN),
- GPIO_INIT(O3, IN),
GPIO_INIT(O4, IN),
- GPIO_INIT(O5, IN),
- GPIO_INIT(O6, OUT0),
- GPIO_INIT(O7, IN),
- GPIO_INIT(P0, OUT0),
- GPIO_INIT(P1, OUT0),
GPIO_INIT(P2, OUT0),
GPIO_INIT(Q0, IN),
- GPIO_INIT(Q1, IN),
- GPIO_INIT(Q2, IN),
+ GPIO_INIT(Q3, IN),
GPIO_INIT(Q5, IN),
- GPIO_INIT(Q6, IN),
- GPIO_INIT(Q7, IN),
GPIO_INIT(R0, OUT0),
- GPIO_INIT(R1, OUT0),
GPIO_INIT(R2, OUT0),
GPIO_INIT(R4, IN),
- GPIO_INIT(R5, OUT0),
GPIO_INIT(R7, IN),
- GPIO_INIT(S0, IN),
- GPIO_INIT(S3, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S5, IN),
- GPIO_INIT(S6, OUT0),
+ GPIO_INIT(S7, IN),
GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, OUT0),
- GPIO_INIT(U0, OUT0),
+ GPIO_INIT(T1, IN),
+ GPIO_INIT(U0, IN),
GPIO_INIT(U1, IN),
GPIO_INIT(U2, IN),
- GPIO_INIT(U3, OUT0),
- GPIO_INIT(U4, OUT0),
+ GPIO_INIT(U3, IN),
+ GPIO_INIT(U4, IN),
GPIO_INIT(U5, IN),
GPIO_INIT(U6, IN),
GPIO_INIT(V0, IN),
GPIO_INIT(V1, IN),
- GPIO_INIT(W2, IN),
- GPIO_INIT(W3, IN),
- GPIO_INIT(X1, OUT0),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, OUT0),
- GPIO_INIT(X5, IN),
- GPIO_INIT(X6, IN),
+ GPIO_INIT(X1, IN),
+ GPIO_INIT(X4, IN),
GPIO_INIT(X7, OUT0),
GPIO_INIT(BB3, OUT0),
GPIO_INIT(BB5, OUT0),
GPIO_INIT(BB7, OUT0),
GPIO_INIT(CC1, IN),
GPIO_INIT(CC2, IN),
- GPIO_INIT(CC5, OUT0),
- GPIO_INIT(EE1, OUT0),
- GPIO_INIT(FF1, OUT0),
- GPIO_INIT(FF2, IN),
+ GPIO_INIT(EE2, OUT1),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
- PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
- PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG2, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI6, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_CTS_N_PJ5, UARTB, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
- PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
- PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
- PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
+ PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA0_PO1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA3_PO4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL0_PQ0, DEFAULT, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL2_PQ2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL4_PQ4, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL5_PQ5, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL6_PQ6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL7_PQ7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW1_PR1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW11_PS3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU5, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
- PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W3_AUD_PW3, SPI6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PY7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CLK_PZ0, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_REQ_PEE2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DP_HPD_PFF0, DP, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
+ PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
- PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
};
--- /dev/null
+if TARGET_OMAP3_CAIRO
+
+config SYS_BOARD
+ default "cairo"
+
+config SYS_VENDOR
+ default "quipos"
+
+config SYS_CONFIG_NAME
+ default "omap3_cairo"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2014 DENX Software Engineering
+# Written-By: Albert ARIBAUD <albert.aribaud@3adev.fr>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cairo.o
--- /dev/null
+/*
+ * Copyright (c) 2014 DENX
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Derived from code written by Robert Aigner (ra@spiid.net)
+ *
+ * Itself derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <netdev.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+#include <asm/omap_mmc.h>
+#include "cairo.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
+ */
+u8 omap3_evm_need_extvbus(void)
+{
+ u8 retval = 0;
+
+ /* TODO: verify if cairo handheld platform needs extvbus programming */
+
+ return retval;
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_CAIRO();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory.
+ *
+ * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->sharing = SAMSUNG_SHARING;
+ timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
+ timings->ctrla = SAMSUNG_V_ACTIMA_165;
+ timings->ctrlb = SAMSUNG_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mr = SAMSUNG_V_MR_165;
+}
+#endif
+
+static const struct ns16550_platdata cairo_serial = {
+ OMAP34XX_UART2,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(cairo_uart) = {
+ "serial_omap",
+ &cairo_serial
+};
+
+/* force SPL booting into U-Boot, not Linux */
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ return 1;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) DENX
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Original code (C) Copyright 2010
+ * Robert Aigner (ra@spiid.net)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _EVM_H_
+#define _EVM_H_
+
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 Cairo board",
+ "NAND",
+};
+
+/*
+ * OMAP3 Cairo handheld hardware revision
+ */
+enum {
+ OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */
+ OMAP3_CAIRO_BOARD_GEN_2,
+};
+
+#define MUX_CAIRO() \
+MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
+MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \
+ (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+
+#endif
config VIDEO_LCD_PANEL_I2C
bool "LCD panel needs to be configured via i2c"
depends on VIDEO
- default m
+ default n
---help---
Say y here if the LCD panel needs to be configured via i2c. This
will add a bitbang i2c controller using gpios to talk to the LCD.
F: configs/Chuwi_V7_CW0825_defconfig
F: configs/Cubieboard_defconfig
F: configs/Hyundai_A7HD_defconfig
+F: configs/jesurun_q5_defconfig
F: configs/Mele_A1000_defconfig
F: configs/Mele_M3_defconfig
F: configs/Mini-X_defconfig
F: configs/i12-tvbox_defconfig
F: configs/Linksprite_pcDuino3_defconfig
F: configs/Linksprite_pcDuino3_fdt_defconfig
+F: configs/Orangepi_defconfig
+F: configs/Orangepi_mini_defconfig
F: configs/qt840a_defconfig
+F: configs/Wits_Pro_A20_DKT_defconfig
F: include/configs/sun8i.h
F: configs/Ippo_q8h_v1_2_defconfig
F: configs/Cubieboard2_defconfig
F: configs/Cubietruck_defconfig
+FORFUN-Q88DB TABLET
+M: Jens Lucius <info@jenslucius.com>
+S: Maintained
+F: configs/forfun_q88db_defconfig
+
GEMEI-G9 TABLET
M: Priit Laes <plaes@plaes.org>
S: Maintained
S: Maintained
F: configs/Marsboard_A10_defconfig
+MELE I7 BOARD
+M: Marcus Cooper <codekipper@gmail.com>
+S: Maintained
+F: configs/Mele_I7_defconfig
+
MELE M5 BOARD
M: Ian Campbell <ijc@hellion.org.uk>
S: Maintained
F: configs/Mele_M5_defconfig
+MK808C BOARD
+M: Marcus Cooper <codekipper@gmail.com>
+S: Maintained
+F: configs/MK808C_defconfig
+
MSI-PRIMO73 BOARD
M: Siarhei Siamashka <siarhei.siamashka@gmail.com>
S: Maintained
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: configs/TZX-Q8-713B7_defconfig
+
+WEXLER-TAB7200 BOARD
+M: Aleksei Mamlin <mamlinav@gmail.com>
+S: Maintained
+F: configs/Wexler_TAB7200_defconfig
# include "dram_timings_sun4i.h"
.active_windowing = 1,
#endif
- .tpr3 = 0,
+ .tpr3 = CONFIG_DRAM_TPR3,
.tpr4 = 0,
.tpr5 = 0,
.emr1 = CONFIG_DRAM_EMR1,
--- /dev/null
+if TARGET_AMCORE
+
+config SYS_CPU
+ string
+ default "mcf530x"
+
+config SYS_BOARD
+ string
+ default "amcore"
+
+config SYS_VENDOR
+ string
+ default "sysam"
+
+config SYS_CONFIG_NAME
+ string
+ default "amcore"
+
+endif
+
+
+
--- /dev/null
+AMCORE BOARD
+M: Angelo Dureghello <angelo@sysam.it>
+S: Maintained
+F: board/sysam/amcore/
+F: include/configs/amcore.h
+F: configs/amcore_defconfig
--- /dev/null
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = amcore.o
--- /dev/null
+/*
+ * Board functions for Sysam AMCORE (MCF5307 based) board
+ *
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file copies memory testdram() from sandburst/common/sb_common.c
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+void init_lcd(void)
+{
+ /* setup for possible K0108 lcd connected on the parallel port */
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ out_be16(&sim->par, 0x300);
+
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+
+ out_be16(&gpio->paddr, 0xfcff);
+ out_be16(&gpio->padat, 0x0c00);
+}
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("AMCORE v.001(alpha)\n");
+
+ init_lcd();
+
+ return 0;
+}
+
+/*
+ * in initdram we are here executing from flash
+ * case 1:
+ * is with no ACR/flash cache enabled
+ * nop = 40ns (scope measured)
+ */
+void fudelay(int usec)
+{
+ while (usec--)
+ asm volatile ("nop");
+}
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize, RC;
+
+ sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
+
+ /*
+ * SDRAM MT48LC4M32B2 details
+ * Memory block 0: 16 MB of SDRAM at address $00000000
+ * Port size: 32-bit port
+ *
+ * Memory block 0 wired as follows:
+ * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
+ * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
+ *
+ * Ensure that there is a delay of at least 100 microseconds from
+ * processor reset to the following code so that the SDRAM is ready
+ * for commands.
+ */
+ fudelay(100);
+
+ /*
+ * DCR
+ * set proper RC as per specification
+ */
+ RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
+ RC = (RC * 15) >> 4;
+
+ /* 0x8000 is the faster option */
+ out_be16(&dc->dcr, 0x8200 | RC);
+
+ /*
+ * DACR0, page mode continuous, CMD on A20 0x0300
+ */
+ out_be32(&dc->dacr0, 0x00003304);
+
+ dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
+ out_be32(&dc->dmr0, dramsize|1);
+
+ /* issue a PRECHARGE ALL */
+ out_be32(&dc->dacr0, 0x0000330c);
+ out_be32((u32 *)0x00000004, 0xbeaddeed);
+ /* issue AUTOREFRESH */
+ out_be32(&dc->dacr0, 0x0000b304);
+ /* let refresh occour */
+ fudelay(1);
+
+ out_be32(&dc->dacr0, 0x0000b344);
+ out_be32((u32 *)0x00000c00, 0xbeaddeed);
+
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+}
--- /dev/null
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffc00000
--- /dev/null
+/*
+ * Linker script for Sysam AMCORE board
+ *
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf530x/start.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.sdata)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
-if TARGET_AEV
-
-config SYS_BOARD
- default "tqm5200"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "aev"
-
-endif
-
if TARGET_CHARON
config SYS_BOARD
endif
-if TARGET_TB5200
-
-config SYS_BOARD
- default "tqm5200"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "TB5200"
-
-endif
-
if TARGET_TQM5200
config SYS_BOARD
F: configs/cam5200_niosflash_defconfig
F: configs/fo300_defconfig
F: configs/MiniFAP_defconfig
-F: include/configs/TB5200.h
-F: configs/TB5200_defconfig
-F: configs/TB5200_B_defconfig
F: configs/TQM5200_defconfig
F: configs/TQM5200_B_defconfig
F: configs/TQM5200_B_HIGHBOOT_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
+obj-y := tqm5200.o cmd_stk52xx.o cam5200_flash.o
+++ /dev/null
-/*
- * (C) Copyright 2005 - 2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * TB5200 specific functions
- */
-/*#define DEBUG*/
-
-#include <common.h>
-#include <command.h>
-
-#if defined(CONFIG_CMD_BSP)
-#if defined (CONFIG_TB5200)
-
-#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
-
-static void led_init(void)
-{
- struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
- /* configure timer 4 for simple GPIO output */
- gpt->gpt4.emsr |= 0x00000024;
-}
-
-int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
- led_init();
-
- if (strcmp (argv[1], "on") == 0) {
- debug ("switch status LED on\n");
- gpt->gpt4.emsr |= (1 << 4);
- } else if (strcmp (argv[1], "off") == 0) {
- debug ("switch status LED off\n");
- gpt->gpt4.emsr &= ~(1 << 4);
- } else {
- printf ("Usage:\nled on/off\n");
- return 1;
- }
-
- return 0;
-}
-
-static void sm501_backlight (unsigned int state)
-{
- if (state == 1) {
- *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
- (1 << 26) | (1 << 27);
- } else if (state == 0)
- *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
- ~((1 << 26) | (1 << 27));
-}
-
-int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (strcmp (argv[1], "on") == 0) {
- debug ("switch backlight on\n");
- sm501_backlight (1);
- } else if (strcmp (argv[1], "off") == 0) {
- debug ("switch backlight off\n");
- sm501_backlight (0);
- } else {
- printf ("Usage:\nbacklight on/off\n");
- return 1;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- led , 2, 1, cmd_led,
- "switch status LED on or off",
- "on/off"
-);
-
-U_BOOT_CMD(
- backlight , 2, 1, cmd_backlight,
- "switch backlight on or off",
- "on/off"
- );
-
-#endif /* CONFIG_STK52XX */
-#endif
int checkboard (void)
{
-#if defined(CONFIG_AEVFIFO)
- puts ("Board: AEVFIFO\n");
- return 0;
-#endif
-
#if defined(CONFIG_TQM5200S)
# define MODULE_NAME "TQM5200S"
#else
#if defined(CONFIG_STK52XX)
# define CARRIER_NAME "STK52xx"
-#elif defined(CONFIG_TB5200)
-# define CARRIER_NAME "TB5200"
#elif defined(CONFIG_CAM5200)
# define CARRIER_NAME "CAM5200"
#elif defined(CONFIG_FO300)
if (line_number == 1) {
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
- defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
+ defined(CONFIG_STK52XX)
} else if (line_number == 2) {
#if defined (CONFIG_CHARON)
strcpy (info, " on a CHARON carrier board");
#if defined (CONFIG_STK52XX)
strcpy (info, " on a STK52xx carrier board");
#endif
-#if defined (CONFIG_TB5200)
- strcpy (info, " on a TB5200 carrier board");
-#endif
#if defined (CONFIG_FO300)
strcpy (info, " on a FO300 carrier board");
#endif
+++ /dev/null
-if TARGET_W7OLMC
-
-config SYS_BOARD
- default "w7o"
-
-config SYS_CONFIG_NAME
- default "W7OLMC"
-
-endif
-
-if TARGET_W7OLMG
-
-config SYS_BOARD
- default "w7o"
-
-config SYS_CONFIG_NAME
- default "W7OLMG"
-
-endif
+++ /dev/null
-W7O BOARD
-M: Erik Theisen <etheisen@mindspring.com>
-S: Maintained
-F: board/w7o/
-F: include/configs/W7OLMC.h
-F: configs/W7OLMC_defconfig
-F: include/configs/W7OLMG.h
-F: configs/W7OLMG_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = w7o.o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
- watchdog.o
-obj-y += init.o post1.o
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-
-#if defined(CONFIG_CMD_BSP)
-
-#include "vpd.h"
-
-/* ======================================================================
- * Interpreter command to retrieve board specific Vital Product Data, "VPD"
- * ======================================================================
- */
-int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- VPD vpd; /* Board specific data struct */
- uchar dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
-
- /* Validate usage */
- if (argc > 2)
- return cmd_usage(cmdtp);
-
- /* Passed in EEPROM address */
- if (argc == 2)
- dev_addr = (uchar) simple_strtoul (argv[1], NULL, 16);
-
- /* Read VPD and output it */
- if (!vpd_get_data (dev_addr, &vpd)) {
- vpd_print (&vpd);
- return 0;
- }
-
- return 1;
-}
-
-U_BOOT_CMD(
- vpd, 2, 1, do_vpd,
- "Read Vital Product Data",
- "[dev_addr]\n"
- " - Read VPD Data from default address, or device address 'dev_addr'."
-);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ERRORS_H_
-#define _ERRORS_H_
-
-#define ERR_FF -1 /* led test value(2) */
-#define ERR_00 0x0000 /* led test value(2) */
-#define ERR_LED 0x01 /* led test failed (1)(3)(4) */
-#define ERR_RAMG 0x04 /* start SDRAM data bus test (2) */
-#define ERR_RAML 0x05 /* SDRAM data bus fault in LSW chip (5) */
-#define ERR_RAMH 0x06 /* SDRAM data bus fault in MSW chip (6) */
-#define ERR_RAMB 0x07 /* SDRAM data bus fault both chips (5)(6)(7) */
-#define ERR_ADDG 0x08 /* start Address ghosting test (13) */
-#define ERR_ADDF 0x09 /* fault during Address ghosting test (13) */
-#define ERR_POST1 0x0a /* post1 tests complete */
-#define ERR_TMP1 0x0b /* */
-#define ERR_R55G 0x0c /* start SDRAM fill 55 test (2) */
-#define ERR_R55L 0x0d /* SDRAM fill test 55 failed in LSW chip (8) */
-#define ERR_R55H 0x0e /* SDRAM fill test 55 failed in MSW chip (9) */
-#define ERR_R55B 0x0f /* SDRAM fill test 55 fail in both chips (10) */
-#define ERR_RAAG 0x10 /* start SDRAM fill aa test (2) */
-#define ERR_RAAL 0x11 /* SDRAM fill test aa failed in LSW chip (8) */
-#define ERR_RAAH 0x12 /* SDRAM fill test aa failed in MSW chip (9) */
-#define ERR_RAAB 0x13 /* SDRAM fill test aa fail in both chips (10) */
-#define ERR_R00G 0x14 /* start SDRAM fill 00 test (2) */
-#define ERR_R00L 0x15 /* SDRAM fill test 00 failed in LSW chip (8) */
-#define ERR_R00H 0x16 /* SDRAM fill test 00 failed in MSW chip (9) */
-#define ERR_R00B 0x17 /* SDRAM fill test 00 fail in both chips (10) */
-#define ERR_RTCG 0x18 /* start RTC test */
-#define ERR_RTCBAT 0x19 /* RTC battery failure */
-#define ERR_RTCTIM 0x1A /* RTC invalid time/date values */
-#define ERR_RTCVAL 0x1B /* RTC NVRAM not accessable */
-#define ERR_FPGAG 0x20 /* fault during FPGA programming */
-#define ERR_XRW1 0x21 /* Xilinx - can't read/write regs on FPGA 1 */
-#define ERR_XRW2 0x22 /* Xilinx - can't read/write regs on FPGA 2 */
-#define ERR_XRW3 0x23 /* Xilinx - can't read/write regs on FPGA 3 */
-#define ERR_XRW4 0x24 /* Xilinx - can't read/write regs on FPGA 4 */
-#define ERR_XRW5 0x25 /* Xilinx - can't read/write regs on FPGA 5 */
-#define ERR_XRW6 0x26 /* Xilinx - can't read/write regs on FPGA 6 */
-#define ERR_XINIT0 0x27 /* Xilinx - INIT line failed to go low */
-#define ERR_XINIT1 0x28 /* Xilinx - INIT line failed to go high */
-#define ERR_XDONE1 0x29 /* Xilinx - DONE line failed to go high */
-#define ERR_XIMAGE 0x2A /* Xilinx - Bad FPGA image in Flash */
-#define ERR_TempG 0x2b /* start temp sensor tests */
-#define ERR_Tinit0 0x2C /* temp sensor 0 failed to init */
-#define ERR_Tinit1 0x2D /* temp sensor 1 failed to init */
-#define ERR_Ttest0 0x2E /* temp sensor 0 failed test */
-#define ERR_Ttest1 0x2F /* temp sensor 1 failed test */
-#define ERR_lm75r 0x30 /* temp sensor read failure */
-#define ERR_lm75w 0x31 /* temp sensor write failure */
-
-
-#define ERR_POSTOK 0x55 /* PANIC: psych... OK */
-
-#if !defined(__ASSEMBLY__)
-extern void log_stat(int errcode);
-extern void log_warn(int errcode);
-extern void log_err(int errcode);
-#endif
-
-/*
-Debugging suggestions:
-(1) periferal data bus shorted or crossed
-(2) general processor halt, check reset, watch dog, power supply ripple, processor clock.
-(3) check p_we, p_r/w, p_oe, p_rdy lines.
-(4) check LED buffers
-(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip.
-(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip.
-(7) check SDRAM control lines and clocks
-(8) check decoupling caps, replace LSW SDRAM
-(9) check decoupling caps, replace MSW SDRAM
-(10)
-(11)
-(12)
-(13) SDRAM address shorted or unconnected, check sdram caps
-*/
-#endif /* _ERRORS_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- * Based on code by:
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-#include <watchdog.h>
-
-/* info for FLASH chips */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*
- * Functions
- */
-static ulong flash_get_size(vu_long *addr, flash_info_t *info);
-static int write_word8(flash_info_t *info, ulong dest, ulong data);
-static int write_word32(flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-
-unsigned long flash_init(void)
-{
- int i;
- unsigned long size_b0, base_b0;
- unsigned long size_b1;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* Get Size of Boot and Main Flashes */
- size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM,
- &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- return 0;
- }
- size_b1 =
- flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
- &flash_info[1]);
- if (flash_info[1].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
- size_b1, size_b1 << 20);
- return 0;
- }
-
- /* Calculate base addresses */
- base_b0 = -size_b0;
-
- /* Setup offsets for Boot Flash */
- flash_get_offsets(base_b0, &flash_info[0]);
-
- /* Protect board level data */
- (void) flash_protect(FLAG_PROTECT_SET,
- base_b0,
- flash_info[0].start[1] - 1, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void) flash_protect(FLAG_PROTECT_SET,
- base_b0 + size_b0 - monitor_flash_len,
- base_b0 + size_b0 - 1, &flash_info[0]);
-
- /* Protect the FPGA image */
- (void) flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE1_PRELIM,
- FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN -
- 1, &flash_info[1]);
-
- /* Protect the default boot image */
- (void) flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN,
- FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN +
- 0x600000 - 1, &flash_info[1]);
-
- /* Setup offsets for Main Flash */
- flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]);
-
- return size_b0 + size_b1;
-}
-
-static void flash_get_offsets(ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table - FOR BOOT ROM ONLY!!! */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- }
-} /* end flash_get_offsets() */
-
-void flash_print_info(flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("1 x AMD ");
- break;
- case FLASH_MAN_STM:
- printf("1 x STM ");
- break;
- case FLASH_MAN_INTEL:
- printf("2 x Intel ");
- break;
- default:
- printf("Unknown Vendor ");
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- printf("AM29LV040 (4096 Kbit, uniform sector size)\n");
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM)
- printf("M29W040B (4096 Kbit, uniform block size)\n");
- else
- printf("UNKNOWN 29x040x (4096 Kbit, uniform sector size)\n");
- break;
- case FLASH_28F320J3A:
- printf("28F320J3A (32 Mbit = 128K x 32)\n");
- break;
- case FLASH_28F640J3A:
- printf("28F640J3A (64 Mbit = 128K x 64)\n");
- break;
- case FLASH_28F128J3A:
- printf("28F128J3A (128 Mbit = 128K x 128)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
- printf(" Size: %ld KB in %d Blocks\n",
- info->size >> 10, info->sector_count);
- } else {
- printf(" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
- }
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *) info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
- }
- printf("\n");
-} /* end flash_print_info() */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size(vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong base = (ulong) addr;
-
- /* Setup default type */
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
-
- /* Test for Boot Flash */
- if (base == FLASH_BASE0_PRELIM) {
- unsigned char value;
- volatile unsigned char *addr2 = (unsigned char *) addr;
-
- /* Write auto select command: read Manufacturer ID */
- *(addr2 + 0x555) = 0xaa;
- *(addr2 + 0x2aa) = 0x55;
- *(addr2 + 0x555) = 0x90;
-
- /* Manufacture ID */
- value = *addr2;
- switch (value) {
- case (unsigned char) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (unsigned char) STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- *addr2 = 0xf0; /* no or unknown flash */
- return 0;
- }
-
- /* Device ID */
- value = *(addr2 + 1);
- switch (value) {
- case (unsigned char) AMD_ID_LV040B:
- case (unsigned char) STM_ID_29W040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512Kb */
- default:
- *addr2 = 0xf0; /* => no or unknown flash */
- return 0;
- }
- } else { /* MAIN Flash */
- unsigned long value;
- volatile unsigned long *addr2 = (unsigned long *) addr;
-
- /* Write auto select command: read Manufacturer ID */
- *addr2 = 0x90909090;
-
- /* Manufacture ID */
- value = *addr2;
- switch (value) {
- case (unsigned long) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- *addr2 = 0xff; /* no or unknown flash */
- return 0;
- }
-
- /* Device ID - This shit is interleaved... */
- value = *(addr2 + 1);
- switch (value) {
- case (unsigned long) INTEL_ID_28F320J3A:
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000 * 2;
- break; /* => 2 X 4 MB */
- case (unsigned long) INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000 * 2;
- break; /* => 2 X 8 MB */
- case (unsigned long) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000 * 2;
- break; /* => 2 X 16 MB */
- default:
- *addr2 = 0xff; /* => no or unknown flash */
- }
- }
-
- /* Make sure we don't exceed CONFIG_SYS_MAX_FLASH_SECT */
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- /* set up sector start address table */
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- break;
- case FLASH_28F320J3A:
- case FLASH_28F640J3A:
- case FLASH_28F128J3A:
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base +
- (i * 0x00020000 * 2); /* 2 Banks */
- break;
- }
-
- /* Test for Boot Flash */
- if (base == FLASH_BASE0_PRELIM) {
- volatile unsigned char *addr2;
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /*
- * read sector protection at sector address,
- * (AX .. A0) = 0x02
- * D0 = 1 if protected
- */
- addr2 = (volatile unsigned char *) (info->start[i]);
- info->protect[i] = *(addr2 + 2) & 1;
- }
-
- /* Restore read mode */
- *(unsigned char *) base = 0xF0; /* Reset NORMAL Flash */
- } else { /* Main Flash */
- volatile unsigned long *addr2;
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /*
- * read sector protection at sector address,
- * (AX .. A0) = 0x02
- * D0 = 1 if protected
- */
- addr2 = (volatile unsigned long *) (info->start[i]);
- info->protect[i] = *(addr2 + 2) & 0x1;
- }
-
- /* Restore read mode */
- *(unsigned long *) base = 0xFFFFFFFF; /* Reset Flash */
- }
-
- return info->size;
-} /* end flash_get_size() */
-
-static int wait_for_DQ7(ulong addr, uchar cmp_val, ulong tout)
-{
- int i;
-
- volatile uchar *vaddr = (uchar *) addr;
-
- /* Loop X times */
- for (i = 1; i <= (100 * tout); i++) { /* Wait up to tout ms */
- udelay(10);
- /* Pause 10 us */
-
- /* Check for completion */
- if ((vaddr[0] & 0x80) == (cmp_val & 0x80))
- return 0;
-
- /* KEEP THE LUSER HAPPY - Print a dot every 1.1 seconds */
- if (!(i % 110000))
- putc('.');
-
- /* Kick the dog if needed */
- WATCHDOG_RESET();
- }
-
- return 1;
-} /* wait_for_DQ7() */
-
-static int flash_erase8(flash_info_t *info, int s_first, int s_last)
-{
- int tcode, rcode = 0;
- volatile uchar *addr = (uchar *) (info->start[0]);
- volatile uchar *sector_addr;
- int flag, prot, sect;
-
- /* Validate arguments */
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf("- missing\n");
- else
- printf("- no sectors to erase\n");
- return 1;
- }
-
- /* Check for KNOWN flash type */
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- /* Check for protected sectors */
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- sector_addr = (uchar *) (info->start[sect]);
-
- if ((info->flash_id & FLASH_VENDMASK) ==
- FLASH_MAN_STM)
- printf("Erasing block %p\n", sector_addr);
- else
- printf("Erasing sector %p\n", sector_addr);
-
- /* Disable interrupts which might cause timeout */
- flag = disable_interrupts();
-
- *(addr + 0x555) = (uchar) 0xAA;
- *(addr + 0x2aa) = (uchar) 0x55;
- *(addr + 0x555) = (uchar) 0x80;
- *(addr + 0x555) = (uchar) 0xAA;
- *(addr + 0x2aa) = (uchar) 0x55;
- *sector_addr = (uchar) 0x30; /* sector erase */
-
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- * Takes up to 6 seconds.
- */
- tcode = wait_for_DQ7((ulong) sector_addr, 0x80, 6000);
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* Make sure we didn't timeout */
- if (tcode) {
- printf("Timeout\n");
- rcode = 1;
- }
- }
- }
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /* reset to read mode */
- addr = (uchar *) info->start[0];
- *addr = (uchar) 0xF0; /* reset bank */
-
- printf(" done\n");
- return rcode;
-} /* end flash_erase8() */
-
-static int flash_erase32(flash_info_t *info, int s_first, int s_last)
-{
- int flag, sect;
- ulong start, now, last;
- int prot = 0;
-
- /* Validate arguments */
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf("- missing\n");
- else
- printf("- no sectors to erase\n");
- return 1;
- }
-
- /* Check for KNOWN flash type */
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
- printf("Can erase only Intel flash types - aborted\n");
- return 1;
- }
-
- /* Check for protected sectors */
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- start = get_timer(0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- WATCHDOG_RESET();
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *) (info->start[sect]);
- unsigned long status;
-
- /* Disable interrupts which might cause a timeout */
- flag = disable_interrupts();
-
- *addr = 0x00500050; /* clear status register */
- *addr = 0x00200020; /* erase setup */
- *addr = 0x00D000D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* Wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- while (((status = *addr) & 0x00800080) != 0x00800080) {
- now = get_timer(start);
- if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- /* suspend erase */
- *addr = 0x00B000B0;
- /* reset to read mode */
- *addr = 0x00FF00FF;
- return 1;
- }
-
- /*
- * show that we're waiting
- * every second (?)
- */
- if ((now - last) > 990) {
- putc('.');
- last = now;
- }
- }
- *addr = 0x00FF00FF; /* reset to read mode */
- }
- }
- printf(" done\n");
- return 0;
-}
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
- return flash_erase8(info, s_first, s_last);
- else
- return flash_erase32(info, s_first, s_last);
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_buff8(flash_info_t *info, uchar *src, ulong addr,
- ulong cnt)
-{
- ulong cp, wp, data;
- ulong start;
- int i, l, rc;
-
- start = get_timer(0);
-
- wp = (addr & ~3); /* get lower word
- aligned address */
-
- /*
- * handle unaligned start bytes
- */
- l = addr - wp;
- if (l != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
-
- for (; cnt == 0 && i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- rc = write_word8(info, wp, data);
- if (rc != 0)
- return rc;
-
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i)
- data = (data << 8) | *src++;
-
- rc = write_word8(info, wp, data);
- if (rc != 0)
- return rc;
-
- wp += 4;
- cnt -= 4;
- if (get_timer(start) > 1000) { /* every second */
- WATCHDOG_RESET();
- putc('.');
- start = get_timer(0);
- }
- }
-
- if (cnt == 0)
- return 0;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
-
- for (; i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- return write_word8(info, wp, data);
-}
-
-#define FLASH_WIDTH 4 /* flash bus width in bytes */
-static int write_buff32(flash_info_t *info, uchar *src, ulong addr,
- ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
- ulong start;
-
- start = get_timer(0);
-
- if (info->flash_id == FLASH_UNKNOWN)
- return 4;
-
- /* get lower FLASH_WIDTH aligned address */
- wp = (addr & ~(FLASH_WIDTH - 1));
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- for (; i < FLASH_WIDTH && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
-
- for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- rc = write_word32(info, wp, data);
- if (rc != 0)
- return rc;
-
- wp += FLASH_WIDTH;
- }
-
- /*
- * handle FLASH_WIDTH aligned part
- */
- while (cnt >= FLASH_WIDTH) {
- data = 0;
- for (i = 0; i < FLASH_WIDTH; ++i)
- data = (data << 8) | *src++;
-
- rc = write_word32(info, wp, data);
- if (rc != 0)
- return rc;
-
- wp += FLASH_WIDTH;
- cnt -= FLASH_WIDTH;
- if (get_timer(start) > 990) { /* every second */
- putc('.');
- start = get_timer(0);
- }
- }
-
- if (cnt == 0)
- return 0;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
-
- for (; i < FLASH_WIDTH; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- return write_word32(info, wp, data);
-}
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- int retval;
-
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
- retval = write_buff8(info, src, addr, cnt);
- else
- retval = write_buff32(info, src, addr, cnt);
-
- return retval;
-}
-
-/*
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-static int write_word8(flash_info_t *info, ulong dest, ulong data)
-{
- volatile uchar *addr2 = (uchar *) (info->start[0]);
- volatile uchar *dest2 = (uchar *) dest;
- volatile uchar *data2 = (uchar *) &data;
- int flag;
- int i, tcode, rcode = 0;
-
- /* Check if Flash is (sufficently) erased */
- if ((*((volatile uchar *)dest) & (uchar)data) != (uchar)data)
- return 2;
-
- for (i = 0; i < (4 / sizeof(uchar)); i++) {
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *(addr2 + 0x555) = (uchar) 0xAA;
- *(addr2 + 0x2aa) = (uchar) 0x55;
- *(addr2 + 0x555) = (uchar) 0xA0;
-
- dest2[i] = data2[i];
-
- /* Wait for write to complete, up to 1ms */
- tcode = wait_for_DQ7((ulong) &dest2[i], data2[i], 1);
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* Make sure we didn't timeout */
- if (tcode)
- rcode = 1;
- }
-
- return rcode;
-}
-
-static int write_word32(flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *) dest;
- ulong status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = 0x00400040; /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer(0);
-
- while (((status = *addr) & 0x00800080) != 0x00800080) {
- WATCHDOG_RESET();
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0x00FF00FF; /* restore read mode */
- return 1;
- }
- }
-
- *addr = 0x00FF00FF; /* restore read mode */
-
- return 0;
-}
-
-static int _flash_protect(flash_info_t *info, long sector)
-{
- int i;
- int flag;
- ulong status;
- int rcode = 0;
- volatile long *addr = (long *)sector;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A:
- case FLASH_28F640J3A:
- case FLASH_28F128J3A:
- /* Disable interrupts which might cause Flash to timeout */
- flag = disable_interrupts();
-
- /* Issue command */
- *addr = 0x00500050L; /* Clear the status register */
- *addr = 0x00600060L; /* Set lock bit setup */
- *addr = 0x00010001L; /* Set lock bit confirm */
-
- /* Wait for command completion */
- for (i = 0; i < 10; i++) { /* 75us timeout, wait 100us */
- udelay(10);
- if ((*addr & 0x00800080L) == 0x00800080L)
- break;
- }
-
- /* Not successful? */
- status = *addr;
- if (status != 0x00800080L) {
- printf("Protect %x sector failed: %x\n",
- (uint) sector, (uint) status);
- rcode = 1;
- }
-
- /* Restore read mode */
- *addr = 0x00ff00ffL;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- break;
- case FLASH_AM040: /* No soft sector protection */
- break;
- }
-
- /* Turn protection on for this sector */
- for (i = 0; i < info->sector_count; i++) {
- if (info->start[i] == sector) {
- info->protect[i] = 1;
- break;
- }
- }
-
- return rcode;
-}
-
-static int _flash_unprotect(flash_info_t *info, long sector)
-{
- int i;
- int flag;
- ulong status;
- int rcode = 0;
- volatile long *addr = (long *) sector;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A:
- case FLASH_28F640J3A:
- case FLASH_28F128J3A:
- /* Disable interrupts which might cause Flash to timeout */
- flag = disable_interrupts();
-
- *addr = 0x00500050L; /* Clear the status register */
- *addr = 0x00600060L; /* Clear lock bit setup */
- *addr = 0x00D000D0L; /* Clear lock bit confirm */
-
- /* Wait for command completion */
- for (i = 0; i < 80; i++) { /* 700ms timeout, wait 800 */
- udelay(10000); /* Delay 10ms */
- if ((*addr & 0x00800080L) == 0x00800080L)
- break;
- }
-
- /* Not successful? */
- status = *addr;
- if (status != 0x00800080L) {
- printf("Un-protect %x sector failed: %x\n",
- (uint) sector, (uint) status);
- *addr = 0x00ff00ffL;
- rcode = 1;
- }
-
- /* restore read mode */
- *addr = 0x00ff00ffL;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- break;
- case FLASH_AM040: /* No soft sector protection */
- break;
- }
-
- /*
- * Fix Intel's little red wagon. Reprotect
- * sectors that were protected before we undid
- * protection on a specific sector.
- */
- for (i = 0; i < info->sector_count; i++) {
- if (info->start[i] != sector) {
- if (info->protect[i]) {
- if (_flash_protect(info, info->start[i]))
- rcode = 1;
- }
- } else /* Turn protection off for this sector */
- info->protect[i] = 0;
- }
-
- return rcode;
-}
-
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- int rcode;
-
- if (prot)
- rcode = _flash_protect(info, info->start[sector]);
- else
- rcode = _flash_unprotect(info, info->start[sector]);
-
- return rcode;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
- * and
- * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-#include <common.h>
-#include "w7o.h"
-#include <asm/processor.h>
-#include <linux/compiler.h>
-#include "errors.h"
-
-static void
-fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
-{
- unsigned long i;
- volatile unsigned long val;
- volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */
-
- for (i = 0; i < len; i++, src++) {
- val = *src;
- *dest = (unsigned short) ((val & 0xff000000L) >> 16);
- *dest = (unsigned short) ((val & 0x00ff0000L) >> 8);
- *dest = (unsigned short) (val & 0x0000ff00L);
- *dest = (unsigned short) ((val & 0x000000ffL) << 8);
- }
-
- /* Terminate programming with 4 C clocks */
- dest = daddr;
- val = *(unsigned short *) dest;
- val = *(unsigned short *) dest;
- val = *(unsigned short *) dest;
- val = *(unsigned short *) dest;
-
-}
-
-
-int
-fpgaDownload(unsigned char *saddr, unsigned long size, unsigned short *daddr)
-{
- int i; /* index, intr disable flag */
- int start; /* timer */
- unsigned long greg, grego; /* GPIO & output register */
- unsigned long length; /* image size in words */
- unsigned long *source; /* image source addr */
- unsigned short *dest; /* destination FPGA addr */
- volatile unsigned short *ndest; /* temp dest FPGA addr */
- unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */
- unsigned long eirq = GPIO_XCV_IRQ;
- int retval = -1; /* Function return value */
- __maybe_unused volatile unsigned short val; /* temp val */
-
- /* Setup some basic values */
- length = (size / 4) + 1; /* size in words, rounding UP
- is OK */
- source = (unsigned long *) saddr;
- dest = (unsigned short *) daddr;
-
- /* Get DCR output register */
- grego = in32(PPC405GP_GPIO0_OR);
-
- /* Reset FPGA */
- grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(PPC405GP_GPIO0_OR, grego);
-
- /* Setup timeout timer */
- start = get_timer(0);
-
- /* Wait for FPGA init line to go low */
- while (in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) {
- /* Check for timeout - 100us max, so use 3ms */
- if (get_timer(start) > 3) {
- printf(" failed to start init.\n");
- log_warn(ERR_XINIT0); /* Don't halt */
-
- /* Reset line stays low */
- goto done; /* I like gotos... */
- }
- }
-
- /* Unreset FPGA */
- grego |= GPIO_XCV_PROG; /* PROG line high */
- out32(PPC405GP_GPIO0_OR, grego);
-
- /* Wait for FPGA end of init period = init line go hi */
- while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) {
-
- /* Check for timeout */
- if (get_timer(start) > 3) {
- printf(" failed to exit init.\n");
- log_warn(ERR_XINIT1);
-
- /* Reset FPGA */
- grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(PPC405GP_GPIO0_OR, grego);
-
- goto done;
- }
- }
-
- /* Now program FPGA ... */
- ndest = dest;
- for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
- /* Toggle IRQ/GPIO */
- greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
- greg |= eirq; /* toggle irq/gpio */
- mtdcr(CPC0_CR0, greg); /* ... just do it */
-
- /* turn on open drain for CNFG */
- greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */
- greg |= cnfg; /* CNFG open drain */
- out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */
-
- /* Turn output enable on for CNFG */
- greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
- greg |= cnfg; /* CNFG tristate inactive */
- out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
-
- /* Setup FPGA for programming */
- grego &= ~cnfg; /* CONFIG line low */
- out32(PPC405GP_GPIO0_OR, grego);
-
- /*
- * Program the FPGA
- */
- printf("\n destination: 0x%lx ", (unsigned long) ndest);
-
- fpga_img_write(source, length, (unsigned short *) ndest);
-
- /* Done programming */
- grego |= cnfg; /* CONFIG line high */
- out32(PPC405GP_GPIO0_OR, grego);
-
- /* Turn output enable OFF for CNFG */
- greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
- greg &= ~cnfg; /* CNFG tristate inactive */
- out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
-
- /* Toggle IRQ/GPIO */
- greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
- greg &= ~eirq; /* toggle irq/gpio */
- mtdcr(CPC0_CR0, greg); /* ... just do it */
-
- /* XXX - Next FPGA addr */
- ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
- cnfg >>= 1; /* XXX - Next */
- eirq >>= 1;
- }
-
- /* Terminate programming with 4 C clocks */
- ndest = dest;
- for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
- val = *ndest;
- val = *ndest;
- val = *ndest;
- val = *ndest;
- ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
- }
-
- /* Setup timer */
- start = get_timer(0);
-
- /* Wait for FPGA end of programming period = Test DONE low */
- while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) {
-
- /* Check for timeout */
- if (get_timer(start) > 3) {
- printf(" done failed to come high.\n");
- log_warn(ERR_XDONE1);
-
- /* Reset FPGA */
- grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(PPC405GP_GPIO0_OR, grego);
-
- goto done;
- }
- }
-
- printf("\n FPGA load succeeded\n");
- retval = 0; /* Program OK */
-
-done:
- return retval;
-}
-
-/* FPGA image is stored in flash */
-extern flash_info_t flash_info[];
-
-int init_fpga(void)
-{
- unsigned int i, j, ptr; /* General purpose */
- unsigned char bufchar; /* General purpose character */
- unsigned char *buf; /* Start of image pointer */
- unsigned long len; /* Length of image */
- unsigned char *fn_buf; /* Start of filename string */
- unsigned int fn_len; /* Length of filename string */
- unsigned char *xcv_buf; /* Pointer to start of image */
- unsigned long xcv_len; /* Length of image */
- unsigned long crc; /* 30bit crc in image */
- unsigned long calc_crc; /* Calc'd 30bit crc */
- int retval = -1;
-
- /* Tell the world what we are doing */
- printf("FPGA: ");
-
- /*
- * Get address of first sector where the FPGA
- * image is stored.
- */
- buf = (unsigned char *) flash_info[1].start[0];
-
- /*
- * Get the stored image's CRC & length.
- */
- crc = *(unsigned long *) (buf + 4); /* CRC is first long word */
- len = *(unsigned long *) (buf + 8); /* Image len is next long */
-
- /* Pedantic */
- if ((len < 0x133A4) || (len > 0x80000))
- goto bad_image;
-
- /*
- * Get the file name pointer and length.
- * filename length is next short
- */
- fn_len = (*(unsigned short *) (buf + 12) & 0xff);
- fn_buf = buf + 14;
-
- /*
- * Get the FPGA image pointer and length length.
- */
- xcv_buf = fn_buf + fn_len; /* pointer to fpga image */
- xcv_len = len - 14 - fn_len; /* fpga image length */
-
- /* Check for uninitialized FLASH */
- if ((strncmp((char *) buf, "w7o", 3) != 0) || (len > 0x0007ffffL)
- || (len == 0))
- goto bad_image;
-
- /*
- * Calculate and Check the image's CRC.
- */
- calc_crc = crc32(0, xcv_buf, xcv_len);
- if (crc != calc_crc) {
- printf("\nfailed - bad CRC\n");
- goto done;
- }
-
- /* Output the file name */
- printf("file name : ");
- for (i = 0; i < fn_len; i++) {
- bufchar = fn_buf[+i];
- if (bufchar < ' ' || bufchar > '~')
- bufchar = '.';
- putc(bufchar);
- }
-
- /*
- * find rest of display data
- */
- ptr = 15; /* Offset to ncd filename
- length in fpga image */
- j = xcv_buf[ptr]; /* Get len of ncd filename */
- if (j > 32)
- goto bad_image;
- ptr = ptr + j + 3; /* skip ncd filename string +
- 3 bytes more bytes */
-
- /*
- * output target device string
- */
- j = xcv_buf[ptr++] - 1; /* len of targ str less term */
- if (j > 32)
- goto bad_image;
- printf("\n target : ");
- for (i = 0; i < j; i++) {
- bufchar = (xcv_buf[ptr++]);
- if (bufchar < ' ' || bufchar > '~')
- bufchar = '.';
- putc(bufchar);
- }
-
- /*
- * output compilation date string and time string
- */
- ptr += 3; /* skip 2 bytes */
- printf("\n synth time : ");
- j = (xcv_buf[ptr++] - 1); /* len of date str less term */
- if (j > 32)
- goto bad_image;
- for (i = 0; i < j; i++) {
- bufchar = (xcv_buf[ptr++]);
- if (bufchar < ' ' || bufchar > '~')
- bufchar = '.';
- putc(bufchar);
- }
-
- ptr += 3; /* Skip 2 bytes */
- printf(" - ");
- j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */
- if (j > 32)
- goto bad_image;
- for (i = 0; i < j; i++) {
- bufchar = (xcv_buf[ptr++]);
- if (bufchar < ' ' || bufchar > '~')
- bufchar = '.';
- putc(bufchar);
- }
-
- /*
- * output crc and length strings
- */
- printf("\n len & crc : 0x%lx 0x%lx", len, crc);
-
- /*
- * Program the FPGA.
- */
- retval = fpgaDownload((unsigned char *) xcv_buf, xcv_len,
- (unsigned short *) 0xfd000000L);
- return retval;
-
-bad_image:
- printf("\n BAD FPGA image format @ %lx\n",
- flash_info[1].start[0]);
- log_warn(ERR_XIMAGE);
-done:
- return retval;
-}
-
-void test_fpga(unsigned short *daddr)
-{
- int i;
- volatile unsigned short *ndest = daddr;
-
- for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
-#if defined(CONFIG_W7OLMG)
- ndest[0x7e] = 0x55aa;
- if (ndest[0x7e] != 0x55aa)
- log_warn(ERR_XRW1 + i);
- ndest[0x7e] = 0xaa55;
- if (ndest[0x7e] != 0xaa55)
- log_warn(ERR_XRW1 + i);
- ndest[0x7e] = 0xc318;
- if (ndest[0x7e] != 0xc318)
- log_warn(ERR_XRW1 + i);
-
-#elif defined(CONFIG_W7OLMC)
- ndest[0x800] = 0x55aa;
- ndest[0x801] = 0xaa55;
- ndest[0x802] = 0xc318;
- ndest[0x4800] = 0x55aa;
- ndest[0x4801] = 0xaa55;
- ndest[0x4802] = 0xc318;
- if ((ndest[0x800] != 0x55aa) ||
- (ndest[0x801] != 0xaa55) || (ndest[0x802] != 0xc318))
- log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */
- if ((ndest[0x4800] != 0x55aa) ||
- (ndest[0x4801] != 0xaa55) || (ndest[0x4802] != 0xc318))
- log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */
-
-#else
-#error "Unknown W7O board configuration"
-#endif
- }
-
- printf(" FPGA ready\n");
- return;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wave 7 Optics, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <elf.h>
-
-/*
- * FIXME: Add code to test image and it's header.
- */
-static int
-image_check(ulong addr)
-{
- return valid_elf_image(addr);
-}
-
-void
-init_fsboot(void)
-{
- char *envp;
- ulong loadaddr;
- ulong testaddr;
- ulong alt_loadaddr;
- char buf[9];
-
- /*
- * Get test image address
- */
- if ((envp = getenv("testaddr")) != NULL)
- testaddr = simple_strtoul(envp, NULL, 16);
- else
- testaddr = -1;
-
- /*
- * Are we going to test boot and image?
- */
- if ((testaddr != -1) && image_check(testaddr)) {
-
- /* Set alt_loadaddr */
- alt_loadaddr = testaddr;
- sprintf(buf, "%lX", alt_loadaddr);
- setenv("alt_loadaddr", buf);
-
- /* Clear test_addr */
- setenv("testaddr", NULL);
-
- /*
- * Save current environment with alt_loadaddr,
- * and cleared testaddr.
- */
- saveenv();
-
- /*
- * Setup temporary loadaddr to alt_loadaddr
- * XXX - DO NOT SAVE ENVIRONMENT!
- */
- loadaddr = alt_loadaddr;
- sprintf(buf, "%lX", loadaddr);
- setenv("loadaddr", buf);
-
- } else { /* Normal boot */
- setenv("alt_loadaddr", NULL); /* Clear alt_loadaddr */
- setenv("testaddr", NULL); /* Clear testaddr */
- saveenv();
- }
-
- return;
-}
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-/******************************************************************************
- * Function: ext_bus_cntlr_init
- *
- * Description: Configures EBC Controller and a few basic chip selects.
- *
- * CS0 is setup to get the Boot Flash out of the addresss range
- * so that we may setup a stack. CS7 is setup so that we can
- * access and reset the hardware watchdog.
- *
- * IMPORTANT: For pass1 this code must run from
- * cache since you can not reliably change a peripheral banks
- * timing register (pbxap) while running code from that bank.
- * For ex., since we are running from ROM on bank 0, we can NOT
- * execute the code that modifies bank 0 timings from ROM, so
- * we run it from cache.
- *
- * Notes: Does NOT use the stack.
- *****************************************************************************/
- .section ".text"
- .align 2
- .globl ext_bus_cntlr_init
- .type ext_bus_cntlr_init, @function
-ext_bus_cntlr_init:
- mflr r0
- /********************************************************************
- * Prefetch entire ext_bus_cntrl_init function into the icache.
- * This is necessary because we are going to change the same CS we
- * are executing from. Otherwise a CPU lockup may occur.
- *******************************************************************/
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
-
- /* Calculate number of cache lines for this function */
- addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
- mtctr r4
-..ebcloop:
- icbt r0, r3 /* prefetch cache line for addr in r3*/
- addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
- bdnz ..ebcloop /* continue for $CTR cache lines */
-
- /********************************************************************
- * Delay to ensure all accesses to ROM are complete before changing
- * bank 0 timings. 200usec should be enough.
- * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
- *******************************************************************/
- addis r3, 0, 0x0
- ori r3, r3, 0xA000 /* wait 200us from reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /********************************************************************
- * Setup External Bus Controller (EBC).
- *******************************************************************/
- addi r3, 0, EBC0_CFG
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
- ori r4, r4, 0x0 /* Drive CS with external master */
- mtdcr EBC0_CFGDATA, r4
-
- /********************************************************************
- * Change PCIINT signal to PerWE
- *******************************************************************/
- mfdcr r4, CPC0_CR1
- ori r4, r4, 0x4000
- mtdcr CPC0_CR1, r4
-
- /********************************************************************
- * Memory Bank 0 (Flash Bank 0) initialization
- *******************************************************************/
- addi r3, 0, PB1AP
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
- ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
- mtdcr EBC0_CFGDATA, r4
-
- addi r3, 0, PB0CR
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
- ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
- mtdcr EBC0_CFGDATA, r4
-
- /********************************************************************
- * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
- *******************************************************************/
- addi r3, 0, PB7AP
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
- ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
- mtdcr EBC0_CFGDATA, r4
-
- addi r3, 0, PB7CR
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
- ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
- mtdcr EBC0_CFGDATA, r4
-
- /* We are all done */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
-/* end ext_bus_cntlr_init() */
-
-/******************************************************************************
- * Function: sdram_init
- *
- * Description: Configures SDRAM memory banks.
- *
- * Serial Presence Detect, "SPD," reads the SDRAM EEPROM
- * via the IIC bus and then configures the SDRAM memory
- * banks appropriately. If Auto Memory Configuration is
- * is not used, it is assumed that a 4MB 11x8x2, non-ECC,
- * SDRAM is soldered down.
- *
- * Notes: Expects that the stack is already setup.
- *****************************************************************************/
- .section ".text"
- .align 2
- .globl sdram_init
- .type sdram_init, @function
-sdram_init:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -8(r1) /* Save back chain and move SP */
- stw r0, +12(r1) /* Save link register */
-
- /*
- * First call spd_sdram to try to init SDRAM according to the
- * contents of the SPD EEPROM. If the SPD EEPROM is blank or
- * erronious, spd_sdram returns 0 in R3.
- */
- li r3,0
- bl spd_sdram
- addic. r3, r3, 0 /* Check for error, save dram size */
- bne ..sdri_done /* If it worked, we're done... */
-
- /********************************************************************
- * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
- * is the SMALLEST SDRAM size the 405 supports. We can do this
- * because W7O boards have soldered on RAM, and there will always
- * be some amount present. If we were using DIMMs, we should hang
- * the board instead, since it doesn't have any RAM to continue
- * running with.
- *******************************************************************/
-
- /*
- * Disable memory controller to allow
- * values to be changed.
- */
- addi r3, 0, SDRAM0_CFG
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x0
- ori r4, r4, 0x0
- mtdcr SDRAM0_CFGDATA, r4
-
- /*
- * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
- * All other banks are disabled.
- */
- addi r3, 0, SDRAM0_B0CR
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
- ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
- mtdcr SDRAM0_CFGDATA, r4
-
- /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
- addi r4, 0, 0 /* Zero the data reg */
-
- addi r3, r3, 4 /* Point to MB1CF reg */
- mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
- mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
-
- addi r3, r3, 4 /* Point to MB2CF reg */
- mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
- mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
-
- addi r3, r3, 4 /* Point to MB3CF reg */
- mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
- mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
-
- /********************************************************************
- * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
- * To set the appropriate timings, we assume sdram is
- * 100MHz (pc100 compliant).
- *******************************************************************/
-
- /*
- * Set up SDTR1
- */
- addi r3, 0, SDRAM0_TR
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
- ori r4, r4, 0x400D
- mtdcr SDRAM0_CFGDATA, r4
-
- /*
- * Set RTR
- */
- addi r3, 0, SDRAM0_RTR
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
- mtdcr SDRAM0_CFGDATA, r4
-
- /********************************************************************
- * Delay to ensure 200usec have elapsed since reset. Assume worst
- * case that the core is running 200Mhz:
- * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- *******************************************************************/
- addis r3, 0, 0x0000
- ori r3, r3, 0xA000 /* Wait 200us from reset */
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 /* spin loop */
-
- /********************************************************************
- * Set memory controller options reg, MCOPT1.
- *******************************************************************/
- addi r3, 0, SDRAM0_CFG
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
- ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
- mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */
-
-..sdri_done:
- /* restore and return */
- lwz r0, +12(r1) /* Get saved link register */
- addi r1, r1, +8 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-.Lfe1: .size sdram_init,.Lfe1-sdram_init
-/* end sdram_init() */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
- * and
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * Description:
- * Routine to exercise memory for the bringing up of our boards.
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include <watchdog.h>
-
-#include "errors.h"
-
-#define _ASMLANGUAGE
-
- .globl test_sdram
- .globl test_led
- .globl log_stat
- .globl log_warn
- .globl log_err
- .globl temp_uart_init
- .globl post_puts
- .globl disp_hex
-
-/*****************************************************
-******* Text Strings for low level printing ******
-******* In section got2 *******
-*****************************************************/
-
-/*
- * Define the text strings for errors and warnings.
- * Switch to .data section.
- */
- .section ".data"
-err_str: .asciz "*** POST ERROR = "
-warn_str: .asciz "*** POST WARNING = "
-end_str: .asciz "\r\n"
-
-/*
- * Enter the labels in Global Entry Table (GOT).
- * Switch to .got2 section.
- */
- START_GOT
- GOT_ENTRY(err_str)
- GOT_ENTRY(warn_str)
- GOT_ENTRY(end_str)
- END_GOT
-
-/*
- * Switch back to .text section.
- */
- .text
-
-/****************************************
- ****************************************
- ******** LED register test ********
- ****************************************
- ***************************************/
-test_led:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
-
- WATCHDOG_RESET /* Reset the watchdog */
-
- addi r3, 0, ERR_FF /* first test value is ffff */
- addi r4, r3, 0 /* save copy of pattern */
- bl set_led /* store first test value */
- bl get_led /* read it back */
- xor. r4, r4, r3 /* compare to original */
-#if defined(CONFIG_W7OLMC)
- andi. r4, r4, 0x00ff /* lmc has 8 bits */
-#else
- andi. r4, r4, 0xffff /* lmg has 16 bits */
-#endif
- beq LED2 /* next test */
- addi r3, 0, ERR_LED /* error code = 1 */
- bl log_err /* display error and halt */
-LED2: addi r3, 0, ERR_00 /* 2nd test value is 0000 */
- addi r4, r3, 0 /* save copy of pattern */
- bl set_led /* store first test value */
- bl get_led /* read it back */
- xor. r4, r4, r3 /* compare to original */
-#if defined(CONFIG_W7OLMC)
- andi. r4, r4, 0x00ff /* lmc has 8 bits */
-#else
- andi. r4, r4, 0xffff /* lmg has 16 bits */
-#endif
- beq LED3 /* next test */
- addi r3, 0, ERR_LED /* error code = 1 */
- bl log_err /* display error and halt */
-
-LED3: /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- lwz r4, +8(r1) /* restore r4 */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-/****************************************
- ****************************************
- ******** SDRAM TESTS ********
- ****************************************
- ***************************************/
-test_sdram:
- /* called with mem size in r3 */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -16(r1) /* Save back chain and move SP */
- stw r0, +20(r1) /* Save link register */
- stmw r30, +8(r1) /* save R30,R31 */
- /* r30 is log2(mem size) */
- /* r31 is mem size */
-
- /* take log2 of total mem size */
- addi r31, r3, 0 /* save total mem size */
- addi r30, 0, 0 /* clear r30 */
-l2_loop:
- srwi. r31, r31, 1 /* shift right 1 */
- addi r30, r30, 1 /* count shifts */
- bne l2_loop /* loop till done */
- addi r30, r30, -1 /* correct for over count */
- addi r31, r3, 0 /* save original size */
-
- /* now kick the dog and test the mem */
- WATCHDOG_RESET /* Reset the watchdog */
- bl Data_Buster /* test crossed/shorted data lines */
- addi r3, r30, 0 /* get log2(memsize) */
- addi r4, r31, 0 /* get memsize */
- bl Ghost_Buster /* test crossed/shorted addr lines */
- addi r3, r31, 0 /* get mem size */
- bl Bit_Buster /* check for bad internal bits */
-
- /* restore stack and return */
- lmw r30, +8(r1) /* Restore r30, r31 */
- lwz r0, +20(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- addi r1, r1, +16 /* Remove frame from stack */
- blr /* Return to calling function */
-
-
-/****************************************
- ******** sdram data bus test ********
- ***************************************/
-Data_Buster:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -24(r1) /* Save back chain and move SP */
- stw r0, +28(r1) /* Save link register */
- stmw r28, 8(r1) /* save r28 - r31 on stack */
- /* r31 i/o register */
- /* r30 sdram base address */
- /* r29 5555 syndrom */
- /* r28 aaaa syndrom */
-
- /* set up led register for this test */
- addi r3, 0, ERR_RAMG /* set led code to 1 */
- bl log_stat /* store test value */
- /* now test the dram data bus */
- xor r30, r30, r30 /* load r30 with base addr of sdram */
- addis r31, 0, 0x5555 /* load r31 with test value */
- ori r31, r31, 0x5555
- stw r31,0(r30) /* sto the value */
- lwz r29,0(r30) /* read it back */
- xor r29,r31,r29 /* compare it to original */
- addis r31, 0, 0xaaaa /* load r31 with test value */
- ori r31, r31, 0xaaaa
- stw r31,0(r30) /* sto the value */
- lwz r28,0(r30) /* read it back */
- xor r28,r31,r28 /* compare it to original */
- or r3,r28,r29 /* or together both error terms */
- /*
- * Now that we have the error bits,
- * we have to decide which part they are in.
- */
- bl get_idx /* r5 is now index to error */
- addi r3, r3, ERR_RAMG
- cmpwi r3, ERR_RAMG /* check for errors */
- beq db_done /* skip if no errors */
- bl log_err /* log the error */
-
-db_done:
- lmw r28, 8(r1) /* restore r28 - r31 from stack */
- lwz r0, +28(r1) /* Get saved link register */
- addi r1, r1, +24 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/****************************************************
- ******** test for address ghosting in dram ********
- ***************************************************/
-
-Ghost_Buster:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -36(r1) /* Save back chain and move SP */
- stw r0, +40(r1) /* Save link register */
- stmw r25, 8(r1) /* save r25 - r31 on stack */
- /* r31 = scratch register */
- /* r30 is main referance loop counter,
- 0 to 23 */
- /* r29 is ghost loop count, 0 to 22 */
- /* r28 is referance address */
- /* r27 is ghost address */
- /* r26 is log2 (mem size) =
- number of byte addr bits */
- /* r25 is mem size */
-
- /* save the log2(mem size) and mem size */
- addi r26, r3, 0 /* r26 is number of byte addr bits */
- addi r25, r4, 0 /* r25 is mem size in bytes */
-
- /* set the leds for address ghost test */
- addi r3, 0, ERR_ADDG
- bl set_led
-
- /* first fill memory with zeros */
- srwi r31, r25, 2 /* convert bytes to longs */
- mtctr r31 /* setup byte counter */
- addi r28, 0, 0 /* start at address at 0 */
- addi r31, 0, 0 /* data value = 0 */
-clr_loop:
- stw r31, 0(r28) /* Store zero value */
- addi r28, r28, 4 /* Increment to next word */
- andi. r27, r28, 0xffff /* check for 2^16 loops */
- bne clr_skip /* if not there, then skip */
- WATCHDOG_RESET /* kick the dog every now and then */
-clr_skip:
- bdnz clr_loop /* Round and round... */
-
- /* now do main test */
- addi r30, 0, 0 /* start referance counter at 0 */
-outside:
- /*
- * Calculate the referance address
- * the referance address is calculated by setting the (r30-1)
- * bit of the base address
- * when r30=0, the referance address is the base address.
- * thus the sequence 0,1,2,4,8,..,2^(n-1)
- * setting the bit is done with the following shift functions.
- */
- WATCHDOG_RESET /* Reset the watchdog */
-
- addi r31, 0, 1 /* r31 = 1 */
- slw r28, r31, r30 /* set bit coresponding to loop cnt */
- srwi r28, r28, 1 /* then shift it right one so */
- /* we start at location 0 */
- /* fill referance address with Fs */
- addi r31, 0, 0x00ff /* r31 = one byte of set bits */
- stb r31,0(r28) /* save ff in referance address */
-
- /* ghost (inner) loop, now check all posible ghosted addresses */
- addi r29, 0, 0 /* start ghosted loop counter at 0 */
-inside:
- /*
- * Calculate the ghost address by flipping one
- * bit of referance address. This gives the
- * sequence 1,2,4,8,...,2^(n-1)
- */
- addi r31, 0, 1 /* r31 = 1 */
- slw r27, r31, r29 /* set bit coresponding to loop cnt */
- xor r27, r28, r27 /* ghost address = ref addr with
- bit flipped*/
-
- /* now check for ghosting */
- lbz r31,0(r27) /* get content of ghost addr */
- cmpwi r31, 0 /* compare read value to 0 */
- bne Casper /* we found a ghost! */
-
- /* now close ghost ( inner ) loop */
- addi r29, r29, 1 /* increment inner loop counter */
- cmpw r29, r26 /* check for last inner loop */
- blt inside /* do more inner loops */
-
- /* now close referance ( outer ) loop */
- addi r31, 0, 0 /* r31 = zero */
- stb r31, 0(28) /* zero out the altered address loc. */
- /*
- * Increment and check for end, count is zero based.
- * With the ble, this gives us one more loops than
- * address bits for sequence 0,1,2,4,8,...2^(n-1)
- */
- addi r30, r30, 1 /* increment outer loop counter */
- cmpw r30, r26 /* check for last inner loop */
- ble outside /* do more outer loops */
-
- /* were done, lets go home */
- b gb_done
-Casper: /* we found a ghost !! */
- addi r3, 0, ERR_ADDF /* get indexed error message */
- bl log_err /* log error led error code */
-gb_done: /* pack your bags, and go home */
- lmw r25, 8(r1) /* restore r25 - r31 from stack */
- lwz r0, +40(r1) /* Get saved link register */
- addi r1, r1, +36 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-/****************************************************
- ******** SDRAM data fill tests **********
- ***************************************************/
-Bit_Buster:
- /* called with mem size in r3 */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -16(r1) /* Save back chain and move SP */
- stw r0, +20(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
- stw r5, +12(r1) /* save r5 */
-
- addis r5, r3, 0 /* save mem size */
-
- /* Test 55555555 */
- addi r3, 0, ERR_R55G /* set up error code in case we fail */
- bl log_stat /* store test value */
- addis r4, 0, 0x5555
- ori r4, r4, 0x5555
- bl fill_test
-
- /* Test aaaaaaaa */
- addi r3, 0, ERR_RAAG /* set up error code in case we fail */
- bl log_stat /* store test value */
- addis r4, 0, 0xAAAA
- ori r4, r4, 0xAAAA
- bl fill_test
-
- /* Test 00000000 */
- addi r3, 0, ERR_R00G /* set up error code in case we fail */
- bl log_stat /* store test value */
- addis r4, 0, 0
- ori r4, r4, 0
- bl fill_test
-
- /* restore stack and return */
- lwz r5, +12(r1) /* restore r4 */
- lwz r4, +8(r1) /* restore r4 */
- lwz r0, +20(r1) /* Get saved link register */
- addi r1, r1, +16 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/****************************************************
- ******** fill test ********
- ***************************************************/
-/* tests memory by filling with value, and reading back */
-/* r5 = Size of memory in bytes */
-/* r4 = Value to write */
-/* r3 = Error code */
-fill_test:
- mflr r0 /* Get link register */
- stwu r1, -32(r1) /* Save back chain and move SP */
- stw r0, +36(r1) /* Save link register */
- stmw r27, 8(r1) /* save r27 - r31 on stack */
- /* r31 - scratch register */
- /* r30 - memory address */
- mr r27, r3
- mr r28, r4
- mr r29, r5
-
- WATCHDOG_RESET /* Reset the watchdog */
-
- /* first fill memory with Value */
- srawi r31, r29, 2 /* convert bytes to longs */
- mtctr r31 /* setup counter */
- addi r30, 0, 0 /* Make r30 = addr 0 */
-ft_0: stw r28, 0(r30) /* Store value */
- addi r30, r30, 4 /* Increment to next word */
- andi. r31, r30, 0xffff /* check for 2^16 loops */
- bne ft_0a /* if not there, then skip */
- WATCHDOG_RESET /* kick the dog every now and then */
-ft_0a: bdnz ft_0 /* Round and round... */
-
- WATCHDOG_RESET /* Reset the watchdog */
-
- /* Now confirm Value is in memory */
- srawi r31, r29, 2 /* convert bytes to longs */
- mtctr r31 /* setup counter */
- addi r30, 0, 0 /* Make r30 = addr 0 */
-ft_1: lwz r31, 0(r30) /* get value from memory */
- xor. r31, r31, r28 /* Writen = Read ? */
- bne ft_err /* If bad, than halt */
- addi r30, r30, 4 /* Increment to next word */
- andi. r31, r30, 0xffff /* check for 2^16 loops*/
- bne ft_1a /* if not there, then skip */
- WATCHDOG_RESET /* kick the dog every now and then */
-ft_1a: bdnz ft_1 /* Round and round... */
-
- WATCHDOG_RESET /* Reset the watchdog */
-
- b fill_done /* restore and return */
-
-ft_err: addi r29, r27, 0 /* save current led code */
- addi r27, r31, 0 /* get pattern in r27 */
- bl get_idx /* get index from r27 */
- add r27, r27, r29 /* add index to old led code */
- bl log_err /* output led err code, halt CPU */
-
-fill_done:
- lmw r27, 8(r1) /* restore r27 - r31 from stack */
- lwz r0, +36(r1) /* Get saved link register */
- addi r1, r1, +32 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/****************************************************
- ******* get error index from r3 pattern ********
- ***************************************************/
-get_idx: /* r3 = (MSW(r3) !=0)*2 +
- (LSW(r3) !=0) */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
-
- andi. r4, r3, 0xffff /* check for lower bits */
- beq gi2 /* skip if no bits set */
- andis. r4, r3, 0xffff /* check for upper bits */
- beq gi3 /* skip if no bits set */
- addi r3, 0, 3 /* both upper and lower bits set */
- b gi_done
-gi2: andis. r4, r3, 0xffff /* check for upper bits*/
- beq gi4 /* skip if no bits set */
- addi r3, 0, 2 /* only upper bits set */
- b gi_done
-gi3: addi r3, 0, 1 /* only lower bits set */
- b gi_done
-gi4: addi r3, 0, 0 /* no bits set */
-gi_done:
- /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- lwz r4, +8(r1) /* restore r4 */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-/****************************************************
- ******** set LED to R5 and hang ********
- ***************************************************/
-log_stat: /* output a led code and continue */
-set_led:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
-
- addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */
-#if defined(CONFIG_W7OLMG) /* only on gateway, invert outputs */
- xori r3,r3, 0xffff /* complement led code, active low */
- sth r3, 0(r4) /* store first test value */
- xori r3,r3, 0xffff /* complement led code, active low */
-#else /* if not gateway, then don't invert */
- sth r3, 0(r4) /* store first test value */
-#endif
-
- /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- lwz r4, +8(r1) /* restore r4 */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-get_led:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
-
- addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */
- lhz r3, 0(r4) /* store first test value */
-#if defined(CONFIG_W7OLMG) /* only on gateway, invert inputs */
- xori r3,r3, 0xffff /* complement led code, active low */
-#endif
-
- /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- lwz r4, +8(r1) /* restore r4 */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-log_err: /* output the error and hang the board ( for now ) */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r3, +8(r1) /* save a copy of error code */
- bl set_led /* set the led pattern */
- GET_GOT /* get GOT address in r14 */
- lwz r3,GOT(err_str) /* get address of string */
- bl post_puts /* output the warning string */
- lwz r3, +8(r1) /* get error code */
- addi r4, 0, 2 /* set disp length to 2 nibbles */
- bl disp_hex /* output the error code */
- lwz r3,GOT(end_str) /* get address of string */
- bl post_puts /* output the warning string */
-halt:
- b halt /* hang */
-
- /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-log_warn: /* output a warning, then continue with operations */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -16(r1) /* Save back chain and move SP */
- stw r0, +20(r1) /* Save link register */
- stw r3, +8(r1) /* save a copy of error code */
- stw r14, +12(r1) /* save a copy of r14 (used by GOT) */
-
- bl set_led /* set the led pattern */
- GET_GOT /* get GOT address in r14 */
- lwz r3,GOT(warn_str) /* get address of string */
- bl post_puts /* output the warning string */
- lwz r3, +8(r1) /* get error code */
- addi r4, 0, 2 /* set disp length to 2 nibbles */
- bl disp_hex /* output the error code */
- lwz r3,GOT(end_str) /* get address of string */
- bl post_puts /* output the warning string */
-
- addis r3, 0, 64 /* has a long delay */
- mtctr r3
-log_2:
- WATCHDOG_RESET /* this keeps dog from barking, */
- /* and takes time */
- bdnz log_2 /* loop till time expires */
-
- /* restore stack and return */
- lwz r0, +20(r1) /* Get saved link register */
- lwz r14, +12(r1) /* restore r14 */
- mtlr r0 /* Restore link register */
- addi r1, r1, +16 /* Remove frame from stack */
- blr /* Return to calling function */
-
-/*******************************************************************
- * temp_uart_init
- * Temporary UART initialization routine
- * Sets up UART0 to run at 9600N81 off of the internal clock.
- * R3-R4 are used.
- ******************************************************************/
-temp_uart_init:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -8(r1) /* Save back chain and move SP */
- stw r0, +12(r1) /* Save link register */
-
- addis r3, 0, 0xef60
- ori r3, r3, 0x0303 /* r3 = UART0_LCR */
- addi r4, 0, 0x83 /* n81 format, divisor regs enabled */
- stb r4, 0(r3)
-
- /* set baud rate to use internal clock,
- baud = (200e6/16)/31/42 = 9600 */
-
- addis r3, 0, 0xef60 /* Address of baud divisor reg */
- ori r3, r3, 0x0300 /* UART0_DLM */
- addi r4, 0, +42 /* uart baud divisor LSB = 93 */
- stb r4, 0(r3) /* baud = (200 /16)/14/93 */
-
- addi r3, r3, 0x0001 /* uart baud divisor addr */
- addi r4, 0, 0
- stb r4, 0(r3) /* Divisor Latch MSB = 0 */
-
- addis r3, 0, 0xef60
- ori r3, r3, 0x0303 /* r3 = UART0_LCR */
- addi r4, 0, 0x03 /* n81 format, tx/rx regs enabled */
- stb r4, 0(r3)
-
- /* output a few line feeds */
- addi r3, 0, '\n' /* load line feed */
- bl post_putc /* output the char */
- addi r3, 0, '\n' /* load line feed */
- bl post_putc /* output the char */
-
- /* restore stack and return */
- lwz r0, +12(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- addi r1, r1, +8 /* Remove frame from stack */
- blr /* Return to calling function */
-
-/**********************************************************************
- ** post_putc
- ** outputs charactor in R3
- ** r3 returns the error code ( -1 if there is an error )
- *********************************************************************/
-
-post_putc:
-
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -20(r1) /* Save back chain and move SP */
- stw r0, +24(r1) /* Save link register */
- stmw r29, 8(r1) /* save r29 - r31 on stack
- r31 - uart base address
- r30 - delay counter
- r29 - scratch reg */
-
- addis r31, 0, 0xef60 /* Point to uart base */
- ori r31, r31, 0x0300
- addis r30, 0, 152 /* Load about 10,000,000 ticks. */
-pputc_lp:
- lbz r29, 5(r31) /* Read Line Status Register */
- andi. r29, r29, 0x20 /* Check THRE status */
- bne thre_set /* Branch if FIFO empty */
- addic. r30, r30, -1 /* Decrement and check if empty. */
- bne pputc_lp /* Try, try again */
- addi r3, 0, -1 /* Load error code for timeout */
- b pputc_done /* Bail out with error code set */
-thre_set:
- stb r3, 0(r31) /* Store character to UART */
- addi r3, 0, 0 /* clear error code */
-pputc_done:
- lmw r29, 8(r1) /*restore r29 - r31 from stack */
- lwz r0, +24(r1) /* Get saved link register */
- addi r1, r1, +20 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/****************************************************************
- post_puts
- Accepts a null-terminated string pointed to by R3
- Outputs to the serial port until 0x00 is found.
- r3 returns the error code ( -1 if there is an error )
-*****************************************************************/
-post_puts:
-
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r31, 8(r1) /* save r31 - char pointer */
-
- addi r31, r3, 0 /* move pointer to R31 */
-pputs_nxt:
- lbz r3, 0(r31) /* Get next character */
- addic. r3, r3, 0 /* Check for zero */
- beq pputs_term /* bail out if zero */
- bl post_putc /* output the char */
- addic. r3, r3, 0 /* check for error */
- bne pputs_err
- addi r31, r31, 1 /* point to next char */
- b pputs_nxt /* loop till term */
-pputs_err:
- addi r3, 0, -1 /* set error code */
- b pputs_end /* were outa here */
-pputs_term:
- addi r3, 0, 1 /* set success code */
- /* restore stack and return */
-pputs_end:
- lwz r31, 8(r1) /* restore r27 - r31 from stack */
- lwz r0, +16(r1) /* Get saved link register */
- addi r1, r1, +12 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/********************************************************************
- ***** disp_hex
- ***** Routine to display a hex value from a register.
- ***** R3 is value to display
- ***** R4 is number of nibbles to display ie 2 for byte 8 for (long)word
- ***** Returns -1 in R3 if there is an error ( ie serial port hangs )
- ***** Returns 0 in R3 if no error
- *******************************************************************/
-disp_hex:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -16(r1) /* Save back chain and move SP */
- stw r0, +20(r1) /* Save link register */
- stmw r30, 8(r1) /* save r30 - r31 on stack */
- /* r31 output char */
- /* r30 uart base address */
- addi r30, 0, 8 /* Go through 8 nibbles. */
- addi r31, r3, 0
-pputh_nxt:
- rlwinm r31, r31, 4, 0, 31 /* Rotate next nibble into position */
- andi. r3, r31, 0x0f /* Get nibble. */
- addi r3, r3, 0x30 /* Add zero's ASCII code. */
- cmpwi r3, 0x03a
- blt pputh_out
- addi r3, r3, 0x07 /* 0x27 for lower case. */
-pputh_out:
- cmpw r30, r4
- bgt pputh_skip
- bl post_putc
- addic. r3, r3, 0 /* check for error */
- bne pputh_err
-pputh_skip:
- addic. r30, r30, -1
- bne pputh_nxt
- xor r3, r3, r3 /* Clear error code */
- b pputh_done
-pputh_err:
- addi r3, 0, -1 /* set error code */
-pputh_done:
- /* restore stack and return */
- lmw r30, 8(r1) /* restore r30 - r31 from stack */
- lwz r0, +20(r1) /* Get saved link register */
- addi r1, r1, +16 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
- * and
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <rtc.h>
-#include "errors.h"
-#include "dtt.h"
-
-/* for LM75 DTT POST test */
-#define DTT_READ_TEMP 0x0
-#define DTT_CONFIG 0x1
-#define DTT_TEMP_HYST 0x2
-#define DTT_TEMP_SET 0x3
-
-#if defined(CONFIG_RTC_M48T35A)
-void rtctest(void)
-{
- volatile uchar *tchar = (uchar*)(CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 9);
- struct rtc_time tmp;
-
- /* set up led code for RTC tests */
- log_stat(ERR_RTCG);
-
- /*
- * Do RTC battery test. The first write after power up
- * fails if battery is low.
- */
- *tchar = 0xaa;
- if ((*tchar ^ 0xaa) != 0x0) log_warn(ERR_RTCBAT);
- *tchar = 0x55; /* Reset test address */
-
- /*
- * Now lets check the validity of the values in the RTC.
- */
- rtc_get(&tmp);
- if ((tmp.tm_sec < 0) | (tmp.tm_sec > 59) |
- (tmp.tm_min < 0) | (tmp.tm_min > 59) |
- (tmp.tm_hour < 0) | (tmp.tm_hour > 23) |
- (tmp.tm_mday < 1 ) | (tmp.tm_mday > 31) |
- (tmp.tm_mon < 1 ) | (tmp.tm_mon > 12) |
- (tmp.tm_year < 2000) | (tmp.tm_year > 2500) |
- (tmp.tm_wday < 1 ) | (tmp.tm_wday > 7)) {
- log_warn(ERR_RTCTIM);
- rtc_reset();
- }
-
- /*
- * Now lets do a check to see if the NV RAM is there.
- */
- *tchar = 0xaa;
- if ((*tchar ^ 0xaa) != 0x0) log_err(ERR_RTCVAL);
- *tchar = 0x55; /* Reset test address */
-
-} /* rtctest() */
-#endif /* CONFIG_RTC_M48T35A */
-
-
-#ifdef CONFIG_DTT_LM75
-int dtt_test(int sensor)
-{
- short temp, trip, hyst;
-
- /* get values */
- temp = dtt_read(sensor, DTT_READ_TEMP) / 256;
- trip = dtt_read(sensor, DTT_TEMP_SET) / 256;
- hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256;
-
- /* check values */
- if ((hyst != (CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS)) ||
- (trip != CONFIG_SYS_DTT_MAX_TEMP) ||
- (temp < CONFIG_SYS_DTT_LOW_TEMP) || (temp > CONFIG_SYS_DTT_MAX_TEMP))
- return 1;
-
- return 0;
-} /* dtt_test() */
-#endif /* CONFIG_DTT_LM75 */
-
-/*****************************************/
-
-void post2(void)
-{
-#if defined(CONFIG_RTC_M48T35A)
- rtctest();
-#endif /* CONFIG_RTC_M48T35A */
-
-#ifdef CONFIG_DTT_LM75
- log_stat(ERR_TempG);
- if(dtt_test(2) != 0) log_warn(ERR_Ttest0);
- if(dtt_test(4) != 0) log_warn(ERR_Ttest1);
-#endif /* CONFIG_DTT_LM75 */
-} /* post2() */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#if defined(VXWORKS)
-#include <stdio.h>
-#include <string.h>
-#define CONFIG_SYS_DEF_EEPROM_ADDR 0xa0
-extern char iicReadByte(char, char);
-extern ulong_t crc32(unsigned char *, unsigned long);
-#else
-#include <common.h>
-#endif
-
-#include "vpd.h"
-
-/*
- * vpd_reader() - reads VPD data from I2C EEPROMS.
- * returns pointer to buffer or NULL.
- */
-static unsigned char *vpd_reader(unsigned char *buf, unsigned dev_addr,
- unsigned off, unsigned count)
-{
- unsigned offset = off; /* Calculated offset */
-
- /*
- * The main board EEPROM contains
- * SDRAM SPD in the first 128 bytes,
- * so skew the offset.
- */
- if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
- offset += SDRAM_SPD_DATA_SIZE;
-
- /* Try to read the I2C EEPROM */
-#if defined(VXWORKS)
- {
- int i;
-
- for (i = 0; i < count; ++i)
- buf[i] = iicReadByte(dev_addr, offset + i);
- }
-#else
- if (eeprom_read(dev_addr, offset, buf, count)) {
- printf("Failed to read %d bytes from VPD EEPROM 0x%x @ 0x%x\n",
- count, dev_addr, offset);
- return NULL;
- }
-#endif
-
- return buf;
-}
-
-
-/*
- * vpd_get_packet() - returns next VPD packet or NULL.
- */
-static vpd_packet_t *vpd_get_packet(vpd_packet_t * vpd_packet)
-{
- vpd_packet_t *packet = vpd_packet;
-
- if (packet != NULL) {
- if (packet->identifier == VPD_PID_TERM)
- return NULL;
- else
- packet = (vpd_packet_t *) ((char *) packet +
- packet->size + 2);
- }
-
- return packet;
-}
-
-
-/*
- * vpd_find_packet() - Locates and returns the specified
- * VPD packet or NULL on error.
- */
-static vpd_packet_t *vpd_find_packet(vpd_t * vpd, unsigned char ident)
-{
- vpd_packet_t *packet = (vpd_packet_t *) &vpd->packets;
-
- /* Guaranteed illegal */
- if (ident == VPD_PID_GI)
- return NULL;
-
- /* Scan tuples looking for a match */
- while ((packet->identifier != ident) &&
- (packet->identifier != VPD_PID_TERM))
- packet = vpd_get_packet(packet);
-
- /* Did we find it? */
- if ((packet->identifier) && (packet->identifier != ident))
- return NULL;
- return packet;
-}
-
-
-/*
- * vpd_is_valid() - Validates contents of VPD data
- * in I2C EEPROM. Returns 1 for
- * success or 0 for failure.
- */
-static int vpd_is_valid(unsigned dev_addr, unsigned char *buf)
-{
- unsigned num_bytes;
- vpd_packet_t *packet;
- vpd_t *vpd = (vpd_t *) buf;
- unsigned short stored_crc16, calc_crc16 = 0xffff;
-
- /* Check Eyecatcher */
- if (strncmp
- ((char *) (vpd->header.eyecatcher), VPD_EYECATCHER,
- VPD_EYE_SIZE) != 0) {
- unsigned offset = 0;
-
- if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
- offset += SDRAM_SPD_DATA_SIZE;
- printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr,
- offset);
-
- return 0;
- }
-
- /* Check Length */
- if (vpd->header.size > VPD_MAX_EEPROM_SIZE) {
- printf("Error: VPD EEPROM 0x%x contains bad size 0x%x\n",
- dev_addr, vpd->header.size);
- return 0;
- }
-
- /* Now find the termination packet */
- packet = vpd_find_packet(vpd, VPD_PID_TERM);
- if (packet == NULL) {
- printf("Error: VPD EEPROM 0x%x missing termination packet\n",
- dev_addr);
- return 0;
- }
-
- /* Calculate data size */
- num_bytes = (unsigned long) ((unsigned char *) packet -
- (unsigned char *) vpd +
- sizeof(vpd_packet_t));
-
- /* Find stored CRC and clear it */
- packet = vpd_find_packet(vpd, VPD_PID_CRC);
- if (packet == NULL) {
- printf("Error: VPD EEPROM 0x%x missing CRC\n", dev_addr);
- return 0;
- }
- memcpy(&stored_crc16, packet->data, sizeof(ushort));
- memset(packet->data, 0, sizeof(ushort));
-
- /* OK, lets calculate the CRC and check it */
-#if defined(VXWORKS)
- calc_crc16 = (0xffff & crc32(buf, num_bytes));
-#else
- calc_crc16 = (0xffff & crc32(0, buf, num_bytes));
-#endif
- /* Now restore the CRC */
- memcpy(packet->data, &stored_crc16, sizeof(ushort));
- if (stored_crc16 != calc_crc16) {
- printf("Error: VPD EEPROM 0x%x has bad CRC 0x%x\n",
- dev_addr, stored_crc16);
- return 0;
- }
-
- return 1;
-}
-
-
-/*
- * size_ok() - Check to see if packet size matches
- * size of data we want. Returns 1 for
- * good match or 0 for failure.
- */
-static int size_ok(vpd_packet_t *packet, unsigned long size)
-{
- if (packet->size != size) {
- printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
- return 0;
- }
- return 1;
-}
-
-
-/*
- * strlen_ok() - Check to see if packet size matches
- * strlen of the string we want to populate.
- * Returns 1 for valid length or 0 for failure.
- */
-static int strlen_ok(vpd_packet_t *packet, unsigned long length)
-{
- if (packet->size >= length) {
- printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
- return 0;
- }
- return 1;
-}
-
-
-/*
- * get_vpd_data() - populates the passed VPD structure 'vpdInfo'
- * with data obtained from the specified
- * I2C EEPROM 'dev_addr'. Returns 0 for
- * success or 1 for failure.
- */
-int vpd_get_data(unsigned char dev_addr, VPD *vpdInfo)
-{
- unsigned char buf[VPD_EEPROM_SIZE];
- vpd_t *vpd = (vpd_t *) buf;
- vpd_packet_t *packet;
-
- if (vpdInfo == NULL)
- return 1;
-
- /*
- * Fill vpdInfo with 0s to blank out
- * unused fields, fill vpdInfo->ethAddrs
- * with all 0xffs so that other's code can
- * determine how many real Ethernet addresses
- * there are. OUIs starting with 0xff are
- * broadcast addresses, and would never be
- * permantely stored.
- */
- memset((void *) vpdInfo, 0, sizeof(VPD));
- memset((void *) &vpdInfo->ethAddrs, 0xff, sizeof(vpdInfo->ethAddrs));
- vpdInfo->_devAddr = dev_addr;
-
- /* Read the minimum size first */
- if (vpd_reader(buf, dev_addr, 0, VPD_EEPROM_SIZE) == NULL)
- return 1;
-
- /* Check validity of VPD data */
- if (!vpd_is_valid(dev_addr, buf)) {
- printf("VPD Data is INVALID!\n");
- return 1;
- }
-
- /*
- * Walk all the packets and populate
- * the VPD info structure.
- */
- packet = (vpd_packet_t *) &vpd->packets;
- do {
- switch (packet->identifier) {
- case VPD_PID_GI:
- printf("Error: Illegal VPD value\n");
- break;
- case VPD_PID_PID:
- if (strlen_ok(packet, MAX_PROD_ID)) {
- strncpy(vpdInfo->productId,
- (char *) (packet->data),
- packet->size);
- }
- break;
- case VPD_PID_REV:
- if (size_ok(packet, sizeof(char)))
- vpdInfo->revisionId = *packet->data;
- break;
- case VPD_PID_SN:
- if (size_ok(packet, sizeof(unsigned long))) {
- memcpy(&vpdInfo->serialNum,
- packet->data,
- sizeof(unsigned long));
- }
- break;
- case VPD_PID_MANID:
- if (size_ok(packet, sizeof(unsigned char)))
- vpdInfo->manuID = *packet->data;
- break;
- case VPD_PID_PCO:
- if (size_ok(packet, sizeof(unsigned long))) {
- memcpy(&vpdInfo->configOpt,
- packet->data,
- sizeof(unsigned long));
- }
- break;
- case VPD_PID_SYSCLK:
- if (size_ok(packet, sizeof(unsigned long)))
- memcpy(&vpdInfo->sysClk,
- packet->data,
- sizeof(unsigned long));
- break;
- case VPD_PID_SERCLK:
- if (size_ok(packet, sizeof(unsigned long)))
- memcpy(&vpdInfo->serClk,
- packet->data,
- sizeof(unsigned long));
- break;
- case VPD_PID_FLASH:
- if (size_ok(packet, 9)) { /* XXX - hardcoded,
- padding in struct */
- memcpy(&vpdInfo->flashCfg, packet->data, 9);
- }
- break;
- case VPD_PID_ETHADDR:
- memcpy(vpdInfo->ethAddrs, packet->data, packet->size);
- break;
- case VPD_PID_POTS:
- if (size_ok(packet, sizeof(char)))
- vpdInfo->numPOTS = (unsigned) *packet->data;
- break;
- case VPD_PID_DS1:
- if (size_ok(packet, sizeof(char)))
- vpdInfo->numDS1 = (unsigned) *packet->data;
- case VPD_PID_GAL:
- case VPD_PID_CRC:
- case VPD_PID_TERM:
- break;
- default:
- printf("Warning: Found unknown VPD packet ID 0x%x\n",
- packet->identifier);
- break;
- }
- } while ((packet = vpd_get_packet(packet)));
-
- return 0;
-}
-
-
-/*
- * vpd_init() - Initialize default VPD environment
- */
-int vpd_init(unsigned char dev_addr)
-{
- return 0;
-}
-
-
-/*
- * vpd_print() - Pretty print the VPD data.
- */
-void vpd_print(VPD *vpdInfo)
-{
- const char *const sp = "";
- const char *const sfmt = "%4s%-20s: \"%s\"\n";
- const char *const cfmt = "%4s%-20s: '%c'\n";
- const char *const dfmt = "%4s%-20s: %ld\n";
- const char *const hfmt = "%4s%-20s: %08lX\n";
- const char *const dsfmt = "%4s%-20s: %d\n";
- const char *const hsfmt = "%4s%-20s: %04X\n";
- const char *const dhfmt = "%4s%-20s: %ld (%lX)\n";
-
- printf("VPD read from I2C device: %02X\n", vpdInfo->_devAddr);
-
- if (vpdInfo->productId[0])
- printf(sfmt, sp, "Product ID", vpdInfo->productId);
- else
- printf(sfmt, sp, "Product ID", "UNKNOWN");
-
- if (vpdInfo->revisionId)
- printf(cfmt, sp, "Revision ID", vpdInfo->revisionId);
-
- if (vpdInfo->serialNum)
- printf(dfmt, sp, "Serial Number", vpdInfo->serialNum);
-
- if (vpdInfo->manuID)
- printf(dfmt, sp, "Manufacture ID", (long) vpdInfo->manuID);
-
- if (vpdInfo->configOpt)
- printf(hfmt, sp, "Configuration", vpdInfo->configOpt);
-
- if (vpdInfo->sysClk)
- printf(dhfmt, sp, "System Clock", vpdInfo->sysClk,
- vpdInfo->sysClk);
-
- if (vpdInfo->serClk)
- printf(dhfmt, sp, "Serial Clock", vpdInfo->serClk,
- vpdInfo->serClk);
-
- if (vpdInfo->numPOTS)
- printf(dfmt, sp, "Number of POTS lines", vpdInfo->numPOTS);
-
- if (vpdInfo->numDS1)
- printf(dfmt, sp, "Number of DS1s", vpdInfo->numDS1);
-
- /* Print Ethernet Addresses */
- if (vpdInfo->ethAddrs[0][0] != 0xff) {
- int i, j;
-
- printf("%4sEtherNet Address(es): ", sp);
- for (i = 0; i < MAX_ETH_ADDRS; i++) {
- if (vpdInfo->ethAddrs[i][0] != 0xff) {
- for (j = 0; j < 6; j++) {
- printf("%02X",
- vpdInfo->ethAddrs[i][j]);
- if (((j + 1) % 6) != 0)
- printf(":");
- else
- printf(" ");
- }
- if (((i + 1) % 3) == 0)
- printf("\n%24s: ", sp);
- }
- }
- printf("\n");
- }
-
- if (vpdInfo->flashCfg.mfg && vpdInfo->flashCfg.dev) {
- printf("Main Flash Configuration:\n");
- printf(hsfmt, sp, "Manufacture ID", vpdInfo->flashCfg.mfg);
- printf(hsfmt, sp, "Device ID", vpdInfo->flashCfg.dev);
- printf(dsfmt, sp, "Device Width", vpdInfo->flashCfg.devWidth);
- printf(dsfmt, sp, "Num. Devices", vpdInfo->flashCfg.numDevs);
- printf(dsfmt, sp, "Num. Columns", vpdInfo->flashCfg.numCols);
- printf(dsfmt, sp, "Column Width", vpdInfo->flashCfg.colWidth);
- printf(dsfmt, sp, "WE Data Width",
- vpdInfo->flashCfg.weDataWidth);
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _VPD_H_
-#define _VPD_H_
-
-/*
- * Main Flash Configuration.
- */
-typedef struct flashCfg_s {
- unsigned short mfg; /* Manufacture ID */
- unsigned short dev; /* Device ID */
- unsigned char devWidth; /* Device Width */
- unsigned char numDevs; /* Number of devices */
- unsigned char numCols; /* Number of columns */
- unsigned char colWidth; /* Width of a column */
- unsigned char weDataWidth; /* Write/Erase Data Width */
-} flashCfg_t;
-
-/*
- * Vital Product Data - VPD
- */
-#define MAX_PROD_ID 15
-#define MAX_ETH_ADDRS 10
-typedef unsigned char EthAddr[6];
-typedef struct vpd {
- unsigned char _devAddr; /* Device address during read */
- char productId[MAX_PROD_ID]; /* Product ID */
- char revisionId; /* Revision ID as a char */
- unsigned long serialNum; /* Serial number */
- unsigned char manuID; /* Manufact ID - byte int */
- unsigned long configOpt; /* Config Option - bit field */
- unsigned long sysClk; /* System clock in Hertz */
- unsigned long serClk; /* Ext. clock in Hertz */
- flashCfg_t flashCfg; /* Flash configuration */
- unsigned long numPOTS; /* Number of POTS lines */
- unsigned long numDS1; /* Number of DS1 circuits */
- EthAddr ethAddrs[MAX_ETH_ADDRS]; /* Ethernet MAC, 1st = craft */
-} VPD;
-
-
-#define VPD_MAX_EEPROM_SIZE 512 /* Max size VPD EEPROM */
-#define SDRAM_SPD_DATA_SIZE 128 /* Size SPD in VPD EEPROM */
-
-/*
- * PIDs - Packet Identifiers
- */
-#define VPD_PID_GI 0x0 /* Guaranted Illegal */
-#define VPD_PID_PID 0x1 /* Product Identifier */
-#define VPD_PID_REV 0x2 /* Product Revision */
-#define VPD_PID_SN 0x3 /* Serial Number */
-#define VPD_PID_MANID 0x4 /* Manufacture ID */
-#define VPD_PID_PCO 0x5 /* Product configuration */
-#define VPD_PID_SYSCLK 0x6 /* System Clock */
-#define VPD_PID_SERCLK 0x7 /* Ser. Clk. Speed in Hertz */
-#define VPD_PID_CRC 0x8 /* VPD CRC */
-#define VPD_PID_FLASH 0x9 /* Flash Configuration */
-#define VPD_PID_ETHADDR 0xA /* Ethernet Address(es) */
-#define VPD_PID_GAL 0xB /* Galileo Switch Config */
-#define VPD_PID_POTS 0xC /* Number of POTS Lines */
-#define VPD_PID_DS1 0xD /* Number of DS1s */
-#define VPD_PID_TERM 0xFF /* Termination packet */
-
-/*
- * VPD - Eyecatcher/Magic
- */
-#define VPD_EYECATCHER "W7O"
-#define VPD_EYE_SIZE 3
-typedef struct vpd_header {
- unsigned char eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "W7O" */
- unsigned short size __attribute__((packed)); /* size of EEPROM */
-} vpd_header_t;
-
-
-#define VPD_DATA_SIZE (VPD_MAX_EEPROM_SIZE - SDRAM_SPD_DATA_SIZE - \
- sizeof(vpd_header_t))
-typedef struct vpd_s {
- vpd_header_t header;
- unsigned char packets[VPD_DATA_SIZE];
-} vpd_t;
-
-typedef struct vpd_packet {
- unsigned char identifier;
- unsigned char size;
- unsigned char data[1];
-} vpd_packet_t;
-
-/*
- * VPD configOpt bit mask
- */
-#define VPD_HAS_BBRAM 0x1 /* Battery backed SRAM */
-#define VPD_HAS_RTC 0x2 /* Battery backed RTC */
-#define VPD_HAS_EXT_SER_CLK 0x4 /* External serial clock */
-#define VPD_HAS_SER_TRANS_1 0x8 /* COM1 transceiver */
-#define VPD_HAS_SER_TRANS_2 0x10 /* COM2 transceiver */
-#define VPD_HAS_CRAFT_PHY 0x20 /* CRAFT Ethernet */
-#define VPD_HAS_DTT_1 0x40 /* I2C Digital therm. #1 */
-#define VPD_HAS_DTT_2 0x80 /* I2C Digital therm. #2 */
-#define VPD_HAS_1000_UP_LASER 0x100 /* GMM - 1000Mbit Uplink */
-#define VPD_HAS_70KM_UP_LASER 0x200 /* CMM - 70KM Uplink laser */
-#define VPD_HAS_2_UPLINKS 0x400 /* CMM - 2 uplink lasers */
-#define VPD_HAS_FPGA 0x800 /* Has 1 or more FPGAs */
-#define VPD_HAS_DFA 0x1000 /* CLM - Has 2 Fiber Inter. */
-#define VPD_HAS_GAL_SWITCH 0x2000 /* GMM - Has a Gal switch */
-#define VPD_HAS_POTS_LINES 0x4000 /* GMM - Has POTS lines */
-#define VPD_HAS_DS1_CHANNELS 0x8000 /* GMM - Has DS1 channels */
-#define VPD_HAS_CABLE_RETURN 0x10000 /* GBM/GBR - Cable ret. path */
-
-#define VPD_EEPROM_SIZE (256 - SDRAM_SPD_DATA_SIZE) /* Size EEPROM */
-
-extern int vpd_get_data(unsigned char dev_addr, VPD *vpd);
-extern void vpd_print(VPD *vpdInfo);
-
-#endif /* _VPD_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include "w7o.h"
-#include <asm/processor.h>
-
-#include "vpd.h"
-#include "errors.h"
-#include <watchdog.h>
-
-unsigned long get_dram_size (void);
-void sdram_init(void);
-
-/* ------------------------------------------------------------------------- */
-
-int board_early_init_f (void)
-{
-#if defined(CONFIG_W7OLMG)
- /*
- * Setup GPIO pins - reset devices.
- */
- out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
- out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
- out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
- */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
-
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
- INT0 highest priority */
-
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
-#elif defined(CONFIG_W7OLMC)
- /*
- * Setup GPIO pins
- */
- out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
- out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
- out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
- */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
-
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
- INT0 highest priority */
-
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
-#else /* Unknown */
-# error "Unknown W7O board configuration"
-#endif
-
- WATCHDOG_RESET (); /* Reset the watchdog */
- temp_uart_init (); /* init the uart for debug */
- WATCHDOG_RESET (); /* Reset the watchdog */
- test_led (); /* test the LEDs */
- test_sdram (get_dram_size ()); /* test the dram */
- log_stat (ERR_POST1); /* log status,post1 complete */
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- VPD vpd;
-
- puts ("Board: ");
-
- /* VPD data present in I2C EEPROM */
- if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
- /*
- * Known board type.
- */
- if (vpd.productId[0] &&
- ((strncmp (vpd.productId, "GMM", 3) == 0) ||
- (strncmp (vpd.productId, "CMM", 3) == 0))) {
-
- /* Output board information on startup */
- printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
- return (0);
- }
- }
-
- puts ("### Unknown HW ID - assuming NOTHING\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- /*
- * ToDo: Move the asm init routine sdram_init() to this C file,
- * or even better use some common ppc4xx code available
- * in arch/powerpc/cpu/ppc4xx
- */
- sdram_init();
-
- return get_dram_size ();
-}
-
-unsigned long get_dram_size (void)
-{
- int tmp, i, regs[4];
- int size = 0;
-
- /* Get bank Size registers */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */
- regs[0] = mfdcr (SDRAM0_CFGDATA);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */
- regs[1] = mfdcr (SDRAM0_CFGDATA);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */
- regs[2] = mfdcr (SDRAM0_CFGDATA);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */
- regs[3] = mfdcr (SDRAM0_CFGDATA);
-
- /* compute the size, add each bank if enabled */
- for (i = 0; i < 4; i++) {
- if (regs[i] & 0x0001) { /* if enabled, */
- tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
- tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
- size += tmp;
- }
- }
-
- return size;
-}
-
-int misc_init_f (void)
-{
- return 0;
-}
-
-static void w7o_env_init (VPD * vpd)
-{
- /*
- * Read VPD
- */
- if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
- return;
-
- /*
- * Known board type.
- */
- if (vpd->productId[0] &&
- ((strncmp (vpd->productId, "GMM", 3) == 0) ||
- (strncmp (vpd->productId, "CMM", 3) == 0))) {
- char buf[30];
- char *eth;
- char *serial = getenv ("serial#");
- char *ethaddr = getenv ("ethaddr");
-
- /* Set 'serial#' envvar if serial# isn't set */
- if (!serial) {
- sprintf (buf, "%s-%ld", vpd->productId,
- vpd->serialNum);
- setenv ("serial#", buf);
- }
-
- /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
- eth = (char *)(vpd->ethAddrs[0]);
- if (ethaddr
- && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) {
- /* Now setup ethaddr */
- sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
- eth[0], eth[1], eth[2], eth[3], eth[4],
- eth[5]);
- setenv ("ethaddr", buf);
- }
- }
-} /* w7o_env_init() */
-
-
-int misc_init_r (void)
-{
- VPD vpd; /* VPD information */
-
-#if defined(CONFIG_W7OLMG)
- unsigned long greg; /* GPIO Register */
-
- greg = in32 (PPC405GP_GPIO0_OR);
-
- /*
- * XXX - Unreset devices - this should be moved into VxWorks driver code
- */
- greg |= 0x41800000L; /* SAM, PHY, Galileo */
-
- out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
-#endif /* CONFIG_W7OLMG */
-
- /*
- * Initialize W7O environment variables
- */
- w7o_env_init (&vpd);
-
- /*
- * Initialize the FPGA(s).
- */
- if (init_fpga () == 0)
- test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
-
- /* More POST testing. */
- post2 ();
-
- /* Done with hardware initialization and POST. */
- log_stat (ERR_POSTOK);
-
- /* Call silly, fail safe boot init routine */
- init_fsboot ();
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _W7O_H_
-#define _W7O_H_
-#include <config.h>
-
-/* AMCC 405GP PowerPC GPIO registers */
-#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */
-#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
-#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
-#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
-
-/* LMG FPGA <=> CPU GPIO signals */
-#define LMG_XCV_INIT 0x10000000L
-#define LMG_XCV_PROG 0x04000000L
-#define LMG_XCV_DONE 0x00400000L
-#define LMG_XCV_CNFG_0 0x08000000L
-#define LMG_XCV_IRQ_0 0x0L
-
-/* LMC FPGA <=> CPU GPIO signals */
-#define LMC_XCV_INIT 0x00800000L
-#define LMC_XCV_PROG 0x40000000L
-#define LMC_XCV_DONE 0x01000000L
-#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */
-#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */
-#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */
-#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */
-#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */
-#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */
-
-
-/*
- * Setup FPGA <=> GPIO mappings
- */
-#if defined(CONFIG_W7OLMG)
-# define GPIO_XCV_INIT LMG_XCV_INIT
-# define GPIO_XCV_PROG LMG_XCV_PROG
-# define GPIO_XCV_DONE LMG_XCV_DONE
-# define GPIO_XCV_CNFG LMG_XCV_CNFG_0
-# define GPIO_XCV_IRQ LMG_XCV_IRQ_0
-# define GPIO_GPIO_1 0x40000000L
-# define GPIO_GPIO_6 0x02000000L
-# define GPIO_GPIO_7 0x01000000L
-# define GPIO_GPIO_8 0x00800000L
-#elif defined(CONFIG_W7OLMC)
-# define GPIO_XCV_INIT LMC_XCV_INIT
-# define GPIO_XCV_PROG LMC_XCV_PROG
-# define GPIO_XCV_DONE LMC_XCV_DONE
-# define GPIO_XCV_CNFG LMC_XCV_CNFG_0
-# define GPIO_XCV_IRQ LMC_XCV_IRQ_0
-#else
-# error "Unknown W7O board configuration"
-#endif
-
-/* Power On Self Tests */
-extern void post2(void);
-extern int test_led(void);
-extern int test_sdram(unsigned long size);
-extern void test_fpga(unsigned short *daddr);
-
-/* FGPA */
-extern int init_fpga(void);
-
-/* Misc */
-extern int temp_uart_init(void);
-extern void init_fsboot(void);
-
-#endif /* _W7O_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * W7O board level hardware watchdog.
- */
-#include <common.h>
-#include <config.h>
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-
-void hw_watchdog_reset(void)
-{
- volatile ushort *hwd = (ushort *)(CONFIG_SYS_W7O_EBC_PB7CR & 0xfff00000);
-
- /*
- * Read the LMG's hwd register and toggle the
- * watchdog bit to reset it. On the LMC, just
- * reading it is enough, but toggling the bit
- * doen't hurt either.
- */
- *hwd = *hwd ^ 0x8000;
-
-} /* hw_watchdog_reset() */
-
-#endif /* CONFIG_HW_WATCHDOG */
Infinite write loop on address range
config CMD_MEMTEST
- bool "crc32"
+ bool "memtest"
help
Simple RAM read/write test.
return 0;
}
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int init_func_ram(void)
{
#ifdef CONFIG_BOARD_TYPES
/* Get the top of usable RAM */
__weak ulong board_get_usable_ram_top(ulong total_size)
{
+#ifdef CONFIG_SYS_SDRAM_BASE
+ /*
+ * Detect whether we have so much RAM it goes past the end of our
+ * 32-bit address space. If so, clip the usable RAM so it doesn't.
+ */
+ if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
+ /*
+ * Will wrap back to top of 32-bit space when reservations
+ * are made.
+ */
+ return 0;
+#endif
return gd->ram_top;
}
return 0;
}
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int setup_board_part1(void)
{
bd_t *bd = gd->bd;
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
+#if defined(CONFIG_M68K) && defined(CONFIG_PCI)
+ bd->bi_pcifreq = gd->pci_clk;
+#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+ bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
+ bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
+ bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
+#endif
return 0;
}
{
#ifdef CONFIG_SYS_TEXT_BASE
gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
+#ifdef CONFIG_M68K
+ /*
+ * On all ColdFire arch cpu, monitor code starts always
+ * just after the default vector table location, so at 0x400
+ */
+ gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
+#endif
#endif
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
#endif
#ifdef CONFIG_FSL_ESDHC
get_clocks,
+#endif
+#ifdef CONFIG_M68K
+ get_clocks,
#endif
env_init, /* initialize environment */
#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
#if defined(CONFIG_MPC83xx)
prt_83xx_rsr,
#endif
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
checkcpu,
#endif
print_cpuinfo, /* display cpu info (and speed) */
#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
dram_init, /* configure available RAM banks */
#endif
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
init_func_ram,
#endif
#ifdef CONFIG_POST
reserve_stacks,
setup_dram_config,
show_dram_config,
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
setup_board_part1,
INIT_FUNC_WATCHDOG_RESET
setup_board_part2,
* Transfer execution from Flash to RAM by calculating the address
* of the in-RAM copy of board_init_r() and calling it
*/
- (board_init_r + gd->reloc_off)(gd, gd->relocaddr);
+ (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
/* NOTREACHED - board_init_r() does not return */
hang();
return 0;
}
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int initr_trap(void)
{
/*
* Setup trap handlers
*/
+#if defined(CONFIG_PPC)
trap_init(gd->relocaddr);
-
+#else
+ trap_init(CONFIG_SYS_SDRAM_BASE);
+#endif
return 0;
}
#endif
#ifdef CONFIG_NEEDS_MANUAL_RELOC
initr_manual_reloc_cmdtable,
#endif
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
initr_trap,
#endif
#ifdef CONFIG_ADDR_MAP
initr_flash,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
#if defined(CONFIG_ARM) || defined(CONFIG_AVR32)
initr_enable_interrupts,
#endif
-#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
+#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) \
+ || defined(CONFIG_M68K)
timer_init, /* initialize timer */
#endif
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
return CMD_RET_USAGE;
}
- if (state != BOOTM_STATE_START && images.state >= state) {
+ if (((state & BOOTM_STATE_START) != BOOTM_STATE_START) &&
+ images.state >= state) {
printf("Trying to execute a command out of order\n");
return CMD_RET_USAGE;
}
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
char *sload, *saddr;
+ const char *ep = getenv("autostart");
/* -------------------------------------------------- */
int rcode = 0;
else
addr = load_elf_image_shdr(addr);
+ if (ep && !strcmp(ep, "no"))
+ return rcode;
+
printf("## Starting application at 0x%08lx ...\n", addr);
/*
/* extract disk guid */
s = str;
- tok = strsep(&s, ";");
- val = extract_val(tok, "uuid_disk");
+ val = extract_val(str, "uuid_disk");
if (!val) {
+#ifdef CONFIG_RANDOM_UUID
+ *str_disk_guid = malloc(UUID_STR_LEN + 1);
+ gen_rand_uuid_str(*str_disk_guid, UUID_STR_FORMAT_STD);
+#else
free(str);
return -2;
+#endif
+ } else {
+ val = strsep(&val, ";");
+ if (extract_env(val, &p))
+ p = val;
+ *str_disk_guid = strdup(p);
+ free(val);
+ /* Move s to first partition */
+ strsep(&s, ";");
}
- if (extract_env(val, &p))
- p = val;
- *str_disk_guid = strdup(p);
- free(val);
-
if (strlen(s) == 0)
return -3;
/* uuid */
val = extract_val(tok, "uuid");
- if (!val) { /* 'uuid' is mandatory */
- errno = -4;
- goto err;
- }
- if (extract_env(val, &p))
- p = val;
- if (strlen(p) >= sizeof(parts[i].uuid)) {
- printf("Wrong uuid format for partition %d\n", i);
+ if (!val) {
+ /* 'uuid' is optional if random uuid's are enabled */
+#ifdef CONFIG_RANDOM_UUID
+ gen_rand_uuid_str(parts[i].uuid, UUID_STR_FORMAT_STD);
+#else
errno = -4;
goto err;
+#endif
+ } else {
+ if (extract_env(val, &p))
+ p = val;
+ if (strlen(p) >= sizeof(parts[i].uuid)) {
+ printf("Wrong uuid format for partition %d\n", i);
+ errno = -4;
+ goto err;
+ }
+ strcpy((char *)parts[i].uuid, p);
+ free(val);
}
- strcpy((char *)parts[i].uuid, p);
- free(val);
-
/* name */
val = extract_val(tok, "name");
if (!val) { /* name is mandatory */
}
/* save partitions layout to disk */
- gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count);
+ ret = gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count);
free(str_disk_guid);
free(partitions);
- return 0;
+ return ret;
}
/**
U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
"Use the UMS [User Mass Storage]",
- "ums <USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n"
+ "<USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n"
" devtype defaults to mmc"
);
U_BOOT_CMD(ytrace, 2, 0, do_ytrace,
"show/set yaffs trace mask",
- "ytrace [new_mask] show/set yaffs trace mask");
+ "[new_mask] show/set yaffs trace mask");
U_BOOT_CMD(ydevls, 1, 0, do_ydevls,
"list yaffs mount points", "list yaffs mount points");
U_BOOT_CMD(ydevconfig, 5, 0, do_ydevconfig,
"configure yaffs mount point",
- "ydevconfig mtpoint mtd_id start_block end_block configures a yaffs2 mount point");
+ "mtpoint mtd_id start_block end_block configures a yaffs2 mount point");
U_BOOT_CMD(ymount, 2, 0, do_ymount,
- "mount yaffs", "ymount mtpoint mounts a yaffs2 mount point");
+ "mount yaffs", "mtpoint mounts a yaffs2 mount point");
U_BOOT_CMD(yumount, 2, 0, do_yumount,
- "unmount yaffs", "yunmount mtpoint unmounts a yaffs2 mount point");
+ "unmount yaffs", "mtpoint unmounts a yaffs2 mount point");
-U_BOOT_CMD(yls, 3, 0, do_yls, "yaffs ls", "yls [-l] dirname");
+U_BOOT_CMD(yls, 3, 0, do_yls, "yaffs ls", "[-l] dirname");
U_BOOT_CMD(yrd, 2, 0, do_yrd,
- "read file from yaffs", "yrd path read file from yaffs");
+ "read file from yaffs", "path read file from yaffs");
U_BOOT_CMD(ywr, 4, 0, do_ywr,
"write file to yaffs",
- "ywr filename value num_vlues write values to yaffs file");
+ "filename value num_vlues write values to yaffs file");
U_BOOT_CMD(yrdm, 3, 0, do_yrdm,
"read file to memory from yaffs",
- "yrdm filename offset reads yaffs file into memory");
+ "filename offset reads yaffs file into memory");
U_BOOT_CMD(ywrm, 4, 0, do_ywrm,
"write file from memory to yaffs",
- "ywrm filename offset size writes memory to yaffs file");
+ "filename offset size writes memory to yaffs file");
U_BOOT_CMD(ymkdir, 2, 0, do_ymkdir,
- "YAFFS mkdir", "ymkdir dir create a yaffs directory");
+ "YAFFS mkdir", "dir create a yaffs directory");
U_BOOT_CMD(yrmdir, 2, 0, do_yrmdir,
- "YAFFS rmdir", "yrmdir dirname removes a yaffs directory");
+ "YAFFS rmdir", "dirname removes a yaffs directory");
-U_BOOT_CMD(yrm, 2, 0, do_yrm, "YAFFS rm", "yrm path removes a yaffs file");
+U_BOOT_CMD(yrm, 2, 0, do_yrm, "YAFFS rm", "path removes a yaffs file");
U_BOOT_CMD(ymv, 4, 0, do_ymv,
"YAFFS mv",
- "ymv old_path new_path moves/rename files within a yaffs mount point");
+ "old_path new_path moves/rename files within a yaffs mount point");
debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start,
mem_malloc_end);
-
- memset((void *)mem_malloc_start, 0, size);
-
+#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
+ memset((void *)mem_malloc_start, 0x0, size);
+#endif
malloc_bin_reloc();
}
/* check if expand_top called, in which case don't need to clear */
+#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
#if MORECORE_CLEARS
mchunkptr oldtop = top;
INTERNAL_SIZE_T oldtopsize = chunksize(top);
+#endif
#endif
Void_t* mem = mALLOc (sz);
csz = chunksize(p);
+#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
#if MORECORE_CLEARS
if (p == oldtop && csz > oldtopsize)
{
/* clear only the bytes from non-freshly-sbrked memory */
csz = oldtopsize;
}
+#endif
#endif
MALLOC_ZERO(mem, csz - SIZE_SZ);
lcd_puts(buf);
}
+
+static int do_lcd_setcursor(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned int col, row;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ col = simple_strtoul(argv[1], NULL, 10);
+ row = simple_strtoul(argv[2], NULL, 10);
+ lcd_position_cursor(col, row);
+
+ return 0;
+}
+
+static int do_lcd_puts(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ lcd_puts(argv[1]);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ setcurs, 3, 1, do_lcd_setcursor,
+ "set cursor position within screen",
+ " <col> <row> in character"
+);
+
+U_BOOT_CMD(
+ lcdputs, 2, 1, do_lcd_puts,
+ "print string on lcd-framebuffer",
+ " <string>"
+);
+
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-olinuxino-lime.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
-+S:CONFIG_MMC0_CD_PIN="PG1"
-+S:CONFIG_MMC1_CD_PIN="PG13"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_MMC0_CD_PIN="PG1"
+CONFIG_MMC1_CD_PIN="PG13"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-lime2.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-lime.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_FDTFILE="sun7i-a20-olinuxino-micro.dtb"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_VIDEO_VGA=y
-+S:CONFIG_MMC0_CD_PIN="PH1"
-+S:CONFIG_MMC3_CD_PIN="PH11"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC3_CD_PIN="PH11"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb"
CONFIG_USB1_VBUS_PIN="PG13"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_B4860QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_B4860QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_B4860QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_B4860QDS=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_BC3450=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_BSC9131RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_BSC9131RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_BSC9131RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_BSC9131RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_BSC9132QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_BSC9132QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_BSC9132QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-bananapi.dtb"
CONFIG_GMAC_TX_DELAY=3
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_USB1_VBUS_PIN="PH0"
CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_GMAC_TX_DELAY=3
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_C29XPCIE=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_C29XPCIE=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31s-cs908.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
# Ethernet phy power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
# Wifi power
-+S:CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3300
# No Vbus gpio for either usb
-+S:CONFIG_USB1_VBUS_PIN=""
-+S:CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
CONFIG_VIDEO_LCD_SPI_MOSI="PA2"
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=240
-+S:CONFIG_DRAM_ZQ=251
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=240
+CONFIG_DRAM_ZQ=251
# Wifi power
-+S:CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3300
# No Vbus gpio for usb1
-+S:CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB1_VBUS_PIN=""
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-cubieboard.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
CONFIG_VIDEO_VGA=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_FDTFILE="sun6i-a31-hummingbird.dtb"
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=312
-+S:CONFIG_DRAM_ZQ=251
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=312
+CONFIG_DRAM_ZQ=251
# Wifi power
-+S:CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3300
# Vbus gpio for usb1
-+S:CONFIG_USB1_VBUS_PIN="PH24"
+CONFIG_USB1_VBUS_PIN="PH24"
# No Vbus gpio for usb2
-+S:CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW=n
CONFIG_VIDEO_LCD_PANEL_LVDS=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v1.2.dtb"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="axp_drivebus"
+CONFIG_USB0_VBUS_DET="axp_vbus_detect"
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN8I=y
-+S:CONFIG_DRAM_CLK=432
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I=y
+CONFIG_DRAM_CLK=432
# zq = 0xf74a
-+S:CONFIG_DRAM_ZQ=63306
+CONFIG_DRAM_ZQ=63306
# Wifi power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP
-+S:CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v5.dtb"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="axp_drivebus"
+CONFIG_USB0_VBUS_DET="axp_vbus_detect"
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN8I=y
-+S:CONFIG_DRAM_CLK=480
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I=y
+CONFIG_DRAM_CLK=480
# zq = 0xf777
-+S:CONFIG_DRAM_ZQ=63351
+CONFIG_DRAM_ZQ=63351
# Wifi power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP
-+S:CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_AXP221_ALDO1_VOLT=3000
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_JSE=y
CONFIG_FDTFILE="sun7i-a20-pcduino3-nano.dtb"
CONFIG_GMAC_TX_DELAY=3
CONFIG_USB1_VBUS_PIN="PH11"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=122
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=122
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=122
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=122
+CONFIG_DRAM_EMR1=4
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
CONFIG_OF_CONTROL=y
CONFIG_OF_SEPARATE=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=122
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=122
+CONFIG_DRAM_EMR1=4
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-pcduino.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
--- /dev/null
+# The MK808C is an Allwinner based Android TV dongle.
+#
+# It features a A20 SOC, 1G RAM, 8GB NAND, HDMI out, A/V out,
+# 1 USB A, 1 USB mini OTG, Bluetooth and Wireless LAN.
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-mk808c.dtb"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC83xx=y
-+S:CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC8313ERDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC83xx=y
-+S:CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC8313ERDB=y
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_USB_KEYBOARD=n
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_USB_KEYBOARD=n
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=122
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=122
# Wifi power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-marsboard.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
CONFIG_VIDEO_VGA=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
--- /dev/null
+# The Mele I7 is a Allwinner based Android TV box.
+#
+# It features a A31 SOC, 1G RAM, 8GB NAND, HDMI out, A/V out,
+# SPDIF, IrDA, 3 USB A, 1 USB micro OTG and Wireless LAN.
+#
+# For more details see: http://linux-sunxi.org/Mele_I7
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
+CONFIG_FDTFILE="sun6i-a31-i7.dtb"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=312
+CONFIG_DRAM_ZQ=120
+# The Mele I7 uses 3.3V for general IO
+CONFIG_AXP221_DCDC1_VOLT=3300
+# Ethernet phy power
+CONFIG_AXP221_DLDO1_VOLT=3300
+# USB hub power
+CONFIG_AXP221_DLDO4_VOLT=3300
+# Wifi power
+CONFIG_AXP221_ALDO1_VOLT=3300
+# Vbus gpio for usb1
+CONFIG_USB1_VBUS_PIN="PC27"
+# No Vbus gpio for usb2
+CONFIG_USB2_VBUS_PIN=""
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-m3.dtb"
CONFIG_VIDEO_VGA=y
-+S:CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-+S:CONFIG_MMC0_CD_PIN="PH1"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,USB_EHCI,STATUSLED=234"
CONFIG_FDTFILE="sun7i-a20-m5.dtb"
CONFIG_VIDEO_HDMI=y
-+S:CONFIG_MMC0_CD_PIN="PH1"
-+S:CONFIG_USB1_VBUS_PIN="PH6"
-+S:CONFIG_USB2_VBUS_PIN="PH3"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=122
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_USB1_VBUS_PIN="PH6"
+CONFIG_USB2_VBUS_PIN="PH3"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=122
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31-m9.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=312
-+S:CONFIG_DRAM_ZQ=120
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=312
+CONFIG_DRAM_ZQ=120
# The Mele M9 uses 3.3V for general IO
-+S:CONFIG_AXP221_DCDC1_VOLT=3300
+CONFIG_AXP221_DCDC1_VOLT=3300
# Ethernet phy power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
# USB hub power
-+S:CONFIG_AXP221_DLDO4_VOLT=3300
+CONFIG_AXP221_DLDO4_VOLT=3300
# Wifi power
-+S:CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3300
# Vbus gpio for usb1
-+S:CONFIG_USB1_VBUS_PIN="PC27"
+CONFIG_USB1_VBUS_PIN="PC27"
# No Vbus gpio for usb2
-+S:CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-orangepi.dtb"
+CONFIG_GMAC_TX_DELAY=3
+CONFIG_USB1_VBUS_PIN="PH26"
+CONFIG_USB2_VBUS_PIN="PH22"
+CONFIG_VIDEO_VGA=y
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-orangepi.dtb"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_MMC0_CD_PIN="PH10"
+CONFIG_MMC3_CD_PIN="PH11"
+CONFIG_GMAC_TX_DELAY=3
+CONFIG_USB1_VBUS_PIN="PH26"
+CONFIG_USB2_VBUS_PIN="PH22"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T4240QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T4240QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T4240QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T4240QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T4240QDS=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TB5200=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TB5200=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_TL059WV5C0=y
-+S:CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-+S:CONFIG_MMC0_CD_PIN="PG0"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_MMC0_CD_PIN="PG0"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_W7OLMC=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_W7OLMG=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-wexler-tab7200.dtb"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-wits-pro-a20-dkt.dtb"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
+CONFIG_VIDEO_VGA=y
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC5xxx=y
-+S:CONFIG_TARGET_A3M071=y
+CONFIG_PPC=y
+CONFIG_MPC5xxx=y
+CONFIG_TARGET_A3M071=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC5xxx=y
-+S:CONFIG_TARGET_A3M071=y
+CONFIG_PPC=y
+CONFIG_MPC5xxx=y
+CONFIG_TARGET_A3M071=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_AEV=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_FIT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_NOR=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_CONS_INDEX=1
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
CONFIG_CONS_INDEX=1
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_IGEP0033=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_IGEP0033=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_AM3517_CRANE=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_AM3517_CRANE=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_AM3517_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_AM3517_EVM=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM43XX_EVM=y
--- /dev/null
+CONFIG_M68K=y
+CONFIG_TARGET_AMCORE=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_APALIS_T30=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_APALIS_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_APF27=y
+CONFIG_ARM=y
+CONFIG_TARGET_APF27=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_APX4DEVKIT=y
+CONFIG_ARM=y
+CONFIG_TARGET_APX4DEVKIT=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_ARNDALE=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_ARNDALE=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_TAURUS=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_TAURUS=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb"
CONFIG_USB2_VBUS_PIN="PH12"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_BEAGLE_X15=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_BEAVER=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_BEAVER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_BG0900=y
+CONFIG_ARM=y
+CONFIG_TARGET_BG0900=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_ARM=y
+CONFIG_TARGET_BAV335X=y
+CONFIG_BAV_VERSION=1
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_ARM=y
+CONFIG_TARGET_BAV335X=y
+CONFIG_BAV_VERSION=2
--- /dev/null
+CONFIG_SPL=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_CAIRO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_CAM_ENC_4XX=y
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_TARGET_CAM_ENC_4XX=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_CARDHU=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_CARDHU=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_CM_FX6=y
+CONFIG_ARM=y
+CONFIG_TARGET_CM_FX6=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_CM_T335=y
+CONFIG_ARM=y
+CONFIG_TARGET_CM_T335=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=n
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_CM_T3517=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_CM_T3517=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_CM_T35=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_CM_T35=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_CM_T54=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_CM_T54=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_COLIBRI_T20_IRIS=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_COLIBRI_T20_IRIS=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri_t20_iris"
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_COLIBRI_T30=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_COLIBRI_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_CORVUS=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_CORVUS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_DA850EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_TARGET_DA850EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_DA850EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_TARGET_DA850EVM=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA114=y
-+S:CONFIG_TARGET_DALMORE=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA114=y
+CONFIG_TARGET_DALMORE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_DB_MV784MP_GP=y
+CONFIG_ARM=y
+CONFIG_TARGET_DB_MV784MP_GP=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_DEVKIT8000=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_DEVKIT8000=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPL_YMODEM_SUPPORT"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_DRACO=y
+CONFIG_ARM=y
+CONFIG_TARGET_DRACO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP44XX=y
-+S:CONFIG_TARGET_DUOVERO=y
+CONFIG_ARM=y
+CONFIG_OMAP44XX=y
+CONFIG_TARGET_DUOVERO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_DXR2=y
+CONFIG_ARM=y
+CONFIG_TARGET_DXR2=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_ECO5PK=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_ECO5PK=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
+CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ORION5X=y
CONFIG_TARGET_EDMINIV2=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+CONFIG_FDTFILE="sun5i-a13-forfun-q88db.dtb"
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB0_VBUS_PIN="PG12"
+CONFIG_USB0_VBUS_DET="PG1"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="AXP0-0"
+CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
+
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="galaxy5200_LOWBOOT"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_GALAXY5200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="galaxy5200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_GALAXY5200=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_GW_VENTANA=y
+CONFIG_ARM=y
+CONFIG_TARGET_GW_VENTANA=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_HARMONY=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_HARMONY=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_IPAM390=y
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_TARGET_IPAM390=y
--- /dev/null
+# The Jesurun Q5 has a black plastic casing with the approximate dimensions of
+# 100mm x 100mm x 24mm with rounded edges. In terms of hardware it features an
+# Allwinner A10 SoC with 1GB RAM and 8GB of NAND flash. The storage capacity
+# can be extended up to 32GB with a MicroSD card. The external connectors are:
+# 2x USB-A female supporting USB2.0, 3.5mm female jack for audio, HDMI female,
+# SPDIF, RJ45 LAN and Power. In addition the device has 1x red LED (hard wired
+# to power) and an programmable green led. On the board there is also an
+# unpopulated IR receiver and the UART. The device is equipped with an
+# AXP209 PMU.
+#
+# For more details see: http://linux-sunxi.org/Jesurun_Q5
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,MACPWR=SUNXI_GPH(19)"
+CONFIG_FDTFILE="sun4i-a10-jesurun-q5.dtb"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=312
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA124=y
-+S:CONFIG_TARGET_JETSON_TK1=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA124=y
+CONFIG_TARGET_JETSON_TK1=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_KEYSTONE=y
-+S:CONFIG_TARGET_K2E_EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_TARGET_K2E_EVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_KEYSTONE=y
-+S:CONFIG_TARGET_K2HK_EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_TARGET_K2HK_EVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_KEYSTONE=y
-+S:CONFIG_TARGET_K2L_EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_TARGET_K2L_EVM=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KORAT=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="KORAT_PERMANENT"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KORAT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_KWB=y
+CONFIG_ARM=y
+CONFIG_TARGET_KWB=y
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5"
-+S:CONFIG_PPC=y
-+S:CONFIG_4xx=y
-+S:CONFIG_TARGET_LWMON5=y
+CONFIG_PPC=y
+CONFIG_4xx=y
+CONFIG_TARGET_LWMON5=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021AQDS=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021AQDS=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021AQDS=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021AQDS=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021ATWR=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021ATWR=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021ATWR=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_M28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_M28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_M53EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_M53EVK=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MAXBCM=y
+CONFIG_ARM=y
+CONFIG_TARGET_MAXBCM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_MCX=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_MCX=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_MEDCOM_WIDE=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_MEDCOM_WIDE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
CONFIG_SPL=y
-+S:CONFIG_MICROBLAZE=y
-+S:CONFIG_TARGET_MICROBLAZE_GENERIC=y
+CONFIG_MICROBLAZE=y
+CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-mk802.dtb"
CONFIG_USB1_VBUS_PIN="PB10"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mk802.dtb"
CONFIG_USB2_VBUS_PIN="PH12"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mk802ii.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_MT_VENTOUX=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_MT_VENTOUX=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX23_OLINUXINO=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX23_OLINUXINO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX23EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX23EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX31PDK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX31PDK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX6SABRESD=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX6SABRESD=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_KOSAGI_NOVENA=y
+CONFIG_ARM=y
+CONFIG_TARGET_KOSAGI_NOVENA=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA124=y
-+S:CONFIG_TARGET_NYAN_BIG=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA124=y
+CONFIG_TARGET_NYAN_BIG=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ODROID_XU3=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_BEAGLE=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_BEAGLE=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_EVM=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TAO3530=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TAO3530=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_OVERO=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_OVERO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP44XX=y
-+S:CONFIG_TARGET_OMAP4_PANDA=y
+CONFIG_ARM=y
+CONFIG_OMAP44XX=y
+CONFIG_TARGET_OMAP4_PANDA=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP44XX=y
-+S:CONFIG_TARGET_OMAP4_SDP4430=y
+CONFIG_ARM=y
+CONFIG_OMAP44XX=y
+CONFIG_TARGET_OMAP4_SDP4430=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_OMAP5_UEVM=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_OMAP5_UEVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_ORIGEN=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_ORIGEN=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_OT1200=y
+CONFIG_ARM=y
+CONFIG_TARGET_OT1200=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PALMTREO680=y
+CONFIG_ARM=y
+CONFIG_TARGET_PALMTREO680=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_PAZ00=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_PAZ00=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="REV1"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PCM051=y
+CONFIG_ARM=y
+CONFIG_TARGET_PCM051=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="REV3"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PCM051=y
+CONFIG_ARM=y
+CONFIG_TARGET_PCM051=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_PEACH_PI=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_PEACH_PI=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_PEACH_PIT=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_PEACH_PIT=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PENGWYN=y
+CONFIG_ARM=y
+CONFIG_TARGET_PENGWYN=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PEPPER=y
+CONFIG_ARM=y
+CONFIG_TARGET_PEPPER=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PLATINUM_PICON=y
+CONFIG_ARM=y
+CONFIG_TARGET_PLATINUM_PICON=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PLATINUM_TITANIUM=y
+CONFIG_ARM=y
+CONFIG_TARGET_PLATINUM_TITANIUM=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_PLUTUX=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_PLUTUX=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PXM2=y
+CONFIG_ARM=y
+CONFIG_TARGET_PXM2=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb"
CONFIG_USB1_VBUS_PIN="PG13"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_RUT=y
+CONFIG_ARM=y
+CONFIG_TARGET_RUT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4EK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4EK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4EK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SANSA_FUZE_PLUS=y
+CONFIG_ARM=y
+CONFIG_TARGET_SANSA_FUZE_PLUS=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SC_SPS_1=y
+CONFIG_ARM=y
+CONFIG_TARGET_SC_SPS_1=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_SEABOARD=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_SEABOARD=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_SMDK5250=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_SMDK5250=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_SMDK5420=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_SMDK5420=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_SMDKV310=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_SMDKV310=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_SNOW=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_SNOW=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
CONFIG_CROS_EC=y
CONFIG_DM_CROS_EC=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_ARM=y
+CONFIG_TARGET_SOCFPGA_ARRIA5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
+CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_ARM=y
+CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
+CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_ARM=y
+CONFIG_TARGET_SOCFPGA_CYCLONE5=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_DM=y
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TAO3530=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TAO3530=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_TAURUS=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_TAURUS=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_TEC_NG=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_TEC_NG=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_TEC=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_TEC=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TI814X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_TI814X_EVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TI816X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_TI816X_EVM=y
CONFIG_TARGET_TRATS2=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TRICORDER=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TRICORDER=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TRICORDER=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TRICORDER=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_TRIMSLICE=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_TRIMSLICE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TSERIES=y
+CONFIG_ARM=y
+CONFIG_TARGET_TSERIES=y
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TSERIES=y
+CONFIG_ARM=y
+CONFIG_TARGET_TSERIES=y
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TSERIES=y
+CONFIG_ARM=y
+CONFIG_TARGET_TSERIES=y
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TWISTER=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TWISTER=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX25=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX25=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA124=y
-+S:CONFIG_TARGET_VENICE2=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA124=y
+CONFIG_TARGET_VENICE2=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_VENTANA=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_VENTANA=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_VPAC270=y
+CONFIG_ARM=y
+CONFIG_TARGET_VPAC270=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_WHISTLER=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_WHISTLER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_WOODBURN_SD=y
+CONFIG_ARM=y
+CONFIG_TARGET_WOODBURN_SD=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_X600=y
+CONFIG_ARM=y
+CONFIG_TARGET_X600=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_XFI3=y
+CONFIG_ARM=y
+CONFIG_TARGET_XFI3=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_MICROZED=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_MICROZED=y
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZC70X=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC70X=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_FIT=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZED=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZED=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
CONFIG_FIT=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZYBO=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZYBO=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
CONFIG_FIT=y
--- /dev/null
+DSP side awareness for Freescale heterogeneous multicore chips based on
+StarCore and Power Architecture
+===============================================================
+powerpc/mpc85xx code ve APIs and function to get the number,
+configuration and frequencies of all PowerPC cores and devices
+connected to them, but it didnt have the similar code ofr HEterogeneous
+SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc.
+
+Code for DSP side awareness provides such functionality for Freescale
+Heterogeneous SoCs which are chasis-2 compliant like B4860 and B4420
+
+As part of this feature, following changes have been made:
+==========================================================
+
+1. Changed files:
+=================
+- arch/powerpc/cpu/mpc85xx/cpu.c
+
+Code added in this file to print the DSP cores and other device's(CPRI,
+MAPLE etc) frequencies
+
+- arch/powerpc/cpu/mpc85xx/speed.c
+
+Added Defines and code to extract the frequncy information for all
+required cores and devices from RCW and System frequency
+
+- arch/powerpc/cpu/mpc8xxx/cpu.c
+
+Added API to get the number of SC cores in running system and Their BIT
+MASK, similar to the code written for PowerPC
+
+- arch/powerpc/include/asm/config_mpc85xx.h
+
+Added top level CONFIG to identify presence of HETEROGENUOUS clusters
+in the system and CONFIGS for SC3900/DSP components
+
+- arch/powerpc/include/asm/processor.h
+- include/common.h
+
+Added newly added Functions Declaration
+
+- include/e500.h
+
+Global structure updated for dsp cores and other components
+
+2. CONFIGs ADDED
+================
+
+CONFIG_HETROGENOUS_CLUSTERS - Define for checking the presence of
+ DSP/SC3900 core clusters
+
+CONFIG_SYS_FSL_NUM_CC_PLLS - Define for number of PLLs
+
+Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
+PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the
+value as 5 not 4, to iterate over all PLLs while coding
+
+CONFIG_SYS_MAPLE - Define for MAPLE Baseband Accelerator
+CONFIG_SYS_CPRI - Define for CPRI Interface
+CONFIG_PPC_CLUSTER_START - Start index of ppc clusters
+CONFIG_DSP_CLUSTER_START - Start index of dsp clusters
+
+Following are the defines for PLL's index that provide the Clocking to
+CPRI, ULB and ETVE components
+
+CONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock
+CONFIG_SYS_ULB_CLK - Define PLL index for ULB clock
+CONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock
+
+3. Changes in MPC85xx_SYS_INFO Global structure
+===============================================
+
+DSP cores and other device's components have been added in this structure.
+
+freq_processor_dsp[CONFIG_MAX_DSP_CPUS] - Array to contain the DSP core's frequencies
+freq_cpri - To store CPRI frequency
+freq_maple - To store MAPLE frequency
+freq_maple_ulb - To store MAPLE-ULB frequency
+freq_maple_etvpe - To store MAPLE-eTVPE frequency
+
+4. U-BOOT LOGS
+==============
+4.1 B4860QDS board
+ Boot from NOR flash
+
+U-Boot 2014.07-00222-g70587a8-dirty (Aug 07 2014 - 13:15:47)
+
+CPU0: B4860E, Version: 2.0, (0x86880020)
+Core: e6500, Version: 2.0, (0x80400020) Clock Configuration:
+ CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
+ DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
+ DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
+ CCB:666.667 MHz,
+ DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
+ CPRI:600 MHz
+ MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
+ FMAN1: 666.667 MHz
+ QMAN: 333.333 MHz
+
+CPUn - PowerPC core
+DSP CPUn - SC3900 core
+
+Shaveta Leekha(shaveta@freescale.com)
+Created August 7, 2014
+===========================================
--- /dev/null
+/*
+ * (C) Copyright 2015
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+esbc_validate command
+========================================
+
+1. esbc_validate command is meant for validating header and
+ signature of images (Boot Script and ESBC uboot client).
+ SHA-256 and RSA operations are performed using SEC block in HW.
+ This command works on both PBL based and Non PBL based Freescale
+ platforms.
+ Command usage:
+ esbc_validate img_hdr_addr [pub_key_hash]
+ esbc_validate hdr_addr <hash_val>
+ Validates signature using RSA verification.
+ $hdr_addr Address of header of the image to be validated.
+ $hash_val -Optional. It provides Hash of public/srk key to be
+ used to verify signature.
+
+2. ESBC uboot client can be linux. Additionally, rootfs and device
+ tree blob can also be signed.
+3. In the event of header or signature failure in validation,
+ ITS and ITF bits determine further course of action.
+4. In case of soft failure, appropriate error is dumped on console.
+5. In case of hard failure, SoC is issued RESET REQUEST after
+ dumping error on the console.
+6. KEY REVOCATION Feature:
+ QorIQ platforms like B4/T4 have support of srk key table and key
+ revocation in ISBC code in Silicon.
+ The srk key table allows the user to have a key table with multiple
+ keys and revoke any key in case of particular key gets compromised.
+ In case the ISBC code uses the key revocation and srk key table to
+ verify the u-boot code, the subsequent chain of trust should also
+ use the same.
+6. ISBC KEY EXTENSION Feature:
+ This feature allows large number of keys to be used for esbc validation
+ of images. A set of public keys is being signed and validated by ISBC
+ which can be further used for esbc validation of images.
"partitions=uuid_disk=${uuid_gpt_disk};name=${uboot_name},
size=${uboot_size},uuid=${uboot_uuid};"
- Fields 'name', 'size' and 'uuid' are mandatory for every partition.
+ The fields 'name' and 'size' are mandatory for every partition.
The field 'start' is optional.
- option: CONFIG_RANDOM_UUID
- If any partition "UUID" no exists then it is randomly generated.
+ The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is
+ enabled. A random uuid will be used if omitted or they point to an empty/
+ non-existent environment variable. The environment variable will be set to
+ the generated UUID.
2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT'
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-hawkboard arm arm926ejs - - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
-tnetv107x arm arm1176 - - Chan-Taek Park <c-park@ti.com>
-a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
-cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
-cm41xx arm arm920t - -
-dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
-jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
+korat powerpc ppc4xx - - Larry Johnson <lrj@acm.org>
+galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com>
+W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
+W7OLMG powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
+aev powerpc mpc5xxx - -
+TB5200 powerpc mpc5xxx - -
+JSE powerpc ppc4xx - - Stephen Williams <steve@icarus.com>
+BC3450 powerpc mpc5xxx - -
+hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
+tnetv107x arm arm1176 50b82c4b 2015-02-24 Chan-Taek Park <c-park@ti.com>
+a320evb arm arm920t 29fc6f24 2015-02-24 Po-Yu Chuang <ratbert@faraday-tech.com>
+cm4008 arm arm920t a2f39e83 2015-02-24 Greg Ungerer <greg.ungerer@opengear.com>
+cm41xx arm arm920t a2f39e83 2015-02-24
+dkb arm arm926ejs 346cfba4 2015-02-24 Lei Wen <leiwen@marvell.com>
+jadecpu arm arm926ejs 41fbbbbc 2015-02-24 Matthias Weisser <weisserm@arcor.de>
icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23
cpci5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
alias lukma Lukasz Majewski <l.majewski@samsung.com>
alias macpaul Macpaul Lin <macpaul@andestech.com>
alias marex Marek Vasut <marex@denx.de>
-alias masahiro Masahiro Yamada <yamada.m@jp.panasonic.com>
+alias masahiro Masahiro Yamada <yamada.masahiro@socionext.com>
alias monstr Michal Simek <monstr@monstr.eu>
alias panto Pantelis Antoniou <panto@antoniou-consulting.com>
alias prafulla Prafulla Wadaskar <prafulla@marvell.com>
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_RSA) += mod_exp_uclass.o mod_exp_sw.o
+obj-$(CONFIG_RSA) += mod_exp_uclass.o
+obj-$(CONFIG_RSA_SOFTWARE_EXP) += mod_exp_sw.o
#include <fat.h>
#include <mmc.h>
-static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE)
- dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE];
+static unsigned char *dfu_file_buf;
static long dfu_file_buf_len;
static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part)
if (dfu->layout != DFU_RAW_ADDR) {
/* Do stuff here. */
- ret = mmc_file_op(DFU_OP_WRITE, dfu, &dfu_file_buf,
+ ret = mmc_file_op(DFU_OP_WRITE, dfu, dfu_file_buf,
&dfu_file_buf_len);
/* Now that we're done */
return ret;
}
+void dfu_free_entity_mmc(struct dfu_entity *dfu)
+{
+ if (dfu_file_buf) {
+ free(dfu_file_buf);
+ dfu_file_buf = NULL;
+ }
+}
+
/*
* @param s Parameter string containing space-separated arguments:
* 1st:
dfu->write_medium = dfu_write_medium_mmc;
dfu->flush_medium = dfu_flush_medium_mmc;
dfu->inited = 0;
+ dfu->free_entity = dfu_free_entity_mmc;
+
+ /* Check if file buffer is ready */
+ if (!dfu_file_buf) {
+ dfu_file_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
+ CONFIG_SYS_DFU_MAX_FILE_SIZE);
+ if (!dfu_file_buf) {
+ error("Could not memalign 0x%x bytes",
+ CONFIG_SYS_DFU_MAX_FILE_SIZE);
+ return -ENOMEM;
+ }
+ }
return 0;
}
snprintf(name, sizeof(name), "generic_%x", chip_addr);
str = strdup(name);
+ if (!str)
+ return -ENOMEM;
ret = device_bind_driver(bus, "i2c_generic_chip_drv", str, &dev);
debug("%s: device_bind_driver: ret=%d\n", __func__, ret);
if (ret)
/*
* Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
};
static const struct udevice_id uniphier_fi2c_of_match[] = {
- { .compatible = "panasonic,uniphier-fi2c" },
- {},
+ { .compatible = "socionext,uniphier-fi2c" },
+ { /* sentinel */ }
};
U_BOOT_DRIVER(uniphier_fi2c) = {
/*
* Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
};
static const struct udevice_id uniphier_i2c_of_match[] = {
- { .compatible = "panasonic,uniphier-i2c" },
- {},
+ { .compatible = "socionext,uniphier-i2c" },
+ { /* sentinel */ }
};
U_BOOT_DRIVER(uniphier_i2c) = {
}
#ifdef CONFIG_I2C_MULTI_BUS
-static u32 i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
+static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
static unsigned int current_bus;
return status;
}
-/*
- * Ugly formula to convert m and n values to a frequency comes from
- * TWSI specifications
- */
-
-#define TWSI_FREQUENCY(m, n) \
- (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)))
+static unsigned int twsi_calc_freq(const int n, const int m)
+{
+#ifdef CONFIG_SUNXI
+ return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
+#else
+ return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
+#endif
+}
/*
* Reset controller.
/* compute m, n setting for highest speed not above requested speed */
for (n = 0; n < 8; n++) {
for (m = 0; m < 16; m++) {
- tmp_speed = TWSI_FREQUENCY(m, n);
+ tmp_speed = twsi_calc_freq(n, m);
if ((tmp_speed <= requested_speed)
&& (tmp_speed > highest_speed)) {
highest_speed = tmp_speed;
but otherwise makes few changes. Since cros_ec also supports
LPC (which doesn't support driver model yet), a full
conversion is not yet possible.
+
+config CONFIG_FSL_SEC_MON
+ bool "Enable FSL SEC_MON Driver"
+ help
+ Freescale Security Monitor block is responsible for monitoring
+ system states.
+ Security Monitor can be transitioned on any security failures,
+ like software violations or hardware security violations.
obj-$(CONFIG_STATUS_LED) += status_led.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
+obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_sec_mon.h>
+
+int change_sec_mon_state(u32 initial_state, u32 final_state)
+{
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
+ u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+ int timeout = 10;
+
+ if ((sts & HPSR_SSM_ST_MASK) != initial_state)
+ return -1;
+
+ if (initial_state == HPSR_SSM_ST_TRUST) {
+ switch (final_state) {
+ case HPSR_SSM_ST_NON_SECURE:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
+
+ /*
+ * poll till SEC_MON is in
+ * Soft Fail state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_SOFT_FAIL)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+
+ timeout = 10;
+
+ printf("SEC_MON state transitioning to Non Secure.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST);
+
+ /*
+ * poll till SEC_MON is in
+ * Non Secure state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_NON_SECURE)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_NON_SECURE)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+ case HPSR_SSM_ST_SOFT_FAIL:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
+
+ /*
+ * polling loop till SEC_MON is in
+ * Soft Fail state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_SOFT_FAIL)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ } else if (initial_state == HPSR_SSM_ST_NON_SECURE) {
+ switch (final_state) {
+ case HPSR_SSM_ST_SOFT_FAIL:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
+
+ /*
+ * polling loop till SEC_MON is in
+ * Soft Fail state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_SOFT_FAIL)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ }
+
+ return 0;
+}
uint adsaddr; /* ADMA system address register */
char reserved2[100]; /* reserved */
uint vendorspec; /* Vendor Specific register */
- char reserved3[59]; /* reserved */
+ char reserved3[56]; /* reserved */
uint hostver; /* Host controller version register */
char reserved4[4]; /* reserved */
uint dmaerraddr; /* DMA error address register */
static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
struct mmc *mmc = host->mmc;
- u32 ata = (u32)host->ioaddr + SD_CE_ATA_2;
+ u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
if (mmc->bus_width == 8)
#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
static char *MVSDH_NAME = "mv_sdh";
-int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
{
struct sdhci_host *host = NULL;
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
val = sdhci_readl(host, SDHCI_CONTROL2);
- val &= SDHCI_CTRL2_SELBASECLK_SHIFT;
+ val &= SDHCI_CTRL2_SELBASECLK_MASK(3);
val |= SDHCI_CTRL2_ENSTAASYNCCLR |
SDHCI_CTRL2_ENCMDCNFMSK |
#ifdef CONFIG_MMC_SDMA
if (data->flags == MMC_DATA_READ)
- start_addr = (unsigned int)data->dest;
+ start_addr = (unsigned long)data->dest;
else
- start_addr = (unsigned int)data->src;
+ start_addr = (unsigned long)data->src;
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
(start_addr & 0x7) != 0x0) {
is_aligned = 0;
- start_addr = (unsigned int)aligned_buffer;
+ start_addr = (unsigned long)aligned_buffer;
if (data->flags != MMC_DATA_READ)
memcpy(aligned_buffer, data->src, trans_bytes);
}
if (host->quirks & SDHCI_QUIRK_NO_CD) {
unsigned int status;
- sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
+ sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
SDHCI_HOST_CONTROL);
status = sdhci_readl(host, SDHCI_PRESENT_STATE);
static uint8_t cs_next;
static __maybe_unused struct nand_ecclayout omap_ecclayout;
+#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
+ { CONFIG_NAND_OMAP_GPMC_WSCFG };
+#else
+/* wscfg is preset to zero since its a static variable */
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
/*
* Driver configurations
*/
struct omap_nand_info {
struct bch_control *control;
enum omap_ecc ecc_scheme;
- int cs;
+ uint8_t cs;
+ uint8_t ws; /* wait status pin (0,1) */
};
/* We are wasting a bit of memory but al least we are safe */
/* Check wait pin as dev ready indicator */
static int omap_dev_ready(struct mtd_info *mtd)
{
- return gpmc_cfg->status & (1 << 8);
+ register struct nand_chip *this = mtd->priv;
+ struct omap_nand_info *info = this->priv;
+ return gpmc_cfg->status & (1 << (8 + info->ws));
}
/*
return -EINVAL;
}
} else {
- err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+ if (eccstrength == 1) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_HAM1_CODE_SW,
mtd->writesize, mtd->oobsize);
+ } else if (eccstrength == 8) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+ mtd->writesize, mtd->oobsize);
+ } else {
+ printf("nand: error: unsupported ECC scheme\n");
+ return -EINVAL;
+ }
}
/* Update NAND handling after ECC mode switch */
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
omap_nand_info[cs].control = NULL;
omap_nand_info[cs].cs = cs;
+ omap_nand_info[cs].ws = wscfg[cs];
nand->priv = &omap_nand_info[cs];
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
+#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
&dma_p->opmode);
+#else
+ writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
+ &dma_p->opmode);
+#endif
writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
+#ifdef CONFIG_DW_AXI_BURST_LEN
+ writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
+#endif
+
/* Start up the PHY */
if (phy_startup(priv->phydev)) {
printf("Could not initialize PHY %s\n",
u32 status; /* 0x14 */
u32 opmode; /* 0x18 */
u32 intenable; /* 0x1c */
- u8 reserved[40];
+ u32 reserved1[2];
+ u32 axibus; /* 0x28 */
+ u32 reserved2[7];
u32 currhosttxdesc; /* 0x48 */
u32 currhostrxdesc; /* 0x4c */
u32 currhosttxbuffaddr; /* 0x50 */
return 0;
}
+int axp_get_vbus(void)
+{
+ int ret;
+ u8 val;
+
+ ret = axp221_init();
+ if (ret)
+ return ret;
+
+ ret = pmic_bus_read(AXP221_POWER_STATUS, &val);
+ if (ret)
+ return ret;
+
+ return (val & AXP221_POWER_STATUS_VBUS_USABLE) ? 1 : 0;
+}
+
static int axp_drivebus_setup(void)
{
int ret;
/*
* Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifdef CONFIG_OF_CONTROL
static const struct udevice_id uniphier_uart_of_match[] = {
- { .compatible = "panasonic,uniphier-uart" },
- {},
+ { .compatible = "socionext,uniphier-uart" },
+ { /* sentinel */ }
};
static int uniphier_serial_ofdata_to_platdata(struct udevice *dev)
/*
* Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
DECLARE_GLOBAL_DATA_PTR;
#define FDT gd->fdt_blob
-#define COMPAT "panasonic,uniphier-ehci"
+#define COMPAT "socionext,uniphier-ehci"
static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
{
/*
* Copyright (C) 2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
int count;
count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
- COMPAT_PANASONIC_XHCI, node_list,
+ COMPAT_SOCIONEXT_XHCI, node_list,
ARRAY_SIZE(node_list));
if (index >= count)
#include <asm-generic/gpio.h>
#include "linux-compat.h"
#include "musb_core.h"
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
+#ifdef CONFIG_AXP221_POWER
+#include <axp221.h>
+#endif
/******************************************************************************
******************************************************************************
if (is_host_enabled(musb)) {
int vbus_det = sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
- if (vbus_det == -1) {
- eprintf("Error invalid Vusb-det pin\n");
- return -EINVAL;
- }
- err = gpio_request(vbus_det, "vbus0_det");
- if (err)
- return err;
+#ifdef AXP_VBUS_DETECT
+ if (!strcmp(CONFIG_USB0_VBUS_DET, "axp_vbus_detect")) {
+ err = axp_get_vbus();
+ if (err < 0)
+ return err;
+ } else {
+#endif
+ if (vbus_det == -1) {
+ eprintf("Error invalid Vusb-det pin\n");
+ return -EINVAL;
+ }
+
+ err = gpio_request(vbus_det, "vbus0_det");
+ if (err)
+ return err;
+
+ err = gpio_direction_input(vbus_det);
+ if (err) {
+ gpio_free(vbus_det);
+ return err;
+ }
+
+ err = gpio_get_value(vbus_det);
+ if (err) {
+ gpio_free(vbus_det);
+ return -EIO;
+ }
- err = gpio_direction_input(vbus_det);
- if (err) {
gpio_free(vbus_det);
- return err;
+#ifdef AXP_VBUS_DETECT
}
+#endif
- err = gpio_get_value(vbus_det);
if (err) {
eprintf("Error: A charger is plugged into the OTG\n");
- gpio_free(vbus_det);
return -EIO;
}
-
- gpio_free(vbus_det);
}
err = sunxi_usbc_request_resources(0);
memset((void *)gd->fb_base, 0, 0x20);
*(unsigned int *)gd->fb_base = 0x4000;
+ /* turn ON display through powercontrol function if accessible */
+ if (0 != panel->panel_power_ctrl)
+ panel->panel_power_ctrl(1);
+
+ debug("am335x-fb: wait for stable power ...\n");
+ mdelay(panel->pup_delay);
lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
lcdhw->raster_ctrl = 0;
lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
gd->fb_base += 0x20; /* point fb behind palette */
- /* turn ON display through powercontrol function if accessible */
- if (0 != panel->panel_power_ctrl) {
- mdelay(panel->pon_delay);
- panel->panel_power_ctrl(1);
- }
+ debug("am335x-fb: waiting picture to be stable.\n.");
+ mdelay(panel->pon_delay);
return 0;
}
unsigned int vsw; /* Vertical Sync Pulse Width */
unsigned int pxl_clk_div; /* Pixel clock divider*/
unsigned int pol; /* polarity of sync, clock signals */
+ unsigned int pup_delay; /*
+ * time in ms after power on to
+ * initialization of lcd-controller
+ * (VCC ramp up time)
+ */
unsigned int pon_delay; /*
- * time in ms for turning on lcd after
- * initializing lcd-controller
+ * time in ms after initialization of
+ * lcd-controller (pic stabilization)
*/
void (*panel_power_ctrl)(int); /* fp for power on/off display */
};
}
ext4fs_close();
+ *actwrite = len;
+
return 0;
fail:
ext4fs_close();
+ *actwrite = 0;
return -1;
}
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
unsigned long bi_mbar_base; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
#if defined(CONFIG_MPC512X)
unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */
#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+ unsigned long bi_inpfreq; /* input Freq in MHz */
+ unsigned long bi_vcofreq; /* vco Freq in MHz */
+ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
+#endif
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
#define AXP223_RUNTIME_ADDR 0x2d
/* Page 0 addresses */
+#define AXP221_POWER_STATUS 0x00
+#define AXP221_POWER_STATUS_VBUS_AVAIL (1 << 5)
+#define AXP221_POWER_STATUS_VBUS_USABLE (1 << 4)
#define AXP221_CHIP_ID 0x03
#define AXP221_OUTPUT_CTRL1 0x10
#define AXP221_OUTPUT_CTRL1_DCDC0_EN (1 << 0)
/* Page 1 addresses */
#define AXP221_SID 0x20
+/* We support vbus detection */
+#define AXP_VBUS_DETECT
+
/* We support drivebus control */
#define AXP_DRIVEBUS
int axp221_set_eldo(int eldo_num, unsigned int mvolt);
int axp221_init(void);
int axp221_get_sid(unsigned int *sid);
+int axp_get_vbus(void);
int axp_drivebus_enable(void);
int axp_drivebus_disable(void);
iter++, cpu = cpumask_next(cpu, mask)) \
int cpu_numcores (void);
+int cpu_num_dspcores(void);
u32 cpu_mask (void);
+u32 cpu_dsp_mask(void);
int is_core_valid (unsigned int);
int probecpu (void);
int checkcpu (void);
#ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H
#define _CONFIG_CMD_DISTRO_BOOTCMD_H
+/*
+ * A note on error handling: It is possible for BOOT_TARGET_DEVICES to
+ * reference a device that is not enabled in the U-Boot configuration, e.g.
+ * it may include MMC in the list without CONFIG_CMD_MMC being enabled. Given
+ * that BOOT_TARGET_DEVICES is a macro that's expanded by the C pre-processor
+ * at compile time, it's not possible to detect and report such problems via
+ * a simple #ifdef/#error combination. Still, the code needs to report errors.
+ * The best way I've found to do this is to make BOOT_TARGET_DEVICES expand to
+ * reference a non-existent symbol, and have the name of that symbol encode
+ * the error message. Consequently, this file contains references to e.g.
+ * BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC. Given the
+ * prevalence of capitals here, this looks like a pre-processor macro and
+ * hence seems like it should be all capitals, but it's really an error
+ * message that includes some other pre-processor symbols in the text.
+ */
+
/* We need the part command */
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
+++ /dev/null
-/*
- * -- Version 1.1 --
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * (C) Copyright 2005
- * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
- *
- * History:
- * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
-#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
-
-#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
-#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
-#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
-#define CONFIG_BC3450_USB 1 /* + USB support */
-# define CONFIG_FAT 1 /* + FAT support */
-# define CONFIG_EXT2 1 /* + EXT2 support */
-#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
-#undef CONFIG_BC3450_CAN /* + CAN transceiver */
-#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
-#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
-#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
-#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
-#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000 boot low (standard configuration with room for
- * max 64 MByte Flash ROM)
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFC000000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * AT-PS/2 Multiplexer
- */
-#ifdef CONFIG_BC3450_PS2
-# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
-# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
-# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
-# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
-# define CONFIG_BOARD_EARLY_INIT_R
-#endif /* CONFIG_BC3450_PS2 */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-# define CONFIG_PCI 1
-# define CONFIG_PCI_PNP 1
-/* #define CONFIG_PCI_SCAN_SHOW 1 */
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-
-/*
- * Video console
- */
-# define CONFIG_VIDEO
-# define CONFIG_VIDEO_SM501
-# define CONFIG_VIDEO_SM501_32BPP
-# define CONFIG_CFB_CONSOLE
-# define CONFIG_VIDEO_LOGO
-# define CONFIG_VGA_AS_SINGLE_DEVICE
-# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
-# define CONFIG_VIDEO_SW_CURSOR
-# define CONFIG_SPLASH_SCREEN
-# define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/*
- * Partitions
- */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/*
- * USB
- */
-#ifdef CONFIG_BC3450_USB
-# define CONFIG_USB_OHCI
-# define CONFIG_USB_STORAGE
-#endif /* CONFIG_BC3450_USB */
-
-/*
- * POST support
- */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_I2C)
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif /* CONFIG_POST */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_BSP
-
-#ifdef CONFIG_VIDEO
- #define CONFIG_CMD_BMP
-#endif
-
-#ifdef CONFIG_BC3450_IDE
- #define CONFIG_CMD_IDE
-#endif
-
-#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
- #ifdef CONFIG_FAT
- #define CONFIG_CMD_FAT
- #endif
-
- #ifdef CONFIG_EXT2
- #define CONFIG_CMD_EXT2
- #endif
-#endif
-
-#ifdef CONFIG_BC3450_USB
- #define CONFIG_CMD_USB
-#endif
-
-#ifdef CONFIG_PCI
- #define CONFIG_CMD_PCI
-#endif
-
-#ifdef CONFIG_POST
- #define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_TIMESTAMP /* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo;"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "ipaddr=192.168.1.10\0" \
- "serverip=192.168.1.3\0" \
- "netmask=255.255.255.0\0" \
- "hostname=bc3450\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "kernel_addr=fc0a0000\0" \
- "ramdisk_addr=fc1c0000\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "ideargs=setenv bootargs root=/dev/hda2 ro\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addcons=setenv bootargs $(bootargs) " \
- "console=ttyS0,$(baudrate) console=tty0\0" \
- "flash_self=run ramargs addip addcons;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile); " \
- "run nfsargs addip addcons; bootm\0" \
- "ide_nfs=run nfsargs addip addcons; " \
- "disk 200000 0:1; bootm\0" \
- "ide_ide=run ideargs addip addcons; " \
- "disk 200000 0:1; bootm\0" \
- "usb_self=run usbload; run ramargs addip addcons; " \
- "bootm 200000 400000\0" \
- "usbload=usb reset; usb scan; usbboot 200000 0:1; " \
- "usbboot 400000 0:2\0" \
- "bootfile=uImage\0" \
- "load=tftp 200000 $(u-boot)\0" \
- "u-boot=u-boot.bin\0" \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 $(filesize);" \
- "protect on FC000000 FC05FFFF\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
-
-/*
- * I2C clock frequency
- *
- * Please notice, that the resulting clock frequency could differ from the
- * configured value. This is because the I2C clock is derived from system
- * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
- * approximation allways lies below the configured value, never above.
- */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration for I²C EEPROM M24C32
- * M24C64 should work also. For other EEPROMs config should be verified.
- *
- * The TQM5200 module may hold an EEPROM at address 0x50.
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-
-/*
- * RTC configuration
- */
-#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
-# define CONFIG_RTC_M41T11 1
-# define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#else
-# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
-# define CONFIG_BOARD_EARLY_INIT_R
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
-
-/* use CFI flash driver if no module variant is spezified */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=TQM5200-0"
-#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
- "1408k(kernel)," \
- "2m(initrd)," \
- "4m(small-fs)," \
- "16m(big-fs)," \
- "8m(misc)"
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
-#else
-# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#endif /*CONFIG_POST*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- *
- * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-#undef CONFIG_MPC5xxx_MII10
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration on BC3450
- *
- * PSC1: UART1 (Service-UART) [0x xxxxxxx4]
- * PSC2: UART2 [0x xxxxxx4x]
- * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
- * PSC3: USB2 [0x xxxxx1xx]
- * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
- * (this has to match
- * CONFIG_USB_CONFIG which is
- * used by usb_ohci.c to set
- * the USB ports)
- * Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
- * (this is reset to '5'
- * in FEC driver: fec.c)
- * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
- * ATA/CS: ??? [0x x1xxxxxx]
- * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
- * CS1: Use Pin gpio_wkup_6 as second
- * SDRAM chip select (mem_cs1)
- * Timer: CAN2 / SPI
- * I2C: CAN1 / I²C2 [0x bxxxxxxx]
- */
-#ifdef CONFIG_BC3450_AC97
-# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
-#else /* PSC2=UART2 */
-# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
-
-#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
- /* more extensive mem test */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
-#else
-# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-/* automatic configuration of chip selects */
-#ifdef CONFIG_TQM5200
-# define CONFIG_LAST_STAGE_INIT
-#endif /* CONFIG_TQM5200 */
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#ifdef CONFIG_TQM5200
-# define CONFIG_SYS_CS2_START 0xE5000000
-# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
-# define CONFIG_SYS_CS2_CFG 0x0004D930
-#endif /* CONFIG_TQM5200 */
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#ifdef CONFIG_TQM5200
-# define SM501_FB_BASE 0xE0000000
-# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
-# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
-# define CONFIG_SYS_CS1_CFG 0x8F48FF70
-# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
-#endif /* CONFIG_TQM5200 */
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
- /* flash and SM501 */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*
- * USB stuff
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
-
-/*
- * IDE/ATA stuff Supports IDE harddisk
- */
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2003 Picture Elements, Inc.
- * Stephen Williams <steve@icarus.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options for the JSE board
- * (Theoretically easy to change, but the board is fixed.)
- */
-
-#define CONFIG_JSE 1
- /* JSE has a PPC405GPr */
-#define CONFIG_405GP 1
- /* ... with a 33MHz OSC. connected to the SysCLK input */
-#define CONFIG_SYS_CLK_FREQ 33333333
- /* ... with on-chip memory here (4KBytes) */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
- /* Do not set up locked dcache as init ram. */
-#undef CONFIG_SYS_INIT_DCACHE_CS
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
- /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
-#define CONFIG_SYSTEMACE 1
-#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
-#define CONFIG_SYS_SYSTEMACE_WIDTH 8
-#define CONFIG_DOS_PARTITION 1
-
- /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
- /* ... place INIT RAM in the OCM address */
-# define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
- /* ... give it the whole init ram */
-# define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
- /* ... Shave a bit off the end for global data */
-# define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
- /* ... and place the stack pointer at the top of what's left. */
-# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
- /* Enable board_pre_init function */
-#define CONFIG_BOARD_PRE_INIT 1
-#define CONFIG_BOARD_EARLY_INIT_F 1
- /* Disable post-clk setup init function */
-#undef CONFIG_BOARD_POSTCLK_INIT
- /* Disable call to post_init_f: late init function. */
-#undef CONFIG_POST
- /* Enable DRAM test. */
-#define CONFIG_SYS_DRAM_TEST 1
- /* Enable misc_init_r function. */
-#define CONFIG_MISC_INIT_R 1
-
- /* JSE has EEPROM chips that are good for environment. */
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#undef CONFIG_ENV_IS_NOWHERE
-
- /* This is the 7bit address of the device, not including P. */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
- /* After the device address, need one more address byte. */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
- /* The EEPROM is 512 bytes. */
-#define CONFIG_SYS_EEPROM_SIZE 512
- /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
- /* Put the environment in the second half. */
-#define CONFIG_ENV_OFFSET 0x00
-#define CONFIG_ENV_SIZE 512
-
- /* The JSE connects UART1 to the console tap connector. */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
- /* Set console baudrate to 9600 */
-#define CONFIG_BAUDRATE 9600
-
-/*
- * Configuration related to auto-boot.
- *
- * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
- * before resorting to autoboot. This value can be overridden by the
- * bootdelay environment variable.
- *
- * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
- * user that an autoboot will happen.
- *
- * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
- * execute to boot the JSE. This loads the uimage and initrd.img files
- * from CompactFlash into memory, then boots them from memory.
- *
- * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
- * it going on the JSE.
- */
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw"
-#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
-
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-
-
- /* watchdog disabled */
-#undef CONFIG_WATCHDOG
- /* SPD EEPROM (sdram speed config) disabled */
-#undef CONFIG_SPD_EEPROM
-#undef SPD_EEPROM_ADDRESS
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
-#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-#endif /* __CONFIG_H */
#define CONFIG_M54451 /* define processor type */
#define CONFIG_M54451EVB /* M54451EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
#define CONFIG_SYS_LOWBOOT
#endif
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
+++ /dev/null
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
-#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000 boot low (standard configuration with room for
- * max 64 MByte Flash ROM)
- * 0xFFF00000 boot high (for a backup copy of U-Boot)
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFC000000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
-#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Video console
- */
-#if 1
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_I2C)
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_USB
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_CMD_BMP
-#endif
-
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_TIMESTAMP /* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#if defined(CONFIG_TQM5200_B)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
- "update=protect off FC000000 FC07FFFF;" \
- "erase FC000000 FC07FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC07FFFF\0" \
- ""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 $(u-boot)\0" \
- "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC05FFFF\0" \
- ""
-#endif /* CONFIG_TQM5200_B */
-
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
-
-/*
- * I2C clock frequency
- *
- * Please notice, that the resulting clock frequency could differ from the
- * configured value. This is because the I2C clock is derived from system
- * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
- * approximation allways lies below the configured value, never above.
- */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
- * also). For other EEPROMs configuration should be verified. On Mini-FAP the
- * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
- * same configuration could be used.
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/* List of I2C addresses to be verified by POST */
-#undef CONFIG_SYS_POST_I2C_ADDRS
-#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_SLAVE}
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#if defined(CONFIG_TQM5200_B)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif /* CONFIG_TQM5200_B */
-#endif /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=TQM5200-0"
-#if defined(CONFIG_TQM5200_B)
-#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
- "1280k(kernel)," \
- "2m(initrd)," \
- "4m(small-fs)," \
- "16m(big-fs)," \
- "8m(misc)"
-#else
-#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
- "1408k(kernel)," \
- "2m(initrd)," \
- "4m(small-fs)," \
- "16m(big-fs)," \
- "8m(misc)"
-#endif /* CONFIG_TQM5200_B */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#if defined(CONFIG_TQM5200_B)
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#else
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_TQM5200_B */
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#endif
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#if defined(CONFIG_TQM5200_B)
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#endif /* CONFIG_TQM5200_B */
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- *
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- * Bit 0 (mask: 0x80000000): 1
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- * Use for REV200 STK52XX boards. Do not use with REV100 modules
- * (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- * 000 -> All PSC2 pins are GIOPs
- * 001 -> CAN1/2 on PSC2 pins
- * Use for REV100 STK52xx boards
- * use PSC3: Bits 20:23 (mask: 0x00000300):
- * 0001 -> USB2
- * 0000 -> GPIO
- * use PSC6:
- * on STK52xx:
- * use as UART. Pins PSC6_0 to PSC6_3 are used.
- * Bits 9:11 (mask: 0x00700000):
- * 101 -> PSC6 : Extended POST test is not available
- * on MINI-FAP and TQM5200_IB:
- * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- * 000 -> PSC6 could not be used as UART, CODEC or IrDA
- * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- * tests.
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500114
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
- year */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
-#else
-#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#define CONFIG_SYS_CS2_START 0xE5000000
-#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
-#define CONFIG_SYS_CS2_CFG 0x0004D930
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#define SM501_FB_BASE 0xE0000000
-#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
-#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
-#define CONFIG_SYS_CS1_CFG 0x8F48FF70
-#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
-#define CONFIG_W7OLMC 1 /* ...specifically an LMC */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADADDR F0080000
-
-#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_IPADDR 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.168.1.2
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_REGINFO
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
-
-#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
-#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
-#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#endif
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 384000
-
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE {9600}
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
-/* resource configuration */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Set up values for external bus controller
- * used by cpu_init.c
- *-----------------------------------------------------------------------
- */
- /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
-#undef CONFIG_USE_PERWE
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* bank 0 is boot flash */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
-/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
-
-/* bank 1 is main flash */
-/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_EBC_PB1AP 0x05850240
-/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
-#define CONFIG_SYS_EBC_PB1CR 0xF00FC000
-
-/* bank 2 is RTC/NVRAM */
-/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_EBC_PB2AP 0x03000440
-/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_EBC_PB2CR 0xFC018000
-
-/* bank 3 is FPGA 0 */
-/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
-#define CONFIG_SYS_EBC_PB3AP 0x02000400
-/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
-#define CONFIG_SYS_EBC_PB3CR 0xFD01A000
-
-/* bank 4 is FPGA 1 */
-/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CONFIG_SYS_EBC_PB4AP 0x02000400
-/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_EBC_PB4CR 0xFD11A000
-
-/* bank 5 is FPGA 2 */
-/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CONFIG_SYS_EBC_PB5AP 0x02000400
-/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
-#define CONFIG_SYS_EBC_PB5CR 0xFD21A000
-
-/* bank 6 is unused */
-/* PB6AP = 0 */
-#define CONFIG_SYS_EBC_PB6AP 0x00000000
-/* PB6CR = 0 */
-#define CONFIG_SYS_EBC_PB6CR 0x00000000
-
-/* bank 7 is LED register */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
-/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
-#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-/*define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
-#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
-
-#else /* Use Boot Flash for environment variables */
-/*-----------------------------------------------------------------------
- * Flash EEPROM for environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
-
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
-
-/*
- * Init Memory Controller:
- */
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in RAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * FPGA(s) configuration
- */
-#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
-#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */
-#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
-#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
-#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
-#define CONFIG_W7OLMG 1 /* ...specifically an LMG */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADADDR F0080000
-
-#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_IPADDR 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.168.1.2
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DTT
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
-
-#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
-#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
-#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#endif
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 384000
-
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE {9600}
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
-/* resource configuration */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Set up values for external bus controller
- * used by cpu_init.c
- *-----------------------------------------------------------------------
- */
- /* use PerWE instead of PCI_INT ( these functions share a pin ) */
-#define CONFIG_USE_PERWE 1
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* bank 0 is boot flash */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
-/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
-
-/* bank 1 is main flash */
-/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_EBC_PB1AP 0x04850240
-/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
-#define CONFIG_SYS_EBC_PB1CR 0xF00FC000
-
-/* bank 2 is RTC/NVRAM */
-/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_EBC_PB2AP 0x03000440
-/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_EBC_PB2CR 0xFC018000
-
-/* bank 3 is FPGA 0 */
-/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
-#define CONFIG_SYS_EBC_PB3AP 0x02000400
-/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
-#define CONFIG_SYS_EBC_PB3CR 0xFD01A000
-
-/* bank 4 is SAM 8 bit range */
-/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CONFIG_SYS_EBC_PB4AP 0x02840380
-/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_EBC_PB4CR 0xFE878000
-
-/* bank 5 is SAM 16 bit range */
-/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
-#define CONFIG_SYS_EBC_PB5AP 0x05040d80
-/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
-#define CONFIG_SYS_EBC_PB5CR 0xFD87A000
-
-/* bank 6 is unused */
-/* PB6AP = 0 */
-#define CONFIG_SYS_EBC_PB6AP 0x00000000
-/* PB6CR = 0 */
-#define CONFIG_SYS_EBC_PB6CR 0x00000000
-
-/* bank 7 is LED register */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
-/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
-#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-/*define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
-#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
-
-#else /* Use Boot Flash for environment variables */
-/*-----------------------------------------------------------------------
- * Flash EEPROM for environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
-
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (ATMEL 24C04N)
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
-
-/*
- * Init Memory Controller:
- */
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in RAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * FPGA(s) configuration
- */
-#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
-#define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */
-#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
-#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
-#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
-#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
-#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
-#define CONFIG_AEVFIFO 1
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000 boot low (standard configuration with room for
- * max 64 MByte Flash ROM)
- * 0xFFF00000 boot high (for a backup copy of U-Boot)
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFC000000
-#endif
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#ifdef CONFIG_AEVFIFO
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-/* #define CONFIG_PCI_SCAN_SHOW 1 */
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-#endif /* CONFIG_AEVFIFO */
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_I2C)
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_TIMESTAMP /* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath} " \
- "console=ttyS0,${baudrate}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC05FFFF\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#ifdef CONFIG_TQM5200_REV100
-#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
-#else
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
-#endif
-
-/*
- * I2C clock frequency
- *
- * Please notice, that the resulting clock frequency could differ from the
- * configured value. This is because the I2C clock is derived from system
- * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
- * approximation allways lies below the configured value, never above.
- */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
- * also). For other EEPROMs configuration should be verified. On Mini-FAP the
- * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
- * same configuration could be used.
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
-
-/* use CFI flash driver if no module variant is spezified */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#endif
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- *
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- * Bit 0 (mask: 0x80000000): 1
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- * Use for REV200 STK52XX boards. Do not use with REV100 modules
- * (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- * 000 -> All PSC2 pins are GIOPs
- * 001 -> CAN1/2 on PSC2 pins
- * Use for REV100 STK52xx boards
- * use PSC6:
- * on STK52xx:
- * use as UART. Pins PSC6_0 to PSC6_3 are used.
- * Bits 9:11 (mask: 0x00700000):
- * 101 -> PSC6 : Extended POST test is not available
- * on MINI-FAP and TQM5200_IB:
- * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- * 000 -> PSC6 could not be used as UART, CODEC or IrDA
- * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- * tests.
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
-#else
-#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#define CONFIG_SYS_CS2_START 0xE5000000
-#define CONFIG_SYS_CS2_SIZE 0x80000 /* 512 kByte */
-#define CONFIG_SYS_CS2_CFG 0x0004D930
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#define SM501_FB_BASE 0xE0000000
-#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
-#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
-#define CONFIG_SYS_CS1_CFG 0x8F48FF70
-#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-#endif /* __CONFIG_H */
#endif /* CONFIG_MUSB_GADGET */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* Remove other SPL modes. */
+#undef CONFIG_SPL_YMODEM_SUPPORT
+#undef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_IS_IN_NAND
/* disable host part of MUSB in SPL */
#undef CONFIG_MUSB_HOST
/* disable EFI partitions and partition UUID support */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
--- /dev/null
+/*
+ * Sysam AMCORE board configuration
+ *
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AMCORE_CONFIG_H
+#define __AMCORE_CONFIG_H
+
+#define CONFIG_AMCORE
+#define CONFIG_HOSTNAME AMCORE
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_MCF530x
+#define CONFIG_M5307
+
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BOOTCOMMAND "bootm ffc20000"
+
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_AES
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_TIMER
+#define CONFIG_CMD_DIAG
+
+#define CONFIG_SYS_PROMPT "amcore $ "
+/* undef to save memory */
+#undef CONFIG_SYS_LONGHELP
+
+#if defined(CONFIG_CMD_KGDB)
+/* Console I/O buff. size */
+#define CONFIG_SYS_CBSIZE 1024
+#else
+#define CONFIG_SYS_CBSIZE 256
+#endif
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+
+#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START 0x0
+#define CONFIG_SYS_MEMTEST_END 0x1000000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_CLK 45000000
+#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
+/* Register Base Addrs */
+#define CONFIG_SYS_MBAR 0x10000000
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+/* size of internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE 0x1000000
+#define CONFIG_SYS_FLASH_BASE 0xffc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+/* amcore design has flash data bytes wired swapped */
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+/* reserve 128-4KB */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_SECT_SIZE 0x1000
+
+/* memory map space for linux boot data */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Cache Configuration
+ *
+ * Special 8K version 3 core cache.
+ * This is a single unified instruction/data cache.
+ * sdram - single region - no masks
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+ CF_ACR_EN)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
+ CF_CACR_EC)
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
+/* 4MB, AA=0,V=1 C/I BIT for errata */
+#define CONFIG_SYS_CS0_MASK 0x003f0001
+/* WS=10, AA=1, PS=16bit (10) */
+#define CONFIG_SYS_CS0_CTRL 0x1980
+/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
+#define CONFIG_SYS_CS1_BASE 0x3000
+#define CONFIG_SYS_CS1_MASK 0x00070001
+#define CONFIG_SYS_CS1_CTRL 0x0100
+
+#endif /* __AMCORE_CONFIG_H */
+
/*
- * Copyright (c) 2014 Marcel Ziswiler
+ * Copyright (c) 2014-2015 Marcel Ziswiler
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
-/* USB networking support */
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-
/* PCI host support */
-#undef CONFIG_PCI /* just define once Tegra PCIe support got merged */
+#define CONFIG_PCI
#define CONFIG_PCI_TEGRA
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
/* PCI networking support */
#define CONFIG_E1000
-#undef CONFIG_E1000_NO_NVM /* just define once E1000 driver got fixed */
+#define CONFIG_E1000_NO_NVM
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
+/* Miscellaneous commands */
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_FAT_WRITE
+
+/* Increase console I/O buffer size */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE 1024
+
+/* Increase arguments buffer size */
+#undef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Increase print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Increase maximum number of arguments */
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 32
+
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#ifndef __CONFIG_ASPENITE_H
#define __CONFIG_ASPENITE_H
+/*
+ * Generic board support
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
--- /dev/null
+/*
+ * bav335x.h
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_BAV335X_H
+#define __CONFIG_BAV335X_H
+
+#include <configs/ti_am335x_common.h>
+#define CONFIG_ENV_IS_NOWHERE
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_FIT
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+# ifdef CONFIG_ENABLE_VBOOT
+# define CONFIG_FIT_SIGNATURE
+# define CONFIG_RSA
+# endif
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
+
+#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
+#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+/* Custom script for NOR */
+#define CONFIG_SYS_LDSCRIPT "board/birdland/bav335x/u-boot.lds"
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${fdtaddr} u-boot-spl-os; " \
+ "nand read ${loadaddr} kernel; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NANDARGS ""
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+DEFAULT_LINUX_BOOT_ENV \
+"boot_fdt=try\0" \
+"bootpart=0:2\0" \
+"bootdir=\0" \
+"fdtdir=/dtbs\0" \
+"bootfile=zImage\0" \
+"fdtfile=undefined\0" \
+"console=ttyO0,115200n8\0" \
+"loadaddr=0x82000000\0" \
+"fdtaddr=0x88000000\0" \
+"rdaddr=0x88080000\0" \
+"initrd_high=0xffffffff\0" \
+"fdt_high=0xffffffff\0" \
+"partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+"optargs=\0" \
+"cmdline=\0" \
+"mmcdev=0\0" \
+"mmcpart=1\0" \
+"mmcroot=/dev/mmcblk0p2 ro\0" \
+"mmcrootfstype=ext4 rootwait fixrtc\0" \
+"rootpath=/export/rootfs\0" \
+"nfsopts=nolock\0" \
+"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+"ramroot=/dev/ram0 rw\0" \
+"ramrootfstype=ext2\0" \
+"mmcargs=setenv bootargs console=${console} ${optargs} " \
+ "root=${mmcroot} rootfstype=${mmcrootfstype} ${cmdline}\0" \
+"server_ip=192.168.1.100\0" \
+"gw_ip=192.168.1.1\0" \
+"netmask=255.255.255.0\0" \
+"hostname=\0" \
+"device=eth0\0" \
+"autoconf=off\0" \
+"root_dir=/home/userid/targetNFS\0" \
+"nfs_options=,vers=3\0" \
+"nfsrootfstype=ext4 rootwait fixrtc\0" \
+"nfsargs=setenv bootargs console=${console} ${optargs} " \
+ "root=/dev/nfs rw rootfstype=${nfsrootfstype} " \
+ "nfsroot=${nfsroot} ip=${ip} ${cmdline}\0" \
+"netargs=setenv bootargs console=${console} " \
+ "${optargs} root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp\0" \
+"bootenv=uEnv.txt\0" \
+"script=boot.scr\0" \
+"scriptfile=${script}\0" \
+"loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
+"bootscript=echo Running bootscript from mmc${bootpart} ...; " \
+ "source ${loadaddr}\0" \
+ "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
+"importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t -r $loadaddr $filesize\0" \
+"ramargs=setenv bootargs console=${console} " \
+ "${optargs} root=${ramroot} rootfstype=${ramrootfstype}\0" \
+"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadrd=load mmc ${bootpart} ${rdaddr} " \
+ "${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \
+"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; " \
+ "load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \
+"mmcboot=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "gpio set 54;" \
+ "setenv bootpart ${mmcdev}:1; " \
+ "if test -e mmc ${bootpart} /etc/fstab; then " \
+ "setenv mmcpart 1;" \
+ "fi; " \
+ "echo Checking for: /uEnv.txt ...;" \
+ "if test -e mmc ${bootpart} /uEnv.txt; then " \
+ "if run loadbootenv; then " \
+ "gpio set 55;" \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "echo Checking if uenvcmd is set ...;" \
+ "if test -n ${uenvcmd}; then " \
+ "gpio set 56; " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "echo Checking if client_ip is set ...;" \
+ "if test -n ${client_ip}; then " \
+ "if test -n ${dtb}; then " \
+ "setenv fdtfile ${dtb};" \
+ "echo using ${fdtfile} ...;" \
+ "fi;" \
+ "gpio set 56; " \
+ "if test -n ${uname_r}; then " \
+ "echo Running nfsboot_uname_r ...;" \
+ "run nfsboot_uname_r;" \
+ "fi;" \
+ "echo Running nfsboot ...;" \
+ "run nfsboot;" \
+ "fi;" \
+ "fi; " \
+ "echo Checking for: /${script} ...;" \
+ "if test -e mmc ${bootpart} /${script}; then " \
+ "gpio set 55;" \
+ "setenv scriptfile ${script};" \
+ "run loadbootscript;" \
+ "echo Loaded script from ${scriptfile};" \
+ "gpio set 56; " \
+ "run bootscript;" \
+ "fi; " \
+ "echo Checking for: /boot/${script} ...;" \
+ "if test -e mmc ${bootpart} /boot/${script}; then " \
+ "gpio set 55;" \
+ "setenv scriptfile /boot/${script};" \
+ "run loadbootscript;" \
+ "echo Loaded script from ${scriptfile};" \
+ "gpio set 56; " \
+ "run bootscript;" \
+ "fi; " \
+ "echo Checking for: /boot/uEnv.txt ...;" \
+ "for i in 1 2 3 4 5 6 7 ; do " \
+ "setenv mmcpart ${i};" \
+ "setenv bootpart ${mmcdev}:${mmcpart};" \
+ "if test -e mmc ${bootpart} /boot/uEnv.txt; then " \
+ "gpio set 55;" \
+ "load mmc ${bootpart} ${loadaddr} " \
+ "/boot/uEnv.txt;" \
+ "env import -t ${loadaddr} ${filesize};" \
+ "echo Loaded environment from /boot/uEnv.txt;" \
+ "if test -n ${dtb}; then " \
+ "setenv fdtfile ${dtb};" \
+ "echo Using: dtb=${fdtfile} ...;" \
+ "fi;" \
+ "echo Checking if uname_r is set in " \
+ "/boot/uEnv.txt...;" \
+ "if test -n ${uname_r}; then " \
+ "gpio set 56; " \
+ "echo Running uname_boot ...;" \
+ "setenv mmcroot /dev/mmcblk${mmcdev}" \
+ "p${mmcpart} ro;" \
+ "run uname_boot;" \
+ "fi;" \
+ "fi;" \
+ "done;" \
+ "fi;\0" \
+"netboot=echo Booting from network ...; " \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} ${fdtfile}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot=echo Booting from ${server_ip} ...; " \
+ "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+ "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+ ":${device}:${autoconf}; " \
+ "setenv autoload no; " \
+ "setenv serverip ${server_ip}; " \
+ "setenv ipaddr ${client_ip}; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} dtbs/${fdtfile}; " \
+ "run nfsargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot_uname_r=echo Booting from ${server_ip} ...; " \
+ "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+ "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+ ":${device}:${autoconf}; " \
+ "setenv autoload no; " \
+ "setenv serverip ${server_ip}; " \
+ "setenv ipaddr ${client_ip}; " \
+ "tftp ${loadaddr} vmlinuz-${uname_r}; " \
+ "tftp ${fdtaddr} dtbs/${uname_r}/${fdtfile}; " \
+ "run nfsargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"ramboot=echo Booting from ramdisk ...; " \
+ "run ramargs; " \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+"findfdt="\
+ "if test $board_rev = B; then " \
+ "setenv fdtfile birdland_bav335b.dtb; " \
+ "setenv fdtbase am335x-boneblack; fi; " \
+ "if test $board_rev = A; then " \
+ "setenv fdtfile birdland_bav335a.dtb; " \
+ "setenv fdtbase am335x-boneblack; fi; " \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0" \
+"uname_boot="\
+ "setenv bootdir /boot; " \
+ "setenv bootfile vmlinuz-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
+ "echo loading ${bootdir}/${bootfile} ...; "\
+ "run loadimage;" \
+ "setenv fdtdir /boot/dtbs/${uname_r}; " \
+ "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \
+ "if test -e mmc ${bootpart} ${fdtdir}/" \
+ "${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /boot/dtb-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${fdtdir}" \
+ "/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /boot/dtbs; " \
+ "if test -e mmc ${bootpart} ${fdtdir}" \
+ "/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "echo; echo unable to find " \
+ "[${fdtfile}] " \
+ "did you name it correctly?" \
+ "echo booting fallback " \
+ "[/boot/dtbs/" \
+ "${uname_r}" \
+ "/${fdtbase}.dtb]...;" \
+ "setenv fdtdir /boot/dtbs/" \
+ "${uname_r}; " \
+ "setenv fdtfile " \
+ "${fdtbase}.dtb; " \
+ "run loadfdt;" \
+ "fi;" \
+ "fi;" \
+ "fi;" \
+ "fi;" \
+ "fi; " \
+ "setenv rdfile initrd.img-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \
+ "echo loading ${bootdir}/${rdfile} ...; "\
+ "run loadrd;" \
+ "if test -n ${uuid}; then " \
+ "setenv mmcroot UUID=${uuid} ro;" \
+ "fi;" \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} " \
+ "${fdtaddr}] ... ;" \
+ "bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \
+ "else " \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "fi;" \
+"fi;\0" \
+ NANDARGS \
+ DFUARGS
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+ "gpio set 53; " \
+ "i2c mw 0x24 1 0x3e; " \
+ "run findfdt; " \
+ "setenv mmcdev 0; " \
+ "setenv bootpart 0:1; " \
+ "run mmcboot;" \
+ "gpio clear 56; " \
+ "gpio clear 55; " \
+ "gpio clear 54; " \
+ "setenv mmcdev 1; " \
+ "setenv bootpart 1:1; " \
+ "run mmcboot;"
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* USB gadget RNDIS */
+#define CONFIG_SPL_MUSB_NEW_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#endif
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define MTDIDS_DEFAULT "nand0=nand.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=nand.0:" \
+ "128k(NAND.SPL)," \
+ "128k(NAND.SPL.backup1)," \
+ "128k(NAND.SPL.backup2)," \
+ "128k(NAND.SPL.backup3)," \
+ "256k(NAND.u-boot-spl-os)," \
+ "1m(NAND.u-boot)," \
+ "128k(NAND.u-boot-env)," \
+ "128k(NAND.u-boot-env.backup1)," \
+ "8m(NAND.kernel)," \
+ "-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+#endif /* !CONFIG_NAND */
+
+/*
+ * For NOR boot, we must set this to the start of where NOR is mapped
+ * in memory.
+ */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+#endif
+
+/*
+ * USB configuration. We enable MUSB support, both for host and for
+ * gadget. We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each. Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* Fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#endif
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/* USB TI's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#endif /* CONFIG_MUSB_GADGET */
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+/* General network SPL */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "BAV335x U-Boot SPL"
+#endif
+
+/* USB Device Firmware Update support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_CMD_DFU
+#define DFU_ALT_INFO_MMC \
+ "dfu_alt_info_mmc=" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "MLO fat 0 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x400;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 0 1;" \
+ "spl-os-image fat 0 1;" \
+ "u-boot.img fat 0 1;" \
+ "uEnv.txt fat 0 1\0"
+#ifdef CONFIG_NAND
+#define CONFIG_DFU_NAND
+#define DFU_ALT_INFO_NAND \
+ "dfu_alt_info_nand=" \
+ "SPL part 0 1;" \
+ "SPL.backup1 part 0 2;" \
+ "SPL.backup2 part 0 3;" \
+ "SPL.backup3 part 0 4;" \
+ "u-boot part 0 5;" \
+ "u-boot-spl-os part 0 6;" \
+ "kernel part 0 8;" \
+ "rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+#define CONFIG_DFU_RAM
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "kernel ram 0x80200000 0xD80000;" \
+ "fdt ram 0x80F80000 0x80000;" \
+ "ramdisk ram 0x81000000 0x4000000\0"
+#define DFUARGS \
+ "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_RAM \
+ DFU_ALT_INFO_NAND
+#endif
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x020000 : SPL (128KiB)
+ * 0x020000 - 0x0A0000 : U-Boot (512KiB)
+ * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
+ * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
+ * 0x0E0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
+#define MTDIDS_DEFAULT "nor0=m25p80-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \
+ "512k(u-boot),128k(u-boot-env1)," \
+ "128k(u-boot-env2),3464k(kernel)," \
+ "-(rootfs)"
+#elif defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET 0x0
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* SPI flash. */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/*
+ * NOR Size = 16 MiB
+ * Number of Sectors/Blocks = 128
+ * Sector Size = 128 KiB
+ * Word length = 16 bits
+ * Default layout:
+ * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
+ * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
+ * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
+ * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
+ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
+ */
+#if defined(CONFIG_NOR)
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:" \
+ "512k(u-boot)," \
+ "128k(u-boot-env1)," \
+ "128k(u-boot-env2)," \
+ "4m(kernel),-(rootfs)"
+#endif
+#endif /* NOR support */
+
+#endif /* ! __CONFIG_AM335X_EVM_H */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_GIGE /* per-board part of CPSW */
#define CONFIG_PHYLIB
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
#define CONFIG_SUPPORT_EMMC_BOOT
#define MACH_TYPE_BEAVER 4597 /* not yet in mach-types.h */
#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
+#define BUR_COMMON_ENV \
+"defaultip=192.168.60.253\0" \
+"defaultsip=192.168.60.254\0" \
+"netconsole=echo switching to network console ...; " \
+"if dhcp; then " \
+"setenv ncip ${serverip}; else " \
+"setenv ncip 192.168.60.254; " \
+"setenv serverip 192.168.60.254; " \
+"setenv gatewayip 192.168.60.254; " \
+"setenv ipaddr 192.168.60.1; " \
+"fi;" \
+"setenv netdisplay0 '" \
+"setcurs 1 9; puts myip; setcurs 10 9; puts ${ipaddr};" \
+"setcurs 1 10;puts serverip; setcurs 10 10; puts ${serverip};" \
+"run netdisplay0; " \
+"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
+
+#define CONFIG_CMD_TIME
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4)
+#define CONFIG_CMD_UNZIP
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_24BMP
+#define CONFIG_BMP_32BPP
+
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_AM33XX
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_NET_RETRY_COUNT 4
+#define CONFIG_NET_RETRY_COUNT 2
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
-
+/* Network console */
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */
/*
* SPL related defines. The Public RAM memory map the ROM defines the
* area between 0x402F0400 and 0x4030B800 as a download area and
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_MALLOC_LEN (5120 << 10)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
/* As stated above, the following choices are optional. */
#define CONFIG_SYS_LONGHELP
#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_CM_T3517 /* working with CM-T3517 */
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_TEGRA_UARTA_SDIO1
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* SD/MMC support */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/*
- * Copyright (c) 2013-2014 Stefan Agner
+ * Copyright (c) 2013-2015 Stefan Agner
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "tegra30-common.h"
+/* High-level configuration options */
#define V_PROMPT "Colibri T30 # "
#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30"
-/* Board-specific config */
+/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
+/* Miscellaneous commands */
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_FAT_WRITE
+
+/* Increase console I/O buffer size */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE 1024
+
+/* Increase arguments buffer size */
+#undef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Increase print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Increase maximum number of arguments */
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 32
+
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
#define MACH_TYPE_OMAP3_CPS 2751
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
/*
* High Level Configuration Options
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Add target to build it automatically upon "make" */
+#define CONFIG_BUILD_TARGET "u-boot.kwb"
/*
* Commands configuration
#ifndef _CONFIG_EDMINIV2_H
#define _CONFIG_EDMINIV2_H
+/* general settings */
+#define CONFIG_SYS_GENERIC_BOARD
+
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NOR_SUPPORT
+#define CONFIG_SPL_TEXT_BASE 0xffff0000
+#define CONFIG_SPL_MAX_SIZE 0x0000fff0
+#define CONFIG_SPL_STACK 0x00020000
+#define CONFIG_SPL_BSS_START_ADDR 0x00020000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
+#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_UBOOT_BASE 0xfff90000
+#define CONFIG_SYS_UBOOT_START 0x00800000
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+
/*
* Version number information
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE 0xfff80000
-#define CONFIG_SYS_FLASH_SECTSZ \
- {16384, 8192, 8192, 32768, \
- 65536, 65536, 65536, 65536, 65536, 65536, 65536}
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_USE_ARCH_MEMSET
+
/* Keep L2 Cache Disabled */
#define CONFIG_CMD_CACHE
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_GENERIC_BOARD
/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
+++ /dev/null
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messatechnik GmbH
- *
- * (C) Copyright 2009
- * Jon Smirl <jonsmirl@gmail.com>
- *
- * (C) Copyright 2009
- * Eric Millbrandt, DEKA Research and Development Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_BOARDINFO "galaxy5200"
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000 boot high (standard configuration)
- * 0xFE000000 boot low
- * 0x00100000 boot from RAM (for testing only) does not work
- */
-#ifdef CONFIG_galaxy5200_LOWBOOT
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#endif
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */
- /* define gps port conf. */
- /* register later on to */
- /* enable UART function! */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FAT
-
-#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
-#define CONFIG_SYS_LOWBOOT 1
-#endif
-/* RAMBOOT will be defined automatically in memory section */
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
- "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
- /* even with bootdelay=0 */
-#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */
-#define CONFIG_RESET_TO_RETRY
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome to U-Boot;"\
- "echo"
-
-#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \
- "bootm ff040000 ff900000 fffc0000"
-#define CONFIG_BOOTARGS "console=ttyPSC0,115200"
-#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#define CONFIG_SYS_XLB_PIPELINING 1
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */
-
-/*
- * EEPROM CAT24WC32 configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
-#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_SIZE 4096
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Flash configuration
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xfe000000
-/*
- * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
- * variable defined
- */
-#define CONFIG_SYS_FLASH_SIZE 0x02000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
- /* (= chip selects) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Use hardware protection. This seems required, as the BDI uses hardware
- * protection. Without this, U-Boot can't work with this sectors as its
- * protection is software only by default.
- */
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-/*
- * Environment settings
- */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
- /* beginning of the EEPROM */
-#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
-
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * SDRAM configuration
- */
-#define SDRAM_DDR 1
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x71500F00
-#define SDRAM_CONFIG1 0x73711930
-#define SDRAM_CONFIG2 0x47770000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
- /* bootloader or debugger config */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-
-/* End of used area in SPRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* Chip Select configuration for NAND flash */
-#define CONFIG_SYS_CS1_START 0x20000000
-#define CONFIG_SYS_CS1_SIZE 0x90000
-#define CONFIG_SYS_CS1_CFG 0x00025b00
-
-/* Chip Select configuration for Epson S1D13513 */
-#define CONFIG_SYS_CS3_START 0x10000000
-#define CONFIG_SYS_CS3_SIZE 0x400000
-#define CONFIG_SYS_CS3_CFG 0xffff3d10
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR 0x01
-#define CONFIG_NO_AUTOLOAD 1
-
-/*
- * GPIO configuration
- *
- * GPS port configuration
- *
- * [29:31] = 01x
- * AC97 on PSC1
- * PSC1_0 -> AC97 SDATA out
- * PSC1_1 -> AC97 SDTA in
- * PSC1_2 -> AC97 SYNC out
- * PSC1_3 -> AC97 bitclock out
- * PSC1_4 -> AC97 reset out
- *
- * [28] = Reserved
- *
- * [25:27] = 110
- * SPI on PSC2
- * PSC2_0 -> MOSI
- * PSC2_1 -> MISO
- * PSC2_2 -> n/a
- * PSC2_3 -> CLK
- * PSC2_4 -> SS
- *
- * [24] = Reserved
- *
- * [20:23] = 0001
- * USB on PSC3
- * PSC3_0 -> USB_OE OE out
- * PSC3_1 -> USB_TXN Tx- out
- * PSC3_2 -> USB_TXP Tx+ out
- * PSC3_3 -> USB_TXD
- * PSC3_4 -> USB_RXP Rx+ in
- * PSC3_5 -> USB_RXN Rx- in
- * PSC3_6 -> USB_PWR PortPower out
- * PSC3_7 -> USB_SPEED speed out
- * PSC3_8 -> USB_SUSPEND suspend
- * PSC3_9 -> USB_OVRCURNT overcurrent in
- *
- * [18:19] = 10
- * Two UARTs
- *
- * [17] = 0
- * USB differential mode
- *
- * [16] = 1
- * PCI disabled
- *
- * [12:15] = 0101
- * Ethernet 100Mbit with MD
- * ETH_0 -> ETH Txen
- * ETH_1 -> ETH TxD0
- * ETH_2 -> ETH TxD1
- * ETH_3 -> ETH TxD2
- * ETH_4 -> ETH TxD3
- * ETH_5 -> ETH Txerr
- * ETH_6 -> ETH MDC
- * ETH_7 -> ETH MDIO
- * ETH_8 -> ETH RxDv
- * ETH_9 -> ETH RxCLK
- * ETH_10 -> ETH Collision
- * ETH_11 -> ETH TxD
- * ETH_12 -> ETH RxD0
- * ETH_13 -> ETH RxD1
- * ETH_14 -> ETH RxD2
- * ETH_15 -> ETH RxD3
- * ETH_16 -> ETH Rxerr
- * ETH_17 -> ETH CRS
- *
- * [9:11] = 111
- * SPI on PSC6
- * PSC6_0 -> MISO
- * PSC6_1 -> SS#
- * PSC6_2 -> MOSI
- * PSC6_3 -> CLK
- *
- * [8] = 0
- * IrDA/USB 48MHz clock generated internally
- *
- * [6:7] = 01
- * ATA chip selects on csb_4/5
- * CSB_4 -> ATA_CS0 out
- * CSB_5 -> ATA_CS1 out
- *
- * [5] = 1
- * PSC3_4 is used as CS6
- *
- * [4] = 1
- * PSC3_5 is used as CS7
- *
- * [2:3] = 00
- * No Alternatives
- *
- * [1] = 0
- * gpio_wkup_7 is GPIO
- *
- * [0] = 0
- * gpio_wkup_6 is GPIO
- *
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_CRC32_VERIFY 1
-
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-#define CONFIG_VERSION_VARIABLE 1
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-/* no burst access on the LPB */
-#define CONFIG_SYS_CS_BURST 0x00000000
-/* one deadcycle for the 33MHz statemachine */
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
-
-#define CONFIG_SYS_BOOTCS_CFG 0x0002d900
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*
- * USB settings
- */
-#define CONFIG_USB_CLOCK 0x0001bbbb
-/* USB is on PSC3 */
-#define CONFIG_PSC3_USB
-#define CONFIG_USB_CONFIG 0x00000100
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/*
- * IDE/ATA stuff Supports IDE harddisk
- */
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-#define CONFIG_ATAPI 1
-
-/* we enable IDE and FAT support, so we also need partition support */
-#define CONFIG_DOS_PARTITION 1
-
-/*
- * Open Firmware flat tree
- */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,5200@0"
-#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
-#define OF_SOC "soc5200@f0000000"
-#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600"
-
-#endif /* __CONFIG_H */
#define MACH_TYPE_SHEEVAD 2625
#endif
+/*
+ * Generic board support
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
-
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/*
* Board
*/
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_BARIX_IPAM390
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
#ifndef __CONFIG_KM8309_COMMON_H
#define __CONFIG_KM8309_COMMON_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_KM8321_COMMON_H
#define __CONFIG_KM8321_COMMON_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/* KMBEC FPGA (PRIO) */
#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
+++ /dev/null
-/*
- * (C) Copyright 2007-2009
- * Larry Johnson, lrj@acm.org
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * korat.h - configuration for Korat board
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_SYS_CLK_FREQ 33333333
-
-#ifdef CONFIG_KORAT_PERMANENT
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#else
-#define CONFIG_SYS_TEXT_BASE 0xF7F60000
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*
- * Manufacturer's information serial EEPROM parameters
- */
-#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
-#define MAN_INFO_FIELD 2
-#define MAN_INFO_LENGTH 9
-#define MAN_MAC_ADDR_FIELD 3
-#define MAN_MAC_ADDR_LENGTH 12
-
-/*
- * Base addresses -- Note these are effective addresses where the actual
- * resources get mapped (not physical addresses).
- */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH0_SIZE 0x01000000
-#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
-#define CONFIG_SYS_FLASH1_TOP 0xF8000000
-#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
-#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
-
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-#define CONFIG_SYS_CPLD_BASE 0xc0000000
-
-/*
- * Initial RAM & stack pointer
- */
-/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
-#undef CONFIG_SYS_INIT_RAM_DCACHE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
-#define CONFIG_DDR_ECC /* Use ECC when available */
-#define SPD_EEPROM_ADDRESS {0x50}
-#define CONFIG_PROG_SDRAM_TLB
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */
- /* per 440EPx Errata CHIP_11 */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T60 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/* I2C SYSMON (LM73) */
-#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
-#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_MIN_TEMP -30
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_HOSTNAME korat
-
-/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "u_boot=korat/u-boot.bin\0" \
- "load=tftp 200000 ${u_boot}\0" \
- "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
- "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
- "F7F60000 F7FBFFFF\0" \
- "upd=run load update\0" \
- "bootfile=korat/uImage\0" \
- "dtb=korat/korat.dtb\0" \
- "kernel_addr=F4000000\0" \
- "ramdisk_addr=F4400000\0" \
- "dtb_addr=F41E0000\0" \
- "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
- "cp.b ${fileaddr} F4000000 ${filesize}\0" \
- "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
- "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
- "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
- "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
- "${dtb}\0" \
- "rd_size=73728\0" \
- "ramargs=setenv bootargs root=/dev/ram rw " \
- "ramdisk_size=${rd_size}\0" \
- "usbdev=sda1\0" \
- "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
- "rootpath=/opt/eldk/ppc_4xxFP\0" \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "pciclk=33\0" \
- "addide=setenv bootargs ${bootargs} ide=reverse " \
- "idebus=${pciclk}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_cf=run usbargs addide addip addtty; " \
- "bootm ${kernel_addr} - ${dtb_addr}\0" \
- "flash_nfs=run nfsargs addide addip addtty; " \
- "bootm ${kernel_addr} - ${dtb_addr}\0" \
- "flash_self=run ramargs addip addtty; " \
- "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_cf"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
-#define CONFIG_PHY_DYNAMIC_ANEG 1
-
-#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */
- /* buffers & descriptors */
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 3
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_USB
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ECC | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_SPR | \
- CONFIG_SYS_POST_UART)
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*
- * Korat-specific options
- */
-#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
- /* CONFIG_SYS_PCI_MEMBASE */
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data have to be in the
- * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
- * during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
-#define CONFIG_SYS_EBC_PB0AP 0x04017300
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
-#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
-#define CONFIG_SYS_EBC_PB0AP 0x04017300
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
-#else
-#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
-#endif
-
-/* Memory Bank 1 (NOR-FLASH) initialization */
-#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
-#define CONFIG_SYS_EBC_PB1AP 0x04017300
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
-#else
-#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
-#endif
-
-/* Memory Bank 2 (CPLD) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x04017300
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
-
-/*
- * GPIO Setup
- *
- * Korat GPIO usage:
- *
- * Init.
- * Pin Source I/O value Function
- * ------ ------ --- ----- ---------------------------------
- * GPIO00 Alt1 I/O x PerAddr07
- * GPIO01 Alt1 I/O x PerAddr06
- * GPIO02 Alt1 I/O x PerAddr05
- * GPIO03 GPIO x x GPIO03 to expansion bus connector
- * GPIO04 GPIO x x GPIO04 to expansion bus connector
- * GPIO05 GPIO x x GPIO05 to expansion bus connector
- * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
- * GPIO07 Alt1 O x PerCS2 (CPLD)
- * GPIO08 Alt1 O x PerCS3 to expansion bus connector
- * GPIO09 Alt1 O x PerCS4 to expansion bus connector
- * GPIO10 Alt1 O x PerCS5 to expansion bus connector
- * GPIO11 Alt1 I x PerErr
- * GPIO12 GPIO O 0 ATMega !Reset
- * GPIO13 GPIO x x Test Point 2 (TP2)
- * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
- * GPIO15 GPIO O 0 CPU Run LED !On
- * GPIO16 Alt1 O x GMC1TxD0
- * GPIO17 Alt1 O x GMC1TxD1
- * GPIO18 Alt1 O x GMC1TxD2
- * GPIO19 Alt1 O x GMC1TxD3
- * GPIO20 Alt1 I x RejectPkt0
- * GPIO21 Alt1 I x RejectPkt1
- * GPIO22 GPIO I x PGOOD_DDR
- * GPIO23 Alt1 O x SCPD0
- * GPIO24 Alt1 O x GMC0TxD2
- * GPIO25 Alt1 O x GMC0TxD3
- * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
- * GPIO27 GPIO O 0 PHY #0 1000BASE-X select
- * GPIO28 GPIO O 0 PHY #1 1000BASE-X select
- * GPIO29 GPIO I x Test jumper !Present
- * GPIO30 GPIO I x SFP module #0 !Present
- * GPIO31 GPIO I x SFP module #1 !Present
- *
- * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
- * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
- * GPIO34 Alt2 I x !UART1_CTS
- * GPIO35 Alt2 O x !UART1_RTS
- * GPIO36 Alt1 I x !UART0_CTS
- * GPIO37 Alt1 O x !UART0_RTS
- * GPIO38 Alt2 O x UART1_Tx
- * GPIO39 Alt2 I x UART1_Rx
- * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
- * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
- * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
- * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
- * GPIO44 xxxx x x (grounded through pulldown)
- * GPIO45 GPIO O 0 PHY #0 Enable
- * GPIO46 GPIO O 0 PHY #1 Enable
- * GPIO47 GPIO I x Reset switch !Pressed
- * GPIO48 GPIO I x Shutdown switch !Pressed
- * GPIO49 xxxx x x (reserved for trace port)
- * . . . . .
- * . . . . .
- * . . . . .
- * GPIO63 xxxx x x (reserved for trace port)
- */
-
-#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
-#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
-#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
-#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
-#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
-#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
-#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
-#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
-#define CONFIG_SYS_GPIO_PHY0_EN 45
-#define CONFIG_SYS_GPIO_PHY1_EN 46
-#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
-
-/*
- * PPC440 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#endif /* __CONFIG_H */
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_NOSTDOUT
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP LCD_COLOR32
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SPL_MMC_SUPPORT
-#undef CONFIG_SPL_OS_BOOT
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
-
-/* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
-
-#endif /* CONFIG_SPL_OS_BOOT */
-
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE (64 << 10)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=0\0" \
- "loadaddr=0x80100000\0" \
- "bootfile=arimg\0" \
- "usbboot=echo Booting from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 ${loadaddr} ${bootfile}; " \
- "usb stop; " \
- "go ${loadaddr};\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload 0; " \
- "dhcp; " \
- "tftp ${loadaddr} arimg; " \
- "go ${loadaddr}\0" \
- "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 0x80000000 updateubootusb.img; " \
- "source;\0" \
- "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
- "setenv autoload 0; " \
- "dhcp;" \
- "tftp 0x80000000 updateUBOOT.img;" \
- "source;\0"
+BUR_COMMON_ENV \
+"vx_romfsbase=0x800E0000\0" \
+"vx_romfssize=0x20000\0" \
+"vx_memtop=0x8FBEF000\0" \
+"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \
+"autoload=0\0" \
+"loadaddr=0x80100000\0" \
+"logoaddr=0x82000000\0" \
+"defaultARlen=0x8000\0" \
+"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \
+"defaultAR=run loadromfs; run loaddefaultAR; go ${loadaddr}\0" \
+"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \
+ "bmp display ${logoaddr} 0 0\0" \
+"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \
+ "bmp display ${logoaddr} 0 0\0" \
+"mmcboot=echo booting AR from eMMC-flash ...; "\
+ "run logo0 || run logo1; " \
+ "run loadromfs; " \
+ "fatload mmc 0:1 ${loadaddr} arimg && go ${loadaddr}; " \
+ "run defaultAR;\0" \
+"netboot=echo booting AR from network ...; " \
+ "run loadromfs; " \
+ "tftp ${loadaddr} arimg && go ${loadaddr}; " \
+ "puts 'networkboot failed!';\0" \
+"usbupdate=echo updating u-boot from usb ...; " \
+ "usb start; " \
+ "fatload usb 0 0x80000000 updateubootusb.img && source; " \
+ "puts 'usbupdate failed!'\0" \
+"netscript=echo running script from network (tftp) ...; " \
+ "tftp 0x80000000 netscript.img && source; " \
+ "puts 'netscript load failed!'\0" \
+"netupdate=tftp ${loadddr} MLO && mmc write ${loadaddr} 100 100; " \
+ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 300\0" \
+"netupdatedefaultAR=echo updating defaultAR from network (tftp) ...; " \
+ "if tftp 0x80100000 arimg.bin; " \
+ "then mmc write 0x80100000 800 ${defaultARlen}; " \
+ "else setcurs 1 8; puts 'defAR update failed (tftp)!'; fi;\0" \
+"netupdateROMFS=echo updating romfs from network (tftp) ...; " \
+ "if tftp 0x80100000 romfs.bin; " \
+ "then mmc write 0x80100000 700 100; " \
+ "else setcurs 1 8; puts 'romfs update failed (tftp)!'; fi;\0"
+
#endif /* !CONFIG_SPL_BUILD*/
#define CONFIG_BOOTCOMMAND \
"run usbupdate;"
-#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+#define CONFIG_BOOTDELAY 0
/* undefine command which we not need here */
-#undef CONFIG_BOOTM_LINUX
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
-#undef CONFIG_GZIP
-#undef CONFIG_ZLIB
+#undef CONFIG_CMD_CRC32
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMD_BOOTZ
/* USB configuration */
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#ifdef CONFIG_MUSB_HOST
#define CONFIG_CMD_USB
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
+/* Errata fixes */
+#define CONFIG_ARM_ERRATA_828024
+#define CONFIG_ARM_ERRATA_826974
+
/* Link Definitions */
#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_OMAP3_MCX /* working with mcx */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define MACH_TYPE_MCX 3656
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#define CONFIG_OF_LIBFDT
#define CONFIG_FIT
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#define CONFIG_MX35
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_GENERIC_BOARD
/* Set TEXT at the beginning of the NOR flash */
#define CONFIG_SYS_TEXT_BASE 0xA0000000
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#include <asm/arch/mem.h>
#include <linux/stringify.h>
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
--- /dev/null
+/*
+ * Configuration settings for the QUIPOS Cairo board.
+ *
+ * Copyright (C) DENX GmbH
+ *
+ * Author :
+ * Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Derived from EVM code by
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Itself derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Also derived from include/configs/omap3_beagle.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __OMAP3_CAIRO_CONFIG_H
+#define __OMAP3_CAIRO_CONFIG_H
+
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs. We use this rather than the inherited defines from
+ * ti_armv7_common.h for backwards compatibility.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+
+#define CONFIG_NAND
+
+#include <configs/ti_omap3_common.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_ENV_OVERWRITE
+
+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* Probe all devices */
+#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
+
+#define CONFIG_NAND
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+
+/* Disable some commands */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_LED 1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST 1
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+ /* devices */
+/* override default CONFIG_BOOTDELAY */
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "machid=ffffffff\0" \
+ "fdt_high=0x87000000\0" \
+ "baudrate=115200\0" \
+ "ethaddr=00:50:C2:7E:90:F0\0" \
+ "fec_addr=00:50:C2:7E:90:F0\0" \
+ "netmask=255.255.255.0\0" \
+ "ipaddr=192.168.2.9\0" \
+ "gateway=192.168.2.1\0" \
+ "serverip=192.168.2.10\0" \
+ "nfshost=192.168.2.10\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "bootargs_mmc_ramdisk=mem=128M " \
+ "console=ttyO1,115200n8 " \
+ "root=/dev/ram0 rw " \
+ "initrd=0x81600000,16M " \
+ "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
+ "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
+ "mmcboot=mmc init; " \
+ "fatload mmc 0 0x80000000 uImage; " \
+ "fatload mmc 0 0x81600000 ramdisk.gz; " \
+ "setenv bootargs ${bootargs_mmc_ramdisk}; " \
+ "bootm 0x80000000\0" \
+ "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
+ "root=/dev/nfs " \
+ "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
+ "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
+ "omap_vout.vid1_static_vrfb_alloc=y\0" \
+ "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
+ "bootm 0x80000000\0" \
+ "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
+ "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
+ "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
+ "omapfb.rotate_type=1\0" \
+ "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
+ "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
+ "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
+ "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
+ "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
+ "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
+ "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
+ "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
+ "nand erase 0 20000; " \
+ "fatload mmc 0 0x81600000 MLO; " \
+ "nandecc hw; " \
+ "nand write.i 0x81600000 0 20000;\0" \
+ "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
+ "nand erase 80000 40000; " \
+ "fatload mmc 0 0x81600000 u-boot.bin; " \
+ "nandecc sw; " \
+ "nand write.i 0x81600000 80000 40000;\0" \
+ "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
+ "nand erase 280000 300000; " \
+ "fatload mmc 0 0x81600000 uImage; " \
+ "nandecc sw; " \
+ "nand write.i 0x81600000 280000 300000;\0" \
+ "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
+ "nandecc sw; " \
+ "nand write.jffs2 0x680000 0xFF ${filesize}; " \
+ "nand erase 680000 ${filesize}; " \
+ "nand write.jffs2 81600000 680000 ${filesize};\0" \
+ "flash_scrub=nand scrub; " \
+ "run flash_xloader; " \
+ "run flash_uboot; " \
+ "run flash_kernel; " \
+ "run flash_rootfs;\0" \
+ "flash_all=run ledred; " \
+ "nand erase.chip; " \
+ "run ledorange; " \
+ "run flash_xloader; " \
+ "run flash_uboot; " \
+ "run flash_kernel; " \
+ "run flash_rootfs; " \
+ "run ledgreen; " \
+ "run boot_nand; \0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
+ "else run boot_nand; fi"
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+#define CONFIG_OMAP3_SPI
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/* Defines for SPL */
+#define CONFIG_SPL_OMAP3_ID_NAND
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+
+/* env defaults */
+#define CONFIG_BOOTFILE "uImage"
+
+/* Override OMAP3 common serial console configuration from UART3
+ * to UART2.
+ *
+ * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
+ * are needed and peripheral clocks for UART2 must be enabled in
+ * function per_clocks_enable().
+ */
+#undef CONFIG_CONS_INDEX
+#define CONFIG_CONS_INDEX 2
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SYS_NS16550_COM3
+#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
+#undef CONFIG_SERIAL3
+#define CONFIG_SERIAL2
+#endif
+
+/* Keep old prompt in case some existing script depends on it */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "Cairo # "
+
+/* Provide MACH_TYPE for compatibility with non-DT kernels */
+#define MACH_TYPE_OMAP3_CAIRO 3063
+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
+ /* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
+ CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+#endif /* __OMAP3_CAIRO_CONFIG_H */
#define __OMAP3EVM_CONFIG_H
#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
* Supported U-boot commands
#define CONFIG_OMAP /* This is TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#define __OMAP3_EVM_QUICK_MMC_H
#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
* Supported U-boot commands
#define __OMAP3_EVM_QUICK_NAND_H
#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
* Supported U-boot commands
#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80400000
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* NOTE: these #defines presume standard SDP jumper settings.
#define CONFIG_NAND
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#include <configs/ti_omap3_common.h>
/* Remove SPL boot option - we do not support that on LDP yet */
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
--- /dev/null
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
+#define __CONFIG_SOCFPGA_ARRIA5_H__
+
+#include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/iocsr_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#define CONFIG_REGEX /* Enable regular expression support */
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#endif
+#define CONFIG_LOADADDR 0x8000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "Altera"
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_arria5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
* High level configuration
*/
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CLOCKS
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_REGEX /* Enable regular expression support */
#endif
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "Altera"
+
/* Extra Environment */
#define CONFIG_HOSTNAME socfpga_cyclone5
* Common configurations used for both spear3xx as well as spear6xx
*/
+#define CONFIG_SYS_GENERIC_BOARD
+
/* U-boot Load Address */
#define CONFIG_SYS_TEXT_BASE 0x00700000
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
-#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */
/* We use pin names in Kconfig and sunxi_name_to_gpio() */
#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda
#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl
extern int soft_i2c_gpio_sda;
extern int soft_i2c_gpio_scl;
#endif
+#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */
+#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */
+#else
+#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */
+#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */
#endif
#define CONFIG_CMD_I2C
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define MACH_TYPE_OMAP3_TAO3530 2836
#define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/*
* Size of malloc() pool
*/
+#ifdef CONFIG_DFU_MMC
+#define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \
+ CONFIG_SYS_DFU_DATA_BUF_SIZE)
+#else
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
+#endif
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
/* Misc utility code */
#define CONFIG_BOUNCE_BUFFER
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
-#define CONFIG_SYS_MALLOC_LEN (16 << 20)
+#ifdef CONFIG_DFU_MMC
+#define CONFIG_SYS_MALLOC_LEN ((16 << 20) + CONFIG_SYS_DFU_DATA_BUF_SIZE)
+#else
+#define CONFIG_SYS_MALLOC_LEN (16 << 20)
+#endif
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#ifndef CONFIG_SPL_BUILD
# define CONFIG_OMAP_SERIAL
#endif
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
+
/* The chip has SDRC controller */
#define CONFIG_SDRC
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ARCH_CPU_INIT
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_798870
+
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Use General purpose timer 1 */
/* High Level Configuration Options */
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
/*
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* SPI */
#define CONFIG_TEGRA20_SFLASH
#define CONFIG_SPI_FLASH
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_NOSTDOUT
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP LCD_COLOR32
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_OMAP_WATCHDOG
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
/* Support both device trees and ATAGs. */
#define CONFIG_OF_LIBFDT
+#define CONFIG_USE_FDT /* use fdt within board code */
+#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif /* CONFIG_NAND */
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE (64 << 10)
#ifdef CONFIG_NAND
#define NANDARGS \
#ifdef CONFIG_MMC
#define MMCARGS \
- "silent=1\0"
+"dtbdev=mmc\0" \
+"dtbpart=0:1\0" \
+"logo0=ext4load mmc 0:3 ${loadaddr} /PPTLogo.bmp.gz && " \
+ "bmp display ${loadaddr} 0 0\0" \
+"logo1=ext4load mmc 0:1 ${loadaddr} /PPTLogo.bmp.gz && " \
+ "bmp display ${loadaddr} 0 0\0" \
+"mmcroot0=setenv bootargs ${optargs} console=${console}\0" \
+"mmcroot1=setenv bootargs ${optargs} console=${console} root=/dev/mmcblk0p2 " \
+ "rootfstype=ext4\0" \
+"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \
+ "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \
+ "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \
+ "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \
+"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \
+ "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \
+ "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \
+"defboot=run logo0 || run logo1; " \
+ "ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \
+ "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \
+ "run ramboot; run usbupdate;\0" \
+"bootlimit=1\0" \
+"altbootcmd=run logo0 || run logo1; " \
+ "run mmcboot0;\0" \
+"upduboot=dhcp; " \
+ "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \
+ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0"
#else
#define MMCARGS ""
#endif /* CONFIG_MMC */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=0\0" \
- "loadaddr=0x80200000\0" \
- "bootfile=zImage\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=\0" \
- "rootpath=/tftpboot/tseries/rootfs-small\0" \
- "nfsopts=nolock\0" \
- "netargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
- "ip=dhcp\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload no; " \
- "dhcp; " \
- "tftp ${loadaddr} ${bootfile}; " \
- "run netargs; " \
- "bootm ${loadaddr}\0" \
- "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 0x80000000 updateubootusb.img; " \
- "source;\0" \
- "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
- "setenv autoload 0; " \
- "dhcp;" \
- "tftp 0x80000000 updateUBOOT.img;" \
- "source;\0" \
- NANDARGS \
- MMCARGS
+BUR_COMMON_ENV \
+"verify=no\0" \
+"autoload=0\0" \
+"dtb=bur-ppt-ts30.dtb\0" \
+"dtbaddr=0x80100000\0" \
+"loadaddr=0x80200000\0" \
+"ramaddr=0x80A00000\0" \
+"kernel=zImage\0" \
+"ramdisk=rootfs.cpio.uboot\0" \
+"console=ttyO0,115200n8\0" \
+"optargs=consoleblank=0 quiet lpj=1191936 panic=2\0" \
+"nfsroot=/tftpboot/tseries/rootfs-small\0" \
+"nfsopts=nolock\0" \
+"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \
+"netargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \
+ "ip=dhcp\0" \
+"netboot=echo Booting from network ...; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${kernel}; " \
+ "tftp ${dtbaddr} ${dtb}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${dtbaddr}\0" \
+"ramboot=echo Booting from network into RAM ...; "\
+ "if dhcp; then; " \
+ "tftp ${loadaddr} ${kernel}; " \
+ "tftp ${ramaddr} ${ramdisk}; " \
+ "if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \
+ "then; else tftp ${dtbaddr} ${dtb}; fi;" \
+ "run mmcroot0; " \
+ "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \
+"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+ "usb start && fatload usb 0 0x80000000 updateubootusb.img && source\0" \
+"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+ "setenv autoload 0; " \
+ "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \
+NANDARGS \
+MMCARGS
#endif /* !CONFIG_SPL_BUILD*/
#define CONFIG_BOOTCOMMAND \
- "run mmcboot1;"
-#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+ "run defboot;"
+#define CONFIG_BOOTDELAY 0
#ifdef CONFIG_NAND
/*
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
+#define CONFIG_FS_EXT4
+#define CONFIG_EXT4_WRITE
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FS_GENERIC
#endif /* CONFIG_MMC, ... */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* High Level Configuration Options
*/
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
-
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
-#define CONFIG_SYS_NO_FLASH
-
#define CONFIG_SUPPORT_RAW_INITRD
/* Cache Definitions */
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
-
-/* SMP Spin Table Definitions */
-#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
-#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
-#else
-#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#endif
-
/* CS register bases for the original memory map. */
#define V2M_PA_CS0 0x00000000
#define V2M_PA_CS1 0x14000000
#define V2M_BASE 0x80000000
-/*
- * Physical addresses, offset from V2M_PA_CS0-3
- */
-#define V2M_NOR0 (V2M_PA_CS0)
-#define V2M_NOR1 (V2M_PA_CS4)
-#define V2M_SRAM (V2M_PA_CS1)
-
/* Common peripherals relative to CS7. */
#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
-/* SMSC91C111 Ethernet Configuration */
+/* Ethernet Configuration */
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+/* The real hardware Versatile express uses SMSC9118 */
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_BASE (0x018000000)
+#else
+/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE (0x01A000000)
+#endif
/* PL011 Serial Configuration */
#define CONFIG_PL011_SERIAL
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
"fdt_addr_r=0x83000000\0" \
"fdt_high=0xa0000000\0"
-#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0"
#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \
"$initrd_addr_r:$initrd_size $fdt_addr_r"
#define CONFIG_BOOTDELAY -1
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS 64 /* max command args */
+/* Flash memory is available on the Juno board only */
+#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_NO_FLASH
+#else
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
+#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+
+#endif
+
#endif /* __VEXPRESS_AEMV8A_H */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* Top level Makefile configuration choices
*/
#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_GENERIC_BOARD
/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
*/
#define CONFIG_SPEAR600 /* SPEAr600 SoC */
#define CONFIG_X600 /* on X600 board */
+#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/hardware.h>
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
-#define CONFIG_SYS_MALLOC_LEN 0xC00000
+#define CONFIG_SYS_MALLOC_LEN 0x1400000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
typedef struct
{
unsigned long freq_processor[CONFIG_MAX_CPUS];
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned long freq_processor_dsp[CONFIG_MAX_DSP_CPUS];
+#endif
unsigned long freq_systembus;
unsigned long freq_ddrbus;
unsigned long freq_localbus;
#ifdef CONFIG_SYS_DPAA_PME
unsigned long freq_pme;
#endif
+#ifdef CONFIG_SYS_CPRI
+ unsigned long freq_cpri;
+#endif
+#ifdef CONFIG_SYS_MAPLE
+ unsigned long freq_maple;
+ unsigned long freq_maple_ulb;
+ unsigned long freq_maple_etvpe;
+#endif
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
unsigned char diff_sysclk;
#endif
COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */
COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
- COMPAT_PANASONIC_XHCI, /* Panasonic UniPhier xHCI */
+ COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */
COMPAT_COUNT,
};
* related information
*/
struct sg_entry {
-#ifdef defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
uint32_t addr_lo; /* Memory Address - lo */
uint16_t addr_hi; /* Memory Address of start of buffer - hi */
uint16_t reserved_zero;
--- /dev/null
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_SEC_MON_H
+#define __FSL_SEC_MON_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SEC_MON_LE
+#define sec_mon_in32(a) in_le32(a)
+#define sec_mon_out32(a, v) out_le32(a, v)
+#define sec_mon_in16(a) in_le16(a)
+#define sec_mon_clrbits32 clrbits_le32
+#define sec_mon_setbits32 setbits_le32
+#elif defined(CONFIG_SYS_FSL_SEC_MON_BE)
+#define sec_mon_in32(a) in_be32(a)
+#define sec_mon_out32(a, v) out_be32(a, v)
+#define sec_mon_in16(a) in_be16(a)
+#define sec_mon_clrbits32 clrbits_be32
+#define sec_mon_setbits32 setbits_be32
+#else
+#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined
+#endif
+
+struct ccsr_sec_mon_regs {
+ u8 reserved0[0x04];
+ u32 hp_com; /* 0x04 SEC_MON_HP Command Register */
+ u8 reserved2[0x0c];
+ u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
+};
+
+#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
+#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
+#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
+#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
+#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */
+#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */
+#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */
+#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */
+
+/*
+ * SEC_MON read. This specifies the possible reads
+ * from the SEC_MON
+ */
+enum {
+ SEC_MON_SSM_ST,
+ SEC_MON_SW_FSV,
+ SEC_MON_SW_SV,
+};
+
+int change_sec_mon_state(uint32_t initial_state, uint32_t final_state);
+
+#endif /* __FSL_SEC_MON_H */
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_SECBOOT_ERR_H
+#define _FSL_SECBOOT_ERR_H
+
+#define ERROR_ESBC_PAMU_INIT 0x100000
+#define ERROR_ESBC_SEC_RESET 0x200000
+#define ERROR_ESBC_SEC_INIT 0x400000
+#define ERROR_ESBC_SEC_DEQ 0x800000
+#define ERROR_ESBC_SEC_DEQ_TO 0x1000000
+#define ERROR_ESBC_SEC_ENQ 0x2000000
+#define ERROR_ESBC_SEC_JOBQ_STATUS 0x4000000
+#define ERROR_ESBC_CLIENT_CPUID_NO_MATCH 0x1
+#define ERROR_ESBC_CLIENT_HDR_LOC 0x2
+#define ERROR_ESBC_CLIENT_HEADER_BARKER 0x4
+#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN 0x8
+#define ERROR_ESBC_CLIENT_HEADER_SIG_LEN 0x10
+#define ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED 0x11
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY 0x12
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM 0x13
+#define ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN 0x14
+#define ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED 0x15
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY 0x16
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM 0x17
+#define ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN 0x18
+#define ERROR_IE_TABLE_NOT_FOUND 0x19
+#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN 0x20
+#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1 0x40
+#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2 0x80
+#define ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD 0x100
+#define ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP 0x200
+#define ERROR_ESBC_CLIENT_HASH_COMPARE_KEY 0x400
+#define ERROR_ESBC_CLIENT_HASH_COMPARE_EM 0x800
+#define ERROR_ESBC_CLIENT_SSM_TRUSTSTS 0x1000
+#define ERROR_ESBC_CLIENT_BAD_ADDRESS 0x2000
+#define ERROR_ESBC_CLIENT_MISC 0x4000
+#define ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD 0x8000
+#define ERROR_ESBC_CLIENT_HEADER_SG 0x10000
+#define ERROR_ESBC_CLIENT_HEADER_IMG_SIZE 0x20000
+#define ERROR_ESBC_WRONG_CMD 0x40000
+#define ERROR_ESBC_MISSING_BOOTM 0x80000
+#define ERROR_ESBC_CLIENT_MAX 0x0
+
+struct fsl_secboot_errcode {
+ int errcode;
+ const char *name;
+};
+
+static const struct fsl_secboot_errcode fsl_secboot_errcodes[] = {
+ { ERROR_ESBC_PAMU_INIT,
+ "Error in initializing PAMU"},
+ { ERROR_ESBC_SEC_RESET,
+ "Error in resetting Job ring of SEC"},
+ { ERROR_ESBC_SEC_INIT,
+ "Error in initializing SEC"},
+ { ERROR_ESBC_SEC_ENQ,
+ "Error in enqueue operation by SEC"},
+ { ERROR_ESBC_SEC_DEQ_TO,
+ "Dequeue operation by SEC is timed out"},
+ { ERROR_ESBC_SEC_DEQ,
+ "Error in dequeue operation by SEC"},
+ { ERROR_ESBC_SEC_JOBQ_STATUS,
+ "Error in status of the job submitted to SEC"},
+ { ERROR_ESBC_CLIENT_CPUID_NO_MATCH,
+ "Current core is not boot core i.e core0" },
+ { ERROR_ESBC_CLIENT_HDR_LOC,
+ "Header address not in allowed memory range" },
+ { ERROR_ESBC_CLIENT_HEADER_BARKER,
+ "Wrong barker code in header" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_LEN,
+ "Wrong public key length in header" },
+ { ERROR_ESBC_CLIENT_HEADER_SIG_LEN,
+ "Wrong signature length in header" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN,
+ "Public key length not twice of signature length" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1,
+ "Public key Modulus most significant bit not set" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2,
+ "Public key Modulus in header not odd" },
+ { ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD,
+ "Signature not less than modulus" },
+ { ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP,
+ "Entry point not in allowed space or one of the SG entries" },
+ { ERROR_ESBC_CLIENT_HASH_COMPARE_KEY,
+ "Public key hash comparison failed" },
+ { ERROR_ESBC_CLIENT_HASH_COMPARE_EM,
+ "RSA verification failed" },
+ { ERROR_ESBC_CLIENT_SSM_TRUSTSTS,
+ "SNVS not in TRUSTED state" },
+ { ERROR_ESBC_CLIENT_BAD_ADDRESS,
+ "Bad address error" },
+ { ERROR_ESBC_CLIENT_MISC,
+ "Miscallaneous error" },
+ { ERROR_ESBC_CLIENT_HEADER_SG,
+ "No SG support" },
+ { ERROR_ESBC_CLIENT_HEADER_IMG_SIZE,
+ "Invalid Image size" },
+ { ERROR_ESBC_WRONG_CMD,
+ "Unknown cmd/Wrong arguments. Core in infinite loop"},
+ { ERROR_ESBC_MISSING_BOOTM,
+ "Bootm command missing from bootscript" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED,
+ "Selected key is revoked" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY,
+ "Wrong key entry" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM,
+ "Wrong key is selected" },
+ { ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN,
+ "Wrong srk public key len in header" },
+ { ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED,
+ "Selected IE key is revoked" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY,
+ "Wrong key entry in IE Table" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM,
+ "Wrong IE key is selected" },
+ { ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN,
+ "Wrong IE public key len in header" },
+ { ERROR_IE_TABLE_NOT_FOUND,
+ "Information about IE Table missing" },
+ { ERROR_ESBC_CLIENT_MAX, "NULL" }
+};
+
+void fsl_secboot_handle_error(int error);
+#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_SFP_SNVS_
+#define _FSL_SFP_SNVS_
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SRK_LE
+#define srk_in32(a) in_le32(a)
+#else
+#define srk_in32(a) in_be32(a)
+#endif
+
+#ifdef CONFIG_SYS_FSL_SFP_LE
+#define sfp_in32(a) in_le32(a)
+#define sfp_out32(a, v) out_le32(a, v)
+#define sfp_in16(a) in_le16(a)
+#elif defined(CONFIG_SYS_FSL_SFP_BE)
+#define sfp_in32(a) in_be32(a)
+#define sfp_out32(a, v) out_be32(a, v)
+#define sfp_in16(a) in_be16(a)
+#else
+#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
+#endif
+
+/* Number of SRKH registers */
+#define NUM_SRKH_REGS 8
+
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+struct ccsr_sfp_regs {
+ u32 ospr; /* 0x200 */
+ u32 ospr1; /* 0x204 */
+ u32 reserved1[4];
+ u32 fswpr; /* 0x218 FSL Section Write Protect */
+ u32 fsl_uid; /* 0x21c FSL UID 0 */
+ u32 fsl_uid_1; /* 0x220 FSL UID 0 */
+ u32 reserved2[12];
+ u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
+ u32 oem_uid; /* 0x274 OEM UID 0*/
+ u32 oem_uid_1; /* 0x278 OEM UID 1*/
+ u32 oem_uid_2; /* 0x27c OEM UID 2*/
+ u32 oem_uid_3; /* 0x280 OEM UID 3*/
+ u32 oem_uid_4; /* 0x284 OEM UID 4*/
+ u32 reserved3[8];
+};
+#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0)
+struct ccsr_sfp_regs {
+ u32 ospr; /* 0x200 */
+ u32 reserved0[14];
+ u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */
+ u32 oem_uid; /* 0x9c OEM Unique ID */
+ u8 reserved2[0x04];
+ u32 ovpr; /* 0xA4 Intent To Secure */
+ u8 reserved4[0x08];
+ u32 fsl_uid; /* 0xB0 FSL Unique ID */
+ u8 reserved5[0x04];
+ u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
+ u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
+
+};
+#else
+struct ccsr_sfp_regs {
+ u8 reserved0[0x40];
+ u32 ospr; /* 0x40 OEM Security Policy Register */
+ u8 reserved2[0x38];
+ u32 srk_hash[8]; /* 0x7c Super Root Key Hash */
+ u32 oem_uid; /* 0x9c OEM Unique ID */
+ u8 reserved4[0x4];
+ u32 ovpr; /* 0xA4 OEM Validation Policy Register */
+ u8 reserved8[0x8];
+ u32 fsl_uid; /* 0xB0 FSL Unique ID */
+};
+#endif
+#define ITS_MASK 0x00000004
+#define ITS_BIT 2
+#define OSPR_KEY_REVOC_SHIFT 13
+#define OSPR_KEY_REVOC_MASK 0x0000e000
+
+#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_VALIDATE_H_
+#define _FSL_VALIDATE_H_
+
+#include <fsl_sec.h>
+#include <fsl_sec_mon.h>
+#include <command.h>
+#include <linux/types.h>
+
+#define WORD_SIZE 4
+
+/* Minimum and maximum size of RSA signature length in bits */
+#define KEY_SIZE 4096
+#define KEY_SIZE_BYTES (KEY_SIZE/8)
+#define KEY_SIZE_WORDS (KEY_SIZE_BYTES/(WORD_SIZE))
+
+extern struct jobring jr;
+
+#ifdef CONFIG_KEY_REVOCATION
+/* Srk table and key revocation check */
+#define SRK_FLAG 0x01
+#define UNREVOCABLE_KEY 4
+#define ALIGN_REVOC_KEY 3
+#define MAX_KEY_ENTRIES 4
+#endif
+
+/* Barker code size in bytes */
+#define ESBC_BARKER_LEN 4 /* barker code length in ESBC uboot client */
+ /* header */
+
+/* No-error return values */
+#define ESBC_VALID_HDR 0 /* header is valid */
+
+/* Maximum number of SG entries allowed */
+#define MAX_SG_ENTRIES 8
+
+/*
+ * ESBC uboot client header structure.
+ * The struct contain the following fields
+ * barker code
+ * public key offset
+ * pub key length
+ * signature offset
+ * length of the signature
+ * ptr to SG table
+ * no of entries in SG table
+ * esbc ptr
+ * size of esbc
+ * esbc entry point
+ * Scatter gather flag
+ * UID flag
+ * FSL UID
+ * OEM UID
+ * Here, pub key is modulus concatenated with exponent
+ * of equal length
+ */
+struct fsl_secboot_img_hdr {
+ u8 barker[ESBC_BARKER_LEN]; /* barker code */
+ union {
+ u32 pkey; /* public key offset */
+#ifdef CONFIG_KEY_REVOCATION
+ u32 srk_tbl_off;
+#endif
+ };
+
+ union {
+ u32 key_len; /* pub key length in bytes */
+#ifdef CONFIG_KEY_REVOCATION
+ struct {
+ u32 srk_table_flag:8;
+ u32 srk_sel:8;
+ u32 num_srk:16;
+ } len_kr;
+#endif
+ };
+
+ u32 psign; /* signature offset */
+ u32 sign_len; /* length of the signature in bytes */
+ union {
+ struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */
+ u8 *pimg; /* ptr to ESBC client image */
+ };
+ union {
+ u32 sg_entries; /* no of entries in SG table */
+ u32 img_size; /* ESBC client image size in bytes */
+ };
+ ulong img_start; /* ESBC client entry point */
+ u32 sg_flag; /* Scatter gather flag */
+ u32 uid_flag;
+ u32 fsl_uid_0;
+ u32 oem_uid_0;
+ u32 reserved1[2];
+ u32 fsl_uid_1;
+ u32 oem_uid_1;
+ u32 reserved2[2];
+ u32 ie_flag;
+ u32 ie_key_sel;
+};
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+struct ie_key_table {
+ u32 key_len;
+ u8 pkey[2 * KEY_SIZE_BYTES];
+};
+
+struct ie_key_info {
+ uint32_t key_revok;
+ uint32_t num_keys;
+ struct ie_key_table ie_key_tbl[32];
+};
+#endif
+
+#ifdef CONFIG_KEY_REVOCATION
+struct srk_table {
+ u32 key_len;
+ u8 pkey[2 * KEY_SIZE_BYTES];
+};
+#endif
+
+/*
+ * SG table.
+ */
+#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * source address
+ */
+struct fsl_secboot_sg_table {
+ u32 len; /* length of the segment in bytes */
+ ulong src_addr; /* ptr to the data segment */
+};
+#else
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * Destination Target ID
+ * source address
+ * destination address
+ */
+struct fsl_secboot_sg_table {
+ u32 len;
+ u32 trgt_id;
+ ulong src_addr;
+ ulong dst_addr;
+};
+#endif
+
+/*
+ * ESBC private structure.
+ * Private structure used by ESBC to store following fields
+ * ESBC client key
+ * ESBC client key hash
+ * ESBC client Signature
+ * Encoded hash recovered from signature
+ * Encoded hash of ESBC client header plus ESBC client image
+ */
+struct fsl_secboot_img_priv {
+ uint32_t hdr_location;
+ ulong ie_addr;
+ u32 key_len;
+ struct fsl_secboot_img_hdr hdr;
+
+ u8 img_key[2 * KEY_SIZE_BYTES]; /* ESBC client key */
+ u8 img_key_hash[32]; /* ESBC client key hash */
+
+#ifdef CONFIG_KEY_REVOCATION
+ struct srk_table srk_tbl[MAX_KEY_ENTRIES];
+#endif
+ u8 img_sign[KEY_SIZE_BYTES]; /* ESBC client signature */
+
+ u8 img_encoded_hash[KEY_SIZE_BYTES]; /* EM wrt RSA PKCSv1.5 */
+ /* Includes hash recovered after
+ * signature verification
+ */
+
+ u8 img_encoded_hash_second[KEY_SIZE_BYTES];/* EM' wrt RSA PKCSv1.5 */
+ /* Includes hash of
+ * ESBC client header plus
+ * ESBC client image
+ */
+
+ struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */
+ u32 ehdrloc; /* ESBC client location */
+};
+
+int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+
+#endif
#include <asm/linkage.h>
+/* Some toolchains use other characters (e.g. '`') to mark new line in macro */
+#ifndef ASM_NL
+#define ASM_NL ;
+#endif
+
#ifdef __cplusplus
#define CPP_ASMLINKAGE extern "C"
#else
#define ALIGN_STR __ALIGN_STR
#define LENTRY(name) \
- ALIGN; \
+ ALIGN ASM_NL \
SYMBOL_NAME_LABEL(name)
#define ENTRY(name) \
- .globl SYMBOL_NAME(name); \
+ .globl SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#define WEAK(name) \
- .weak SYMBOL_NAME(name); \
+ .weak SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#ifndef END
#ifndef ENDPROC
#define ENDPROC(name) \
- .type name STT_FUNC; \
+ .type name STT_FUNC ASM_NL \
END(name)
#endif
#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06
#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F
+#define TPS65217_PWR_OFF 0x80
#define TPS65217_PWR_SRC_USB_BITMASK 0x4
#define TPS65217_PWR_SRC_AC_BITMASK 0x8
struct stdio_dev {
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
- char name[16]; /* Device name */
+ char name[32]; /* Device name */
/* GENERAL functions */
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
-#if defined(CONFIG_ARM)
-
DEFINE(GD_RELOCADDR, offsetof(struct global_data, relocaddr));
DEFINE(GD_RELOC_OFF, offsetof(struct global_data, reloc_off));
DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp));
-#endif
-
return 0;
}
COMPAT(AMS_AS3722, "ams,as3722"),
COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
- COMPAT(PANASONIC_XHCI, "panasonic,uniphier-xhci"),
+ COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o rsa-mod-exp.o
+obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
+obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o
define_config(m, slen, hash);
- /* printf(" $(wildcard include/config/"); */
- /* modified for U-Boot */
- printf(" $(wildcard %sinclude/config/",
- strncmp(depfile, "spl/", 4) ?
- (strncmp(depfile, "tpl/", 4) ? "" : "tpl/") : "spl/");
+ printf(" $(wildcard include/config/");
for (i = 0; i < slen; i++) {
c = m[i];
if (c == '_')
# Random bits by Matt Mackall <mpm@selenic.com>
# M68k port by Geert Uytterhoeven and Andreas Schwab
# AVR32 port by Haavard Skinnemoen (Atmel)
-# PARISC port by Kyle McMartin <kyle@parisc-linux.org>
+# AArch64, PARISC ports by Kyle McMartin
# sparc port by Martin Habets <errandir_news@mph.eclipse.co.uk>
#
# Usage:
# $1 (first bracket) matches the dynamic amount of the stack growth
#
# use anything else and feel the pain ;)
-my (@stack, $re, $dre, $x, $xs);
+my (@stack, $re, $dre, $x, $xs, $funcre);
{
my $arch = shift;
if ($arch eq "") {
$x = "[0-9a-f]"; # hex character
$xs = "[0-9a-f ]"; # hex character or space
- if ($arch eq 'arm') {
+ $funcre = qr/^$x* <(.*)>:$/;
+ if ($arch eq 'aarch64') {
+ #ffffffc0006325cc: a9bb7bfd stp x29, x30, [sp,#-80]!
+ $re = qr/^.*stp.*sp,\#-([0-9]{1,8})\]\!/o;
+ } elsif ($arch eq 'arm') {
#c0008ffc: e24dd064 sub sp, sp, #100 ; 0x64
$re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o;
} elsif ($arch eq 'avr32') {
#8000008a: 20 1d sub sp,4
#80000ca8: fa cd 05 b0 sub sp,sp,1456
$re = qr/^.*sub.*sp.*,([0-9]{1,8})/o;
- } elsif ($arch =~ /^i[3456]86$/) {
+ } elsif ($arch =~ /^x86(_64)?$/ || $arch =~ /^i[3456]86$/) {
#c0105234: 81 ec ac 05 00 00 sub $0x5ac,%esp
- $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%esp$/o;
- $dre = qr/^.*[as][du][db] (%.*),\%esp$/o;
- } elsif ($arch eq 'x86_64') {
- # 2f60: 48 81 ec e8 05 00 00 sub $0x5e8,%rsp
- $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%rsp$/o;
- $dre = qr/^.*[as][du][db] (\%.*),\%rsp$/o;
+ # or
+ # 2f60: 48 81 ec e8 05 00 00 sub $0x5e8,%rsp
+ $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%(e|r)sp$/o;
+ $dre = qr/^.*[as][du][db] (%.*),\%(e|r)sp$/o;
} elsif ($arch eq 'ia64') {
#e0000000044011fc: 01 0f fc 8c adds r12=-384,r12
$re = qr/.*adds.*r12=-(([0-9]{2}|[3-9])[0-9]{2}),r12/o;
# 2b6c: 4e56 fb70 linkw %fp,#-1168
# 1df770: defc ffe4 addaw #-28,%sp
$re = qr/.*(?:linkw %fp,|addaw )#-([0-9]{1,4})(?:,%sp)?$/o;
+ } elsif ($arch eq 'metag') {
+ #400026fc: 40 00 00 82 ADD A0StP,A0StP,#0x8
+ $re = qr/.*ADD.*A0StP,A0StP,\#(0x$x{1,8})/o;
+ $funcre = qr/^$x* <[^\$](.*)>:$/;
} elsif ($arch eq 'mips64') {
#8800402c: 67bdfff0 daddiu sp,sp,-16
$re = qr/.*daddiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o;
#
# main()
#
-my $funcre = qr/^$x* <(.*)>:$/;
my ($func, $file, $lastslash);
while (my $line = <STDIN>) {
arch = 'unknown'
str = self.col.Color(color, ' ' + target)
if not arch in done_arch:
- str = self.col.Color(color, char) + ' ' + str
+ str = ' %s %s' % (self.col.Color(color, char), str)
done_arch[arch] = True
if not arch in arch_list:
arch_list[arch] = str
expected_colour = col.GREEN if ok else col.RED
expect = '%10s: ' % arch
# TODO(sjg@chromium.org): If plus is '', we shouldn't need this
- expect += col.Color(expected_colour, plus)
+ expect += ' ' + col.Color(expected_colour, plus)
expect += ' '
for board in boards:
expect += col.Color(expected_colour, ' %s' % board)
# Check that the toolchain works
print 'Testing'
dirpath = os.path.join(dest, path)
- compiler_fname = self.ScanPath(dirpath, True)
- if not compiler_fname:
+ compiler_fname_list = self.ScanPath(dirpath, True)
+ if not compiler_fname_list:
print 'Could not locate C compiler - fetch failed.'
return 1
- toolchain = Toolchain(compiler_fname, True, True)
+ if len(compiler_fname_list) != 1:
+ print ('Internal error, ambiguous toolchains: %s' %
+ (', '.join(compiler_fname)))
+ return 1
+ toolchain = Toolchain(compiler_fname_list[0], True, True)
# Make sure that it will be found by buildman
if not self.TestSettingsHasPath(dirpath):
binhdrsz = sizeof(struct opt_hdr_v1) +
(binarye->binary.nargs + 1) * sizeof(unsigned int) +
s.st_size;
+ binhdrsz = ALIGN_SUP(binhdrsz, 32);
hdr->headersz_lsb = binhdrsz & 0xFFFF;
hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
projects / people / ms / u-boot.git / commitdiff
