*.orig
*.a
*.o
+*.su
*~
*.swp
*.patch
Kshitij Gupta <kshitij@ti.com>
omap1510inn ARM925T
- omap1610inn ARM926EJS
Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
-v VENDOR, --vendor VENDOR Build all boards with vendor VENDOR
-s SOC, --soc SOC Build all boards with soc SOC
-l, --list List all targets to be built
+ -m, --maintainers List all targets and maintainer email
+ -M, --mails List all targets and all affilated emails
-h, --help This help output
Selections by these options are logically ANDed; if the same option
exit ${ret}
}
-SHORT_OPTS="ha:c:v:s:l"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list"
+SHORT_OPTS="ha:c:v:s:lmM"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails"
# Option processing based on util-linux-2.13/getopt-parse.bash
SELECTED=''
ONLY_LIST=''
+PRINT_MAINTS=''
+MAINTAINERS_ONLY=''
while true ; do
case "$1" in
-l|--list)
ONLY_LIST='y'
shift ;;
+ -m|--maintainers)
+ ONLY_LIST='y'
+ PRINT_MAINTS='y'
+ MAINTAINERS_ONLY='y'
+ shift ;;
+ -M|--mails)
+ ONLY_LIST='y'
+ PRINT_MAINTS='y'
+ shift ;;
-h|--help)
usage ;;
--)
#-----------------------------------------------------------------------
+get_target_location() {
+ local target=$1
+ local BOARD_NAME=""
+ local CONFIG_NAME=""
+ local board=""
+ local vendor=""
+
+ # Automatic mode
+ local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg`
+
+ if [ -z "${line}" ] ; then echo "" ; return ; fi
+
+ set ${line}
+
+ # add default board name if needed
+ [ $# = 3 ] && set ${line} ${1}
+
+ CONFIG_NAME="${1%_config}"
+
+ [ "${BOARD_NAME}" ] || BOARD_NAME="${1%_config}"
+
+ if [ "$4" = "-" ] ; then
+ board=${BOARD_NAME}
+ else
+ board="$4"
+ fi
+
+ [ $# -gt 4 ] && [ "$5" != "-" ] && vendor="$5"
+ [ $# -gt 6 ] && [ "$7" != "-" ] && {
+ tmp="${7%:*}"
+ if [ "$tmp" ] ; then
+ CONFIG_NAME="$tmp"
+ fi
+ }
+
+ # Assign board directory to BOARDIR variable
+ if [ -z "${vendor}" ] ; then
+ BOARDDIR=${board}
+ else
+ BOARDDIR=${vendor}/${board}
+ fi
+
+ echo "${CONFIG_NAME}:${BOARDDIR}"
+}
+
+get_target_maintainers() {
+ local name=`echo $1 | cut -d : -f 1`
+
+ if ! grep -qsi "[[:blank:]]${name}[[:blank:]]" MAINTAINERS ; then
+ echo ""
+ return ;
+ fi
+
+ local line=`tac MAINTAINERS | grep -ni "[[:blank:]]${name}[[:blank:]]" | cut -d : -f 1`
+ local mail=`tac MAINTAINERS | tail -n +${line} | \
+ sed -n ":start /.*@.*/ { b mail } ; n ; b start ; :mail /.*@.*/ { p ; n ; b mail } ; q" | \
+ sed "s/^.*<//;s/>.*$//"`
+ echo "$mail"
+}
+
+list_target() {
+ if [ "$PRINT_MAINTS" != 'y' ] ; then
+ echo "$1"
+ return
+ fi
+
+ echo -n "$1:"
+
+ local loc=`get_target_location $1`
+
+ if [ -z "${loc}" ] ; then echo "ERROR" ; return ; fi
+
+ local maintainers_result=`get_target_maintainers ${loc} | tr " " "\n"`
+
+ if [ "$MAINTAINERS_ONLY" != 'y' ] ; then
+
+ local dir=`echo ${loc} | cut -d ":" -f 2`
+ local cfg=`echo ${loc} | cut -d ":" -f 1`
+ local git_result=`git log --format=%aE board/${dir} \
+ include/configs/${cfg}.h | grep "@"`
+ local git_result_recent=`echo ${git_result} | tr " " "\n" | \
+ head -n 3`
+ local git_result_top=`echo ${git_result} | tr " " "\n" | \
+ sort | uniq -c | sort -nr | head -n 3 | \
+ sed "s/^ \+[0-9]\+ \+//"`
+
+ echo -e "$git_result_recent\n$git_result_top\n$maintainers_result" | \
+ sort -u | tr "\n" " " | sed "s/ $//" ;
+ else
+ echo -e "$maintainers_result" | sort -u | tr "\n" " " | \
+ sed "s/ $//" ;
+ fi
+
+ echo ""
+}
+
build_target() {
target=$1
if [ "$ONLY_LIST" == 'y' ] ; then
- echo "$target"
+ list_target ${target}
return
fi
TOTAL_CNT=$((TOTAL_CNT + 1))
- ${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
- | tee -a ${LOG_DIR}/$target.MAKELOG
+ OBJS=${BUILD_DIR}/u-boot
+ if [ -e ${BUILD_DIR}/spl/u-boot-spl ]; then
+ OBJS="${OBJS} ${BUILD_DIR}/spl/u-boot-spl"
+ fi
+
+ ${CROSS_COMPILE}size ${OBJS} | tee -a ${LOG_DIR}/$target.MAKELOG
}
build_targets() {
for t in "$@" ; do
# that (or fail if absent). Otherwise, search for a linker script in a
# standard location.
+LDSCRIPT_MAKEFILE_DIR = $(dir $(LDSCRIPT))
+
ifndef LDSCRIPT
#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
ifdef CONFIG_SYS_LDSCRIPT
endif
endif
+# If there is no specified link script, we look in a number of places for it
ifndef LDSCRIPT
ifeq ($(CONFIG_NAND_U_BOOT),y)
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
ifeq ($(wildcard $(LDSCRIPT)),)
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds
endif
+ ifeq ($(wildcard $(LDSCRIPT)),)
+ LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds
+ # We don't expect a Makefile here
+ LDSCRIPT_MAKEFILE_DIR =
+ endif
ifeq ($(wildcard $(LDSCRIPT)),)
$(error could not find linker script)
endif
# on the fly.
LDPPFLAGS += \
-include $(TOPDIR)/include/u-boot/u-boot.lds.h \
+ -DCPUDIR=$(CPUDIR) \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
$(obj)include/autoconf.mk \
$(obj)include/generated/generic-asm-offsets.h \
$(obj)include/generated/asm-offsets.h
- for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \
+ for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
$(MAKE) -C $$dir _depend ; done
TAG_SUBDIRS = $(SUBDIRS)
fi;
@$(MKCONFIG) -n $@ SX1 arm arm925t sx1
-#########################################################################
-## XScale Systems
-#########################################################################
-
-pdnb3_config \
-scpu_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring scpu_,$@)" ] ; then \
- echo "#define CONFIG_SCPU" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a pdnb3 arm ixp pdnb3 prodrive
-
#########################################################################
## ARM1176 Systems
#########################################################################
@rm -f $(obj)MLO
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@find $(OBJTREE) -type f \
- \( -name 'core' -o -name '*.bak' -o -name '*~' \
+ \( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
| xargs rm -f
May be defined to allow interrupt polling
instead of using asynchronous interrupts
+ CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
+ txfilltuning field in the EHCI controller on reset.
+
- USB Device:
Define the below if you wish to use the USB console.
Once firmware is rebuilt from a serial console issue the
- FAT(File Allocation Table) filesystem write function support:
CONFIG_FAT_WRITE
- Support for saving memory data as a file
- in FAT formatted partition
+
+ Define this to enable support for saving memory data as a
+ file in FAT formatted partition.
+
+ This will also enable the command "fatwrite" enabling the
+ user to write files to FAT.
- Keyboard Support:
CONFIG_ISA_KEYBOARD
CONFIG_SPL
Enable building of SPL globally.
+ CONFIG_SPL_LDSCRIPT
+ LDSCRIPT for linking the SPL binary.
+
+ CONFIG_SPL_MAX_SIZE
+ Maximum binary size (text, data and rodata) of the SPL binary.
+
CONFIG_SPL_TEXT_BASE
TEXT_BASE for linking the SPL binary.
- CONFIG_SPL_LDSCRIPT
- LDSCRIPT for linking the SPL binary.
+ CONFIG_SPL_BSS_START_ADDR
+ Link address for the BSS within the SPL binary.
+
+ CONFIG_SPL_BSS_MAX_SIZE
+ Maximum binary size of the BSS section of the SPL binary.
+
+ CONFIG_SPL_STACK
+ Adress of the start of the stack SPL will use
+
+ CONFIG_SYS_SPL_MALLOC_START
+ Starting address of the malloc pool used in SPL.
+
+ CONFIG_SYS_SPL_MALLOC_SIZE
+ The size of the malloc pool used in SPL.
CONFIG_SPL_LIBCOMMON_SUPPORT
Support for common/libcommon.o in SPL binary
CONFIG_SPL_MMC_SUPPORT
Support for drivers/mmc/libmmc.o in SPL binary
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+ CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
+ CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION
+ Address, size and partition on the MMC to load U-Boot from
+ when the MMC is being used in raw mode.
+
+ CONFIG_SPL_FAT_SUPPORT
+ Support for fs/fat/libfat.o in SPL binary
+
+ CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
+ Filename to read to load U-Boot when reading from FAT
+
+ CONFIG_SPL_NAND_SIMPLE
+ Support for drivers/mtd/nand/libnand.o in SPL binary
+
+ CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
+ CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
+ CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
+ CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
+ CONFIG_SYS_NAND_ECCBYTES
+ Defines the size and behavior of the NAND that SPL uses
+ to read U-Boot with CONFIG_SPL_NAND_SIMPLE
+
+ CONFIG_SYS_NAND_U_BOOT_OFFS
+ Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot
+ from.
+
+ CONFIG_SYS_NAND_U_BOOT_START
+ Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot
+ to.
+
+ CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+ Define this if you need to first read the OOB and then the
+ data. This is used for example on davinci plattforms.
+
+ CONFIG_SPL_OMAP3_ID_NAND
+ Support for an OMAP3-specific set of functions to return the
+ ID and MFR of the first attached NAND chip, if present.
+
CONFIG_SPL_SERIAL_SUPPORT
Support for drivers/serial/libserial.o in SPL binary
CONFIG_SPL_SPI_SUPPORT
Support for drivers/spi/libspi.o in SPL binary
- CONFIG_SPL_FAT_SUPPORT
- Support for fs/fat/libfat.o in SPL binary
-
CONFIG_SPL_LIBGENERIC_SUPPORT
Support for lib/libgeneric.o in SPL binary
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
-- CONFIG_SYS_NAND_HW_ECC_OOBFIRST
- define this, if you want to read first the oob data
- and then the data. This is used for example on
- davinci plattforms.
-
- CONFIG_USE_ARCH_MEMCPY
CONFIG_USE_ARCH_MEMSET
If these options are used a optimized version of memcpy/memset will
run - run commands in an environment variable
bootm - boot application image from memory
bootp - boot image via network using BootP/TFTP protocol
+bootz - boot zImage from memory
tftpboot- boot image via network using TFTP protocol
and env variables "ipaddr" and "serverip"
(and eventually "gatewayip")
useful when you configure U-Boot to use a real shell (hush)
as command interpreter.
+Booting the Linux zImage:
+-------------------------
+
+On some platforms, it's possible to boot Linux zImage. This is done
+using the "bootz" command. The syntax of "bootz" command is the same
+as the syntax of "bootm" command.
+
+Note, defining the CONFIG_SUPPORT_INITRD_RAW allows user to supply
+kernel with raw initrd images. The syntax is slightly different, the
+address of the initrd must be augmented by it's size, in the following
+format: "<initrd addres>:<initrd size>".
+
Standalone HOWTO:
=================
endif
endif
-ifdef CONFIG_SYS_LDSCRIPT
-# need to strip off double quotes
-LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
-else
-LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
-endif
-
# needed for relocation
ifndef CONFIG_NAND_SPL
LDFLAGS_u-boot += -pie
return "WDOG";
case 0x0006:
return "JTAG";
+ case 0x0007:
+ return "ARM11P power gating";
default:
return "unknown reset";
}
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * Copyright (C) 2005-2007 Samsung Electronics
- * Kyungin Park <kyugnmin.park@samsung.com>
- *
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm1136/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm1176/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm720t/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
#include <asm/io.h>
#include <asm/arch/s3c24x0_cpu.h>
-int timer_load_val = 0;
-static ulong timer_clk;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
- struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
-
- return readl(&timers->tcnto4) & 0xffff;
-}
-
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
int timer_init(void)
{
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
writel(0x0f00, &timers->tcfg0);
- if (timer_load_val == 0) {
+ if (gd->tbu == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
- timer_load_val = get_PCLK() / (2 * 16 * 100);
- timer_clk = get_PCLK() / (2 * 16);
+ gd->tbu = get_PCLK() / (2 * 16 * 100);
+ gd->timer_rate_hz = get_PCLK() / (2 * 16);
}
/* load value for 10 ms timeout */
- lastdec = timer_load_val;
- writel(timer_load_val, &timers->tcntb4);
+ writel(gd->tbu, &timers->tcntb4);
/* auto load, manual update of timer 4 */
tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->tcon);
/* auto load, start timer 4 */
tmr = (tmr & ~0x0700000) | 0x0500000;
writel(tmr, &timers->tcon);
- timestamp = 0;
+ gd->lastinc = 0;
+ gd->tbl = 0;
- return (0);
+ return 0;
}
/*
ulong start = get_ticks();
tmo = usec / 1000;
- tmo *= (timer_load_val * 100);
+ tmo *= (gd->tbu * 100);
tmo /= 1000;
while ((ulong) (get_ticks() - start) < tmo)
{
ulong tmr = get_ticks();
- return tmr / (timer_clk / CONFIG_SYS_HZ);
+ return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ);
}
void udelay_masked(unsigned long usec)
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= (timer_load_val * 100);
+ tmo *= (gd->tbu * 100);
tmo /= 1000;
} else {
- tmo = usec * (timer_load_val * 100);
+ tmo = usec * (gd->tbu * 100);
tmo /= (1000 * 1000);
}
*/
unsigned long long get_ticks(void)
{
- ulong now = READ_TIMER();
+ struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+ ulong now = readl(&timers->tcnto4) & 0xffff;
- if (lastdec >= now) {
+ if (gd->lastinc >= now) {
/* normal mode */
- timestamp += lastdec - now;
+ gd->tbl += gd->lastinc - now;
} else {
/* we have an overflow ... */
- timestamp += lastdec + timer_load_val - now;
+ gd->tbl += gd->lastinc + gd->tbu - now;
}
- lastdec = now;
+ gd->lastinc = now;
- return timestamp;
+ return gd->tbl;
}
/*
*/
ulong get_tbclk(void)
{
- ulong tbclk;
-
-#if defined(CONFIG_SMDK2400)
- tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SBC2410X) || \
- defined(CONFIG_SMDK2410) || \
- defined(CONFIG_S3C2440) || \
- defined(CONFIG_VCMA9)
- tbclk = CONFIG_SYS_HZ;
-#else
-# error "tbclk not configured"
-#endif
-
- return tbclk;
+ return CONFIG_SYS_HZ;
}
/*
+++ /dev/null
-/*
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm920t/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, <wg@denx.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm925t/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
-static inline void dcache_noop(void)
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+void invalidate_dcache_all(void)
{
- if (dcache_status()) {
- puts("WARNING: cache operations are not implemented!\n"
- "WARNING: disabling D-Cache now, you can re-enable it"
- "later with 'dcache on' command\n");
- dcache_disable();
- }
+ asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0));
}
-void invalidate_dcache_all(void)
+void flush_dcache_all(void)
{
- dcache_noop();
+ asm volatile(
+ "0:"
+ "mrc p15, 0, r15, c7, c14, 3\n"
+ "bne 0b\n"
+ "mcr p15, 0, %0, c7, c10, 4\n"
+ ::"r"(0):"memory"
+ );
+}
+
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+ int ok = 1;
+
+ if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
+
+ if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
+
+ if (!ok)
+ printf("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+ start, stop);
+
+ return ok;
}
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
- dcache_noop();
+ if (!check_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
- dcache_noop();
+ if (!check_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+
+ asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
}
-void flush_cache(unsigned long start, unsigned long size)
+void flush_cache(unsigned long start, unsigned long size)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
- uint32_t clkctrl, clkseq, clkfrac;
- uint32_t frac, div;
+ uint32_t clkctrl, clkseq, div;
+ uint8_t clkfrac, frac;
clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
}
/* REF Path */
- clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
- frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK;
+ clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
+ frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
- uint32_t frac, div;
- uint32_t clkctrl, clkseq, clkfrac;
+ uint32_t clkctrl, clkseq, div;
+ uint8_t clkfrac, frac;
clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
return XTAL_FREQ_MHZ / div;
}
- clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
-
/* REF Path */
- frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >>
- CLKCTRL_FRAC0_EMIFRAC_OFFSET;
+ clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
+ frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
- uint32_t frac, div;
- uint32_t clkctrl, clkseq, clkfrac;
+ uint32_t clkctrl, clkseq, div;
+ uint8_t clkfrac, frac;
clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
return XTAL_FREQ_MHZ / div;
}
- clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1);
-
/* REF Path */
- frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >>
- CLKCTRL_FRAC1_GPMIFRAC_OFFSET;
+ clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
+ frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
+ int io_reg;
if (freq == 0)
return;
- if (io > MXC_IOCLK1)
+ if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
return;
div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
if (div > 35)
div = 35;
- if (io == MXC_IOCLK0) {
- writel(CLKCTRL_FRAC0_CLKGATEIO0,
- &clkctrl_regs->hw_clkctrl_frac0_set);
- clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
- CLKCTRL_FRAC0_IO0FRAC_MASK,
- div << CLKCTRL_FRAC0_IO0FRAC_OFFSET);
- writel(CLKCTRL_FRAC0_CLKGATEIO0,
- &clkctrl_regs->hw_clkctrl_frac0_clr);
- } else {
- writel(CLKCTRL_FRAC0_CLKGATEIO1,
- &clkctrl_regs->hw_clkctrl_frac0_set);
- clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
- CLKCTRL_FRAC0_IO1FRAC_MASK,
- div << CLKCTRL_FRAC0_IO1FRAC_OFFSET);
- writel(CLKCTRL_FRAC0_CLKGATEIO1,
- &clkctrl_regs->hw_clkctrl_frac0_clr);
- }
+ io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);
+ writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK),
+ &clkctrl_regs->hw_clkctrl_frac0[io_reg]);
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);
}
/*
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
- uint32_t tmp, ret;
+ uint8_t ret;
+ int io_reg;
- if (io > MXC_IOCLK1)
+ if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
return 0;
- tmp = readl(&clkctrl_regs->hw_clkctrl_frac0);
+ io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
- if (io == MXC_IOCLK0)
- ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >>
- CLKCTRL_FRAC0_IO0FRAC_OFFSET;
- else
- ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >>
- CLKCTRL_FRAC0_IO1FRAC_OFFSET;
+ ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
+ CLKCTRL_FRAC_FRAC_MASK;
return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
}
return;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
- (ssp * sizeof(struct mx28_register));
+ (ssp * sizeof(struct mx28_register_32));
clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
return XTAL_FREQ_KHZ;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
- (ssp * sizeof(struct mx28_register));
+ (ssp * sizeof(struct mx28_register_32));
tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
{
u32 reg, ofs, bp, bm;
void *iomux_base = (void *)MXS_PINCTRL_BASE;
- struct mx28_register *mxs_reg;
+ struct mx28_register_32 *mxs_reg;
/* muxsel */
ofs = 0x100;
/* vol */
if (PAD_VOL_VALID(pad)) {
bp = PAD_PIN(pad) % 8 * 4 + 2;
- mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+ mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
if (PAD_VOL(pad))
writel(1 << bp, &mxs_reg->reg_set);
else
ofs = PULL_OFFSET;
ofs += PAD_BANK(pad) * 0x10;
bp = PAD_PIN(pad);
- mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+ mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
if (PAD_PULL(pad))
writel(1 << bp, &mxs_reg->reg_set);
else
;
}
-int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
+int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
{
while (--timeout) {
if ((readl(®->reg) & mask) == mask)
return !timeout;
}
-int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
+int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
{
while (--timeout) {
if ((readl(®->reg) & mask) == 0)
return !timeout;
}
-int mx28_reset_block(struct mx28_register *reg)
+int mx28_reset_block(struct mx28_register_32 *reg)
{
/* Clear SFTRST */
writel(MX28_BLOCK_SFTRST, ®->reg_clr);
}
#endif
-#define HW_DIGCTRL_SCRATCH0 0x8001c280
-#define HW_DIGCTRL_SCRATCH1 0x8001c290
int mx28_dram_init(void)
{
+ struct mx28_digctl_regs *digctl_regs =
+ (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
uint32_t sz[2];
- sz[0] = readl(HW_DIGCTRL_SCRATCH0);
- sz[1] = readl(HW_DIGCTRL_SCRATCH1);
+ sz[0] = readl(&digctl_regs->hw_digctl_scratch0);
+ sz[1] = readl(&digctl_regs->hw_digctl_scratch1);
if (sz[0] != sz[1]) {
printf("MX28:\n"
#include "mx28_init.h"
uint32_t dram_vals[] = {
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
- 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
- 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
- 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
- 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
- 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
- 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
- 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
- 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
- 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
- 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
- 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
- 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
- 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00010101, 0x01010101,
+ 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
+ 0x00000100, 0x00000100, 0x00000000, 0x00000002,
+ 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+ 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
+ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
+ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000612, 0x01000F02,
+ 0x06120612, 0x00000200, 0x00020007, 0xf5014b27,
+ 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300,
+ 0x07000300, 0x07000300, 0x07000300, 0x00000006,
+ 0x00000000, 0x00000000, 0x01000000, 0x01020408,
+ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
+ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00010000, 0x00020304,
+ 0x00000004, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x01010000,
+ 0x01000000, 0x03030000, 0x00010303, 0x01020202,
+ 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+ 0x06120612, 0x04320432, 0x04320432, 0x00040004,
+ 0x00040004, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00010001
};
void init_m28_200mhz_ddr2(void)
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Gate EMI clock */
- writel(CLKCTRL_FRAC0_CLKGATEEMI,
- &clkctrl_regs->hw_clkctrl_frac0_set);
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
- /* EMI = 205MHz */
- writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
- &clkctrl_regs->hw_clkctrl_frac0_set);
- writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
- CLKCTRL_FRAC0_EMIFRAC_MASK,
- &clkctrl_regs->hw_clkctrl_frac0_clr);
+ /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
+ writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
+ &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
/* Ungate EMI clock */
- writel(CLKCTRL_FRAC0_CLKGATEEMI,
- &clkctrl_regs->hw_clkctrl_frac0_clr);
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
early_delay(11000);
+ /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
&clkctrl_regs->hw_clkctrl_emi);
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
- /* CPU = 454MHz and ungate CPU clock */
- clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
- CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
- 19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
+ /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
+ * and ungate CPU clock */
+ writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
+ (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
/* Set CPU bypass */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&power_regs->hw_power_vdddctrl);
}
-#define HW_DIGCTRL_SCRATCH0 0x8001c280
-#define HW_DIGCTRL_SCRATCH1 0x8001c290
-void data_abort_memdetect_handler(void) __attribute__((naked));
-void data_abort_memdetect_handler(void)
-{
- asm volatile("subs pc, r14, #4");
-}
-
void mx28_mem_get_size(void)
{
+ struct mx28_digctl_regs *digctl_regs =
+ (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
uint32_t sz, da;
uint32_t *vt = (uint32_t *)0x20;
+ /* The following is "subs pc, r14, #4", used as return from DABT. */
+ const uint32_t data_abort_memdetect_handler = 0xe25ef004;
/* Replace the DABT handler. */
da = vt[4];
- vt[4] = (uint32_t)&data_abort_memdetect_handler;
+ vt[4] = data_abort_memdetect_handler;
sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- writel(sz, HW_DIGCTRL_SCRATCH0);
- writel(sz, HW_DIGCTRL_SCRATCH1);
+ writel(sz, &digctl_regs->hw_digctl_scratch0);
+ writel(sz, &digctl_regs->hw_digctl_scratch1);
/* Restore the old DABT handler. */
vt[4] = da;
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
POWER_STS_VDD5V_GT_VDDIO))
- early_delay(1500);
+ early_delay(500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
POWER_STS_VDD5V_GT_VDDIO))
- early_delay(1500);
+ early_delay(500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
POWER_STS_VDD5V_GT_VDDIO))
- early_delay(1500);
+ early_delay(500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
POWER_STS_VDD5V_GT_VDDIO))
- early_delay(1500);
+ early_delay(500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
while ((signed)(end - READ_TIMER()) > 0)
;
}
+
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
+++ /dev/null
-/*
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm926ejs/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm946es/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm_intcm/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
START := start.o
-ifndef CONFIG_SPL_BUILD
COBJS += cache_v7.o
-endif
COBJS += cpu.o
COBJS += syslib.o
*
* we turn off caches etc ...
*/
+#ifndef CONFIG_SPL_BUILD
disable_interrupts();
+#endif
/*
* Turn off I-cache and invalidate it
LIB = $(obj)lib$(SOC).o
-COBJS := timer.o
+COBJS := timer.o bootcount.o
SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+void bootcount_store(ulong a)
+{
+ writel((BOOTCOUNT_MAGIC & 0xffff0000) | a, CONFIG_SYS_BOOTCOUNT_ADDR);
+}
+
+ulong bootcount_load(void)
+{
+ u32 tmp = readl(CONFIG_SYS_BOOTCOUNT_ADDR);
+
+ if ((tmp & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
+ return 0;
+ else
+ return tmp & 0x0000ffff;
+}
+#endif
--- /dev/null
+PLATFORM_CPPFLAGS += -march=armv7-a
static inline unsigned long long us_to_tick(unsigned long long us)
{
- unsigned long long tick = us << 16;
+ unsigned long long tick = us * 1000;
tick += NS_PER_TICK - 1;
do_div(tick, NS_PER_TICK);
- return tick >> 16;
+ return tick;
}
unsigned long long get_ticks(void)
{
return tick_to_time(get_ticks());
}
+
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
switch (cause) {
case 0x00001:
+ case 0x00011:
return "POR";
case 0x00004:
return "CSU";
}
#if defined(CONFIG_DISPLAY_CPUINFO)
+
+static char *get_imx_type(u32 imxtype)
+{
+ switch (imxtype) {
+ case 0x63:
+ return "6Q"; /* Quad-core version of the mx6 */
+ case 0x61:
+ return "6DS"; /* Dual/Solo version of the mx6 */
+ case 0x60:
+ return "6SL"; /* Solo-Lite version of the mx6 */
+ case 0x51:
+ return "51";
+ case 0x53:
+ return "53";
+ default:
+ return "unknown";
+ }
+}
+
int print_cpuinfo(void)
{
u32 cpurev;
cpurev = get_cpu_rev();
- printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
- (cpurev & 0xFF000) >> 12,
+
+ printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
+ get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
#elif defined(CONFIG_MX53)
+ /* Switch peripheral to PLL2 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00808145
+ orr r1, r1, #(2 << 10)
+ orr r1, r1, #(0 << 16)
+ orr r1, r1, #(1 << 19)
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ ldr r1, =0x00016154
+ str r1, [r0, #CLKCTL_CBCMR]
+ /* Change uart clk parent to pll2*/
+ ldr r1, [r0, #CLKCTL_CSCMR1]
+ and r1, r1, #0xfcffffff
+ orr r1, r1, #0x01000000
+ str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, [r0, #CLKCTL_CSCDR1]
- orr r1, r1, #0x3f
- eor r1, r1, #0x3f
- orr r1, r1, #0x21
+ and r1, r1, #0xffffffc0
+ orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
#endif
/* make sure divider effective */
struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
+void enable_usboh3_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
+ else
+ reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
+ __raw_writel(reg, &imx_ccm->CCGR6);
+
+}
+
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
u32 div;
u32 get_cpu_rev(void)
{
- int system_rev = 0x61000 | CHIP_REV_1_0;
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int reg = readl(&anatop->digprog);
+
+ /* Read mx6 variant: quad, dual or solo */
+ int system_rev = (reg >> 4) & 0xFF000;
+ /* Read mx6 silicon revision */
+ system_rev |= (reg & 0xFF) + 0x10;
return system_rev;
}
ifdef CONFIG_SPL_MMC_SUPPORT
COBJS += spl_mmc.o
endif
+ifdef CONFIG_SPL_YMODEM_SUPPORT
+COBJS += spl_ymodem.o
+endif
endif
ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
static void setup_non_essential_dplls(void)
{
- u32 sys_clk_khz, abe_ref_clk;
+ u32 abe_ref_clk;
const struct dpll_params *params;
- sys_clk_khz = get_sys_clk_freq() / 1000;
-
/* IVA */
clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
}
+/*
+ * Default function to determine if u-boot or the OS should
+ * be started. This implementation always returns 1.
+ *
+ * Please implement your own board specific funcion to do this.
+ *
+ * RETURN
+ * 0 to not start u-boot
+ * positive if u-boot should start
+ */
+#ifdef CONFIG_SPL_OS_BOOT
+__weak int spl_start_uboot(void)
+{
+ printf("SPL: Please implement spl_start_uboot() for your board\n");
+ printf("SPL: Direct Linux boot not active!\n");
+ return 1;
+}
+#endif
+
void spl_parse_image_header(const struct image_header *header)
{
u32 header_size = sizeof(struct image_header);
/* Signature not found - assume u-boot.bin */
printf("mkimage signature not found - ih_magic = %x\n",
header->ih_magic);
- puts("Assuming u-boot.bin ..\n");
+ debug("Assuming u-boot.bin ..\n");
/* Let's assume U-Boot will not be more than 200 KB */
spl_image.size = 200 * 1024;
spl_image.entry_point = CONFIG_SYS_TEXT_BASE;
}
}
-static void jump_to_image_no_args(void)
+/*
+ * This function jumps to an image with argument. Normally an FDT or ATAGS
+ * image.
+ * arg: Pointer to paramter image in RAM
+ */
+#ifdef CONFIG_SPL_OS_BOOT
+static void __noreturn jump_to_image_linux(void *arg)
+{
+ debug("Entering kernel arg pointer: 0x%p\n", arg);
+ typedef void (*image_entry_arg_t)(int, int, void *)
+ __attribute__ ((noreturn));
+ image_entry_arg_t image_entry =
+ (image_entry_arg_t) spl_image.entry_point;
+ cleanup_before_linux();
+ image_entry(0, CONFIG_MACH_TYPE, arg);
+}
+#endif
+
+static void __noreturn jump_to_image_no_args(void)
{
- typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn));
+ typedef void __noreturn (*image_entry_noargs_t)(u32 *);
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image.entry_point;
image_entry((u32 *)boot_params_ptr_addr);
}
-void jump_to_image_no_args(void) __attribute__ ((noreturn));
void board_init_r(gd_t *id, ulong dummy)
{
u32 boot_device;
case BOOT_DEVICE_NAND:
spl_nand_load_image();
break;
+#endif
+#ifdef CONFIG_SPL_YMODEM_SUPPORT
+ case BOOT_DEVICE_UART:
+ spl_ymodem_load_image();
+ break;
#endif
default:
printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);
debug("Jumping to U-Boot\n");
jump_to_image_no_args();
break;
+#ifdef CONFIG_SPL_OS_BOOT
+ case IH_OS_LINUX:
+ debug("Jumping to Linux\n");
+ spl_board_prepare_for_linux();
+ jump_to_image_linux((void *)CONFIG_SYS_SPL_ARGS_ADDR);
+ break;
+#endif
default:
puts("Unsupported OS image.. Jumping nevertheless..\n");
jump_to_image_no_args();
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
#include <nand.h>
#include <version.h>
#include <asm/omap_common.h>
-
void spl_nand_load_image(void)
{
struct image_header *header;
+ int *src __attribute__((unused));
+ int *dst __attribute__((unused));
+
switch (omap_boot_mode()) {
case NAND_MODE_HW_ECC:
debug("spl: nand - using hw ecc\n");
/*use CONFIG_SYS_TEXT_BASE as temporary storage area */
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+#ifdef CONFIG_SPL_OS_BOOT
+ if (!spl_start_uboot()) {
+ /*
+ * load parameter image
+ * load to temp position since nand_spl_load_image reads
+ * a whole block which is typically larger than
+ * CONFIG_CMD_SAVEBP_WRITE_SIZE therefore may overwrite
+ * following sections like BSS
+ */
+ nand_spl_load_image(CONFIG_CMD_SPL_NAND_OFS,
+ CONFIG_CMD_SPL_WRITE_SIZE,
+ (void *)CONFIG_SYS_TEXT_BASE);
+ /* copy to destintion */
+ for (dst = (int *)CONFIG_SYS_SPL_ARGS_ADDR,
+ src = (int *)CONFIG_SYS_TEXT_BASE;
+ src < (int *)(CONFIG_SYS_TEXT_BASE +
+ CONFIG_CMD_SPL_WRITE_SIZE);
+ src++, dst++) {
+ writel(readl(src), dst);
+ }
+ /* load linux */
+ nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
+ CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+ spl_parse_image_header(header);
+ if (header->ih_os == IH_OS_LINUX) {
+ /* happy - was a linux */
+ nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
+ spl_image.size, (void *)spl_image.load_addr);
+ nand_deselect();
+ return;
+ } else {
+ printf("The Expected Linux image was not"
+ "found. Please check your NAND"
+ "configuration.\n");
+ printf("Trying to start u-boot now...\n");
+ }
+ }
+#endif
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET,
CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
spl_parse_image_header(header);
nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size,
- (void *)image_load_addr);
+ (void *)spl_image.load_addr);
#ifdef CONFIG_ENV_OFFSET_REDUND
nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND,
CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
spl_parse_image_header(header);
nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size,
- (void *)image_load_addr);
+ (void *)spl_image.load_addr);
#endif
#endif
/* Load u-boot */
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Matt Porter <mporter@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <xyzModem.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+
+#define BUF_SIZE 1024
+
+static int getcymodem(void) {
+ if (tstc())
+ return (getc());
+ return -1;
+}
+
+void spl_ymodem_load_image(void)
+{
+ int size = 0;
+ int err;
+ int res;
+ int ret;
+ connection_info_t info;
+ char buf[BUF_SIZE];
+ ulong store_addr = ~0;
+ ulong addr = 0;
+
+ info.mode = xyzModem_ymodem;
+ ret = xyzModem_stream_open(&info, &err);
+
+ if (!ret) {
+ while ((res =
+ xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
+ if (addr == 0)
+ spl_parse_image_header((struct image_header *)buf);
+ store_addr = addr + spl_image.load_addr;
+ size += res;
+ addr += res;
+ memcpy((char *)(store_addr), buf, res);
+ }
+ } else {
+ printf("spl: ymodem err - %s\n", xyzModem_error(err));
+ hang();
+ }
+
+ xyzModem_stream_close(&err);
+ xyzModem_stream_terminate(false, &getcymodem);
+
+ printf("Loaded %d bytes\n", size);
+}
void spl_board_init(void)
{
+#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
}
#endif /* CONFIG_SPL_BUILD */
write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
rfr_ctrl, mr);
make_cs1_contiguous();
- write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,
+ write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb,
rfr_ctrl, mr);
#endif
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
static int is_cpu_powered(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
}
static void remove_cpu_io_clamps(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
u32 reg;
/* Remove the clamps on the CPU I/O signals */
static void powerup_cpu(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
static void enable_cpu_power_rail(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_cntrl);
void init_pmc_scratch(void)
{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
int i;
/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
writel(0xC0, &pmt->pmt_cfg_ctl);
/*
- * If we are ARM7 - give it a different stack. We are about to
- * start up the A9 which will want to use this one.
- */
- asm volatile("ldr sp, =%c0\n"
- : : "i"(AVP_EARLY_BOOT_STACK_LIMIT));
+ * If we are ARM7 - give it a different stack. We are about to
+ * start up the A9 which will want to use this one.
+ */
+ asm volatile("mov sp, %0\n"
+ : : "r"(AVP_EARLY_BOOT_STACK_LIMIT));
start_cpu((u32)_start);
halt_avp();
unsigned int query_sdram_size(void)
{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_scratch20);
#include <asm/arch/tegra2.h>
#include <common.h>
#include <div64.h>
+#include <fdtdec.h>
/*
* This is our record of the current clock rate of each clock. We don't
CLOCK_TYPE_MCPT,
CLOCK_TYPE_PCM,
CLOCK_TYPE_PCMT,
+ CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
CLOCK_TYPE_PCXTS,
CLOCK_TYPE_PDCT,
{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
{ CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
};
/* 0x08 */
TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
/* 0x28 */
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
/* 0x30 */
* Given the parent's rate and the required rate for the children, this works
* out the peripheral clock divider to use, in 7.1 binary format.
*
+ * @param divider_bits number of divider bits (8 or 16)
* @param parent_rate clock rate of parent clock in Hz
* @param rate required clock rate for this clock
* @return divider which should be used
*/
-static int clk_div7_1_get_divider(unsigned long parent_rate,
- unsigned long rate)
+static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
+ unsigned long rate)
{
u64 divider = parent_rate * 2;
+ unsigned max_divider = 1 << divider_bits;
divider += rate - 1;
do_div(divider, rate);
if ((s64)divider - 2 < 0)
return 0;
- if ((s64)divider - 2 > 255)
+ if ((s64)divider - 2 >= max_divider)
return -1;
return divider - 2;
* required child clock rate. This function assumes that a second-stage
* divisor is available which can divide by powers of 2 from 1 to 256.
*
+ * @param divider_bits number of divider bits (8 or 16)
* @param parent_rate clock rate of parent clock in Hz
* @param rate required clock rate for this clock
* @param extra_div value for the second-stage divisor (not set if this
* @return divider which should be used, or -1 if nothing is valid
*
*/
-static int find_best_divider(unsigned long parent_rate, unsigned long rate,
- int *extra_div)
+static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
+ unsigned long rate, int *extra_div)
{
int shift;
int best_divider = -1;
/* try dividers from 1 to 256 and find closest match */
for (shift = 0; shift <= 8 && best_error > 0; shift++) {
unsigned divided_parent = parent_rate >> shift;
- int divider = clk_div7_1_get_divider(divided_parent, rate);
+ int divider = clk_get_divider(divider_bits, divided_parent,
+ rate);
unsigned effective_rate = get_rate_from_divider(divided_parent,
divider);
int error = rate - effective_rate;
* @param periph_id peripheral to start
* @param source PLL id of required parent clock
* @param mux_bits Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
* @return mux value (0-4, or -1 if not found)
*/
static int get_periph_clock_source(enum periph_id periph_id,
- enum clock_id parent, int *mux_bits)
+ enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
enum periphc_internal_id internal_id;
type = clock_periph_type[internal_id];
assert(clock_type_id_isvalid(type));
- /* Special case here for the clock with a 4-bit source mux */
+ /*
+ * Special cases here for the clock with a 4-bit source mux and I2C
+ * with its 16-bit divisor
+ */
if (type == CLOCK_TYPE_PCXTS)
*mux_bits = 4;
else
*mux_bits = 2;
+ if (type == CLOCK_TYPE_PCMT16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
* Adjust peripheral PLL to use the given divider and source.
*
* @param periph_id peripheral to adjust
- * @param parent Required parent clock (for source mux)
- * @param divider Required divider in 7.1 format
+ * @param source Source number (0-3 or 0-7)
+ * @param mux_bits Number of mux bits (2 or 4)
+ * @param divider Required divider in 7.1 or 15.1 format
* @return 0 if ok, -1 on error (requesting a parent clock which is not valid
* for this peripheral)
*/
-static int adjust_periph_pll(enum periph_id periph_id,
- enum clock_id parent, unsigned divider)
+static int adjust_periph_pll(enum periph_id periph_id, int source,
+ int mux_bits, unsigned divider)
{
u32 *reg = get_periph_source_reg(periph_id);
- unsigned source;
- int mux_bits;
clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
divider << OUT_CLK_DIVISOR_SHIFT);
udelay(1);
/* work out the source clock and set it */
- source = get_periph_clock_source(periph_id, parent, &mux_bits);
if (source < 0)
return -1;
if (mux_bits == 4) {
enum clock_id parent, unsigned rate, int *extra_div)
{
unsigned effective_rate;
+ int mux_bits, divider_bits, source;
int divider;
+ /* work out the source clock and set it */
+ source = get_periph_clock_source(periph_id, parent, &mux_bits,
+ ÷r_bits);
+
if (extra_div)
- divider = find_best_divider(pll_rate[parent], rate, extra_div);
+ divider = find_best_divider(divider_bits, pll_rate[parent],
+ rate, extra_div);
else
- divider = clk_div7_1_get_divider(pll_rate[parent], rate);
+ divider = clk_get_divider(divider_bits, pll_rate[parent],
+ rate);
assert(divider >= 0);
- if (adjust_periph_pll(periph_id, parent, divider))
+ if (adjust_periph_pll(periph_id, source, mux_bits, divider))
return -1U;
debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
get_periph_source_reg(periph_id),
reset_set_enable(periph_id, 0);
}
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id Clock ID according to tegra2 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+static enum periph_id clk_id_to_periph_id(int clk_id)
+{
+ if (clk_id > 95)
+ return PERIPH_ID_NONE;
+
+ switch (clk_id) {
+ case 1:
+ case 2:
+ case 7:
+ case 10:
+ case 20:
+ case 30:
+ case 35:
+ case 49:
+ case 56:
+ case 74:
+ case 76:
+ case 77:
+ case 78:
+ case 79:
+ case 80:
+ case 81:
+ case 82:
+ case 83:
+ case 91:
+ case 95:
+ return PERIPH_ID_NONE;
+ default:
+ return clk_id;
+ }
+}
+
+int clock_decode_periph_id(const void *blob, int node)
+{
+ enum periph_id id;
+ u32 cell[2];
+ int err;
+
+ err = fdtdec_get_int_array(blob, node, "clocks", cell,
+ ARRAY_SIZE(cell));
+ if (err)
+ return -1;
+ id = clk_id_to_periph_id(cell[1]);
+ assert(clock_periph_id_isvalid(id));
+ return id;
+}
+#endif /* CONFIG_OF_CONTROL */
+
int clock_verify(void)
{
struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
endif
USE_PRIVATE_LIBGCC = yes
+
+CONFIG_ARCH_DEVICE_TREE := tegra20
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/uart.h>
+#include <asm/arch/usb.h>
+#include <libfdt.h>
+#include <fdtdec.h>
+
+enum {
+ USB_PORTS_MAX = 4, /* Maximum ports we allow */
+};
+
+/* Parameters we need for USB */
+enum {
+ PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
+ PARAM_DIVM, /* PLL INPUT DIVIDER */
+ PARAM_DIVP, /* POST DIVIDER (2^N) */
+ PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
+ PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
+ PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
+ PARAM_STABLE_COUNT, /* PLL-U STABLE count */
+ PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
+ PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
+ PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
+ PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
+
+ PARAM_COUNT
+};
+
+/* Possible port types (dual role mode) */
+enum dr_mode {
+ DR_MODE_NONE = 0,
+ DR_MODE_HOST, /* supports host operation */
+ DR_MODE_DEVICE, /* supports device operation */
+ DR_MODE_OTG, /* supports both */
+};
+
+/* Information about a USB port */
+struct fdt_usb {
+ struct usb_ctlr *reg; /* address of registers in physical memory */
+ unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
+ unsigned enabled:1; /* 1 to enable, 0 to disable */
+ unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
+ enum dr_mode dr_mode; /* dual role mode */
+ enum periph_id periph_id;/* peripheral id */
+ struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
+};
+
+static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
+static unsigned port_count; /* Number of available ports */
+static int port_current; /* Current port (-1 = none) */
+
+/*
+ * This table has USB timing parameters for each Oscillator frequency we
+ * support. There are four sets of values:
+ *
+ * 1. PLLU configuration information (reference clock is osc/clk_m and
+ * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
+ *
+ * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
+ * ----------------------------------------------------------------------
+ * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
+ * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
+ * Filter frequency (MHz) 1 4.8 6 2
+ * CPCON 1100b 0011b 1100b 1100b
+ * LFCON0 0 0 0 0
+ *
+ * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
+ *
+ * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
+ * ---------------------------------------------------------------------------
+ * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
+ * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
+ * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
+ * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
+ *
+ * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
+ * SessEnd. Each of these signals have their own debouncer and for each of
+ * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
+ * BIAS_DEBOUNCE_B).
+ *
+ * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
+ * 0xffff -> No debouncing at all
+ * <n> ms = <n> *1000 / (1/19.2MHz) / 4
+ *
+ * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
+ * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
+ *
+ * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
+ * values, so we can keep those to default.
+ *
+ * 4. The 20 microsecond delay after bias cell operation.
+ */
+static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+ /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
+ { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
+ { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
+ { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
+ { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
+};
+
+/* UTMIP Idle Wait Delay */
+static const u8 utmip_idle_wait_delay = 17;
+
+/* UTMIP Elastic limit */
+static const u8 utmip_elastic_limit = 16;
+
+/* UTMIP High Speed Sync Start Delay */
+static const u8 utmip_hs_sync_start_delay = 9;
+
+/* Put the port into host mode (this only works for OTG ports) */
+static void set_host_mode(struct fdt_usb *config)
+{
+ if (config->dr_mode == DR_MODE_OTG) {
+ /* Check whether remote host from USB1 is driving VBus */
+ if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)
+ return;
+
+ /*
+ * If not driving, we set the GPIO to enable VBUS. We assume
+ * that the pinmux is set up correctly for this.
+ */
+ if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+ fdtdec_setup_gpio(&config->vbus_gpio);
+ gpio_direction_output(config->vbus_gpio.gpio, 1);
+ debug("set_host_mode: GPIO %d high\n",
+ config->vbus_gpio.gpio);
+ }
+ }
+}
+
+void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
+{
+ /* Reset the USB controller with 2us delay */
+ reset_periph(config->periph_id, 2);
+
+ /*
+ * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
+ * base address
+ */
+ if (config->has_legacy_mode)
+ setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
+
+ /* Put UTMIP1/3 in reset */
+ setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+ /* Enable the UTMIP PHY */
+ if (config->utmi)
+ setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
+
+ /*
+ * TODO: where do we take the USB1 out of reset? The old code would
+ * take USB3 out of reset, but not USB1. This code doesn't do either.
+ */
+}
+
+/* set up the USB controller with the parameters provided */
+static int init_usb_controller(struct fdt_usb *config,
+ struct usb_ctlr *usbctlr, const u32 timing[])
+{
+ u32 val;
+ int loop_count;
+
+ clock_enable(config->periph_id);
+
+ /* Reset the usb controller */
+ usbf_reset_controller(config, usbctlr);
+
+ /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
+ clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+ /* Follow the crystal clock disable by >100ns delay */
+ udelay(1);
+
+ /*
+ * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
+ * mux must be switched to actually use a_sess_vld threshold.
+ */
+ if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+ clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
+ VBUS_SENSE_CTL_MASK,
+ VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
+ }
+
+ /*
+ * PLL Delay CONFIGURATION settings. The following parameters control
+ * the bring up of the plls.
+ */
+ val = readl(&usbctlr->utmip_misc_cfg1);
+ clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
+ timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
+ clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
+ timing[PARAM_ACTIVE_DELAY_COUNT] <<
+ UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
+ writel(val, &usbctlr->utmip_misc_cfg1);
+
+ /* Set PLL enable delay count and crystal frequency count */
+ val = readl(&usbctlr->utmip_pll_cfg1);
+ clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
+ timing[PARAM_ENABLE_DELAY_COUNT] <<
+ UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
+ clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
+ timing[PARAM_XTAL_FREQ_COUNT] <<
+ UTMIP_XTAL_FREQ_COUNT_SHIFT);
+ writel(val, &usbctlr->utmip_pll_cfg1);
+
+ /* Setting the tracking length time */
+ clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
+ UTMIP_BIAS_PDTRK_COUNT_MASK,
+ timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
+
+ /* Program debounce time for VBUS to become valid */
+ clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
+ UTMIP_DEBOUNCE_CFG0_MASK,
+ timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
+
+ setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
+
+ /* Disable battery charge enabling bit */
+ setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
+
+ clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
+ setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
+
+ /*
+ * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
+ * Setting these fields, together with default values of the
+ * other fields, results in programming the registers below as
+ * follows:
+ * UTMIP_HSRX_CFG0 = 0x9168c000
+ * UTMIP_HSRX_CFG1 = 0x13
+ */
+
+ /* Set PLL enable delay count and Crystal frequency count */
+ val = readl(&usbctlr->utmip_hsrx_cfg0);
+ clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
+ utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
+ clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
+ utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
+ writel(val, &usbctlr->utmip_hsrx_cfg0);
+
+ /* Configure the UTMIP_HS_SYNC_START_DLY */
+ clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
+ UTMIP_HS_SYNC_START_DLY_MASK,
+ utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
+
+ /* Preceed the crystal clock disable by >100ns delay. */
+ udelay(1);
+
+ /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
+ setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+ /* Finished the per-controller init. */
+
+ /* De-assert UTMIP_RESET to bring out of reset. */
+ clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+ /* Wait for the phy clock to become valid in 100 ms */
+ for (loop_count = 100000; loop_count != 0; loop_count--) {
+ if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
+ break;
+ udelay(1);
+ }
+ if (loop_count == 100000)
+ return -1;
+
+ return 0;
+}
+
+static void power_up_port(struct usb_ctlr *usbctlr)
+{
+ /* Deassert power down state */
+ clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
+ UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
+ clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
+ UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
+}
+
+static void config_clock(const u32 timing[])
+{
+ clock_start_pll(CLOCK_ID_USB,
+ timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
+ timing[PARAM_CPCON], timing[PARAM_LFCON]);
+}
+
+/**
+ * Add a new USB port to the list of available ports.
+ *
+ * @param config USB port configuration
+ * @return 0 if ok, -1 if error (too many ports)
+ */
+static int add_port(struct fdt_usb *config, const u32 timing[])
+{
+ struct usb_ctlr *usbctlr = config->reg;
+
+ if (port_count == USB_PORTS_MAX) {
+ debug("tegrausb: Cannot register more than %d ports\n",
+ USB_PORTS_MAX);
+ return -1;
+ }
+ if (init_usb_controller(config, usbctlr, timing)) {
+ debug("tegrausb: Cannot init port\n");
+ return -1;
+ }
+ if (config->utmi) {
+ /* Disable ICUSB FS/LS transceiver */
+ clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
+
+ /* Select UTMI parallel interface */
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS);
+ power_up_port(usbctlr);
+ }
+ port[port_count++] = *config;
+
+ return 0;
+}
+
+int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor)
+{
+ struct usb_ctlr *usbctlr;
+
+ if (portnum >= port_count)
+ return -1;
+ tegrausb_stop_port();
+ set_host_mode(&port[portnum]);
+
+ usbctlr = port[portnum].reg;
+ *hccr = (u32)&usbctlr->cap_length;
+ *hcor = (u32)&usbctlr->usb_cmd;
+ port_current = portnum;
+ return 0;
+}
+
+int tegrausb_stop_port(void)
+{
+ struct usb_ctlr *usbctlr;
+
+ if (port_current == -1)
+ return -1;
+
+ usbctlr = port[port_current].reg;
+
+ /* Stop controller */
+ writel(0, &usbctlr->usb_cmd);
+ udelay(1000);
+
+ /* Initiate controller reset */
+ writel(2, &usbctlr->usb_cmd);
+ udelay(1000);
+ port_current = -1;
+ return 0;
+}
+
+int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
+ struct fdt_usb *config)
+{
+ const char *phy, *mode;
+
+ config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ if (mode) {
+ if (0 == strcmp(mode, "host"))
+ config->dr_mode = DR_MODE_HOST;
+ else if (0 == strcmp(mode, "peripheral"))
+ config->dr_mode = DR_MODE_DEVICE;
+ else if (0 == strcmp(mode, "otg"))
+ config->dr_mode = DR_MODE_OTG;
+ else {
+ debug("%s: Cannot decode dr_mode '%s'\n", __func__,
+ mode);
+ return -FDT_ERR_NOTFOUND;
+ }
+ } else {
+ config->dr_mode = DR_MODE_HOST;
+ }
+
+ phy = fdt_getprop(blob, node, "phy_type", NULL);
+ config->utmi = phy && 0 == strcmp("utmi", phy);
+ config->enabled = fdtdec_get_is_enabled(blob, node);
+ config->has_legacy_mode = fdtdec_get_bool(blob, node,
+ "nvidia,has-legacy-mode");
+ config->periph_id = clock_decode_periph_id(blob, node);
+ if (config->periph_id == PERIPH_ID_NONE) {
+ debug("%s: Missing/invalid peripheral ID\n", __func__);
+ return -FDT_ERR_NOTFOUND;
+ }
+ fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
+ debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, "
+ "dr_mode=%d\n", config->enabled, config->has_legacy_mode,
+ config->utmi, config->periph_id, config->vbus_gpio.gpio,
+ config->dr_mode);
+
+ return 0;
+}
+
+int board_usb_init(const void *blob)
+{
+ struct fdt_usb config;
+ unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
+ enum clock_osc_freq freq;
+ int node_list[USB_PORTS_MAX];
+ int node, count, i;
+
+ /* Set up the USB clocks correctly based on our oscillator frequency */
+ freq = clock_get_osc_freq();
+ config_clock(usb_pll[freq]);
+
+ /* count may return <0 on error */
+ count = fdtdec_find_aliases_for_id(blob, "usb",
+ COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
+ for (i = 0; i < count; i++) {
+ debug("USB %d: ", i);
+ node = node_list[i];
+ if (!node)
+ continue;
+ if (fdt_decode_usb(blob, node, osc_freq, &config)) {
+ debug("Cannot decode USB node %s\n",
+ fdt_get_name(blob, node, NULL));
+ return -1;
+ }
+
+ if (add_port(&config, usb_pll[freq]))
+ return -1;
+ set_host_mode(&config);
+ }
+ port_current = -1;
+
+ return 0;
+}
PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
+PLATFORM_LDFLAGS += -EB
+USE_PRIVATE_LIBGCC = yes
+
# -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error
PLATFORM_RELFLAGS += -ffunction-sections
LDFLAGS_u-boot += --gc-sections
/*
* Initialize Control plane
*/
- if (ixEthDBInit() != IX_ETH_ACC_SUCCESS)
+ if (ixEthDBInit() != IX_ETH_DB_SUCCESS)
{
IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0);
IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
{
IxNpeMhMessage message;
- IxOsalMutex *ackPortAddressLock;
IX_STATUS result;
/* use this macro instead CHECK_PORT
return IX_ETH_DB_PORT_UNINITIALIZED;
}
- ackPortAddressLock = &ixEthDBPortInfo[portID].npeAckLock;
-
/* Operation stops here when Ethernet Learning is not enabled */
if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
{
#ifndef NDEBUG
UINT8 i = 0;
- IxQMgrQInfo *q;
UINT32 intEnableRegVal = 0;
printf ("Livelock statistics are printed on the fly.\n");
for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
{
- q = &dispatchQInfo[i];
-
if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER)
{
printf (" %2d ", i);
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/lh7a40x/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
+
+ulong get_tbclk(void)
+{
+ return TIMER_FREQ_HZ;
+}
+++ /dev/null
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/pxa/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- . = ALIGN(4096);
-
- .mmutable : {
- *(.mmutable)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/s3c44b0/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (C) Copyright 2003-2004
- * MontaVista Software, Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/sa1100/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
/*
- * January 2004 - Changed to support H4 device
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
- arch/arm/cpu/armv7/start.o (.text)
+ __image_copy_start = .;
+ CPUDIR/start.o (.text)
*(.text)
}
_end = .;
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss)
--- /dev/null
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value. The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+ aliases { };
+ memory { device_type = "memory"; reg = <0 0>; };
+};
--- /dev/null
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "nvidia,tegra20";
+ interrupt-parent = <&intc>;
+
+ tegra_car: clock@60006000 {
+ compatible = "nvidia,tegra20-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ intc: interrupt-controller@50041000 {
+ compatible = "nvidia,tegra20-gic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = < 0x50041000 0x1000 >,
+ < 0x50040100 0x0100 >;
+ };
+
+ i2c@7000c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000C000 0x100>;
+ interrupts = < 70 >;
+ /* PERIPH_ID_I2C1, PLL_P_OUT3 */
+ clocks = <&tegra_car 12>, <&tegra_car 124>;
+ };
+
+ i2c@7000c400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000C400 0x100>;
+ interrupts = < 116 >;
+ /* PERIPH_ID_I2C2, PLL_P_OUT3 */
+ clocks = <&tegra_car 54>, <&tegra_car 124>;
+ };
+
+ i2c@7000c500 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000C500 0x100>;
+ interrupts = < 124 >;
+ /* PERIPH_ID_I2C3, PLL_P_OUT3 */
+ clocks = <&tegra_car 67>, <&tegra_car 124>;
+ };
+
+ i2c@7000d000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2c-dvc";
+ reg = <0x7000D000 0x200>;
+ interrupts = < 85 >;
+ /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
+ clocks = <&tegra_car 47>, <&tegra_car 124>;
+ };
+
+ i2s@70002800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2s";
+ reg = <0x70002800 0x200>;
+ interrupts = < 45 >;
+ dma-channel = < 2 >;
+ };
+
+ i2s@70002a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2s";
+ reg = <0x70002a00 0x200>;
+ interrupts = < 35 >;
+ dma-channel = < 1 >;
+ };
+
+ das@70000c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-das";
+ reg = <0x70000c00 0x80>;
+ };
+
+ gpio: gpio@6000d000 {
+ compatible = "nvidia,tegra20-gpio";
+ reg = < 0x6000d000 0x1000 >;
+ interrupts = < 64 65 66 67 87 119 121 >;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ pinmux: pinmux@70000000 {
+ compatible = "nvidia,tegra20-pinmux";
+ reg = < 0x70000014 0x10 /* Tri-state registers */
+ 0x70000080 0x20 /* Mux registers */
+ 0x700000a0 0x14 /* Pull-up/down registers */
+ 0x70000868 0xa8 >; /* Pad control registers */
+ };
+
+ serial@70006000 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006000 0x40>;
+ reg-shift = <2>;
+ interrupts = < 68 >;
+ };
+
+ serial@70006040 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006040 0x40>;
+ reg-shift = <2>;
+ interrupts = < 69 >;
+ };
+
+ serial@70006200 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006200 0x100>;
+ reg-shift = <2>;
+ interrupts = < 78 >;
+ };
+
+ serial@70006300 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006300 0x100>;
+ reg-shift = <2>;
+ interrupts = < 122 >;
+ };
+
+ serial@70006400 {
+ compatible = "nvidia,tegra20-uart";
+ reg = <0x70006400 0x100>;
+ reg-shift = <2>;
+ interrupts = < 123 >;
+ };
+
+ sdhci@c8000000 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000000 0x200>;
+ interrupts = < 46 >;
+ };
+
+ sdhci@c8000200 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000200 0x200>;
+ interrupts = < 47 >;
+ };
+
+ sdhci@c8000400 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000400 0x200>;
+ interrupts = < 51 >;
+ };
+
+ sdhci@c8000600 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000600 0x200>;
+ interrupts = < 63 >;
+ };
+
+ usb@c5000000 {
+ compatible = "nvidia,tegra20-ehci", "usb-ehci";
+ reg = <0xc5000000 0x4000>;
+ interrupts = < 52 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
+ nvidia,has-legacy-mode;
+ };
+
+ usb@c5004000 {
+ compatible = "nvidia,tegra20-ehci", "usb-ehci";
+ reg = <0xc5004000 0x4000>;
+ interrupts = < 53 >;
+ phy_type = "ulpi";
+ clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
+ };
+
+ usb@c5008000 {
+ compatible = "nvidia,tegra20-ehci", "usb-ehci";
+ reg = <0xc5008000 0x4000>;
+ interrupts = < 129 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
+ };
+
+};
#define __DMC_H__
#ifndef __ASSEMBLY__
+struct exynos4_dmc {
+ unsigned int concontrol;
+ unsigned int memcontrol;
+ unsigned int memconfig0;
+ unsigned int memconfig1;
+ unsigned int directcmd;
+ unsigned int prechconfig;
+ unsigned int phycontrol0;
+ unsigned int phycontrol1;
+ unsigned int phycontrol2;
+ unsigned int phycontrol3;
+ unsigned int pwrdnconfig;
+ unsigned char res1[0x4];
+ unsigned int timingref;
+ unsigned int timingrow;
+ unsigned int timingdata;
+ unsigned int timingpower;
+ unsigned int phystatus;
+ unsigned int phyzqcontrol;
+ unsigned int chip0status;
+ unsigned int chip1status;
+ unsigned int arefstatus;
+ unsigned int mrstatus;
+ unsigned int phytest0;
+ unsigned int phytest1;
+ unsigned int qoscontrol0;
+ unsigned int qosconfig0;
+ unsigned int qoscontrol1;
+ unsigned int qosconfig1;
+ unsigned int qoscontrol2;
+ unsigned int qosconfig2;
+ unsigned int qoscontrol3;
+ unsigned int qosconfig3;
+ unsigned int qoscontrol4;
+ unsigned int qosconfig4;
+ unsigned int qoscontrol5;
+ unsigned int qosconfig5;
+ unsigned int qoscontrol6;
+ unsigned int qosconfig6;
+ unsigned int qoscontrol7;
+ unsigned int qosconfig7;
+ unsigned int qoscontrol8;
+ unsigned int qosconfig8;
+ unsigned int qoscontrol9;
+ unsigned int qosconfig9;
+ unsigned int qoscontrol10;
+ unsigned int qosconfig10;
+ unsigned int qoscontrol11;
+ unsigned int qosconfig11;
+ unsigned int qoscontrol12;
+ unsigned int qosconfig12;
+ unsigned int qoscontrol13;
+ unsigned int qosconfig13;
+ unsigned int qoscontrol14;
+ unsigned int qosconfig14;
+ unsigned int qoscontrol15;
+ unsigned int qosconfig15;
+ unsigned int qostimeout0;
+ unsigned int qostimeout1;
+ unsigned char res2[0x8];
+ unsigned int ivcontrol;
+ unsigned char res3[0x8];
+ unsigned int perevconfig;
+ unsigned char res4[0xDF00];
+ unsigned int pmnc_ppc_a;
+ unsigned char res5[0xC];
+ unsigned int cntens_ppc_a;
+ unsigned char res6[0xC];
+ unsigned int cntenc_ppc_a;
+ unsigned char res7[0xC];
+ unsigned int intens_ppc_a;
+ unsigned char res8[0xC];
+ unsigned int intenc_ppc_a;
+ unsigned char res9[0xC];
+ unsigned int flag_ppc_a;
+ unsigned char res10[0xAC];
+ unsigned int ccnt_ppc_a;
+ unsigned char res11[0xC];
+ unsigned int pmcnt0_ppc_a;
+ unsigned char res12[0xC];
+ unsigned int pmcnt1_ppc_a;
+ unsigned char res13[0xC];
+ unsigned int pmcnt2_ppc_a;
+ unsigned char res14[0xC];
+ unsigned int pmcnt3_ppc_a;
+ unsigned char res15[0xEBC];
+ unsigned int pmnc_ppc_m;
+ unsigned char res16[0xC];
+ unsigned int cntens_ppc_m;
+ unsigned char res17[0xC];
+ unsigned int cntenc_ppc_m;
+ unsigned char res18[0xC];
+ unsigned int intens_ppc_m;
+ unsigned char res19[0xC];
+ unsigned int intenc_ppc_m;
+ unsigned char res20[0xC];
+ unsigned int flag_ppc_m;
+ unsigned char res21[0xAC];
+ unsigned int ccnt_ppc_m;
+ unsigned char res22[0xC];
+ unsigned int pmcnt0_ppc_m;
+ unsigned char res23[0xC];
+ unsigned int pmcnt1_ppc_m;
+ unsigned char res24[0xC];
+ unsigned int pmcnt2_ppc_m;
+ unsigned char res25[0xC];
+ unsigned int pmcnt3_ppc_m;
+};
+
struct exynos5_dmc {
unsigned int concontrol;
unsigned int memcontrol;
#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
+#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \
+ IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R)
+
/*
* Macros to make it easy to access the GPIO registers
*/
#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line))
#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line))
#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line))
-#define GPIO_INT_ACT_LOW_SET(line) *IXP425_GPIO_GPIT1R = \
- (*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3))
+#define GPIO_INT_ACT_LOW_SET(line) \
+ *IXP425_GPIO_GPITR(line) = \
+ (*IXP425_GPIO_GPITR(line) & \
+ ~(0x7 << (((line) & 0x7) * 3))) | \
+ (0x1 << (((line) & 0x7) * 3)) \
/*
* Constants to make it easy to access Timer Control/Status registers
#include <asm/arch/regs-base.h>
#include <asm/arch/regs-bch.h>
#include <asm/arch/regs-clkctrl.h>
+#include <asm/arch/regs-digctl.h>
#include <asm/arch/regs-gpmi.h>
#include <asm/arch/regs-i2c.h>
#include <asm/arch/regs-ocotp.h>
#ifndef __ASSEMBLY__
struct mx28_apbh_regs {
- mx28_reg(hw_apbh_ctrl0)
- mx28_reg(hw_apbh_ctrl1)
- mx28_reg(hw_apbh_ctrl2)
- mx28_reg(hw_apbh_channel_ctrl)
- mx28_reg(hw_apbh_devsel)
- mx28_reg(hw_apbh_dma_burst_size)
- mx28_reg(hw_apbh_debug)
+ mx28_reg_32(hw_apbh_ctrl0)
+ mx28_reg_32(hw_apbh_ctrl1)
+ mx28_reg_32(hw_apbh_ctrl2)
+ mx28_reg_32(hw_apbh_channel_ctrl)
+ mx28_reg_32(hw_apbh_devsel)
+ mx28_reg_32(hw_apbh_dma_burst_size)
+ mx28_reg_32(hw_apbh_debug)
uint32_t reserved[36];
union {
struct {
- mx28_reg(hw_apbh_ch_curcmdar)
- mx28_reg(hw_apbh_ch_nxtcmdar)
- mx28_reg(hw_apbh_ch_cmd)
- mx28_reg(hw_apbh_ch_bar)
- mx28_reg(hw_apbh_ch_sema)
- mx28_reg(hw_apbh_ch_debug1)
- mx28_reg(hw_apbh_ch_debug2)
+ mx28_reg_32(hw_apbh_ch_curcmdar)
+ mx28_reg_32(hw_apbh_ch_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch_cmd)
+ mx28_reg_32(hw_apbh_ch_bar)
+ mx28_reg_32(hw_apbh_ch_sema)
+ mx28_reg_32(hw_apbh_ch_debug1)
+ mx28_reg_32(hw_apbh_ch_debug2)
} ch[16];
struct {
- mx28_reg(hw_apbh_ch0_curcmdar)
- mx28_reg(hw_apbh_ch0_nxtcmdar)
- mx28_reg(hw_apbh_ch0_cmd)
- mx28_reg(hw_apbh_ch0_bar)
- mx28_reg(hw_apbh_ch0_sema)
- mx28_reg(hw_apbh_ch0_debug1)
- mx28_reg(hw_apbh_ch0_debug2)
- mx28_reg(hw_apbh_ch1_curcmdar)
- mx28_reg(hw_apbh_ch1_nxtcmdar)
- mx28_reg(hw_apbh_ch1_cmd)
- mx28_reg(hw_apbh_ch1_bar)
- mx28_reg(hw_apbh_ch1_sema)
- mx28_reg(hw_apbh_ch1_debug1)
- mx28_reg(hw_apbh_ch1_debug2)
- mx28_reg(hw_apbh_ch2_curcmdar)
- mx28_reg(hw_apbh_ch2_nxtcmdar)
- mx28_reg(hw_apbh_ch2_cmd)
- mx28_reg(hw_apbh_ch2_bar)
- mx28_reg(hw_apbh_ch2_sema)
- mx28_reg(hw_apbh_ch2_debug1)
- mx28_reg(hw_apbh_ch2_debug2)
- mx28_reg(hw_apbh_ch3_curcmdar)
- mx28_reg(hw_apbh_ch3_nxtcmdar)
- mx28_reg(hw_apbh_ch3_cmd)
- mx28_reg(hw_apbh_ch3_bar)
- mx28_reg(hw_apbh_ch3_sema)
- mx28_reg(hw_apbh_ch3_debug1)
- mx28_reg(hw_apbh_ch3_debug2)
- mx28_reg(hw_apbh_ch4_curcmdar)
- mx28_reg(hw_apbh_ch4_nxtcmdar)
- mx28_reg(hw_apbh_ch4_cmd)
- mx28_reg(hw_apbh_ch4_bar)
- mx28_reg(hw_apbh_ch4_sema)
- mx28_reg(hw_apbh_ch4_debug1)
- mx28_reg(hw_apbh_ch4_debug2)
- mx28_reg(hw_apbh_ch5_curcmdar)
- mx28_reg(hw_apbh_ch5_nxtcmdar)
- mx28_reg(hw_apbh_ch5_cmd)
- mx28_reg(hw_apbh_ch5_bar)
- mx28_reg(hw_apbh_ch5_sema)
- mx28_reg(hw_apbh_ch5_debug1)
- mx28_reg(hw_apbh_ch5_debug2)
- mx28_reg(hw_apbh_ch6_curcmdar)
- mx28_reg(hw_apbh_ch6_nxtcmdar)
- mx28_reg(hw_apbh_ch6_cmd)
- mx28_reg(hw_apbh_ch6_bar)
- mx28_reg(hw_apbh_ch6_sema)
- mx28_reg(hw_apbh_ch6_debug1)
- mx28_reg(hw_apbh_ch6_debug2)
- mx28_reg(hw_apbh_ch7_curcmdar)
- mx28_reg(hw_apbh_ch7_nxtcmdar)
- mx28_reg(hw_apbh_ch7_cmd)
- mx28_reg(hw_apbh_ch7_bar)
- mx28_reg(hw_apbh_ch7_sema)
- mx28_reg(hw_apbh_ch7_debug1)
- mx28_reg(hw_apbh_ch7_debug2)
- mx28_reg(hw_apbh_ch8_curcmdar)
- mx28_reg(hw_apbh_ch8_nxtcmdar)
- mx28_reg(hw_apbh_ch8_cmd)
- mx28_reg(hw_apbh_ch8_bar)
- mx28_reg(hw_apbh_ch8_sema)
- mx28_reg(hw_apbh_ch8_debug1)
- mx28_reg(hw_apbh_ch8_debug2)
- mx28_reg(hw_apbh_ch9_curcmdar)
- mx28_reg(hw_apbh_ch9_nxtcmdar)
- mx28_reg(hw_apbh_ch9_cmd)
- mx28_reg(hw_apbh_ch9_bar)
- mx28_reg(hw_apbh_ch9_sema)
- mx28_reg(hw_apbh_ch9_debug1)
- mx28_reg(hw_apbh_ch9_debug2)
- mx28_reg(hw_apbh_ch10_curcmdar)
- mx28_reg(hw_apbh_ch10_nxtcmdar)
- mx28_reg(hw_apbh_ch10_cmd)
- mx28_reg(hw_apbh_ch10_bar)
- mx28_reg(hw_apbh_ch10_sema)
- mx28_reg(hw_apbh_ch10_debug1)
- mx28_reg(hw_apbh_ch10_debug2)
- mx28_reg(hw_apbh_ch11_curcmdar)
- mx28_reg(hw_apbh_ch11_nxtcmdar)
- mx28_reg(hw_apbh_ch11_cmd)
- mx28_reg(hw_apbh_ch11_bar)
- mx28_reg(hw_apbh_ch11_sema)
- mx28_reg(hw_apbh_ch11_debug1)
- mx28_reg(hw_apbh_ch11_debug2)
- mx28_reg(hw_apbh_ch12_curcmdar)
- mx28_reg(hw_apbh_ch12_nxtcmdar)
- mx28_reg(hw_apbh_ch12_cmd)
- mx28_reg(hw_apbh_ch12_bar)
- mx28_reg(hw_apbh_ch12_sema)
- mx28_reg(hw_apbh_ch12_debug1)
- mx28_reg(hw_apbh_ch12_debug2)
- mx28_reg(hw_apbh_ch13_curcmdar)
- mx28_reg(hw_apbh_ch13_nxtcmdar)
- mx28_reg(hw_apbh_ch13_cmd)
- mx28_reg(hw_apbh_ch13_bar)
- mx28_reg(hw_apbh_ch13_sema)
- mx28_reg(hw_apbh_ch13_debug1)
- mx28_reg(hw_apbh_ch13_debug2)
- mx28_reg(hw_apbh_ch14_curcmdar)
- mx28_reg(hw_apbh_ch14_nxtcmdar)
- mx28_reg(hw_apbh_ch14_cmd)
- mx28_reg(hw_apbh_ch14_bar)
- mx28_reg(hw_apbh_ch14_sema)
- mx28_reg(hw_apbh_ch14_debug1)
- mx28_reg(hw_apbh_ch14_debug2)
- mx28_reg(hw_apbh_ch15_curcmdar)
- mx28_reg(hw_apbh_ch15_nxtcmdar)
- mx28_reg(hw_apbh_ch15_cmd)
- mx28_reg(hw_apbh_ch15_bar)
- mx28_reg(hw_apbh_ch15_sema)
- mx28_reg(hw_apbh_ch15_debug1)
- mx28_reg(hw_apbh_ch15_debug2)
+ mx28_reg_32(hw_apbh_ch0_curcmdar)
+ mx28_reg_32(hw_apbh_ch0_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch0_cmd)
+ mx28_reg_32(hw_apbh_ch0_bar)
+ mx28_reg_32(hw_apbh_ch0_sema)
+ mx28_reg_32(hw_apbh_ch0_debug1)
+ mx28_reg_32(hw_apbh_ch0_debug2)
+ mx28_reg_32(hw_apbh_ch1_curcmdar)
+ mx28_reg_32(hw_apbh_ch1_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch1_cmd)
+ mx28_reg_32(hw_apbh_ch1_bar)
+ mx28_reg_32(hw_apbh_ch1_sema)
+ mx28_reg_32(hw_apbh_ch1_debug1)
+ mx28_reg_32(hw_apbh_ch1_debug2)
+ mx28_reg_32(hw_apbh_ch2_curcmdar)
+ mx28_reg_32(hw_apbh_ch2_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch2_cmd)
+ mx28_reg_32(hw_apbh_ch2_bar)
+ mx28_reg_32(hw_apbh_ch2_sema)
+ mx28_reg_32(hw_apbh_ch2_debug1)
+ mx28_reg_32(hw_apbh_ch2_debug2)
+ mx28_reg_32(hw_apbh_ch3_curcmdar)
+ mx28_reg_32(hw_apbh_ch3_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch3_cmd)
+ mx28_reg_32(hw_apbh_ch3_bar)
+ mx28_reg_32(hw_apbh_ch3_sema)
+ mx28_reg_32(hw_apbh_ch3_debug1)
+ mx28_reg_32(hw_apbh_ch3_debug2)
+ mx28_reg_32(hw_apbh_ch4_curcmdar)
+ mx28_reg_32(hw_apbh_ch4_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch4_cmd)
+ mx28_reg_32(hw_apbh_ch4_bar)
+ mx28_reg_32(hw_apbh_ch4_sema)
+ mx28_reg_32(hw_apbh_ch4_debug1)
+ mx28_reg_32(hw_apbh_ch4_debug2)
+ mx28_reg_32(hw_apbh_ch5_curcmdar)
+ mx28_reg_32(hw_apbh_ch5_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch5_cmd)
+ mx28_reg_32(hw_apbh_ch5_bar)
+ mx28_reg_32(hw_apbh_ch5_sema)
+ mx28_reg_32(hw_apbh_ch5_debug1)
+ mx28_reg_32(hw_apbh_ch5_debug2)
+ mx28_reg_32(hw_apbh_ch6_curcmdar)
+ mx28_reg_32(hw_apbh_ch6_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch6_cmd)
+ mx28_reg_32(hw_apbh_ch6_bar)
+ mx28_reg_32(hw_apbh_ch6_sema)
+ mx28_reg_32(hw_apbh_ch6_debug1)
+ mx28_reg_32(hw_apbh_ch6_debug2)
+ mx28_reg_32(hw_apbh_ch7_curcmdar)
+ mx28_reg_32(hw_apbh_ch7_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch7_cmd)
+ mx28_reg_32(hw_apbh_ch7_bar)
+ mx28_reg_32(hw_apbh_ch7_sema)
+ mx28_reg_32(hw_apbh_ch7_debug1)
+ mx28_reg_32(hw_apbh_ch7_debug2)
+ mx28_reg_32(hw_apbh_ch8_curcmdar)
+ mx28_reg_32(hw_apbh_ch8_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch8_cmd)
+ mx28_reg_32(hw_apbh_ch8_bar)
+ mx28_reg_32(hw_apbh_ch8_sema)
+ mx28_reg_32(hw_apbh_ch8_debug1)
+ mx28_reg_32(hw_apbh_ch8_debug2)
+ mx28_reg_32(hw_apbh_ch9_curcmdar)
+ mx28_reg_32(hw_apbh_ch9_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch9_cmd)
+ mx28_reg_32(hw_apbh_ch9_bar)
+ mx28_reg_32(hw_apbh_ch9_sema)
+ mx28_reg_32(hw_apbh_ch9_debug1)
+ mx28_reg_32(hw_apbh_ch9_debug2)
+ mx28_reg_32(hw_apbh_ch10_curcmdar)
+ mx28_reg_32(hw_apbh_ch10_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch10_cmd)
+ mx28_reg_32(hw_apbh_ch10_bar)
+ mx28_reg_32(hw_apbh_ch10_sema)
+ mx28_reg_32(hw_apbh_ch10_debug1)
+ mx28_reg_32(hw_apbh_ch10_debug2)
+ mx28_reg_32(hw_apbh_ch11_curcmdar)
+ mx28_reg_32(hw_apbh_ch11_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch11_cmd)
+ mx28_reg_32(hw_apbh_ch11_bar)
+ mx28_reg_32(hw_apbh_ch11_sema)
+ mx28_reg_32(hw_apbh_ch11_debug1)
+ mx28_reg_32(hw_apbh_ch11_debug2)
+ mx28_reg_32(hw_apbh_ch12_curcmdar)
+ mx28_reg_32(hw_apbh_ch12_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch12_cmd)
+ mx28_reg_32(hw_apbh_ch12_bar)
+ mx28_reg_32(hw_apbh_ch12_sema)
+ mx28_reg_32(hw_apbh_ch12_debug1)
+ mx28_reg_32(hw_apbh_ch12_debug2)
+ mx28_reg_32(hw_apbh_ch13_curcmdar)
+ mx28_reg_32(hw_apbh_ch13_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch13_cmd)
+ mx28_reg_32(hw_apbh_ch13_bar)
+ mx28_reg_32(hw_apbh_ch13_sema)
+ mx28_reg_32(hw_apbh_ch13_debug1)
+ mx28_reg_32(hw_apbh_ch13_debug2)
+ mx28_reg_32(hw_apbh_ch14_curcmdar)
+ mx28_reg_32(hw_apbh_ch14_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch14_cmd)
+ mx28_reg_32(hw_apbh_ch14_bar)
+ mx28_reg_32(hw_apbh_ch14_sema)
+ mx28_reg_32(hw_apbh_ch14_debug1)
+ mx28_reg_32(hw_apbh_ch14_debug2)
+ mx28_reg_32(hw_apbh_ch15_curcmdar)
+ mx28_reg_32(hw_apbh_ch15_nxtcmdar)
+ mx28_reg_32(hw_apbh_ch15_cmd)
+ mx28_reg_32(hw_apbh_ch15_bar)
+ mx28_reg_32(hw_apbh_ch15_sema)
+ mx28_reg_32(hw_apbh_ch15_debug1)
+ mx28_reg_32(hw_apbh_ch15_debug2)
};
};
- mx28_reg(hw_apbh_version)
+ mx28_reg_32(hw_apbh_version)
};
#endif
#ifndef __ASSEMBLY__
struct mx28_bch_regs {
- mx28_reg(hw_bch_ctrl)
- mx28_reg(hw_bch_status0)
- mx28_reg(hw_bch_mode)
- mx28_reg(hw_bch_encodeptr)
- mx28_reg(hw_bch_dataptr)
- mx28_reg(hw_bch_metaptr)
+ mx28_reg_32(hw_bch_ctrl)
+ mx28_reg_32(hw_bch_status0)
+ mx28_reg_32(hw_bch_mode)
+ mx28_reg_32(hw_bch_encodeptr)
+ mx28_reg_32(hw_bch_dataptr)
+ mx28_reg_32(hw_bch_metaptr)
uint32_t reserved[4];
- mx28_reg(hw_bch_layoutselect)
- mx28_reg(hw_bch_flash0layout0)
- mx28_reg(hw_bch_flash0layout1)
- mx28_reg(hw_bch_flash1layout0)
- mx28_reg(hw_bch_flash1layout1)
- mx28_reg(hw_bch_flash2layout0)
- mx28_reg(hw_bch_flash2layout1)
- mx28_reg(hw_bch_flash3layout0)
- mx28_reg(hw_bch_flash3layout1)
- mx28_reg(hw_bch_dbgkesread)
- mx28_reg(hw_bch_dbgcsferead)
- mx28_reg(hw_bch_dbgsyndegread)
- mx28_reg(hw_bch_dbgahbmread)
- mx28_reg(hw_bch_blockname)
- mx28_reg(hw_bch_version)
+ mx28_reg_32(hw_bch_layoutselect)
+ mx28_reg_32(hw_bch_flash0layout0)
+ mx28_reg_32(hw_bch_flash0layout1)
+ mx28_reg_32(hw_bch_flash1layout0)
+ mx28_reg_32(hw_bch_flash1layout1)
+ mx28_reg_32(hw_bch_flash2layout0)
+ mx28_reg_32(hw_bch_flash2layout1)
+ mx28_reg_32(hw_bch_flash3layout0)
+ mx28_reg_32(hw_bch_flash3layout1)
+ mx28_reg_32(hw_bch_dbgkesread)
+ mx28_reg_32(hw_bch_dbgcsferead)
+ mx28_reg_32(hw_bch_dbgsyndegread)
+ mx28_reg_32(hw_bch_dbgahbmread)
+ mx28_reg_32(hw_bch_blockname)
+ mx28_reg_32(hw_bch_version)
};
#endif
#ifndef __ASSEMBLY__
struct mx28_clkctrl_regs {
- mx28_reg(hw_clkctrl_pll0ctrl0) /* 0x00 */
- mx28_reg(hw_clkctrl_pll0ctrl1) /* 0x10 */
- mx28_reg(hw_clkctrl_pll1ctrl0) /* 0x20 */
- mx28_reg(hw_clkctrl_pll1ctrl1) /* 0x30 */
- mx28_reg(hw_clkctrl_pll2ctrl0) /* 0x40 */
- mx28_reg(hw_clkctrl_cpu) /* 0x50 */
- mx28_reg(hw_clkctrl_hbus) /* 0x60 */
- mx28_reg(hw_clkctrl_xbus) /* 0x70 */
- mx28_reg(hw_clkctrl_xtal) /* 0x80 */
- mx28_reg(hw_clkctrl_ssp0) /* 0x90 */
- mx28_reg(hw_clkctrl_ssp1) /* 0xa0 */
- mx28_reg(hw_clkctrl_ssp2) /* 0xb0 */
- mx28_reg(hw_clkctrl_ssp3) /* 0xc0 */
- mx28_reg(hw_clkctrl_gpmi) /* 0xd0 */
- mx28_reg(hw_clkctrl_spdif) /* 0xe0 */
- mx28_reg(hw_clkctrl_emi) /* 0xf0 */
- mx28_reg(hw_clkctrl_saif0) /* 0x100 */
- mx28_reg(hw_clkctrl_saif1) /* 0x110 */
- mx28_reg(hw_clkctrl_lcdif) /* 0x120 */
- mx28_reg(hw_clkctrl_etm) /* 0x130 */
- mx28_reg(hw_clkctrl_enet) /* 0x140 */
- mx28_reg(hw_clkctrl_hsadc) /* 0x150 */
- mx28_reg(hw_clkctrl_flexcan) /* 0x160 */
+ mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
+ mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
+ mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
+ mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
+ mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
+ mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */
+ mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */
+ mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */
+ mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */
+ mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */
+ mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
+ mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
+ mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
+ mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
+ mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */
+ mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */
+ mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */
+ mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */
+ mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */
+ mx28_reg_32(hw_clkctrl_etm) /* 0x130 */
+ mx28_reg_32(hw_clkctrl_enet) /* 0x140 */
+ mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */
+ mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */
uint32_t reserved[16];
- mx28_reg(hw_clkctrl_frac0) /* 0x1b0 */
- mx28_reg(hw_clkctrl_frac1) /* 0x1c0 */
- mx28_reg(hw_clkctrl_clkseq) /* 0x1d0 */
- mx28_reg(hw_clkctrl_reset) /* 0x1e0 */
- mx28_reg(hw_clkctrl_status) /* 0x1f0 */
- mx28_reg(hw_clkctrl_version) /* 0x200 */
+ mx28_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
+ mx28_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
+ mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
+ mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */
+ mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */
+ mx28_reg_32(hw_clkctrl_version) /* 0x200 */
};
#endif
#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28)
#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27)
-#define CLKCTRL_FRAC0_CLKGATEIO0 (1 << 31)
-#define CLKCTRL_FRAC0_IO0_STABLE (1 << 30)
-#define CLKCTRL_FRAC0_IO0FRAC_MASK (0x3f << 24)
-#define CLKCTRL_FRAC0_IO0FRAC_OFFSET 24
-#define CLKCTRL_FRAC0_CLKGATEIO1 (1 << 23)
-#define CLKCTRL_FRAC0_IO1_STABLE (1 << 22)
-#define CLKCTRL_FRAC0_IO1FRAC_MASK (0x3f << 16)
-#define CLKCTRL_FRAC0_IO1FRAC_OFFSET 16
-#define CLKCTRL_FRAC0_CLKGATEEMI (1 << 15)
-#define CLKCTRL_FRAC0_EMI_STABLE (1 << 14)
-#define CLKCTRL_FRAC0_EMIFRAC_MASK (0x3f << 8)
-#define CLKCTRL_FRAC0_EMIFRAC_OFFSET 8
-#define CLKCTRL_FRAC0_CLKGATECPU (1 << 7)
-#define CLKCTRL_FRAC0_CPU_STABLE (1 << 6)
-#define CLKCTRL_FRAC0_CPUFRAC_MASK 0x3f
-#define CLKCTRL_FRAC0_CPUFRAC_OFFSET 0
-
-#define CLKCTRL_FRAC1_CLKGATEGPMI (1 << 23)
-#define CLKCTRL_FRAC1_GPMI_STABLE (1 << 22)
-#define CLKCTRL_FRAC1_GPMIFRAC_MASK (0x3f << 16)
-#define CLKCTRL_FRAC1_GPMIFRAC_OFFSET 16
-#define CLKCTRL_FRAC1_CLKGATEHSADC (1 << 15)
-#define CLKCTRL_FRAC1_HSADC_STABLE (1 << 14)
-#define CLKCTRL_FRAC1_HSADCFRAC_MASK (0x3f << 8)
-#define CLKCTRL_FRAC1_HSADCFRAC_OFFSET 8
-#define CLKCTRL_FRAC1_CLKGATEPIX (1 << 7)
-#define CLKCTRL_FRAC1_PIX_STABLE (1 << 6)
-#define CLKCTRL_FRAC1_PIXFRAC_MASK 0x3f
-#define CLKCTRL_FRAC1_PIXFRAC_OFFSET 0
+#define CLKCTRL_FRAC_CLKGATE (1 << 7)
+#define CLKCTRL_FRAC_STABLE (1 << 6)
+#define CLKCTRL_FRAC_FRAC_MASK 0x3f
+#define CLKCTRL_FRAC_FRAC_OFFSET 0
+#define CLKCTRL_FRAC0_CPU 0
+#define CLKCTRL_FRAC0_EMI 1
+#define CLKCTRL_FRAC0_IO1 2
+#define CLKCTRL_FRAC0_IO0 3
+#define CLKCTRL_FRAC1_PIX 0
+#define CLKCTRL_FRAC1_HSADC 1
+#define CLKCTRL_FRAC1_GPMI 2
#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18)
#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14)
*
*/
-#define __mx28_reg(name) \
+#define __mx28_reg_8(name) \
+ uint8_t name[4]; \
+ uint8_t name##_set[4]; \
+ uint8_t name##_clr[4]; \
+ uint8_t name##_tog[4]; \
+
+#define __mx28_reg_32(name) \
uint32_t name; \
uint32_t name##_set; \
uint32_t name##_clr; \
uint32_t name##_tog;
-struct mx28_register {
- __mx28_reg(reg)
+struct mx28_register_8 {
+ __mx28_reg_8(reg)
+};
+
+struct mx28_register_32 {
+ __mx28_reg_32(reg)
};
-#define mx28_reg(name) \
+#define mx28_reg_8(name) \
+ union { \
+ struct { __mx28_reg_8(name) }; \
+ struct mx28_register_32 name##_reg; \
+ };
+
+#define mx28_reg_32(name) \
union { \
- struct { __mx28_reg(name) }; \
- struct mx28_register name##_reg; \
+ struct { __mx28_reg_32(name) }; \
+ struct mx28_register_32 name##_reg; \
};
#endif /* __MX28_REGS_COMMON_H__ */
--- /dev/null
+/*
+ * Freescale i.MX28 DIGCTL Register Definitions
+ *
+ * Copyright (C) 2012 Robert Delien <robert@delien.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_DIGCTL_H__
+#define __MX28_REGS_DIGCTL_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_digctl_regs {
+ mx28_reg_32(hw_digctl_ctrl) /* 0x000 */
+ mx28_reg_32(hw_digctl_status) /* 0x010 */
+ mx28_reg_32(hw_digctl_hclkcount) /* 0x020 */
+ mx28_reg_32(hw_digctl_ramctrl) /* 0x030 */
+ mx28_reg_32(hw_digctl_emi_status) /* 0x040 */
+ mx28_reg_32(hw_digctl_read_margin) /* 0x050 */
+ uint32_t hw_digctl_writeonce; /* 0x060 */
+ uint32_t reserved_writeonce[3];
+ mx28_reg_32(hw_digctl_bist_ctl) /* 0x070 */
+ mx28_reg_32(hw_digctl_bist_status) /* 0x080 */
+ uint32_t hw_digctl_entropy; /* 0x090 */
+ uint32_t reserved_entropy[3];
+ uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
+ uint32_t reserved_entropy_latched[3];
+
+ uint32_t reserved1[4];
+
+ mx28_reg_32(hw_digctl_microseconds) /* 0x0c0 */
+ uint32_t hw_digctl_dbgrd; /* 0x0d0 */
+ uint32_t reserved_hw_digctl_dbgrd[3];
+ uint32_t hw_digctl_dbg; /* 0x0e0 */
+ uint32_t reserved_hw_digctl_dbg[3];
+
+ uint32_t reserved2[4];
+
+ mx28_reg_32(hw_digctl_usb_loopback) /* 0x100 */
+ mx28_reg_32(hw_digctl_ocram_status0) /* 0x110 */
+ mx28_reg_32(hw_digctl_ocram_status1) /* 0x120 */
+ mx28_reg_32(hw_digctl_ocram_status2) /* 0x130 */
+ mx28_reg_32(hw_digctl_ocram_status3) /* 0x140 */
+ mx28_reg_32(hw_digctl_ocram_status4) /* 0x150 */
+ mx28_reg_32(hw_digctl_ocram_status5) /* 0x160 */
+ mx28_reg_32(hw_digctl_ocram_status6) /* 0x170 */
+ mx28_reg_32(hw_digctl_ocram_status7) /* 0x180 */
+ mx28_reg_32(hw_digctl_ocram_status8) /* 0x190 */
+ mx28_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
+ mx28_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
+ mx28_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
+ mx28_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
+ mx28_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
+
+ uint32_t reserved3[36];
+
+ uint32_t hw_digctl_scratch0; /* 0x280 */
+ uint32_t reserved_hw_digctl_scratch0[3];
+ uint32_t hw_digctl_scratch1; /* 0x290 */
+ uint32_t reserved_hw_digctl_scratch1[3];
+ uint32_t hw_digctl_armcache; /* 0x2a0 */
+ uint32_t reserved_hw_digctl_armcache[3];
+ mx28_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
+ uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */
+ uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3];
+ uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */
+ uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3];
+ uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */
+ uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3];
+ uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */
+ uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3];
+ uint32_t hw_digctl_fsl; /* 0x300 */
+ uint32_t reserved_hw_digctl_fsl[3];
+ uint32_t hw_digctl_chipid; /* 0x310 */
+ uint32_t reserved_hw_digctl_chipid[3];
+
+ uint32_t reserved4[4];
+
+ uint32_t hw_digctl_ahb_stats_select; /* 0x330 */
+ uint32_t reserved_hw_digctl_ahb_stats_select[3];
+
+ uint32_t reserved5[12];
+
+ uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */
+ uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3];
+ uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */
+ uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3];
+ uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */
+ uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3];
+ uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */
+ uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3];
+ uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */
+ uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3];
+ uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */
+ uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3];
+ uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */
+ uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3];
+ uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */
+ uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3];
+ uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */
+ uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3];
+
+ uint32_t reserved6[64];
+
+ uint32_t hw_digctl_mpte0_loc; /* 0x500 */
+ uint32_t reserved_hw_digctl_mpte0_loc[3];
+ uint32_t hw_digctl_mpte1_loc; /* 0x510 */
+ uint32_t reserved_hw_digctl_mpte1_loc[3];
+ uint32_t hw_digctl_mpte2_loc; /* 0x520 */
+ uint32_t reserved_hw_digctl_mpte2_loc[3];
+ uint32_t hw_digctl_mpte3_loc; /* 0x530 */
+ uint32_t reserved_hw_digctl_mpte3_loc[3];
+ uint32_t hw_digctl_mpte4_loc; /* 0x540 */
+ uint32_t reserved_hw_digctl_mpte4_loc[3];
+ uint32_t hw_digctl_mpte5_loc; /* 0x550 */
+ uint32_t reserved_hw_digctl_mpte5_loc[3];
+ uint32_t hw_digctl_mpte6_loc; /* 0x560 */
+ uint32_t reserved_hw_digctl_mpte6_loc[3];
+ uint32_t hw_digctl_mpte7_loc; /* 0x570 */
+ uint32_t reserved_hw_digctl_mpte7_loc[3];
+ uint32_t hw_digctl_mpte8_loc; /* 0x580 */
+ uint32_t reserved_hw_digctl_mpte8_loc[3];
+ uint32_t hw_digctl_mpte9_loc; /* 0x590 */
+ uint32_t reserved_hw_digctl_mpte9_loc[3];
+ uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */
+ uint32_t reserved_hw_digctl_mpte10_loc[3];
+ uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */
+ uint32_t reserved_hw_digctl_mpte11_loc[3];
+ uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */
+ uint32_t reserved_hw_digctl_mpte12_loc[3];
+ uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */
+ uint32_t reserved_hw_digctl_mpte13_loc[3];
+ uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */
+ uint32_t reserved_hw_digctl_mpte14_loc[3];
+ uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */
+ uint32_t reserved_hw_digctl_mpte15_loc[3];
+};
+#endif
+
+#endif /* __MX28_REGS_DIGCTL_H__ */
#ifndef __ASSEMBLY__
struct mx28_gpmi_regs {
- mx28_reg(hw_gpmi_ctrl0)
- mx28_reg(hw_gpmi_compare)
- mx28_reg(hw_gpmi_eccctrl)
- mx28_reg(hw_gpmi_ecccount)
- mx28_reg(hw_gpmi_payload)
- mx28_reg(hw_gpmi_auxiliary)
- mx28_reg(hw_gpmi_ctrl1)
- mx28_reg(hw_gpmi_timing0)
- mx28_reg(hw_gpmi_timing1)
+ mx28_reg_32(hw_gpmi_ctrl0)
+ mx28_reg_32(hw_gpmi_compare)
+ mx28_reg_32(hw_gpmi_eccctrl)
+ mx28_reg_32(hw_gpmi_ecccount)
+ mx28_reg_32(hw_gpmi_payload)
+ mx28_reg_32(hw_gpmi_auxiliary)
+ mx28_reg_32(hw_gpmi_ctrl1)
+ mx28_reg_32(hw_gpmi_timing0)
+ mx28_reg_32(hw_gpmi_timing1)
uint32_t reserved[4];
- mx28_reg(hw_gpmi_data)
- mx28_reg(hw_gpmi_stat)
- mx28_reg(hw_gpmi_debug)
- mx28_reg(hw_gpmi_version)
+ mx28_reg_32(hw_gpmi_data)
+ mx28_reg_32(hw_gpmi_stat)
+ mx28_reg_32(hw_gpmi_debug)
+ mx28_reg_32(hw_gpmi_version)
};
#endif
#ifndef __ASSEMBLY__
struct mx28_i2c_regs {
- mx28_reg(hw_i2c_ctrl0)
- mx28_reg(hw_i2c_timing0)
- mx28_reg(hw_i2c_timing1)
- mx28_reg(hw_i2c_timing2)
- mx28_reg(hw_i2c_ctrl1)
- mx28_reg(hw_i2c_stat)
- mx28_reg(hw_i2c_queuectrl)
- mx28_reg(hw_i2c_queuestat)
- mx28_reg(hw_i2c_queuecmd)
- mx28_reg(hw_i2c_queuedata)
- mx28_reg(hw_i2c_data)
- mx28_reg(hw_i2c_debug0)
- mx28_reg(hw_i2c_debug1)
- mx28_reg(hw_i2c_version)
+ mx28_reg_32(hw_i2c_ctrl0)
+ mx28_reg_32(hw_i2c_timing0)
+ mx28_reg_32(hw_i2c_timing1)
+ mx28_reg_32(hw_i2c_timing2)
+ mx28_reg_32(hw_i2c_ctrl1)
+ mx28_reg_32(hw_i2c_stat)
+ mx28_reg_32(hw_i2c_queuectrl)
+ mx28_reg_32(hw_i2c_queuestat)
+ mx28_reg_32(hw_i2c_queuecmd)
+ mx28_reg_32(hw_i2c_queuedata)
+ mx28_reg_32(hw_i2c_data)
+ mx28_reg_32(hw_i2c_debug0)
+ mx28_reg_32(hw_i2c_debug1)
+ mx28_reg_32(hw_i2c_version)
};
#endif
#ifndef __ASSEMBLY__
struct mx28_ocotp_regs {
- mx28_reg(hw_ocotp_ctrl) /* 0x0 */
- mx28_reg(hw_ocotp_data) /* 0x10 */
- mx28_reg(hw_ocotp_cust0) /* 0x20 */
- mx28_reg(hw_ocotp_cust1) /* 0x30 */
- mx28_reg(hw_ocotp_cust2) /* 0x40 */
- mx28_reg(hw_ocotp_cust3) /* 0x50 */
- mx28_reg(hw_ocotp_crypto0) /* 0x60 */
- mx28_reg(hw_ocotp_crypto1) /* 0x70 */
- mx28_reg(hw_ocotp_crypto2) /* 0x80 */
- mx28_reg(hw_ocotp_crypto3) /* 0x90 */
- mx28_reg(hw_ocotp_hwcap0) /* 0xa0 */
- mx28_reg(hw_ocotp_hwcap1) /* 0xb0 */
- mx28_reg(hw_ocotp_hwcap2) /* 0xc0 */
- mx28_reg(hw_ocotp_hwcap3) /* 0xd0 */
- mx28_reg(hw_ocotp_hwcap4) /* 0xe0 */
- mx28_reg(hw_ocotp_hwcap5) /* 0xf0 */
- mx28_reg(hw_ocotp_swcap) /* 0x100 */
- mx28_reg(hw_ocotp_custcap) /* 0x110 */
- mx28_reg(hw_ocotp_lock) /* 0x120 */
- mx28_reg(hw_ocotp_ops0) /* 0x130 */
- mx28_reg(hw_ocotp_ops1) /* 0x140 */
- mx28_reg(hw_ocotp_ops2) /* 0x150 */
- mx28_reg(hw_ocotp_ops3) /* 0x160 */
- mx28_reg(hw_ocotp_un0) /* 0x170 */
- mx28_reg(hw_ocotp_un1) /* 0x180 */
- mx28_reg(hw_ocotp_un2) /* 0x190 */
- mx28_reg(hw_ocotp_rom0) /* 0x1a0 */
- mx28_reg(hw_ocotp_rom1) /* 0x1b0 */
- mx28_reg(hw_ocotp_rom2) /* 0x1c0 */
- mx28_reg(hw_ocotp_rom3) /* 0x1d0 */
- mx28_reg(hw_ocotp_rom4) /* 0x1e0 */
- mx28_reg(hw_ocotp_rom5) /* 0x1f0 */
- mx28_reg(hw_ocotp_rom6) /* 0x200 */
- mx28_reg(hw_ocotp_rom7) /* 0x210 */
- mx28_reg(hw_ocotp_srk0) /* 0x220 */
- mx28_reg(hw_ocotp_srk1) /* 0x230 */
- mx28_reg(hw_ocotp_srk2) /* 0x240 */
- mx28_reg(hw_ocotp_srk3) /* 0x250 */
- mx28_reg(hw_ocotp_srk4) /* 0x260 */
- mx28_reg(hw_ocotp_srk5) /* 0x270 */
- mx28_reg(hw_ocotp_srk6) /* 0x280 */
- mx28_reg(hw_ocotp_srk7) /* 0x290 */
- mx28_reg(hw_ocotp_version) /* 0x2a0 */
+ mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */
+ mx28_reg_32(hw_ocotp_data) /* 0x10 */
+ mx28_reg_32(hw_ocotp_cust0) /* 0x20 */
+ mx28_reg_32(hw_ocotp_cust1) /* 0x30 */
+ mx28_reg_32(hw_ocotp_cust2) /* 0x40 */
+ mx28_reg_32(hw_ocotp_cust3) /* 0x50 */
+ mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */
+ mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */
+ mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */
+ mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */
+ mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
+ mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
+ mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
+ mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
+ mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
+ mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
+ mx28_reg_32(hw_ocotp_swcap) /* 0x100 */
+ mx28_reg_32(hw_ocotp_custcap) /* 0x110 */
+ mx28_reg_32(hw_ocotp_lock) /* 0x120 */
+ mx28_reg_32(hw_ocotp_ops0) /* 0x130 */
+ mx28_reg_32(hw_ocotp_ops1) /* 0x140 */
+ mx28_reg_32(hw_ocotp_ops2) /* 0x150 */
+ mx28_reg_32(hw_ocotp_ops3) /* 0x160 */
+ mx28_reg_32(hw_ocotp_un0) /* 0x170 */
+ mx28_reg_32(hw_ocotp_un1) /* 0x180 */
+ mx28_reg_32(hw_ocotp_un2) /* 0x190 */
+ mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */
+ mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */
+ mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */
+ mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */
+ mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */
+ mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */
+ mx28_reg_32(hw_ocotp_rom6) /* 0x200 */
+ mx28_reg_32(hw_ocotp_rom7) /* 0x210 */
+ mx28_reg_32(hw_ocotp_srk0) /* 0x220 */
+ mx28_reg_32(hw_ocotp_srk1) /* 0x230 */
+ mx28_reg_32(hw_ocotp_srk2) /* 0x240 */
+ mx28_reg_32(hw_ocotp_srk3) /* 0x250 */
+ mx28_reg_32(hw_ocotp_srk4) /* 0x260 */
+ mx28_reg_32(hw_ocotp_srk5) /* 0x270 */
+ mx28_reg_32(hw_ocotp_srk6) /* 0x280 */
+ mx28_reg_32(hw_ocotp_srk7) /* 0x290 */
+ mx28_reg_32(hw_ocotp_version) /* 0x2a0 */
};
#endif
#ifndef __ASSEMBLY__
struct mx28_pinctrl_regs {
- mx28_reg(hw_pinctrl_ctrl) /* 0x0 */
+ mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */
uint32_t reserved1[60];
- mx28_reg(hw_pinctrl_muxsel0) /* 0x100 */
- mx28_reg(hw_pinctrl_muxsel1) /* 0x110 */
- mx28_reg(hw_pinctrl_muxsel2) /* 0x120 */
- mx28_reg(hw_pinctrl_muxsel3) /* 0x130 */
- mx28_reg(hw_pinctrl_muxsel4) /* 0x140 */
- mx28_reg(hw_pinctrl_muxsel5) /* 0x150 */
- mx28_reg(hw_pinctrl_muxsel6) /* 0x160 */
- mx28_reg(hw_pinctrl_muxsel7) /* 0x170 */
- mx28_reg(hw_pinctrl_muxsel8) /* 0x180 */
- mx28_reg(hw_pinctrl_muxsel9) /* 0x190 */
- mx28_reg(hw_pinctrl_muxsel10) /* 0x1a0 */
- mx28_reg(hw_pinctrl_muxsel11) /* 0x1b0 */
- mx28_reg(hw_pinctrl_muxsel12) /* 0x1c0 */
- mx28_reg(hw_pinctrl_muxsel13) /* 0x1d0 */
+ mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
+ mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
+ mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
+ mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
+ mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
+ mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
+ mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
+ mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
+ mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
+ mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */
+ mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */
+ mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */
+ mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */
+ mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */
uint32_t reserved2[72];
- mx28_reg(hw_pinctrl_drive0) /* 0x300 */
- mx28_reg(hw_pinctrl_drive1) /* 0x310 */
- mx28_reg(hw_pinctrl_drive2) /* 0x320 */
- mx28_reg(hw_pinctrl_drive3) /* 0x330 */
- mx28_reg(hw_pinctrl_drive4) /* 0x340 */
- mx28_reg(hw_pinctrl_drive5) /* 0x350 */
- mx28_reg(hw_pinctrl_drive6) /* 0x360 */
- mx28_reg(hw_pinctrl_drive7) /* 0x370 */
- mx28_reg(hw_pinctrl_drive8) /* 0x380 */
- mx28_reg(hw_pinctrl_drive9) /* 0x390 */
- mx28_reg(hw_pinctrl_drive10) /* 0x3a0 */
- mx28_reg(hw_pinctrl_drive11) /* 0x3b0 */
- mx28_reg(hw_pinctrl_drive12) /* 0x3c0 */
- mx28_reg(hw_pinctrl_drive13) /* 0x3d0 */
- mx28_reg(hw_pinctrl_drive14) /* 0x3e0 */
- mx28_reg(hw_pinctrl_drive15) /* 0x3f0 */
- mx28_reg(hw_pinctrl_drive16) /* 0x400 */
- mx28_reg(hw_pinctrl_drive17) /* 0x410 */
- mx28_reg(hw_pinctrl_drive18) /* 0x420 */
- mx28_reg(hw_pinctrl_drive19) /* 0x430 */
+ mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */
+ mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */
+ mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */
+ mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */
+ mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */
+ mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */
+ mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */
+ mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */
+ mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */
+ mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */
+ mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */
+ mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */
+ mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */
+ mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */
+ mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */
+ mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */
+ mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */
+ mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */
+ mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */
+ mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */
uint32_t reserved3[112];
- mx28_reg(hw_pinctrl_pull0) /* 0x600 */
- mx28_reg(hw_pinctrl_pull1) /* 0x610 */
- mx28_reg(hw_pinctrl_pull2) /* 0x620 */
- mx28_reg(hw_pinctrl_pull3) /* 0x630 */
- mx28_reg(hw_pinctrl_pull4) /* 0x640 */
- mx28_reg(hw_pinctrl_pull5) /* 0x650 */
- mx28_reg(hw_pinctrl_pull6) /* 0x660 */
+ mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */
+ mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */
+ mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */
+ mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */
+ mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */
+ mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */
+ mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */
uint32_t reserved4[36];
- mx28_reg(hw_pinctrl_dout0) /* 0x700 */
- mx28_reg(hw_pinctrl_dout1) /* 0x710 */
- mx28_reg(hw_pinctrl_dout2) /* 0x720 */
- mx28_reg(hw_pinctrl_dout3) /* 0x730 */
- mx28_reg(hw_pinctrl_dout4) /* 0x740 */
+ mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */
+ mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */
+ mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */
+ mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */
+ mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */
uint32_t reserved5[108];
- mx28_reg(hw_pinctrl_din0) /* 0x900 */
- mx28_reg(hw_pinctrl_din1) /* 0x910 */
- mx28_reg(hw_pinctrl_din2) /* 0x920 */
- mx28_reg(hw_pinctrl_din3) /* 0x930 */
- mx28_reg(hw_pinctrl_din4) /* 0x940 */
+ mx28_reg_32(hw_pinctrl_din0) /* 0x900 */
+ mx28_reg_32(hw_pinctrl_din1) /* 0x910 */
+ mx28_reg_32(hw_pinctrl_din2) /* 0x920 */
+ mx28_reg_32(hw_pinctrl_din3) /* 0x930 */
+ mx28_reg_32(hw_pinctrl_din4) /* 0x940 */
uint32_t reserved6[108];
- mx28_reg(hw_pinctrl_doe0) /* 0xb00 */
- mx28_reg(hw_pinctrl_doe1) /* 0xb10 */
- mx28_reg(hw_pinctrl_doe2) /* 0xb20 */
- mx28_reg(hw_pinctrl_doe3) /* 0xb30 */
- mx28_reg(hw_pinctrl_doe4) /* 0xb40 */
+ mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */
+ mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */
+ mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */
+ mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */
+ mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */
uint32_t reserved7[300];
- mx28_reg(hw_pinctrl_pin2irq0) /* 0x1000 */
- mx28_reg(hw_pinctrl_pin2irq1) /* 0x1010 */
- mx28_reg(hw_pinctrl_pin2irq2) /* 0x1020 */
- mx28_reg(hw_pinctrl_pin2irq3) /* 0x1030 */
- mx28_reg(hw_pinctrl_pin2irq4) /* 0x1040 */
+ mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */
+ mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */
+ mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */
+ mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */
+ mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */
uint32_t reserved8[44];
- mx28_reg(hw_pinctrl_irqen0) /* 0x1100 */
- mx28_reg(hw_pinctrl_irqen1) /* 0x1110 */
- mx28_reg(hw_pinctrl_irqen2) /* 0x1120 */
- mx28_reg(hw_pinctrl_irqen3) /* 0x1130 */
- mx28_reg(hw_pinctrl_irqen4) /* 0x1140 */
+ mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */
+ mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */
+ mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */
+ mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */
+ mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */
uint32_t reserved9[44];
- mx28_reg(hw_pinctrl_irqlevel0) /* 0x1200 */
- mx28_reg(hw_pinctrl_irqlevel1) /* 0x1210 */
- mx28_reg(hw_pinctrl_irqlevel2) /* 0x1220 */
- mx28_reg(hw_pinctrl_irqlevel3) /* 0x1230 */
- mx28_reg(hw_pinctrl_irqlevel4) /* 0x1240 */
+ mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */
+ mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */
+ mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */
+ mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */
+ mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */
uint32_t reserved10[44];
- mx28_reg(hw_pinctrl_irqpol0) /* 0x1300 */
- mx28_reg(hw_pinctrl_irqpol1) /* 0x1310 */
- mx28_reg(hw_pinctrl_irqpol2) /* 0x1320 */
- mx28_reg(hw_pinctrl_irqpol3) /* 0x1330 */
- mx28_reg(hw_pinctrl_irqpol4) /* 0x1340 */
+ mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */
+ mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */
+ mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */
+ mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */
+ mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */
uint32_t reserved11[44];
- mx28_reg(hw_pinctrl_irqstat0) /* 0x1400 */
- mx28_reg(hw_pinctrl_irqstat1) /* 0x1410 */
- mx28_reg(hw_pinctrl_irqstat2) /* 0x1420 */
- mx28_reg(hw_pinctrl_irqstat3) /* 0x1430 */
- mx28_reg(hw_pinctrl_irqstat4) /* 0x1440 */
+ mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */
+ mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */
+ mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */
+ mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */
+ mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */
uint32_t reserved12[380];
- mx28_reg(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
+ mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
uint32_t reserved13[76];
- mx28_reg(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
+ mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
};
#endif
#ifndef __ASSEMBLY__
struct mx28_power_regs {
- mx28_reg(hw_power_ctrl)
- mx28_reg(hw_power_5vctrl)
- mx28_reg(hw_power_minpwr)
- mx28_reg(hw_power_charge)
+ mx28_reg_32(hw_power_ctrl)
+ mx28_reg_32(hw_power_5vctrl)
+ mx28_reg_32(hw_power_minpwr)
+ mx28_reg_32(hw_power_charge)
uint32_t hw_power_vdddctrl;
uint32_t reserved_vddd[3];
uint32_t hw_power_vddactrl;
uint32_t reserved_misc[3];
uint32_t hw_power_dclimits;
uint32_t reserved_dclimits[3];
- mx28_reg(hw_power_loopctrl)
+ mx28_reg_32(hw_power_loopctrl)
uint32_t hw_power_sts;
uint32_t reserved_sts[3];
- mx28_reg(hw_power_speed)
+ mx28_reg_32(hw_power_speed)
uint32_t hw_power_battmonitor;
uint32_t reserved_battmonitor[3];
uint32_t reserved[4];
- mx28_reg(hw_power_reset)
- mx28_reg(hw_power_debug)
- mx28_reg(hw_power_thermal)
- mx28_reg(hw_power_usb1ctrl)
- mx28_reg(hw_power_special)
- mx28_reg(hw_power_version)
- mx28_reg(hw_power_anaclkctrl)
- mx28_reg(hw_power_refctrl)
+ mx28_reg_32(hw_power_reset)
+ mx28_reg_32(hw_power_debug)
+ mx28_reg_32(hw_power_thermal)
+ mx28_reg_32(hw_power_usb1ctrl)
+ mx28_reg_32(hw_power_special)
+ mx28_reg_32(hw_power_version)
+ mx28_reg_32(hw_power_anaclkctrl)
+ mx28_reg_32(hw_power_refctrl)
};
#endif
#ifndef __ASSEMBLY__
struct mx28_rtc_regs {
- mx28_reg(hw_rtc_ctrl)
- mx28_reg(hw_rtc_stat)
- mx28_reg(hw_rtc_milliseconds)
- mx28_reg(hw_rtc_seconds)
- mx28_reg(hw_rtc_rtc_alarm)
- mx28_reg(hw_rtc_watchdog)
- mx28_reg(hw_rtc_persistent0)
- mx28_reg(hw_rtc_persistent1)
- mx28_reg(hw_rtc_persistent2)
- mx28_reg(hw_rtc_persistent3)
- mx28_reg(hw_rtc_persistent4)
- mx28_reg(hw_rtc_persistent5)
- mx28_reg(hw_rtc_debug)
- mx28_reg(hw_rtc_version)
+ mx28_reg_32(hw_rtc_ctrl)
+ mx28_reg_32(hw_rtc_stat)
+ mx28_reg_32(hw_rtc_milliseconds)
+ mx28_reg_32(hw_rtc_seconds)
+ mx28_reg_32(hw_rtc_rtc_alarm)
+ mx28_reg_32(hw_rtc_watchdog)
+ mx28_reg_32(hw_rtc_persistent0)
+ mx28_reg_32(hw_rtc_persistent1)
+ mx28_reg_32(hw_rtc_persistent2)
+ mx28_reg_32(hw_rtc_persistent3)
+ mx28_reg_32(hw_rtc_persistent4)
+ mx28_reg_32(hw_rtc_persistent5)
+ mx28_reg_32(hw_rtc_debug)
+ mx28_reg_32(hw_rtc_version)
};
#endif
#ifndef __ASSEMBLY__
struct mx28_ssp_regs {
- mx28_reg(hw_ssp_ctrl0)
- mx28_reg(hw_ssp_cmd0)
- mx28_reg(hw_ssp_cmd1)
- mx28_reg(hw_ssp_xfer_size)
- mx28_reg(hw_ssp_block_size)
- mx28_reg(hw_ssp_compref)
- mx28_reg(hw_ssp_compmask)
- mx28_reg(hw_ssp_timing)
- mx28_reg(hw_ssp_ctrl1)
- mx28_reg(hw_ssp_data)
- mx28_reg(hw_ssp_sdresp0)
- mx28_reg(hw_ssp_sdresp1)
- mx28_reg(hw_ssp_sdresp2)
- mx28_reg(hw_ssp_sdresp3)
- mx28_reg(hw_ssp_ddr_ctrl)
- mx28_reg(hw_ssp_dll_ctrl)
- mx28_reg(hw_ssp_status)
- mx28_reg(hw_ssp_dll_sts)
- mx28_reg(hw_ssp_debug)
- mx28_reg(hw_ssp_version)
+ mx28_reg_32(hw_ssp_ctrl0)
+ mx28_reg_32(hw_ssp_cmd0)
+ mx28_reg_32(hw_ssp_cmd1)
+ mx28_reg_32(hw_ssp_xfer_size)
+ mx28_reg_32(hw_ssp_block_size)
+ mx28_reg_32(hw_ssp_compref)
+ mx28_reg_32(hw_ssp_compmask)
+ mx28_reg_32(hw_ssp_timing)
+ mx28_reg_32(hw_ssp_ctrl1)
+ mx28_reg_32(hw_ssp_data)
+ mx28_reg_32(hw_ssp_sdresp0)
+ mx28_reg_32(hw_ssp_sdresp1)
+ mx28_reg_32(hw_ssp_sdresp2)
+ mx28_reg_32(hw_ssp_sdresp3)
+ mx28_reg_32(hw_ssp_ddr_ctrl)
+ mx28_reg_32(hw_ssp_dll_ctrl)
+ mx28_reg_32(hw_ssp_status)
+ mx28_reg_32(hw_ssp_dll_sts)
+ mx28_reg_32(hw_ssp_debug)
+ mx28_reg_32(hw_ssp_version)
};
#endif
#ifndef __ASSEMBLY__
struct mx28_timrot_regs {
- mx28_reg(hw_timrot_rotctrl)
- mx28_reg(hw_timrot_rotcount)
- mx28_reg(hw_timrot_timctrl0)
- mx28_reg(hw_timrot_running_count0)
- mx28_reg(hw_timrot_fixed_count0)
- mx28_reg(hw_timrot_match_count0)
- mx28_reg(hw_timrot_timctrl1)
- mx28_reg(hw_timrot_running_count1)
- mx28_reg(hw_timrot_fixed_count1)
- mx28_reg(hw_timrot_match_count1)
- mx28_reg(hw_timrot_timctrl2)
- mx28_reg(hw_timrot_running_count2)
- mx28_reg(hw_timrot_fixed_count2)
- mx28_reg(hw_timrot_match_count2)
- mx28_reg(hw_timrot_timctrl3)
- mx28_reg(hw_timrot_running_count3)
- mx28_reg(hw_timrot_fixed_count3)
- mx28_reg(hw_timrot_match_count3)
- mx28_reg(hw_timrot_version)
+ mx28_reg_32(hw_timrot_rotctrl)
+ mx28_reg_32(hw_timrot_rotcount)
+ mx28_reg_32(hw_timrot_timctrl0)
+ mx28_reg_32(hw_timrot_running_count0)
+ mx28_reg_32(hw_timrot_fixed_count0)
+ mx28_reg_32(hw_timrot_match_count0)
+ mx28_reg_32(hw_timrot_timctrl1)
+ mx28_reg_32(hw_timrot_running_count1)
+ mx28_reg_32(hw_timrot_fixed_count1)
+ mx28_reg_32(hw_timrot_match_count1)
+ mx28_reg_32(hw_timrot_timctrl2)
+ mx28_reg_32(hw_timrot_running_count2)
+ mx28_reg_32(hw_timrot_fixed_count2)
+ mx28_reg_32(hw_timrot_match_count2)
+ mx28_reg_32(hw_timrot_timctrl3)
+ mx28_reg_32(hw_timrot_running_count3)
+ mx28_reg_32(hw_timrot_fixed_count3)
+ mx28_reg_32(hw_timrot_match_count3)
+ mx28_reg_32(hw_timrot_version)
};
#endif
#define __REGS_USBPHY_H__
struct mx28_usbphy_regs {
- mx28_reg(hw_usbphy_pwd)
- mx28_reg(hw_usbphy_tx)
- mx28_reg(hw_usbphy_rx)
- mx28_reg(hw_usbphy_ctrl)
- mx28_reg(hw_usbphy_status)
- mx28_reg(hw_usbphy_debug)
- mx28_reg(hw_usbphy_debug0_status)
- mx28_reg(hw_usbphy_debug1)
- mx28_reg(hw_usbphy_version)
- mx28_reg(hw_usbphy_ip)
+ mx28_reg_32(hw_usbphy_pwd)
+ mx28_reg_32(hw_usbphy_tx)
+ mx28_reg_32(hw_usbphy_rx)
+ mx28_reg_32(hw_usbphy_ctrl)
+ mx28_reg_32(hw_usbphy_status)
+ mx28_reg_32(hw_usbphy_debug)
+ mx28_reg_32(hw_usbphy_debug0_status)
+ mx28_reg_32(hw_usbphy_debug1)
+ mx28_reg_32(hw_usbphy_version)
+ mx28_reg_32(hw_usbphy_ip)
};
#define USBPHY_PWD_RXPWDRX (1 << 20)
#ifndef __MX28_H__
#define __MX28_H__
-int mx28_reset_block(struct mx28_register *reg);
-int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout);
-int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout);
+int mx28_reset_block(struct mx28_register_32 *reg);
+int mx28_wait_mask_set(struct mx28_register_32 *reg,
+ uint32_t mask,
+ int timeout);
+int mx28_wait_mask_clr(struct mx28_register_32 *reg,
+ uint32_t mask,
+ int timeout);
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
+void enable_usboh3_clk(unsigned char enable);
#endif /* __ASM_ARCH_CLOCK_H */
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
-#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
+#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
+#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
+#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
u32 opacr4;
};
+struct anatop_regs {
+ u32 pll_sys; /* 0x000 */
+ u32 pll_sys_set; /* 0x004 */
+ u32 pll_sys_clr; /* 0x008 */
+ u32 pll_sys_tog; /* 0x00c */
+ u32 usb1_pll_480_ctrl; /* 0x010 */
+ u32 usb1_pll_480_ctrl_set; /* 0x014 */
+ u32 usb1_pll_480_ctrl_clr; /* 0x018 */
+ u32 usb1_pll_480_ctrl_tog; /* 0x01c */
+ u32 usb2_pll_480_ctrl; /* 0x020 */
+ u32 usb2_pll_480_ctrl_set; /* 0x024 */
+ u32 usb2_pll_480_ctrl_clr; /* 0x028 */
+ u32 usb2_pll_480_ctrl_tog; /* 0x02c */
+ u32 pll_528; /* 0x030 */
+ u32 pll_528_set; /* 0x034 */
+ u32 pll_528_clr; /* 0x038 */
+ u32 pll_528_tog; /* 0x03c */
+ u32 pll_528_ss; /* 0x040 */
+ u32 rsvd0[3];
+ u32 pll_528_num; /* 0x050 */
+ u32 rsvd1[3];
+ u32 pll_528_denom; /* 0x060 */
+ u32 rsvd2[3];
+ u32 pll_audio; /* 0x070 */
+ u32 pll_audio_set; /* 0x074 */
+ u32 pll_audio_clr; /* 0x078 */
+ u32 pll_audio_tog; /* 0x07c */
+ u32 pll_audio_num; /* 0x080 */
+ u32 rsvd3[3];
+ u32 pll_audio_denom; /* 0x090 */
+ u32 rsvd4[3];
+ u32 pll_video; /* 0x0a0 */
+ u32 pll_video_set; /* 0x0a4 */
+ u32 pll_video_clr; /* 0x0a8 */
+ u32 pll_video_tog; /* 0x0ac */
+ u32 pll_video_num; /* 0x0b0 */
+ u32 rsvd5[3];
+ u32 pll_video_denom; /* 0x0c0 */
+ u32 rsvd6[3];
+ u32 pll_mlb; /* 0x0d0 */
+ u32 pll_mlb_set; /* 0x0d4 */
+ u32 pll_mlb_clr; /* 0x0d8 */
+ u32 pll_mlb_tog; /* 0x0dc */
+ u32 pll_enet; /* 0x0e0 */
+ u32 pll_enet_set; /* 0x0e4 */
+ u32 pll_enet_clr; /* 0x0e8 */
+ u32 pll_enet_tog; /* 0x0ec */
+ u32 pfd_480; /* 0x0f0 */
+ u32 pfd_480_set; /* 0x0f4 */
+ u32 pfd_480_clr; /* 0x0f8 */
+ u32 pfd_480_tog; /* 0x0fc */
+ u32 pfd_528; /* 0x100 */
+ u32 pfd_528_set; /* 0x104 */
+ u32 pfd_528_clr; /* 0x108 */
+ u32 pfd_528_tog; /* 0x10c */
+ u32 reg_1p1; /* 0x110 */
+ u32 reg_1p1_set; /* 0x114 */
+ u32 reg_1p1_clr; /* 0x118 */
+ u32 reg_1p1_tog; /* 0x11c */
+ u32 reg_3p0; /* 0x120 */
+ u32 reg_3p0_set; /* 0x124 */
+ u32 reg_3p0_clr; /* 0x128 */
+ u32 reg_3p0_tog; /* 0x12c */
+ u32 reg_2p5; /* 0x130 */
+ u32 reg_2p5_set; /* 0x134 */
+ u32 reg_2p5_clr; /* 0x138 */
+ u32 reg_2p5_tog; /* 0x13c */
+ u32 reg_core; /* 0x140 */
+ u32 reg_core_set; /* 0x144 */
+ u32 reg_core_clr; /* 0x148 */
+ u32 reg_core_tog; /* 0x14c */
+ u32 ana_misc0; /* 0x150 */
+ u32 ana_misc0_set; /* 0x154 */
+ u32 ana_misc0_clr; /* 0x158 */
+ u32 ana_misc0_tog; /* 0x15c */
+ u32 ana_misc1; /* 0x160 */
+ u32 ana_misc1_set; /* 0x164 */
+ u32 ana_misc1_clr; /* 0x168 */
+ u32 ana_misc1_tog; /* 0x16c */
+ u32 ana_misc2; /* 0x170 */
+ u32 ana_misc2_set; /* 0x174 */
+ u32 ana_misc2_clr; /* 0x178 */
+ u32 ana_misc2_tog; /* 0x17c */
+ u32 tempsense0; /* 0x180 */
+ u32 tempsense0_set; /* 0x184 */
+ u32 tempsense0_clr; /* 0x188 */
+ u32 tempsense0_tog; /* 0x18c */
+ u32 tempsense1; /* 0x190 */
+ u32 tempsense1_set; /* 0x194 */
+ u32 tempsense1_clr; /* 0x198 */
+ u32 tempsense1_tog; /* 0x19c */
+ u32 usb1_vbus_detect; /* 0x1a0 */
+ u32 usb1_vbus_detect_set; /* 0x1a4 */
+ u32 usb1_vbus_detect_clr; /* 0x1a8 */
+ u32 usb1_vbus_detect_tog; /* 0x1ac */
+ u32 usb1_chrg_detect; /* 0x1b0 */
+ u32 usb1_chrg_detect_set; /* 0x1b4 */
+ u32 usb1_chrg_detect_clr; /* 0x1b8 */
+ u32 usb1_chrg_detect_tog; /* 0x1bc */
+ u32 usb1_vbus_det_stat; /* 0x1c0 */
+ u32 usb1_vbus_det_stat_set; /* 0x1c4 */
+ u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
+ u32 usb1_vbus_det_stat_tog; /* 0x1cc */
+ u32 usb1_chrg_det_stat; /* 0x1d0 */
+ u32 usb1_chrg_det_stat_set; /* 0x1d4 */
+ u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
+ u32 usb1_chrg_det_stat_tog; /* 0x1dc */
+ u32 usb1_loopback; /* 0x1e0 */
+ u32 usb1_loopback_set; /* 0x1e4 */
+ u32 usb1_loopback_clr; /* 0x1e8 */
+ u32 usb1_loopback_tog; /* 0x1ec */
+ u32 usb1_misc; /* 0x1f0 */
+ u32 usb1_misc_set; /* 0x1f4 */
+ u32 usb1_misc_clr; /* 0x1f8 */
+ u32 usb1_misc_tog; /* 0x1fc */
+ u32 usb2_vbus_detect; /* 0x200 */
+ u32 usb2_vbus_detect_set; /* 0x204 */
+ u32 usb2_vbus_detect_clr; /* 0x208 */
+ u32 usb2_vbus_detect_tog; /* 0x20c */
+ u32 usb2_chrg_detect; /* 0x210 */
+ u32 usb2_chrg_detect_set; /* 0x214 */
+ u32 usb2_chrg_detect_clr; /* 0x218 */
+ u32 usb2_chrg_detect_tog; /* 0x21c */
+ u32 usb2_vbus_det_stat; /* 0x220 */
+ u32 usb2_vbus_det_stat_set; /* 0x224 */
+ u32 usb2_vbus_det_stat_clr; /* 0x228 */
+ u32 usb2_vbus_det_stat_tog; /* 0x22c */
+ u32 usb2_chrg_det_stat; /* 0x230 */
+ u32 usb2_chrg_det_stat_set; /* 0x234 */
+ u32 usb2_chrg_det_stat_clr; /* 0x238 */
+ u32 usb2_chrg_det_stat_tog; /* 0x23c */
+ u32 usb2_loopback; /* 0x240 */
+ u32 usb2_loopback_set; /* 0x244 */
+ u32 usb2_loopback_clr; /* 0x248 */
+ u32 usb2_loopback_tog; /* 0x24c */
+ u32 usb2_misc; /* 0x250 */
+ u32 usb2_misc_set; /* 0x254 */
+ u32 usb2_misc_clr; /* 0x258 */
+ u32 usb2_misc_tog; /* 0x25c */
+ u32 digprog; /* 0x260 */
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
#define OSC_FREQ_SHIFT 30
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
-/* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 */
+/*
+ * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
+ * but can be 16. We could use knowledge we have to restrict the mask in
+ * the 8-bit cases (the divider_bits value returned by
+ * get_periph_clock_source()) but it does not seem worth it since the code
+ * already checks the ranges of values it is writing, in clk_get_divider().
+ */
#define OUT_CLK_DIVISOR_SHIFT 0
-#define OUT_CLK_DIVISOR_MASK (255 << OUT_CLK_DIVISOR_SHIFT)
+#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
#define OUT_CLK_SOURCE_SHIFT 30
#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT)
PERIPH_ID_CRAM2,
PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
};
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
*/
void clock_ll_start_uart(enum periph_id periph_id);
+/**
+ * Decode a peripheral ID from a device tree node.
+ *
+ * This works by looking up the peripheral's 'clocks' node and reading out
+ * the second cell, which is the clock number / peripheral ID.
+ *
+ * @param blob FDT blob to use
+ * @param node Node to look at
+ * @return peripheral ID, or PERIPH_ID_NONE if none
+ */
+enum periph_id clock_decode_periph_id(const void *blob, int node);
+
/*
* Checks that clocks are valid and prints a warning if not
*
#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
#define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
-#define NV_PA_PMC_BASE 0x7000E400
+#define TEGRA2_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
#define NV_PA_CSITE_BASE 0x70040000
+#define TEGRA_USB1_BASE 0xC5000000
+#define TEGRA_USB3_BASE 0xC5008000
#define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE
#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
unsigned int cntr_1us;
};
#else /* __ASSEMBLY__ */
-#define PRM_RSTCTRL NV_PA_PMC_BASE
+#define PRM_RSTCTRL TEGRA2_PMC_BASE
#endif
#endif /* TEGRA2_H */
--- /dev/null
+/*
+ * NVIDIA Tegra2 I2C controller
+ *
+ * Copyright 2010-2011 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_I2C_H_
+#define _TEGRA_I2C_H_
+
+#include <asm/types.h>
+
+enum {
+ I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */
+ I2C_FIFO_DEPTH = 8, /* I2C fifo depth */
+};
+
+enum i2c_transaction_flags {
+ I2C_IS_WRITE = 0x1, /* for I2C write operation */
+ I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */
+ I2C_USE_REPEATED_START = 0x4, /* for repeat start */
+ I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */
+ I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */
+ I2C_NO_STOP = 0x20,
+};
+
+/* Contians the I2C transaction details */
+struct i2c_trans_info {
+ /* flags to indicate the transaction details */
+ enum i2c_transaction_flags flags;
+ u32 address; /* I2C slave device address */
+ u32 num_bytes; /* number of bytes to be transferred */
+ /*
+ * Send/receive buffer. For the I2C send operation this buffer should
+ * be filled with the data to be sent to the slave device. For the I2C
+ * receive operation this buffer is filled with the data received from
+ * the slave device.
+ */
+ u8 *buf;
+ int is_10bit_address;
+};
+
+struct i2c_control {
+ u32 tx_fifo;
+ u32 rx_fifo;
+ u32 packet_status;
+ u32 fifo_control;
+ u32 fifo_status;
+ u32 int_mask;
+ u32 int_status;
+};
+
+struct dvc_ctlr {
+ u32 ctrl1; /* 00: DVC_CTRL_REG1 */
+ u32 ctrl2; /* 04: DVC_CTRL_REG2 */
+ u32 ctrl3; /* 08: DVC_CTRL_REG3 */
+ u32 status; /* 0C: DVC_STATUS_REG */
+ u32 ctrl; /* 10: DVC_I2C_CTRL_REG */
+ u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */
+ u32 reserved_0[2]; /* 18: */
+ u32 req; /* 20: DVC_REQ_REGISTER */
+ u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */
+ u32 reserved_1[6]; /* 28: */
+ u32 cnfg; /* 40: DVC_I2C_CNFG */
+ u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */
+ u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */
+ u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */
+ u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */
+ u32 reserved_2[2]; /* 54: */
+ u32 i2c_status; /* 5C: DVC_I2C_STATUS */
+ struct i2c_control control; /* 60 ~ 78 */
+};
+
+struct i2c_ctlr {
+ u32 cnfg; /* 00: I2C_I2C_CNFG */
+ u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */
+ u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */
+ u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */
+ u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */
+ u32 reserved_0[2]; /* 14: */
+ u32 status; /* 1C: I2C_I2C_STATUS */
+ u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */
+ u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */
+ u32 sl_status; /* 28: I2C_I2C_SL_STATUS */
+ u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */
+ u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */
+ u32 reserved_1[2]; /* 34: */
+ u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */
+ u32 reserved_2[4]; /* 40: */
+ struct i2c_control control; /* 50 ~ 68 */
+};
+
+/* bit fields definitions for IO Packet Header 1 format */
+#define PKT_HDR1_PROTOCOL_SHIFT 4
+#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT)
+#define PKT_HDR1_CTLR_ID_SHIFT 12
+#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT)
+#define PKT_HDR1_PKT_ID_SHIFT 16
+#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT)
+#define PROTOCOL_TYPE_I2C 1
+
+/* bit fields definitions for IO Packet Header 2 format */
+#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0
+#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
+
+/* bit fields definitions for IO Packet Header 3 format */
+#define PKT_HDR3_READ_MODE_SHIFT 19
+#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT)
+#define PKT_HDR3_SLAVE_ADDR_SHIFT 0
+#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
+
+#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26
+#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \
+ (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
+
+/* I2C_CNFG */
+#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11
+#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
+#define I2C_CNFG_PACKET_MODE_SHIFT 10
+#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT)
+
+/* I2C_SL_CNFG */
+#define I2C_SL_CNFG_NEWSL_SHIFT 2
+#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT)
+
+/* I2C_FIFO_STATUS */
+#define TX_FIFO_FULL_CNT_SHIFT 0
+#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT)
+#define TX_FIFO_EMPTY_CNT_SHIFT 4
+#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT)
+
+/* I2C_INTERRUPT_STATUS */
+#define I2C_INT_XFER_COMPLETE_SHIFT 7
+#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT)
+#define I2C_INT_NO_ACK_SHIFT 3
+#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT)
+#define I2C_INT_ARBITRATION_LOST_SHIFT 2
+#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_USB_H_
+#define _TEGRA_USB_H_
+
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+ /* 0x000 */
+ uint id;
+ uint reserved0;
+ uint host;
+ uint device;
+
+ /* 0x010 */
+ uint txbuf;
+ uint rxbuf;
+ uint reserved1[2];
+
+ /* 0x020 */
+ uint reserved2[56];
+
+ /* 0x100 */
+ u16 cap_length;
+ u16 hci_version;
+ uint hcs_params;
+ uint hcc_params;
+ uint reserved3[5];
+
+ /* 0x120 */
+ uint dci_version;
+ uint dcc_params;
+ uint reserved4[6];
+
+ /* 0x140 */
+ uint usb_cmd;
+ uint usb_sts;
+ uint usb_intr;
+ uint frindex;
+
+ /* 0x150 */
+ uint reserved5;
+ uint periodic_list_base;
+ uint async_list_addr;
+ uint async_tt_sts;
+
+ /* 0x160 */
+ uint burst_size;
+ uint tx_fill_tuning;
+ uint reserved6; /* is this port_sc1 on some controllers? */
+ uint icusb_ctrl;
+
+ /* 0x170 */
+ uint ulpi_viewport;
+ uint reserved7;
+ uint endpt_nak;
+ uint endpt_nak_enable;
+
+ /* 0x180 */
+ uint reserved;
+ uint port_sc1;
+ uint reserved8[6];
+
+ /* 0x1a0 */
+ uint reserved9;
+ uint otgsc;
+ uint usb_mode;
+ uint endpt_setup_stat;
+
+ /* 0x1b0 */
+ uint reserved10[20];
+
+ /* 0x200 */
+ uint reserved11[0x80];
+
+ /* 0x400 */
+ uint susp_ctrl;
+ uint phy_vbus_sensors;
+ uint phy_vbus_wakeup_id;
+ uint phy_alt_vbus_sys;
+
+ /* 0x410 */
+ uint usb1_legacy_ctrl;
+ uint reserved12[3];
+
+ /* 0x420 */
+ uint reserved13[56];
+
+ /* 0x500 */
+ uint reserved14[64 * 3];
+
+ /* 0x800 */
+ uint utmip_pll_cfg0;
+ uint utmip_pll_cfg1;
+ uint utmip_xcvr_cfg0;
+ uint utmip_bias_cfg0;
+
+ /* 0x810 */
+ uint utmip_hsrx_cfg0;
+ uint utmip_hsrx_cfg1;
+ uint utmip_fslsrx_cfg0;
+ uint utmip_fslsrx_cfg1;
+
+ /* 0x820 */
+ uint utmip_tx_cfg0;
+ uint utmip_misc_cfg0;
+ uint utmip_misc_cfg1;
+ uint utmip_debounce_cfg0;
+
+ /* 0x830 */
+ uint utmip_bat_chrg_cfg0;
+ uint utmip_spare_cfg0;
+ uint utmip_xcvr_cfg1;
+ uint utmip_bias_cfg1;
+};
+
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE 1
+
+#define VBUS_SENSE_CTL_SHIFT 1
+#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
+#define VBUS_SENSE_CTL_AB_SESS_VLD 2
+#define VBUS_SENSE_CTL_A_SESS_VLD 3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB (1 << 12)
+#define UTMIP_RESET (1 << 11)
+#define USB_PHY_CLK_VALID (1 << 7)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
+#define UTMIP_PLLU_STABLE_COUNT_MASK \
+ (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
+ (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
+ (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
+#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK \
+ (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
+#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J (1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG 1
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL (1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT 15
+#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT 10
+#define UTMIP_ELASTIC_LIMIT_MASK \
+ (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG0_1 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
+#define UTMIP_HS_SYNC_START_DLY_MASK \
+ (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1 (1 << 3)
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define PTS_SHIFT 30
+#define PTS_MASK (3U << PTS_SHIFT)
+#define PTS_UTMI 0
+#define PTS_RESERVED 1
+#define PTS_ULP 2
+#define PTS_ICUSB_SER 3
+
+#define STS (1 << 29)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS (1 << 26)
+
+
+/* Change the USB host port into host mode */
+void usb_set_host_mode(void);
+
+/* Setup USB on the board */
+int board_usb_init(const void *blob);
+
+/**
+ * Start up the given port number (ports are numbered from 0 on each board).
+ * This returns values for the appropriate hccr and hcor addresses to use for
+ * USB EHCI operations.
+ *
+ * @param portnum port number to start
+ * @param hccr returns start address of EHCI HCCR registers
+ * @param hcor returns start address of EHCI HCOR registers
+ * @return 0 if ok, -1 on error (generally invalid port number)
+ */
+int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor);
+
+/**
+ * Stop the current port
+ *
+ * @return 0 if ok, -1 if no port was active
+ */
+int tegrausb_stop_port(void);
+
+#endif /* _TEGRA_USB_H_ */
--- /dev/null
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef ARM_BOOTM_H
+#define ARM_BOOTM_H
+
+#ifdef CONFIG_USB_DEVICE
+extern void udc_disconnect(void);
+#endif
+
+#endif
/* SPL common function s*/
void spl_parse_image_header(const struct image_header *header);
void omap_rev_string(void);
+void spl_board_prepare_for_linux(void);
+int spl_start_uboot(void);
/* NAND SPL functions */
void spl_nand_load_image(void);
/* MMC SPL functions */
void spl_mmc_load_image(void);
+/* YMODEM SPL functions */
+void spl_ymodem_load_image(void);
+
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void);
#endif
COBJS-y += board.o
COBJS-y += bootm.o
-COBJS-y += cache.o
-COBJS-y += cache-cp15.o
COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
COBJS-y += interrupts.o
COBJS-y += reset.o
SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
endif
+COBJS-y += cache.o
+COBJS-y += cache-cp15.o
+
SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
$(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
}
}
+#ifdef CONFIG_OF_CONTROL
+ /* For now, put this check after the console is ready */
+ if (fdtdec_prepare_fdt()) {
+ panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+ "doc/README.fdt-control");
+ }
+#endif
+
debug("monitor len: %08lX\n", gd->mon_len);
/*
* Ram is setup, size stored in gd !!
-/*
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ * - Added prep subcommand support
+ * - Reorganized source - modeled after powerpc version
+ *
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <asm/bootm.h>
DECLARE_GLOBAL_DATA_PTR;
-#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
- defined (CONFIG_CMDLINE_TAG) || \
- defined (CONFIG_INITRD_TAG) || \
- defined (CONFIG_SERIAL_TAG) || \
- defined (CONFIG_REVISION_TAG)
-static void setup_start_tag (bd_t *bd);
-
-# ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags (bd_t *bd);
-# endif
-static void setup_commandline_tag (bd_t *bd, char *commandline);
-
-# ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag (bd_t *bd, ulong initrd_start,
- ulong initrd_end);
-# endif
-static void setup_end_tag (bd_t *bd);
-
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
static struct tag *params;
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
-
-static ulong get_sp(void);
-#if defined(CONFIG_OF_LIBFDT)
-static int bootm_linux_fdt(int machid, bootm_headers_t *images);
#endif
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, sp" : "=r"(ret) : );
+ return ret;
+}
+
void arch_lmb_reserve(struct lmb *lmb)
{
ulong sp;
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
}
-static void announce_and_cleanup(void)
-{
- printf("\nStarting kernel ...\n\n");
- bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
-#ifdef CONFIG_BOOTSTAGE_REPORT
- bootstage_report();
-#endif
-
-#ifdef CONFIG_USB_DEVICE
- {
- extern void udc_disconnect(void);
- udc_disconnect();
- }
-#endif
- cleanup_before_linux();
-}
-
-int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
-{
- bd_t *bd = gd->bd;
- char *s;
- int machid = bd->bi_arch_number;
- void (*kernel_entry)(int zero, int arch, uint params);
-
-#ifdef CONFIG_CMDLINE_TAG
- char *commandline = getenv ("bootargs");
-#endif
-
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
-
- s = getenv ("machid");
- if (s) {
- machid = simple_strtoul (s, NULL, 16);
- printf ("Using machid 0x%x from environment\n", machid);
- }
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
#ifdef CONFIG_OF_LIBFDT
- if (images->ft_len)
- return bootm_linux_fdt(machid, images);
-#endif
-
- kernel_entry = (void (*)(int, int, uint))images->ep;
-
- debug ("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong) kernel_entry);
-
-#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
- defined (CONFIG_CMDLINE_TAG) || \
- defined (CONFIG_INITRD_TAG) || \
- defined (CONFIG_SERIAL_TAG) || \
- defined (CONFIG_REVISION_TAG)
- setup_start_tag (bd);
-#ifdef CONFIG_SERIAL_TAG
- setup_serial_tag (¶ms);
-#endif
-#ifdef CONFIG_REVISION_TAG
- setup_revision_tag (¶ms);
-#endif
-#ifdef CONFIG_SETUP_MEMORY_TAGS
- setup_memory_tags (bd);
-#endif
-#ifdef CONFIG_CMDLINE_TAG
- setup_commandline_tag (bd, commandline);
-#endif
-#ifdef CONFIG_INITRD_TAG
- if (images->rd_start && images->rd_end)
- setup_initrd_tag (bd, images->rd_start, images->rd_end);
-#endif
- setup_end_tag(bd);
-#endif
-
- announce_and_cleanup();
-
- kernel_entry(0, machid, bd->bi_boot_params);
- /* does not return */
-
- return 1;
-}
-
-#if defined(CONFIG_OF_LIBFDT)
static int fixup_memory_node(void *blob)
{
bd_t *bd = gd->bd;
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
}
+#endif
-static int bootm_linux_fdt(int machid, bootm_headers_t *images)
+static void announce_and_cleanup(void)
{
- ulong rd_len;
- void (*kernel_entry)(int zero, int dt_machid, void *dtblob);
- ulong of_size = images->ft_len;
- char **of_flat_tree = &images->ft_addr;
- ulong *initrd_start = &images->initrd_start;
- ulong *initrd_end = &images->initrd_end;
- struct lmb *lmb = &images->lmb;
- int ret;
-
- kernel_entry = (void (*)(int, int, void *))images->ep;
-
- boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
-
- rd_len = images->rd_end - images->rd_start;
- ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
- initrd_start, initrd_end);
- if (ret)
- return ret;
-
- ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
- if (ret)
- return ret;
-
- debug("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong) kernel_entry);
-
- fdt_chosen(*of_flat_tree, 1);
-
- fixup_memory_node(*of_flat_tree);
-
- fdt_fixup_ethernet(*of_flat_tree);
-
- fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
-
- announce_and_cleanup();
-
- kernel_entry(0, machid, *of_flat_tree);
- /* does not return */
+ printf("\nStarting kernel ...\n\n");
+ bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+#ifdef CONFIG_BOOTSTAGE_REPORT
+ bootstage_report();
+#endif
- return 1;
-}
+#ifdef CONFIG_USB_DEVICE
+ udc_disconnect();
#endif
+ cleanup_before_linux();
+}
-#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
- defined (CONFIG_CMDLINE_TAG) || \
- defined (CONFIG_INITRD_TAG) || \
- defined (CONFIG_SERIAL_TAG) || \
- defined (CONFIG_REVISION_TAG)
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
static void setup_start_tag (bd_t *bd)
{
- params = (struct tag *) bd->bi_boot_params;
+ params = (struct tag *)bd->bi_boot_params;
params->hdr.tag = ATAG_CORE;
params->hdr.size = tag_size (tag_core);
params = tag_next (params);
}
-
+#endif
#ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags (bd_t *bd)
+static void setup_memory_tags(bd_t *bd)
{
int i;
params = tag_next (params);
}
}
-#endif /* CONFIG_SETUP_MEMORY_TAGS */
-
+#endif
-static void setup_commandline_tag (bd_t *bd, char *commandline)
+#ifdef CONFIG_CMDLINE_TAG
+static void setup_commandline_tag(bd_t *bd, char *commandline)
{
char *p;
params = tag_next (params);
}
-
+#endif
#ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end)
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
{
/* an ATAG_INITRD node tells the kernel where the compressed
* ramdisk can be found. ATAG_RDIMG is a better name, actually.
params = tag_next (params);
}
-#endif /* CONFIG_INITRD_TAG */
+#endif
#ifdef CONFIG_SERIAL_TAG
-void setup_serial_tag (struct tag **tmp)
+void setup_serial_tag(struct tag **tmp)
{
struct tag *params = *tmp;
struct tag_serialnr serialnr;
params->u.revision.rev = rev;
params = tag_next (params);
}
-#endif /* CONFIG_REVISION_TAG */
+#endif
-static void setup_end_tag (bd_t *bd)
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+static void setup_end_tag(bd_t *bd)
{
params->hdr.tag = ATAG_NONE;
params->hdr.size = 0;
}
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+#endif
-static ulong get_sp(void)
+#ifdef CONFIG_OF_LIBFDT
+static int create_fdt(bootm_headers_t *images)
{
- ulong ret;
+ ulong of_size = images->ft_len;
+ char **of_flat_tree = &images->ft_addr;
+ ulong *initrd_start = &images->initrd_start;
+ ulong *initrd_end = &images->initrd_end;
+ struct lmb *lmb = &images->lmb;
+ ulong rd_len;
+ int ret;
- asm("mov %0, sp" : "=r"(ret) : );
- return ret;
+ debug("using: FDT\n");
+
+ boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+
+ rd_len = images->rd_end - images->rd_start;
+ ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
+ initrd_start, initrd_end);
+ if (ret)
+ return ret;
+
+ ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+ if (ret)
+ return ret;
+
+ fdt_chosen(*of_flat_tree, 1);
+ fixup_memory_node(*of_flat_tree);
+ fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+
+ return 0;
+}
+#endif
+
+/* Subcommand: PREP */
+static void boot_prep_linux(bootm_headers_t *images)
+{
+#ifdef CONFIG_CMDLINE_TAG
+ char *commandline = getenv("bootargs");
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+ if (images->ft_len) {
+ debug("using: FDT\n");
+ if (create_fdt(images)) {
+ printf("FDT creation failed! hanging...");
+ hang();
+ }
+ } else
+#endif
+ {
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+ debug("using: ATAGS\n");
+ setup_start_tag(gd->bd);
+#ifdef CONFIG_SERIAL_TAG
+ setup_serial_tag(¶ms);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+ setup_commandline_tag(gd->bd, commandline);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ setup_revision_tag(¶ms);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+ setup_memory_tags(gd->bd);
+#endif
+#ifdef CONFIG_INITRD_TAG
+ if (images->rd_start && images->rd_end)
+ setup_initrd_tag(gd->bd, images->rd_start,
+ images->rd_end);
+#endif
+ setup_end_tag(gd->bd);
+#else /* all tags */
+ printf("FDT and ATAGS support not compiled in - hanging\n");
+ hang();
+#endif /* all tags */
+ }
+}
+
+/* Subcommand: GO */
+static void boot_jump_linux(bootm_headers_t *images)
+{
+ unsigned long machid = gd->bd->bi_arch_number;
+ char *s;
+ void (*kernel_entry)(int zero, int arch, uint params);
+
+ kernel_entry = (void (*)(int, int, uint))images->ep;
+
+ s = getenv("machid");
+ if (s) {
+ strict_strtoul(s, 16, &machid);
+ printf("Using machid 0x%lx from environment\n", machid);
+ }
+
+ debug("## Transferring control to Linux (at address %08lx)" \
+ "...\n", (ulong) kernel_entry);
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+ announce_and_cleanup();
+ kernel_entry(0, machid, gd->bd->bi_boot_params);
+}
+
+/* Main Entry point for arm bootm implementation
+ *
+ * Modeled after the powerpc implementation
+ * DIFFERENCE: Instead of calling prep and go at the end
+ * they are called if subcommand is equal 0.
+ */
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+ /* No need for those on ARM */
+ if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+ return -1;
+
+ if (flag & BOOTM_STATE_OS_PREP) {
+ boot_prep_linux(images);
+ return 0;
+ }
+
+ if (flag & BOOTM_STATE_OS_GO) {
+ boot_jump_linux(images);
+ return 0;
+ }
+
+ boot_prep_linux(images);
+ boot_jump_linux(images);
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BOOTZ
+
+struct zimage_header {
+ uint32_t code[9];
+ uint32_t zi_magic;
+ uint32_t zi_start;
+ uint32_t zi_end;
+};
+
+#define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818
+
+int bootz_setup(void *image, void **start, void **end)
+{
+ struct zimage_header *zi = (struct zimage_header *)image;
+
+ if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) {
+ puts("Bad Linux ARM zImage magic!\n");
+ return 1;
+ }
+
+ *start = (void *)zi->zi_start;
+ *end = (void *)zi->zi_end;
+
+ debug("Kernel image @ 0x%08x [ 0x%08x - 0x%08x ]\n",
+ (uint32_t)image, (uint32_t)*start, (uint32_t)*end);
+
+ return 0;
}
+#endif /* CONFIG_CMD_BOOTZ */
--- /dev/null
+/*
+ * Renesas SuperH MMCIF driver.
+ *
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ */
+#ifndef _SH_MMC_H_
+#define _SH_MMC_H_
+
+int mmcif_mmc_init(void);
+
+#endif /* _SH_MMC_H_ */
+
#include <version.h>
#include <watchdog.h>
#include <net.h>
+#include <mmc.h>
#include <environment.h>
#ifdef CONFIG_BITBANGMII
int board_init(void)
{
- gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
int board_init(void)
{
- gd->bd->bi_arch_number = MACH_TYPE_ACTUX2;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
int board_init(void)
{
- gd->bd->bi_arch_number = MACH_TYPE_ACTUX3;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
int board_init(void)
{
- gd->bd->bi_arch_number = MACH_TYPE_ACTUX4;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
#include <common.h>
#include <errno.h>
+#include <hush.h>
#include <linux/mtd/nand.h>
#include <nand.h>
#include <miiphy.h>
size_t size;
};
-static struct fit_images_info images[10];
+static struct fit_images_info imgs[10];
struct menu_display {
char title[50];
{
struct menu *m;
int i;
- char *choice = NULL;
+ void *choice = NULL;
char key[2];
int ret;
char *s;
sprintf(key, "%d", 1);
menu_default_set(m, key);
- if (menu_get_choice(m, (void **)&choice) != 1)
+ if (menu_get_choice(m, &choice) != 1)
debug("Problem picking a choice!\n");
menu_destroy(m);
sprintf(s, "%lx", i);
ret = setenv("header_addr", s);
if (ret == 0)
- ret = run_command2("run img_writeheader", 0);
+ ret = run_command("run img_writeheader", 0);
if (ret != 0)
break;
}
* img_writeramdisk: write ramdisk to ubi volume
*/
- while (images[count].type != IH_TYPE_INVALID) {
+ while (imgs[count].type != IH_TYPE_INVALID) {
printf("Installing %s\n",
- genimg_get_type_name(images[count].type));
- sprintf(s, "%p", images[count].data);
+ genimg_get_type_name(imgs[count].type));
+ sprintf(s, "%p", imgs[count].data);
setenv("img_addr_r", s);
- sprintf(s, "%lx", (unsigned long)images[count].size);
+ sprintf(s, "%lx", (unsigned long)imgs[count].size);
setenv("filesize", s);
- switch (images[count].subtype) {
+ switch (imgs[count].subtype) {
case FIT_SUBTYPE_DF_ENV_IMAGE:
- ret = run_command2("run img_writedfenv", 0);
+ ret = run_command("run img_writedfenv", 0);
break;
case FIT_SUBTYPE_RAMDISK_IMAGE:
t = getenv("img_volume");
if (ret != 0)
break;
- ret = run_command2("run img_writeramdisk", 0);
+ ret = run_command("run img_writeramdisk", 0);
break;
case FIT_SUBTYPE_SPL_IMAGE:
- ret = run_command2("run img_writespl", 0);
+ ret = run_command("run img_writespl", 0);
break;
case FIT_SUBTYPE_UBL_HEADER:
ret = ait_writeublheader();
break;
case FIT_SUBTYPE_UBOOT_IMAGE:
- ret = run_command2("run img_writeuboot", 0);
+ ret = run_command("run img_writeuboot", 0);
break;
default:
/* not supported type */
count++;
}
/* now save dvn_* and img_volume env vars to new values */
- if (ret == 0)
- ret = run_command2("run savenewvers", 0);
+ if (ret == 0) {
+ t = getenv("x_dvn_boot_vers");
+ if (t)
+ setenv("dvn_boot_vers", t);
+
+ t = getenv("x_dvn_app_vers");
+ if (t)
+ setenv("dvn_boot_vers", t);
+
+ setenv("x_dvn_boot_vers", NULL);
+ setenv("x_dvn_app_vers", NULL);
+ ret = run_command("run savenewvers", 0);
+ }
return ret;
}
break;
case '2':
/* cancel, back to main */
+ setenv("x_dvn_boot_vers", NULL);
+ setenv("x_dvn_app_vers", NULL);
break;
}
int found_uboot = -1;
int found_ramdisk = -1;
- memset(images, 0, sizeof(images));
+ memset(imgs, 0, sizeof(imgs));
s = getenv("fit_addr_r");
fit_addr = s ? (unsigned long)simple_strtol(s, NULL, 16) : \
CONFIG_BOARD_IMG_ADDR_R;
fit_image_print(addr, noffset, "");
fit_image_get_type(addr, noffset,
- &images[count].type);
+ &imgs[count].type);
/* Mandatory properties */
ret = fit_get_desc(addr, noffset, &desc);
printf("Description: ");
if (ret) {
printf("unavailable\n");
} else {
- images[count].subtype = ait_subtype_nr(subtype);
+ imgs[count].subtype = ait_subtype_nr(subtype);
printf("%s %d\n", subtype,
- images[count].subtype);
+ imgs[count].subtype);
}
- sprintf(images[count].desc, "%s", desc);
+ sprintf(imgs[count].desc, "%s", desc);
ret = fit_image_get_data(addr, noffset,
- &images[count].data,
- &images[count].size);
+ &imgs[count].data,
+ &imgs[count].size);
printf("Data Size: ");
if (ret)
printf("unavailable\n");
else
- genimg_print_size(images[count].size);
- printf("Data @ %p\n", images[count].data);
+ genimg_print_size(imgs[count].size);
+ printf("Data @ %p\n", imgs[count].data);
count++;
}
}
for (i = 0; i < count; i++) {
- if (images[i].subtype == FIT_SUBTYPE_UBOOT_IMAGE)
+ if (imgs[i].subtype == FIT_SUBTYPE_UBOOT_IMAGE)
found_uboot = i;
- if (images[i].type == IH_TYPE_RAMDISK) {
+ if (imgs[i].type == IH_TYPE_RAMDISK) {
found_ramdisk = i;
- images[i].subtype = FIT_SUBTYPE_RAMDISK_IMAGE;
+ imgs[i].subtype = FIT_SUBTYPE_RAMDISK_IMAGE;
}
}
if (found_uboot >= 0) {
s = getenv("dvn_boot_vers");
if (s) {
- ret = strcmp(s, images[found_uboot].desc);
+ ret = strcmp(s, imgs[found_uboot].desc);
if (ret != 0) {
- setenv("dvn_boot_vers",
- images[found_uboot].desc);
+ setenv("x_dvn_boot_vers",
+ imgs[found_uboot].desc);
} else {
found_uboot = -1;
printf("no new uboot version\n");
}
} else {
- setenv("dvn_boot_vers", images[found_uboot].desc);
+ setenv("dvn_boot_vers", imgs[found_uboot].desc);
}
}
if (found_ramdisk >= 0) {
s = getenv("dvn_app_vers");
if (s) {
- ret = strcmp(s, images[found_ramdisk].desc);
+ ret = strcmp(s, imgs[found_ramdisk].desc);
if (ret != 0) {
- setenv("dvn_app_vers",
- images[found_ramdisk].desc);
+ setenv("x_dvn_app_vers",
+ imgs[found_ramdisk].desc);
} else {
found_ramdisk = -1;
printf("no new ramdisk version\n");
}
} else {
- setenv("dvn_app_vers", images[found_ramdisk].desc);
+ setenv("dvn_app_vers", imgs[found_ramdisk].desc);
}
}
if ((found_uboot == -1) && (found_ramdisk == -1))
break;
case '2':
/* load image */
- ret = run_command2("run load_img", 0);
+ ret = run_command("run load_img", 0);
printf("ret: %d\n", ret);
if (ret)
return MENU_UPDATE;
{
int ret;
- run_command2("run saveparms", 0);
+ run_command("run saveparms", 0);
ret = ait_menu_show(&ait_main, bootdelay);
- run_command2("run restoreparms", 0);
+ run_command("run restoreparms", 0);
if (ret == MENU_EXIT_BOOTCMD)
return 0;
void menu_display_statusline(struct menu *m)
{
- printf("State: dvn_boot_vers: %s dvn_app_vers: %s\n",
- getenv("dvn_boot_vers"), getenv("dvn_app_vers"));
+ char *s1, *s2;
+
+ s1 = getenv("x_dvn_boot_vers");
+ if (!s1)
+ s1 = getenv("dvn_boot_vers");
+
+ s2 = getenv("x_dvn_app_vers");
+ if (!s2)
+ s2 = getenv("dvn_app_vers");
+
+ printf("State: dvn_boot_vers: %s dvn_app_vers: %s\n", s1, s2);
return;
}
#endif
UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
ifndef CONFIG_SPL_BUILD
ALL-y += $(obj)u-boot.ubl
+else
+# as SPL_TEXT_BASE is not page-aligned, we need for some
+# linkers the -n flag (Do not page align data), to prevent
+# the following error message:
+# arm-linux-ld: u-boot-spl: Not enough room for program headers, try linking
+# with -N
+LDFLAGS_u-boot-spl += -n
endif
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
+ . = CONFIG_SPL_TEXT_BASE;
. = ALIGN(4);
.text :
ulong get_board_rev(void){
return readl((u32 *)SYS_ID);
}
+
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+ulong get_tbclk (void)
+{
+ return (ulong)CONFIG_SYS_HZ;
+}
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
#include <asm/arch/da8xx-fb.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
- struct davinci_gpio *gpio6_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
-
/* PinMux for GPIO */
if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
return 1;
/* Set the RESETOUTn low */
- writel((readl(&gpio6_base->set_data) & ~(1 << 15)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir);
+ gpio_direction_output(111, 0);
/* Set U0_SW0 low for UART0 as console*/
- writel((readl(&gpio6_base->set_data) & ~(1 << 10)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir);
+ gpio_direction_output(106, 0);
/* Set U0_SW1 low for UART0 as console*/
- writel((readl(&gpio6_base->set_data) & ~(1 << 12)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir);
+ gpio_direction_output(108, 0);
/* Set LCD_B_PWR low to power down LCD Backlight*/
- writel((readl(&gpio6_base->set_data) & ~(1 << 6)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 6)), &gpio6_base->dir);
+ gpio_direction_output(102, 0);
/* Set DISP_ON low to disable LCD output*/
- writel((readl(&gpio6_base->set_data) & ~(1 << 1)),
- &gpio6_base->set_data);
- writel((readl(&gpio6_base->dir) & ~(1 << 1)), &gpio6_base->dir);
+ gpio_direction_output(97, 0);
#ifndef CONFIG_USE_IRQ
irq_init();
&davinci_syscfg_regs->mstpri[2]);
/* Set LCD_B_PWR low to power up LCD Backlight*/
- writel((readl(&gpio6_base->set_data) | (1 << 6)),
- &gpio6_base->set_data);
+ gpio_set_value(102, 1);
/* Set DISP_ON low to disable LCD output*/
- writel((readl(&gpio6_base->set_data) | (1 << 1)),
- &gpio6_base->set_data);
+ gpio_set_value(97, 1);
return 0;
}
int board_late_init(void)
{
- struct davinci_gpio *gpio8_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK8;
-
/* PinMux for HALTEN */
if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
return 1;
/* Set HALTEN to high */
- writel((readl(&gpio8_base->set_data) | (1 << 6)),
- &gpio8_base->set_data);
- writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir);
+ gpio_direction_output(134, 1);
setenv("stdout", "serial");
#include <asm/arch/sys_proto.h>
#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
- MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
- MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
- MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
/* UART1 */
+#ifdef CONFIG_DENX_M28_V10
+ MX28_PAD_AUART0_CTS__DUART_RX,
+ MX28_PAD_AUART0_RTS__DUART_TX,
+#else
MX28_PAD_PWM0__DUART_RX,
MX28_PAD_PWM1__DUART_TX,
+#endif
MX28_PAD_AUART0_TX__DUART_RTS,
MX28_PAD_AUART0_RX__DUART_CTS,
int board_init(void)
{
- gd->bd->bi_arch_number = MACH_TYPE_DVLHOST;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
#include <spi.h>
#include <dataflash.h>
#include <mmc.h>
+#include <atmel_mci.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <net.h>
#include <netdev.h>
#include <mmc.h>
+#include <atmel_mci.h>
#include <i2c.h>
#include <spi.h>
#include <asm/io.h>
/*
* write RTC kick register to enable write
- * for RTC Scratch registers. Cratch0 and 1 are
+ * for RTC Scratch registers. Scratch0 and 1 are
* used for bootcount values.
*/
writel(RTC_KICK0R_WE, ®->kick0r);
#ifdef CONFIG_PCI
#include <pci.h>
-#ifdef CONFIG_PCI_PNP
-int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
-#endif
-
#include "../../Marvell/include/pci.h"
#undef DEBUG
int board_eth_init(bd_t *bis)
{
- int rc = 0;
+ int rc = -ENODEV;
weim_smc911x_iomux();
weim_cs1_settings();
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
}
+iomux_v3_cfg_t usb_pads[] = {
+ MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+
+ /* Reset USB hub */
+ gpio_direction_output(GPIO_NUMBER(7, 12), 0);
+ mdelay(2);
+ gpio_set_value(GPIO_NUMBER(7, 12), 1);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR, 1},
}
#endif
+u32 get_board_rev(void)
+{
+ return 0x63000 ;
+}
+
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t ecspi1_pads[] = {
/* SS1 */
if (ret)
printf("FEC MXC: %s:failed\n", __func__);
-#ifdef CONFIG_MXC_SPI
- setup_spi();
-#endif
-
return 0;
}
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+
return 0;
}
#include <common.h>
#include <ahci.h>
+#include <netdev.h>
#include <scsi.h>
#include <asm/sizes.h>
+#include <asm/io.h>
+
+#define HB_SREG_A9_PWR_REQ 0xfff3cf00
+#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
+#define HB_PWR_SUSPEND 0
+#define HB_PWR_SOFT_RESET 1
+#define HB_PWR_HARD_RESET 2
+#define HB_PWR_SHUTDOWN 3
DECLARE_GLOBAL_DATA_PTR;
int misc_init_r(void)
{
+ char envbuffer[16];
+ u32 boot_choice;
+
ahci_init(0xffe08000);
scsi_scan(1);
+
+ boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
+ sprintf(envbuffer, "bootcmd%d", boot_choice);
+ if (getenv(envbuffer)) {
+ sprintf(envbuffer, "run bootcmd%d", boot_choice);
+ setenv("bootcmd", envbuffer);
+ } else
+ setenv("bootcmd", "");
+
return 0;
}
void reset_cpu(ulong addr)
{
+ writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
+ asm(" wfi");
}
#include <asm/arch/pinmux.h>
#include <asm/arch/uart.h>
#include <spi.h>
+#include <asm/arch/usb.h>
+#include <i2c.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+void __pin_mux_usb(void)
+{
+}
+
+void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
+
/*
* Routine: board_init
* Description: Early hardware init.
#endif
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
+#ifdef CONFIG_TEGRA_I2C
+#ifndef CONFIG_SYS_I2C_INIT_BOARD
+#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
+#endif
+ i2c_init_board();
+#endif
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+ pin_mux_usb();
+ board_usb_init(gd->fdt_blob);
+#endif
return 0;
}
void gpio_config_uart(void);
void gpio_early_init_uart(void);
+/*
+ * Set up any pin muxing needed for USB (for now, since fdt doesn't support
+ * it). Boards can overwrite the default fucction which does nothing.
+ */
+void pin_mux_usb(void);
+
#endif /* BOARD_H */
--- /dev/null
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "NVIDIA Seaboard";
+ compatible = "nvidia,seaboard", "nvidia,tegra20";
+
+ chosen {
+ bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
+ };
+
+ aliases {
+ /* This defines the order of our USB ports */
+ usb0 = "/usb@c5008000";
+ usb1 = "/usb@c5000000";
+
+ i2c0 = "/i2c@7000d000";
+ i2c1 = "/i2c@7000c000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = < 0x00000000 0x40000000 >;
+ };
+
+ /* This is not used in U-Boot, but is expected to be in kernel .dts */
+ i2c@7000d000 {
+ clock-frequency = <100000>;
+ pmic@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+
+ clk_32k: clock {
+ compatible = "fixed-clock";
+ /*
+ * leave out for now due to CPP:
+ * #clock-cells = <0>;
+ */
+ clock-frequency = <32768>;
+ };
+ };
+ };
+
+ clocks {
+ osc {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ clock@60006000 {
+ clocks = <&clk_32k &osc>;
+ };
+
+ serial@70006300 {
+ clock-frequency = < 216000000 >;
+ };
+
+ sdhci@c8000400 {
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ };
+
+ sdhci@c8000600 {
+ support-8bit;
+ };
+
+ usb@c5000000 {
+ nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+ dr_mode = "otg";
+ };
+
+ usb@c5004000 {
+ status = "disabled";
+ };
+
+ i2c@7000c000 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c400 {
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ clock-frequency = <100000>;
+ };
+};
return 0;
}
#endif
+
+void pin_mux_usb(void)
+{
+ /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
+ pinmux_tristate_disable(PINGRP_SLXK);
+}
/*
* write RTC kick register to enable write
- * for RTC Scratch registers. Cratch0 and 1 are
+ * for RTC Scratch registers. Scratch0 and 1 are
* used for bootcount values.
*/
writel(RTC_KICK0R_WE, ®->kick0r);
#ifdef CONFIG_PCI
#include <pci.h>
-#ifdef CONFIG_PCI_PNP
-int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
-#endif
-
#include "../../Marvell/include/pci.h"
#undef DEBUG
{
int i;
- if (len % 4) {
- for (i = 0; i < len; i++)
- buf[i] = readb(&(pdnb3_ndfc->data));
- } else {
- ulong *ptr = (ulong *)buf;
- int count = len >> 2;
-
- for (i = 0; i < count; i++)
- *ptr++ = readl(&(pdnb3_ndfc->data));
- }
+ for (i = 0; i < len; i++)
+ buf[i] = readb(&(pdnb3_ndfc->data));
}
static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
{
- volatile u_char val;
-
/*
* Blocking read to wait for NAND to be ready
*/
- val = readb(&(pdnb3_ndfc->wait));
+ readb(&(pdnb3_ndfc->wait));
/*
* Return always true
*/
int board_init(void)
{
- /* arch number of PDNB3 */
- gd->bd->bi_arch_number = MACH_TYPE_PDNB3;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
COBJS := ecovec.o
SOBJS := lowlevel_init.o
-$(LIB): $(obj).depend $(COBJS) $(SOBJS)
- $(call cmd_link_o_target, $(COBJS) $(SOBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
{
u8 mac[6];
char env_mac[17];
- int i;
udelay(1000);
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/mmc.h>
#include <spi_flash.h>
int checkboard(void)
return 0;
}
+int board_mmc_init(bd_t *bis)
+{
+ return mmcif_mmc_init();
+}
+
static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
struct spi_flash *spi;
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
int i;
- /* UART1 GPIOs (part1) : GPA0CON[7:4] 0x2222 */
- for (i = 4; i < 8; i++) {
+ /*
+ * UART0 GPIOs : GPA0CON[3:0] 0x2222
+ * Must set CFG17 switches to select UART0 to use.
+ */
+ for (i = 0; i <= 3; i++) {
s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
}
+
+ /*
+ * UART1 GPIOs : GPA0CON[5:4] 0x22
+ * Must set CFG17 switches to select UART1 to use.
+ *
+ * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down
+ * in order to use them (so that those pins can be used for I2C).
+ */
+ for (i = 4; i <= 5; i++) {
+ s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
+ }
+
+ /*
+ * UART2 GPIOs : GPA1CON[1:0] 0x22
+ * Must set CFG17 switches to select UART2 to use.
+ *
+ * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down
+ * in order to use them (so that those pins can be used for I2C).
+ */
+ for (i = 0; i <= 1; i++) {
+ s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2));
+ }
+
+ /*
+ * UART3 GPIOs : GPA1CON[5:4] 0x22
+ * Must set CFG16 switches to select UART3 to use.
+ */
+ for (i = 4; i <= 5; i++) {
+ s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2));
+ }
+
+ /*
+ * There's no mux for UART4--it's internal only
+ */
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
return omap_mmc_init(0);
}
#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * Do board specific preperation before SPL
+ * Linux boot
+ */
+void spl_board_prepare_for_linux(void)
+{
+ /* init cs for extern lan */
+ enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+}
+int spl_start_uboot(void)
+{
+ int val = 0;
+ if (!gpio_request(CONFIG_SPL_OS_BOOT_KEY, "U-Boot key")) {
+ gpio_direction_input(CONFIG_SPL_OS_BOOT_KEY);
+ val = gpio_get_value(CONFIG_SPL_OS_BOOT_KEY);
+ gpio_free(CONFIG_SPL_OS_BOOT_KEY);
+ }
+ return val;
+}
+#endif
/* FPGA CS1 configuration */
#define FPGA_GPMC_CONFIG1 0x00001200
-#define FPGA_GPMC_CONFIG2 0x00111a00
-#define FPGA_GPMC_CONFIG3 0x00010100
-#define FPGA_GPMC_CONFIG4 0x06041a04
-#define FPGA_GPMC_CONFIG5 0x0019101a
-#define FPGA_GPMC_CONFIG6 0x890503c0
-#define FPGA_GPMC_CONFIG7 0x00000860
+#define FPGA_GPMC_CONFIG2 0x00161f00
+#define FPGA_GPMC_CONFIG3 0x00040400
+#define FPGA_GPMC_CONFIG4 0x120c1f08
+#define FPGA_GPMC_CONFIG5 0x001e161f
+#define FPGA_GPMC_CONFIG6 0x96080fcf
#define FPGA_BASE_ADDR 0x20000000
/*
* Enable DVI power
*/
-static void beagle_dvi_pup() {
+static void beagle_dvi_pup(void)
+{
uchar val;
switch (get_board_revision()) {
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := omap1610innovator.o flash.o
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Kshitij Gupta <Kshitij@ti.com>
-#
-# TI Innovator board with OMAP1610 (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Innovator has 1 bank of 256 MB SDRAM
-# Physical Address:
-# 1000'0000 to 2000'0000
-#
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
-# (mem base + reserved)
-#
-# we load ourself to 1108'0000
-#
-#
-
-
-CONFIG_SYS_TEXT_BASE = 0x11080000
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x) __swab16(x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) __swab32(x)
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
- unsigned int sector_number;
- unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
- {4, 32 * 1024}, /* 4 * 32kBytes sectors */
- {255, 128 * 1024}, /* 255 * 128kBytes sectors */
-};
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-void flash_unlock(flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[i]);
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[i]);
- /* to reset the lock bit */
- flash_unlock(&flash_info[i]);
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_unlock(flash_info_t * info)
-{
- int j;
- for (j=2;j<CONFIG_SYS_MAX_FLASH_SECT;j++){
- FPWV *addr = (FPWV *) (info->start[j]);
- flash_unprotect_sectors (addr);
- *addr = (FPW) 0x00500050;/* clear status register */
- *addr = (FPW) 0x00FF00FF;/* resest to read mode */
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- if (i > 255) {
- info->start[i] = base + (i * 0x8000);
- info->protect[i] = 0;
- } else {
- info->start[i] = base +
- (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F256L18T:
- printf ("FLASH 28F256L18T\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
- volatile FPW value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- mb ();
- value = addr[0];
-
- switch (value) {
-
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[1]; /* device ID */
- switch (value) {
-
- case (FPW) (INTEL_ID_28F256L18T):
- info->flash_id += FLASH_28F256L18T;
- info->sector_count = 259;
- info->size = 0x02000000;
- break; /* => 32 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-#define PD_FINTEL_WSMS_READY_MASK 0x0080
-
- *addr = (FPW) 0x00500050; /* clear status register */
-
- /* this sends the clear lock bit command */
- *addr = (FPW) 0x00600060;
- *addr = (FPW) 0x00D000D0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- flash_unprotect_sectors (addr);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- *addr = (FPW) 0x00500050;/* clear status register */
- *addr = (FPW) 0x00200020;/* erase setup */
- *addr = (FPW) 0x00D000D0;/* erase confirm */
-
- while (((status =
- *addr) & (FPW) 0x00800080) !=
- (FPW) 0x00800080) {
- if (get_timer(start) >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- /* suspend erase */
- *addr = (FPW) 0x00B000B0;
- /* reset to read mode */
- *addr = (FPW) 0x00FF00FF;
- rcode = 1;
- break;
- }
- }
-
- /* clear status register cmd. */
- *addr = (FPW) 0x00500050;
- *addr = (FPW) 0x00FF00FF;/* resest to read mode */
- printf (" done\n");
- }
- }
- if (flag)
- enable_interrupts();
-
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- int flag, rc = 0;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf("not erased at %08lx (%x)\n", (ulong) addr, *addr);
- return 2;
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- rc = 1;
- goto done;
- }
- }
-done:
- if (flag)
- enable_interrupts();
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return rc;
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
+++ /dev/null
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#endif
-
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
-
-.globl lowlevel_init
-lowlevel_init:
-
-
- /*------------------------------------------------------*
- *mask all IRQs by setting all bits in the INTMR default*
- *------------------------------------------------------*/
- mov r1, #0xffffffff
- ldr r0, =REG_IHL1_MIR
- str r1, [r0]
- ldr r0, =REG_IHL2_MIR
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT1) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT1
- ldr r1, VAL_ARM_IDLECT1
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT2) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT2
- ldr r1, VAL_ARM_IDLECT2
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT3) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT3
- ldr r1, VAL_ARM_IDLECT3
- str r1, [r0]
-
-#ifdef CONFIG_CS_AUTOBOOT /* do the setup depending on boot mode */
- ldr r0, CONF_STATUS
- ldr r1, [r0]
- tst r1, #0x02
- beq disable_wd /* booting from RAM, skip setup */
-#endif
-
- mov r1, #0x01 /* PER_EN bit */
- ldr r0, REG_ARM_RSTCT2
- strh r1, [r0] /* CLKM; Peripheral reset. */
-
- /* Set CLKM to Sync-Scalable */
- /* I supposedly need to enable the dsp clock before switching */
- mov r1, #0x0000
- ldr r0, REG_ARM_SYSST
- strh r1, [r0]
- mov r0, #0x400
-1:
- subs r0, r0, #0x1 /* wait for any bubbles to finish */
- bne 1b
- ldr r1, VAL_ARM_CKCTL
- ldr r0, REG_ARM_CKCTL
- strh r1, [r0]
-
- /* a few nops to let settle */
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* setup DPLL 1 */
- /* Ramp up the clock to 96Mhz */
- ldr r1, VAL_DPLL1_CTL
- ldr r0, REG_DPLL1_CTL
- strh r1, [r0]
- ands r1, r1, #0x10 /* Check if PLL is enabled. */
- beq lock_end /* Do not look for lock if BYPASS selected */
-2:
- ldrh r1, [r0]
- ands r1, r1, #0x01 /* Check the LOCK bit.*/
- beq 2b /* loop until bit goes hi. */
-lock_end:
-
-
- /*------------------------------------------------------*
- * Turn off the watchdog during init... *
- *------------------------------------------------------*/
-disable_wd:
- ldr r0, REG_WATCHDOG
- ldr r1, WATCHDOG_VAL1
- str r1, [r0]
- ldr r1, WATCHDOG_VAL2
- str r1, [r0]
- ldr r0, REG_WSPRDOG
- ldr r1, WSPRDOG_VAL1
- str r1, [r0]
- ldr r0, REG_WWPSDOG
-
-watch1Wait:
- ldr r1, [r0]
- tst r1, #0x10
- bne watch1Wait
-
- ldr r0, REG_WSPRDOG
- ldr r1, WSPRDOG_VAL2
- str r1, [r0]
- ldr r0, REG_WWPSDOG
-watch2Wait:
- ldr r1, [r0]
- tst r1, #0x10
- bne watch2Wait
-
-
- /* Set memory timings corresponding to the new clock speed */
-
- /* Check execution location to determine current execution location
- * and branch to appropriate initialization code.
- */
- /* Load physical SDRAM base. */
- mov r0, #0x10000000
- /* Get current execution location. */
- mov r1, pc
- /* Compare. */
- cmp r1, r0
- /* Skip over EMIF-fast initialization if running from SDRAM. */
- bge skip_sdram
-
- /*
- * Delay for SDRAM initialization.
- */
- mov r3, #0x1800 /* value should be checked */
-3:
- subs r3, r3, #0x1 /* Decrement count */
- bne 3b
-
-
- /*
- * Set SDRAM control values. Disable refresh before MRS command.
- */
-
- /* mobile ddr operation */
- ldr r0, REG_SDRAM_OPERATION
- mov r2, #07
- str r2, [r0]
-
- /* config register */
- ldr r0, REG_SDRAM_CONFIG
- ldr r1, SDRAM_CONFIG_VAL
- str r1, [r0]
-
- /* manual command register */
- ldr r0, REG_SDRAM_MANUAL_CMD
- /* issue set cke high */
- mov r1, #CMD_SDRAM_CKE_SET_HIGH
- str r1, [r0]
- /* issue nop */
- mov r1, #CMD_SDRAM_NOP
- str r1, [r0]
-
- mov r2, #0x0100
-waitMDDR1:
- subs r2, r2, #1
- bne waitMDDR1 /* delay loop */
-
- /* issue precharge */
- mov r1, #CMD_SDRAM_PRECHARGE
- str r1, [r0]
-
- /* issue autorefresh x 2 */
- mov r1, #CMD_SDRAM_AUTOREFRESH
- str r1, [r0]
- str r1, [r0]
-
- /* mrs register ddr mobile */
- ldr r0, REG_SDRAM_MRS
- mov r1, #0x33
- str r1, [r0]
-
- /* emrs1 low-power register */
- ldr r0, REG_SDRAM_EMRS1
- /* self refresh on all banks */
- mov r1, #0
- str r1, [r0]
-
- ldr r0, REG_DLL_URD_CONTROL
- ldr r1, DLL_URD_CONTROL_VAL
- str r1, [r0]
-
- ldr r0, REG_DLL_LRD_CONTROL
- ldr r1, DLL_LRD_CONTROL_VAL
- str r1, [r0]
-
- ldr r0, REG_DLL_WRT_CONTROL
- ldr r1, DLL_WRT_CONTROL_VAL
- str r1, [r0]
-
- /* delay loop */
- mov r2, #0x0100
-waitMDDR2:
- subs r2, r2, #1
- bne waitMDDR2
-
- /*
- * Delay for SDRAM initialization.
- */
- mov r3, #0x1800
-4:
- subs r3, r3, #1 /* Decrement count. */
- bne 4b
- b common_tc
-
-skip_sdram:
-
- ldr r0, REG_SDRAM_CONFIG
- ldr r1, SDRAM_CONFIG_VAL
- str r1, [r0]
-
-common_tc:
- /* slow interface */
- ldr r1, VAL_TC_EMIFS_CS0_CONFIG
- ldr r0, REG_TC_EMIFS_CS0_CONFIG
- str r1, [r0] /* Chip Select 0 */
-
- ldr r1, VAL_TC_EMIFS_CS1_CONFIG
- ldr r0, REG_TC_EMIFS_CS1_CONFIG
- str r1, [r0] /* Chip Select 1 */
- ldr r1, VAL_TC_EMIFS_CS3_CONFIG
- ldr r0, REG_TC_EMIFS_CS3_CONFIG
- str r1, [r0] /* Chip Select 3 */
-
-#ifdef CONFIG_H2_OMAP1610
- /* inserting additional 2 clock cycle hold time for LAN */
- ldr r0, REG_TC_EMIFS_CS1_ADVANCED
- ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
- str r1, [r0]
-#endif
- /* Start MPU Timer 1 */
- ldr r0, REG_MPU_LOAD_TIMER
- ldr r1, VAL_MPU_LOAD_TIMER
- str r1, [r0]
-
- ldr r0, REG_MPU_CNTL_TIMER
- ldr r1, VAL_MPU_CNTL_TIMER
- str r1, [r0]
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-#ifdef CONFIG_CS_AUTOBOOT
-CONF_STATUS:
- .word 0xfffe1130 /* 32 bits */
-#endif
-
-REG_TC_EMIFS_CONFIG: /* 32 bits */
- .word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
- .word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
- .word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
- .word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
- .word 0xfffecc1c
-
-#ifdef CONFIG_H2_OMAP1610
-REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
- .word 0xfffecc54
-#endif
-
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL: /* 16 bits */
- .word 0xfffece00
-
-REG_ARM_IDLECT3: /* 16 bits */
- .word 0xfffece24
-REG_ARM_IDLECT2: /* 16 bits */
- .word 0xfffece08
-REG_ARM_IDLECT1: /* 16 bits */
- .word 0xfffece04
-
-REG_ARM_RSTCT2: /* 16 bits */
- .word 0xfffece14
-REG_ARM_SYSST: /* 16 bits */
- .word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL: /* 16 bits */
- .word 0xfffecf00
-
-/* Watch Dog register */
-/* secure watchdog stop */
-REG_WSPRDOG:
- .word 0xfffeb048
-/* watchdog write pending */
-REG_WWPSDOG:
- .word 0xfffeb034
-
-WSPRDOG_VAL1:
- .word 0x0000aaaa
-WSPRDOG_VAL2:
- .word 0x00005555
-
-/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
- counter @8192 rows, 10 ns, 8 burst */
-REG_SDRAM_CONFIG:
- .word 0xfffecc20
-
-/* Operation register */
-REG_SDRAM_OPERATION:
- .word 0xfffecc80
-
-/* Manual command register */
-REG_SDRAM_MANUAL_CMD:
- .word 0xfffecc84
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_MRS:
- .word 0xfffecc70
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_EMRS1:
- .word 0xfffecc78
-
-/* WRT DLL register */
-REG_DLL_WRT_CONTROL:
- .word 0xfffecc68
-DLL_WRT_CONTROL_VAL:
- .word 0x03f00002
-
-/* URD DLL register */
-REG_DLL_URD_CONTROL:
- .word 0xfffeccc0
-DLL_URD_CONTROL_VAL:
- .word 0x00800002
-
-/* LRD DLL register */
-REG_DLL_LRD_CONTROL:
- .word 0xfffecccc
-
-REG_WATCHDOG:
- .word 0xfffec808
-
-REG_MPU_LOAD_TIMER:
- .word 0xfffec504
-REG_MPU_CNTL_TIMER:
- .word 0xfffec500
-
-/* 96 MHz Samsung Mobile DDR */
-SDRAM_CONFIG_VAL:
- .word 0x001200f4
-
-DLL_LRD_CONTROL_VAL:
- .word 0x00800002
-
-VAL_ARM_CKCTL:
- .word 0x3000
-VAL_DPLL1_CTL:
- .word 0x2830
-
-#ifdef CONFIG_INNOVATOROMAP1610
-VAL_TC_EMIFS_CS0_CONFIG:
- .word 0x002130b0
-VAL_TC_EMIFS_CS1_CONFIG:
- .word 0x00001131
-VAL_TC_EMIFS_CS2_CONFIG:
- .word 0x000055f0
-VAL_TC_EMIFS_CS3_CONFIG:
- .word 0x88011131
-#endif
-
-#ifdef CONFIG_H2_OMAP1610
-VAL_TC_EMIFS_CS0_CONFIG:
- .word 0x00203331
-VAL_TC_EMIFS_CS1_CONFIG:
- .word 0x8180fff3
-VAL_TC_EMIFS_CS2_CONFIG:
- .word 0xf800f22a
-VAL_TC_EMIFS_CS3_CONFIG:
- .word 0x88011131
-VAL_TC_EMIFS_CS1_ADVANCED:
- .word 0x00000022
-#endif
-
-VAL_TC_EMIFF_SDRAM_CONFIG:
- .word 0x010290fc
-VAL_TC_EMIFF_MRS:
- .word 0x00000027
-
-VAL_ARM_IDLECT1:
- .word 0x00000400
-
-VAL_ARM_IDLECT2:
- .word 0x00000886
-VAL_ARM_IDLECT3:
- .word 0x00000015
-
-WATCHDOG_VAL1:
- .word 0x000000f5
-WATCHDOG_VAL2:
- .word 0x000000a0
-
-VAL_MPU_LOAD_TIMER:
- .word 0xffffffff
-VAL_MPU_CNTL_TIMER:
- .word 0xffffffa1
-
-/* command values */
-.equ CMD_SDRAM_NOP, 0x00000000
-.equ CMD_SDRAM_PRECHARGE, 0x00000001
-.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
-.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CS_AUTOBOOT
-unsigned long omap_flash_base;
-#endif
-
-void flash__init (void);
-void ether__init (void);
-void set_muxconf_regs (void);
-void peripheral_power_enable (void);
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x10000100;
-
- /* Configure MUX settings */
- set_muxconf_regs ();
- peripheral_power_enable ();
-
-/* this speeds up your boot a quite a bit. However to make it
- * work, you need make sure your kernel startup flush bug is fixed.
- * ... rkw ...
- */
- icache_enable ();
-
- flash__init ();
- ether__init ();
- return 0;
-}
-
-
-int misc_init_r (void)
-{
- /* currently empty */
- return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-#define EMIFS_GlB_Config_REG 0xfffecc0c
- unsigned int regval;
-
-#ifdef CONFIG_CS_AUTOBOOT
- /* Check swapping of CS0 and CS3, set flash base accordingly */
- omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
- PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
-#endif
- regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
- /* Turn off write protection for flash devices. */
- regval = regval | 0x0001;
- *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
- for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-#define ETH_CONTROL_REG 0x0400030b
-
-#ifdef CONFIG_H2_OMAP1610
- #define LAN_RESET_REGISTER 0x0400001c
-
- /* The debug board on which the lan chip resides may not be powered
- * ON at the same time as the OMAP chip. So wait in a loop until the
- * lan reset register (on the debug board) is available (powered on)
- * and reset the lan chip.
- */
-
- *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
- do {
- *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
- udelay (3);
- } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
-
- do {
- *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
- udelay (3);
- } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
-#endif
-
- *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
- udelay (3);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-/******************************************************
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers
- specific to the hardware
-*******************************************************/
-void set_muxconf_regs (void)
-{
- volatile unsigned int *MuxConfReg;
- /* set each registers to its reset value; */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
- /* setup for UART1 */
- *MuxConfReg &= ~(0x02000000); /* bit 25 */
- /* setup for UART2 */
- *MuxConfReg &= ~(0x01000000); /* bit 24 */
- /* Disable Uwire CS Hi-Z */
- *MuxConfReg |= 0x08000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
- /*setup mux for UART3 */
- *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */
- *MuxConfReg &= ~0x0000003e;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
- /* Disable Uwire CS Hi-Z */
- *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
- /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
- /* hardware will actually use TX and RTS based on bit 25 in */
- /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
- *MuxConfReg |= 0x00201000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
- /* setup for UART2 */
- /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
- /* hardware will actually use TX and RTS based on bit 24 in */
- /* FUNC_MUX_CTRL_0. */
- *MuxConfReg |= 0x09000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
- *MuxConfReg = 0x00000000;
- /* mux setup for SD/MMC driver */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
- *MuxConfReg &= 0xFFFE0FFF;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
- /* bit 13 for MMC2 XOR_CLK */
- *MuxConfReg &= ~(0x00002000);
- /* bit 29 for UART 1 */
- *MuxConfReg &= ~(0x00002000);
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
- /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
- *MuxConfReg |= 0x000C0000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
- *MuxConfReg &= ~(0x00000070);
- *MuxConfReg &= ~(0x00000008);
- *MuxConfReg |= 0x00000003;
- *MuxConfReg |= 0x00000180;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
- /* bit 17, software controls VBUS */
- *MuxConfReg &= ~(0x00020000);
- /* Enable USB 48 and 12M clocks */
- *MuxConfReg |= 0x00000200;
- *MuxConfReg &= ~(0x00000180);
- /*2.75V for MMCSDIO1 */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
- *MuxConfReg = 0x00001FE7;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
- *MuxConfReg = 0x00000000;
- /* Turn on UART2 48 MHZ clock */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
- *MuxConfReg |= 0x40000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
- /* setup for USB VBus detection OMAP161x */
- *MuxConfReg |= 0x00040000; /* bit 18 */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
- /* PullUps for SD/MMC driver */
- *MuxConfReg |= ~(0xFFFE0FFF);
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
- *MuxConfReg = COMP_MODE_ENABLE;
-}
-
-/******************************************************
- Routine: peripheral_power_enable
- Description: Enable the power for UART1
-*******************************************************/
-void peripheral_power_enable (void)
-{
-#define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
-#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
-
- *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
- return rc;
-}
-#endif
#include <asm/arch/mem.h>
#include <asm/mach-types.h>
#include "devkit8000.h"
+#include <asm/gpio.h>
#ifdef CONFIG_DRIVER_DM9000
#include <net.h>
#include <netdev.h>
return 0;
}
+/* Configure GPMC registers for DM9000 */
+static void gpmc_dm9000_config(void)
+{
+ enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
+ CONFIG_DM9000_BASE, GPMC_SIZE_16M);
+}
+
/*
* Routine: misc_init_r
* Description: Configure board specific parts
}
#endif
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * Do board specific preperation before SPL
+ * Linux boot
+ */
+void spl_board_prepare_for_linux(void)
+{
+ gpmc_dm9000_config();
+}
+
+/*
+ * devkit8000 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if the button is not pressed
+ * 1 if the button is pressed
+ */
+int spl_start_uboot(void)
+{
+ int val = 0;
+ if (!gpio_request(CONFIG_SPL_OS_BOOT_KEY, "U-Boot key")) {
+ gpio_direction_input(CONFIG_SPL_OS_BOOT_KEY);
+ val = gpio_get_value(CONFIG_SPL_OS_BOOT_KEY);
+ gpio_free(CONFIG_SPL_OS_BOOT_KEY);
+ }
+ return !val;
+}
+#endif
+
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
for (;;)
;
}
-
-void icache_disable(void) {}
-void dcache_disable(void) {}
#include <serial.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
#include <spi.h>
#include <asm/io.h>
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
#ifdef CONFIG_CMD_SPI
struct {
mx28evk arm arm926ejs - freescale mx28
nhk8815 arm arm926ejs nhk8815 st nomadik
nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
-omap1610h2 arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT
-omap1610h2_cs0boot arm arm926ejs omap1610inn ti omap omap1610inn:CS0_BOOT
-omap1610h2_cs3boot arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT
-omap1610h2_cs_autoboot arm arm926ejs omap1610inn ti omap omap1610inn:CS_AUTOBOOT
-omap1610inn arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT
-omap1610inn_cs0boot arm arm926ejs omap1610inn ti omap omap1610inn:CS0_BOOT
-omap1610inn_cs3boot arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT
-omap1610inn_cs_autoboot arm arm926ejs omap1610inn ti omap omap1610inn:CS_AUTOBOOT
omap5912osk arm arm926ejs - ti omap
omap730p2 arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT
omap730p2_cs0boot arm arm926ejs omap730p2 ti omap omap730p2:CS0_BOOT
actux3 arm ixp
actux4 arm ixp
dvlhost arm ixp
+pdnb3 arm ixp pdnb3 prodrive
+scpu arm ixp pdnb3 prodrive - pdnb3:SCPU
balloon3 arm pxa
lubbock arm pxa
palmld arm pxa
COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
COBJS-$(CONFIG_ENV_IS_IN_MG_DISK) += env_mgdisk.o
COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+COBJS-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
endif
COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
+COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o
# others
ifdef CONFIG_DDR_SPD
COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
endif
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
+endif
COBJS-y += console.o
COBJS-y += dlmalloc.o
COBJS-y += memsize.o
#define IH_INITRD_ARCH IH_ARCH_DEFAULT
-static void bootm_start_lmb(void)
-{
#ifdef CONFIG_LMB
+static void boot_start_lmb(bootm_headers_t *images)
+{
ulong mem_start;
phys_size_t mem_size;
- lmb_init(&images.lmb);
+ lmb_init(&images->lmb);
mem_start = getenv_bootm_low();
mem_size = getenv_bootm_size();
- lmb_add(&images.lmb, (phys_addr_t)mem_start, mem_size);
+ lmb_add(&images->lmb, (phys_addr_t)mem_start, mem_size);
- arch_lmb_reserve(&images.lmb);
- board_lmb_reserve(&images.lmb);
+ arch_lmb_reserve(&images->lmb);
+ board_lmb_reserve(&images->lmb);
+}
#else
-# define lmb_reserve(lmb, base, size)
+static inline void boot_start_lmb(bootm_headers_t *images) { }
#endif
-}
static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
memset((void *)&images, 0, sizeof(images));
images.verify = getenv_yesno("verify");
- bootm_start_lmb();
+ boot_start_lmb(&images);
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_START, "bootm_start");
return 1;
}
#endif
+
+#ifdef CONFIG_CMD_BOOTZ
+
+static int __bootz_setup(void *image, void **start, void **end)
+{
+ /* Please define bootz_setup() for your platform */
+
+ puts("Your platform's zImage format isn't supported yet!\n");
+ return -1;
+}
+int bootz_setup(void *image, void **start, void **end)
+ __attribute__((weak, alias("__bootz_setup")));
+
+/*
+ * zImage booting support
+ */
+static int bootz_start(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[], bootm_headers_t *images)
+{
+ int ret;
+ void *zi_start, *zi_end;
+
+ memset(images, 0, sizeof(bootm_headers_t));
+
+ boot_start_lmb(images);
+
+ /* Setup Linux kernel zImage entry point */
+ if (argc < 2) {
+ images->ep = load_addr;
+ debug("* kernel: default image load address = 0x%08lx\n",
+ load_addr);
+ } else {
+ images->ep = simple_strtoul(argv[1], NULL, 16);
+ debug("* kernel: cmdline image address = 0x%08lx\n",
+ images->ep);
+ }
+
+ ret = bootz_setup((void *)images->ep, &zi_start, &zi_end);
+ if (ret != 0)
+ return 1;
+
+ lmb_reserve(&images->lmb, images->ep, zi_end - zi_start);
+
+ /* Find ramdisk */
+ ret = boot_get_ramdisk(argc, argv, images, IH_INITRD_ARCH,
+ &images->rd_start, &images->rd_end);
+ if (ret) {
+ puts("Ramdisk image is corrupt or invalid\n");
+ return 1;
+ }
+
+#if defined(CONFIG_OF_LIBFDT)
+ /* find flattened device tree */
+ ret = boot_get_fdt(flag, argc, argv, images,
+ &images->ft_addr, &images->ft_len);
+ if (ret) {
+ puts("Could not find a valid device tree\n");
+ return 1;
+ }
+
+ set_working_fdt_addr(images->ft_addr);
+#endif
+
+ return 0;
+}
+
+static int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong iflag;
+ bootm_headers_t images;
+
+ if (bootz_start(cmdtp, flag, argc, argv, &images))
+ return 1;
+
+ /*
+ * We have reached the point of no return: we are going to
+ * overwrite all exception vector code, so we cannot easily
+ * recover from any failures any more...
+ */
+ iflag = disable_interrupts();
+
+#if defined(CONFIG_CMD_USB)
+ /*
+ * turn off USB to prevent the host controller from writing to the
+ * SDRAM while Linux is booting. This could happen (at least for OHCI
+ * controller), because the HCCA (Host Controller Communication Area)
+ * lies within the SDRAM and the host controller writes continously to
+ * this area (as busmaster!). The HccaFrameNumber is for example
+ * updated every 1 ms within the HCCA structure in SDRAM! For more
+ * details see the OpenHCI specification.
+ */
+ usb_stop();
+#endif
+
+#ifdef CONFIG_SILENT_CONSOLE
+ fixup_silent_linux();
+#endif
+ arch_preboot_os();
+
+ do_bootm_linux(0, argc, argv, &images);
+#ifdef DEBUG
+ puts("\n## Control returned to monitor - resetting...\n");
+#endif
+ do_reset(cmdtp, flag, argc, argv);
+
+ return 1;
+}
+
+U_BOOT_CMD(
+ bootz, CONFIG_SYS_MAXARGS, 1, do_bootz,
+ "boot Linux zImage image from memory",
+ "[addr [initrd[:size]] [fdt]]\n"
+ " - boot Linux zImage stored in memory\n"
+ "\tThe argument 'initrd' is optional and specifies the address\n"
+ "\tof the initrd in memory. The optional argument ':size' allows\n"
+ "\tspecifying the size of RAW initrd.\n"
+#if defined(CONFIG_OF_LIBFDT)
+ "\tWhen booting a Linux kernel which requires a flat device-tree\n"
+ "\ta third argument is required which is the address of the\n"
+ "\tdevice-tree blob. To boot that kernel without an initrd image,\n"
+ "\tuse a '-' for the second argument. If you do not pass a third\n"
+ "\ta bd_info struct will be passed instead\n"
+#endif
+);
+#endif /* CONFIG_CMD_BOOTZ */
"<interface> <dev[:part]>\n"
" - print information about filesystem from 'dev' on 'interface'"
);
+
+#ifdef CONFIG_FAT_WRITE
+static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ long size;
+ unsigned long addr;
+ unsigned long count;
+ block_dev_desc_t *dev_desc = NULL;
+ int dev = 0;
+ int part = 1;
+ char *ep;
+
+ if (argc < 5)
+ return cmd_usage(cmdtp);
+
+ dev = (int)simple_strtoul(argv[2], &ep, 16);
+ dev_desc = get_dev(argv[1], dev);
+ if (dev_desc == NULL) {
+ puts("\n** Invalid boot device **\n");
+ return 1;
+ }
+ if (*ep) {
+ if (*ep != ':') {
+ puts("\n** Invalid boot device, use `dev[:part]' **\n");
+ return 1;
+ }
+ part = (int)simple_strtoul(++ep, NULL, 16);
+ }
+ if (fat_register_device(dev_desc, part) != 0) {
+ printf("\n** Unable to use %s %d:%d for fatwrite **\n",
+ argv[1], dev, part);
+ return 1;
+ }
+ addr = simple_strtoul(argv[3], NULL, 16);
+ count = simple_strtoul(argv[5], NULL, 16);
+
+ size = file_fat_write(argv[4], (void *)addr, count);
+ if (size == -1) {
+ printf("\n** Unable to write \"%s\" from %s %d:%d **\n",
+ argv[4], argv[1], dev, part);
+ return 1;
+ }
+
+ printf("%ld bytes written\n", size);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ fatwrite, 6, 0, do_fat_fswrite,
+ "write file into a dos filesystem",
+ "<interface> <dev[:part]> <addr> <filename> <bytes>\n"
+ " - write file 'filename' from the address 'addr' in RAM\n"
+ " to 'dev' on 'interface'"
+);
+#endif
DECLARE_GLOBAL_DATA_PTR;
/* Local prototypes */
-static void logbuff_putc (const char c);
-static void logbuff_puts (const char *s);
+static void logbuff_putc(const char c);
+static void logbuff_puts(const char *s);
static int logbuff_printk(const char *line);
static char buf[1024];
{
return CONFIG_SYS_SDRAM_BASE + gd->ram_size - LOGBUFF_LEN;
}
-unsigned long logbuffer_base (void) __attribute__((weak, alias("__logbuffer_base")));
+unsigned long logbuffer_base(void)
+__attribute__((weak, alias("__logbuffer_base")));
-void logbuff_init_ptrs (void)
+void logbuff_init_ptrs(void)
{
unsigned long tag, post_word;
char *s;
log = (logbuff_t *)CONFIG_ALT_LH_ADDR;
lbuf = (char *)CONFIG_ALT_LB_ADDR;
#else
- log = (logbuff_t *)(logbuffer_base ()) - 1;
+ log = (logbuff_t *)(logbuffer_base()) - 1;
lbuf = (char *)log->buf;
#endif
/* Set up log version */
if ((s = getenv ("logversion")) != NULL)
- log_version = (int)simple_strtoul (s, NULL, 10);
+ log_version = (int)simple_strtoul(s, NULL, 10);
if (log_version == 2)
tag = log->v2.tag;
post_word = post_word_load();
#ifdef CONFIG_POST
/* The post routines have setup the word so we can simply test it */
- if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) {
- logbuff_reset ();
- }
+ if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT))
+ logbuff_reset();
#else
/* No post routines, so we do our own checking */
if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) {
/* Initialize default loglevel if present */
if ((s = getenv ("loglevel")) != NULL)
- console_loglevel = (int)simple_strtoul (s, NULL, 10);
+ console_loglevel = (int)simple_strtoul(s, NULL, 10);
gd->flags |= GD_FLG_LOGINIT;
}
-void logbuff_reset (void)
+void logbuff_reset(void)
{
#ifndef CONFIG_ALT_LB_ADDR
- memset (log, 0, sizeof (logbuff_t));
+ memset(log, 0, sizeof(logbuff_t));
#endif
if (log_version == 2) {
log->v2.tag = LOGBUFF_MAGIC;
}
}
-int drv_logbuff_init (void)
+int drv_logbuff_init(void)
{
struct stdio_dev logdev;
int rc;
logdev.putc = logbuff_putc; /* 'putc' function */
logdev.puts = logbuff_puts; /* 'puts' function */
- rc = stdio_register (&logdev);
+ rc = stdio_register(&logdev);
return (rc == 0) ? 1 : rc;
}
-static void logbuff_putc (const char c)
+static void logbuff_putc(const char c)
{
char buf[2];
buf[0] = c;
buf[1] = '\0';
- logbuff_printk (buf);
+ logbuff_printk(buf);
}
-static void logbuff_puts (const char *s)
+static void logbuff_puts(const char *s)
{
logbuff_printk (s);
}
void logbuff_log(char *msg)
{
if ((gd->flags & GD_FLG_LOGINIT)) {
- logbuff_printk (msg);
+ logbuff_printk(msg);
} else {
- /* Can happen only for pre-relocated errors as logging */
- /* at that stage should be disabled */
+ /*
+ * Can happen only for pre-relocated errors as logging
+ * at that stage should be disabled
+ */
puts (msg);
}
}
* Return: None
*
*/
-int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *s;
unsigned long i, start, size;
- if (strcmp(argv[1],"append") == 0) {
+ if (strcmp(argv[1], "append") == 0) {
/* Log concatenation of all arguments separated by spaces */
- for (i=2; i<argc; i++) {
- logbuff_printk (argv[i]);
- logbuff_putc ((i<argc-1) ? ' ' : '\n');
+ for (i = 2; i < argc; i++) {
+ logbuff_printk(argv[i]);
+ logbuff_putc((i < argc - 1) ? ' ' : '\n');
}
return 0;
}
switch (argc) {
case 2:
- if (strcmp(argv[1],"show") == 0) {
+ if (strcmp(argv[1], "show") == 0) {
if (log_version == 2) {
start = log->v2.start;
size = log->v2.end - log->v2.start;
- }
- else {
+ } else {
start = log->v1.start;
size = log->v1.size;
}
- for (i=0; i < (size&LOGBUFF_MASK); i++) {
- s = lbuf+((start+i)&LOGBUFF_MASK);
- putc (*s);
+ if (size > LOGBUFF_LEN)
+ size = LOGBUFF_LEN;
+ for (i = 0; i < size; i++) {
+ s = lbuf + ((start + i) & LOGBUFF_MASK);
+ putc(*s);
}
return 0;
- } else if (strcmp(argv[1],"reset") == 0) {
- logbuff_reset ();
+ } else if (strcmp(argv[1], "reset") == 0) {
+ logbuff_reset();
return 0;
- } else if (strcmp(argv[1],"info") == 0) {
- printf ("Logbuffer at %08lx\n", (unsigned long)lbuf);
+ } else if (strcmp(argv[1], "info") == 0) {
+ printf("Logbuffer at %08lx\n", (unsigned long)lbuf);
if (log_version == 2) {
- printf ("log_start = %08lx\n", log->v2.start);
- printf ("log_end = %08lx\n", log->v2.end);
- printf ("logged_chars = %08lx\n", log->v2.chars);
+ printf("log_start = %08lx\n",
+ log->v2.start);
+ printf("log_end = %08lx\n", log->v2.end);
+ printf("log_con = %08lx\n", log->v2.con);
+ printf("logged_chars = %08lx\n",
+ log->v2.chars);
}
else {
- printf ("log_start = %08lx\n", log->v1.start);
- printf ("log_size = %08lx\n", log->v1.size);
- printf ("logged_chars = %08lx\n", log->v1.chars);
+ printf("log_start = %08lx\n",
+ log->v1.start);
+ printf("log_size = %08lx\n",
+ log->v1.size);
+ printf("logged_chars = %08lx\n",
+ log->v1.chars);
}
return 0;
}
int line_feed;
static signed char msg_level = -1;
- strcpy (buf + 3, line);
- i = strlen (line);
+ strcpy(buf + 3, line);
+ i = strlen(line);
buf_end = buf + 3 + i;
for (p = buf + 3; p < buf_end; p++) {
msg = p;
p[0] = '<';
p[1] = default_message_loglevel + '0';
p[2] = '>';
- } else
+ } else {
msg += 3;
+ }
msg_level = p[1] - '0';
}
line_feed = 0;
if (log->v2.end - log->v2.start > LOGBUFF_LEN)
log->v2.start++;
log->v2.chars++;
- }
- else {
+ } else {
lbuf[(log->v1.start + log->v1.size) &
LOGBUFF_MASK] = *p;
if (log->v1.size < LOGBUFF_LEN)
!defined(CONFIG_ENV_IS_IN_DATAFLASH) && \
!defined(CONFIG_ENV_IS_IN_MG_DISK) && \
!defined(CONFIG_ENV_IS_IN_MMC) && \
+ !defined(CONFIG_ENV_IS_IN_FAT) && \
!defined(CONFIG_ENV_IS_IN_NAND) && \
!defined(CONFIG_ENV_IS_IN_NVRAM) && \
!defined(CONFIG_ENV_IS_IN_ONENAND) && \
!defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \
!defined(CONFIG_ENV_IS_NOWHERE)
# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|MG_DISK|NVRAM|MMC} or CONFIG_ENV_IS_NOWHERE
+SPI_FLASH|MG_DISK|NVRAM|MMC|FAT} or CONFIG_ENV_IS_NOWHERE
#endif
#define XMK_STR(x) #x
do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *pxefile_addr_str;
- void *pxefile_addr_r;
+ unsigned long pxefile_addr_r;
int err;
if (argc != 1)
* Keep trying paths until we successfully get a file we're looking
* for.
*/
- if (pxe_uuid_path(pxefile_addr_r) > 0
- || pxe_mac_path(pxefile_addr_r) > 0
- || pxe_ipaddr_paths(pxefile_addr_r) > 0
- || get_pxelinux_path("default", pxefile_addr_r) > 0) {
+ if (pxe_uuid_path((void *)pxefile_addr_r) > 0
+ || pxe_mac_path((void *)pxefile_addr_r) > 0
+ || pxe_ipaddr_paths((void *)pxefile_addr_r) > 0
+ || get_pxelinux_path("default", (void *)pxefile_addr_r) > 0) {
printf("Config file found\n");
*/
static int get_relfile_envaddr(char *file_path, char *envaddr_name)
{
- void *file_addr;
+ unsigned long file_addr;
char *envaddr;
envaddr = from_env(envaddr_name);
if (!envaddr)
return -ENOENT;
- if (strict_strtoul(envaddr, 16, (unsigned long *)&file_addr) < 0)
+ if (strict_strtoul(envaddr, 16, &file_addr) < 0)
return -EINVAL;
- return get_relfile(file_path, file_addr);
+ return get_relfile(file_path, (void *)file_addr);
}
/*
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cmd_spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char **subcmd_list[] = {
+
+ [SPL_EXPORT_FDT] = (const char * []) {
+#ifdef CONFIG_OF_LIBFDT
+ "start",
+ "loados",
+ #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+ "ramdisk",
+ #endif
+ "fdt",
+ "cmdline",
+ "bdt",
+ "prep",
+#endif
+ NULL,
+ },
+ [SPL_EXPORT_ATAGS] = (const char * []) {
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+ "start",
+ "loados",
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+ "ramdisk",
+#endif
+ "cmdline",
+ "bdt",
+ "prep",
+#endif
+ NULL,
+ },
+ NULL
+};
+
+/* Calls bootm with the parameters given */
+static int call_bootm(int argc, char * const argv[], const char *subcommand[])
+{
+ char *bootm_argv[5];
+
+ int i = 0;
+ int ret = 0;
+ int j;
+
+ /* create paramter array */
+ bootm_argv[0] = "do_bootm";
+ switch (argc) {
+ case 3:
+ bootm_argv[4] = argv[2]; /* fdt addr */
+ case 2:
+ bootm_argv[3] = argv[1]; /* initrd addr */
+ case 1:
+ bootm_argv[2] = argv[0]; /* kernel addr */
+ }
+
+
+ /*
+ * - do the work -
+ * exec subcommands of do_bootm to init the images
+ * data structure
+ */
+ while (subcommand[i] != NULL) {
+ bootm_argv[1] = (char *)subcommand[i];
+ debug("args %d: %s %s ", argc, bootm_argv[0], bootm_argv[1]);
+ for (j = 0; j < argc; j++)
+ debug("%s ", bootm_argv[j + 2]);
+ debug("\n");
+
+ ret = do_bootm(find_cmd("do_bootm"), 0, argc+2,
+ bootm_argv);
+ debug("Subcommand retcode: %d\n", ret);
+ i++;
+ }
+
+ if (ret) {
+ printf("ERROR prep subcommand failed!\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static cmd_tbl_t cmd_spl_export_sub[] = {
+ U_BOOT_CMD_MKENT(fdt, 0, 1, (void *)SPL_EXPORT_FDT, "", ""),
+ U_BOOT_CMD_MKENT(atags, 0, 1, (void *)SPL_EXPORT_ATAGS, "", ""),
+};
+
+static int spl_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const cmd_tbl_t *c;
+
+ if (argc < 2) /* no subcommand */
+ return cmd_usage(cmdtp);
+
+ c = find_cmd_tbl(argv[1], &cmd_spl_export_sub[0],
+ ARRAY_SIZE(cmd_spl_export_sub));
+ if ((c) && ((int)c->cmd <= SPL_EXPORT_LAST)) {
+ argc -= 2;
+ argv += 2;
+ if (call_bootm(argc, argv, subcmd_list[(int)c->cmd]))
+ return -1;
+ switch ((int)c->cmd) {
+ case SPL_EXPORT_FDT:
+ printf("Argument image is now in RAM: 0x%p\n",
+ (void *)images.ft_addr);
+ break;
+ case SPL_EXPORT_ATAGS:
+ printf("Argument image is now in RAM at: 0x%p\n",
+ (void *)gd->bd->bi_boot_params);
+ break;
+ }
+ } else {
+ /* Unrecognized command */
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+static cmd_tbl_t cmd_spl_sub[] = {
+ U_BOOT_CMD_MKENT(export, 0, 1, (void *)SPL_EXPORT, "", ""),
+};
+
+static int do_spl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const cmd_tbl_t *c;
+ int cmd;
+
+ if (argc < 2) /* no subcommand */
+ return cmd_usage(cmdtp);
+
+ c = find_cmd_tbl(argv[1], &cmd_spl_sub[0], ARRAY_SIZE(cmd_spl_sub));
+ if (c) {
+ cmd = (int)c->cmd;
+ switch (cmd) {
+ case SPL_EXPORT:
+ argc--;
+ argv++;
+ if (spl_export(cmdtp, flag, argc, argv))
+ printf("Subcommand failed\n");
+ break;
+ default:
+ /* unrecognized command */
+ return cmd_usage(cmdtp);
+ }
+ } else {
+ /* Unrecognized command */
+ return cmd_usage(cmdtp);
+ }
+ return 0;
+}
+
+U_BOOT_CMD(
+ spl, 6 , 1, do_spl, "SPL configuration",
+ "export <img=atags|fdt> [kernel_addr] [initrd_addr] "
+ "[fdt_addr if <img> = fdt] - export a kernel parameter image\n"
+ "\t initrd_img can be set to \"-\" if fdt_addr without initrd img is"
+ "used");
--- /dev/null
+/*
+ * (c) Copyright 2011 by Tigris Elektronik GmbH
+ *
+ * Author:
+ * Maximilian Schwerin <mvs@tigris.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+#include <search.h>
+#include <errno.h>
+#include <fat.h>
+#include <mmc.h>
+
+char *env_name_spec = "FAT";
+
+env_t *env_ptr;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+uchar env_get_char_spec(int index)
+{
+ return *((uchar *)(gd->env_addr + index));
+}
+
+int env_init(void)
+{
+ /* use default */
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_SAVEENV
+int saveenv(void)
+{
+ env_t env_new;
+ ssize_t len;
+ char *res;
+ block_dev_desc_t *dev_desc = NULL;
+ int dev = FAT_ENV_DEVICE;
+ int part = FAT_ENV_PART;
+
+ res = (char *)&env_new.data;
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
+ if (len < 0) {
+ error("Cannot export environment: errno = %d\n", errno);
+ return 1;
+ }
+
+#ifdef CONFIG_MMC
+ if (strcmp (FAT_ENV_INTERFACE, "mmc") == 0) {
+ struct mmc *mmc = find_mmc_device(dev);
+
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", dev);
+ return 1;
+ }
+
+ mmc->has_init = 0;
+ mmc_init(mmc);
+ }
+#endif /* CONFIG_MMC */
+
+ dev_desc = get_dev(FAT_ENV_INTERFACE, dev);
+ if (dev_desc == NULL) {
+ printf("Failed to find %s%d\n",
+ FAT_ENV_INTERFACE, dev);
+ return 1;
+ }
+ if (fat_register_device(dev_desc, part) != 0) {
+ printf("Failed to register %s%d:%d\n",
+ FAT_ENV_INTERFACE, dev, part);
+ return 1;
+ }
+
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ if (file_fat_write(FAT_ENV_FILE, (void *)&env_new, sizeof(env_t)) == -1) {
+ printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
+ FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part);
+ return 1;
+ }
+
+ puts("done\n");
+ return 0;
+}
+#endif /* CONFIG_CMD_SAVEENV */
+
+void env_relocate_spec(void)
+{
+ char buf[CONFIG_ENV_SIZE];
+ block_dev_desc_t *dev_desc = NULL;
+ int dev = FAT_ENV_DEVICE;
+ int part = FAT_ENV_PART;
+
+#ifdef CONFIG_MMC
+ if (strcmp (FAT_ENV_INTERFACE, "mmc") == 0) {
+ struct mmc *mmc = find_mmc_device(dev);
+
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", dev);
+ set_default_env(NULL);
+ return;
+ }
+
+ mmc->has_init = 0;
+ mmc_init(mmc);
+ }
+#endif /* CONFIG_MMC */
+
+ dev_desc = get_dev(FAT_ENV_INTERFACE, dev);
+ if (dev_desc == NULL) {
+ printf("Failed to find %s%d\n",
+ FAT_ENV_INTERFACE, dev);
+ set_default_env(NULL);
+ return;
+ }
+ if (fat_register_device(dev_desc, part) != 0) {
+ printf("Failed to register %s%d:%d\n",
+ FAT_ENV_INTERFACE, dev, part);
+ set_default_env(NULL);
+ return;
+ }
+
+ if (file_fat_read(FAT_ENV_FILE, (unsigned char *)&buf, CONFIG_ENV_SIZE) == -1) {
+ printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
+ FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part);
+ set_default_env(NULL);
+ return;
+ }
+
+ env_import(buf, 1);
+}
ulong rd_addr, rd_load;
ulong rd_data, rd_len;
const image_header_t *rd_hdr;
+#ifdef CONFIG_SUPPORT_RAW_INITRD
+ char *end;
+#endif
#if defined(CONFIG_FIT)
void *fit_hdr;
const char *fit_uname_config = NULL;
break;
#endif
default:
- puts("Wrong Ramdisk Image Format\n");
- rd_data = rd_len = rd_load = 0;
- return 1;
+#ifdef CONFIG_SUPPORT_RAW_INITRD
+ if (argc >= 3 && (end = strchr(argv[2], ':'))) {
+ rd_len = simple_strtoul(++end, NULL, 16);
+ rd_data = rd_addr;
+ } else
+#endif
+ {
+ puts("Wrong Ramdisk Image Format\n");
+ rd_data = rd_len = rd_load = 0;
+ return 1;
+ }
}
} else if (images->legacy_hdr_valid &&
image_check_type(&images->legacy_hdr_os_copy,
# only supported compiler options are used
#
CC_OPTIONS_CACHE_FILE := $(OBJTREE)/include/generated/cc_options.mk
-
-$(if $(wildcard $(CC_OPTIONS_CACHE_FILE)),,\
- $(shell mkdir -p $(dir $(CC_OPTIONS_CACHE_FILE))))
+CC_TEST_OFILE := $(OBJTREE)/include/generated/cc_test_file.o
-include $(CC_OPTIONS_CACHE_FILE)
-cc-option-sys = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \
+cc-option-sys = $(shell mkdir -p $(dir $(CC_TEST_OFILE)); \
+ if $(CC) $(CFLAGS) $(1) -S -xc /dev/null -o $(CC_TEST_OFILE) \
> /dev/null 2>&1; then \
echo 'CC_OPTIONS += $(strip $1)' >> $(CC_OPTIONS_CACHE_FILE); \
echo "$(1)"; fi)
$(call cc-option,-Wno-format-security)
CFLAGS += $(CFLAGS_WARN)
+# Report stack usage if supported
+CFLAGS_STACK := $(call cc-option,-fstack-usage)
+CFLAGS += $(CFLAGS_STACK)
+
# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
# option to the assembler.
AFLAGS_DEBUG :=
block_dev_desc_t* (*reloc_get_dev)(int dev);
char *name;
+ if (!ifname)
+ return NULL;
+
name = drvr->name;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
name += gd->reloc_off;
PORTMUX_DIR_OUTPUT
PORTMUX_DIR_INPUT
-These mutually-exlusive flags configure the initial direction of the
+These mutually-exclusive flags configure the initial direction of the
pins. PORTMUX_DIR_OUTPUT means that the pins are driven by the CPU,
while PORTMUX_DIR_INPUT means that the pins are tristated by the CPU.
These flags are ignored by portmux_select_peripheral().
PORTMUX_DRIVE_HIGH
PORTMUX_DRIVE_MAX
-These mutually-exlusive flags determine the drive strength of the
+These mutually-exclusive flags determine the drive strength of the
pins. PORTMUX_DRIVE_MIN will give low power-consumption, but may cause
corruption of high-speed signals. PORTMUX_DRIVE_MAX will give high
power-consumption, but may be necessary on pins toggling at very high
+++ /dev/null
-
-These are brief instructions on how to add support for CF adapters to
-custom designed PXA boards. You need to set the parameters in the
-config file. This should work for most implementations especially if you
-follow the connections of the standard lubbock. Anyway just the block
-marked memory configuration should be touched since the other parameters
-are imposed by the PXA architecture.
-
-EDIT 2010-07-01: in common/cmd_ide.c, having CONFIG_PXA_PCMCIA defined
-would cause looping on inw()/outw() rather than using insw()/outsw(),
-thus making sure IDE / ATA bytes are properly swapped. This behaviour
-is now controlled by CONFIG_IDE_SWAP_IO, therefore PXA boards with
-PCMCIA should #define CONFIG_IDE_SWAP_IO.
-
-#define CONFIG_IDE_SWAP_IO
-
-#define CONFIG_PXA_PCMCIA 1
-#define CONFIG_PXA_IDE 1
-
-#define CONFIG_PCMCIA_SLOT_A 1
-/* just to keep build system happy */
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x28000000
-#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000000
-
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00004204
-#define CONFIG_SYS_MCMEM1_VAL 0x00000000
-#define CONFIG_SYS_MCATT0_VAL 0x00010504
-#define CONFIG_SYS_MCATT1_VAL 0x00000000
-#define CONFIG_SYS_MCIO0_VAL 0x00008407
-#define CONFIG_SYS_MCIO1_VAL 0x00000000
-/* memory configuration */
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-/* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-/* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x1f0
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x1f0
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x3f0
-
-
-Another important point is that maybe you have to power the pcmcia
-subsystem. This is very board specific, for an example on how to
-do it please search for CONFIG_EXADRON1 in cmd_pcmcia.c
parameter of server's IP address or environment variable
"ntpserverip". The network time is sent as UTC. So if you want to
set local time to RTC, set the offset in second from UTC to the
-enviroment variable "time offset".
+environment variable "time offset".
If the DHCP server provides time server's IP or time offset, you
don't need to set the above environment variables yourself.
=> setenv serverip 192.168.0.10
=> setenv gatewayip=192.168.0.1
=> saveenv
-Saving Enviroment to Flash...
+Saving Environment to Flash...
Un-Protected 1 sectors
Erasing Flash...
done
=> cp.b 0x100000 FFF00000 1f28c
Copy to Flash... done
=> saveenv
-Saving Enviroment to Flash...
+Saving Environment to Flash...
Un-Protected 1 sectors
Erasing Flash...
done
done
Erased 7 sectors
Copy to Flash... done
-Saving Enviroment to Flash...
+Saving Environment to Flash...
Un-Protected 1 sectors
Erasing Flash...
done
U-Boot environment variables can be stored at different places:
- Dataflash on SPI chip select 0 (dataflash card)
- Nand flash.
- - Nor falsh (not populate by default)
+ - Nor flash (not populate by default)
You can choose your storage location at config step (here for at91sam9260ek) :
make at91sam9263ek_config - use data flash (spi cs0) (default)
make at91sam9263ek_nandflash_config - use nand flash
make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
- make at91sam9263ek_norflash_config - use nor falsh
+ make at91sam9263ek_norflash_config - use nor flash
You can choose to boot directly from U-Boot at config step
- make at91sam9263ek_norflash_boot_config - boot from nor falsh
+ make at91sam9263ek_norflash_boot_config - boot from nor flash
------------------------------------------------------------------------------
--- /dev/null
+The spl command is used to export a boot parameter image to RAM. Later
+it may implement more functions connected to the SPL.
+
+SUBCOMMAND EXPORT
+To execute the command everything has to be in place as if bootm should be
+used. (kernel image, initrd-image, fdt-image etc.)
+
+export has two subcommands:
+ atags: exports the ATAGS
+ fdt: exports the FDT
+
+Call is:
+spl export <ftd|atags> [kernel_addr] [initrd_addr] [fdt_addr if fdt]
+
+
+TYPICAL CALL
+
+on OMAP3:
+nandecc hw
+nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
+spl export atags /* export ATAGS */
+nand erase 0x680000 0x20000 /* erase - one page */
+nand write 0x80000100 0x680000 0x20000 /* write the image - one page */
+
+call with FDT:
+nandecc hw
+nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
+tftpboot 0x80000100 devkit8000.dtb /* Read fdt */
+spl export fdt 0x82000000 - 0x80000100 /* export FDT */
+nand erase 0x680000 0x20000 /* erase - one page */
+nand write <adress shown by spl export> 0x680000 0x20000
=======================================================================
This file contains some handy info regarding U-Boot and the AMCC
-Ebony evalutation board. See the README.ppc440 for additional
+Ebony evaluation board. See the README.ppc440 for additional
information.
c<n> - the controller number, eg. c0, c1
d<n> - the DIMM number, eg. d0, d1
spd - print SPD data
- dimmparms - DIMM paramaters, calcualted from SPD
+ dimmparms - DIMM parameters, calculated from SPD
commonparms - lowest common parameters for all DIMMs
opts - options
addresses - address assignment (not implemented yet)
c<n> - the controller number, eg. c0, c1
d<n> - the DIMM number, eg. d0, d1
spd - print SPD data
- dimmparms - DIMM paramaters, calcualted from SPD
+ dimmparms - DIMM parameters, calculated from SPD
commonparms - lowest common parameters for all DIMMs
opts - options
addresses - address assignment (not implemented yet)
"On" == 0
SW3 is switch 18 as silk-screened onto the board.
- SW4[8] is the bit labled 8 on Switch 4.
+ SW4[8] is the bit labeled 8 on Switch 4.
SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
"On" == 0
SW18 is switch 18 as silk-screened onto the board.
- SW4[8] is the bit labled 8 on Switch 4.
+ SW4[8] is the bit labeled 8 on Switch 4.
SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
"Off" == 1
"On" == 0
- SW4[8] is the bit labled 8 on Switch 4.
+ SW4[8] is the bit labeled 8 on Switch 4.
SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
and bits labeled 8 is set as "Off".
Memory Map
----------
-0xff80_0000 - 0xffbf_ffff Alernate bank 4MB
+0xff80_0000 - 0xffbf_ffff Alternate bank 4MB
0xffc0_0000 - 0xffff_ffff Boot bank 4MB
0xffb8_0000 Alternate image start 512KB
Memory Map
----------
-0xe800_0000 - 0xebff_ffff Alernate bank 64MB
+0xe800_0000 - 0xebff_ffff Alternate bank 64MB
0xec00_0000 - 0xefff_ffff Boot bank 64MB
0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB
- Select "Advanced setup" -> " Prompt for advanced kernel
configuration options"
- Select "Set physical address where the kernel is loaded" and
- set it to 0x20000000, asssuming core1 will start from 512MB.
+ set it to 0x20000000, assuming core1 will start from 512MB.
- Select "Set custom page offset address"
- Select "Set custom kernel base address"
- Select "Set maximum low memory"
"On" == 0
SW18 is switch 18 as silk-screened onto the board.
- SW4[8] is the bit labled 8 on Switch 4.
+ SW4[8] is the bit labeled 8 on Switch 4.
SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3
2.4 I2C
LM75 @ 0x90 for temperature monitoring.
EEPROM @ 0xA0 for vendor specifics.
- image sensor interface (slave adresses depend on sensor)
+ image sensor interface (slave addresses depend on sensor)
3 Flash layout.
MAX5381 DAC @ 0x60 for 1st digital input threshold.
LM75 @ 0x90 for temperature monitoring.
EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
- 1st image sensor interface (slave adresses depend on sensor)
+ 1st image sensor interface (slave addresses depend on sensor)
Bus2:
MAX5381 DAC @ 0x60 for 2nd digital input threshold.
- 2nd image sensor interface (slave adresses depend on sensor)
+ 2nd image sensor interface (slave addresses depend on sensor)
3 Flash layout.
2.4 I2C
EEPROM @ 0xA0 for vendor specifics.
- image sensor interface (slave adresses depend on sensor)
+ image sensor interface (slave addresses depend on sensor)
3 Flash layout.
---------------------------------
The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports
-boot from SD card only. However, by default, the early version of SabreLite
+boot from SD card only. However, by default, the SabreLite
boards boot from the SPI NOR flash. These boards need to be reflashed with
a small SD card loader to support boot from SD card. This small SD card loader
will be flashed into the SPI NOR. The board will still boot from SPI NOR, but
the loader will in turn request the BootROM to load the U-Boot from SD card.
-At the moment of writing, please check with Freescale on the availablity of
-this small SD loader binary.
+
+The SD card loader is available from
+
+https://wiki.linaro.org/Boards/MX6QSabreLite
+
+under a open-source 3-clause BSD license.
To update the SPI-NOR on the SabreLite board without the Freescale
manufacturing tool use the following procedure:
1. Write this SD card loader onto a large SD card using:
- sudo dd if=MX6_SPI_to_SD_loader.bin of=/dev/sXx
+ sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx
Note: Replace sXx with the device representing the SD card in your system.
=======================================================================
This file contains some handy info regarding U-Boot and the AMCC
-Ocotea 440gx evalutation board. See the README.ppc440 for additional
+Ocotea 440gx evaluation board. See the README.ppc440 for additional
information.
Memory Map
----------
-0xef00_0000 - 0xef7f_ffff Alernate bank 8MB
+0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
0xe800_0000 - 0xefff_ffff Boot bank 8MB
0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB
"Prompt for advanced kernel configuration options"
- Select
"Set physical address where the kernel is loaded"
- and set it to 0x20000000, asssuming core1 will
+ and set it to 0x20000000, assuming core1 will
start from 512MB.
- Select "Set custom page offset address"
- Select "Set custom kernel base address"
- SPI ROM 8MB
- 2D Graphic controller
- Ethernet controller
+ - eMMC 2GB
configuration for This board:
--- /dev/null
+Overview of SPL on OMAP3 devices
+================================
+
+Introduction
+------------
+
+This document provides an overview of how SPL functions on OMAP3 (and related
+such as am35x and am37x) processors.
+
+Methodology
+-----------
+
+On these platforms the ROM supports trying a sequence of boot devices. Once
+one has been used successfully to load SPL this information is stored in memory
+and the location stored in a register. We will read this to determine where to
+read U-Boot from in turn.
+
+Memory Map
+----------
+
+This is an example of a typical setup. See top-level README for documentation
+of which CONFIG variables control these values. For a given board and the
+amount of DRAM available to it different values may need to be used.
+Note that the size of the SPL text rodata and data is enforced with a CONFIG
+option and growing over that size results in a link error. The SPL stack
+starts at the top of SRAM (which is configurable) and grows downward. The
+space between the top of SRAM and the enforced upper bound on the size of the
+SPL text, data and rodata is considered the safe stack area. Details on
+confirming this behavior are shown below.
+
+A portion of the system memory map looks as follows:
+SRAM: 0x40200000 - 0x4020FFFF
+DDR1: 0x80000000 - 0xBFFFFFFF
+
+Option 1 (SPL only):
+0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
+0x4020BC00 - 0x4020FFFC: Area for the SPL stack.
+0x80000000 - 0x8007FFFF: Area for the SPL BSS.
+0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot
+0x80208000 - 0x80307FFF: malloc() pool available to SPL.
+
+Option 2 (SPL or X-Loader):
+0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
+0x4020BC00 - 0x4020FFFC: Area for the SPL stack.
+0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot
+0x87000000 - 0x8707FFFF: Area for the SPL BSS.
+0x87080000 - 0x870FFFFF: malloc() pool available to SPL.
+
+For the areas that reside within DDR1 they must not be used prior to s_init()
+completing. Note that CONFIG_SYS_TEXT_BASE must be clear of the areas that SPL
+uses while running. This is why we have two versions of the memory map that
+only vary in where the BSS and malloc pool reside.
+
+Estimating stack usage
+----------------------
+
+With gcc 4.6 (and later) and the use of GNU cflow it is possible to estimate
+stack usage at various points in run sequence of SPL. The -fstack-usage option
+to gcc will produce '.su' files (such as arch/arm/cpu/armv7/syslib.su) that
+will give stack usage information and cflow can construct program flow.
+
+Must have gcc 4.6 or later, which supports -fstack-usage
+
+1) Build normally
+2) Perform the following shell command to generate a list of C files used in
+SPL:
+$ find spl -name '*.su' | sed -e 's:^spl/::' -e 's:[.]su$:.c:' > used-spl.list
+3) Execute cflow:
+$ cflow --main=board_init_r `cat used-spl.list` 2>&1 | $PAGER
+
+cflow will spit out a number of warnings as it does not parse
+the config files and picks functions based on #ifdef. Parsing the '.i'
+files instead introduces another set of headaches. These warnings are
+not usually important to understanding the flow, however.
--- /dev/null
+Device Tree Bindings Staging Area
+=================================
+
+This directory contains device tree bindings for U-Boot.
+
+These follow along with Linux kernel bindings, with a few additions. By
+adding the files here, U-Boot patches can clearly show thees additions.
+This makes it easier for device tree people to review these additions in
+patches sent to the U-Boot mailing list.
+
+The intent IS to commit these files to U-Boot. Hopefully at some point
+the files will be stored in another repo (shared with Linux) which is
+brought in as needed. Changes here are intended to mirror changes in the
+Linux Documentation/devicetree/bindings/ directory.
+
+sjg@chromium.org
+17-Jan-12
--- /dev/null
+NVIDIA Tegra20 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be "nvidia,tegra20-car"
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+ the 32 KHz "32k_in", and the board-specific oscillator "osc".
+- #clock-cells : Should be 1.
+ In clock consumers, this cell represents the clock ID exposed by the CAR.
+
+ The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ this case, those clocks are assigned IDs above 95 in order to highlight
+ this issue. Implementations that interpret these clock IDs as bit values
+ within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ explicitly handle these special cases.
+
+ The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+ above.
+
+ 0 cpu
+ 1 unassigned
+ 2 unassigned
+ 3 ac97
+ 4 rtc
+ 5 tmr
+ 6 uart1
+ 7 unassigned (register bit affects uart2 and vfir)
+ 8 gpio
+ 9 sdmmc2
+ 10 unassigned (register bit affects spdif_in and spdif_out)
+ 11 i2s1
+ 12 i2c1
+ 13 ndflash
+ 14 sdmmc1
+ 15 sdmmc4
+ 16 twc
+ 17 pwm
+ 18 i2s2
+ 19 epp
+ 20 unassigned (register bit affects vi and vi_sensor)
+ 21 2d
+ 22 usbd
+ 23 isp
+ 24 3d
+ 25 ide
+ 26 disp2
+ 27 disp1
+ 28 host1x
+ 29 vcp
+ 30 unassigned
+ 31 cache2
+
+ 32 mem
+ 33 ahbdma
+ 34 apbdma
+ 35 unassigned
+ 36 kbc
+ 37 stat_mon
+ 38 pmc
+ 39 fuse
+ 40 kfuse
+ 41 sbc1
+ 42 snor
+ 43 spi1
+ 44 sbc2
+ 45 xio
+ 46 sbc3
+ 47 dvc
+ 48 dsi
+ 49 unassigned (register bit affects tvo and cve)
+ 50 mipi
+ 51 hdmi
+ 52 csi
+ 53 tvdac
+ 54 i2c2
+ 55 uart3
+ 56 unassigned
+ 57 emc
+ 58 usb2
+ 59 usb3
+ 60 mpe
+ 61 vde
+ 62 bsea
+ 63 bsev
+
+ 64 speedo
+ 65 uart4
+ 66 uart5
+ 67 i2c3
+ 68 sbc4
+ 69 sdmmc3
+ 70 pcie
+ 71 owr
+ 72 afi
+ 73 csite
+ 74 unassigned
+ 75 avpucq
+ 76 la
+ 77 unassigned
+ 78 unassigned
+ 79 unassigned
+ 80 unassigned
+ 81 unassigned
+ 82 unassigned
+ 83 unassigned
+ 84 irama
+ 85 iramb
+ 86 iramc
+ 87 iramd
+ 88 cram2
+ 89 audio_2x a/k/a audio_2x_sync_clk
+ 90 clk_d
+ 91 unassigned
+ 92 sus
+ 93 cdev1
+ 94 cdev2
+ 95 unassigned
+
+ 96 uart2
+ 97 vfir
+ 98 spdif_in
+ 99 spdif_out
+ 100 vi
+ 101 vi_sensor
+ 102 tvo
+ 103 cve
+ 104 osc
+ 105 clk_32k a/k/a clk_s
+ 106 clk_m
+ 107 sclk
+ 108 cclk
+ 109 hclk
+ 110 pclk
+ 111 blink
+ 112 pll_a
+ 113 pll_a_out0
+ 114 pll_c
+ 115 pll_c_out1
+ 116 pll_d
+ 117 pll_d_out0
+ 118 pll_e
+ 119 pll_m
+ 120 pll_m_out1
+ 121 pll_p
+ 122 pll_p_out1
+ 123 pll_p_out2
+ 124 pll_p_out3
+ 125 pll_p_out4
+ 126 pll_s
+ 127 pll_u
+ 128 pll_x
+ 129 cop a/k/a avp
+ 130 audio a/k/a audio_sync_clk
+
+Example SoC include file:
+
+/ {
+ tegra_car: clock@60006000 {
+ compatible = "nvidia,tegra20-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ usb@c5004000 {
+ clocks = <&tegra_car 58>; /* usb2 */
+ };
+};
+
+Example board file:
+
+/ {
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+ };
+
+ i2c@7000d000 {
+ pmic@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+
+ clk_32k: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+ };
+
+ &tegra_car {
+ clocks = <&clk_32k> <&osc>;
+ };
+};
--- /dev/null
+(Placeholder note while we locate the kernel Tegra20 bindings)
+
+Added in U-Boot:
+
+Required properties:
+ - clocks : Two clocks must be given, each as a phandle to the Tegra's
+ CAR node and the clock number as a parameter:
+ - the I2C clock to use for the peripheral
+ - the pll_p_out3 clock, which can be used for fast operation. This
+ does not change and is the same for all I2C nodes.
+
+Example:
+(TODO: merge with existing example):
+
+ i2c@7000c400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000C400 0x100>;
+ interrupts = < 116 >;
+ /* PERIPH_ID_I2C2, PLL_P_OUT3 */
+ clocks = <&tegra_car 54>, <&tegra_car 124>;
+ };
--- /dev/null
+Tegra SOC USB controllers
+
+The device node for a USB controller that is part of a Tegra
+SOC is as described in the document "Open Firmware Recommended
+Practice : Universal Serial Bus" with the following modifications
+and additions :
+
+Required properties :
+ - compatible : Should be "nvidia,tegra20-ehci" for USB controllers
+ used in host mode.
+ - phy_type : Should be one of "ulpi" or "utmi".
+ - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
+ activated for the bus to be powered.
+
+Optional properties:
+ - dr_mode : dual role mode. Indicates the working mode for
+ nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral",
+ or "otg". Default to "host" if not defined for backward compatibility.
+ host means this is a host controller
+ peripheral means it is device controller
+ otg means it can operate as either ("on the go")
+ - nvidia,has-legacy-mode : boolean indicates whether this controller can
+ operate in legacy mode (as APX 2500 / 2600). In legacy mode some
+ registers are accessed through the APB_MISC base address instead of
+ the USB controller.
return tmp;
}
+#ifndef CONFIG_SYS_DCACHE_OFF
+void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
+{
+ uint32_t addr;
+ uint32_t size;
+
+ addr = (uint32_t)desc;
+ size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
+
+ flush_dcache_range(addr, addr + size);
+}
+#else
+inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc) {}
+#endif
+
/*
* Enable a DMA channel.
*
struct mxs_dma_desc *mxs_dma_desc_alloc(void)
{
struct mxs_dma_desc *pdesc;
+ uint32_t size;
- pdesc = memalign(MXS_DMA_ALIGNMENT, sizeof(struct mxs_dma_desc));
+ size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
+ pdesc = memalign(MXS_DMA_ALIGNMENT, size);
if (pdesc == NULL)
return NULL;
last->cmd.next = mxs_dma_cmd_address(pdesc);
last->cmd.data |= MXS_DMA_DESC_CHAIN;
+
+ mxs_dma_flush_desc(last);
}
pdesc->flags |= MXS_DMA_DESC_READY;
if (pdesc->flags & MXS_DMA_DESC_FIRST)
pchan->pending_num++;
list_add_tail(&pdesc->node, &pchan->active);
+ mxs_dma_flush_desc(pdesc);
+
return ret;
}
{
uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DIN(bank);
- struct mx28_register *reg =
- (struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+ struct mx28_register_32 *reg =
+ (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
return (readl(®->reg) >> PAD_PIN(gpio)) & 1;
}
{
uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DOUT(bank);
- struct mx28_register *reg =
- (struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+ struct mx28_register_32 *reg =
+ (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
if (value)
writel(1 << PAD_PIN(gpio), ®->reg_set);
{
uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DOE(bank);
- struct mx28_register *reg =
- (struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+ struct mx28_register_32 *reg =
+ (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
writel(1 << PAD_PIN(gpio), ®->reg_clr);
{
uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DOE(bank);
- struct mx28_register *reg =
- (struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+ struct mx28_register_32 *reg =
+ (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
writel(1 << PAD_PIN(gpio), ®->reg_set);
COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
+COBJS-$(CONFIG_TEGRA_I2C) += tegra_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (c) 2010-2011 NVIDIA Corporation
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned int i2c_bus_num;
+
+/* Information about i2c controller */
+struct i2c_bus {
+ int id;
+ enum periph_id periph_id;
+ int speed;
+ int pinmux_config;
+ struct i2c_control *control;
+ struct i2c_ctlr *regs;
+ int is_dvc; /* DVC type, rather than I2C */
+ int inited; /* bus is inited */
+};
+
+static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];
+
+static void set_packet_mode(struct i2c_bus *i2c_bus)
+{
+ u32 config;
+
+ config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
+
+ if (i2c_bus->is_dvc) {
+ struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
+
+ writel(config, &dvc->cnfg);
+ } else {
+ writel(config, &i2c_bus->regs->cnfg);
+ /*
+ * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
+ * issues, i.e., some slaves may be wrongly detected.
+ */
+ setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
+ }
+}
+
+static void i2c_reset_controller(struct i2c_bus *i2c_bus)
+{
+ /* Reset I2C controller. */
+ reset_periph(i2c_bus->periph_id, 1);
+
+ /* re-program config register to packet mode */
+ set_packet_mode(i2c_bus);
+}
+
+static void i2c_init_controller(struct i2c_bus *i2c_bus)
+{
+ /*
+ * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
+ * here, in section 23.3.1, but in fact we seem to need a factor of
+ * 16 to get the right frequency.
+ */
+ clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
+ i2c_bus->speed * 2 * 8);
+
+ /* Reset I2C controller. */
+ i2c_reset_controller(i2c_bus);
+
+ /* Configure I2C controller. */
+ if (i2c_bus->is_dvc) { /* only for DVC I2C */
+ struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
+
+ setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
+ }
+
+ funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
+}
+
+static void send_packet_headers(
+ struct i2c_bus *i2c_bus,
+ struct i2c_trans_info *trans,
+ u32 packet_id)
+{
+ u32 data;
+
+ /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
+ data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
+ data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
+ data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
+ writel(data, &i2c_bus->control->tx_fifo);
+ debug("pkt header 1 sent (0x%x)\n", data);
+
+ /* prepare header2 */
+ data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
+ writel(data, &i2c_bus->control->tx_fifo);
+ debug("pkt header 2 sent (0x%x)\n", data);
+
+ /* prepare IO specific header: configure the slave address */
+ data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
+
+ /* Enable Read if it is not a write transaction */
+ if (!(trans->flags & I2C_IS_WRITE))
+ data |= PKT_HDR3_READ_MODE_MASK;
+
+ /* Write I2C specific header */
+ writel(data, &i2c_bus->control->tx_fifo);
+ debug("pkt header 3 sent (0x%x)\n", data);
+}
+
+static int wait_for_tx_fifo_empty(struct i2c_control *control)
+{
+ u32 count;
+ int timeout_us = I2C_TIMEOUT_USEC;
+
+ while (timeout_us >= 0) {
+ count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
+ >> TX_FIFO_EMPTY_CNT_SHIFT;
+ if (count == I2C_FIFO_DEPTH)
+ return 1;
+ udelay(10);
+ timeout_us -= 10;
+ }
+
+ return 0;
+}
+
+static int wait_for_rx_fifo_notempty(struct i2c_control *control)
+{
+ u32 count;
+ int timeout_us = I2C_TIMEOUT_USEC;
+
+ while (timeout_us >= 0) {
+ count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
+ >> TX_FIFO_FULL_CNT_SHIFT;
+ if (count)
+ return 1;
+ udelay(10);
+ timeout_us -= 10;
+ }
+
+ return 0;
+}
+
+static int wait_for_transfer_complete(struct i2c_control *control)
+{
+ int int_status;
+ int timeout_us = I2C_TIMEOUT_USEC;
+
+ while (timeout_us >= 0) {
+ int_status = readl(&control->int_status);
+ if (int_status & I2C_INT_NO_ACK_MASK)
+ return -int_status;
+ if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
+ return -int_status;
+ if (int_status & I2C_INT_XFER_COMPLETE_MASK)
+ return 0;
+
+ udelay(10);
+ timeout_us -= 10;
+ }
+
+ return -1;
+}
+
+static int send_recv_packets(struct i2c_bus *i2c_bus,
+ struct i2c_trans_info *trans)
+{
+ struct i2c_control *control = i2c_bus->control;
+ u32 int_status;
+ u32 words;
+ u8 *dptr;
+ u32 local;
+ uchar last_bytes;
+ int error = 0;
+ int is_write = trans->flags & I2C_IS_WRITE;
+
+ /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
+ int_status = readl(&control->int_status);
+ writel(int_status, &control->int_status);
+
+ send_packet_headers(i2c_bus, trans, 1);
+
+ words = DIV_ROUND_UP(trans->num_bytes, 4);
+ last_bytes = trans->num_bytes & 3;
+ dptr = trans->buf;
+
+ while (words) {
+ u32 *wptr = (u32 *)dptr;
+
+ if (is_write) {
+ /* deal with word alignment */
+ if ((unsigned)dptr & 3) {
+ memcpy(&local, dptr, sizeof(u32));
+ writel(local, &control->tx_fifo);
+ debug("pkt data sent (0x%x)\n", local);
+ } else {
+ writel(*wptr, &control->tx_fifo);
+ debug("pkt data sent (0x%x)\n", *wptr);
+ }
+ if (!wait_for_tx_fifo_empty(control)) {
+ error = -1;
+ goto exit;
+ }
+ } else {
+ if (!wait_for_rx_fifo_notempty(control)) {
+ error = -1;
+ goto exit;
+ }
+ /*
+ * for the last word, we read into our local buffer,
+ * in case that caller did not provide enough buffer.
+ */
+ local = readl(&control->rx_fifo);
+ if ((words == 1) && last_bytes)
+ memcpy(dptr, (char *)&local, last_bytes);
+ else if ((unsigned)dptr & 3)
+ memcpy(dptr, &local, sizeof(u32));
+ else
+ *wptr = local;
+ debug("pkt data received (0x%x)\n", local);
+ }
+ words--;
+ dptr += sizeof(u32);
+ }
+
+ if (wait_for_transfer_complete(control)) {
+ error = -1;
+ goto exit;
+ }
+ return 0;
+exit:
+ /* error, reset the controller. */
+ i2c_reset_controller(i2c_bus);
+
+ return error;
+}
+
+static int tegra2_i2c_write_data(u32 addr, u8 *data, u32 len)
+{
+ int error;
+ struct i2c_trans_info trans_info;
+
+ trans_info.address = addr;
+ trans_info.buf = data;
+ trans_info.flags = I2C_IS_WRITE;
+ trans_info.num_bytes = len;
+ trans_info.is_10bit_address = 0;
+
+ error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
+ if (error)
+ debug("tegra2_i2c_write_data: Error (%d) !!!\n", error);
+
+ return error;
+}
+
+static int tegra2_i2c_read_data(u32 addr, u8 *data, u32 len)
+{
+ int error;
+ struct i2c_trans_info trans_info;
+
+ trans_info.address = addr | 1;
+ trans_info.buf = data;
+ trans_info.flags = 0;
+ trans_info.num_bytes = len;
+ trans_info.is_10bit_address = 0;
+
+ error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
+ if (error)
+ debug("tegra2_i2c_read_data: Error (%d) !!!\n", error);
+
+ return error;
+}
+
+#ifndef CONFIG_OF_CONTROL
+#error "Please enable device tree support to use this driver"
+#endif
+
+unsigned int i2c_get_bus_speed(void)
+{
+ return i2c_controllers[i2c_bus_num].speed;
+}
+
+int i2c_set_bus_speed(unsigned int speed)
+{
+ struct i2c_bus *i2c_bus;
+
+ i2c_bus = &i2c_controllers[i2c_bus_num];
+ i2c_bus->speed = speed;
+ i2c_init_controller(i2c_bus);
+
+ return 0;
+}
+
+static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
+{
+ i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
+
+ /*
+ * We don't have a binding for pinmux yet. Leave it out for now. So
+ * far no one needs anything other than the default.
+ */
+ i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
+ i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
+ i2c_bus->periph_id = clock_decode_periph_id(blob, node);
+
+ /*
+ * We can't specify the pinmux config in the fdt, so I2C2 will not
+ * work on Seaboard. It normally has no devices on it anyway.
+ * You could add in this little hack if you need to use it.
+ * The correct solution is a pinmux binding in the fdt.
+ *
+ * if (i2c_bus->periph_id == PERIPH_ID_I2C2)
+ * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
+ */
+ if (i2c_bus->periph_id == -1)
+ return -FDT_ERR_NOTFOUND;
+
+ return 0;
+}
+
+/*
+ * Process a list of nodes, adding them to our list of I2C ports.
+ *
+ * @param blob fdt blob
+ * @param node_list list of nodes to process (any <=0 are ignored)
+ * @param count number of nodes to process
+ * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
+ * @return 0 if ok, -1 on error
+ */
+static int process_nodes(const void *blob, int node_list[], int count,
+ int is_dvc)
+{
+ struct i2c_bus *i2c_bus;
+ int i;
+
+ /* build the i2c_controllers[] for each controller */
+ for (i = 0; i < count; i++) {
+ int node = node_list[i];
+
+ if (node <= 0)
+ continue;
+
+ i2c_bus = &i2c_controllers[i];
+ i2c_bus->id = i;
+
+ if (i2c_get_config(blob, node, i2c_bus)) {
+ printf("i2c_init_board: failed to decode bus %d\n", i);
+ return -1;
+ }
+
+ i2c_bus->is_dvc = is_dvc;
+ if (is_dvc) {
+ i2c_bus->control =
+ &((struct dvc_ctlr *)i2c_bus->regs)->control;
+ } else {
+ i2c_bus->control = &i2c_bus->regs->control;
+ }
+ debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
+ is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
+ i2c_bus->periph_id, i2c_bus->speed);
+ i2c_init_controller(i2c_bus);
+ debug("ok\n");
+ i2c_bus->inited = 1;
+
+ /* Mark position as used */
+ node_list[i] = -1;
+ }
+
+ return 0;
+}
+
+/* Sadly there is no error return from this function */
+void i2c_init_board(void)
+{
+ int node_list[TEGRA_I2C_NUM_CONTROLLERS];
+ const void *blob = gd->fdt_blob;
+ int count;
+
+ /* First get the normal i2c ports */
+ count = fdtdec_find_aliases_for_id(blob, "i2c",
+ COMPAT_NVIDIA_TEGRA20_I2C, node_list,
+ TEGRA_I2C_NUM_CONTROLLERS);
+ if (process_nodes(blob, node_list, count, 0))
+ return;
+
+ /* Now look for dvc ports */
+ count = fdtdec_add_aliases_for_id(blob, "i2c",
+ COMPAT_NVIDIA_TEGRA20_DVC, node_list,
+ TEGRA_I2C_NUM_CONTROLLERS);
+ if (process_nodes(blob, node_list, count, 1))
+ return;
+}
+
+void i2c_init(int speed, int slaveaddr)
+{
+ /* This will override the speed selected in the fdt for that port */
+ debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
+ i2c_set_bus_speed(speed);
+}
+
+/* i2c write version without the register address */
+int i2c_write_data(uchar chip, uchar *buffer, int len)
+{
+ int rc;
+
+ debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
+ debug("write_data: ");
+ /* use rc for counter */
+ for (rc = 0; rc < len; ++rc)
+ debug(" 0x%02x", buffer[rc]);
+ debug("\n");
+
+ /* Shift 7-bit address over for lower-level i2c functions */
+ rc = tegra2_i2c_write_data(chip << 1, buffer, len);
+ if (rc)
+ debug("i2c_write_data(): rc=%d\n", rc);
+
+ return rc;
+}
+
+/* i2c read version without the register address */
+int i2c_read_data(uchar chip, uchar *buffer, int len)
+{
+ int rc;
+
+ debug("inside i2c_read_data():\n");
+ /* Shift 7-bit address over for lower-level i2c functions */
+ rc = tegra2_i2c_read_data(chip << 1, buffer, len);
+ if (rc) {
+ debug("i2c_read_data(): rc=%d\n", rc);
+ return rc;
+ }
+
+ debug("i2c_read_data: ");
+ /* reuse rc for counter*/
+ for (rc = 0; rc < len; ++rc)
+ debug(" 0x%02x", buffer[rc]);
+ debug("\n");
+
+ return 0;
+}
+
+/* Probe to see if a chip is present. */
+int i2c_probe(uchar chip)
+{
+ int rc;
+ uchar reg;
+
+ debug("i2c_probe: addr=0x%x\n", chip);
+ reg = 0;
+ rc = i2c_write_data(chip, ®, 1);
+ if (rc) {
+ debug("Error probing 0x%x.\n", chip);
+ return 1;
+ }
+ return 0;
+}
+
+static int i2c_addr_ok(const uint addr, const int alen)
+{
+ /* We support 7 or 10 bit addresses, so one or two bytes each */
+ return alen == 1 || alen == 2;
+}
+
+/* Read bytes */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ uint offset;
+ int i;
+
+ debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n",
+ chip, addr, len);
+ if (!i2c_addr_ok(addr, alen)) {
+ debug("i2c_read: Bad address %x.%d.\n", addr, alen);
+ return 1;
+ }
+ for (offset = 0; offset < len; offset++) {
+ if (alen) {
+ uchar data[alen];
+ for (i = 0; i < alen; i++) {
+ data[alen - i - 1] =
+ (addr + offset) >> (8 * i);
+ }
+ if (i2c_write_data(chip, data, alen)) {
+ debug("i2c_read: error sending (0x%x)\n",
+ addr);
+ return 1;
+ }
+ }
+ if (i2c_read_data(chip, buffer + offset, 1)) {
+ debug("i2c_read: error reading (0x%x)\n", addr);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+/* Write bytes */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ uint offset;
+ int i;
+
+ debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n",
+ chip, addr, len);
+ if (!i2c_addr_ok(addr, alen)) {
+ debug("i2c_write: Bad address %x.%d.\n", addr, alen);
+ return 1;
+ }
+ for (offset = 0; offset < len; offset++) {
+ uchar data[alen + 1];
+ for (i = 0; i < alen; i++)
+ data[alen - i - 1] = (addr + offset) >> (8 * i);
+ data[alen] = buffer[offset];
+ if (i2c_write_data(chip, data, alen + 1)) {
+ debug("i2c_write: error sending (0x%x)\n", addr);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+/*
+ * Functions for multiple I2C bus handling
+ */
+unsigned int i2c_get_bus_num(void)
+{
+ return i2c_bus_num;
+}
+
+int i2c_set_bus_num(unsigned int bus)
+{
+ if (bus >= TEGRA_I2C_NUM_CONTROLLERS || !i2c_controllers[bus].inited)
+ return -1;
+ i2c_bus_num = bus;
+
+ return 0;
+}
+#endif
case 1:
buf[0] = val & 0xff;
break;
+ default:
+ printf("%s: invalid tx_num: %d", __func__, pmic_i2c_tx_num);
+ return -1;
}
if (i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num))
case 1:
ret_val = buf[0];
break;
+ default:
+ printf("%s: invalid tx_num: %d", __func__, pmic_i2c_tx_num);
+ return -1;
}
memcpy(val, &ret_val, sizeof(ret_val));
int board_mmc_getcd(struct mmc *mmc)__attribute__((weak,
alias("__board_mmc_getcd")));
+#ifdef CONFIG_MMC_BOUNCE_BUFFER
+static int mmc_bounce_need_bounce(struct mmc_data *orig)
+{
+ ulong addr, len;
+
+ if (orig->flags & MMC_DATA_READ)
+ addr = (ulong)orig->dest;
+ else
+ addr = (ulong)orig->src;
+
+ if (addr % ARCH_DMA_MINALIGN) {
+ debug("MMC: Unaligned data destination address %08lx!\n", addr);
+ return 1;
+ }
+
+ len = (ulong)(orig->blocksize * orig->blocks);
+ if (len % ARCH_DMA_MINALIGN) {
+ debug("MMC: Unaligned data destination length %08lx!\n", len);
+ return 1;
+ }
+
+ return 0;
+}
+
+static int mmc_bounce_buffer_start(struct mmc_data *backup,
+ struct mmc_data *orig)
+{
+ ulong origlen, len;
+ void *buffer;
+
+ if (!orig)
+ return 0;
+
+ if (!mmc_bounce_need_bounce(orig))
+ return 0;
+
+ memcpy(backup, orig, sizeof(struct mmc_data));
+
+ origlen = orig->blocksize * orig->blocks;
+ len = roundup(origlen, ARCH_DMA_MINALIGN);
+ buffer = memalign(ARCH_DMA_MINALIGN, len);
+ if (!buffer) {
+ puts("MMC: Error allocating MMC bounce buffer!\n");
+ return 1;
+ }
+
+ if (orig->flags & MMC_DATA_READ) {
+ orig->dest = buffer;
+ } else {
+ memcpy(buffer, orig->src, origlen);
+ orig->src = buffer;
+ }
+
+ return 0;
+}
+
+static void mmc_bounce_buffer_stop(struct mmc_data *backup,
+ struct mmc_data *orig)
+{
+ ulong len;
+
+ if (!orig)
+ return;
+
+ if (!mmc_bounce_need_bounce(backup))
+ return;
+
+ if (backup->flags & MMC_DATA_READ) {
+ len = backup->blocksize * backup->blocks;
+ memcpy(backup->dest, orig->dest, len);
+ free(orig->dest);
+ orig->dest = backup->dest;
+ } else {
+ free((void *)orig->src);
+ orig->src = backup->src;
+ }
+
+ return;
+
+}
+#else
+static inline int mmc_bounce_buffer_start(struct mmc_data *backup,
+ struct mmc_data *orig) { return 0; }
+static inline void mmc_bounce_buffer_stop(struct mmc_data *backup,
+ struct mmc_data *orig) { }
+#endif
+
int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
-#ifdef CONFIG_MMC_TRACE
+ struct mmc_data backup;
int ret;
+
+ memset(&backup, 0, sizeof(backup));
+
+ ret = mmc_bounce_buffer_start(&backup, data);
+ if (ret)
+ return ret;
+
+#ifdef CONFIG_MMC_TRACE
int i;
u8 *ptr;
printf("\t\tERROR MMC rsp not supported\n");
break;
}
- return ret;
#else
- return mmc->send_cmd(mmc, cmd, data);
+ ret = mmc->send_cmd(mmc, cmd, data);
#endif
+ mmc_bounce_buffer_stop(&backup, data);
+ return ret;
}
int mmc_send_status(struct mmc *mmc, int timeout)
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/dma.h>
struct mxsmmc_priv {
int id;
uint32_t *clkctrl_ssp;
uint32_t buswidth;
int (*mmc_is_wp)(int);
+ struct mxs_dma_desc *desc;
};
#define MXSMMC_MAX_TIMEOUT 10000
struct mx28_ssp_regs *ssp_regs = priv->regs;
uint32_t reg;
int timeout;
- uint32_t data_count;
- uint32_t *data_ptr;
+ uint32_t data_count, cache_data_count;
uint32_t ctrl0;
debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
if (!data)
return 0;
- /* Process the data */
data_count = data->blocksize * data->blocks;
- timeout = MXSMMC_MAX_TIMEOUT;
+
+ if (data_count % ARCH_DMA_MINALIGN)
+ cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
+ else
+ cache_data_count = data_count;
+
if (data->flags & MMC_DATA_READ) {
- data_ptr = (uint32_t *)data->dest;
- while (data_count && --timeout) {
- reg = readl(&ssp_regs->hw_ssp_status);
- if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
- *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
- data_count -= 4;
- timeout = MXSMMC_MAX_TIMEOUT;
- } else
- udelay(1000);
- }
+ priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
+ priv->desc->cmd.address = (dma_addr_t)data->dest;
} else {
- data_ptr = (uint32_t *)data->src;
- timeout *= 100;
- while (data_count && --timeout) {
- reg = readl(&ssp_regs->hw_ssp_status);
- if (!(reg & SSP_STATUS_FIFO_FULL)) {
- writel(*data_ptr++, &ssp_regs->hw_ssp_data);
- data_count -= 4;
- timeout = MXSMMC_MAX_TIMEOUT;
- } else
- udelay(1000);
- }
+ priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
+ priv->desc->cmd.address = (dma_addr_t)data->src;
+
+ /* Flush data to DRAM so DMA can pick them up */
+ flush_dcache_range((uint32_t)priv->desc->cmd.address,
+ (uint32_t)(priv->desc->cmd.address + cache_data_count));
}
- if (!timeout) {
- printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
- mmc->block_dev.dev, cmd->cmdidx, reg);
+ priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
+ (data_count << MXS_DMA_DESC_BYTES_OFFSET);
+
+
+ mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc);
+ if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) {
+ printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev);
return COMM_ERR;
}
+ /* The data arrived into DRAM, invalidate cache over them */
+ if (data->flags & MMC_DATA_READ) {
+ invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
+ (uint32_t)(priv->desc->cmd.address + cache_data_count));
+ }
+
/* Check data errors */
reg = readl(&ssp_regs->hw_ssp_status);
if (reg &
/* 8 bits word length in MMC mode */
clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
- SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
+ SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
+ SSP_CTRL1_DMA_ENABLE);
/* Set initial bit clock 400 KHz */
mx28_set_ssp_busclock(priv->id, 400);
return -ENOMEM;
}
+ priv->desc = mxs_dma_desc_alloc();
+ if (!priv->desc) {
+ free(priv);
+ free(mmc);
+ return -ENOMEM;
+ }
+
priv->mmc_is_wp = wp;
priv->id = id;
switch (id) {
*/
mmc->f_min = 400000;
mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
- mmc->b_max = 0;
+ mmc->b_max = 0x40;
mmc_register(mmc);
return 0;
struct mmc_host *host = (struct mmc_host *)mmc->priv;
int flags, i;
int result;
- unsigned int mask;
+ unsigned int mask = 0;
unsigned int retry = 0x100000;
debug(" mmc_send_cmd called\n");
int cur_chip;
uint32_t cmd_queue_len;
+ uint32_t data_buf_size;
uint8_t *cmd_buf;
uint8_t *data_buf;
struct nand_ecclayout fake_ecc_layout;
+/*
+ * Cache management functions
+ */
+#ifndef CONFIG_SYS_DCACHE_OFF
+static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
+{
+ uint32_t addr = (uint32_t)info->data_buf;
+
+ flush_dcache_range(addr, addr + info->data_buf_size);
+}
+
+static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
+{
+ uint32_t addr = (uint32_t)info->data_buf;
+
+ invalidate_dcache_range(addr, addr + info->data_buf_size);
+}
+
+static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
+{
+ uint32_t addr = (uint32_t)info->cmd_buf;
+
+ flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
+}
+#else
+static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
+static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
+static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
+#endif
+
static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
{
struct mxs_dma_desc *desc;
mxs_dma_desc_append(channel, d);
+ /* Flush caches */
+ mxs_nand_flush_cmd_buf(nand_info);
+
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
if (ret)
goto rtn;
}
+ /* Invalidate caches */
+ mxs_nand_inval_data_buf(nand_info);
+
memcpy(buf, nand_info->data_buf, length);
rtn:
mxs_dma_desc_append(channel, d);
+ /* Flush caches */
+ mxs_nand_flush_data_buf(nand_info);
+
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
if (ret)
goto rtn;
}
+ /* Invalidate caches */
+ mxs_nand_inval_data_buf(nand_info);
+
/* Read DMA completed, now do the mark swapping. */
mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
mxs_dma_desc_append(channel, d);
+ /* Flush caches */
+ mxs_nand_flush_data_buf(nand_info);
+
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
if (ret) {
uint8_t *buf;
const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
+ nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
+
/* DMA buffers */
- buf = memalign(MXS_DMA_ALIGNMENT, size);
+ buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
if (!buf) {
printf("MXS NAND: Error allocating DMA buffers\n");
return -ENOMEM;
}
- memset(buf, 0, size);
+ memset(buf, 0, nand_info->data_buf_size);
nand_info->data_buf = buf;
nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
-
/* Command buffers */
nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
MXS_NAND_COMMAND_BUFFER_SIZE);
#include <asm/arch/mem.h>
#include <asm/arch/omap_gpmc.h>
#include <linux/mtd/nand_ecc.h>
+#include <linux/compiler.h>
#include <nand.h>
static uint8_t cs;
-static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
+static __maybe_unused struct nand_ecclayout hw_nand_oob =
+ GPMC_NAND_HW_ECC_LAYOUT;
/*
* omap_nand_hwcontrol - Set the address pointers corretly for the
* @mtd: MTD device structure
*
*/
-static void omap_hwecc_init(struct nand_chip *chip)
+static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
{
/*
* Init ECC Control Register
*
* @return 0 if data is OK or corrected, else returns -1
*/
-static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
+static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
uint8_t *read_ecc, uint8_t *calc_ecc)
{
uint32_t orig_ecc, new_ecc, res, hm;
* @dat: unused
* @ecc_code: ecc_code buffer
*/
-static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
- uint8_t *ecc_code)
+static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd,
+ const uint8_t *dat, uint8_t *ecc_code)
{
u_int32_t val;
* @mtd: MTD device structure
* @mode: Read/Write mode
*/
-static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
+static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
{
struct nand_chip *chip = mtd->priv;
uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
*/
#include <common.h>
#include <malloc.h>
+#include <linux/compiler.h>
#include <linux/err.h>
#include <asm/io.h>
#error "CONFIG_MII has to be defined!"
#endif
-#ifndef CONFIG_FEC_XCV_TYPE
-#define CONFIG_FEC_XCV_TYPE MII100
+#ifndef CONFIG_FEC_XCV_TYPE
+#define CONFIG_FEC_XCV_TYPE MII100
#endif
/*
* The i.MX28 operates with packets in big endian. We need to swap them before
* sending and after receiving.
*/
-#ifdef CONFIG_MX28
-#define CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CONFIG_MX28
+#define CONFIG_FEC_MXC_SWAP_PACKET
+#endif
+
+#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
+
+/* Check various alignment issues at compile time */
+#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
+#error "ARCH_DMA_MINALIGN must be multiple of 16!"
+#endif
+
+#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
+ (PKTALIGN % ARCH_DMA_MINALIGN != 0))
+#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
#endif
#undef DEBUG
uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
};
-#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CONFIG_FEC_MXC_SWAP_PACKET
static void swap_packet(uint32_t *packet, int length)
{
int i;
* Initialize receive task's buffer descriptors
* @param[in] fec all we know about the device yet
* @param[in] count receive buffer count to be allocated
- * @param[in] size size of each receive buffer
+ * @param[in] dsize desired size of each receive buffer
* @return 0 on success
*
* For this task we need additional memory for the data buffers. And each
* data buffer requires some alignment. Thy must be aligned to a specific
- * boundary each (DB_DATA_ALIGNMENT).
+ * boundary each.
*/
-static int fec_rbd_init(struct fec_priv *fec, int count, int size)
+static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
{
- int ix;
- uint32_t p = 0;
-
- /* reserve data memory and consider alignment */
- if (fec->rdb_ptr == NULL)
- fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
- p = (uint32_t)fec->rdb_ptr;
- if (!p) {
- puts("fec_mxc: not enough malloc memory\n");
- return -ENOMEM;
- }
- memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
- p += DB_DATA_ALIGNMENT-1;
- p &= ~(DB_DATA_ALIGNMENT-1);
-
- for (ix = 0; ix < count; ix++) {
- writel(p, &fec->rbd_base[ix].data_pointer);
- p += size;
- writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
- writew(0, &fec->rbd_base[ix].data_length);
- }
+ uint32_t size;
+ int i;
+
/*
- * mark the last RBD to close the ring
+ * Allocate memory for the buffers. This allocation respects the
+ * alignment
*/
- writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
+ size = roundup(dsize, ARCH_DMA_MINALIGN);
+ for (i = 0; i < count; i++) {
+ uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
+ if (data_ptr == 0) {
+ uint8_t *data = memalign(ARCH_DMA_MINALIGN,
+ size);
+ if (!data) {
+ printf("%s: error allocating rxbuf %d\n",
+ __func__, i);
+ goto err;
+ }
+ writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
+ } /* needs allocation */
+ writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
+ writew(0, &fec->rbd_base[i].data_length);
+ }
+
+ /* Mark the last RBD to close the ring. */
+ writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
fec->rbd_index = 0;
return 0;
+
+err:
+ for (; i >= 0; i--) {
+ uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
+ free((void *)data_ptr);
+ }
+
+ return -ENOMEM;
}
/**
*/
static void fec_tbd_init(struct fec_priv *fec)
{
+ unsigned addr = (unsigned)fec->tbd_base;
+ unsigned size = roundup(2 * sizeof(struct fec_bd),
+ ARCH_DMA_MINALIGN);
writew(0x0000, &fec->tbd_base[0].status);
writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
fec->tbd_index = 0;
+ flush_dcache_range(addr, addr+size);
}
/**
*/
static void fec_rbd_clean(int last, struct fec_bd *pRbd)
{
- /*
- * Reset buffer descriptor as empty
- */
+ unsigned short flags = FEC_RBD_EMPTY;
if (last)
- writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
- else
- writew(FEC_RBD_EMPTY, &pRbd->status);
- /*
- * no data in it
- */
+ flags |= FEC_RBD_WRAP;
+ writew(flags, &pRbd->status);
writew(0, &pRbd->data_length);
}
{
struct fec_priv *fec = (struct fec_priv *)edev->priv;
int speed;
+ uint32_t addr, size;
+ int i;
debug("fec_open: fec_open(dev)\n");
/* full-duplex, heartbeat disabled */
writel(1 << 2, &fec->eth->x_cntrl);
fec->rbd_index = 0;
+ /* Invalidate all descriptors */
+ for (i = 0; i < FEC_RBD_NUM - 1; i++)
+ fec_rbd_clean(0, &fec->rbd_base[i]);
+ fec_rbd_clean(1, &fec->rbd_base[i]);
+
+ /* Flush the descriptors into RAM */
+ size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
+ ARCH_DMA_MINALIGN);
+ addr = (uint32_t)fec->rbd_base;
+ flush_dcache_range(addr, addr + size);
+
#ifdef FEC_QUIRK_ENET_MAC
/* Enable ENET HW endian SWAP */
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
static int fec_init(struct eth_device *dev, bd_t* bd)
{
- uint32_t base;
struct fec_priv *fec = (struct fec_priv *)dev->priv;
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
uint32_t rcntrl;
- int i;
+ uint32_t size;
+ int i, ret;
/* Initialize MAC address */
fec_set_hwaddr(dev);
/*
- * reserve memory for both buffer descriptor chains at once
- * Datasheet forces the startaddress of each chain is 16 byte
- * aligned
+ * Allocate transmit descriptors, there are two in total. This
+ * allocation respects cache alignment.
*/
- if (fec->base_ptr == NULL)
- fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
- sizeof(struct fec_bd) + DB_ALIGNMENT);
- base = (uint32_t)fec->base_ptr;
- if (!base) {
- puts("fec_mxc: not enough malloc memory\n");
- return -ENOMEM;
+ if (!fec->tbd_base) {
+ size = roundup(2 * sizeof(struct fec_bd),
+ ARCH_DMA_MINALIGN);
+ fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
+ if (!fec->tbd_base) {
+ ret = -ENOMEM;
+ goto err1;
+ }
+ memset(fec->tbd_base, 0, size);
+ fec_tbd_init(fec);
+ flush_dcache_range((unsigned)fec->tbd_base, size);
}
- memset((void *)base, 0, (2 + FEC_RBD_NUM) *
- sizeof(struct fec_bd) + DB_ALIGNMENT);
- base += (DB_ALIGNMENT-1);
- base &= ~(DB_ALIGNMENT-1);
-
- fec->rbd_base = (struct fec_bd *)base;
- base += FEC_RBD_NUM * sizeof(struct fec_bd);
-
- fec->tbd_base = (struct fec_bd *)base;
+ /*
+ * Allocate receive descriptors. This allocation respects cache
+ * alignment.
+ */
+ if (!fec->rbd_base) {
+ size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
+ ARCH_DMA_MINALIGN);
+ fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
+ if (!fec->rbd_base) {
+ ret = -ENOMEM;
+ goto err2;
+ }
+ memset(fec->rbd_base, 0, size);
+ /*
+ * Initialize RxBD ring
+ */
+ if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
+ ret = -ENOMEM;
+ goto err3;
+ }
+ flush_dcache_range((unsigned)fec->rbd_base,
+ (unsigned)fec->rbd_base + size);
+ }
/*
* Set interrupt mask register
writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
- /*
- * Initialize RxBD/TxBD rings
- */
- if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
- free(fec->base_ptr);
- fec->base_ptr = NULL;
- return -ENOMEM;
- }
- fec_tbd_init(fec);
-
-
#ifndef CONFIG_PHYLIB
if (fec->xcv_type != SEVENWIRE)
miiphy_restart_aneg(dev);
#endif
fec_open(dev);
return 0;
+
+err3:
+ free(fec->rbd_base);
+err2:
+ free(fec->tbd_base);
+err1:
+ return ret;
}
/**
* @param[in] length Data count in bytes
* @return 0 on success
*/
-static int fec_send(struct eth_device *dev, volatile void* packet, int length)
+static int fec_send(struct eth_device *dev, volatile void *packet, int length)
{
unsigned int status;
+ uint32_t size;
+ uint32_t addr;
/*
* This routine transmits one frame. This routine only accepts
}
/*
- * Setup the transmit buffer
- * Note: We are always using the first buffer for transmission,
- * the second will be empty and only used to stop the DMA engine
+ * Setup the transmit buffer. We are always using the first buffer for
+ * transmission, the second will be empty and only used to stop the DMA
+ * engine. We also flush the packet to RAM here to avoid cache trouble.
*/
-#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)packet, length);
#endif
+
+ addr = (uint32_t)packet;
+ size = roundup(length, ARCH_DMA_MINALIGN);
+ flush_dcache_range(addr, addr + size);
+
writew(length, &fec->tbd_base[fec->tbd_index].data_length);
- writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
+ writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
+
/*
* update BD's status now
* This block:
status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
writew(status, &fec->tbd_base[fec->tbd_index].status);
+ /*
+ * Flush data cache. This code flushes both TX descriptors to RAM.
+ * After this code, the descriptors will be safely in RAM and we
+ * can start DMA.
+ */
+ size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+ addr = (uint32_t)fec->tbd_base;
+ flush_dcache_range(addr, addr + size);
+
/*
* Enable SmartDMA transmit task
*/
fec_tx_task_enable(fec);
/*
- * wait until frame is sent .
+ * Wait until frame is sent. On each turn of the wait cycle, we must
+ * invalidate data cache to see what's really in RAM. Also, we need
+ * barrier here.
*/
+ invalidate_dcache_range(addr, addr + size);
while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
udelay(1);
+ invalidate_dcache_range(addr, addr + size);
}
+
debug("fec_send: status 0x%x index %d\n",
readw(&fec->tbd_base[fec->tbd_index].status),
fec->tbd_index);
int frame_length, len = 0;
struct nbuf *frame;
uint16_t bd_status;
+ uint32_t addr, size;
+ int i;
uchar buff[FEC_MAX_PKT_SIZE];
/*
}
/*
- * ensure reading the right buffer status
+ * Read the buffer status. Before the status can be read, the data cache
+ * must be invalidated, because the data in RAM might have been changed
+ * by DMA. The descriptors are properly aligned to cachelines so there's
+ * no need to worry they'd overlap.
+ *
+ * WARNING: By invalidating the descriptor here, we also invalidate
+ * the descriptors surrounding this one. Therefore we can NOT change the
+ * contents of this descriptor nor the surrounding ones. The problem is
+ * that in order to mark the descriptor as processed, we need to change
+ * the descriptor. The solution is to mark the whole cache line when all
+ * descriptors in the cache line are processed.
*/
+ addr = (uint32_t)rbd;
+ addr &= ~(ARCH_DMA_MINALIGN - 1);
+ size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(addr, addr + size);
+
bd_status = readw(&rbd->status);
debug("fec_recv: status 0x%x\n", bd_status);
*/
frame = (struct nbuf *)readl(&rbd->data_pointer);
frame_length = readw(&rbd->data_length) - 4;
+ /*
+ * Invalidate data cache over the buffer
+ */
+ addr = (uint32_t)frame;
+ size = roundup(frame_length, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(addr, addr + size);
+
/*
* Fill the buffer and pass it to upper layers
*/
-#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)frame->data, frame_length);
#endif
memcpy(buff, frame->data, frame_length);
(ulong)rbd->data_pointer,
bd_status);
}
+
/*
- * free the current buffer, restart the engine
- * and move forward to the next buffer
+ * Free the current buffer, restart the engine and move forward
+ * to the next buffer. Here we check if the whole cacheline of
+ * descriptors was already processed and if so, we mark it free
+ * as whole.
*/
- fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
+ size = RXDESC_PER_CACHELINE - 1;
+ if ((fec->rbd_index & size) == size) {
+ i = fec->rbd_index - size;
+ addr = (uint32_t)&fec->rbd_base[i];
+ for (; i <= fec->rbd_index ; i++) {
+ fec_rbd_clean(i == (FEC_RBD_NUM - 1),
+ &fec->rbd_base[i]);
+ }
+ flush_dcache_range(addr,
+ addr + ARCH_DMA_MINALIGN);
+ }
+
fec_rx_task_enable(fec);
fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
}
bus->read = fec_phy_read;
bus->write = fec_phy_write;
sprintf(bus->name, edev->name);
-#ifdef CONFIG_MX28
+#ifdef CONFIG_MX28
/*
* The i.MX28 has two ethernet interfaces, but they are not equal.
* Only the first one can access the MDIO bus.
return ret;
}
-#ifndef CONFIG_FEC_MXC_MULTI
+#ifndef CONFIG_FEC_MXC_MULTI
int fecmxc_initialize(bd_t *bd)
{
int lout = 1;
#define MIIGSK_ENR_EN (1 << 1)
#endif
-/**
- * @brief Descriptor buffer alignment
- *
- * i.MX27 requires a 16 byte alignment (but for the first element only)
- */
-#define DB_ALIGNMENT 16
-
-/**
- * @brief Data buffer alignment
- *
- * i.MX27 requires a four byte alignment for transmit and 16 bits
- * alignment for receive so take 16
- * Note: Valid for member data_pointer in struct buffer_descriptor
- */
-#define DB_DATA_ALIGNMENT 16
-
/**
* @brief Receive & Transmit Buffer Descriptor definitions
*
struct fec_bd *tbd_base; /* TBD ring */
int tbd_index; /* next transmit BD to write */
bd_t *bd;
- void *rdb_ptr;
- void *base_ptr;
+ uint8_t *tdb_ptr;
int dev_id;
int phy_id;
struct mii_dev *bus;
#endif /* !CONFIG_SMC91111_EXT_PHY */
-/*------------------------------------------------------------
- . Waits the specified number of milliseconds - kernel friendly
- .-------------------------------------------------------------*/
-#ifndef CONFIG_SMC91111_EXT_PHY
-static void smc_wait_ms(unsigned int ms)
-{
- udelay(ms*1000);
-}
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-
/*------------------------------------------------------------
. Configures the specified PHY using Autonegotiation. Calls
. smc_phy_fixed() if the user has requested a certain config.
break;
}
- smc_wait_ms (500); /* wait 500 millisecs */
+ mdelay(500); /* wait 500 millisecs */
}
if (timeout < 1) {
break;
}
- smc_wait_ms (500); /* wait 500 millisecs */
+ mdelay(500); /* wait 500 millisecs */
/* Restart auto-negotiation if remote fault */
if (status & PHY_STAT_REM_FLT) {
#define FSL_PCIE_CFG_RDY 0x4b0
#define FSL_PROG_IF_AGENT 0x1
-void pciauto_prescan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus);
-void pciauto_postscan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus);
-
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS 0
#endif
COBJS-$(CONFIG_I82365) += i82365.o
COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o
-COBJS-$(CONFIG_PXA_PCMCIA) += pxa_pcmcia.o
COBJS-y += rpx_pcmcia.o
COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
COBJS-y += tqm8xx_pcmcia.o
+++ /dev/null
-#include <common.h>
-#include <config.h>
-
-#include <pcmcia.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-static inline void msWait(unsigned msVal)
-{
- udelay(msVal*1000);
-}
-
-int pcmcia_on (void)
-{
- unsigned int reg_arr[] = {
- 0x48000028, CONFIG_SYS_MCMEM0_VAL,
- 0x4800002c, CONFIG_SYS_MCMEM1_VAL,
- 0x48000030, CONFIG_SYS_MCATT0_VAL,
- 0x48000034, CONFIG_SYS_MCATT1_VAL,
- 0x48000038, CONFIG_SYS_MCIO0_VAL,
- 0x4800003c, CONFIG_SYS_MCIO1_VAL,
-
- 0, 0
- };
- int i, rc;
-
-#ifdef CONFIG_EXADRON1
- int cardDetect;
- volatile unsigned int *v_pBCRReg =
- (volatile unsigned int *) 0x08000000;
-#endif
-
- debug ("%s\n", __FUNCTION__);
-
- i = 0;
- while (reg_arr[i]) {
- (*(volatile unsigned int *) reg_arr[i]) |= reg_arr[i + 1];
- i += 2;
- }
- udelay (1000);
-
- debug ("%s: programmed mem controller \n", __FUNCTION__);
-
-#ifdef CONFIG_EXADRON1
-
-/*define useful BCR masks */
-#define BCR_CF_INIT_VAL 0x00007230
-#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231
-#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233
-#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213
-#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211
-
- /* we see from the GPIO bit if the card is present */
- cardDetect = !(GPLR0 & GPIO_bit (14));
-
- if (cardDetect) {
- printf ("No PCMCIA card found!\n");
- }
-
- /* reset the card via the BCR line */
- *v_pBCRReg = (unsigned) BCR_CF_INIT_VAL;
- msWait (500);
-
- *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL;
- msWait (500);
-
- *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL;
- msWait (500);
-
- *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL;
- msWait (500);
-
- *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL;
- msWait (1500);
-
- /* enable address bus */
- GPCR1 = 0x01;
- /* and the first CF slot */
- MECR = 0x00000002;
-
-#endif /* EXADRON 1 */
-
- rc = check_ide_device (0); /* use just slot 0 */
-
- return rc;
-}
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_off (void)
-{
- return 0;
-}
-#endif
void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
u8 dev_grp, u8 dev_grp_sel)
{
- /* Select the Device Group */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
- dev_grp);
+ int ret;
/* Select the Voltage */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
+ ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
vsel_reg);
+ if (ret != 0) {
+ printf("Could could not write vsel to reg %02x (%d)\n",
+ vsel_reg, ret);
+ return;
+ }
+
+ /* Select the Device Group (enable the supply if dev_grp_sel != 0) */
+ ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
+ dev_grp);
+ if (ret != 0)
+ printf("Could could not write grp_sel to reg %02x (%d)\n",
+ dev_grp, ret);
}
void twl4030_power_init(void)
if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
printf("MXS SPI: Timeout waiting for start\n");
- return -1;
+ return -ETIMEDOUT;
}
if (tx)
if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
printf("MXS SPI: Timeout waiting for data\n");
- return -1;
+ return -ETIMEDOUT;
}
*rx = readl(&ssp_regs->hw_ssp_data);
if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
printf("MXS SPI: Timeout waiting for finish\n");
- return -1;
+ return -ETIMEDOUT;
}
}
return 0;
}
+/*McSPI Transmit Receive Mode*/
+int omap3_spi_txrx(struct spi_slave *slave,
+ unsigned int len, const u8 *txp, u8 *rxp, unsigned long flags)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+ int timeout = SPI_WAIT_TIMEOUT;
+ int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+ int irqstatus = readl(&ds->regs->irqstatus);
+ int i=0;
+
+ /*Enable SPI channel*/
+ if (flags & SPI_XFER_BEGIN)
+ writel(OMAP3_MCSPI_CHCTRL_EN,
+ &ds->regs->channel[ds->slave.cs].chctrl);
+
+ /*set TRANSMIT-RECEIVE Mode*/
+ chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+ chconf |= OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ /*Shift in and out 1 byte at time*/
+ for (i=0; i < len; i++){
+ /* Write: wait for TX empty (TXS == 1)*/
+ irqstatus |= (1<< (4*(ds->slave.bus)));
+ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ OMAP3_MCSPI_CHSTAT_TXS)) {
+ if (--timeout <= 0) {
+ printf("SPI TXS timed out, status=0x%08x\n",
+ readl(&ds->regs->channel[ds->slave.cs].chstat));
+ return -1;
+ }
+ }
+ /* Write the data */
+ writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
+
+ /*Read: wait for RX containing data (RXS == 1)*/
+ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ OMAP3_MCSPI_CHSTAT_RXS)) {
+ if (--timeout <= 0) {
+ printf("SPI RXS timed out, status=0x%08x\n",
+ readl(&ds->regs->channel[ds->slave.cs].chstat));
+ return -1;
+ }
+ }
+ /* Read the data */
+ rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
+ }
+
+ /*if transfer must be terminated disable the channel*/
+ if (flags & SPI_XFER_END) {
+ chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ }
+
+ return 0;
+}
+
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
}
ret = 0;
} else {
- if (dout != NULL)
+ if (dout != NULL && din != NULL)
+ ret = omap3_spi_txrx(slave, len, txp, rxp, flags);
+ else if (dout != NULL)
ret = omap3_spi_write(slave, len, txp, flags);
-
- if (din != NULL)
+ else if (din != NULL)
ret = omap3_spi_read(slave, len, rxp, flags);
}
return ret;
return container_of(slave, struct omap3_spi_slave, slave);
}
+int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const u8 *txp,
+ u8 *rxp, unsigned long flags);
int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
unsigned long flags);
int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
/*
* SH SPI driver
*
- * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011-2012 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
{
}
+static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
+{
+ unsigned long val = 0;
+
+ if (cs & 0x01)
+ val |= SH_SPI_SSS0;
+ if (cs & 0x02)
+ val |= SH_SPI_SSS1;
+
+ sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
+ sh_spi_set_bit(val, &ss->regs->cr4);
+}
+
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
sh_spi_write(0x00, &ss->regs->cr1);
/* CR3 init */
sh_spi_write(0x00, &ss->regs->cr3);
+ sh_spi_set_cs(ss, cs);
clear_fifo(ss);
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
- /* This driver supports "bus = 0" and "cs = 0" only. */
- if (!bus && !cs)
+ if (!bus && cs < SH_SPI_NUM_CS)
return 1;
else
return 0;
#define SH_SPI_TBFI 0x40
#define SH_SPI_RBEI 0x20
#define SH_SPI_RBFI 0x10
+#define SH_SPI_SSS1 0x08
#define SH_SPI_WPABRT 0x04
-#define SH_SPI_SSS 0x01
+#define SH_SPI_SSS0 0x01
#define SH_SPI_FIFO_SIZE 32
+#define SH_SPI_NUM_CS 4
struct sh_spi {
struct spi_slave slave;
COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
+COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
COBJS := $(COBJS-y)
#endif
ehci_writel(reg_ptr, tmp);
}
+
+#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
+ cmd = ehci_readl(&hcor->or_txfilltuning);
+ cmd &= ~TXFIFO_THRESH(0x3f);
+ cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
+ ehci_writel(&hcor->or_txfilltuning, cmd);
+#endif
out:
return ret;
}
--- /dev/null
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <errno.h>
+#include <linux/compiler.h>
+#include <usb/ehci-fsl.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6x_pins.h>
+#include <asm/arch/iomux-v3.h>
+
+#include "ehci.h"
+#include "ehci-core.h"
+
+#define USB_OTGREGS_OFFSET 0x000
+#define USB_H1REGS_OFFSET 0x200
+#define USB_H2REGS_OFFSET 0x400
+#define USB_H3REGS_OFFSET 0x600
+#define USB_OTHERREGS_OFFSET 0x800
+
+#define USB_H1_CTRL_OFFSET 0x04
+
+#define USBPHY_CTRL 0x00000030
+#define USBPHY_CTRL_SET 0x00000034
+#define USBPHY_CTRL_CLR 0x00000038
+#define USBPHY_CTRL_TOG 0x0000003c
+
+#define USBPHY_PWD 0x00000000
+#define USBPHY_CTRL_SFTRST 0x80000000
+#define USBPHY_CTRL_CLKGATE 0x40000000
+#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
+#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
+
+#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
+#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
+
+#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
+#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
+#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
+#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
+
+
+#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
+
+/* USBCMD */
+#define UH1_USBCMD_OFFSET 0x140
+#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
+#define UCMD_RESET (1 << 1) /* controller reset */
+
+static void usbh1_internal_phy_clock_gate(int on)
+{
+ void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
+
+ phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
+ __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
+}
+
+static void usbh1_power_config(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ /*
+ * Some phy and power's special controls for host1
+ * 1. The external charger detector needs to be disabled
+ * or the signal at DP will be poor
+ * 2. The PLL's power and output to usb for host 1
+ * is totally controlled by IC, so the Software only needs
+ * to enable them at initializtion.
+ */
+ __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
+ ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
+ &anatop->usb2_chrg_detect);
+
+ __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
+ &anatop->usb2_pll_480_ctrl);
+
+ __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
+ ANADIG_USB2_PLL_480_CTRL_POWER |
+ ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
+ &anatop->usb2_pll_480_ctrl_set);
+}
+
+static int usbh1_phy_enable(void)
+{
+ void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
+ void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+ void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR +
+ USB_H1REGS_OFFSET +
+ UH1_USBCMD_OFFSET);
+ u32 val;
+
+ /* Stop then Reset */
+ val = __raw_readl(usb_cmd);
+ val &= ~UCMD_RUN_STOP;
+ __raw_writel(val, usb_cmd);
+ while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
+ ;
+
+ val = __raw_readl(usb_cmd);
+ val |= UCMD_RESET;
+ __raw_writel(val, usb_cmd);
+ while (__raw_readl(usb_cmd) & UCMD_RESET)
+ ;
+
+ /* Reset USBPHY module */
+ val = __raw_readl(phy_ctrl);
+ val |= USBPHY_CTRL_SFTRST;
+ __raw_writel(val, phy_ctrl);
+ udelay(10);
+
+ /* Remove CLKGATE and SFTRST */
+ val = __raw_readl(phy_ctrl);
+ val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
+ __raw_writel(val, phy_ctrl);
+ udelay(10);
+
+ /* Power up the PHY */
+ __raw_writel(0, phy_reg + USBPHY_PWD);
+ /* enable FS/LS device */
+ val = __raw_readl(phy_reg + USBPHY_CTRL);
+ val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
+ __raw_writel(val, phy_reg + USBPHY_CTRL);
+
+ return 0;
+}
+
+static void usbh1_oc_config(void)
+{
+ void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
+ void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
+ u32 val;
+
+ val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
+#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
+ /* mx6qarm2 seems to required a different setting*/
+ val &= ~UCTRL_OVER_CUR_POL;
+#else
+ val |= UCTRL_OVER_CUR_POL;
+#endif
+ __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+
+ val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
+ val |= UCTRL_OVER_CUR_DIS;
+ __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+}
+
+int ehci_hcd_init(void)
+{
+ struct usb_ehci *ehci;
+
+ enable_usboh3_clk(1);
+ mdelay(1);
+
+ /* Do board specific initialization */
+ board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
+
+#if CONFIG_MXC_USB_PORT == 1
+ /* USB Host 1 */
+ usbh1_power_config();
+ usbh1_oc_config();
+ usbh1_internal_phy_clock_gate(1);
+ usbh1_phy_enable();
+#else
+#error "MXC USB port not yet supported"
+#endif
+
+ ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
+ (0x200 * CONFIG_MXC_USB_PORT));
+ hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ hcor = (struct ehci_hcor *)((uint32_t)hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ setbits_le32(&ehci->usbmode, CM_HOST);
+
+ __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+
+ mdelay(10);
+
+ return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+ return 0;
+}
int ret;
uint32_t usb_base, cap_base;
- struct mx28_register *digctl_ctrl =
- (struct mx28_register *)HW_DIGCTL_CTRL;
+ struct mx28_register_32 *digctl_ctrl =
+ (struct mx28_register_32 *)HW_DIGCTL_CTRL;
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
{
int ret;
uint32_t tmp;
- struct mx28_register *digctl_ctrl =
- (struct mx28_register *)HW_DIGCTL_CTRL;
+ struct mx28_register_32 *digctl_ctrl =
+ (struct mx28_register_32 *)HW_DIGCTL_CTRL;
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * 2004 (c) MontaVista Software, Inc.
+ * Copyright (c) 2009 NVIDIA Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
+#include <common.h>
+#include <usb.h>
- . = ALIGN(4);
- .text :
- {
- cpu/sa1100/start.o (.text)
- *(.text)
- }
+#include "ehci.h"
+#include "ehci-core.h"
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+#include <asm/errno.h>
+#include <asm/arch/usb.h>
- . = ALIGN(4);
- .data : { *(.data) }
- . = ALIGN(4);
- .got : { *(.got) }
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+ u32 our_hccr, our_hcor;
+ /*
+ * Select the first port, as we don't have a way of selecting others
+ * yet
+ */
+ if (tegrausb_start_port(0, &our_hccr, &our_hcor))
+ return -1;
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ hccr = (struct ehci_hccr *)our_hccr;
+ hcor = (struct ehci_hcor *)our_hcor;
- . = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- __bss_end__ = .;
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+ tegrausb_stop_port();
+ return 0;
}
uint32_t or_ctrldssegment;
uint32_t or_periodiclistbase;
uint32_t or_asynclistaddr;
- uint32_t _reserved_[9];
+ uint32_t _reserved_0_;
+ uint32_t or_burstsize;
+ uint32_t or_txfilltuning;
+#define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
+ uint32_t _reserved_1_[6];
uint32_t or_configflag;
#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
$(ELF):
$(obj)%: $(obj)%.o $(LIB)
- $(LD) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \
+ $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \
-o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \
-L$(gcclibdir) -lgcc
}
static int total_sector;
-static int disk_write(__u32 startblock, __u32 getsize, __u8 *bufptr)
+static int disk_write(__u32 block, __u32 nr_blocks, void *buf)
{
- if (cur_dev == NULL)
+ if (!cur_dev || !cur_dev->block_write)
return -1;
- if (startblock + getsize > total_sector) {
+ if (cur_part_info.start + block + nr_blocks >
+ cur_part_info.start + total_sector) {
printf("error: overflow occurs\n");
return -1;
}
- startblock += part_offset;
-
- if (cur_dev->block_read) {
- return cur_dev->block_write(cur_dev->dev, startblock, getsize,
- (unsigned long *) bufptr);
- }
- return -1;
+ return cur_dev->block_write(cur_dev->dev,
+ cur_part_info.start + block, nr_blocks, buf);
}
/*
if (size % mydata->sect_size)
sect_num++;
- if (startsect + sect_num > total_sector)
+ if (startsect + sect_num > cur_part_info.start + total_sector)
return -1;
return 0;
static dir_entry *find_directory_entry(fsdata *mydata, int startsect,
char *filename, dir_entry *retdent, __u32 start)
{
- __u16 prevcksum = 0xffff;
__u32 curclust = (startsect - mydata->data_begin) / mydata->clust_size;
debug("get_dentfromdir: %s\n", filename);
#ifdef CONFIG_SUPPORT_VFAT
if ((dentptr->attr & ATTR_VFAT) &&
(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
- prevcksum =
- ((dir_slot *)dentptr)->alias_checksum;
get_long_file_name(mydata, curclust,
get_dentfromdir_block,
&dentptr, l_name);
unsigned long size)
{
dir_entry *dentptr, *retdent;
- dir_slot *slotptr;
__u32 startsect;
__u32 start_cluster;
boot_sector bs;
fsdata datablock;
fsdata *mydata = &datablock;
int cursect;
- int root_cluster, ret = -1, name_len;
+ int ret = -1, name_len;
char l_filename[VFAT_MAXLEN_BYTES];
int write_size = size;
total_sector = bs.total_sect;
if (total_sector == 0)
- total_sector = part_size;
-
- root_cluster = bs.root_cluster;
+ total_sector = cur_part_info.size;
if (mydata->fatsize == 32)
mydata->fatlength = bs.fat32_length;
goto exit;
}
} else {
- slotptr = (dir_slot *)empty_dentptr;
-
/* Set short name to set alias checksum field in dir_slot */
set_name(empty_dentptr, filename);
fill_dir_slot(mydata, &empty_dentptr, filename);
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#ifndef _NAND_SPL_H_
+#define _NAND_SPL_H_
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
+#define SPL_EXPORT (0x00000001)
- . = ALIGN(4);
- .text :
- {
- cpu/pxa/start.o (.text)
- *(.text)
- }
+#define SPL_EXPORT_FDT (0x00000001)
+#define SPL_EXPORT_ATAGS (0x00000002)
+#define SPL_EXPORT_LAST SPL_EXPORT_ATAGS
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- __bss_end__ = .;
-}
+#endif /* _NAND_SPL_H_ */
#define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */
#define CONFIG_CMD_BMP /* BMP support */
#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_BOOTZ /* boot zImage */
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
#define CONFIG_IXP425 1
#define CONFIG_ACTUX1 1
+#define CONFIG_MACH_TYPE 1479
+
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_IXP425 1
#define CONFIG_ACTUX2 1
+#define CONFIG_MACH_TYPE 1480
+
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_IXP425 1
#define CONFIG_ACTUX3 1
+#define CONFIG_MACH_TYPE 1481
+
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_IXP425 1
#define CONFIG_ACTUX4 1
+#define CONFIG_MACH_TYPE 1532
+
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/*
#define CONFIG_MENU
#define CONFIG_MENU_SHOW
#define CONFIG_FIT
-#define CONFIG_CMD_PXE
#define CONFIG_BOARD_IMG_ADDR_R 0x80000000
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_ENV_SIZE (16 << 10)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x180000
+#define CONFIG_ENV_RANGE 0x040000
#define CONFIG_ENV_OFFSET_REDUND 0x1c0000
-#define CONFIG_ENV_RANGE 0x020000
#undef CONFIG_ENV_IS_IN_FLASH
#endif
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_LOAD
#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
#define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
-#define CONFIG_SPL_TEXT_BASE 0x0000020 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_TEXT_BASE 0x00000020 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE 12320
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
+#define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE 0x100000
/* for UBL header */
#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
" 0 3000;nandrbl uboot\0" \
"writeuboot=nandrbl uboot;" \
"nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \
+ xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
" " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
"nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \
"img_writeuboot=nandrbl uboot;" \
"nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \
+ xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
";nand write ${img_addr_r} " \
xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
"img_writedfenv=ubi part ubi 2048;" \
"ubi write ${img_addr_r} default ${filesize}\0" \
"img_volume=rootfs1\0" \
- "img_writeramdisk=ubi part ubi 2048;ubifsmount ${img_volume};" \
+ "img_writeramdisk=ubi part ubi 2048;" \
"ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \
"load_img=tftp ${fit_addr_r} ${img_file}\0" \
"net_nfs=run load_kernel; " \
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
-
+#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
#define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
+#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
/* NAND boot config */
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
+/* SPL OS boot options */
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_OS_BOOT_KEY 26
+
+#define CONFIG_CMD_SPL
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
+#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
+ 0x400000)
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
+
#endif /* __CONFIG_H */
#define CONFIG_IXP425 1
#define CONFIG_DVLHOST 1
+#define CONFIG_MACH_TYPE 1343
+
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
+#define CONFIG_DA8XX_GPIO
/*
* Memory Info
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_GPIO
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_CS (1 | 121 << 8)
+#define CONFIG_SF_DEFAULT_CS (1 | 121 << 8)
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x90000000
-#define CONFIG_SYS_MEMTEST_END 0x10000
+#define CONFIG_SYS_MEMTEST_END 0x90010000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_BAUDRATE 38400
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfff3cf0c
+
#define CONFIG_MISC_INIT_R
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_LOAD_ADDR 0x800000
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "fdtaddr_r=0x600000\0" \
- "pxefile_addr_r=0x700000\0" \
- "kernel_addr_r=0x800000\0" \
- "ramdisk_addr_r=0x01000000\0" \
-
/*-----------------------------------------------------------------------
* Stack sizes
*
#define CONFIG_SYS_MEMTEST_START 0x100000
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000)
-/* Room required on the stack for the environment data */
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_IS_NOWHERE
+/* Environment data setup
+*/
+#define CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
+#define CONFIG_ENV_SIZE 0x2000 /* Size of Environ */
+#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_TEXT_BASE 0x00001000
+#define CONFIG_SYS_TEXT_BASE 0x00008000
#define CONFIG_SYS_INIT_SP_ADDR 0x01000000
#define CONFIG_SKIP_LOWLEVEL_INIT
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
+#define CONFIG_MMC_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_MXS_MMC
#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_CS 2
+#define CONFIG_SF_DEFAULT_CS 2
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_FIT 1
#define CONFIG_OF_LIBFDT 1
+#if defined(CONFIG_XILINX_AXIEMAC)
+# define CONFIG_MII 1
+# define CONFIG_CMD_MII 1
+# define CONFIG_PHY_GIGE 1
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
+# define CONFIG_PHYLIB 1
+# define CONFIG_PHY_ATHEROS 1
+# define CONFIG_PHY_BROADCOM 1
+# define CONFIG_PHY_DAVICOM 1
+# define CONFIG_PHY_LXT 1
+# define CONFIG_PHY_MARVELL 1
+# define CONFIG_PHY_MICREL 1
+# define CONFIG_PHY_NATSEMI 1
+# define CONFIG_PHY_REALTEK 1
+# define CONFIG_PHY_VITESSE 1
+#else
+# undef CONFIG_MII
+# undef CONFIG_CMD_MII
+# undef CONFIG_PHYLIB
+#endif
+
#endif /* __CONFIG_H */
#define V_PROMPT "mt_ventoux => "
#define CONFIG_SYS_PROMPT V_PROMPT
+/*
+ * Set its own mtdparts, different from common
+ */
+#undef MTDIDS_DEFAULT
+#undef MTDPARTS_DEFAULT
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
+ "1m(u-boot),256k(env1)," \
+ "256k(env2),8m(ubisystem),-(rootfs)"
+
/*
* FPGA
*/
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*
+ * DMA
+ */
+#define CONFIG_APBH_DMA
+
/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
#endif
/* SPI Flash */
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
+#define CONFIG_SF_DEFAULT_BUS 2
+#define CONFIG_SF_DEFAULT_CS 0
/* this may vary and depends on the installed chip */
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END 0x10000
+#define CONFIG_SYS_MEMTEST_END 0x80010000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x90000000
-#define CONFIG_SYS_MEMTEST_END 0x10000
+#define CONFIG_SYS_MEMTEST_END 0x90010000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x70000000
-#define CONFIG_SYS_MEMTEST_END 0x10000
+#define CONFIG_SYS_MEMTEST_END 0x70010000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x70000000
-#define CONFIG_SYS_MEMTEST_END 0x10000
+#define CONFIG_SYS_MEMTEST_END 0x70010000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_MACH_TYPE 3769
+
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuration settings for the TI OMAP 1610 H2 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP1610 1 /* which is in a 1610 */
-#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */
-
-#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_H2
-
-/* input clock of PLL */
-/* the OMAP1610 H2 has 12MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE 0x04000300
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
-#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-
-#include <configs/omap1510.h>
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp"
-#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
-#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
-
-/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
- * DPLL1. This time is further subdivided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
-#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-
-#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */
-#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */
-
-#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */
-
-#ifndef __ASSEMBLY__
-extern unsigned long omap_flash_base; /* set in flash__init */
-#endif
-#define CONFIG_SYS_FLASH_BASE omap_flash_base
-
-#elif defined(CONFIG_CS0_BOOT)
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0
-
-#else
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1
-
-#endif
-
-#define PHYS_SRAM 0x20000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
-/* addr of environment */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuation settings for the TI OMAP Innovator board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP1610 1 /* which is in a 1610 */
-#define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */
-
-#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_INNOVATOR
-
-/* input clock of PLL */
-/* the OMAP1610 Innovator has 12MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-/*
-*/
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE 0x04000300
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
-#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-
-#include <configs/omap1510.h>
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \
- root=/dev/nfs rw nfsroot=157.87.82.48:\
- /home/a0875451/mwd/myfs/target ip=dhcp"
-#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */
-#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */
-#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
-#define CONFIG_BOOTFILE "uImage" /* file to load */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
-
-/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
- * DPLL1. This time is further subdivided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
-#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-
-#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */
-#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */
-
-#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */
-
-#ifndef __ASSEMBLY__
-extern unsigned long omap_flash_base; /* set in flash__init */
-#endif
-#define CONFIG_SYS_FLASH_BASE omap_flash_base
-
-#elif defined(CONFIG_CS0_BOOT)
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0
-
-#else
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1
-
-#endif
-
-#define PHYS_SRAM 0x20000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
-/* addr of environment */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
-
-#endif /* __CONFIG_H */
#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
#define CONFIG_PDNB3 1 /* on an PDNB3 board */
+#define CONFIG_MACH_TYPE 1002
+
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
#include <asm/sizes.h>
#include "tegra2-common.h"
+/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (SeaBoard) # "
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+/* I2C */
+#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS 4
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_CMD_I2C
+
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
#endif /* __CONFIG_H */
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO 1
+/* MMCIF */
+#define CONFIG_MMC 1
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_SH_MMCIF 1
+#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
+#define CONFIG_SH_MMCIF_CLK 48000000
+
/* SH7757 board */
#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
#define SH7757LCR_GRA_OFFSET 0x1f000000
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_EXTBDINFO
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
+/*
+ * This parameter affects a TXFILLTUNING field that controls how much data is
+ * sent to the latency fifo before it is sent to the wire. Without this
+ * parameter, the default (2) causes occasional Data Buffer Errors in OUT
+ * packets depending on the buffer address and size.
+ */
+#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_DCACHE
+
+/* Total I2C ports on Tegra2 */
+#define TEGRA_I2C_NUM_CONTROLLERS 4
+
/* include default commands */
#include <config_cmd_default.h>
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
"bootcmd=run nandboot\0"
+/* SPL OS boot options */
+#define CONFIG_CMD_SPL
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
+#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
+ 0x600000)
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_OS_BOOT_KEY 55
+
+#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
+#define CONFIG_SPL_BOARD_INIT
+
#endif /* __CONFIG_H */
#include <asm/sizes.h>
#include "tegra2-common.h"
+/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (Ventana) # "
* Use gpio 4 pin 25 as chip select for SPI flash
* This corresponds to gpio 121
*/
-#define CONFIG_SPI_FLASH_CS (1 | (121 << 8))
+#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8))
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
- "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
+ "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
+ "then " \
"source 0xa0000000; " \
"else " \
"bootm 0x60000; " \
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
-#define CONFIG_PXA_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
+/*
+ * SRAM Map
+ */
+#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
+#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
+
/*
* DRAM Map
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048)
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
/*
* NOR FLASH
*/
enum fdt_compat_id {
COMPAT_UNKNOWN,
+ COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */
+ COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra2 i2c */
+ COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra2 dvc (really just i2c) */
COMPAT_COUNT,
};
+/* GPIOs are numbered from 0 */
+enum {
+ FDT_GPIO_NONE = -1U, /* an invalid GPIO used to end our list */
+
+ FDT_GPIO_ACTIVE_LOW = 1 << 0, /* input is active low (else high) */
+};
+
+/* This is the state of a GPIO pin as defined by the fdt */
+struct fdt_gpio_state {
+ const char *name; /* name of the fdt property defining this */
+ uint gpio; /* GPIO number, or FDT_GPIO_NONE if none */
+ u8 flags; /* FDT_GPIO_... flags */
+};
+
+/* This tells us whether a fdt_gpio_state record is valid or not */
+#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE)
+
/**
* Find the next numbered alias for a peripheral. This is used to enumerate
* all the peripherals of a certain type.
int fdtdec_next_alias(const void *blob, const char *name,
enum fdt_compat_id id, int *upto);
+/**
+ * Find the next compatible node for a peripheral.
+ *
+ * Do the first call with node = 0. This function will return a pointer to
+ * the next compatible node. Next time you call this function, pass the
+ * value returned, and the next node will be provided.
+ *
+ * @param blob FDT blob to use
+ * @param node Start node for search
+ * @param id Compatible ID to look for (enum fdt_compat_id)
+ * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more
+ */
+int fdtdec_next_compatible(const void *blob, int node,
+ enum fdt_compat_id id);
+
/**
* Look up an address property in a node and return it as an address.
* The property must hold either one address with no trailing data or
* Checks whether a node is enabled.
* This looks for a 'status' property. If this exists, then returns 1 if
* the status is 'ok' and 0 otherwise. If there is no status property,
- * it returns the default value.
+ * it returns 1 on the assumption that anything mentioned should be enabled
+ * by default.
*
* @param blob FDT blob
* @param node node to examine
- * @param default_val default value to return if no 'status' property exists
- * @return integer value 0/1, if found, or default_val if not
+ * @return integer value 0 (not enabled) or 1 (enabled)
*/
-int fdtdec_get_is_enabled(const void *blob, int node, int default_val);
+int fdtdec_get_is_enabled(const void *blob, int node);
/**
- * Checks whether we have a valid fdt available to control U-Boot, and panic
- * if not.
+ * Make sure we have a valid fdt available to control U-Boot.
+ *
+ * If not, a message is printed to the console if the console is ready.
+ *
+ * @return 0 if all ok, -1 if not
+ */
+int fdtdec_prepare_fdt(void);
+
+/**
+ * Checks that we have a valid fdt available to control U-Boot.
+
+ * However, if not then for the moment nothing is done, since this function
+ * is called too early to panic().
+ *
+ * @returns 0
*/
int fdtdec_check_fdt(void);
+
+/**
+ * Find the nodes for a peripheral and return a list of them in the correct
+ * order. This is used to enumerate all the peripherals of a certain type.
+ *
+ * To use this, optionally set up a /aliases node with alias properties for
+ * a peripheral. For example, for usb you could have:
+ *
+ * aliases {
+ * usb0 = "/ehci@c5008000";
+ * usb1 = "/ehci@c5000000";
+ * };
+ *
+ * Pass "usb" as the name to this function and will return a list of two
+ * nodes offsets: /ehci@c5008000 and ehci@c5000000.
+ *
+ * All nodes returned will match the compatible ID, as it is assumed that
+ * all peripherals use the same driver.
+ *
+ * If no alias node is found, then the node list will be returned in the
+ * order found in the fdt. If the aliases mention a node which doesn't
+ * exist, then this will be ignored. If nodes are found with no aliases,
+ * they will be added in any order.
+ *
+ * If there is a gap in the aliases, then this function return a 0 node at
+ * that position. The return value will also count these gaps.
+ *
+ * This function checks node properties and will not return nodes which are
+ * marked disabled (status = "disabled").
+ *
+ * @param blob FDT blob to use
+ * @param name Root name of alias to search for
+ * @param id Compatible ID to look for
+ * @param node_list Place to put list of found nodes
+ * @param maxcount Maximum number of nodes to find
+ * @return number of nodes found on success, FTD_ERR_... on error
+ */
+int fdtdec_find_aliases_for_id(const void *blob, const char *name,
+ enum fdt_compat_id id, int *node_list, int maxcount);
+
+/*
+ * This function is similar to fdtdec_find_aliases_for_id() except that it
+ * adds to the node_list that is passed in. Any 0 elements are considered
+ * available for allocation - others are considered already used and are
+ * skipped.
+ *
+ * You can use this by calling fdtdec_find_aliases_for_id() with an
+ * uninitialised array, then setting the elements that are returned to -1,
+ * say, then calling this function, perhaps with a different compat id.
+ * Any elements you get back that are >0 are new nodes added by the call
+ * to this function.
+ *
+ * Note that if you have some nodes with aliases and some without, you are
+ * sailing close to the wind. The call to fdtdec_find_aliases_for_id() with
+ * one compat_id may fill in positions for which you have aliases defined
+ * for another compat_id. When you later call *this* function with the second
+ * compat_id, the alias positions may already be used. A debug warning may
+ * be generated in this case, but it is safest to define aliases for all
+ * nodes when you care about the ordering.
+ */
+int fdtdec_add_aliases_for_id(const void *blob, const char *name,
+ enum fdt_compat_id id, int *node_list, int maxcount);
+
+/*
+ * Get the name for a compatible ID
+ *
+ * @param id Compatible ID to look for
+ * @return compatible string for that id
+ */
+const char *fdtdec_get_compatible(enum fdt_compat_id id);
+
+/* Look up a phandle and follow it to its node. Then return the offset
+ * of that node.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @return node offset if found, -ve error code on error
+ */
+int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name);
+
+/**
+ * Look up a property in a node and return its contents in an integer
+ * array of given length. The property must have at least enough data for
+ * the array (4*count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param array array to fill with data
+ * @param count number of array elements
+ * @return 0 if ok, or -FDT_ERR_NOTFOUND if the property is not found,
+ * or -FDT_ERR_BADLAYOUT if not enough data
+ */
+int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
+ u32 *array, int count);
+
+/**
+ * Look up a boolean property in a node and return it.
+ *
+ * A boolean properly is true if present in the device tree and false if not
+ * present, regardless of its value.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @return 1 if the properly is present; 0 if it isn't present
+ */
+int fdtdec_get_bool(const void *blob, int node, const char *prop_name);
+
+/**
+ * Decode a single GPIOs from an FDT.
+ *
+ * If the property is not found, then the GPIO structure will still be
+ * initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to
+ * provide optional GPIOs.
+ *
+ * @param blob FDT blob to use
+ * @param node Node to look at
+ * @param prop_name Node property name
+ * @param gpio gpio elements to fill from FDT
+ * @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing.
+ */
+int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name,
+ struct fdt_gpio_state *gpio);
+
+/**
+ * Set up a GPIO pin according to the provided gpio information. At present this
+ * just requests the GPIO.
+ *
+ * If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to
+ * deal with optional GPIOs.
+ *
+ * @param gpio GPIO info to use for set up
+ * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error
+ */
+int fdtdec_setup_gpio(struct fdt_gpio_state *gpio);
#endif
} bootm_headers_t;
+extern bootm_headers_t images;
+
/*
* Some systems (for example LWMON) have very short watchdog periods;
* we must make sure to split long operations like memmove() or
#include <commproc.h>
#endif /* CONFIG_8xx */
+#include <asm/cache.h>
#include <asm/byteorder.h> /* for nton* / ntoh* stuff */
# define PKTBUFSRX 4
#endif
-#define PKTALIGN 32
+#define PKTALIGN ARCH_DMA_MINALIGN
/* IPv4 addresses are always 32 bits in size */
typedef u32 IPaddr_t;
struct pci_region *mem,
struct pci_region *prefetch,
struct pci_region *io);
+extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
+ pci_dev_t dev, int sub_bus);
+extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
+ pci_dev_t dev, int sub_bus);
extern void pciauto_config_init(struct pci_controller *hose);
-int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
+extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
#endif
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \
- || defined(CONFIG_PXA_PCMCIA)
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
extern int check_ide_device(int slot);
#endif
COBJS-y += display_options.o
COBJS-y += errno.o
COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o
+COBJS-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
COBJS-$(CONFIG_GZIP) += gunzip.o
COBJS-y += hashtable.o
COBJS-$(CONFIG_LMB) += lmb.o
COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += display_options.o
endif
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
+endif
COBJS-y += ctype.o
COBJS-y += div64.o
COBJS-y += string.o
#include <libfdt.h>
#include <fdtdec.h>
+/* we need the generic GPIO interface here */
+#include <asm-generic/gpio.h>
+
DECLARE_GLOBAL_DATA_PTR;
/*
*/
#define COMPAT(id, name) name
static const char * const compat_names[COMPAT_COUNT] = {
+ COMPAT(UNKNOWN, "<none>"),
+ COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
+ COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"),
+ COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"),
};
+const char *fdtdec_get_compatible(enum fdt_compat_id id)
+{
+ /* We allow reading of the 'unknown' ID for testing purposes */
+ assert(id >= 0 && id < COMPAT_COUNT);
+ return compat_names[id];
+}
+
/**
* Look in the FDT for an alias with the given name and return its node.
*
return default_val;
}
-int fdtdec_get_is_enabled(const void *blob, int node, int default_val)
+int fdtdec_get_is_enabled(const void *blob, int node)
{
const char *cell;
+ /*
+ * It should say "okay", so only allow that. Some fdts use "ok" but
+ * this is a bug. Please fix your device tree source file. See here
+ * for discussion:
+ *
+ * http://www.mail-archive.com/u-boot@lists.denx.de/msg71598.html
+ */
cell = fdt_getprop(blob, node, "status", NULL);
if (cell)
- return 0 == strcmp(cell, "ok");
- return default_val;
+ return 0 == strcmp(cell, "okay");
+ return 1;
}
enum fdt_compat_id fd_dec_lookup(const void *blob, int node)
/* snprintf() is not available */
assert(strlen(name) < MAX_STR_LEN);
sprintf(str, "%.*s%d", MAX_STR_LEN, name, *upto);
- (*upto)++;
node = find_alias_node(blob, str);
if (node < 0)
return node;
err = fdt_node_check_compatible(blob, node, compat_names[id]);
if (err < 0)
return err;
- return err ? -FDT_ERR_NOTFOUND : node;
+ if (err)
+ return -FDT_ERR_NOTFOUND;
+ (*upto)++;
+ return node;
+}
+
+int fdtdec_find_aliases_for_id(const void *blob, const char *name,
+ enum fdt_compat_id id, int *node_list, int maxcount)
+{
+ memset(node_list, '\0', sizeof(*node_list) * maxcount);
+
+ return fdtdec_add_aliases_for_id(blob, name, id, node_list, maxcount);
+}
+
+/* TODO: Can we tighten this code up a little? */
+int fdtdec_add_aliases_for_id(const void *blob, const char *name,
+ enum fdt_compat_id id, int *node_list, int maxcount)
+{
+ int name_len = strlen(name);
+ int nodes[maxcount];
+ int num_found = 0;
+ int offset, node;
+ int alias_node;
+ int count;
+ int i, j;
+
+ /* find the alias node if present */
+ alias_node = fdt_path_offset(blob, "/aliases");
+
+ /*
+ * start with nothing, and we can assume that the root node can't
+ * match
+ */
+ memset(nodes, '\0', sizeof(nodes));
+
+ /* First find all the compatible nodes */
+ for (node = count = 0; node >= 0 && count < maxcount;) {
+ node = fdtdec_next_compatible(blob, node, id);
+ if (node >= 0)
+ nodes[count++] = node;
+ }
+ if (node >= 0)
+ debug("%s: warning: maxcount exceeded with alias '%s'\n",
+ __func__, name);
+
+ /* Now find all the aliases */
+ for (offset = fdt_first_property_offset(blob, alias_node);
+ offset > 0;
+ offset = fdt_next_property_offset(blob, offset)) {
+ const struct fdt_property *prop;
+ const char *path;
+ int number;
+ int found;
+
+ node = 0;
+ prop = fdt_get_property_by_offset(blob, offset, NULL);
+ path = fdt_string(blob, fdt32_to_cpu(prop->nameoff));
+ if (prop->len && 0 == strncmp(path, name, name_len))
+ node = fdt_path_offset(blob, prop->data);
+ if (node <= 0)
+ continue;
+
+ /* Get the alias number */
+ number = simple_strtoul(path + name_len, NULL, 10);
+ if (number < 0 || number >= maxcount) {
+ debug("%s: warning: alias '%s' is out of range\n",
+ __func__, path);
+ continue;
+ }
+
+ /* Make sure the node we found is actually in our list! */
+ found = -1;
+ for (j = 0; j < count; j++)
+ if (nodes[j] == node) {
+ found = j;
+ break;
+ }
+
+ if (found == -1) {
+ debug("%s: warning: alias '%s' points to a node "
+ "'%s' that is missing or is not compatible "
+ " with '%s'\n", __func__, path,
+ fdt_get_name(blob, node, NULL),
+ compat_names[id]);
+ continue;
+ }
+
+ /*
+ * Add this node to our list in the right place, and mark
+ * it as done.
+ */
+ if (fdtdec_get_is_enabled(blob, node)) {
+ if (node_list[number]) {
+ debug("%s: warning: alias '%s' requires that "
+ "a node be placed in the list in a "
+ "position which is already filled by "
+ "node '%s'\n", __func__, path,
+ fdt_get_name(blob, node, NULL));
+ continue;
+ }
+ node_list[number] = node;
+ if (number >= num_found)
+ num_found = number + 1;
+ }
+ nodes[found] = 0;
+ }
+
+ /* Add any nodes not mentioned by an alias */
+ for (i = j = 0; i < maxcount; i++) {
+ if (!node_list[i]) {
+ for (; j < maxcount; j++)
+ if (nodes[j] &&
+ fdtdec_get_is_enabled(blob, nodes[j]))
+ break;
+
+ /* Have we run out of nodes to add? */
+ if (j == maxcount)
+ break;
+
+ assert(!node_list[i]);
+ node_list[i] = nodes[j++];
+ if (i >= num_found)
+ num_found = i + 1;
+ }
+ }
+
+ return num_found;
+}
+
+int fdtdec_check_fdt(void)
+{
+ /*
+ * We must have an FDT, but we cannot panic() yet since the console
+ * is not ready. So for now, just assert(). Boards which need an early
+ * FDT (prior to console ready) will need to make their own
+ * arrangements and do their own checks.
+ */
+ assert(!fdtdec_prepare_fdt());
+ return 0;
}
/*
* point if the architecture board.c files merge this will make more sense.
* Even now, it is common code.
*/
-int fdtdec_check_fdt(void)
+int fdtdec_prepare_fdt(void)
+{
+ if (((uintptr_t)gd->fdt_blob & 3) || fdt_check_header(gd->fdt_blob)) {
+ printf("No valid FDT found - please append one to U-Boot "
+ "binary, use u-boot-dtb.bin or define "
+ "CONFIG_OF_EMBED\n");
+ return -1;
+ }
+ return 0;
+}
+
+int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name)
+{
+ const u32 *phandle;
+ int lookup;
+
+ phandle = fdt_getprop(blob, node, prop_name, NULL);
+ if (!phandle)
+ return -FDT_ERR_NOTFOUND;
+
+ lookup = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*phandle));
+ return lookup;
+}
+
+/**
+ * Look up a property in a node and check that it has a minimum length.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param min_len minimum property length in bytes
+ * @param err 0 if ok, or -FDT_ERR_NOTFOUND if the property is not
+ found, or -FDT_ERR_BADLAYOUT if not enough data
+ * @return pointer to cell, which is only valid if err == 0
+ */
+static const void *get_prop_check_min_len(const void *blob, int node,
+ const char *prop_name, int min_len, int *err)
{
- /* We must have an fdt */
- if (fdt_check_header(gd->fdt_blob))
- panic("No valid fdt found - please append one to U-Boot\n"
- "binary or define CONFIG_OF_EMBED\n");
+ const void *cell;
+ int len;
+
+ debug("%s: %s\n", __func__, prop_name);
+ cell = fdt_getprop(blob, node, prop_name, &len);
+ if (!cell)
+ *err = -FDT_ERR_NOTFOUND;
+ else if (len < min_len)
+ *err = -FDT_ERR_BADLAYOUT;
+ else
+ *err = 0;
+ return cell;
+}
+
+int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
+ u32 *array, int count)
+{
+ const u32 *cell;
+ int i, err = 0;
+
+ debug("%s: %s\n", __func__, prop_name);
+ cell = get_prop_check_min_len(blob, node, prop_name,
+ sizeof(u32) * count, &err);
+ if (!err) {
+ for (i = 0; i < count; i++)
+ array[i] = fdt32_to_cpu(cell[i]);
+ }
+ return err;
+}
+
+int fdtdec_get_bool(const void *blob, int node, const char *prop_name)
+{
+ const s32 *cell;
+ int len;
+
+ debug("%s: %s\n", __func__, prop_name);
+ cell = fdt_getprop(blob, node, prop_name, &len);
+ return cell != NULL;
+}
+
+/**
+ * Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no
+ * terminating item.
+ *
+ * @param blob FDT blob to use
+ * @param node Node to look at
+ * @param prop_name Node property name
+ * @param gpio Array of gpio elements to fill from FDT. This will be
+ * untouched if either 0 or an error is returned
+ * @param max_count Maximum number of elements allowed
+ * @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would
+ * be exceeded, or -FDT_ERR_NOTFOUND if the property is missing.
+ */
+static int fdtdec_decode_gpios(const void *blob, int node,
+ const char *prop_name, struct fdt_gpio_state *gpio,
+ int max_count)
+{
+ const struct fdt_property *prop;
+ const u32 *cell;
+ const char *name;
+ int len, i;
+
+ debug("%s: %s\n", __func__, prop_name);
+ assert(max_count > 0);
+ prop = fdt_get_property(blob, node, prop_name, &len);
+ if (!prop) {
+ debug("FDT: %s: property '%s' missing\n", __func__, prop_name);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ /* We will use the name to tag the GPIO */
+ name = fdt_string(blob, fdt32_to_cpu(prop->nameoff));
+ cell = (u32 *)prop->data;
+ len /= sizeof(u32) * 3; /* 3 cells per GPIO record */
+ if (len > max_count) {
+ debug("FDT: %s: too many GPIOs / cells for "
+ "property '%s'\n", __func__, prop_name);
+ return -FDT_ERR_BADLAYOUT;
+ }
+
+ /* Read out the GPIO data from the cells */
+ for (i = 0; i < len; i++, cell += 3) {
+ gpio[i].gpio = fdt32_to_cpu(cell[1]);
+ gpio[i].flags = fdt32_to_cpu(cell[2]);
+ gpio[i].name = name;
+ }
+
+ return len;
+}
+
+int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name,
+ struct fdt_gpio_state *gpio)
+{
+ int err;
+
+ debug("%s: %s\n", __func__, prop_name);
+ gpio->gpio = FDT_GPIO_NONE;
+ gpio->name = NULL;
+ err = fdtdec_decode_gpios(blob, node, prop_name, gpio, 1);
+ return err == 1 ? 0 : err;
+}
+
+int fdtdec_setup_gpio(struct fdt_gpio_state *gpio)
+{
+ /*
+ * Return success if there is no GPIO defined. This is used for
+ * optional GPIOs)
+ */
+ if (!fdt_gpio_isvalid(gpio))
+ return 0;
+
+ if (gpio_request(gpio->gpio, gpio->name))
+ return -1;
return 0;
}
--- /dev/null
+/*
+ * Some very basic tests for fdtdec, accessed through test_fdtdec command.
+ * They are easiest to use with sandbox.
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
+#include <os.h>
+
+/* The size of our test fdt blob */
+#define FDT_SIZE (16 * 1024)
+
+/**
+ * Check if an operation failed, and if so, print an error
+ *
+ * @param oper_name Name of operation
+ * @param err Error code to check
+ *
+ * @return 0 if ok, -1 if there was an error
+ */
+static int fdt_checkerr(const char *oper_name, int err)
+{
+ if (err) {
+ printf("%s: %s: %s\n", __func__, oper_name, fdt_strerror(err));
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * Check the result of an operation and if incorrect, print an error
+ *
+ * @param oper_name Name of operation
+ * @param expected Expected value
+ * @param value Actual value
+ *
+ * @return 0 if ok, -1 if there was an error
+ */
+static int checkval(const char *oper_name, int expected, int value)
+{
+ if (expected != value) {
+ printf("%s: %s: expected %d, but returned %d\n", __func__,
+ oper_name, expected, value);
+ return -1;
+ }
+
+ return 0;
+}
+
+#define CHECK(op) if (fdt_checkerr(#op, op)) return -1
+#define CHECKVAL(op, expected) \
+ if (checkval(#op, expected, op)) \
+ return -1
+#define CHECKOK(op) CHECKVAL(op, 0)
+
+/* maximum number of nodes / aliases to generate */
+#define MAX_NODES 20
+
+/*
+ * Make a test fdt
+ *
+ * @param fdt Device tree pointer
+ * @param size Size of device tree blob
+ * @param aliases Specifies alias assignments. Format is a list of items
+ * separated by space. Items are #a where
+ * # is the alias number
+ * a is the node to point to
+ * @param nodes Specifies nodes to generate (a=0, b=1), upper case
+ * means to create a disabled node
+ */
+static int make_fdt(void *fdt, int size, const char *aliases,
+ const char *nodes)
+{
+ char name[20], value[20];
+ const char *s;
+ int fd;
+
+ CHECK(fdt_create(fdt, size));
+ CHECK(fdt_finish_reservemap(fdt));
+ CHECK(fdt_begin_node(fdt, ""));
+
+ CHECK(fdt_begin_node(fdt, "aliases"));
+ for (s = aliases; *s;) {
+ sprintf(name, "i2c%c", *s);
+ sprintf(value, "/i2c%d@0", s[1] - 'a');
+ CHECK(fdt_property_string(fdt, name, value));
+ s += 2 + (s[2] != '\0');
+ }
+ CHECK(fdt_end_node(fdt));
+
+ for (s = nodes; *s; s++) {
+ sprintf(value, "i2c%d@0", (*s & 0xdf) - 'A');
+ CHECK(fdt_begin_node(fdt, value));
+ CHECK(fdt_property_string(fdt, "compatible",
+ fdtdec_get_compatible(COMPAT_UNKNOWN)));
+ if (*s <= 'Z')
+ CHECK(fdt_property_string(fdt, "status", "disabled"));
+ CHECK(fdt_end_node(fdt));
+ }
+
+ CHECK(fdt_end_node(fdt));
+ CHECK(fdt_finish(fdt));
+ CHECK(fdt_pack(fdt));
+#if defined(DEBUG) && defined(CONFIG_SANDBOX)
+ fd = os_open("/tmp/fdtdec-text.dtb", OS_O_CREAT | OS_O_WRONLY);
+ if (fd == -1) {
+ printf("Could not open .dtb file to write\n");
+ return -1;
+ }
+ os_write(fd, fdt, size);
+ os_close(fd);
+#endif
+ return 0;
+}
+
+static int run_test(const char *aliases, const char *nodes, const char *expect)
+{
+ int list[MAX_NODES];
+ const char *s;
+ void *blob;
+ int i;
+
+ blob = malloc(FDT_SIZE);
+ if (!blob) {
+ printf("%s: out of memory\n", __func__);
+ return 1;
+ }
+
+ printf("aliases=%s, nodes=%s, expect=%s: ", aliases, nodes, expect);
+ CHECKVAL(make_fdt(blob, FDT_SIZE, aliases, nodes), 0);
+ CHECKVAL(fdtdec_find_aliases_for_id(blob, "i2c",
+ COMPAT_UNKNOWN,
+ list, ARRAY_SIZE(list)), strlen(expect));
+
+ /* Check we got the right ones */
+ for (i = 0, s = expect; *s; s++, i++) {
+ int want = *s;
+ const char *name;
+ int got = ' ';
+
+ name = list[i] ? fdt_get_name(blob, list[i], NULL) : NULL;
+ if (name)
+ got = name[3] + 'a' - '0';
+
+ if (got != want) {
+ printf("Position %d: Expected '%c', got '%c' ('%s')\n",
+ i, want, got, name);
+ return 1;
+ }
+ }
+
+ printf("pass\n");
+ return 0;
+}
+
+static int do_test_fdtdec(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ /* basic tests */
+ CHECKOK(run_test("", "", ""));
+ CHECKOK(run_test("1e 3d", "", ""));
+
+ /*
+ * 'a' represents 0, 'b' represents 1, etc.
+ * The first character is the alias number, the second is the node
+ * number. So the params mean:
+ * 0a 1b : point alias 0 to node 0 (a), alias 1 to node 1(b)
+ * ab : to create nodes 0 and 1 (a and b)
+ * ab : we expect the function to return two nodes, in
+ * the order 0, 1
+ */
+ CHECKOK(run_test("0a 1b", "ab", "ab"));
+
+ CHECKOK(run_test("0a 1c", "ab", "ab"));
+ CHECKOK(run_test("1c", "ab", "ab"));
+ CHECKOK(run_test("1b", "ab", "ab"));
+ CHECKOK(run_test("0b", "ab", "ba"));
+ CHECKOK(run_test("0b 2d", "dbc", "bcd"));
+ CHECKOK(run_test("0d 3a 1c 2b", "dbac", "dcba"));
+
+ /* things with holes */
+ CHECKOK(run_test("1b 3d", "dbc", "cb d"));
+ CHECKOK(run_test("1e 3d", "dbc", "bc d"));
+
+ /* no aliases */
+ CHECKOK(run_test("", "dbac", "dbac"));
+
+ /* disabled nodes */
+ CHECKOK(run_test("0d 3a 1c 2b", "dBac", "dc a"));
+ CHECKOK(run_test("0b 2d", "DBc", "c"));
+ CHECKOK(run_test("0b 4d 2c", "DBc", " c"));
+
+ /* conflicting aliases - first one gets it */
+ CHECKOK(run_test("2a 1a 0a", "a", " a"));
+ CHECKOK(run_test("0a 1a 2a", "a", "a"));
+
+ printf("Test passed\n");
+ return 0;
+}
+
+U_BOOT_CMD(
+ test_fdtdec, 3, 1, do_test_fdtdec,
+ "test_fdtdec",
+ "Run tests for fdtdec library");
}
}
- debug ("LZMA: Uncompresed size............ 0x%x\n", outSizeFull);
- debug ("LZMA: Compresed size.............. 0x%x\n", compressedSize);
+ debug("LZMA: Uncompresed size............ 0x%zx\n", outSizeFull);
+ debug("LZMA: Compresed size.............. 0x%zx\n", compressedSize);
g_Alloc.Alloc = SzAlloc;
g_Alloc.Free = SzFree;
*/
unsigned long post_time_ms(unsigned long base)
{
-#if defined(CONFIG_PPC) || defined(CONFIG_BLACKFIN) || \
- (defined(CONFIG_ARM) && !defined(CONFIG_KIRKWOOD))
+#if defined(CONFIG_PPC) || defined(CONFIG_BLACKFIN) || defined(CONFIG_ARM)
return (unsigned long)lldiv(get_ticks(), get_tbclk() / CONFIG_SYS_HZ)
- base;
#else
ifeq ($(wildcard $(LDSCRIPT)),)
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds
endif
+ifeq ($(wildcard $(LDSCRIPT)),)
+ LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds
+endif
ifeq ($(wildcard $(LDSCRIPT)),)
$(error could not find linker script)
endif
LDPPFLAGS += \
-include $(TOPDIR)/include/u-boot/u-boot.lds.h \
-include $(OBJTREE)/include/config.h \
+ -DCPUDIR=$(CPUDIR) \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
uint32_t base_offset;
- /* Set default offset */
- imxhdr->flash_offset = FLASH_OFFSET_STANDARD;
+ /* Exit if there is no BOOT_FROM field specifying the flash_offset */
+ if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
+ fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
+ params->imagename);
+ exit(EXIT_FAILURE);
+ }
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
- /* Set default offset */
- imxhdr->flash_offset = FLASH_OFFSET_STANDARD;
+ /* Exit if there is no BOOT_FROM field specifying the flash_offset */
+ if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
+ fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
+ params->imagename);
+ exit(EXIT_FAILURE);
+ }
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
* set up function ptr group to V1 by default.
*/
imximage_version = IMXIMAGE_V1;
+ /* Be able to detect if the cfg file has no BOOT_FROM tag */
+ imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
#define HEADER_OFFSET 0x400
#define CMD_DATA_STR "DATA"
+#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
#define FLASH_OFFSET_STANDARD 0x400
#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
+#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <unistd.h>
-#include <compiler.h>
#include <sys/types.h>
#include <sys/stat.h>
+#include <sys/mman.h>
+#include "compiler.h"
#include <u-boot/crc.h>
#include <version.h>
static void usage(const char *exec_name)
{
- fprintf(stderr, "%s [-h] [-r] [-b] [-p <byte>] "
- "-s <environment partition size> -o <output> <input file>\n"
+ fprintf(stderr, "%s [-h] [-r] [-b] [-p <byte>] -s <environment partition size> -o <output> <input file>\n"
"\n"
- "This tool takes a key=value input file (same as would a "
- "`printenv' show) and generates the corresponding environment "
- "image, ready to be flashed.\n"
+ "This tool takes a key=value input file (same as would a `printenv' show) and generates the corresponding environment image, ready to be flashed.\n"
"\n"
"\tThe input file is in format:\n"
"\t\tkey1=value1\n"
"\t\t...\n"
"\t-r : the environment has multiple copies in flash\n"
"\t-b : the target is big endian (default is little endian)\n"
- "\t-p <byte> : fill the image with <byte> bytes instead of "
- "0xff bytes\n"
+ "\t-p <byte> : fill the image with <byte> bytes instead of 0xff bytes\n"
"\t-V : print version information and exit\n"
"\n"
"If the input file is \"-\", data is read from standard input\n",
exec_name);
}
+long int xstrtol(const char *s)
+{
+ long int tmp;
+
+ errno = 0;
+ tmp = strtol(s, NULL, 0);
+ if (!errno)
+ return tmp;
+
+ if (errno == ERANGE)
+ fprintf(stderr, "Bad integer format: %s\n", s);
+ else
+ fprintf(stderr, "Error while parsing %s: %s\n", s,
+ strerror(errno));
+
+ exit(EXIT_FAILURE);
+}
+
int main(int argc, char **argv)
{
uint32_t crc, targetendian_crc;
while ((option = getopt(argc, argv, ":s:o:rbp:hV")) != -1) {
switch (option) {
case 's':
- datasize = strtol(optarg, NULL, 0);
+ datasize = xstrtol(optarg);
break;
case 'o':
bin_filename = strdup(optarg);
if (!bin_filename) {
- fprintf(stderr, "Can't strdup() the output "
- "filename\n");
+ fprintf(stderr, "Can't strdup() the output filename\n");
return EXIT_FAILURE;
}
break;
bigendian = 1;
break;
case 'p':
- padbyte = strtol(optarg, NULL, 0);
+ padbyte = xstrtol(optarg);
break;
case 'h':
usage(prg);
case ':':
fprintf(stderr, "Missing argument for option -%c\n",
optopt);
- usage(argv[0]);
+ usage(prg);
return EXIT_FAILURE;
default:
fprintf(stderr, "Wrong option -%c\n", optopt);
/* Check datasize and allocate the data */
if (datasize == 0) {
- fprintf(stderr,
- "Please specify the size of the environment "
- "partition.\n");
+ fprintf(stderr, "Please specify the size of the environment partition.\n");
usage(prg);
return EXIT_FAILURE;
}
dataptr = malloc(datasize * sizeof(*dataptr));
if (!dataptr) {
- fprintf(stderr, "Can't alloc dataptr.\n");
+ fprintf(stderr, "Can't alloc %d bytes for dataptr.\n",
+ datasize);
return EXIT_FAILURE;
}
/*
* envptr points to the beginning of the actual environment (after the
- * crc and possible `redundant' bit
+ * crc and possible `redundant' byte
*/
envsize = datasize - (CRC_SIZE + redundant);
envptr = dataptr + CRC_SIZE + redundant;
memset(envptr, padbyte, envsize);
/* Open the input file ... */
- if (optind >= argc) {
- fprintf(stderr, "Please specify an input filename\n");
- return EXIT_FAILURE;
- }
-
- txt_filename = argv[optind];
- if (strcmp(txt_filename, "-") == 0) {
+ if (optind >= argc || strcmp(argv[optind], "-") == 0) {
int readbytes = 0;
- int readlen = sizeof(*envptr) * 2048;
+ int readlen = sizeof(*envptr) * 4096;
txt_fd = STDIN_FILENO;
do {
filebuf = realloc(filebuf, readlen);
+ if (!filebuf) {
+ fprintf(stderr, "Can't realloc memory for the input file buffer\n");
+ return EXIT_FAILURE;
+ }
readbytes = read(txt_fd, filebuf + filesize, readlen);
+ if (errno) {
+ fprintf(stderr, "Error while reading stdin: %s\n",
+ strerror(errno));
+ return EXIT_FAILURE;
+ }
filesize += readbytes;
} while (readbytes == readlen);
} else {
+ txt_filename = argv[optind];
txt_fd = open(txt_filename, O_RDONLY);
if (txt_fd == -1) {
fprintf(stderr, "Can't open \"%s\": %s\n",
/* ... and check it */
ret = fstat(txt_fd, &txt_file_stat);
if (ret == -1) {
- fprintf(stderr, "Can't stat() on \"%s\": "
- "%s\n", txt_filename, strerror(errno));
+ fprintf(stderr, "Can't stat() on \"%s\": %s\n",
+ txt_filename, strerror(errno));
return EXIT_FAILURE;
}
filesize = txt_file_stat.st_size;
- /* Read the raw input file and transform it */
- filebuf = malloc(sizeof(*envptr) * filesize);
- ret = read(txt_fd, filebuf, sizeof(*envptr) * filesize);
- if (ret != sizeof(*envptr) * filesize) {
- fprintf(stderr, "Can't read the whole input file\n");
- return EXIT_FAILURE;
+
+ filebuf = mmap(NULL, sizeof(*envptr) * filesize, PROT_READ,
+ MAP_PRIVATE, txt_fd, 0);
+ if (filebuf == MAP_FAILED) {
+ fprintf(stderr, "mmap (%ld bytes) failed: %s\n",
+ sizeof(*envptr) * filesize,
+ strerror(errno));
+ fprintf(stderr, "Falling back to read()\n");
+
+ filebuf = malloc(sizeof(*envptr) * filesize);
+ ret = read(txt_fd, filebuf, sizeof(*envptr) * filesize);
+ if (ret != sizeof(*envptr) * filesize) {
+ fprintf(stderr, "Can't read the whole input file (%ld bytes): %s\n",
+ sizeof(*envptr) * filesize,
+ strerror(errno));
+
+ return EXIT_FAILURE;
+ }
}
ret = close(txt_fd);
}
- /*
- * The right test to do is "=>" (not ">") because of the additional
- * ending \0. See below.
- */
- if (filesize >= envsize) {
- fprintf(stderr, "The input file is larger than the "
- "environment partition size\n");
+ /* The +1 is for the additionnal ending \0. See below. */
+ if (filesize + 1 > envsize) {
+ fprintf(stderr, "The input file is larger than the environment partition size\n");
return EXIT_FAILURE;
}
/* End of a variable */
envptr[ep++] = '\0';
}
- } else if (filebuf[fp] == '#') {
- if (fp != 0 && filebuf[fp-1] == '\n') {
- /* This line is a comment, let's skip it */
- while (fp < txt_file_stat.st_size && fp++ &&
- filebuf[fp] != '\n');
- } else {
- envptr[ep++] = filebuf[fp];
- }
} else {
envptr[ep++] = filebuf[fp];
}
* check the env size again to make sure we have room for two \0
*/
if (ep >= envsize) {
- fprintf(stderr, "The environment file is too large for "
- "the target environment storage\n");
+ fprintf(stderr, "The environment file is too large for the target environment storage\n");
return EXIT_FAILURE;
}
envptr[ep] = '\0';
crc = crc32(0, envptr, envsize);
targetendian_crc = bigendian ? cpu_to_be32(crc) : cpu_to_le32(crc);
- memcpy(dataptr, &targetendian_crc, sizeof(uint32_t));
+ memcpy(dataptr, &targetendian_crc, sizeof(targetendian_crc));
+ if (redundant)
+ dataptr[sizeof(targetendian_crc)] = 1;
- bin_fd = creat(bin_filename, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
- if (bin_fd == -1) {
- fprintf(stderr, "Can't open output file \"%s\": %s\n",
- bin_filename, strerror(errno));
- return EXIT_FAILURE;
+ if (!bin_filename || strcmp(bin_filename, "-") == 0) {
+ bin_fd = STDOUT_FILENO;
+ } else {
+ bin_fd = creat(bin_filename, S_IRUSR | S_IWUSR | S_IRGRP |
+ S_IWGRP);
+ if (bin_fd == -1) {
+ fprintf(stderr, "Can't open output file \"%s\": %s\n",
+ bin_filename, strerror(errno));
+ return EXIT_FAILURE;
+ }
}
if (write(bin_fd, dataptr, sizeof(*dataptr) * datasize) !=
projects / people / ms / u-boot.git / commitdiff
