Merge git://git.denx.de/u-boot-fsl-qoriq

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ed1c4eeb03c07d249b0c358f40163c407401cfd1..6772584a60422c8c14ee47033e43264d59659e05 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -76,6 +76,13 @@ config SECURE_BOOT
        help
                Enable Freescale Secure Boot feature
 
+config QSPI_AHB_INIT
+       bool "Init the QSPI AHB bus"
+       help
+         The default setting for QSPI AHB bus just support 3bytes addressing.
+         But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
+         bus for those flashes to support the full QSPI flash size.
+
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
        depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d6ee54642d214cb1445adab7965e09f6110c12b5..ffbbd729d461da29f4395cfd25d144d3cf8248b8 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -26,6 +26,9 @@
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
 #endif
+#ifdef CONFIG_SYS_FSL_DDR
+#include <fsl_ddr.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -403,7 +406,9 @@ int arch_early_init_r(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
        erratum_a009635();
 #endif
-
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
+       erratum_a009942_check_cpo();
+#endif
 #ifdef CONFIG_MP
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
        /* Check the psci version to determine if the psci is supported */

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index 67d605e38b1812ce9673fa2ac10bb3500e6e5df7..ab83e85adcda609d5af46f2bede1fd83b018ed05 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
@@ -36,6 +36,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
        {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
        {0x39, {SGMII8, SGMII7, SGMII6, PCIE2, SGMII4, SGMII3, SGMII2,
                PCIE1 } },
+       {0x3B, {XFI8, XFI7, XFI6, PCIE2, XFI4, XFI3, XFI2, PCIE1 } },
        {0x4B, {PCIE2, PCIE2, PCIE2, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
        {0x4C, {XFI8, XFI7, XFI6, XFI5, PCIE1, PCIE1, PCIE1, PCIE1 } },
        {0x4D, {SGMII8, SGMII7, PCIE2, PCIE2, SGMII4, SGMII3, PCIE1, PCIE1 } },

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6c4238707d1c32a44a16c3da479bd495b4386478..2f54625d42b90ee4d3836e3dc0efcfc45857d494 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -373,6 +373,45 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_QSPI_AHB_INIT
+/* Enable 4bytes address support and fast read */
+int qspi_ahb_init(void)
+{
+       u32 *qspi_lut, lut_key, *qspi_key;
+
+       qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
+       qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
+
+       lut_key = in_be32(qspi_key);
+
+       if (lut_key == 0x5af05af0) {
+               /* That means the register is BE */
+               out_be32(qspi_key, 0x5af05af0);
+               /* Unlock the lut table */
+               out_be32(qspi_key + 1, 0x00000002);
+               out_be32(qspi_lut, 0x0820040c);
+               out_be32(qspi_lut + 1, 0x1c080c08);
+               out_be32(qspi_lut + 2, 0x00002400);
+               /* Lock the lut table */
+               out_be32(qspi_key, 0x5af05af0);
+               out_be32(qspi_key + 1, 0x00000001);
+       } else {
+               /* That means the register is LE */
+               out_le32(qspi_key, 0x5af05af0);
+               /* Unlock the lut table */
+               out_le32(qspi_key + 1, 0x00000002);
+               out_le32(qspi_lut, 0x0820040c);
+               out_le32(qspi_lut + 1, 0x1c080c08);
+               out_le32(qspi_lut + 2, 0x00002400);
+               /* Lock the lut table */
+               out_le32(qspi_key, 0x5af05af0);
+               out_le32(qspi_key + 1, 0x00000001);
+       }
+
+       return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -382,6 +421,9 @@ int board_late_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
        fsl_setenv_chain_of_trust();
 #endif
+#ifdef CONFIG_QSPI_AHB_INIT
+       qspi_ahb_init();
+#endif
 
        return 0;
 }

diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 119b1afeb7f1d2b6b182ac42fc71746857938bc3..37be16905b9c6d7c9b55e6c620ec10c47fb6c783 100644 (file)
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -176,6 +176,7 @@
                        #size-cells = <0>;
                        reg = <0x1550000 0x10000>,
                                <0x40000000 0x4000000>;
+                       reg-names = "QuadSPI", "QuadSPI-memory";
                        num-cs = <2>;
                        big-endian;
                        status = "disabled";

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d684a077303618870423ca431e216b61abf85d45..b3cfd89a4b65d70c54398910f6050a89d331a55b 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)
 #define CONFIG_SYS_GIC400_ADDR                 (CONFIG_SYS_IMMR + 0x00400000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x00530000)
+#define SYS_FSL_QSPI_ADDR                      (CONFIG_SYS_IMMR + 0x00550000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_CSU_ADDR                        (CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_FSL_GUTS_ADDR               (CONFIG_SYS_IMMR + 0x00ee0000)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 2df56f7a5b20adb9b18369d816ff7b652c8cdcff..e18dcbdd0900348281a9042d4ff16d637020cc90 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR       (CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR       (CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR       (CONFIG_SYS_IMMR + 0x00370000)
+#define SYS_FSL_QSPI_ADDR                      (CONFIG_SYS_IMMR + 0x010c0000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1                        (CONFIG_SYS_IMMR + 0x011C0500)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index c2402a8bda2bfdd32b95171a16d919ecfacfa653..d1b6699a6a1d96981c7788f358141f90e80d0c05 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -45,7 +45,9 @@
 #include <nand.h>
 #include <errno.h>
 #endif
-
+#ifndef CONFIG_ARCH_QEMU_E500
+#include <fsl_ddr.h>
+#endif
 #include "../../../../drivers/block/fsl_sata.h"
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
@@ -947,6 +949,10 @@ int cpu_init_r(void)
 
 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+       erratum_a009942_check_cpo();
+#endif
+
 #ifdef CONFIG_FMAN_ENET
        fman_enet_init();
 #endif

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4877b759815658777a8611b6c8af56aced16d58f..603d6aeadc315db7428f8361529efaf3c92e0c6e 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -512,7 +512,6 @@
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186
@@ -549,7 +548,6 @@
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 4eb38a73c901050761cced88c6498e4b2260d88e..79078d237b44731ecf8b49efe4459c10fa002df8 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -22,7 +22,7 @@
 #include <spl.h>
 #include <fsl_devdis.h>
 #include <fsl_validate.h>
-
+#include <fsl_ddr.h>
 #include "../common/sleep.h"
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
@@ -433,7 +433,9 @@ int board_init(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
        erratum_a010315();
 #endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+       erratum_a009942_check_cpo();
+#endif
        major = get_soc_major_rev();
        if (major == SOC_MAJOR_VER_1_0) {
                /* Set CCI-400 control override register to

diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 1f3d487dcb32616e2615aeed6448f2aced90c0f8..c83b2ebafd726b4bea88e9be00c7b8b12febb7a9 100644 (file)
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -34,3 +34,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_QSPI_AHB_INIT=y

diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index c0514aedb0b4d28c4e141b23acb6ba647ed78605..27bccd1227634dd221f845e7252380cc66b52b8c 100644 (file)
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -38,3 +38,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_QSPI_AHB_INIT=y

diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 13c9f2107d9be83a55f5c428d03b89252b34b76f..459682dc5a102886f4f4a0f2c1f91b11fcd3e29e 100644 (file)
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -38,3 +38,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_QSPI_AHB_INIT=y

diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 8508c09336808f62843abe89d5417bb60ff5f2a0..fa173739fb4513f945d0241da92eaf2d09825ccc 100644 (file)
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -24,3 +24,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_QSPI_AHB_INIT=y

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 32b09679e2ec4fa9a24ad88ab03ddf9c4cb59fe8..f7e87b8ee9d2532bca6ae971f3ead304b99d09ba 100644 (file)
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -5,14 +5,14 @@
  */
 
 /*
- * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
+ * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
  * Based on code from spd_sdram.c
  * Author: James Yang [at freescale.com]
  */
 
 #include <common.h>
 #include <fsl_ddr_sdram.h>
-
+#include <fsl_errata.h>
 #include <fsl_ddr.h>
 #include <fsl_immap.h>
 #include <asm/io.h>
@@ -2306,6 +2306,38 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
        unsigned int ip_rev = 0;
        unsigned int unq_mrs_en = 0;
        int cs_en = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+       unsigned int ddr_freq;
+#endif
+#if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
+       defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
+       defined(CONFIG_SYS_FSL_ERRATUM_A009942)
+       struct ccsr_ddr __iomem *ddrc;
+
+       switch (ctrl_num) {
+       case 0:
+               ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+               break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+       case 1:
+               ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+               break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+       case 2:
+               ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+               break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+       case 3:
+               ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+               break;
+#endif
+       default:
+               printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
+               return 1;
+       }
+#endif
 
        memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
 
@@ -2526,5 +2558,105 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
                ddr->debug[2] |= 0x00000200;    /* set bit 22 */
 #endif
 
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
+       /* Erratum applies when accumulated ECC is used, or DBI is enabled */
+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
+       if (has_erratum_a008378()) {
+               if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
+                   IS_DBI(ddr->ddr_sdram_cfg_3)) {
+                       ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
+                       ddr->debug[28] |= (0x9 << 20);
+               }
+       }
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+       ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+       ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
+       ddr->debug[28] &= 0xff0fff00;
+       if (ddr_freq <= 1333)
+               ddr->debug[28] |= 0x0080006a;
+       else if (ddr_freq <= 1600)
+               ddr->debug[28] |= 0x0070006f;
+       else if (ddr_freq <= 1867)
+               ddr->debug[28] |= 0x00700076;
+       else if (ddr_freq <= 2133)
+               ddr->debug[28] |= 0x0060007b;
+       if (popts->cpo_sample)
+               ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
+                                 popts->cpo_sample;
+#endif
+
        return check_fsl_memctl_config_regs(ddr);
 }
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+/*
+ * This additional workaround of A009942 checks the condition to determine if
+ * the CPO value set by the existing A009942 workaround needs to be updated.
+ * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
+ * expected optimal value, the optimal value is highly board dependent.
+ */
+void erratum_a009942_check_cpo(void)
+{
+       struct ccsr_ddr __iomem *ddr =
+               (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+       u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
+       u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
+       u32 cpo_max = cpo_min;
+       u32 sdram_cfg, i, tmp, lanes, ddr_type;
+       bool update_cpo = false, has_ecc = false;
+
+       sdram_cfg = ddr_in32(&ddr->sdram_cfg);
+       if (sdram_cfg & SDRAM_CFG_32_BE)
+               lanes = 4;
+       else if (sdram_cfg & SDRAM_CFG_16_BE)
+               lanes = 2;
+       else
+               lanes = 8;
+
+       if (sdram_cfg & SDRAM_CFG_ECC_EN)
+               has_ecc = true;
+
+       /* determine the maximum and minimum CPO values */
+       for (i = 9; i < 9 + lanes / 2; i++) {
+               cpo = ddr_in32(&ddr->debug[i]);
+               cpo_e = cpo >> 24;
+               cpo_o = (cpo >> 8) & 0xff;
+               tmp = min(cpo_e, cpo_o);
+               if (tmp < cpo_min)
+                       cpo_min = tmp;
+               tmp = max(cpo_e, cpo_o);
+               if (tmp > cpo_max)
+                       cpo_max = tmp;
+       }
+
+       if (has_ecc) {
+               cpo = ddr_in32(&ddr->debug[13]);
+               cpo = cpo >> 24;
+               if (cpo < cpo_min)
+                       cpo_min = cpo;
+               if (cpo > cpo_max)
+                       cpo_max = cpo;
+       }
+
+       cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
+       cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
+       debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
+             cpo_target);
+       debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
+
+       ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
+                   SDRAM_CFG_SDRAM_TYPE_SHIFT;
+       if (ddr_type == SDRAM_TYPE_DDR4)
+               update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
+       else if (ddr_type == SDRAM_TYPE_DDR3)
+               update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
+
+       if (update_cpo) {
+               printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
+               printf("in <board>/ddr.c to optimize cpo\n");
+       }
+}
+#endif

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 042af09770f4623f0bd3abd271c9cdf3a968db94..dadcb3abc39b81450b54a3c11e1046aa53c63589 100644 (file)
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -47,13 +47,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 {
        unsigned int i, bus_width;
        struct ccsr_ddr __iomem *ddr;
-       u32 temp_sdram_cfg;
+       u32 temp32;
        u32 total_gb_size_per_controller;
        int timeout;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
-       defined(CONFIG_SYS_FSL_ERRATUM_A009801)
-       u32 temp32;
-#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
        u32 mr6;
@@ -61,11 +57,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
        u32 *vref_seq = vref_seq1;
 #endif
-#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
-       defined(CONFIG_SYS_FSL_ERRATUM_A010165)
-       ulong ddr_freq;
-       u32 tmp;
-#endif
 #ifdef CONFIG_FSL_DDR_BIST
        u32 mtcr, err_detect, err_sbe;
        u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
@@ -73,7 +64,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #ifdef CONFIG_FSL_DDR_BIST
        char buffer[CONFIG_SYS_CBSIZE];
 #endif
-
        switch (ctrl_num) {
        case 0:
                ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
@@ -230,16 +220,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                        ddr_out32(&ddr->debug[i], regs->debug[i]);
                }
        }
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
-       /* Erratum applies when accumulated ECC is used, or DBI is enabled */
-#define IS_ACC_ECC_EN(v) ((v) & 0x4)
-#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
-       if (has_erratum_a008378()) {
-               if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
-                   IS_DBI(regs->ddr_sdram_cfg_3))
-                       ddr_setbits32(&ddr->debug[28], 0x9 << 20);
-       }
-#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
        /* Part 1 of 2 */
@@ -277,24 +257,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->debug[25], temp32);
 #endif
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
-       ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
-       tmp = ddr_in32(&ddr->debug[28]);
-       if (ddr_freq <= 1333)
-               ddr_out32(&ddr->debug[28], tmp | 0x0080006a);
-       else if (ddr_freq <= 1600)
-               ddr_out32(&ddr->debug[28], tmp | 0x0070006f);
-       else if (ddr_freq <= 1867)
-               ddr_out32(&ddr->debug[28], tmp | 0x00700076);
-       else if (ddr_freq <= 2133)
-               ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
-#endif
-
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
-       ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
-       if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
-               tmp = ddr_in32(&ddr->debug[28]);
-               ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
+       temp32 = get_ddr_freq(ctrl_num) / 1000000;
+       if ((temp32 > 1900) && (temp32 < 2300)) {
+               temp32 = ddr_in32(&ddr->debug[28]);
+               ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
        }
 #endif
        /*
@@ -312,9 +279,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
 step2:
        /* Set, but do not enable the memory */
-       temp_sdram_cfg = regs->ddr_sdram_cfg;
-       temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
-       ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
+       temp32 = regs->ddr_sdram_cfg;
+       temp32 &= ~(SDRAM_CFG_MEM_EN);
+       ddr_out32(&ddr->sdram_cfg, temp32);
 
        /*
         * 500 painful micro-seconds must elapse between
@@ -329,18 +296,18 @@ step2:
 #ifdef CONFIG_DEEP_SLEEP
        if (is_warm_boot()) {
                /* enter self-refresh */
-               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
-               temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
-               ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+               temp32 = ddr_in32(&ddr->sdram_cfg_2);
+               temp32 |= SDRAM_CFG2_FRC_SR;
+               ddr_out32(&ddr->sdram_cfg_2, temp32);
                /* do board specific memory setup */
                board_mem_sleep_setup();
 
-               temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+               temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
        } else
 #endif
-               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+               temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
        /* Let the controller go */
-       ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+       ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
        mb();
        isb();
 
@@ -483,9 +450,9 @@ step2:
 #ifdef CONFIG_DEEP_SLEEP
        if (is_warm_boot()) {
                /* exit self-refresh */
-               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
-               temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
-               ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+               temp32 = ddr_in32(&ddr->sdram_cfg_2);
+               temp32 &= ~SDRAM_CFG2_FRC_SR;
+               ddr_out32(&ddr->sdram_cfg_2, temp32);
        }
 #endif
 

diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 653b7f0c770c965f0e31f84271c478d441413d06..1bfb9d4097ced8f0bb1f604649a1773b554fe0e0 100644 (file)
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -174,9 +174,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                        out_be32(&ddr->debug[i], regs->debug[i]);
                }
        }
-#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
-       out_be32(&ddr->debug[28], 0x30003000);
-#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
        out_be32(&ddr->debug[12], 0x00000015);

diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 0dc3dd8117058b8c0c016ca0ad23d55c98d141b7..6069c935c12e6e2fe95e0a0f3c303507d3c199c5 100644 (file)
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -138,6 +138,10 @@ bool has_erratum_a005697(void)
        case SVR_9131:
        case SVR_9132:
                return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+#ifdef ONFIG_ARM64
+       case SVR_LS1012A:
+               return IS_SVR_REV(svr, 1, 0);
 #endif
        }
        return false;

diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 3351acdd7aed4b9715f83b2f3b9d8e78aeee3d86..0c3be0e2e02a8336754b7b62af759251b1633047 100644 (file)
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -138,4 +138,6 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 void update_spd_address(unsigned int ctrl_num,
                        unsigned int slot,
                        unsigned int *addr);
+
+void erratum_a009942_check_cpo(void);
 #endif

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 36bd9d7c934a7a299a147a5c0c0d29bb15d8aa60..1404c5793607089c519c8d8f6dfe0fc9ef18fe57 100644 (file)
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -374,7 +374,8 @@ typedef struct memctl_options_s {
        unsigned int additive_latency_override_value;
 
        unsigned int clk_adjust;                /* */
-       unsigned int cpo_override;
+       unsigned int cpo_override;              /* override timing_cfg_2[CPO]*/
+       unsigned int cpo_sample;                /* optimize debug_29[24:31] */
        unsigned int write_data_delay;          /* DQS adjust */
 
        unsigned int cswl_override;