86xx: Add support for 'cpu disable' command

Support disabling of a core via user command 'cpu disable'.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c
index ecdf2fb389b9eea35cf1f98e8967082bbba61c3d..b4a0faacde0c8bcc11914e49492603e07ec911d2 100644 (file)
--- a/cpu/mpc86xx/mp.c
+++ b/cpu/mpc86xx/mp.c
@@ -48,8 +48,22 @@ int cpu_status(int nr)
 
 int cpu_disable(int nr)
 {
-       /* dummy function so common/cmd_mp.c will build */
-       return 1;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+
+       switch (nr) {
+       case 0:
+               setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
+               break;
+       case 1:
+               setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
+               break;
+       default:
+               printf("Invalid cpu number for disable %d\n", nr);
+               return 1;
+       }
+
+       return 0;
 }
 
 int cpu_release(int nr, int argc, char *argv[])

diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 098f25384b7b5ee568beb96f43f71a83f62a60b7..fd7acdb767447aed5d78bff43793d6338dafb8ca 100644 (file)
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1186,17 +1186,8 @@ typedef struct ccsr_rio {
 typedef struct ccsr_gur {
        uint    porpllsr;       /* 0xe0000 - POR PLL ratio status register */
        uint    porbmsr;        /* 0xe0004 - POR boot mode status register */
-#define MPC8610_PORBMSR_HA      0x00070000
-#define MPC8610_PORBMSR_HA_SHIFT       16
-#define MPC8641_PORBMSR_HA      0x00060000
-#define MPC8641_PORBMSR_HA_SHIFT       17
        uint    porimpscr;      /* 0xe0008 - POR I/O impedance status and control register */
        uint    pordevsr;       /* 0xe000c - POR I/O device status regsiter */
-#define MPC8610_PORDEVSR_IO_SEL                0x00380000
-#define MPC8610_PORDEVSR_IO_SEL_SHIFT          19
-#define MPC8641_PORDEVSR_IO_SEL                0x000F0000
-#define MPC8641_PORDEVSR_IO_SEL_SHIFT          16
-#define MPC86xx_PORDEVSR_CORE1TE       0x00000080 /* ASMP (Core1 addr trans) */
        uint    pordbgmsr;      /* 0xe0010 - POR debug mode status register */
        char    res1[12];
        uint    gpporcr;        /* 0xe0020 - General-purpose POR configuration register */
@@ -1210,11 +1201,6 @@ typedef struct ccsr_gur {
        uint    pmuxcr;         /* 0xe0060 - Alternate function signal multiplex control */
        char    res6[12];
        uint    devdisr;        /* 0xe0070 - Device disable control */
-#define MPC86xx_DEVDISR_PCIEX1 0x80000000
-#define MPC86xx_DEVDISR_PCIEX2 0x40000000
-#define MPC86xx_DEVDISR_PCI1   0x80000000
-#define MPC86xx_DEVDISR_PCIE1  0x40000000
-#define MPC86xx_DEVDISR_PCIE2  0x20000000
        char    res7[12];
        uint    powmgtcsr;      /* 0xe0080 - Power management status and control register */
        char    res8[12];
@@ -1225,7 +1211,6 @@ typedef struct ccsr_gur {
        uint    svr;            /* 0xe00a4 - System version register */
        char    res10a[8];
        uint    rstcr;          /* 0xe00b0 - Reset control register */
-#define MPC86xx_RSTCR_HRST_REQ 0x00000002
        char    res10b[1868];
        uint    clkdvdr;        /* 0xe0800 - Clock Divide register */
        char    res10c[796];
@@ -1250,6 +1235,24 @@ typedef struct ccsr_gur {
        char    res16[184];
 } ccsr_gur_t;
 
+#define MPC8610_PORBMSR_HA      0x00070000
+#define MPC8610_PORBMSR_HA_SHIFT       16
+#define MPC8641_PORBMSR_HA      0x00060000
+#define MPC8641_PORBMSR_HA_SHIFT       17
+#define MPC8610_PORDEVSR_IO_SEL                0x00380000
+#define MPC8610_PORDEVSR_IO_SEL_SHIFT          19
+#define MPC8641_PORDEVSR_IO_SEL                0x000F0000
+#define MPC8641_PORDEVSR_IO_SEL_SHIFT          16
+#define MPC86xx_PORDEVSR_CORE1TE       0x00000080 /* ASMP (Core1 addr trans) */
+#define MPC86xx_DEVDISR_PCIEX1 0x80000000
+#define MPC86xx_DEVDISR_PCIEX2 0x40000000
+#define MPC86xx_DEVDISR_PCI1   0x80000000
+#define MPC86xx_DEVDISR_PCIE1  0x40000000
+#define MPC86xx_DEVDISR_PCIE2  0x20000000
+#define MPC86xx_DEVDISR_CPU0   0x00008000
+#define MPC86xx_DEVDISR_CPU1   0x00004000
+#define MPC86xx_RSTCR_HRST_REQ 0x00000002
+
 /*
  * Watchdog register block(0xe_4000-0xe_4fff)
  */