obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+else
+obj-y += spr_misc.o spr_lowlevel_init.o
endif
extra-$(CONFIG_SPL_BUILD) := start.o
}
#endif
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
}
#endif
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+/* Remove JR node used by SEC firmware */
+void fdt_fixup_remove_jr(void *blob)
+{
+ int jr_node, addr_cells, len;
+ int crypto_node = fdt_path_offset(blob, "crypto");
+ u64 jr_offset, used_jr;
+ fdt32_t *reg;
+
+ used_jr = sec_firmware_used_jobring_offset();
+ fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
+
+ jr_node = fdt_node_offset_by_compatible(blob, crypto_node,
+ "fsl,sec-v4.0-job-ring");
+
+ while (jr_node != -FDT_ERR_NOTFOUND) {
+ reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
+ jr_offset = fdt_read_number(reg, addr_cells);
+ if (jr_offset == used_jr) {
+ fdt_del_node(blob, jr_node);
+ break;
+ }
+ jr_node = fdt_node_offset_by_compatible(blob, jr_node,
+ "fsl,sec-v4.0-job-ring");
+ }
+}
+#endif
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
-#ifdef CONFIG_FSL_LSCH2
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- unsigned int svr = in_be32(&gur->svr);
+ unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(svr))
else {
ccsr_sec_t __iomem *sec;
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+ if (fdt_fixup_kaslr(blob))
+ fdt_fixup_remove_jr(blob);
+#endif
+
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
-#endif
#ifdef CONFIG_MP
ft_fixup_cpu(blob);
}
#endif
+/*
+ * Check with sec_firmware if it supports random number generation
+ * via HW RNG
+ *
+ * The return value will be true if it is supported
+ */
+bool sec_firmware_support_hwrng(void)
+{
+ uint8_t rand[8];
+ if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
+ if (!sec_firmware_get_random(rand, 8))
+ return true;
+ }
+
+ return false;
+}
+
+/*
+ * sec_firmware_get_random - Get a random number from SEC Firmware
+ * @rand: random number buffer to be filled
+ * @bytes: Number of bytes of random number to be supported
+ * @eret: -1 in case of error, 0 for success
+ */
+int sec_firmware_get_random(uint8_t *rand, int bytes)
+{
+ unsigned long long num;
+ struct pt_regs regs;
+ int param1;
+
+ if (!bytes || bytes > 8) {
+ printf("Max Random bytes genration supported is 8\n");
+ return -1;
+ }
+#define SIP_RNG_64 0xC200FF11
+ regs.regs[0] = SIP_RNG_64;
+
+ if (bytes <= 4)
+ param1 = 0;
+ else
+ param1 = 1;
+ regs.regs[1] = param1;
+
+ smc_call(®s);
+
+ if (regs.regs[0])
+ return -1;
+
+ num = regs.regs[1];
+ memcpy(rand, &num, bytes);
+
+ return 0;
+}
+
/*
* sec_firmware_init - Initialize the SEC Firmware
* @sec_firmware_img: the SEC Firmware image address
return 0;
}
+
+/*
+ * fdt_fix_kaslr - Add kalsr-seed node in Device tree
+ * @fdt: Device tree
+ * @eret: 0 in case of error, 1 for success
+ */
+int fdt_fixup_kaslr(void *fdt)
+{
+ int nodeoffset;
+ int err, ret = 0;
+ u8 rand[8];
+
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)
+ /* Check if random seed generation is supported */
+ if (sec_firmware_support_hwrng() == false)
+ return 0;
+
+ ret = sec_firmware_get_random(rand, 8);
+ if (ret < 0) {
+ printf("WARNING: No random number to set kaslr-seed\n");
+ return 0;
+ }
+
+ err = fdt_check_header(fdt);
+ if (err < 0) {
+ printf("fdt_chosen: %s\n", fdt_strerror(err));
+ return 0;
+ }
+
+ /* find or create "/chosen" node. */
+ nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
+ if (nodeoffset < 0)
+ return 0;
+
+ err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", rand,
+ sizeof(rand));
+ if (err < 0) {
+ printf("WARNING: can't set kaslr-seed %s.\n",
+ fdt_strerror(err));
+ return 0;
+ }
+ ret = 1;
+#endif
+
+ return ret;
+}
&edma 25>;
dma-names = "tx", "rx";
interrupts = <64>;
- interrupt-parent = <&intc>;
reg = <0x48060000 0x1000>;
status = "disabled";
};
&edma 3>;
dma-names = "tx", "rx";
interrupts = <28>;
- interrupt-parent = <&intc>;
reg = <0x481d8000 0x1000>;
status = "disabled";
};
ti,hwmods = "mmc3";
ti,needs-special-reset;
interrupts = <29>;
- interrupt-parent = <&intc>;
reg = <0x47810000 0x1000>;
status = "disabled";
};
0x4a101200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
- interrupt-parent = <&intc>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
lcdc: lcdc@4830e000 {
compatible = "ti,am33xx-tilcdc";
reg = <0x4830e000 0x1000>;
- interrupt-parent = <&intc>;
interrupts = <36>;
ti,hwmods = "lcdc";
status = "disabled";
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
- interrupt-parent = <&intc>;
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";
status = "disabled";
};
+ rstc@f8048000 {
+ compatible = "atmel,sama5d3-rstc";
+ reg = <0xf8048000 0x10>;
+ clocks = <&clk32k>;
+ };
+
+ shdwc@f8048010 {
+ compatible = "atmel,sama5d2-shdwc";
+ reg = <0xf8048010 0x10>;
+ clocks = <&clk32k>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,wakeup-rtc-timer;
+ };
+
+ pit: timer@f8048030 {
+ compatible = "atmel,at91sam9260-pit";
+ reg = <0xf8048030 0x10>;
+ clocks = <&h32ck>;
+ };
+
+ watchdog@f8048040 {
+ compatible = "atmel,sama5d4-wdt";
+ reg = <0xf8048040 0x10>;
+ clocks = <&clk32k>;
+ status = "disabled";
+ };
+
sckc@f8048050 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xf8048050 0x4>;
#define __SEC_FIRMWARE_H_
#define PSCI_INVALID_VER 0xffffffff
+#define SEC_JR3_OFFSET 0x40000
int sec_firmware_init(const void *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
+bool sec_firmware_support_hwrng(void);
+int sec_firmware_get_random(uint8_t *rand, int bytes);
+int fdt_fixup_kaslr(void *fdt);
#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
unsigned int sec_firmware_support_psci_version(void);
unsigned int _sec_firmware_support_psci_version(void);
}
#endif
+static inline unsigned int sec_firmware_used_jobring_offset(void)
+{
+ return SEC_JR3_OFFSET;
+}
+
#endif /* __SEC_FIRMWARE_H_ */
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
obj-y += timer.o
+endif
ifndef CONFIG_SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
obj-y += timer.o
+endif
select SPL_OF_CONTROL
select SPL_OF_LIBFDT
select SPL_OF_TRANSLATE
- select SPL_OS_BOOT
+ imply SPL_OS_BOOT
select SPL_PINCTRL
select SPL_RAM
select SPL_SERIAL_SUPPORT
ulong count;
};
-int interrupt_init_cpu (unsigned *decrementer_count)
+void interrupt_init_cpu (unsigned *decrementer_count)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/* Enable e300 time base */
immr->sysconf.spcr |= 0x00400000;
-
- return 0;
}
#include <post.h>
#endif
-int interrupt_init_cpu(unsigned *decrementer_count)
+void interrupt_init_cpu(unsigned *decrementer_count)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
#ifdef CONFIG_POST
post_word_store(post_word);
#endif
-
- return (0);
}
/* Install and free a interrupt handler. Not implemented yet. */
#include <post.h>
#endif
-int interrupt_init_cpu(unsigned *decrementer_count)
+void interrupt_init_cpu(unsigned *decrementer_count)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_pic_t *pic = &immr->im_pic;
#ifdef CONFIG_POST
post_word_store(post_word);
#endif
-
- return 0;
}
/*
/************************************************************************/
-int interrupt_init_cpu(unsigned *decrementer_count)
+void interrupt_init_cpu(unsigned *decrementer_count)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
/* Configure CPM interrupts */
cpm_interrupt_init();
-
- return 0;
}
/************************************************************************/
void print_reginfo(void);
#endif
-int interrupt_init_cpu(unsigned *);
+void interrupt_init_cpu(unsigned *);
void timer_interrupt_cpu(struct pt_regs *);
unsigned long search_exception_table(unsigned long addr);
int interrupt_init (void)
{
- int ret;
-
/* call cpu specific function from $(CPU)/interrupts.c */
- ret = interrupt_init_cpu (&decrementer_count);
-
- if (ret)
- return ret;
+ interrupt_init_cpu (&decrementer_count);
set_dec (decrementer_count);
S: Maintained
F: board/isee/igep00x0/
F: include/configs/omap3_igep00x0.h
-F: configs/igep0020_defconfig
-F: configs/igep0030_defconfig
+F: configs/igep00x0_defconfig
F: configs/igep0032_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := igep00x0.o
+ifdef CONFIG_SPL_BUILD
+obj-y := spl.o common.o
+else
+obj-y := igep00x0.o common.o
+endif
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/omap_mmc.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <jffs2/load_kernel.h>
+#include <linux/mtd/nand.h>
+#include "igep00x0.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ int loops = 100;
+
+ /* find out flash memory type, assume NAND first */
+ gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+ gpmc_init();
+
+ /* Issue a RESET and then READID */
+ writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
+ writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
+ while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
+ != NAND_STATUS_READY) {
+ udelay(1);
+ if (--loops == 0) {
+ gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
+ gpmc_init(); /* reinitialize for OneNAND */
+ break;
+ }
+ }
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
-#include <linux/mtd/nand.h>
#include <linux/mtd/onenand.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <fdt_support.h>
#include "igep00x0.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct ns16550_platdata igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
};
/*
- * Routine: board_init
- * Description: Early hardware init.
+ * Routine: get_board_revision
+ * Description: GPIO_28 and GPIO_129 are used to read board and revision from
+ * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
+ * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
+ * this functionality is shared by USB HOST.
+ * Once USB reset is applied, U-boot configures these pins as input pullup to
+ * detect board and revision:
+ * IGEP0020-RF = 0b00
+ * IGEP0020-RC = 0b01
+ * IGEP0030-RG = 0b10
+ * IGEP0030-RE = 0b11
*/
-int board_init(void)
+static int get_board_revision(void)
{
- int loops = 100;
-
- /* find out flash memory type, assume NAND first */
- gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
- gpmc_init();
+ int revision;
- /* Issue a RESET and then READID */
- writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
- writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
- while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
- != NAND_STATUS_READY) {
- udelay(1);
- if (--loops == 0) {
- gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
- gpmc_init(); /* reinitialize for OneNAND */
- break;
- }
- }
+ gpio_request(IGEP0030_USB_TRANSCEIVER_RESET,
+ "igep0030_usb_transceiver_reset");
+ gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0);
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+ gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection");
+ gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION);
+ revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION);
+ gpio_free(GPIO_IGEP00X0_BOARD_DETECTION);
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
- status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- int mfr, id, err = identify_nand_chip(&mfr, &id);
-
- timings->mr = MICRON_V_MR_165;
- if (!err) {
- switch (mfr) {
- case NAND_MFR_HYNIX:
- timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
- timings->ctrla = HYNIX_V_ACTIMA_200;
- timings->ctrlb = HYNIX_V_ACTIMB_200;
- break;
- case NAND_MFR_MICRON:
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- break;
- default:
- /* Should not happen... */
- break;
- }
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
- } else {
- if (get_cpu_family() == CPU_OMAP34XX) {
- timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_165;
- timings->ctrlb = NUMONYX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- } else {
- timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_200;
- timings->ctrlb = NUMONYX_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- }
- gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
- }
-}
+ gpio_request(GPIO_IGEP00X0_REVISION_DETECTION,
+ "igep00x0_revision_detection");
+ gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION);
+ revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION);
+ gpio_free(GPIO_IGEP00X0_REVISION_DETECTION);
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
+ gpio_free(IGEP0030_USB_TRANSCEIVER_RESET);
- return 0;
+ return revision;
}
-#endif
-#endif
int onenand_board_init(struct mtd_info *mtd)
{
static inline void setup_net_chip(void) {}
#endif
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
#ifdef CONFIG_OF_BOARD_SETUP
static int ft_enable_by_compatible(void *blob, char *compat, int enable)
{
}
#endif
-void set_fdt(void)
+void set_led(void)
{
- switch (gd->bd->bi_arch_number) {
- case MACH_TYPE_IGEP0020:
- env_set("fdtfile", "omap3-igep0020.dtb");
+ switch (get_board_revision()) {
+ case 0:
+ case 1:
+ gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led");
+ gpio_direction_output(IGEP0020_GPIO_LED, 1);
+ break;
+ case 2:
+ case 3:
+ gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led");
+ gpio_direction_output(IGEP0030_GPIO_LED, 0);
break;
- case MACH_TYPE_IGEP0030:
- env_set("fdtfile", "omap3-igep0030.dtb");
+ default:
+ /* Should not happen... */
break;
}
}
+void set_boardname(void)
+{
+ char rev[5] = { 'F','C','G','E', };
+ int i = get_board_revision();
+
+ rev[i+1] = 0;
+ env_set("board_rev", rev + i);
+ env_set("board_name", i < 2 ? "igep0020" : "igep0030");
+}
+
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
+ t2_t *t2_base = (t2_t *)T2_BASE;
+ u32 pbias_lite;
+
twl4030_power_init();
+ /* set VSIM to 1.8V */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+ TWL4030_PM_RECEIVER_VSIM_VSEL_18,
+ TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ /* set up dual-voltage GPIOs to 1.8V */
+ pbias_lite = readl(&t2_base->pbias_lite);
+ pbias_lite &= ~PBIASLITEVMODE1;
+ pbias_lite |= PBIASLITEPWRDNZ1;
+ writel(pbias_lite, &t2_base->pbias_lite);
+ if (get_cpu_family() == CPU_OMAP36XX)
+ writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
+ OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
+ OMAP34XX_CTRL_WKUP_CTRL);
+
setup_net_chip();
omap_die_id_display();
- set_fdt();
+ set_led();
+
+ set_boardname();
return 0;
}
*mtdparts = parts;
}
}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_DEFAULT();
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
- MUX_IGEP0020();
-#endif
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
- MUX_IGEP0030();
-#endif
-}
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\
+ MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
#endif
-
-#define MUX_IGEP0020() \
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
-
-#define MUX_IGEP0030() \
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <jffs2/load_kernel.h>
+#include <linux/mtd/nand.h>
+#include "igep00x0.h"
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ int mfr, id, err = identify_nand_chip(&mfr, &id);
+
+ timings->mr = MICRON_V_MR_165;
+ if (!err) {
+ switch (mfr) {
+ case NAND_MFR_HYNIX:
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ break;
+ case NAND_MFR_MICRON:
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ break;
+ default:
+ /* Should not happen... */
+ break;
+ }
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+ } else {
+ if (get_cpu_family() == CPU_OMAP34XX) {
+ timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ } else {
+ timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_200;
+ timings->ctrlb = NUMONYX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
+ gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
+ }
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-# necessary to create built-in.o
-obj- := __dummy__.o
-else
-obj-y := spr_misc.o
-obj-y += spr_lowlevel_init.o
-endif
const char *ids, *parts;
const char *current_partition;
int ids_changed;
- char tmp_ep[PARTITION_MAXLEN];
+ char tmp_ep[PARTITION_MAXLEN + 1];
char tmp_parts[MTDPARTS_MAXLEN];
debug("\n---mtdparts_init---\n");
/* save it for later parsing, cannot rely on current partition pointer
* as 'partition' variable may be updated during init */
- tmp_ep[0] = '\0';
+ memset(tmp_parts, 0, sizeof(tmp_parts));
if (current_partition)
strncpy(tmp_ep, current_partition, PARTITION_MAXLEN);
case SPL_EXPORT_FDT:
printf("Argument image is now in RAM: 0x%p\n",
(void *)images.ft_addr);
+ env_set_addr("fdtargsaddr", images.ft_addr);
+ env_set_hex("fdtargslen", fdt_totalsize(images.ft_addr));
+ if (fdt_totalsize(images.ft_addr) >
+ CONFIG_CMD_SPL_WRITE_SIZE)
+ puts("WARN: FDT size > CMD_SPL_WRITE_SIZE\n");
break;
#endif
case SPL_EXPORT_ATAGS:
CONFIG_OF_BOARD_SETUP=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_LCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_LCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_LCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_PHYLIB=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_ONENAND=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=16
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=27
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_LCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_LCD=y
CONFIG_FAT_WRITE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_LCD=y
CONFIG_FAT_WRITE=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
#undef CHECK_FOR_POWERPC_PLATTFORM
#define CD_SECTSIZE 2048
-static unsigned char tmpbuf[CD_SECTSIZE];
+static unsigned char tmpbuf[CD_SECTSIZE] __aligned(ARCH_DMA_MINALIGN);
unsigned long iso_dread(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt, void *buffer)
storage can not be predicted nor provided at commandline, it depends
highly on your system setup and your provided data (ATAGS or FDT).
However at the end of an succesful 'spl export' run it will print the
-RAM address of temporary storage.
+RAM address of temporary storage. The RAM address of FDT will also be
+set in the environment variable 'fdtargsaddr', the new length of the
+prepared FDT will be set in the environment variable 'fdtargslen'.
+These environment variables can be used in scripts for writing updated
+FDT to persistent storage.
+
Now the user have to save the generated BLOB from that printed address
to the pre-defined address in persistent storage
(CONFIG_CMD_SPL_NAND_OFS in case of NAND).
Device Tree Bindings
--------------------
The following properties are required in the FIT's signature node(s) to
-allow thes signer to operate. These should be added to the .its file.
+allow the signer to operate. These should be added to the .its file.
Signature nodes sit at the same level as hash nodes and are called
signature@1, signature@2, etc.
- required: If present this indicates that the key must be verified for the
image / configuration to be considered valid. Only required keys are
normally verified by the FIT image booting algorithm. Valid values are
-"image" to force verification of all images, and "conf" to force verfication
+"image" to force verification of all images, and "conf" to force verification
of the selected configuration (which then relies on hashes in the images to
verify those).
With signed images, nothing protects against this. Whether it gains an
advantage for the attacker is debatable, but it is not secure.
-To solved this problem, we support signed configurations. In this case it
+To solve this problem, we support signed configurations. In this case it
is the configurations that are signed, not the image. Each image has its
own hash, and we include the hash in the configuration signature.
In addition to the options to enable FIT itself, the following CONFIGs must
be enabled:
-CONFIG_FIT_SIGNATURE - enable signing and verfication in FITs
+CONFIG_FIT_SIGNATURE - enable signing and verification in FITs
CONFIG_RSA - enable RSA algorithm for signing
WARNING: When relying on signed FIT images with required signature check
Testing
-------
-An easy way to test signing and verfication is to use the test script
+An easy way to test signing and verification is to use the test script
provided in test/vboot/vboot_test.sh. This uses sandbox (a special version
of U-Boot which runs under Linux) to show the operation of a 'bootm'
command loading and verifying images.
add signatures as well.
The public key can be stored in U-Boot's CONFIG_OF_CONTROL device tree in
-a standard place. Then when a FIT it loaded it can be verified using that
+a standard place. Then when a FIT is loaded it can be verified using that
public key. Multiple keys and multiple signatures are supported.
See signature.txt for more information.
/*-----------------------------------------------------------------------
*/
#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
-flash_info_t *flash_get_info(ulong base)
+static flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t *info;
/*
* Write a proper sized command to the correct address
*/
-void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
- uint offset, u32 cmd)
+static void flash_write_cmd(flash_info_t *info, flash_sect_t sect,
+ uint offset, u32 cmd)
{
void *addr;
/*-----------------------------------------------------------------------
*/
-void flash_protect_default(void)
+static void flash_protect_default(void)
{
#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
int i;
setting up RAM (e.g. SDRAM / DDR) within SPL.
config TPL_RAM
- bool "Enable RAM support in SPL"
+ bool "Enable RAM support in TPL"
depends on RAM && TPL_DM
help
The RAM subsystem adds a small amount of overhead to the image.
Select this to enable a timer for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
+config ATMEL_PIT_TIMER
+ bool "Atmel periodic interval timer support"
+ depends on TIMER
+ help
+ Select this to enable a periodic interval timer for Atmel devices,
+ it is designed to offer maximum accuracy and efficient management,
+ even for systems with long response time.
+
config SANDBOX_TIMER
bool "Sandbox timer support"
depends on SANDBOX && TIMER
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
+obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define AT91_PIT_VALUE 0xfffff
+#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
+
+struct atmel_pit_regs {
+ u32 mode;
+ u32 status;
+ u32 value;
+ u32 value_image;
+};
+
+struct atmel_pit_platdata {
+ struct atmel_pit_regs *regs;
+};
+
+static int atmel_pit_get_count(struct udevice *dev, u64 *count)
+{
+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pit_regs *const regs = plat->regs;
+ u32 val = readl(®s->value_image);
+
+ *count = timer_conv_64(val);
+
+ return 0;
+}
+
+static int atmel_pit_probe(struct udevice *dev)
+{
+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pit_regs *const regs = plat->regs;
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct clk clk;
+ ulong clk_rate;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return -EINVAL;
+
+ clk_rate = clk_get_rate(&clk);
+ if (!clk_rate)
+ return -EINVAL;
+
+ uc_priv->clock_rate = clk_rate / 16;
+
+ writel(AT91_PIT_VALUE | AT91_PIT_PITEN, ®s->mode);
+
+ return 0;
+}
+
+static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
+{
+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+
+ plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
+
+ return 0;
+}
+
+static const struct timer_ops atmel_pit_ops = {
+ .get_count = atmel_pit_get_count,
+};
+
+static const struct udevice_id atmel_pit_ids[] = {
+ { .compatible = "atmel,at91sam9260-pit" },
+ { }
+};
+
+U_BOOT_DRIVER(atmel_pit) = {
+ .name = "atmel_pit",
+ .id = UCLASS_TIMER,
+ .of_match = atmel_pit_ids,
+ .ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
+ .probe = atmel_pit_probe,
+ .ops = &atmel_pit_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
ofs = sizeof(struct journal_header_t);
do {
- tag = (struct ext3_journal_block_tag *)&p_jdb[ofs];
+ tag = (struct ext3_journal_block_tag *)(p_jdb + ofs);
ofs += sizeof(struct ext3_journal_block_tag);
if (ofs > fs->blksz)
ofs = sizeof(struct journal_header_t);
do {
tag = (struct ext3_journal_block_tag *)
- &p_jdb[ofs];
+ (p_jdb + ofs);
ofs += sizeof(struct ext3_journal_block_tag);
if (ofs > fs->blksz)
break;
if (offset != 0)
sect_num++;
- if (startsect + sect_num > cur_part_info.start + total_sector)
+ if (startsect + sect_num > total_sector)
return -1;
return 0;
}
#define CONFIG_NR_DRAM_BANKS 2
#include <configs/ti_omap3_common.h>
-#include <asm/mach-types.h>
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
#define CONFIG_REVISION_TAG 1
-/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
- (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
-#define RED_LED_GPIO 27
-#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-#define RED_LED_GPIO 16
-#endif
-#endif
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */
+#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */
+
+/* TPS65950 */
+#define PBIASLITEVMODE1 (1 << 8)
+
+/* LED */
+#define IGEP0020_GPIO_LED 27
+#define IGEP0030_GPIO_LED 16
+
+/* Board and revision detection GPIOs */
+#define IGEP0030_USB_TRANSCEIVER_RESET 54
+#define GPIO_IGEP00X0_BOARD_DETECTION 28
+#define GPIO_IGEP00X0_REVISION_DETECTION 129
/* USB */
#define CONFIG_USB_MUSB_UDC 1
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run distro_bootcmd"
+
#include <config_distro_bootcmd.h>
+#define ENV_FINDFDT \
+ "findfdt="\
+ "if test ${board_name} = igep0020; then " \
+ "if test ${board_rev} = F; then " \
+ "setenv fdtfile omap3-igep0020-rev-f.dtb; " \
+ "else " \
+ "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \
+ "if test ${board_name} = igep0030; then " \
+ "if test ${board_rev} = G; then " \
+ "setenv fdtfile omap3-igep0030-rev-g.dtb; " \
+ "else " \
+ "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \
+ "if test ${fdtfile} = ''; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_FINDFDT \
ENV_DEVICE_SETTINGS \
MEM_LAYOUT_SETTINGS \
BOOTENV
"vram=16M\0" \
"partitions=" PARTS_DEFAULT "\0" \
"optargs=\0" \
- "dofastboot=0\0"
+ "dofastboot=0\0" \
+ "emmc_android_boot=" \
+ "setenv eval_bootargs setenv bootargs $bootargs; " \
+ "run eval_bootargs; " \
+ "setenv mmcdev 1; " \
+ "setenv fdt_part 3; " \
+ "setenv boot_part 9; " \
+ "setenv machid fe6; " \
+ "mmc dev $mmcdev; " \
+ "mmc rescan; " \
+ "part start mmc ${mmcdev} ${fdt_part} fdt_start; " \
+ "part size mmc ${mmcdev} ${fdt_part} fdt_size; " \
+ "part start mmc ${mmcdev} ${boot_part} boot_start; " \
+ "part size mmc ${mmcdev} ${boot_part} boot_size; " \
+ "mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \
+ "mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
+ "echo Booting from eMMC ...; " \
+ "bootm $loadaddr $loadaddr $fdtaddr;\0"
#ifdef CONFIG_OMAP54XX
"setenv bootpart 1:2; " \
"setenv mmcroot /dev/mmcblk0p2 rw; " \
"run mmcboot;" \
+ "run emmc_android_boot; " \
""
#endif /* CONFIG_OMAP54XX */
/* Prototypes */
extern unsigned long flash_init (void);
-extern void flash_protect_default(void);
extern void flash_print_info (flash_info_t *);
extern int flash_erase (flash_info_t *, int, int);
extern int flash_sect_erase (ulong addr_first, ulong addr_last);
#define CFI_CMDSET_AMD_LEGACY 0xFFF0
#endif
-#if defined(CONFIG_SYS_FLASH_CFI)
-extern flash_info_t *flash_get_info(ulong base);
-#endif
-
/*-----------------------------------------------------------------------
* return codes from flash_write():
*/
#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS
#endif
-void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
- uint offset, u32 cmd);
phys_addr_t cfi_flash_bank_addr(int i);
unsigned long cfi_flash_bank_size(int i);
void flash_cmd_reset(flash_info_t *info);
do_objdump() {
dir=$(get_output_dir $1)
base=${1##*/}
+ stripped=$dir/${base%.o}.stripped
dis=$dir/${base%.o}.dis
[ ! -d "$dir" ] && mkdir -p $dir
# remove addresses for a cleaner diff
# http://dummdida.tumblr.com/post/60924060451/binary-diff-between-libc-from-scientificlinux-and
- $OBJDUMP -D $1 | sed "s/^[[:space:]]\+[0-9a-f]\+//" > $dis
+ $STRIP -g $1 -R __bug_table -R .note -R .comment -o $stripped
+ $OBJDUMP -D $stripped | sed -e "s/^[[:space:]]\+[0-9a-f]\+//" -e "s:^$stripped:$1:" > $dis
}
dorecord() {
CMT="`git rev-parse --short HEAD`"
+ STRIP="${CROSS_COMPILE}strip"
OBJDUMP="${CROSS_COMPILE}objdump"
for d in $FILES; do
projects / people / ms / u-boot.git / commitdiff
