Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

diff --combined board/freescale/t102xqds/ddr.c
index 912d6a950f8c4653e222797c599f2e8b91a54020,fa1394d9f0a36ac04b8d2a752520f282e8bec03a..c26f3503b99192bf009010fe0df981c9a5f9c005
--- 1/board/freescale/t102xqds/ddr.c
--- 2/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@@ -35,18 -35,18 +35,18 @@@ static const struct board_specific_para
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
         */
  #if defined(CONFIG_SYS_FSL_DDR4)
 -      {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
 -      {2,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
 -      {1,  1666,  0,  4,  6,  0x0708090B,  0x0C0D0E09,},
 -      {1,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
 -      {1,  2200,  0,  4,  7,  0x08090A0D,  0x0F0F100C,},
 +      {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 +      {2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
 +      {1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
 +      {1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
 +      {1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
  #elif defined(CONFIG_SYS_FSL_DDR3)
 -      {2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
 -      {2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
 -      {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
 -      {1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
 -      {1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
 -      {1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
 +      {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
 +      {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
 +      {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 +      {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
 +      {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
 +      {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  #else
  #error DDR type not defined
  #endif
@@@ -172,14 -172,13 +172,13 @@@ phys_size_t initdram(int board_type
  
  #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
        puts("Initializing....using SPD\n");
- 
        dram_size = fsl_ddr_sdram();
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-       dram_size *= 0x100000;
  #else
        /* DDR has been initialised by first stage boot loader */
        dram_size =  fsl_ddr_sdram_size();
  #endif
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
  
  #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
        fsl_dp_resume();

diff --combined board/freescale/t102xrdb/ddr.c
index 60ab9ff8ade08a6d775656842098d9d0903ce0a4,b13692bb4a88bb855175c7af3657de8feaa90ba4..edfbdbf3a814e65b1fe3fd246b51f2fa38c9f5fd
--- 1/board/freescale/t102xrdb/ddr.c
--- 2/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@@ -34,12 -34,12 +34,12 @@@ static const struct board_specific_para
         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
         */
 -      {2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
 -      {2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
 -      {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
 -      {1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
 -      {1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
 -      {1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
 +      {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
 +      {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
 +      {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 +      {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
 +      {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
 +      {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
        {}
  };
  
@@@ -234,12 -234,12 +234,12 @@@ phys_size_t initdram(int board_type
        puts("Initializing....using SPD\n");
  #endif
        dram_size = fsl_ddr_sdram();
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-       dram_size *= 0x100000;
  #else
        /* DDR has been initialised by first stage boot loader */
        dram_size =  fsl_ddr_sdram_size();
  #endif
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
  
  #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
        fsl_dp_resume();

diff --combined drivers/gpio/Kconfig
index 32219ed478899dfb997f01c7b66de261e36d9051,8595e2e9a250d0348d8c989fba34e5ccc8b53d07..73b862dc0b219b1a5e5445fb113f10d83e554c0a
--- 1/drivers/gpio/Kconfig
--- 2/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@@ -109,21 -109,6 +109,21 @@@ config SANDBOX_GPIO_COUN
          of 'anonymous' GPIOs that do not belong to any device or bank.
          Select a suitable value depending on your needs.
  
 +config TEGRA_GPIO
 +      bool "Tegra20..210 GPIO driver"
 +      depends on DM_GPIO
 +      help
 +        Support for the GPIO controller contained in NVIDIA Tegra20 through
 +        Tegra210.
 +
 +config TEGRA186_GPIO
 +      bool "Tegra186 GPIO driver"
 +      depends on DM_GPIO
 +      help
 +        Support for the GPIO controller contained in NVIDIA Tegra186. This
 +        covers both the "main" and "AON" controller instances, even though
 +        they have slightly different register layout.
 +
  config GPIO_UNIPHIER
        bool "UniPhier GPIO"
        depends on ARCH_UNIPHIER
@@@ -188,4 -173,30 +188,30 @@@ config DM_PCA953
  
          Now, max 24 bits chips and PCA953X compatible chips are
          supported
+ 
+ config MPC85XX_GPIO
+       bool "Freescale MPC85XX GPIO driver"
+       depends on DM_GPIO
+       help
+         This driver supports the built-in GPIO controller of MPC85XX CPUs.
+         Each GPIO bank is identified by its own entry in the device tree,
+         i.e.
+ 
+         gpio-controller@fc00 {
+               #gpio-cells = <2>;
+               compatible = "fsl,pq3-gpio";
+               reg = <0xfc00 0x100>
+         }
+ 
+         By default, each bank is assumed to have 32 GPIOs, but the ngpios
+         setting is honored, so the number of GPIOs for each bank is
+         configurable to match the actual GPIO count of the SoC (e.g. the
+         32/32/23 banks of the P1022 SoC).
+ 
+         Aside from the standard functions of input/output mode, and output
+         value setting, the open-drain feature, which can configure individual
+         GPIOs to work as open-drain outputs, is supported.
+ 
+         The driver has been tested on MPC85XX, but it is likely that other
+         PowerQUICC III devices will work as well.
  endmenu

diff --combined drivers/gpio/Makefile
index 3c4310176d1d86bf8807e604ba0aa515a5f6724c,21b2cc267767e6fef6f326efb7465cac0116fad6..792d19186aadf19a4a0a6a63efcccb759d24188a
--- 1/drivers/gpio/Makefile
--- 2/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@@ -31,11 -31,11 +31,12 @@@ obj-$(CONFIG_S5P)          += s5p_gpio.
  obj-$(CONFIG_SANDBOX_GPIO)    += sandbox.o
  obj-$(CONFIG_SPEAR_GPIO)      += spear_gpio.o
  obj-$(CONFIG_TEGRA_GPIO)      += tegra_gpio.o
 +obj-$(CONFIG_TEGRA186_GPIO)   += tegra186_gpio.o
  obj-$(CONFIG_DA8XX_GPIO)      += da8xx_gpio.o
  obj-$(CONFIG_DM644X_GPIO)     += da8xx_gpio.o
  obj-$(CONFIG_ALTERA_PIO)      += altera_pio.o
  obj-$(CONFIG_MPC83XX_GPIO)    += mpc83xx_gpio.o
+ obj-$(CONFIG_MPC85XX_GPIO)    += mpc85xx_gpio.o
  obj-$(CONFIG_SH_GPIO_PFC)     += sh_pfc.o
  obj-$(CONFIG_OMAP_GPIO)       += omap_gpio.o
  obj-$(CONFIG_DB8500_GPIO)     += db8500_gpio.o