I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
{
static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
{
static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
uint8_t *read_ecc, uint8_t *calc_ecc)
{
static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
uint8_t *read_ecc, uint8_t *calc_ecc)
{
- struct nand_chip *this = mtd->priv;
unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
int i;
unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
int i;
unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
+#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
static int nand_davinci_dev_ready(struct mtd_info *mtd)
{