LIST_sh4=" \
ms7750se \
ms7722se \
- Migo-R \
+ MigoR \
r7780mp \
r2dplus \
sh7763rdp \
LIB = $(obj)lib$(BOARD).a
-OBJS := migo_r.o
+COBJS := migo_r.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
LIB = $(obj)lib$(BOARD).a
-OBJS := mpr2.o
+COBJS := mpr2.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
LIB = $(obj)lib$(BOARD).a
-OBJS := ms7720se.o
+COBJS := ms7720se.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
int board_init(void)
{
-
return 0;
}
LIB = $(obj)lib$(BOARD).a
-OBJS := ms7722se.o
+COBJS := ms7722se.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
/*
- * Copyright (C) 2007
+ * Copyright (C) 2007,2008
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* Copyright (C) 2007
return 0;
}
-int dram_init (void)
+int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-void led_set_state (unsigned short value)
+void led_set_state(unsigned short value)
{
- *((volatile unsigned short *) LED_BASE) = (value & 0xFF);
+ writew(value & 0xFF, LED_BASE);
}
LIB = $(obj)lib$(BOARD).a
-OBJS := ms7750se.o
+COBJS := ms7750se.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
LIB = $(obj)lib$(BOARD).a
-OBJS := r2dplus.o
+COBJS := r2dplus.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
#include <common.h>
#include <ide.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <asm/pci.h>
int checkboard(void)
return 0;
}
-int dram_init (void)
+int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-#define FPGA_BASE 0xA4000000
-#define FPGA_CFCTL (FPGA_BASE + 0x04)
-#define FPGA_CFPOW (FPGA_BASE + 0x06)
-#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
+#define FPGA_BASE 0xA4000000
+#define FPGA_CFCTL (FPGA_BASE + 0x04)
+#define CFCTL_EN (0x432)
+#define FPGA_CFPOW (FPGA_BASE + 0x06)
+#define CFPOW_ON (0x02)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
+#define CFCDINTCLR_EN (0x01)
-void ide_set_reset (int idereset)
+void ide_set_reset(int idereset)
{
/* if reset = 1 IDE reset will be asserted */
- if (idereset){
- (*(vu_short *)FPGA_CFCTL) = 0x432;
- (*(vu_short *)FPGA_CFPOW) |= 0x02;
- (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ if (idereset) {
+ outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
+ outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
+ outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
}
}
-#if defined(CONFIG_PCI)
static struct pci_controller hose;
void pci_init_board(void)
{
- pci_sh7751_init( &hose );
+ pci_sh7751_init(&hose);
}
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-OBJS := r7780mp.o
+COBJS := r7780mp.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
int board_init(void)
{
/* SCIF Enable */
- *(vu_short*)PHCR = 0x0000;
+ writew(0x0, PHCR);
return 0;
}
-int dram_init (void)
+int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-void led_set_state (unsigned short value)
+void led_set_state(unsigned short value)
{
}
-void ide_set_reset (int idereset)
+void ide_set_reset(int idereset)
{
/* if reset = 1 IDE reset will be asserted */
- if (idereset){
- (*(vu_short *)FPGA_CFCTL) = 0x432;
+ if (idereset) {
+ writew(0x432, FPGA_CFCTL);
#if defined(CONFIG_R7780MP)
- (*(vu_short *)FPGA_CFPOW) |= 0x01;
+ writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
#else
- (*(vu_short *)FPGA_CFPOW) |= 0x02;
+ writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
#endif
- (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ writew(0x01, FPGA_CFCDINTCLR);
}
}
-#if defined(CONFIG_PCI)
static struct pci_controller hose;
void pci_init_board(void)
{
- pci_sh7780_init( &hose );
+ pci_sh7780_init(&hose);
}
-#endif
LIB = $(obj)lib$(BOARD).a
-OBJS := sh7763rdp.o
+COBJS := sh7763rdp.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
{
vu_short dat;
- *(vu_short *)(CPU_CMDREG) |= 0x0001;
+ /* Enable mode */
+ writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG);
/* GPIO Setting (eth1) */
- dat = *(vu_short *)(PSEL1);
- *(vu_short *)PSEL1 = ((dat & ~0xff00) | 0x2400);
- *(vu_short *)PFCR = 0;
- *(vu_short *)PGCR = 0;
- *(vu_short *)PHCR = 0;
+ dat = inw(PSEL1);
+ writew(((dat & ~0xff00) | 0x2400), PSEL1);
+ writew(0, PFCR);
+ writew(0, PGCR);
+ writew(0, PHCR);
return 0;
}
-int dram_init (void)
+int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-void led_set_state (unsigned short value)
+void led_set_state(unsigned short value)
{
}
#include <common.h>
#include <at91rm9200_net.h>
#include <net.h>
+#include <miiphy.h>
#include <lxt971a.h>
#ifdef CONFIG_DRIVER_ETHER
unsigned short Id1, Id2;
at91rm9200_EmacEnableMDIO (p_mac);
- at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID1, &Id1);
- at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID2, &Id2);
+ at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1);
+ at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2);
at91rm9200_EmacDisableMDIO (p_mac);
if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0))
unsigned short value;
/* Set lxt972 control register */
- if (!at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_CTRL, &value))
+ if (!at91rm9200_EmacReadPhy (p_mac, PHY_BMCR, &value))
return FALSE;
/* Restart Auto_negotiation */
- value |= PHY_COMMON_CTRL_RES_AUTO;
- if (!at91rm9200_EmacWritePhy (p_mac, PHY_COMMON_CTRL, &value))
+ value |= PHY_BMCR_RST_NEG;
+ if (!at91rm9200_EmacWritePhy (p_mac, PHY_BMCR, &value))
return FALSE;
/*check AutoNegotiate complete */
udelay (10000);
- at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_STAT, &value);
- if (!(value & PHY_COMMON_STAT_AN_COMP))
+ at91rm9200_EmacReadPhy(p_mac, PHY_BMSR, &value);
+ if (!(value & PHY_BMSR_AUTN_COMP))
return FALSE;
return (lxt972_GetLinkSpeed (p_mac));
#include <common.h>
#include <net.h>
+#include <miiphy.h>
#include <lxt971a.h>
#include <asm/arch/emac_defs.h>
int lxt972_is_phy_connected(int phy_addr)
{
- u_int16_t id1, id2;
+ u_int16_t id1, id2;
- if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID1, &id1))
+ if (!dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &id1))
return(0);
- if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID2, &id2))
+ if (!dm644x_eth_phy_read(phy_addr, PHY_PHYIDR2, &id2))
return(0);
if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0))
int lxt972_get_link_speed(int phy_addr)
{
- u_int16_t stat1, tmp;
- volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
+ u_int16_t stat1, tmp;
+ volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
return(0);
if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
return(0);
-
/* Speed doesn't matter, there is no setting for it in EMAC... */
- if (stat1 & PHY_LXT971_STAT2_100BTX) {
- if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
+ if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
+ /* set DM644x EMAC for Full Duplex */
+ emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+ EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
} else {
- if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
+ /*set DM644x EMAC for Half Duplex */
+ emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
}
- return(0);
+ return(1);
}
int lxt972_init_phy(int phy_addr)
{
- int ret = 1;
+ int ret = 1;
if (!lxt972_get_link_speed(phy_addr)) {
/* Try another time */
int lxt972_auto_negotiate(int phy_addr)
{
- u_int16_t tmp;
-
+ u_int16_t tmp;
- if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_CTRL, &tmp))
+ if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
return(0);
/* Restart Auto_negotiation */
- tmp |= PHY_COMMON_CTRL_RES_AUTO;
- dm644x_eth_phy_write(phy_addr, PHY_COMMON_CTRL, tmp);
+ tmp |= PHY_BMCR_RST_NEG;
+ dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp);
/*check AutoNegotiate complete */
udelay (10000);
- if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_STAT, &tmp))
+ if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
return(0);
- if (!(tmp & PHY_COMMON_STAT_AN_COMP))
+ if (!(tmp & PHY_BMSR_AUTN_COMP))
return(0);
return (lxt972_get_link_speed(phy_addr));
return ((int)dma_check());
}
#endif /*CONFIG_DDR_ECC*/
+
+#ifdef CONFIG_TSEC_ENET
+/* Default initializations for TSEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int tsec_initialize(bd_t * bis, int index, char *devname);
+
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_TSEC1)
+ tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
+#endif
+#if defined(CONFIG_TSEC2)
+ tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
+#endif
+ return 0;
+}
+#endif
}
out_be32(mxmr, loopval); /* OP_NORMAL */
}
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC)
+/* Default initializations for TSEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int tsec_initialize(bd_t * bis, int index, char *devname);
+
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_TSEC1)
+ tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
+#endif
+#if defined(CONFIG_TSEC2)
+ tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
+#endif
+#if defined(CONFIG_MPC85XX_FEC)
+ tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
+#else
+#if defined(CONFIG_TSEC3)
+ tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
+#endif
+#if defined(CONFIG_TSEC4)
+ tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
+#endif
+#endif
+ return 0;
+}
+#endif
printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
}
+
+#ifdef CONFIG_TSEC_ENET
+/* Default initializations for TSEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int tsec_initialize(bd_t * bis, int index, char *devname);
+
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_TSEC1)
+ tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
+#endif
+#if defined(CONFIG_TSEC2)
+ tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
+#endif
+#if defined(CONFIG_TSEC3)
+ tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
+#endif
+#if defined(CONFIG_TSEC4)
+ tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
+#endif
+ return 0;
+}
+#endif
+
LIB = $(obj)lib$(CPU).a
SOBJS = start.o
-OBJS = cpu.o interrupts.o watchdog.o time.o cache.o
+COBJS = cpu.o interrupts.o watchdog.o time.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
LIB = $(obj)lib$(CPU).a
SOBJS = start.o
-OBJS = cpu.o interrupts.o watchdog.o time.o cache.o
+COBJS = cpu.o interrupts.o watchdog.o time.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
+COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t))
-u8 dev_addr[6];
-
#define PCNET_CMD 0x00
#define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */
#define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */
{
int i, r;
- PRINTK("nic base is %lx\n", nic_base);
+ PRINTK("nic base is %lx\n", nic.base);
n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD);
- PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD));
+ PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD));
n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
- PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD));
+ PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD));
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
- PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD));
+ PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD));
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
return 0;
}
-u32 nic_base;
-
/* U-boot specific routines */
static u8 *pbuf = NULL;
int eth_init(bd_t *bd) {
int r;
+ u8 dev_addr[6];
char ethaddr[20];
PRINTK("### eth_init\n");
}
#endif
- nic_base = CONFIG_DRIVER_NE2000_BASE;
nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
r = get_prom(dev_addr);
ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
/* reset PHY */
- ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET);
- ns7520_mii_write(PHY_COMMON_CTRL, 0);
+ ns7520_mii_write(PHY_BMCR, PHY_BMCR_RESET);
+ ns7520_mii_write(PHY_BMCR, 0);
udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */
/* run auto-negotation */
/* define what we are capable of */
- ns7520_mii_write(PHY_COMMON_AUTO_ADV,
- PHY_COMMON_AUTO_ADV_100BTXFD |
- PHY_COMMON_AUTO_ADV_100BTX |
- PHY_COMMON_AUTO_ADV_10BTFD |
- PHY_COMMON_AUTO_ADV_10BT |
- PHY_COMMON_AUTO_ADV_802_3);
+ ns7520_mii_write(PHY_ANAR,
+ PHY_ANLPAR_TXFD |
+ PHY_ANLPAR_TX |
+ PHY_ANLPAR_10FD |
+ PHY_ANLPAR_10 |
+ PHY_ANLPAR_PSB_802_3);
/* start auto-negotiation */
- ns7520_mii_write(PHY_COMMON_CTRL,
- PHY_COMMON_CTRL_AUTO_NEG |
- PHY_COMMON_CTRL_RES_AUTO);
+ ns7520_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
/* wait for completion */
ulStartJiffies = get_timer(0);
while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) {
- uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
+ uiStatus = ns7520_mii_read(PHY_BMSR);
if ((uiStatus &
- (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT))
- ==
- (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) {
+ (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) ==
+ (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) {
/* lucky we are, auto-negotiation succeeded */
ns7520_link_print_changed();
ns7520_link_update_egcr();
DEBUG_FN(DEBUG_LINK);
- uiControl = ns7520_mii_read(PHY_COMMON_CTRL);
+ uiControl = ns7520_mii_read(PHY_BMCR);
- if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) ==
- PHY_COMMON_CTRL_AUTO_NEG) {
- /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */
- uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
+ if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) {
+ /* PHY_BMSR_LS is only set on autonegotiation */
+ uiStatus = ns7520_mii_read(PHY_BMSR);
- if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) {
+ if (!(uiStatus & PHY_BMSR_LS)) {
printk(KERN_WARNING NS7520_DRIVER_NAME
": link down\n");
/* @TODO Linux: carrier_off */
DEBUG_FN(DEBUG_MII);
- phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1);
+ phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_PHYIDR1);
switch (phyDetected) {
case PHY_LXT971A:
szName = "LXT971A";
- uiID2 = ns7520_mii_read(PHY_COMMON_ID2);
+ uiID2 = ns7520_mii_read(PHY_PHYIDR2);
nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
cRes = 1;
break;
#include "ns9750_eth.h" /* for Ethernet and PHY */
-/* some definition to make transistion to linux easier */
+/* some definition to make transition to linux easier */
#define NS9750_DRIVER_NAME "eth"
#define KERN_WARNING "Warning:"
ns9750_mii_get_clock_divisor (nPhyMaxMdioClock);
/* reset PHY */
- ns9750_mii_write (PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET);
- ns9750_mii_write (PHY_COMMON_CTRL, 0);
+ ns9750_mii_write(PHY_BMCR, PHY_BMCR_RESET);
+ ns9750_mii_write(PHY_BMCR, 0);
/* @TODO check time */
udelay (3000); /* [2] p.70 says at least 300us reset recovery time. But
DEBUG_FN (DEBUG_LINK);
- uiControl = ns9750_mii_read (PHY_COMMON_CTRL);
- uiControl &= ~(PHY_COMMON_CTRL_SPD_MA |
- PHY_COMMON_CTRL_AUTO_NEG | PHY_COMMON_CTRL_DUPLEX);
+ uiControl = ns9750_mii_read(PHY_BMCR);
+ uiControl &= ~(PHY_BMCR_SPEED_MASK |
+ PHY_BMCR_AUTON | PHY_BMCR_DPLX);
uiLastLinkStatus = 0;
if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) ==
FS_EEPROM_AUTONEG_SPEED_100) {
- uiControl |= PHY_COMMON_CTRL_SPD_100;
+ uiControl |= PHY_BMCR_100MB;
uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX;
} else
- uiControl |= PHY_COMMON_CTRL_SPD_10;
+ uiControl |= PHY_BMCR_10_MBPS;
if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) ==
FS_EEPROM_AUTONEG_DUPLEX_FULL) {
- uiControl |= PHY_COMMON_CTRL_DUPLEX;
+ uiControl |= PHY_BMCR_DPLX;
uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE;
}
- ns9750_mii_write (PHY_COMMON_CTRL, uiControl);
+ ns9750_mii_write(PHY_BMCR, uiControl);
ns9750_link_print_changed ();
ns9750_link_update_egcr ();
/* run auto-negotation */
/* define what we are capable of */
- ns9750_mii_write (PHY_COMMON_AUTO_ADV,
- PHY_COMMON_AUTO_ADV_100BTXFD |
- PHY_COMMON_AUTO_ADV_100BTX |
- PHY_COMMON_AUTO_ADV_10BTFD |
- PHY_COMMON_AUTO_ADV_10BT |
- PHY_COMMON_AUTO_ADV_802_3);
+ ns9750_mii_write(PHY_ANAR,
+ PHY_ANLPAR_TXFD |
+ PHY_ANLPAR_TX |
+ PHY_ANLPAR_10FD |
+ PHY_ANLPAR_10 |
+ PHY_ANLPAR_PSB_802_3);
/* start auto-negotiation */
- ns9750_mii_write (PHY_COMMON_CTRL,
- PHY_COMMON_CTRL_AUTO_NEG |
- PHY_COMMON_CTRL_RES_AUTO);
+ ns9750_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
/* wait for completion */
ulStartJiffies = get_ticks ();
while (get_ticks () < ulStartJiffies + NS9750_MII_NEG_DELAY) {
- uiStatus = ns9750_mii_read (PHY_COMMON_STAT);
+ uiStatus = ns9750_mii_read(PHY_BMSR);
if ((uiStatus &
- (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) ==
- (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) {
+ (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) ==
+ (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) {
/* lucky we are, auto-negotiation succeeded */
ns9750_link_print_changed ();
ns9750_link_update_egcr ();
DEBUG_FN (DEBUG_LINK);
- uiControl = ns9750_mii_read (PHY_COMMON_CTRL);
+ uiControl = ns9750_mii_read(PHY_BMCR);
- if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) ==
- PHY_COMMON_CTRL_AUTO_NEG) {
- /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */
- uiStatus = ns9750_mii_read (PHY_COMMON_STAT);
+ if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) {
+ /* PHY_BMSR_LS is only set on autonegotiation */
+ uiStatus = ns9750_mii_read(PHY_BMSR);
- if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) {
+ if (!(uiStatus & PHY_BMSR_LS)) {
printk (KERN_WARNING NS9750_DRIVER_NAME
": link down\n");
/* @TODO Linux: carrier_off */
/* mask out all uninteresting parts */
}
- /* other PHYs must store there link information in
+ /* other PHYs must store their link information in
uiStatus as PHY_LXT971 */
}
} else {
DEBUG_FN (DEBUG_MII);
- phyDetected = (PhyType) uiID1 = ns9750_mii_read (PHY_COMMON_ID1);
+ phyDetected = (PhyType) uiID1 = ns9750_mii_read(PHY_PHYIDR1);
switch (phyDetected) {
case PHY_LXT971A:
szName = "LXT971A";
- uiID2 = ns9750_mii_read (PHY_COMMON_ID2);
+ uiID2 = ns9750_mii_read(PHY_PHYIDR2);
nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
cRes = 1;
break;
--- /dev/null
+/*
+ * sh_eth.c - Driver for Renesas SH7763's ethernet controler.
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (c) 2008 Nobuhiro Iwamatsu
+ * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include "sh_eth.h"
+
+#ifndef CONFIG_SH_ETHER_USE_PORT
+# error "Please define CONFIG_SH_ETHER_USE_PORT"
+#endif
+#ifndef CONFIG_SH_ETHER_PHY_ADDR
+# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
+#endif
+
+extern int eth_init(bd_t *bd);
+extern void eth_halt(void);
+extern int eth_rx(void);
+extern int eth_send(volatile void *packet, int length);
+
+static struct dev_info_s *dev;
+
+/*
+ * Bits are written to the PHY serially using the
+ * PIR register, just like a bit banger.
+ */
+static void sh_eth_mii_write_phy_bits(int port, u32 val, int len)
+{
+ int i;
+ u32 pir;
+
+ /* Bit positions is 1 less than the number of bits */
+ for (i = len - 1; i >= 0; i--) {
+ /* Write direction, bit to write, clock is low */
+ pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
+ outl(pir, PIR(port));
+ udelay(1);
+ /* Write direction, bit to write, clock is high */
+ pir = 3 | ((val & 1 << i) ? 1 << 2 : 0);
+ outl(pir, PIR(port));
+ udelay(1);
+ /* Write direction, bit to write, clock is low */
+ pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
+ outl(pir, PIR(port));
+ udelay(1);
+ }
+}
+
+static void sh_eth_mii_bus_release(int port)
+{
+ /* Read direction, clock is low */
+ outl(0, PIR(port));
+ udelay(1);
+ /* Read direction, clock is high */
+ outl(1, PIR(port));
+ udelay(1);
+ /* Read direction, clock is low */
+ outl(0, PIR(port));
+ udelay(1);
+}
+
+static void sh_eth_mii_ind_bus_release(int port)
+{
+ /* Read direction, clock is low */
+ outl(0, PIR(port));
+ udelay(1);
+}
+
+static int sh_eth_mii_read_phy_bits(int port, u32 * val, int len)
+{
+ int i;
+ u32 pir;
+
+ *val = 0;
+ for (i = len - 1; i >= 0; i--) {
+ /* Read direction, clock is high */
+ outl(1, PIR(port));
+ udelay(1);
+ /* Read bit */
+ pir = inl(PIR(port));
+ *val |= (pir & 8) ? 1 << i : 0;
+ /* Read direction, clock is low */
+ outl(0, PIR(port));
+ udelay(1);
+ }
+
+ return 0;
+}
+
+#define PHY_INIT 0xFFFFFFFF
+#define PHY_READ 0x02
+#define PHY_WRITE 0x01
+/*
+ * To read a phy register, mii managements frames are sent to the phy.
+ * The frames look like this:
+ * pre (32 bits): 0xffff ffff
+ * st (2 bits): 01
+ * op (2bits): 10: read 01: write
+ * phyad (5 bits): xxxxx
+ * regad (5 bits): xxxxx
+ * ta (Bus release):
+ * data (16 bits): read data
+ */
+static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg)
+{
+ u32 val;
+
+ /* Sent mii management frame */
+ /* pre */
+ sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
+ /* st (start of frame) */
+ sh_eth_mii_write_phy_bits(port, 0x1, 2);
+ /* op (code) */
+ sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
+ /* phy address */
+ sh_eth_mii_write_phy_bits(port, phy_addr, 5);
+ /* Register to read */
+ sh_eth_mii_write_phy_bits(port, reg, 5);
+
+ /* Bus release */
+ sh_eth_mii_bus_release(port);
+
+ /* Read register */
+ sh_eth_mii_read_phy_bits(port, &val, 16);
+
+ return val;
+}
+
+/*
+ * To write a phy register, mii managements frames are sent to the phy.
+ * The frames look like this:
+ * pre (32 bits): 0xffff ffff
+ * st (2 bits): 01
+ * op (2bits): 10: read 01: write
+ * phyad (5 bits): xxxxx
+ * regad (5 bits): xxxxx
+ * ta (2 bits): 10
+ * data (16 bits): write data
+ * idle (Independent bus release)
+ */
+static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val)
+{
+ /* Sent mii management frame */
+ /* pre */
+ sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
+ /* st (start of frame) */
+ sh_eth_mii_write_phy_bits(port, 0x1, 2);
+ /* op (code) */
+ sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2);
+ /* phy address */
+ sh_eth_mii_write_phy_bits(port, phy_addr, 5);
+ /* Register to read */
+ sh_eth_mii_write_phy_bits(port, reg, 5);
+ /* ta */
+ sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
+ /* Write register data */
+ sh_eth_mii_write_phy_bits(port, val, 16);
+
+ /* Independent bus release */
+ sh_eth_mii_ind_bus_release(port);
+}
+
+void eth_halt(void)
+{
+}
+
+int eth_send(volatile void *packet, int len)
+{
+ int port = dev->port;
+ struct port_info_s *port_info = &dev->port_info[port];
+ int timeout;
+ int rc = 0;
+
+ if (!packet || len > 0xffff) {
+ printf("eth_send: Invalid argument\n");
+ return -EINVAL;
+ }
+
+ /* packet must be a 4 byte boundary */
+ if ((int)packet & (4 - 1)) {
+ printf("eth_send: packet not 4 byte alligned\n");
+ return -EFAULT;
+ }
+
+ /* Update tx descriptor */
+ port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
+ port_info->tx_desc_cur->td1 = len << 16;
+ /* Must preserve the end of descriptor list indication */
+ if (port_info->tx_desc_cur->td0 & TD_TDLE)
+ port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
+ else
+ port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
+
+ /* Restart the transmitter if disabled */
+ if (!(inl(EDTRR(port)) & EDTRR_TRNS))
+ outl(EDTRR_TRNS, EDTRR(port));
+
+ /* Wait until packet is transmitted */
+ timeout = 1000;
+ while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
+ udelay(100);
+
+ if (timeout < 0) {
+ printf("eth_send: transmit timeout\n");
+ rc = -1;
+ goto err;
+ }
+
+err:
+ port_info->tx_desc_cur++;
+ if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
+ port_info->tx_desc_cur = port_info->tx_desc_base;
+
+ return rc;
+}
+
+int eth_rx(void)
+{
+ int port = dev->port;
+ struct port_info_s *port_info = &dev->port_info[port];
+ int len = 0;
+ volatile u8 *packet;
+
+ /* Check if the rx descriptor is ready */
+ if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
+ /* Check for errors */
+ if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
+ len = port_info->rx_desc_cur->rd1 & 0xffff;
+ packet = (volatile u8 *)
+ ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+ NetReceive(packet, len);
+ }
+
+ /* Make current descriptor available again */
+ if (port_info->rx_desc_cur->rd0 & RD_RDLE)
+ port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
+ else
+ port_info->rx_desc_cur->rd0 = RD_RACT;
+
+ /* Point to the next descriptor */
+ port_info->rx_desc_cur++;
+ if (port_info->rx_desc_cur >=
+ port_info->rx_desc_base + NUM_RX_DESC)
+ port_info->rx_desc_cur = port_info->rx_desc_base;
+ }
+
+ /* Restart the receiver if disabled */
+ if (!(inl(EDRRR(port)) & EDRRR_R))
+ outl(EDRRR_R, EDRRR(port));
+
+ return len;
+}
+
+#define EDMR_INIT_CNT 1000
+static int sh_eth_reset(struct dev_info_s *dev)
+{
+ int port = dev->port;
+ int i;
+
+ /* Start e-dmac transmitter and receiver */
+ outl(EDSR_ENALL, EDSR(port));
+
+ /* Perform a software reset and wait for it to complete */
+ outl(EDMR_SRST, EDMR(port));
+ for (i = 0; i < EDMR_INIT_CNT; i++) {
+ if (!(inl(EDMR(port)) & EDMR_SRST))
+ break;
+ udelay(1000);
+ }
+
+ if (i == EDMR_INIT_CNT) {
+ printf("Error: Software reset timeout\n");
+ return -1;
+ }
+ return 0;
+}
+
+static int sh_eth_tx_desc_init(struct dev_info_s *dev)
+{
+ int port = dev->port;
+ struct port_info_s *port_info = &dev->port_info[port];
+ u32 tmp_addr;
+ struct tx_desc_s *cur_tx_desc;
+ int i;
+
+ /* Allocate tx descriptors. They must be TX_DESC_SIZE bytes
+ aligned */
+ if (!(port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
+ sizeof(struct tx_desc_s) +
+ TX_DESC_SIZE - 1))) {
+ printf("Error: malloc failed\n");
+ return -ENOMEM;
+ }
+ tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
+ ~(TX_DESC_SIZE - 1));
+ /* Make sure we use a P2 address (non-cacheable) */
+ port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
+
+ port_info->tx_desc_cur = port_info->tx_desc_base;
+
+ /* Initialize all descriptors */
+ for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
+ cur_tx_desc++, i++) {
+ cur_tx_desc->td0 = 0x00;
+ cur_tx_desc->td1 = 0x00;
+ cur_tx_desc->td2 = 0x00;
+ }
+
+ /* Mark the end of the descriptors */
+ cur_tx_desc--;
+ cur_tx_desc->td0 |= TD_TDLE;
+
+ /* Point the controller to the tx descriptor list. Must use physical
+ addresses */
+ outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
+ outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
+ outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
+ outl(0x01, TDFFR(port));/* Last discriptor bit */
+
+ return 0;
+}
+
+static int sh_eth_rx_desc_init(struct dev_info_s *dev)
+{
+ int port = dev->port;
+ struct port_info_s *port_info = &dev->port_info[port];
+ u32 tmp_addr;
+ struct rx_desc_s *cur_rx_desc;
+ u8 *rx_buf;
+ int i;
+
+ /* Allocate rx descriptors. They must be RX_DESC_SIZE bytes
+ aligned */
+ if (!(port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
+ sizeof(struct rx_desc_s) +
+ RX_DESC_SIZE - 1))) {
+ printf("Error: malloc failed\n");
+ return -ENOMEM;
+ }
+ tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
+ ~(RX_DESC_SIZE - 1));
+ /* Make sure we use a P2 address (non-cacheable) */
+ port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
+
+ port_info->rx_desc_cur = port_info->rx_desc_base;
+
+ /* Allocate rx data buffers. They must be 32 bytes aligned and in
+ P2 area */
+ if (!(port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE +
+ 31))) {
+ printf("Error: malloc failed\n");
+ free(port_info->rx_desc_malloc);
+ port_info->rx_desc_malloc = NULL;
+ return -ENOMEM;
+ }
+ tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
+ ~(32 - 1));
+ port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
+
+ /* Initialize all descriptors */
+ for (cur_rx_desc = port_info->rx_desc_base,
+ rx_buf = port_info->rx_buf_base, i = 0;
+ i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
+ cur_rx_desc->rd0 = RD_RACT;
+ cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
+ cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
+ }
+
+ /* Mark the end of the descriptors */
+ cur_rx_desc--;
+ cur_rx_desc->rd0 |= RD_RDLE;
+
+ /* Point the controller to the rx descriptor list */
+ outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
+ outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
+ outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
+ outl(RDFFR_RDLF, RDFFR(port));
+
+ return 0;
+}
+
+static void sh_eth_desc_free(struct dev_info_s *dev)
+{
+ int port = dev->port;
+ struct port_info_s *port_info = &dev->port_info[port];
+
+ if (port_info->tx_desc_malloc) {
+ free(port_info->tx_desc_malloc);
+ port_info->tx_desc_malloc = NULL;
+ }
+
+ if (port_info->rx_desc_malloc) {
+ free(port_info->rx_desc_malloc);
+ port_info->rx_desc_malloc = NULL;
+ }
+
+ if (port_info->rx_buf_malloc) {
+ free(port_info->rx_buf_malloc);
+ port_info->rx_buf_malloc = NULL;
+ }
+}
+
+static int sh_eth_desc_init(struct dev_info_s *dev)
+{
+ int rc;
+
+ if ((rc = sh_eth_tx_desc_init(dev)) || (rc = sh_eth_rx_desc_init(dev))) {
+ sh_eth_desc_free(dev);
+ return rc;
+ }
+
+ return 0;
+}
+
+static int sh_eth_phy_config(struct dev_info_s *dev)
+{
+ int port = dev->port;
+ struct port_info_s *port_info = &dev->port_info[port];
+ int timeout;
+ u32 val;
+ /* Reset phy */
+ sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET);
+ timeout = 10;
+ while (timeout--) {
+ val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, PHY_CTRL);
+ if (!(val & PHY_C_RESET))
+ break;
+ udelay(50000);
+ }
+ if (timeout < 0) {
+ printf("%s phy reset timeout\n", __func__);
+ return -1;
+ }
+
+ /* Advertise 100/10 baseT full/half duplex */
+ sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA,
+ (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT));
+ /* Autonegotiation, normal operation, full duplex, enable tx */
+ sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL,
+ (PHY_C_ANEGEN|PHY_C_RANEG));
+ /* Wait for autonegotiation to complete */
+ timeout = 100;
+ while (timeout--) {
+ val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
+ if (val & PHY_S_ANEGC)
+ break;
+ udelay(50000);
+ }
+ if (timeout < 0) {
+ printf("sh_eth_phy_config() phy auto-negotiation failed\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static int sh_eth_config(struct dev_info_s *dev, bd_t * bd)
+{
+ int port = dev->port;
+ struct port_info_s *port_info = &dev->port_info[port];
+ u32 val;
+ u32 phy_status;
+ int rc;
+
+ /* Configure e-dmac registers */
+ outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
+ outl(0, EESIPR(port));
+ outl(0, TRSCER(port));
+ outl(0, TFTR(port));
+ outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
+ outl(RMCR_RST, RMCR(port));
+ outl(0, RPADIR(port));
+ outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
+
+ /* Configure e-mac registers */
+ outl(0, ECSIPR(port));
+
+ /* Set Mac address */
+ val = bd->bi_enetaddr[0] << 24 | bd->bi_enetaddr[1] << 16 |
+ bd->bi_enetaddr[2] << 8 | bd->bi_enetaddr[3];
+ outl(val, MAHR(port));
+
+ val = bd->bi_enetaddr[4] << 8 | bd->bi_enetaddr[5];
+ outl(val, MALR(port));
+
+ outl(RFLR_RFL_MIN, RFLR(port));
+ outl(0, PIPR(port));
+ outl(APR_AP, APR(port));
+ outl(MPR_MP, MPR(port));
+ outl(TPAUSER_TPAUSE, TPAUSER(port));
+
+ /* Configure phy */
+ if ((rc = sh_eth_phy_config(dev)))
+ return rc;
+
+ /* Read phy status to finish configuring the e-mac */
+ phy_status = sh_eth_mii_read_phy_reg(dev->port,
+ dev->port_info[dev->port].phy_addr,
+ 1);
+
+ /* Set the transfer speed */
+ if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
+ printf("100Base/");
+ outl(GECMR_100B, GECMR(port));
+ } else {
+ printf("10Base/");
+ outl(GECMR_10B, GECMR(port));
+ }
+
+ /* Check if full duplex mode is supported by the phy */
+ if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) {
+ printf("Full\n");
+ outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
+ } else {
+ printf("Half\n");
+ outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
+ }
+ return 0;
+}
+
+static int sh_eth_start(struct dev_info_s *dev)
+{
+ /*
+ * Enable the e-dmac receiver only. The transmitter will be enabled when
+ * we have something to transmit
+ */
+ outl(EDRRR_R, EDRRR(dev->port));
+
+ return 0;
+}
+
+static int sh_eth_get_mac(bd_t *bd)
+{
+ char *s, *e;
+ int i;
+
+ s = getenv("ethaddr");
+ if (s != NULL) {
+ for (i = 0; i < 6; ++i) {
+ bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+ } else {
+ puts("Please set MAC address\n");
+ }
+ return 0;
+}
+
+int eth_init(bd_t *bd)
+{
+ int rc;
+ /* Allocate main device information structure */
+ if (!(dev = malloc(sizeof(*dev)))) {
+ printf("eth_init: malloc failed\n");
+ return -ENOMEM;
+ }
+
+ memset(dev, 0, sizeof(*dev));
+
+ dev->port = CONFIG_SH_ETHER_USE_PORT;
+ dev->port_info[dev->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
+
+ sh_eth_get_mac(bd);
+
+ if ((rc = sh_eth_reset(dev)) || (rc = sh_eth_desc_init(dev)))
+ goto err;
+
+ if ((rc = sh_eth_config(dev, bd)) || (rc = sh_eth_start(dev)))
+ goto err_desc;
+
+ return 0;
+
+err_desc:
+ sh_eth_desc_free(dev);
+err:
+ free(dev);
+ printf("eth_init: Failed\n");
+ return rc;
+}
--- /dev/null
+/*
+ * sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler.
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (c) 2008 Nobuhiro Iwamatsu
+ * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/types.h>
+
+#define SHETHER_NAME "sh_eth"
+
+/* Malloc returns addresses in the P1 area (cacheable). However we need to
+ use area P2 (non-cacheable) */
+#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
+
+/* The ethernet controller needs to use physical addresses */
+#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
+
+/* Number of supported ports */
+#define MAX_PORT_NUM 2
+
+/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
+ buffers must be a multiple of 32 bytes */
+#define MAX_BUF_SIZE (48 * 32)
+
+/* The number of tx descriptors must be large enough to point to 5 or more
+ frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
+ We use one descriptor per frame */
+#define NUM_TX_DESC 8
+
+/* The size of the tx descriptor is determined by how much padding is used.
+ 4, 20, or 52 bytes of padding can be used */
+#define TX_DESC_PADDING 4
+#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
+
+/* Tx descriptor. We always use 4 bytes of padding */
+struct tx_desc_s {
+ volatile u32 td0;
+ u32 td1;
+ u32 td2; /* Buffer start */
+ u32 padding;
+};
+
+/* There is no limitation in the number of rx descriptors */
+#define NUM_RX_DESC 8
+
+/* The size of the rx descriptor is determined by how much padding is used.
+ 4, 20, or 52 bytes of padding can be used */
+#define RX_DESC_PADDING 4
+#define RX_DESC_SIZE (12 + RX_DESC_PADDING)
+
+/* Rx descriptor. We always use 4 bytes of padding */
+struct rx_desc_s {
+ volatile u32 rd0;
+ volatile u32 rd1;
+ u32 rd2; /* Buffer start */
+ u32 padding;
+};
+
+struct port_info_s {
+ struct tx_desc_s *tx_desc_malloc;
+ struct tx_desc_s *tx_desc_base;
+ struct tx_desc_s *tx_desc_cur;
+ struct rx_desc_s *rx_desc_malloc;
+ struct rx_desc_s *rx_desc_base;
+ struct rx_desc_s *rx_desc_cur;
+ u8 *rx_buf_malloc;
+ u8 *rx_buf_base;
+ u8 mac_addr[6];
+ u8 phy_addr;
+};
+
+struct dev_info_s {
+ int port;
+ struct port_info_s port_info[MAX_PORT_NUM];
+};
+
+/* Register Address */
+#define BASE_IO_ADDR 0xfee00000
+
+#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
+
+#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
+#define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014)
+#define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
+#define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c)
+
+#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
+#define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034)
+#define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
+#define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c)
+
+#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400)
+#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408)
+#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410)
+#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428)
+#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430)
+#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438)
+#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448)
+#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450)
+#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458)
+#define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460)
+#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468)
+#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500)
+#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508)
+#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518)
+#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520)
+#define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c)
+#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554)
+#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558)
+#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564)
+#define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
+#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
+#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
+
+/*
+ * Register's bits
+ * Copy from Linux driver source code
+ */
+#ifdef CONFIG_CPU_SH7763
+/* EDSR */
+enum EDSR_BIT {
+ EDSR_ENT = 0x01, EDSR_ENR = 0x02,
+};
+#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
+#endif
+
+/* EDMR */
+enum DMAC_M_BIT {
+ EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
+#ifdef CONFIG_CPU_SH7763
+ EDMR_SRST = 0x03,
+ EMDR_DESC_R = 0x30, /* Descriptor reserve size */
+ EDMR_EL = 0x40, /* Litte endian */
+#else /* CONFIG_CPU_SH7763 */
+ EDMR_SRST = 0x01,
+#endif
+};
+
+/* RFLR */
+#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
+
+/* EDTRR */
+enum DMAC_T_BIT {
+#ifdef CONFIG_CPU_SH7763
+ EDTRR_TRNS = 0x03,
+#else
+ EDTRR_TRNS = 0x01,
+#endif
+};
+
+/* GECMR */
+enum GECMR_BIT {
+ GECMR_1000B = 0x01, GECMR_100B = 0x40, GECMR_10B = 0x00,
+};
+
+/* EDRRR*/
+enum EDRRR_R_BIT {
+ EDRRR_R = 0x01,
+};
+
+/* TPAUSER */
+enum TPAUSER_BIT {
+ TPAUSER_TPAUSE = 0x0000ffff,
+ TPAUSER_UNLIMITED = 0,
+};
+
+/* BCFR */
+enum BCFR_BIT {
+ BCFR_RPAUSE = 0x0000ffff,
+ BCFR_UNLIMITED = 0,
+};
+
+/* PIR */
+enum PIR_BIT {
+ PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
+};
+
+/* PSR */
+enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
+
+/* EESR */
+enum EESR_BIT {
+#ifndef CONFIG_CPU_SH7763
+ EESR_TWB = 0x40000000,
+#else
+ EESR_TWB = 0xC0000000,
+ EESR_TC1 = 0x20000000,
+ EESR_TUC = 0x10000000,
+ EESR_ROC = 0x80000000,
+#endif
+ EESR_TABT = 0x04000000,
+ EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
+#ifndef CONFIG_CPU_SH7763
+ EESR_ADE = 0x00800000,
+#endif
+ EESR_ECI = 0x00400000,
+ EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
+ EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
+ EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
+#ifndef CONFIG_CPU_SH7763
+ EESR_CND = 0x00000800,
+#endif
+ EESR_DLC = 0x00000400,
+ EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
+ EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
+ EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
+ rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
+ EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
+};
+
+
+#ifdef CONFIG_CPU_SH7763
+# define TX_CHECK (EESR_TC1 | EESR_FTC)
+# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
+ | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
+# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
+
+#else
+# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
+# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
+ | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
+# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
+#endif
+
+/* EESIPR */
+enum DMAC_IM_BIT {
+ DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
+ DMAC_M_RABT = 0x02000000,
+ DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
+ DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
+ DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
+ DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
+ DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
+ DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
+ DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
+ DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
+ DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
+ DMAC_M_RINT1 = 0x00000001,
+};
+
+/* Receive descriptor bit */
+enum RD_STS_BIT {
+ RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
+ RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
+ RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
+ RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
+ RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
+ RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
+ RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
+ RD_RFS1 = 0x00000001,
+};
+#define RDF1ST RD_RFP1
+#define RDFEND RD_RFP0
+#define RD_RFP (RD_RFP1|RD_RFP0)
+
+/* RDFFR*/
+enum RDFFR_BIT {
+ RDFFR_RDLF = 0x01,
+};
+
+/* FCFTR */
+enum FCFTR_BIT {
+ FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
+ FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
+ FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
+};
+#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
+#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
+
+/* Transfer descriptor bit */
+enum TD_STS_BIT {
+#ifdef CONFIG_CPU_SH7763
+ TD_TACT = 0x80000000,
+#else
+ TD_TACT = 0x7fffffff,
+#endif
+ TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
+ TD_TFP0 = 0x10000000,
+};
+#define TDF1ST TD_TFP1
+#define TDFEND TD_TFP0
+#define TD_TFP (TD_TFP1|TD_TFP0)
+
+/* RMCR */
+enum RECV_RST_BIT { RMCR_RST = 0x01, };
+/* ECMR */
+enum FELIC_MODE_BIT {
+#ifdef CONFIG_CPU_SH7763
+ ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
+ ECMR_RZPF = 0x00100000,
+#endif
+ ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
+ ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
+ ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
+ ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
+ ECMR_PRM = 0x00000001,
+};
+
+#ifdef CONFIG_CPU_SH7763
+#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
+ ECMR_TXF | ECMR_MCT)
+#else
+#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
+#endif
+
+/* ECSR */
+enum ECSR_STATUS_BIT {
+#ifndef CONFIG_CPU_SH7763
+ ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
+#endif
+ ECSR_LCHNG = 0x04,
+ ECSR_MPD = 0x02, ECSR_ICD = 0x01,
+};
+
+#ifdef CONFIG_CPU_SH7763
+# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
+#else
+# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
+ ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
+#endif
+
+/* ECSIPR */
+enum ECSIPR_STATUS_MASK_BIT {
+#ifndef CONFIG_CPU_SH7763
+ ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
+#endif
+ ECSIPR_LCHNGIP = 0x04,
+ ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
+};
+
+#ifdef CONFIG_CPU_SH7763
+# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
+#else
+# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
+ ECSIPR_ICDIP | ECSIPR_MPDIP)
+#endif
+
+/* APR */
+enum APR_BIT {
+ APR_AP = 0x00000004,
+};
+
+/* MPR */
+enum MPR_BIT {
+ MPR_MP = 0x00000006,
+};
+
+/* TRSCER */
+enum DESC_I_BIT {
+ DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
+ DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
+ DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
+ DESC_I_RINT1 = 0x0001,
+};
+
+/* RPADIR */
+enum RPADIR_BIT {
+ RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
+ RPADIR_PADR = 0x0003f,
+};
+
+#ifdef CONFIG_CPU_SH7763
+# define RPADIR_INIT (0x00)
+#else
+# define RPADIR_INIT (RPADIR_PADS1)
+#endif
+
+/* FDR */
+enum FIFO_SIZE_BIT {
+ FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
+};
+
+enum PHY_OFFSETS {
+ PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
+ PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
+ PHY_16 = 16,
+};
+
+/* PHY_CTRL */
+enum PHY_CTRL_BIT {
+ PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
+ PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
+ PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
+};
+#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
+
+/* PHY_STAT */
+enum PHY_STAT_BIT {
+ PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
+ PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
+ PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
+ PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
+};
+
+/* PHY_ANA */
+enum PHY_ANA_BIT {
+ PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
+ PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
+ PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
+ PHY_A_SEL = 0x001e,
+ PHY_A_EXT = 0x0001,
+};
+
+/* PHY_ANL */
+enum PHY_ANL_BIT {
+ PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
+ PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
+ PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
+ PHY_L_SEL = 0x001f,
+};
+
+/* PHY_ANE */
+enum PHY_ANE_BIT {
+ PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
+ PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
+};
+
+/* DM9161 */
+enum PHY_16_BIT {
+ PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
+ PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
+ PHY_16_TXselect = 0x0400,
+ PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
+ PHY_16_Force100LNK = 0x0080,
+ PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
+ PHY_16_RPDCTR_EN = 0x0010,
+ PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
+ PHY_16_Sleepmode = 0x0002,
+ PHY_16_RemoteLoopOut = 0x0001,
+};
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.10.100
-#define CONFIG_SERVERIP 192.168.10.77
-#define CONFIG_GATEWAYIP 192.168.10.77
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.0.22
-#define CONFIG_SERVERIP 192.168.0.1
-#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_ENV_OVERWRITE 1
-/* Network setting */
-#define CONFIG_NETMASK 255.0.0.0
-#define CONFIG_IPADDR 10.0.192.51
-#define CONFIG_SERVERIP 10.0.0.1
-#define CONFIG_GATEWAYIP 10.0.0.1
-
/* SDRAM */
#define CFG_SDRAM_BASE (0x8C000000)
#define CFG_SDRAM_SIZE (0x04000000)
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
-#define CFG_MONITOR_LEN (128 * 1024)
+#define CFG_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN (256 * 1024)
+#define CFG_MALLOC_LEN (1024 * 1024)
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE (256)
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/*
- * NOR Flash
+ * NOR Flash ( Spantion S29GL256P )
*/
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
-
-#if defined(CONFIG_R2DPLUS_OLD)
-#define CFG_FLASH_BASE (0xA0000000)
-#define CFG_MAX_FLASH_BANKS (1) /* Max number of
- * Flash memory banks
- */
-#define CFG_MAX_FLASH_SECT 142
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
-
-#else /* CONFIG_R2DPLUS_OLD */
-
#define CFG_FLASH_BASE (0xA0000000)
-#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */
-#define CFG_MAX_FLASH_BANKS (2)
-#define CFG_MAX_FLASH_SECT 270
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
- CFG_FLASH_BASE + 0x100000,\
- CFG_FLASH_BASE + 0x400000,\
- CFG_FLASH_BASE + 0x700000, }
-#endif /* CONFIG_R2DPLUS_OLD */
+#define CFG_MAX_FLASH_BANKS (1)
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000
-#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT 120000
-#define CFG_FLASH_WRITE_TOUT 500
+#define CFG_ENV_SECT_SIZE 0x40000
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
/*
* SuperH Clock setting
/*
* Configuation settings for the Renesas R7780MP board
*
- * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_SH4A 1
#define CONFIG_CPU_SH7780 1
#define CONFIG_R7780MP 1
-#define __LITTLE_ENDIAN 1
+#define CFG_R7780MP_OLD_FLASH 1
+#define __LITTLE_ENDIAN__ 1
/*
* Command line configuration.
/* check for keypress on bootdelay==0 */
/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
-/* Network setting */
-#define CONFIG_NETMASK 255.0.0.0
-#define CONFIG_IPADDR 10.0.192.82
-#define CONFIG_SERVERIP 10.0.0.1
-#define CONFIG_GATEWAYIP 10.0.0.1
-
#define CFG_SDRAM_BASE (0x08000000)
#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
-/* NOR Flash (S29PL127J60TFI130) */
+/* Flash board support */
#define CFG_FLASH_BASE (0xA0000000)
-#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-#define CFG_MAX_FLASH_BANKS (2)
-#define CFG_MAX_FLASH_SECT 270
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
+#ifdef CFG_R7780MP_OLD_FLASH
+/* NOR Flash (S29PL127J60TFI130) */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+# define CFG_MAX_FLASH_BANKS (2)
+# define CFG_MAX_FLASH_SECT 270
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
CFG_FLASH_BASE + 0x100000,\
CFG_FLASH_BASE + 0x400000,\
CFG_FLASH_BASE + 0x700000, }
+#else /* CFG_R7780MP_OLD_FLASH */
+/* NOR Flash (Spantion S29GL256P) */
+# define CFG_MAX_FLASH_BANKS (1)
+# define CFG_MAX_FLASH_SECT 256
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#endif /* CFG_R7780MP_OLD_FLASH */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
-#define CFG_MONITOR_LEN (112 * 1024)
+#define CFG_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN (256 * 1024)
+#define CFG_MALLOC_LEN (1204 * 1024)
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE (256)
#define CFG_FLASH_EMPTY_INFO
#define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE (16 * 1024)
+#define CFG_ENV_SECT_SIZE (256 * 1024)
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_FLASH_ERASE_TOUT 120000
#endif /* CONFIG_CMD_PCI */
#if defined(CONFIG_CMD_NET)
-/* #define CONFIG_NET_MULTI
- #define CONFIG_RTL8169 */
+/*
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8169
+*/
/* AX88696L Support(NE2000 base chip) */
#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_AX88796L
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_JFFS2
#define CONFIG_BOOTDELAY -1
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
settings for this board */
-/* Ethernet */
-#define CONFIG_SH_ETHER 1
-#define CONFIG_SH_ETHER_USE_PORT (1)
-#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
-#define CFG_RX_ETH_BUFFER (8)
-
/* SDRAM */
#define CFG_SDRAM_BASE (0x8C000000)
#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
#define __LXT971A_H__
/* PHY definitions (LXT971A) [2] */
-#define PHY_COMMON_CTRL (0x00)
-#define PHY_COMMON_STAT (0x01)
-#define PHY_COMMON_ID1 (0x02)
-#define PHY_COMMON_ID2 (0x03)
-#define PHY_COMMON_AUTO_ADV (0x04)
-#define PHY_COMMON_AUTO_LNKB (0x05)
-#define PHY_COMMON_AUTO_EXP (0x06)
-#define PHY_COMMON_AUTO_NEXT (0x07)
-#define PHY_COMMON_AUTO_LNKN (0x08)
#define PHY_LXT971_PORT_CFG (0x10)
#define PHY_LXT971_STAT2 (0x11)
#define PHY_LXT971_INT_ENABLE (0x12)
#define PHY_LXT971_DIG_CFG (0x1A)
#define PHY_LXT971_TX_CTRL (0x1E)
-/* CTRL PHY Control Register Bit Fields */
-#define PHY_COMMON_CTRL_RESET (0x8000)
-#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
-#define PHY_COMMON_CTRL_SPD_MA (0x2040)
-#define PHY_COMMON_CTRL_SPD_10 (0x0000)
-#define PHY_COMMON_CTRL_SPD_100 (0x2000)
-#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
-#define PHY_COMMON_CTRL_SPD_RES (0x2040)
-#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
-#define PHY_COMMON_CTRL_POWER_DN (0x0800)
-#define PHY_COMMON_CTRL_ISOLATE (0x0400)
-#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
-#define PHY_COMMON_CTRL_DUPLEX (0x0100)
-#define PHY_COMMON_CTRL_COL_TEST (0x0080)
-#define PHY_COMMON_CTRL_RES1 (0x003F)
-
-/* STAT Status Register Bit Fields */
-#define PHY_COMMON_STAT_100BT4 (0x8000)
-#define PHY_COMMON_STAT_100BXFD (0x4000)
-#define PHY_COMMON_STAT_100BXHD (0x2000)
-#define PHY_COMMON_STAT_10BTFD (0x1000)
-#define PHY_COMMON_STAT_10BTHD (0x0800)
-#define PHY_COMMON_STAT_100BT2FD (0x0400)
-#define PHY_COMMON_STAT_100BT2HD (0x0200)
-#define PHY_COMMON_STAT_EXT_STAT (0x0100)
-#define PHY_COMMON_STAT_RES1 (0x0080)
-#define PHY_COMMON_STAT_MF_PSUP (0x0040)
-#define PHY_COMMON_STAT_AN_COMP (0x0020)
-#define PHY_COMMON_STAT_RMT_FLT (0x0010)
-#define PHY_COMMON_STAT_AN_CAP (0x0008)
-#define PHY_COMMON_STAT_LNK_STAT (0x0004)
-#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
-#define PHY_COMMON_STAT_EXT_CAP (0x0001)
-
-/* AUTO_ADV Auto-neg Advert Register Bit Fields */
-#define PHY_COMMON_AUTO_ADV_NP (0x8000)
-#define PHY_COMMON_AUTO_ADV_RES1 (0x4000)
-#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000)
-#define PHY_COMMON_AUTO_ADV_RES2 (0x1000)
-#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800)
-#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400)
-#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200)
-#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
-#define PHY_COMMON_AUTO_ADV_100BTX (0x0080)
-#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
-#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
-#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F)
-#define PHY_COMMON_AUTO_ADV_802_9 (0x0002)
-#define PHY_COMMON_AUTO_ADV_802_3 (0x0001)
-
-/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
-#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
-#define PHY_COMMON_AUTO_LNKB_ACK (0x4000)
-#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000)
-#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000)
-#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800)
-#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400)
-#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200)
-#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100)
-#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080)
-#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
-#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
-#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
-#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002)
-#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001)
-
-/* AUTO_EXP Auto-neg Expansion Register Bit Fields */
-#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0)
-#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020)
-#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010)
-#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008)
-#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004)
-#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002)
-#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001)
-
-/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
-#define PHY_COMMON_AUTO_NEXT_NP (0x8000)
-#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000)
-#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000)
-#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000)
-#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800)
-#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF)
-
-/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
-#define PHY_COMMON_AUTO_LNKN_NP (0x8000)
-#define PHY_COMMON_AUTO_LNKN_ACK (0x4000)
-#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000)
-#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000)
-#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800)
-#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF)
-
/* PORT_CFG Port Configuration Register Bit Fields */
#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
#ifdef CONFIG_DRIVER_NS7520_ETHERNET
+#include <miiphy.h>
#include "lxt971a.h"
/* The port addresses */
#ifdef CONFIG_DRIVER_NS9750_ETHERNET
+#include <miiphy.h>
#include "lxt971a.h"
#define NS9750_ETH_MODULE_BASE (0xA0600000)
}
/*
- * print sizes as "xxx kB", "xxx.y kB", "xxx MB" or "xxx.y MB" as needed;
- * allow for optional trailing string (like "\n")
+ * print sizes as "xxx kB", "xxx.y kB", "xxx MB", "xxx.y MB",
+ * xxx GB, or xxx.y GB as needed; allow for optional trailing string
+ * (like "\n")
*/
void print_size (phys_size_t size, const char *s)
{
- ulong m, n;
- ulong d = 1 << 20; /* 1 MB */
- char c = 'M';
-
- if (size < d) { /* print in kB */
- c = 'k';
- d = 1 << 10;
+ ulong m = 0, n;
+ phys_size_t d = 1 << 30; /* 1 GB */
+ char c = 'G';
+
+ if (size < d) { /* try MB */
+ c = 'M';
+ d = 1 << 20;
+ if (size < d) { /* print in kB */
+ c = 'k';
+ d = 1 << 10;
+ }
}
n = size / d;
- m = (10 * (size - (n * d)) + (d / 2) ) / d;
+ /* If there's a remainder, deal with it */
+ if(size % d) {
+ m = (10 * (size - (n * d)) + (d / 2) ) / d;
- if (m >= 10) {
- m -= 10;
- n += 1;
+ if (m >= 10) {
+ m -= 10;
+ n += 1;
+ }
}
printf ("%2ld", n);
COBJS-y += board.o
COBJS-y += bootm.o
-#COBJS-y += time.o
+# COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
return 0;
}
+#if defined(CONFIG_CMD_NET)
static int sh_net_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#endif
typedef int (init_fnc_t) (void);
bd_t *bd;
init_fnc_t **init_fnc_ptr;
- char *s;
int i;
+ char *s;
memset (gd, 0, CFG_GBL_DATA_SIZE);
*/
#include <common.h>
-#include <asm/processer.h>
+#include <asm/processor.h>
static void tmu_timer_start (unsigned int timer)
{
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+/*
+ * CPU and board-specific Ethernet initializations. Aliased function
+ * signals caller to move on
+ */
+static int __def_eth_init(bd_t *bis)
+{
+ return -1;
+}
+int cpu_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init")));
+int board_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init")));
+
#ifdef CFG_GT_6426x
extern int gt6426x_eth_initialize(bd_t *bis);
#endif
extern int skge_initialize(bd_t*);
extern int tsi108_eth_initialize(bd_t*);
extern int uli526x_initialize(bd_t *);
-extern int tsec_initialize(bd_t*, int, char *);
extern int npe_initialize(bd_t *);
extern int uec_initialize(int);
extern int bfin_EMAC_initialize(bd_t *);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_init();
#endif
+ /* Try board-specific initialization first. If it fails or isn't
+ * present, try the cpu-specific initialization */
+ if (board_eth_init(bis) < 0)
+ cpu_eth_init(bis);
#if defined(CONFIG_DB64360) || defined(CONFIG_CPCI750)
mv6436x_eth_initialize(bis);
#if defined(CONFIG_SK98)
skge_initialize(bis);
#endif
-#if defined(CONFIG_TSEC1)
- tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
-#endif
-#if defined(CONFIG_TSEC2)
- tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
-#endif
-#if defined(CONFIG_MPC85XX_FEC)
- tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
-#else
-# if defined(CONFIG_TSEC3)
- tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
-# endif
-# if defined(CONFIG_TSEC4)
- tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
-# endif
-#endif
#if defined(CONFIG_UEC_ETH1)
uec_initialize(0);
#endif
projects / people / ms / u-boot.git / commitdiff
