cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
all: $(ALL-y)
-ifneq ($(CONFIG_SYS_GENERIC_BOARD),y)
- @echo "===================== WARNING ======================"
- @echo "Please convert this board to generic board."
- @echo "Otherwise it will be removed by the end of 2014."
- @echo "See doc/README.generic-board for further information"
- @echo "===================================================="
-endif
ifeq ($(CONFIG_DM_I2C_COMPAT),y)
@echo "===================== WARNING ======================"
@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
prepare1: prepare2 $(version_h) $(timestamp_h) \
include/config/auto.conf
-ifeq ($(CONFIG_HAVE_GENERIC_BOARD),)
-ifeq ($(CONFIG_SYS_GENERIC_BOARD),y)
- @echo >&2 " Your architecture does not support generic board."
- @echo >&2 " Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file."
- @/bin/false
-endif
-endif
ifeq ($(wildcard $(LDSCRIPT)),)
@echo >&2 " Could not find linker script."
@/bin/false
If defined, don't allow the -f switch to env set override variable
access flags.
-- CONFIG_SYS_GENERIC_BOARD
- This selects the architecture-generic board system instead of the
- architecture-specific board files. It is intended to move boards
- to this new framework over time. Defining this will disable the
- arch/foo/lib/board.c file and use common/board_f.c and
- common/board_r.c instead. To use this option your architecture
- must support it (i.e. must select HAVE_GENERIC_BOARD in arch/Kconfig).
- If you find problems enabling this option on your board please report
- the problem and send patches!
-
- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
This is set by OMAP boards for the max time that reset should
be asserted. See doc/README.omap-reset-time for details on how
config CREATE_ARCH_SYMLINK
bool
-config HAVE_GENERIC_BOARD
- bool
-
-config SYS_GENERIC_BOARD
- bool
- depends on HAVE_GENERIC_BOARD
-
choice
prompt "Architecture select"
default SANDBOX
config ARC
bool "ARC architecture"
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config ARM
bool "ARM architecture"
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config AVR32
bool "AVR32 architecture"
select CREATE_ARCH_SYMLINK
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
config BLACKFIN
bool "Blackfin architecture"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
config M68K
bool "M68000 architecture"
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
config MICROBLAZE
bool "MicroBlaze architecture"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config MIPS
bool "MIPS architecture"
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config NDS32
bool "NDS32 architecture"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
config NIOS2
bool "Nios II architecture"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
config PPC
bool "PowerPC architecture"
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config SANDBOX
bool "Sandbox"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
select DM
select DM_SPI_FLASH
config SPARC
bool "SPARC architecture"
- select HAVE_GENERIC_BOARD
select CREATE_ARCH_SYMLINK
config X86
bool "x86 architecture"
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
select DM
select DM_SERIAL
select DM
select DM_SERIAL
-config TARGET_AM43XX_EVM
- bool "Support am43xx_evm"
- select CPU_V7
- select SUPPORT_SPL
- select TI_I2C_BOARD_DETECT
-
config TARGET_BAV335X
bool "Support bav335x"
select CPU_V7
select SUPPORT_SPL
select CMD_POWEROFF
+config ARCH_MESON
+ bool "Amlogic Meson"
+ help
+ Support for the Meson SoC family developed by Amlogic Inc.,
+ targeted at media players and tablet computers. We currently
+ support the S905 (GXBaby) 64-bit SoC.
+
config ARCH_MX7
bool "Freescale MX7"
select CPU_V7
select CPU_V7
select SUPPORT_SPL
+config AM43XX
+ bool "AM43XX SoC"
+ select CPU_V7
+ select SUPPORT_SPL
+ help
+ Support for AM43xx SOC from Texas Instruments.
+ The AM43xx high performance SOC features a Cortex-A9
+ ARM core, a quad core PRU-ICSS for industrial Ethernet
+ protocols, dual camera support, optional 3D graphics
+ and an optional customer programmable secure boot.
+
config RMOBILE
bool "Renesas ARM SoCs"
select CPU_V7
source "arch/arm/cpu/armv7/mx5/Kconfig"
-source "arch/arm/cpu/armv7/omap3/Kconfig"
-
-source "arch/arm/cpu/armv7/omap4/Kconfig"
-
-source "arch/arm/cpu/armv7/omap5/Kconfig"
+source "arch/arm/cpu/armv7/omap-common/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/cpu/armv7/rmobile/Kconfig"
+source "arch/arm/mach-meson/Kconfig"
+
source "arch/arm/mach-rockchip/Kconfig"
source "arch/arm/mach-s5pc1xx/Kconfig"
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
+machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
--- /dev/null
+if AM43XX
+config TARGET_AM43XX_EVM
+ bool "Support am43xx_evm"
+ select TI_I2C_BOARD_DETECT
+ help
+ This option specifies support for the AM43xx
+ GP and HS EVM development platforms.The AM437x
+ GP EVM is a standalone test, development, and
+ evaluation module system that enables developers
+ to write software and develop hardware around
+ an AM43xx processor subsystem.
+
+config ISW_ENTRY_ADDR
+ hex "Address in memory or XIP flash of bootloader entry point"
+ help
+ After any reset, the boot ROM on the AM43XX SOC
+ searches the boot media for a valid boot image.
+ For non-XIP devices, the ROM then copies the
+ image into internal memory.
+ For all boot modes, after the ROM processes the
+ boot image it eventually computes the entry
+ point address depending on the device type
+ (secure/non-secure), boot media (xip/non-xip) and
+ image headers.
+ default 0x402F4000
+
+config PUB_ROM_DATA_SIZE
+ hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+ help
+ During the device boot, the public ROM uses the top of
+ the public L3 OCMC RAM to store r/w data like stack,
+ heap, globals etc. When the ROM is copying the boot
+ image from the boot media into memory, the image must
+ not spill over into this area. This value can be used
+ during compile time to determine the maximum size of a
+ boot image. Once the ROM transfers control to the boot
+ image, this area is no longer used, and can be reclaimed
+ for run time use by the boot image.
+ default 0x8400
+endif
obj-y += emif4.o
obj-y += board.o
obj-y += mux.o
+
+obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o
--- /dev/null
+/*
+ * clk-synthesizer.c
+ *
+ * Clock synthesizer apis
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <i2c.h>
+
+/**
+ * clk_synthesizer_reg_read - Read register from synthesizer.
+ * @addr: addr within the i2c device
+ * buf: Buffer to which value is to be read.
+ *
+ * For reading the register from this clock synthesizer, a command needs to
+ * be send along with enabling byte read more, and then read can happen.
+ * Returns 0 on success
+ */
+static int clk_synthesizer_reg_read(int addr, uint8_t *buf)
+{
+ int rc;
+
+ /* Enable Bye read */
+ addr = addr | CLK_SYNTHESIZER_BYTE_MODE;
+
+ /* Send the command byte */
+ rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
+ if (rc)
+ printf("Failed to send command to clock synthesizer\n");
+
+ /* Read the Data */
+ return i2c_read(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
+}
+
+/**
+ * clk_synthesizer_reg_write - Write a value to register in synthesizer.
+ * @addr: addr within the i2c device
+ * val: Value to be written in the addr.
+ *
+ * Enable the byte read mode in the address and start the i2c transfer.
+ * Returns 0 on success
+ */
+static int clk_synthesizer_reg_write(int addr, uint8_t val)
+{
+ uint8_t cmd[2];
+ int rc = 0;
+
+ /* Enable byte write */
+ cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE;
+ cmd[1] = val;
+
+ rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2);
+ if (rc)
+ printf("Clock synthesizer reg write failed at addr = 0x%x\n",
+ addr);
+ return rc;
+}
+
+/**
+ * setup_clock_syntherizer - Program the clock synthesizer to get the desired
+ * frequency.
+ * @data: Data containing the desired output
+ *
+ * This is a PLL-based high performance synthesizer which gives 3 outputs
+ * as per the PLL_DIV and load capacitor programmed.
+ */
+int setup_clock_synthesizer(struct clk_synth *data)
+{
+ int rc;
+ uint8_t val;
+
+ rc = i2c_probe(CLK_SYNTHESIZER_I2C_ADDR);
+ if (rc) {
+ printf("i2c probe failed at address 0x%x\n",
+ CLK_SYNTHESIZER_I2C_ADDR);
+ return rc;
+ }
+
+ rc = clk_synthesizer_reg_read(CLK_SYNTHESIZER_ID_REG, &val);
+ if (val != data->id)
+ return rc;
+
+ /* Crystal Load capacitor selection */
+ rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_XCSEL, data->capacitor);
+ if (rc)
+ return rc;
+ rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_MUX_REG, data->mux);
+ if (rc)
+ return rc;
+ rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2);
+ if (rc)
+ return rc;
+ rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3);
+ if (rc)
+ return rc;
+
+ return 0;
+}
#
# SPDX-License-Identifier: GPL-2.0+
#
+
+include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+#
+# For booting from SPI use
+# u-boot-spl_HS_SPI_X-LOADER to program flash
+#
+# For booting spl from all other media
+# use u-boot-spl_HS_ISSW
+#
+# Refer to README.ti-secure for more info
+#
+ALL-y += u-boot-spl_HS_ISSW
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
+else
ALL-y += MLO
ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
+endif
else
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
+endif
ALL-y += u-boot.img
endif
--- /dev/null
+config TI_SECURE_DEVICE
+ bool "HS Device Type Support"
+ depends on OMAP54XX || AM43XX
+ help
+ If a high secure (HS) device type is being used, this config
+ must be set. This option impacts various aspects of the
+ build system (to create signed boot images that can be
+ authenticated) and the code. See the doc/README.ti-secure
+ file for further details.
+
+source "arch/arm/cpu/armv7/omap3/Kconfig"
+
+source "arch/arm/cpu/armv7/omap4/Kconfig"
+
+source "arch/arm/cpu/armv7/omap5/Kconfig"
+
+source "arch/arm/cpu/armv7/am33xx/Kconfig"
/* Dpll locked with ideal values for nominal opps. */
debug("\n %s Dpll already locked with ideal"
"nominal opp values", dpll);
+
+ bypass_dpll(base);
goto setup_post_dividers;
}
}
writel(temp, &dpll_regs->cm_clksel_dpll);
+setup_post_dividers:
+ setup_post_dividers(base, params);
+
/* Lock */
if (lock)
do_lock_dpll(base);
-setup_post_dividers:
- setup_post_dividers(base, params);
-
/* Wait till the DPLL locks */
if (lock)
wait_for_lock(base);
--- /dev/null
+#
+# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+quiet_cmd_mkomapsecimg = MKIMAGE $@
+ifneq ($(TI_SECURE_DEV_PKG),)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
+ifneq ($(CONFIG_SPL_BUILD),)
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+ $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+else
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+ $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+endif
+else
+cmd_mkomapsecimg = echo "WARNING:" \
+ "$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \
+ "$@ was NOT created!"
+endif
+else
+cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
+ "variable must be defined for TI secure devices. $@ was NOT created!"
+endif
+
+# Standard X-LOADER target (QPSI, NOR flash)
+u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# For MLO targets (SD card boot) the final file name
+# that is copied to the SD card fAT partition must
+# be MLO, so we make a copy of the output file to a
+# new file with that name
+u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+ @if [ -f $@ ]; then \
+ cp -f $@ MLO; \
+ fi
+
+# Standard 2ND target (certain peripheral boot modes)
+u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# Standard ULO target (certain peripheral boot modes)
+u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# Standard ISSW target (certain devices, various boot modes)
+u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# For SPI flash on AM335x and AM43xx, these
+# require special byte swap handling so we use
+# the SPI_X-LOADER target instead of X-LOADER
+# and let the create-boot-image.sh script handle
+# that
+u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# For supporting single stage XiP QSPI on AM43xx, the
+# image is a full u-boot file, not an SPL. In this case
+# the mkomapsecimg command looks for a u-boot-HS_* prefix
+u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin
+ $(call if_changed,mkomapsecimg)
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
+ const char *sec_s;
+
+ switch (get_device_type()) {
+ case TST_DEVICE:
+ sec_s = "TST";
+ break;
+ case EMU_DEVICE:
+ sec_s = "EMU";
+ break;
+ case HS_DEVICE:
+ sec_s = "HS";
+ break;
+ case GP_DEVICE:
+ sec_s = "GP";
+ break;
+ default:
+ sec_s = "?";
+ }
+
if (soc_variant)
printf("OMAP");
else
printf("DRA");
- printf("%x ES%x.%x\n", omap_variant, major_rev,
- minor_rev);
+ printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
}
#ifdef CONFIG_SPL_BUILD
obj-y += prcm-regs.o
obj-y += hw_data.o
obj-y += abb.o
+obj-y += fdt.o
obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
# SPDX-License-Identifier: GPL-2.0+
#
+include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-y += u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER
+else
ALL-y += MLO
+endif
else
ALL-y += u-boot.img
endif
--- /dev/null
+/*
+ * Copyright 2016 Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <malloc.h>
+
+#include <asm/omap_common.h>
+#include <asm/arch-omap5/sys_proto.h>
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+
+/* Give zero values if not already defined */
+#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
+#endif
+#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#endif
+
+static u32 hs_irq_skip[] = {
+ 8, /* Secure violation reporting interrupt */
+ 15, /* One interrupt for SDMA by secure world */
+ 118 /* One interrupt for Crypto DMA by secure world */
+};
+
+static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+ int len, i, old_cnt, new_cnt;
+ u32 *temp;
+ const u32 *p_data;
+
+ /*
+ * Increase the size of the fdt
+ * so we have some breathing room
+ */
+ ret = fdt_increase_size(fdt, 512);
+ if (ret < 0) {
+ printf("Could not increase size of device tree: %s\n",
+ fdt_strerror(ret));
+ return ret;
+ }
+
+ /* Reserve IRQs that are used/needed by secure world */
+ path = "/ocp/crossbar";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+
+ /* Get current entries */
+ p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
+ if (p_data)
+ old_cnt = len / sizeof(u32);
+ else
+ old_cnt = 0;
+
+ new_cnt = sizeof(hs_irq_skip) /
+ sizeof(hs_irq_skip[0]);
+
+ /* Create new/updated skip list for HS parts */
+ temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
+ for (i = 0; i < new_cnt; i++)
+ temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
+ for (i = 0; i < old_cnt; i++)
+ temp[i + new_cnt] = p_data[i];
+
+ /* Blow away old data and set new data */
+ fdt_delprop(fdt, offs, "ti,irqs-skip");
+ ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
+ temp,
+ (old_cnt + new_cnt) * sizeof(u32));
+ free(temp);
+
+ /* Check if the update worked */
+ if (ret < 0) {
+ printf("Could not add ti,irqs-skip property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ft_hs_disable_rng(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+
+ /* Make HW RNG reserved for secure world use */
+ path = "/ocp/rng";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+ ret = fdt_setprop_string(fdt, offs,
+ "status", "disabled");
+ if (ret < 0) {
+ printf("Could not add status property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+ return 0;
+}
+
+#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
+ (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+ u32 temp[2];
+
+ /*
+ * Update SRAM reservations on secure devices. The OCMC RAM
+ * is always reserved for secure use from the start of that
+ * memory region
+ */
+ path = "/ocp/ocmcram@40300000/sram-hs";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+
+ /* relative start offset */
+ temp[0] = cpu_to_fdt32(0);
+ /* reservation size */
+ temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
+ CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
+ fdt_delprop(fdt, offs, "reg");
+ ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
+ if (ret < 0) {
+ printf("Could not add reg property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+
+ return 0;
+}
+#else
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
+#endif
+
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+ /* Check we are running on an HS/EMU device type */
+ if (GP_DEVICE != get_device_type()) {
+ if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
+ (ft_hs_disable_rng(fdt, bd) == 0) &&
+ (ft_hs_fixup_sram(fdt, bd) == 0))
+ return;
+ } else {
+ printf("ERROR: Incorrect device type (GP) detected!");
+ }
+ /* Fixup failed or wrong device type */
+ hang();
+}
+#else
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+}
+#endif
+
+/*
+ * Place for general cpu/SoC FDT fixups. Board specific
+ * fixups should remain in the board files which is where
+ * this function should be called from.
+ */
+void ft_cpu_setup(void *fdt, bd_t *bd)
+{
+ ft_hs_fixups(fdt, bd);
+}
#include <linux/linkage.h>
/*
- * void __asm_flush_dcache_level(level)
+ * void __asm_dcache_level(level)
*
- * clean and invalidate one level cache.
+ * flush or invalidate one level cache.
*
* x0: cache level
- * x1: 0 flush & invalidate, 1 invalidate only
+ * x1: 0 clean & invalidate, 1 invalidate only
* x2~x9: clobbered
*/
-ENTRY(__asm_flush_dcache_level)
+ENTRY(__asm_dcache_level)
lsl x12, x0, #1
msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
b.ge loop_set
ret
-ENDPROC(__asm_flush_dcache_level)
+ENDPROC(__asm_dcache_level)
/*
* void __asm_flush_dcache_all(int invalidate_only)
*
- * x0: 0 flush & invalidate, 1 invalidate only
+ * x0: 0 clean & invalidate, 1 invalidate only
*
- * clean and invalidate all data cache by SET/WAY.
+ * flush or invalidate all data cache by SET/WAY.
*/
ENTRY(__asm_dcache_all)
mov x1, x0
and x12, x12, #7 /* x12 <- cache type */
cmp x12, #2
b.lt skip /* skip if no cache or icache */
- bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */
+ bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */
skip:
add x0, x0, #1 /* increment cache level */
cmp x11, x0
ENDPROC(__asm_dcache_all)
ENTRY(__asm_flush_dcache_all)
- mov x16, lr
mov x0, #0
- bl __asm_dcache_all
- mov lr, x16
- ret
+ b __asm_dcache_all
ENDPROC(__asm_flush_dcache_all)
ENTRY(__asm_invalidate_dcache_all)
- mov x16, lr
mov x0, #0x1
- bl __asm_dcache_all
- mov lr, x16
- ret
+ b __asm_dcache_all
ENDPROC(__asm_invalidate_dcache_all)
/*
#include <config.h>
#include <version.h>
#include <asm/macro.h>
+#include <asm/psci.h>
#include <asm/system.h>
/*
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
"x16", "x17");
}
+
+void __noreturn psci_system_reset(bool conduit_smc)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
+
+ if (conduit_smc)
+ smc_call(®s);
+ else
+ hvc_call(®s);
+
+ while (1)
+ ;
+}
rk3288-jerry.dtb \
rk3288-rock2-square.dtb \
rk3036-sdk.dtb
+dtb-$(CONFIG_ARCH_MESON) += \
+ meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm019-dc5.dtb
-dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
-dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \
+ am335x-evmsk.dtb \
+ am335x-bonegreen.dtb \
+ am335x-icev2.dtb
+dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
+ am43x-epos-evm.dtb \
+ am437x-idk-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
};
};
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&aes {
/ {
model = "TI AM335x BeagleBone";
compatible = "ti,am335x-bone", "ti,am33xx";
- chosen {
- stdout-path = &uart0;
- };
};
&ldo3_reg {
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+/ {
+ model = "TI AM335x BeagleBone Green";
+ compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+};
+
+&ldo3_reg {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmcsd_fixed>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vmmcsd_fixed>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&am33xx_pinmux {
+ uart2_pins: uart2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
+ AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
+ >;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&rtc {
+ system-power-controller;
+};
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&mmc3 {
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * AM335x Starter Kit
+ * http://www.ti.com/tool/tmdssk3358
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "TI AM335x EVM-SK";
+ compatible = "ti,am335x-evmsk", "ti,am33xx";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
+ lis3_reg: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "lis3_reg";
+ regulator-boot-on;
+ };
+
+ wl12xx_vmmc: fixedregulator@2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_gpio>;
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio1 29 0>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ vtt_fixed: fixedregulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_s0>;
+
+ compatible = "gpio-leds";
+
+ led@1 {
+ label = "evmsk:green:usr0";
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@2 {
+ label = "evmsk:green:usr1";
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "evmsk:green:mmc0";
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led@4 {
+ label = "evmsk:green:heartbeat";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ gpio_buttons: gpio_buttons@0 {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@1 {
+ label = "button0";
+ linux,code = <0x100>;
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ switch@2 {
+ label = "button1";
+ linux,code = <0x101>;
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ switch@3 {
+ label = "button2";
+ linux,code = <0x102>;
+ gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
+ };
+
+ switch@4 {
+ label = "button3";
+ linux,code = <0x103>;
+ gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 58 61 66 75 90 125 170 255>;
+ default-brightness-level = <8>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM335x-EVMSK";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ system-clock-frequency = <24000000>;
+ };
+ };
+
+ panel {
+ compatible = "ti,tilcdc,panel";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&lcd_pins_default>;
+ pinctrl-1 = <&lcd_pins_sleep>;
+ status = "okay";
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz = <16>;
+ bpp = <32>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
+ };
+ display-timings {
+ 480x272 {
+ hactive = <480>;
+ vactive = <272>;
+ hback-porch = <43>;
+ hfront-porch = <8>;
+ hsync-len = <4>;
+ vback-porch = <12>;
+ vfront-porch = <4>;
+ vsync-len = <10>;
+ clock-frequency = <9000000>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
+
+ lcd_pins_default: lcd_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
+ AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
+ AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
+ AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
+ AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
+ AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
+ AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
+ AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
+ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
+ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
+ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
+ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
+ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
+ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
+ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
+ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
+ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
+ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
+ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
+ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
+ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
+ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
+ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
+ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
+ AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
+ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
+ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
+ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
+ >;
+ };
+
+ lcd_pins_sleep: lcd_pins_sleep {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */
+ AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */
+ AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */
+ AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */
+ AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */
+ AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */
+ AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */
+ AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */
+ AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
+ AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
+ AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
+ AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
+ AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
+ AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
+ AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
+ AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
+ AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
+ AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
+ AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
+ AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
+ AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
+ AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
+ AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
+ AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
+ AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */
+ AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
+ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
+ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
+ >;
+ };
+
+
+ user_leds_s0: user_leds_s0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
+ AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
+ AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
+ AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
+ >;
+ };
+
+ gpio_keys_s0: gpio_keys_s0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
+ AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
+ AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
+ AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+ >;
+ };
+
+ ecap2_pins: backlight_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+ AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+ AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+ AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+ AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+ AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
+ AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
+ AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
+
+ /* Slave 2 */
+ AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
+ AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
+ AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
+ AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
+ AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
+ AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
+ AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
+ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
+ AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
+ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+ /* Slave 2 reset value*/
+ AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+ >;
+ };
+
+ mcasp1_pins: mcasp1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+ AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+ >;
+ };
+
+ mcasp1_pins_sleep: mcasp1_pins_sleep {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
+ AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+ AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+ >;
+ };
+
+ wl12xx_gpio: pinmux_wl12xx_gpio {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@2d {
+ reg = <0x2d>;
+ };
+
+ lis331dlh: lis331dlh@18 {
+ compatible = "st,lis331dlh", "st,lis3lv02d";
+ reg = <0x18>;
+ Vdd-supply = <&lis3_reg>;
+ Vdd_IO-supply = <&lis3_reg>;
+
+ st,click-single-x;
+ st,click-single-y;
+ st,click-single-z;
+ st,click-thresh-x = <10>;
+ st,click-thresh-y = <10>;
+ st,click-thresh-z = <10>;
+ st,irq1-click;
+ st,irq2-click;
+ st,wakeup-x-lo;
+ st,wakeup-x-hi;
+ st,wakeup-y-lo;
+ st,wakeup-y-hi;
+ st,wakeup-z-lo;
+ st,wakeup-z-hi;
+ st,min-limit-x = <120>;
+ st,min-limit-y = <120>;
+ st,min-limit-z = <140>;
+ st,max-limit-x = <550>;
+ st,max-limit-y = <550>;
+ st,max-limit-z = <750>;
+ };
+
+ tlv320aic3106: tlv320aic3106@1b {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x1b>;
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&vaux2_reg>;
+ IOVDD-supply = <&vaux2_reg>;
+ DRVDD-supply = <&vaux2_reg>;
+ DVDD-supply = <&vbat>;
+ };
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+&epwmss2 {
+ status = "okay";
+
+ ecap2: ecap@48304100 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap2_pins>;
+ };
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1312500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ dual_emac = <1>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii-txid";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii-txid";
+ dual_emac_res_vlan = <2>;
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&sham {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&gpio0 {
+ ti,no-reset-on-init;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&wl12xx_vmmc>;
+ ti,non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+&mcasp1 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp1_pins>;
+ pinctrl-1 = <&mcasp1_pins_sleep>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 0 1 2
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&tscadc {
+ status = "okay";
+ tsc {
+ ti,wires = <4>;
+ ti,x-plate-resistance = <200>;
+ ti,coordinate-readouts = <5>;
+ ti,wire-config = <0x00 0x11 0x22 0x33>;
+ };
+};
+
+&lcdc {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * AM335x ICE V2 board
+ * http://www.ti.com/tool/tmdsice3359
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+ model = "TI AM3359 ICE-V2";
+ compatible = "ti,am3359-icev2", "ti,am33xx";
+
+ chosen {
+ stdout-path = &uart3;
+ tick-timer = &timer2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
+ vtt_fixed: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ leds@0 {
+ compatible = "gpio-leds";
+
+ led@0 {
+ label = "out0";
+ gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@1 {
+ label = "out1";
+ gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@2 {
+ label = "out2";
+ gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "out3";
+ gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@4 {
+ label = "out4";
+ gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@5 {
+ label = "out5";
+ gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@6 {
+ label = "out6";
+ gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@7 {
+ label = "out7";
+ gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ /* Tricolor status LEDs */
+ leds@1 {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds>;
+
+ led@0 {
+ label = "status0:red:cpu0";
+ gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu0";
+ };
+
+ led@1 {
+ label = "status0:green:usr";
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@2 {
+ label = "status0:yellow:usr";
+ gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "status1:red:mmc0";
+ gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ };
+
+ led@4 {
+ label = "status1:green:usr";
+ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@5 {
+ label = "status1:yellow:usr";
+ gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&am33xx_pinmux {
+ user_leds: user_leds {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
+ AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
+ AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
+ AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
+ AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
+ AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
+ >;
+ };
+
+ mmc0_pins_default: mmc0_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
+ AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
+ >;
+ };
+
+ i2c0_pins_default: i2c0_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
+ AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+ >;
+ };
+
+ spi0_pins_default: spi0_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
+ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
+ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
+ AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
+ >;
+ };
+
+ uart3_pins_default: uart3_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
+ AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1, RMII mode */
+ AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_crs.rmii1_crs_dv */
+ AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0)) /* rmii1_refclk.rmii1_refclk */
+ AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd0.rmii1_rxd0 */
+ AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd1.rmii1_rxd1 */
+ AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxerr.rmii1_rxerr */
+ AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd0.rmii1_txd0 */
+ AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd1.rmii1_txd1 */
+ AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txen.rmii1_txen */
+ /* Slave 2, RMII mode */
+ AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wait0.rmii2_crs_dv */
+ AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_col.rmii2_refclk */
+ AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a11.rmii2_rxd0 */
+ AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a10.rmii2_rxd1 */
+ AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wpn.rmii2_rxerr */
+ AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a5.rmii2_txd0 */
+ AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a4.rmii2_txd1 */
+ AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a0.rmii2_txen */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+
+ /* Slave 2 reset value */
+ AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */
+ AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ >;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_default>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: power-controller@2d {
+ reg = <0x2d>;
+ };
+
+ tpic2810: gpio@60 {
+ compatible = "ti,tpic2810";
+ reg = <0x60>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1326000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1144000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+};
+
+&gpio0 {
+ /* Do not idle the GPIO used for holding the VTT regulator */
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+
+ p7 {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FET_SWITCH_CTRL";
+ };
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_default>;
+ status = "okay";
+};
+
+&gpio3 {
+ p4 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PR1_MII_CTRL";
+ };
+
+ p10 {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "MUX_MII_CTRL";
+ };
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <2>;
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ status = "okay";
+ dual_emac;
+};
+
+&phy_sel {
+ rmii-clock-ext;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>; /* PHY datasheet states 1uS min */
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "TI AM437x Industrial Development Kit";
+ compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+
+ v24_0d: fixed-regulator-v24_0d {
+ compatible = "regulator-fixed";
+ regulator-name = "V24_0D";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ v3_3d: fixed-regulator-v3_3d {
+ compatible = "regulator-fixed";
+ regulator-name = "V3_3D";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v24_0d>;
+ };
+
+ vdd_corereg: fixed-regulator-vdd_corereg {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_COREREG";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v24_0d>;
+ };
+
+ vdd_core: fixed-regulator-vdd_core {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_corereg>;
+ };
+
+ v1_8dreg: fixed-regulator-v1_8dreg{
+ compatible = "regulator-fixed";
+ regulator-name = "V1_8DREG";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v24_0d>;
+ };
+
+ v1_8d: fixed-regulator-v1_8d{
+ compatible = "regulator-fixed";
+ regulator-name = "V1_8D";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v1_8dreg>;
+ };
+
+ v1_5dreg: fixed-regulator-v1_5dreg{
+ compatible = "regulator-fixed";
+ regulator-name = "V1_5DREG";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v24_0d>;
+ };
+
+ v1_5d: fixed-regulator-v1_5d{
+ compatible = "regulator-fixed";
+ regulator-name = "V1_5D";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v1_5dreg>;
+ };
+
+ gpio_keys: gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ label = "power-button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ /* fixed 32k external oscillator clock */
+ clk_32k_rtc: clk_32k_rtc {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+};
+
+&am43xx_pinmux {
+ gpio_keys_pins_default: gpio_keys_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
+ >;
+ };
+
+ i2c0_pins_default: i2c0_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ i2c0_pins_sleep: i2c0_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ i2c2_pins_default: i2c2_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
+ AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */
+ >;
+ };
+
+ i2c2_pins_sleep: i2c2_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ mmc1_pins_default: pinmux_mmc1_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+ AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+ AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+ AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+ AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+ AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+ AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+ >;
+ };
+
+ mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ ecap0_pins_default: backlight_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+ AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+ AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+ AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
+ AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
+ AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
+ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
+ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
+ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
+ AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
+ AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ qspi_pins_default: qspi_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
+ AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
+ AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
+ AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
+ AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
+ AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
+ >;
+ };
+
+ qspi_pins_sleep: qspi_pins_sleep{
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c0_pins_default>;
+ pinctrl-1 = <&i2c0_pins_sleep>;
+ clock-frequency = <400000>;
+
+ at24@50 {
+ compatible = "at24,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+
+ tps: tps62362@60 {
+ compatible = "ti,tps62362";
+ reg = <0x60>;
+ regulator-name = "VDD_MPU";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1330000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ vin-supply = <&v3_3d>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_default>;
+ pinctrl-1 = <&i2c2_pins_sleep>;
+ clock-frequency = <100000>;
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&ecap0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap0_pins_default>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&mmc1 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_sleep>;
+ vmmc-supply = <&v3_3d>;
+ bus-width = <4>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&qspi {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_pins_default>;
+ pinctrl-1 = <&qspi_pins_sleep>;
+
+ spi-max-frequency = <48000000>;
+ m25p80@0 {
+ compatible = "mx66l51235l";
+ spi-max-frequency = <48000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * MTD partition table. The ROM checks the first 512KiB for a
+ * valid file to boot(XIP).
+ */
+ partition@0 {
+ label = "QSPI.U_BOOT";
+ reg = <0x00000000 0x000080000>;
+ };
+ partition@1 {
+ label = "QSPI.U_BOOT.backup";
+ reg = <0x00080000 0x00080000>;
+ };
+ partition@2 {
+ label = "QSPI.U-BOOT-SPL_OS";
+ reg = <0x00100000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.U_BOOT_ENV";
+ reg = <0x00110000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.U-BOOT-ENV.backup";
+ reg = <0x00120000 0x00010000>;
+ };
+ partition@5 {
+ label = "QSPI.KERNEL";
+ reg = <0x00130000 0x0800000>;
+ };
+ partition@6 {
+ label = "QSPI.FILESYSTEM";
+ reg = <0x00930000 0x36D0000>;
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii";
+};
+
+&rtc {
+ clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
+ clock-names = "ext-clk", "int-clk";
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&cpu {
+ cpu0-supply = <&tps>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM43x EPOS EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
+
+/ {
+ model = "TI AM43x EPOS EVM";
+ compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
+
+ aliases {
+ display0 = &lcd0;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+
+ vmmcsd_fixed: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
+ lcd0: display {
+ compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
+ label = "lcd";
+
+ panel-timing {
+ clock-frequency = <33000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hfront-porch = <210>;
+ hback-porch = <16>;
+ hsync-len = <30>;
+ vback-porch = <10>;
+ vfront-porch = <22>;
+ vsync-len = <13>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+ };
+
+ matrix_keypad: matrix_keypad@0 {
+ compatible = "gpio-matrix-keypad";
+ debounce-delay-ms = <5>;
+ col-scan-delay-us = <2>;
+
+ row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
+ &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
+ &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
+ &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
+
+ col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
+ &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
+ &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
+ &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
+
+ linux,keymap = <0x00000201 /* P1 */
+ 0x01000204 /* P4 */
+ 0x02000207 /* P7 */
+ 0x0300020a /* NUMERIC_STAR */
+ 0x00010202 /* P2 */
+ 0x01010205 /* P5 */
+ 0x02010208 /* P8 */
+ 0x03010200 /* P0 */
+ 0x00020203 /* P3 */
+ 0x01020206 /* P6 */
+ 0x02020209 /* P9 */
+ 0x0302020b /* NUMERIC_POUND */
+ 0x00030067 /* UP */
+ 0x0103006a /* RIGHT */
+ 0x0203006c /* DOWN */
+ 0x03030069>; /* LEFT */
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 51 53 56 62 75 101 152 255>;
+ default-brightness-level = <8>;
+ };
+
+ sound0: sound@0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM43-EPOS-EVM";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "MIC1LP", "Microphone Jack",
+ "MIC1RP", "Microphone Jack",
+ "MIC1LP", "MICBIAS",
+ "MIC1RP", "MICBIAS",
+ "Headphone Jack", "HPL",
+ "Headphone Jack", "HPR",
+ "Speaker", "SPL",
+ "Speaker", "SPR";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ system-clock-frequency = <12000000>;
+ };
+
+ sound0_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3111>;
+ system-clock-frequency = <12000000>;
+ };
+ };
+};
+
+&am43xx_pinmux {
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
+ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
+ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
+ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
+ AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+ AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
+ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
+ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
+ AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
+ AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
+ AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
+ AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
+ AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
+ AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
+ AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
+ >;
+ };
+
+ ecap0_pins: backlight_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
+ AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
+ >;
+ };
+
+ spi0_pins: pinmux_spi0_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
+ AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
+ AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
+ AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
+ >;
+ };
+
+ spi1_pins: pinmux_spi1_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
+ AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
+ AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
+ AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+ >;
+ };
+
+ qspi1_default: qspi1_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
+ AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
+ AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
+ AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
+ AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
+ AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ pixcir_ts_pins: pixcir_ts_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
+ >;
+ };
+
+ hdq_pins: pinmux_hdq_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
+ >;
+ };
+
+ dss_pins: dss_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
+ AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
+ AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
+ AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
+ AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
+ AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
+ AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
+ AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
+ >;
+ };
+
+ display_mux_pins: display_mux_pins {
+ pinctrl-single,pins = <
+ /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
+ AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+
+ vpfe1_pins_default: vpfe1_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
+ AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
+ AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
+ AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
+ AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
+ AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
+ AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
+ AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
+ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
+ AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
+ AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
+ AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
+ AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
+ >;
+ };
+
+ vpfe1_pins_sleep: vpfe1_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ >;
+ };
+
+ mcasp1_pins: mcasp1_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
+ AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
+ AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
+ AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
+ >;
+ };
+
+ mcasp1_sleep_pins: mcasp1_sleep_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <16>;
+ phy-mode = "rmii";
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rmii";
+};
+
+&phy_sel {
+ rmii-clock-ext;
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <400000>;
+
+ tps65218: tps65218@24 {
+ reg = <0x24>;
+ compatible = "ti,tps65218";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ dcdc1: regulator-dcdc1 {
+ compatible = "ti,tps65218-dcdc1";
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <1144000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc2: regulator-dcdc2 {
+ compatible = "ti,tps65218-dcdc2";
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <1378000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3: regulator-dcdc3 {
+ compatible = "ti,tps65218-dcdc3";
+ regulator-name = "vdcdc3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc4: regulator-dcdc4 {
+ compatible = "ti,tps65218-dcdc4";
+ regulator-name = "vdcdc4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc5: regulator-dcdc5 {
+ compatible = "ti,tps65218-dcdc5";
+ regulator-name = "v1_0bat";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ dcdc6: regulator-dcdc6 {
+ compatible = "ti,tps65218-dcdc6";
+ regulator-name = "v1_8bat";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo1: regulator-ldo1 {
+ compatible = "ti,tps65218-ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+
+ at24@50 {
+ compatible = "at24,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+
+ pixcir_ts@5c {
+ compatible = "pixcir,pixcir_tangoc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pixcir_ts_pins>;
+ reg = <0x5c>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+
+ attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <600>;
+ };
+
+ tlv320aic3111: tlv320aic3111@18 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3111";
+ reg = <0x18>;
+ status = "okay";
+
+ ai31xx-micbias-vg = <MICBIAS_2_0V>;
+
+ /* Regulators */
+ HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+ SPRVDD-supply = <&vbat>; /* vbat */
+ SPLVDD-supply = <&vbat>; /* vbat */
+ AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+ IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
+ DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_mux_pins>;
+ status = "okay";
+
+ p1 {
+ /*
+ * SelLCDorHDMI selects between display and audio paths:
+ * Low: HDMI display with audio via HDMI
+ * High: LCD display with analog audio via aic3111 codec
+ */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "SelLCDorHDMI";
+ };
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_flash_x8>;
+ ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
+ nand@0,0 {
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ ti,nand-ecc-opt = "bch16";
+ ti,elm-id = <&elm>;
+ nand-bus-width = <8>;
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
+ gpmc,cs-wr-off-ns = <40>;
+ gpmc,adv-on-ns = <0>; /* cs-on-ns */
+ gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
+ gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
+ gpmc,we-on-ns = <0>; /* cs-on-ns */
+ gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
+ gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
+ gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
+ gpmc,access-ns = <30>; /* tCEA + 4*/
+ gpmc,rd-cycle-ns = <40>;
+ gpmc,wr-cycle-ns = <40>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wr-access-ns = <40>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+ * which can be independently programmable. For
+ * NAND flash this is equal to size of erase-block */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "NAND.SPL";
+ reg = <0x00000000 0x00040000>;
+ };
+ partition@1 {
+ label = "NAND.SPL.backup1";
+ reg = <0x00040000 0x00040000>;
+ };
+ partition@2 {
+ label = "NAND.SPL.backup2";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition@3 {
+ label = "NAND.SPL.backup3";
+ reg = <0x000C0000 0x00040000>;
+ };
+ partition@4 {
+ label = "NAND.u-boot-spl-os";
+ reg = <0x00100000 0x00080000>;
+ };
+ partition@5 {
+ label = "NAND.u-boot";
+ reg = <0x00180000 0x00100000>;
+ };
+ partition@6 {
+ label = "NAND.u-boot-env";
+ reg = <0x00280000 0x00040000>;
+ };
+ partition@7 {
+ label = "NAND.u-boot-env.backup1";
+ reg = <0x002C0000 0x00040000>;
+ };
+ partition@8 {
+ label = "NAND.kernel";
+ reg = <0x00300000 0x00700000>;
+ };
+ partition@9 {
+ label = "NAND.file-system";
+ reg = <0x00a00000 0x1f600000>;
+ };
+ };
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&tscadc {
+ status = "okay";
+
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&ecap0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap0_pins>;
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb2_phy2 {
+ status = "okay";
+};
+
+&usb2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&qspi {
+ status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi1_default>;
+
+ spi-max-frequency = <48000000>;
+ m25p80@0 {
+ compatible = "mx66l51235l";
+ spi-max-frequency = <48000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+ * The ROM checks the first 512KiB
+ * for a valid file to boot(XIP).
+ */
+ partition@0 {
+ label = "QSPI.U_BOOT";
+ reg = <0x00000000 0x000080000>;
+ };
+ partition@1 {
+ label = "QSPI.U_BOOT.backup";
+ reg = <0x00080000 0x00080000>;
+ };
+ partition@2 {
+ label = "QSPI.U-BOOT-SPL_OS";
+ reg = <0x00100000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.U_BOOT_ENV";
+ reg = <0x00110000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.U-BOOT-ENV.backup";
+ reg = <0x00120000 0x00010000>;
+ };
+ partition@5 {
+ label = "QSPI.KERNEL";
+ reg = <0x00130000 0x0800000>;
+ };
+ partition@6 {
+ label = "QSPI.FILESYSTEM";
+ reg = <0x00930000 0x36D0000>;
+ };
+ };
+};
+
+&hdq {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdq_pins>;
+};
+
+&dss {
+ status = "ok";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_pins>;
+
+ port {
+ dpi_out: endpoint@0 {
+ remote-endpoint = <&lcd_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&vpfe1 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&vpfe1_pins_default>;
+ pinctrl-1 = <&vpfe1_pins_sleep>;
+
+ port {
+ vpfe1_ep: endpoint {
+ /* remote-endpoint = <&sensor>; add once we have it */
+ ti,am437x-vpfe-interface = <0>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+};
+
+&mcasp1 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp1_pins>;
+ pinctrl-1 = <&mcasp1_sleep_pins>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&synctimer_32kclk {
+ assigned-clocks = <&mux_synctimer32k_ck>;
+ assigned-clock-parents = <&clkdiv32k_ick>;
+};
--- /dev/null
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb.dtsi"
+
+/ {
+ compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
+ model = "Hardkernel ODROID-C2";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&uart_AO {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "amlogic,meson-gxbb";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cbus: cbus@c1100000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc1100000 0x0 0x100000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
+
+ uart_A: serial@84c0 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x084c0 0x0 0x14>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@c4301000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xc4301000 0 0x1000>,
+ <0x0 0xc4302000 0 0x2000>,
+ <0x0 0xc4304000 0 0x2000>,
+ <0x0 0xc4306000 0 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ aobus: aobus@c8100000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc8100000 0x0 0x100000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
+
+ uart_AO: serial@4c0 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x004c0 0x0 0x14>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+ };
+
+ apb: apb@d0000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xd0000000 0x0 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
+ };
+ };
+};
status = "okay";
};
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
};
&gmac {
- status = "ok";
+ status = "okay";
};
&hdmi {
--- /dev/null
+/*
+ * clk-synthesizer.h
+ *
+ * Clock synthesizer header
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CLK_SYNTHESIZER_H
+#define __CLK_SYNTHESIZER_H
+
+#include <common.h>
+
+#define CLK_SYNTHESIZER_ID_REG 0x0
+#define CLK_SYNTHESIZER_XCSEL 0x05
+#define CLK_SYNTHESIZER_MUX_REG 0x14
+#define CLK_SYNTHESIZER_PDIV2_REG 0x16
+#define CLK_SYNTHESIZER_PDIV3_REG 0x17
+
+#define CLK_SYNTHESIZER_BYTE_MODE 0x80
+
+/**
+ * struct clk_synth: This structure holds data neeed for configuring
+ * for clock synthesizer.
+ * @id: The id of synthesizer
+ * @capacitor: value of the capacitor attached
+ * @mux: mux settings.
+ * @pdiv2: Div to be applied to second output
+ * @pdiv3: Div to be applied to third output
+ */
+struct clk_synth {
+ u32 id;
+ u32 capacitor;
+ u32 mux;
+ u32 pdiv2;
+ u32 pdiv3;
+};
+
+int setup_clock_synthesizer(struct clk_synth *data);
+
+#endif
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
+/* Micron MT41J128M16JT-125 at 400MHz*/
+#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
+#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
+#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
+#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
+#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
+#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
+#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
+#define MT41J128MJT125_RATIO_400MHz 0x80
+#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
+#define MT41J128MJT125_RD_DQS_400MHz 0x3A
+#define MT41J128MJT125_WR_DQS_400MHz 0x3B
+#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
+#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
+
/* Micron MT41K128M16JT-187E */
#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
--- /dev/null
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GXBB_H__
+#define __GXBB_H__
+
+#define GXBB_PERIPHS_BASE 0xc8834400
+#define GXBB_HIU_BASE 0xc883c000
+#define GXBB_ETH_BASE 0xc9410000
+
+/* Peripherals registers */
+#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
+
+/* GPIO registers 0 to 6 */
+#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
+#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
+#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
+#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
+
+/* Pinmux registers 0 to 12 */
+#define GXBB_PINMUX(n) GXBB_PERIPHS_ADDR(0x2c + (n))
+
+#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
+#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
+
+#define GXBB_ETH_REG_0_PHY_INTF BIT(0)
+#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
+#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
+#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10)
+#define GXBB_ETH_REG_0_CLK_EN BIT(12)
+
+/* HIU registers */
+#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2))
+
+#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
+
+/* Clock gates */
+#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50)
+#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51)
+#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52)
+#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53)
+#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54)
+
+#define GXBB_GCLK_MPEG_1_ETH BIT(3)
+
+#endif /* __GXBB_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MESON_SM_H__
+#define __MESON_SM_H__
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
+
+#endif /* __MESON_SM_H__ */
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
-/* device type */
-#define DEVICE_MASK (0x7 << 8)
+/* boot pin mask */
#define SYSBOOT_MASK 0x1F
-#define TST_DEVICE 0x0
-#define EMU_DEVICE 0x1
-#define HS_DEVICE 0x2
-#define GP_DEVICE 0x3
/* device speed */
#define SKUID_CLK_MASK 0xf
SDIO0_DIV_MASK = 0x3f,
};
+/* CRU_CLKSEL21_CON */
+enum {
+ MAC_DIV_CON_SHIFT = 0xf,
+ MAC_DIV_CON_MASK = 0x1f,
+
+ RMII_EXTCLK_SHIFT = 4,
+ RMII_EXTCLK_MASK = 1,
+ RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+ RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+ EMAC_PLL_SHIFT = 0,
+ EMAC_PLL_MASK = 0x3,
+ EMAC_PLL_SELECT_NEW = 0x0,
+ EMAC_PLL_SELECT_CODEC = 0x1,
+ EMAC_PLL_SELECT_GENERAL = 0x2,
+};
+
/* CRU_CLKSEL25_CON */
enum {
SPI1_PLL_SHIFT = 0xf,
MSCH0_MAINPARTIALPOP_MASK = 1,
};
+/* GRF_SOC_CON1 */
+enum {
+ RMII_MODE_SHIFT = 0xe,
+ RMII_MODE_MASK = 1,
+ RMII_MODE = 1,
+
+ GMAC_CLK_SEL_SHIFT = 0xc,
+ GMAC_CLK_SEL_MASK = 3,
+ GMAC_CLK_SEL_125M = 0,
+ GMAC_CLK_SEL_25M = 0x3,
+ GMAC_CLK_SEL_2_5M = 0x2,
+
+ RMII_CLK_SEL_SHIFT = 0xb,
+ RMII_CLK_SEL_MASK = 1,
+ RMII_CLK_SEL_2_5M = 0,
+ RMII_CLK_SEL_25M,
+
+ GMAC_SPEED_SHIFT = 0xa,
+ GMAC_SPEED_MASK = 1,
+ GMAC_SPEED_10M = 0,
+ GMAC_SPEED_100M,
+
+ GMAC_FLOWCTRL_SHIFT = 0x9,
+ GMAC_FLOWCTRL_MASK = 1,
+
+ GMAC_PHY_INTF_SEL_SHIFT = 0x6,
+ GMAC_PHY_INTF_SEL_MASK = 0x7,
+ GMAC_PHY_INTF_SEL_RGMII = 0x1,
+ GMAC_PHY_INTF_SEL_RMII = 0x4,
+
+ HOST_REMAP_SHIFT = 0x5,
+ HOST_REMAP_MASK = 1
+};
+
/* GRF_SOC_CON2 */
enum {
UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
PWM_PWM = 0,
};
+/* GRF_SOC_CON3 */
+enum {
+ RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
+ RXCLK_DLY_ENA_GMAC_MASK = 1,
+ RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RXCLK_DLY_ENA_GMAC_ENABLE,
+
+ TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
+ TXCLK_DLY_ENA_GMAC_MASK = 1,
+ TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ TXCLK_DLY_ENA_GMAC_ENABLE,
+
+ CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ CLK_RX_DL_CFG_GMAC_MASK = 0x7f,
+
+ CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ CLK_TX_DL_CFG_GMAC_MASK = 0x7f,
+};
+
#endif
#define DRA722_ES1_0 0x07220100
#define DRA722_ES2_0 0x07220200
+/*
+ * silicon device type
+ * Moving to common from cpu.h, since it is shared by various omap devices
+ */
+#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE 0x0
+#define EMU_DEVICE 0x1
+#define HS_DEVICE 0x2
+#define GP_DEVICE 0x3
+
+
/*
* SRAM scratch space entries
*/
#ifndef __ARM_PSCI_H__
#define __ARM_PSCI_H__
-/* PSCI interface */
+/* PSCI 0.1 interface */
#define ARM_PSCI_FN_BASE 0x95c1ba5e
#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
#define ARM_PSCI_RET_INVAL (-2)
#define ARM_PSCI_RET_DENIED (-3)
+/* PSCI 0.2 interface */
+#define ARM_PSCI_0_2_FN_BASE 0x84000000
+#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n))
+
+#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0)
+#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1)
+#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2)
+#define ARM_PSCI_0_2_FN_CPU_ON ARM_PSCI_0_2_FN(3)
+#define ARM_PSCI_0_2_FN_AFFINITY_INFO ARM_PSCI_0_2_FN(4)
+#define ARM_PSCI_0_2_FN_MIGRATE ARM_PSCI_0_2_FN(5)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE ARM_PSCI_0_2_FN(6)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN(7)
+#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
+#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+
#ifndef __ASSEMBLY__
int psci_update_dt(void *fdt);
void psci_board_init(void);
*/
void smc_call(struct pt_regs *args);
+void __noreturn psci_system_reset(bool smc);
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
else
obj-y += interrupts.o
endif
-ifndef CONFIG_RESET
+ifndef CONFIG_SYSRESET
obj-y += reset.o
endif
--- /dev/null
+if ARCH_MESON
+
+config MESON_GXBB
+ bool "Support Meson GXBaby"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ help
+ The Amlogic Meson GXBaby (S905) is an ARM SoC with a
+ quad-core Cortex-A53 CPU and a Mali-450 GPU.
+
+if MESON_GXBB
+
+config TARGET_ODROID_C2
+ bool "ODROID-C2"
+ help
+ ODROID-C2 is a single board computer based on Meson GXBaby
+ with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
+ slot, eMMC, IR receiver and a 40-pin GPIO header.
+
+endif
+
+config SYS_SOC
+ default "meson"
+
+config SYS_MALLOC_F_LEN
+ default 0x1000
+
+source "board/hardkernel/odroid-c2/Kconfig"
+
+endif
--- /dev/null
+#
+# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o sm.o
--- /dev/null
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <linux/err.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <asm/armv8/mmu.h>
+#include <asm/unaligned.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ const fdt64_t *val;
+ int offset;
+ int len;
+
+ offset = fdt_path_offset(gd->fdt_blob, "/memory");
+ if (offset < 0)
+ return -EINVAL;
+
+ val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+ if (len < sizeof(*val) * 2)
+ return -EINVAL;
+
+ /* Use unaligned access since cache is still disabled */
+ gd->ram_size = get_unaligned_be64(&val[1]);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ /* Reserve first 16 MiB of RAM for firmware */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
+ gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset(true);
+}
+
+static struct mm_region gxbb_mem_map[] = {
+ {
+ .base = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .base = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = gxbb_mem_map;
--- /dev/null
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Secure monitor calls.
+ */
+
+#include <common.h>
+#include <asm/arch/gxbb.h>
+#include <linux/kernel.h>
+
+#define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020
+#define FN_GET_SHARE_MEM_OUTPUT_BASE 0x82000021
+#define FN_EFUSE_READ 0x82000030
+#define FN_EFUSE_WRITE 0x82000031
+
+static void *shmem_input;
+static void *shmem_output;
+
+static void meson_init_shmem(void)
+{
+ struct pt_regs regs;
+
+ if (shmem_input && shmem_output)
+ return;
+
+ regs.regs[0] = FN_GET_SHARE_MEM_INPUT_BASE;
+ smc_call(®s);
+ shmem_input = (void *)regs.regs[0];
+
+ regs.regs[0] = FN_GET_SHARE_MEM_OUTPUT_BASE;
+ smc_call(®s);
+ shmem_output = (void *)regs.regs[0];
+
+ debug("Secure Monitor shmem: 0x%p 0x%p\n", shmem_input, shmem_output);
+}
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ meson_init_shmem();
+
+ regs.regs[0] = FN_EFUSE_READ;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+
+ smc_call(®s);
+
+ if (regs.regs[0] == 0)
+ return -1;
+
+ memcpy(buffer, shmem_output, min(size, regs.regs[0]));
+
+ return regs.regs[0];
+}
config DM_GPIO
default y
+config BLK
+ default y
+
source "arch/arm/mach-rockchip/rk3288/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
endif
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3036.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
-int rk3036_reset_request(struct udevice *dev, enum reset_t type)
+int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3036_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
- case RESET_WARM:
+ case SYSRESET_WARM:
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
- case RESET_COLD:
+ case SYSRESET_COLD:
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
default:
return -EINPROGRESS;
}
-static struct reset_ops rk3036_reset = {
- .request = rk3036_reset_request,
+static struct sysreset_ops rk3036_sysreset = {
+ .request = rk3036_sysreset_request,
};
-U_BOOT_DRIVER(reset_rk3036) = {
- .name = "rk3036_reset",
- .id = UCLASS_RESET,
- .ops = &rk3036_reset,
+U_BOOT_DRIVER(sysreset_rk3036) = {
+ .name = "rk3036_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3036_sysreset,
};
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3288.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
-int rk3288_reset_request(struct udevice *dev, enum reset_t type)
+int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3288_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
- case RESET_WARM:
+ case SYSRESET_WARM:
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
- case RESET_COLD:
+ case SYSRESET_COLD:
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
return -EINPROGRESS;
}
-static struct reset_ops rk3288_reset = {
- .request = rk3288_reset_request,
+static struct sysreset_ops rk3288_sysreset = {
+ .request = rk3288_sysreset_request,
};
-U_BOOT_DRIVER(reset_rk3288) = {
- .name = "rk3288_reset",
- .id = UCLASS_RESET,
- .ops = &rk3288_reset,
+U_BOOT_DRIVER(sysreset_rk3288) = {
+ .name = "rk3288_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3288_sysreset,
};
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-static int msm_reset_request(struct udevice *dev, enum reset_t type)
+static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
phys_addr_t addr = dev_get_addr(dev);
if (!addr)
return -EINPROGRESS;
}
-static struct reset_ops msm_reset_ops = {
- .request = msm_reset_request,
+static struct sysreset_ops msm_sysreset_ops = {
+ .request = msm_sysreset_request,
};
-static const struct udevice_id msm_reset_ids[] = {
+static const struct udevice_id msm_sysreset_ids[] = {
{ .compatible = "qcom,pshold" },
{ }
};
U_BOOT_DRIVER(msm_reset) = {
- .name = "msm_reset",
- .id = UCLASS_RESET,
- .of_match = msm_reset_ids,
- .ops = &msm_reset_ops,
+ .name = "msm_sysreset",
+ .id = UCLASS_SYSRESET,
+ .of_match = msm_sysreset_ids,
+ .ops = &msm_sysreset_ops,
};
#ifndef __ASM_U_BOOT_H__
#define __ASM_U_BOOT_H__ 1
-#ifdef CONFIG_SYS_GENERIC_BOARD
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else
-
-typedef struct bd_info {
- unsigned char bi_phy_id[4];
- unsigned long bi_board_number;
- void *bi_boot_params;
- struct {
- unsigned long start;
- unsigned long size;
- } bi_dram[CONFIG_NR_DRAM_BANKS];
- unsigned long bi_flashstart;
- unsigned long bi_flashsize;
- unsigned long bi_flashoffset;
-} bd_t;
-
-#define bi_memstart bi_dram[0].start
-#define bi_memsize bi_dram[0].size
-
-#endif
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_AVR32
#ifndef __U_BOOT_H__
#define __U_BOOT_H__
-/*
- * Board information passed to Linux kernel from U-Boot
- *
- * include/asm-ppc/u-boot.h
- */
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-
-typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_mbar_base; /* base of internal registers */
- unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
- unsigned long bi_intfreq; /* Internal Freq, in MHz */
- unsigned long bi_busfreq; /* Bus Freq, in MHz */
-#ifdef CONFIG_PCI
- unsigned long bi_pcifreq; /* pci Freq in MHz */
-#endif
-#ifdef CONFIG_EXTRA_CLOCK
- unsigned long bi_inpfreq; /* input Freq in MHz */
- unsigned long bi_vcofreq; /* vco Freq in MHz */
- unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
-#endif
-} bd_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
-
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_M68K
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
-#ifdef CONFIG_SYS_GENERIC_BOARD
-
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else /* !CONFIG_SYS_GENERIC_BOARD */
-
-typedef struct bd_info {
- unsigned long bi_arch_number; /* unique id for this board */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
-} bd_t;
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
-
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_MIPS
#include <common.h>
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>
*/
fdt_fixup_ethernet(blob);
}
-#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
+#endif /* CONFIG_OF_BOARD_SETUP */
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += timer.o
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Julius Baxter, julius@opencores.org
- *
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <stdio_dev.h>
-#include <watchdog.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <net.h>
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-#ifdef CONFIG_CMD_NAND
-#include <nand.h> /* cannot even include nand.h if it isnt configured */
-#endif
-
-#include <timestamp.h>
-#include <version.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-
-extern int cache_init(void);
-
-/*
- * Initialization sequence
- */
-static int (* const init_sequence[])(void) = {
- cache_init,
- timer_init, /* initialize timer */
- env_init,
- serial_init,
- console_init_f,
- display_options,
- checkcpu,
- checkboard,
-};
-
-
-/***********************************************************************/
-void board_init(void)
-{
- bd_t *bd;
- int i;
-
- gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR;
-
- memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
-
- gd->bd = (bd_t *)(gd+1); /* At end of global data */
- gd->baudrate = CONFIG_BAUDRATE;
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-
- bd = gd->bd;
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-#ifndef CONFIG_SYS_NO_FLASH
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-#endif
-#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
- bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
- bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
-#endif
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- WATCHDOG_RESET();
- if (init_sequence[i]())
- hang();
- }
-
- WATCHDOG_RESET();
-
- /* The Malloc area is immediately below the monitor copy in RAM */
- mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
-
-#ifndef CONFIG_SYS_NO_FLASH
- WATCHDOG_RESET();
- bd->bi_flashsize = flash_init();
-#endif
-
-#ifdef CONFIG_CMD_NAND
- puts("NAND: ");
- nand_init();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
- puts("MMC: ");
- mmc_initialize(bd);
-#endif
-
- WATCHDOG_RESET();
- env_relocate();
-
- WATCHDOG_RESET();
- stdio_init();
- jumptable_init();
- console_init_r();
-
- WATCHDOG_RESET();
- interrupt_init();
-
-#if defined(CONFIG_BOARD_LATE_INIT)
- board_late_init();
-#endif
-
-#if defined(CONFIG_CMD_NET)
- puts("NET: ");
- eth_initialize();
-#endif
-
- /* main_loop */
- for (;;) {
- WATCHDOG_RESET();
- main_loop();
- }
-}
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
void ft_cpu_setup(void *blob, bd_t *bd)
{
int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0);
#endif
-#if defined(CONFIG_OF_IDE_FIXUP)
+#ifdef CONFIG_OF_IDE_FIXUP
if (!ide_device_present(0)) {
/* NO CF card detected -> delete ata node in DTS */
int nodeoffset = 0;
}
}
-#endif
+#endif /* CONFIG_OF_IDE_FIXUP */
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
#ifdef CONFIG_MPC5xxx_FEC
/* Default initializations for FEC controllers. To override,
* This function is called when the platform is build with SPL
* support from the main (full-blown) U-Boot. And the GD needs
* to get cleared (again) so that the following generic
- * board support code, defined via CONFIG_SYS_GENERIC_BOARD,
- * initializes all variables correctly.
+ * board support code initializes all variables correctly.
*/
mr r3, r2 /* parameter 1: GD pointer */
li r4,0 /* parameter 2: value to fill */
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
void ft_cpu_setup (void *blob, bd_t *bd)
{
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
"clock-frequency", bd->bi_intfreq, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
-#endif /* CONFIG_OF_LIBFDT */
+#endif /* CONFIG_OF_BOARD_SETUP */
/*
* Initializes on-chip ethernet controllers.
mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
PLB4Ax_ACR_RDP_4DEEP);
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
-
-#ifndef CONFIG_SYS_GENERIC_BOARD
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
- /* Clear initial global data */
- memset((void *)gd, 0, sizeof(gd_t));
-#endif
}
/*
#include <asm/cache.h>
#include <asm/ppc4xx.h>
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/4xx_pcie.h>
*/
fdt_pcie_setup(blob);
}
-#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
+#endif /* CONFIG_OF_BOARD_SETUP */
#endif
bl cpu_init_f /* run low-level CPU init code (from Flash) */
-#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
bl board_init_f_alloc_reserve
mr r1, r3
li r0,0
stwu r0, -4(r1)
stwu r0, -4(r1)
-#endif
li r3, 0
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
-#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
bl board_init_f_alloc_reserve
mr r1, r3
bl board_init_f_init_reserve
stwu r0, -4(r1)
stwu r0, -4(r1)
-#endif
li r3, 0
bl board_init_f /* run first part of init code (from Flash) */
/* NOTREACHED - board_init_f() does not return */
#ifndef __U_BOOT_H__
#define __U_BOOT_H__
-/*
- * Board information passed to Linux kernel from U-Boot
- *
- * include/asm-ppc/u-boot.h
- */
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-
-typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
- || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
- unsigned long bi_immr_base; /* base of IMMR register */
-#endif
-#if defined(CONFIG_MPC5xxx)
- unsigned long bi_mbar_base; /* base of internal registers */
-#endif
-#if defined(CONFIG_MPC83xx)
- unsigned long bi_immrbar;
-#endif
- unsigned long bi_bootflags; /* boot / reboot flag (Unused) */
- unsigned long bi_ip_addr; /* IP Address */
- unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */
- unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
- unsigned long bi_intfreq; /* Internal Freq, in MHz */
- unsigned long bi_busfreq; /* Bus Freq, in MHz */
-#if defined(CONFIG_CPM2)
- unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
- unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
- unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
- unsigned long bi_vco; /* VCO Out from PLL, in MHz */
-#endif
-#if defined(CONFIG_MPC512X)
- unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */
-#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
- unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
- unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
-#endif
-#if defined(CONFIG_405) || \
- defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || \
- defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || \
- defined(CONFIG_440)
- unsigned char bi_s_version[4]; /* Version of this structure */
- unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
- unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
- unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
- unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
- unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
-#endif
-
-#ifdef CONFIG_HAS_ETH1
- unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH2
- unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH3
- unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH4
- unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH5
- unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */
-#endif
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
- defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- unsigned int bi_opbfreq; /* OPB clock in Hz */
- int bi_iic_fast[2]; /* Use fast i2c mode */
-#endif
-#if defined(CONFIG_4xx)
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- int bi_phynum[4]; /* Determines phy mapping */
- int bi_phymode[4]; /* Determines phy mode */
-#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
- int bi_phynum[2]; /* Determines phy mapping */
- int bi_phymode[2]; /* Determines phy mode */
-#else
- int bi_phynum[1]; /* Determines phy mapping */
- int bi_phymode[1]; /* Determines phy mode */
-#endif
-#endif /* defined(CONFIG_4xx) */
-} bd_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_PPC
obj-y += reloc.o
obj-$(CONFIG_BAT_RW) += bat_rw.o
-ifndef CONFIG_SPL_BUILD
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y += board.o
-endif
-endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += extable.o
assert(state->ram_buf);
/* No reset yet, so mark it as such. Always allow power reset */
- state->last_reset = RESET_COUNT;
- state->reset_allowed[RESET_POWER] = true;
+ state->last_sysreset = SYSRESET_COUNT;
+ state->sysreset_allowed[SYSRESET_POWER] = true;
/*
* Example of how to use GPIOs:
};
};
+ mbox: mbox {
+ compatible = "sandbox,mbox";
+ #mbox-cells = <1>;
+ };
+
+ mbox-test {
+ compatible = "sandbox,mbox-test";
+ mboxes = <&mbox 100>, <&mbox 1>;
+ mbox-names = "other", "test";
+ };
+
mmc {
compatible = "sandbox,mmc";
};
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_MBOX_H
+#define __SANDBOX_MBOX_H
+
+#include <common.h>
+
+#define SANDBOX_MBOX_PING_XOR 0x12345678
+
+struct udevice;
+
+int sandbox_mbox_test_get(struct udevice *dev);
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg);
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg);
+int sandbox_mbox_test_free(struct udevice *dev);
+
+#endif
#define __SANDBOX_STATE_H
#include <config.h>
-#include <reset.h>
+#include <sysreset.h>
#include <stdbool.h>
#include <linux/stringify.h>
bool write_state; /* Write sandbox state on exit */
bool ignore_missing_state_on_read; /* No error if state missing */
bool show_lcd; /* Show LCD on start-up */
- enum reset_t last_reset; /* Last reset type */
- bool reset_allowed[RESET_COUNT]; /* Allowed reset types */
+ enum sysreset_t last_sysreset; /* Last system reset type */
+ bool sysreset_allowed[SYSRESET_COUNT]; /* Allowed system reset types */
enum state_terminal_raw term_raw; /* Terminal raw/cooked */
bool skip_delays; /* Ignore any time delays (for test) */
bool show_test_output; /* Don't suppress stdout in tests */
{
return 0;
}
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+ /* TODO(sh maintainer): Implement this */
+ while (1);
+}
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
- mov.l ._sh_generic_init, r0
- jsr @r0
+ #TODO(sh maintainer): Fix this up to call the correct code
+ #mov.l ._sh_generic_init, r0
+ #jsr @r0
nop
loop:
._bss_end: .long bss_end
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init: .long sh_generic_init
+#._sh_generic_init: .long sh_generic_init
{
return 0;
}
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+ /* TODO(sh maintainer): Implement this */
+ while (1);
+}
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
- mov.l ._sh_generic_init, r0
- jsr @r0
+ #TODO(sh maintainer): Fix this up to call the correct code
+ #mov.l ._sh_generic_init, r0
+ #jsr @r0
nop
loop:
._bss_end: .long bss_end
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init: .long sh_generic_init
+#._sh_generic_init: .long sh_generic_init
#endif
return 0;
}
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+ /* TODO(sh maintainer): Implement this */
+ while (1);
+}
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
- mov.l ._sh_generic_init, r0
- jsr @r0
+ #TODO(sh maintainer): Fix this up to call the correct code
+ #mov.l ._sh_generic_init, r0
+ #jsr @r0
nop
loop:
._bss_end: .long bss_end
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init: .long sh_generic_init
+#._sh_generic_init: .long sh_generic_init
KEEP(*(SORT(.u_boot_list*)));
}
+ PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
#ifndef __ASM_SH_U_BOOT_H_
#define __ASM_SH_U_BOOT_H_
-typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_boot_params; /* where this board expects params */
-} bd_t;
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_SH
#
-obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
ifeq ($(CONFIG_CPU_SH2),y)
obj-y += time_sh2.o
+++ /dev/null
-/*
- * Copyright (C) 2007, 2008, 2010
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <watchdog.h>
-#include <net.h>
-#include <mmc.h>
-#include <environment.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int cpu_init(void);
-extern int board_init(void);
-extern int dram_init(void);
-extern int timer_init(void);
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
-#ifndef CONFIG_SYS_NO_FLASH
-static int sh_flash_init(void)
-{
- gd->bd->bi_flashsize = flash_init();
-
- if (gd->bd->bi_flashsize >= (1024 * 1024))
- printf("Flash: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
- else
- printf("Flash: %ldKB\n", gd->bd->bi_flashsize / 1024);
-
- return 0;
-}
-#endif /* CONFIG_SYS_NO_FLASH */
-
-#if defined(CONFIG_CMD_NAND)
-# include <nand.h>
-# define INIT_FUNC_NAND_INIT nand_init,
-#else
-# define INIT_FUNC_NAND_INIT
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_WATCHDOG)
-extern int watchdog_init(void);
-extern int watchdog_disable(void);
-# undef INIT_FUNC_WATCHDOG_INIT
-# define INIT_FUNC_WATCHDOG_INIT watchdog_init,
-# define WATCHDOG_DISABLE watchdog_disable
-#else
-# define INIT_FUNC_WATCHDOG_INIT
-# define WATCHDOG_DISABLE
-#endif /* CONFIG_WATCHDOG */
-
-#if defined(CONFIG_CMD_IDE)
-# include <ide.h>
-# define INIT_FUNC_IDE_INIT ide_init,
-#else
-# define INIT_FUNC_IDE_INIT
-#endif /* CONFIG_CMD_IDE */
-
-#if defined(CONFIG_PCI)
-#include <pci.h>
-static int sh_pci_init(void)
-{
- pci_init();
- return 0;
-}
-# define INIT_FUNC_PCI_INIT sh_pci_init,
-#else
-# define INIT_FUNC_PCI_INIT
-#endif /* CONFIG_PCI */
-
-static int sh_mem_env_init(void)
-{
- mem_malloc_init(CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE -
- CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16);
- env_relocate();
- jumptable_init();
- return 0;
-}
-
-#if defined(CONFIG_CMD_MMC)
-static int sh_mmc_init(void)
-{
- puts("MMC: ");
- mmc_initialize(gd->bd);
- return 0;
-}
-#endif
-
-typedef int (init_fnc_t) (void);
-
-init_fnc_t *init_sequence[] =
-{
- cpu_init, /* basic cpu dependent setup */
- board_init, /* basic board dependent setup */
- interrupt_init, /* set up exceptions */
- env_init, /* event init */
- serial_init, /* SCIF init */
- INIT_FUNC_WATCHDOG_INIT /* watchdog init */
- console_init_f,
- display_options,
- checkcpu,
- checkboard, /* Check support board */
- dram_init, /* SDRAM init */
- timer_init, /* SuperH Timer (TCNT0 only) init */
- sh_mem_env_init,
-#ifndef CONFIG_SYS_NO_FLASH
- sh_flash_init, /* Flash memory init*/
-#endif
- INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */
- INIT_FUNC_PCI_INIT /* PCI init */
- stdio_init,
- console_init_r,
- interrupt_init,
-#ifdef CONFIG_BOARD_LATE_INIT
- board_late_init,
-#endif
-#if defined(CONFIG_CMD_MMC)
- sh_mmc_init,
-#endif
- NULL /* Terminate this list */
-};
-
-void sh_generic_init(void)
-{
- bd_t *bd;
- init_fnc_t **init_fnc_ptr;
-
- memset(gd, 0, GENERATED_GBL_DATA_SIZE);
-
- gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
-
- gd->bd = (bd_t *)(gd + 1); /* At end of global data */
- gd->baudrate = CONFIG_BAUDRATE;
-
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-
- bd = gd->bd;
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-#ifndef CONFIG_SYS_NO_FLASH
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-#endif
-#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
- bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
- bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
-#endif
-
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- WATCHDOG_RESET();
- if ((*init_fnc_ptr) () != 0)
- hang();
- }
-
-#ifdef CONFIG_WATCHDOG
- /* disable watchdog if environment is set */
- {
- char *s = getenv("watchdog");
- if (s != NULL)
- if (strncmp(s, "off", 3) == 0)
- WATCHDOG_DISABLE();
- }
-#endif /* CONFIG_WATCHDOG*/
-
-
-#ifdef CONFIG_BITBANGMII
- bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
- puts("Net: ");
- eth_initialize();
-#endif /* CONFIG_CMD_NET */
-
- while (1) {
- WATCHDOG_RESET();
- main_loop();
- }
-}
+++ /dev/null
-(cpu/mpc7xxx/start.S)
-
-start:
- b boot_cold
-
-start_warm:
- b boot_warm
-
-
-boot_cold:
-boot_warm:
- clear bats
- init l2 (if enabled)
- init altivec (if enabled)
- invalidate l2 (if enabled)
- setup bats (from defines in config_EVB)
- enable_addr_trans: (if MMU enabled)
- enable MSR_IR and MSR_DR
- jump to in_flash
-
-in_flash:
- enable l1 dcache
- gal_low_init: (board/evb64260/sdram_init.S)
- config SDRAM (CFG, TIMING, DECODE)
- init scratch regs (810 + 814)
-
- detect DIMM0 (bank 0 only)
- config SDRAM_PARA0 to 256/512Mbit
- bl sdram_op_mode
- detect bank0 width
- write scratch reg 810
- config SDRAM_PARA0 with results
- config SDRAM_PARA1 with results
-
- detect DIMM1 (bank 2 only)
- config SDRAM_PARA2 to 256/512Mbit
- detect bank2 width
- write scratch reg 814
- config SDRAM_PARA2 with results
- config SDRAM_PARA3 with results
-
- setup device bus timings/width
- setup boot device timings/width
-
- setup CPU_CONF (0x0)
- setup cpu master control register 0x160
- setup PCI0 TIMEOUT
- setup PCI1 TIMEOUT
- setup PCI0 BAR
- setup PCI1 BAR
-
- setup MPP control 0-3
- setup GPP level control
- setup Serial ports multiplex
-
- setup stack pointer (r1)
- setup GOT
- call cpu_init_f
- debug leds
- board_init_f: (common/board.c)
- board_early_init_f:
- remap gt regs?
- map PCI mem/io
- map device space
- clear out interrupts
- init_timebase
- env_init
- serial_init
- console_init_f
- display_options
- initdram: (board/evb64260/evb64260.c)
- detect memory
- for each bank:
- dram_size()
- setup PCI slave memory mappings
- setup SCS
- setup monitor
- alloc board info struct
- init bd struct
- relocate_code: (cpu/mpc7xxx/start.S)
- copy,got,clearbss
- board_init_r(bd, dest_addr) (common/board.c)
- setup bd function pointers
- trap_init
- flash_init: (board/evb64260/flash.c)
- setup bd flash info
- cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
- nothing
- mem_malloc_init
- malloc_bin_reloc
- spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
- env_relocated
- misc_init_r(bd): (board/evb64260/evb64260.c)
- mpsc_init2
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- */
-
-#ifndef __I2C_H__
-#define __I2C_H__
-
-/* function declarations */
-uchar i2c_read(uchar, unsigned int, int, uchar*, int);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- */
-
-/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
-
-/*
- * acceptable chips types are:
- *
- * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
- */
-
-/* register addresses, valid only following an CHIP_CMD_RD_ID command */
-#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
-#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
-#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
-#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
-
-/* Commands */
-#define CHIP_CMD_RST 0xFF /* reset flash */
-#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
-#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
-#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
-#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
-#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
-#define CHIP_CMD_PROG 0x40 /* program word command */
-#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
-#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
-#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
-#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
-#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
-#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
-#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
-
-/* status register bits */
-#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
-#define CHIP_STAT_VPPS 0x08 /* VPP Status */
-#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
-#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
-#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
-#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
-
-#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
- CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
-
-/* ID and Lock Configuration */
-#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
-#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID
-
-/* dimensions */
-#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
-#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
-#define CHIP_NBLOCKS 128
-#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
-#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
-
-/********************** DEFINES for Hymod Flash ******************************/
-
-/*
- * The hymod board has 2 x 28F320J5 chips running in
- * 16 bit mode, for a 32 bit wide bank.
- */
-
-typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
-typedef volatile bank_word_t *bank_addr_t;
-typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
-
-#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
-#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
-
-#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
-#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
-#define BANK_NBLOCKS CHIP_NBLOCKS
-#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
-#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
-
-#define MAX_BANKS 1 /* only one bank possible */
-
-/* align bank addresses and sizes to bank word boundaries */
-#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_WIDTH - 1)))
-#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
- (bank_size_t)(s) + (BANK_WIDTH - 1)))
-
-/* align bank addresses and sizes to bank block boundaries */
-#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_BLKSZ - 1)))
-#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
- (bank_size_t)(s) + (BANK_BLKSZ - 1)))
-
-/* align bank addresses and sizes to bank boundaries */
-#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_SIZE - 1)))
-#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
- (bank_size_t)(s) + (BANK_SIZE - 1)))
-
-/* add an offset to a bank address */
-#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
- (bank_size_t)(o))
-
-/* get base address of bank b, given flash base address a */
-#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- (bank_size_t)(b) * BANK_SIZE)
-
-/* adjust a bank address to start of next word, block or bank */
-#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
- BANK_WIDTH)
-#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
- BANK_BLKSZ)
-#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- BANK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- ((bank_size_t)(r) << BANK_WSHIFT))
-
-/* make a bank address for each chip register address */
-
-#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
-#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
-#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
-#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the bank_word_t type, and take into account the
- * chip width and bank layout
- */
-
-#define BANK_FILL_WORD(o) ((bank_word_t)(o))
-
-/* make a bank word value for each chip cmd/stat/rd value */
-
-/* Commands */
-#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
-#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
-#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
-#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
-#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
-#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
-#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
-#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
-#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
-#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
-#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
-#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
-#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
-#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
-#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
-#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
-#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
-
-#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
-#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
-#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)
+++ /dev/null
-/*
- * Copyright - Galileo technology.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- *
- * written or collected and sometimes rewritten by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- */
-
-
-#include <common.h>
-#include "../include/core.h"
-#include "../include/memory.h"
-
-/*******************************************************************************
-* memoryGetBankBaseAddress - Returns the base address of a memory bank.
-* DESCRIPTION:
-* This function returns the base address of one of the SDRAM's memory
-* banks. There are 4 memory banks and each one represents one DIMM side.
-* INPUT:
-* MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit Memory bank base address.
-*******************************************************************************/
-static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
-{
- switch (bank) {
- case BANK0:
- return SCS_0_LOW_DECODE_ADDRESS;
- case BANK1:
- return SCS_1_LOW_DECODE_ADDRESS;
- case BANK2:
- return SCS_2_LOW_DECODE_ADDRESS;
- case BANK3:
- return SCS_3_LOW_DECODE_ADDRESS;
-
- }
- return SCS_0_LOW_DECODE_ADDRESS; /* default value */
-}
-
-unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
-{
- unsigned int base;
- unsigned int regOffset = memoryGetBankRegOffset (bank);
-
- GT_REG_READ (regOffset, &base);
- base = base << 16; /* MV6436x */
- return base;
-}
-
-/*******************************************************************************
-* memoryGetDeviceBaseAddress - Returns the base address of a device.
-* DESCRIPTION:
-* This function returns the base address of a device on the system. There
-* are 5 possible devices (0 - 4 and one boot device) as defined in
-* gtMemory.h. Each of the device parameters is maped to one of the CS
-* (Devices chip selects) base address register.
-* INPUT:
-* device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit Device base address.
-*
-*******************************************************************************/
-static unsigned int memoryGetDeviceRegOffset (DEVICE device)
-{
- switch (device) {
- case DEVICE0:
- return CS_0_LOW_DECODE_ADDRESS;
- case DEVICE1:
- return CS_1_LOW_DECODE_ADDRESS;
- case DEVICE2:
- return CS_2_LOW_DECODE_ADDRESS;
- case DEVICE3:
- return CS_3_LOW_DECODE_ADDRESS;
- case BOOT_DEVICE:
- return BOOTCS_LOW_DECODE_ADDRESS;
- }
- return CS_0_LOW_DECODE_ADDRESS; /* default value */
-}
-
-unsigned int memoryGetDeviceBaseAddress (DEVICE device)
-{
- unsigned int regBase;
- unsigned int regOffset = memoryGetDeviceRegOffset (device);
-
- GT_REG_READ (regOffset, ®Base);
-
- regBase = regBase << 16; /* MV6436x */
- return regBase;
-}
-
-/*******************************************************************************
-* MemoryGetPciBaseAddr - Returns the base address of a PCI window.
-* DESCRIPTION:
-* This function returns the base address of a PCI window. There are 5
-* possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
-* interface as defined in gtMemory.h, used by the CPU's address decoding
-* mechanism.
-* New in MV6436x
-* INPUT:
-* pciWindow - Selects one of the PCI windows as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit PCI window base address.
-*******************************************************************************/
-unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
-{
- unsigned int baseAddrReg, base;
-
- switch (pciWindow) {
- case PCI_0_IO:
- baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
- break;
- case PCI_0_MEM0:
- baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
- break;
- case PCI_0_MEM1:
- baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
- break;
- case PCI_0_MEM2:
- baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
- break;
- case PCI_0_MEM3:
- baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
- break;
- case PCI_1_MEM0:
- baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
- break;
- case PCI_1_MEM1:
- baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
- break;
- case PCI_1_MEM2:
- baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
- break;
- case PCI_1_MEM3:
- baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- return 0xffffffff;
- }
- GT_REG_READ (baseAddrReg, &base);
- return (base << 16);
-}
-
-/*******************************************************************************
-* memoryGetBankSize - Returns the size of a memory bank.
-* DESCRIPTION:
-* This function returns the size of memory bank as described in
-* 'gtMemoryGetBankBaseAddress' function.
-* INPUT:
-* bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit size memory bank size or 0 for a closed or non populated bank.
-*
-*******************************************************************************/
-unsigned int memoryGetBankSize (MEMORY_BANK bank)
-{
- unsigned int sizeReg, size;
- MEMORY_WINDOW window;
-
- switch (bank) {
- case BANK0:
- sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /* CS_0_SIZE; */
- window = CS_0_WINDOW;
- break;
- case BANK1:
- sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /* CS_1_SIZE; */
- window = CS_1_WINDOW;
- break;
- case BANK2:
- sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /* CS_2_SIZE; */
- window = CS_2_WINDOW;
- break;
- case BANK3:
- sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /* CS_3_SIZE; */
- window = CS_3_WINDOW;
- break;
- default:
- return 0;
- break;
- }
- /* If the window is closed, a size of 0 is returned */
- if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
- return 0;
- GT_REG_READ (sizeReg, &size);
- size = ((size << 16) | 0xffff) + 1;
- return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceSize - Returns the size of a device memory space.
-* DESCRIPTION:
-* This function returns the memory space size of a given device.
-* INPUT:
-* device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit size of a device memory space.
-*******************************************************************************/
-unsigned int memoryGetDeviceSize (DEVICE device)
-{
- unsigned int sizeReg, size;
- MEMORY_WINDOW window;
-
- switch (device) {
- case DEVICE0:
- sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
- window = DEVCS_0_WINDOW;
- break;
- case DEVICE1:
- sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
- window = DEVCS_1_WINDOW;
- break;
- case DEVICE2:
- sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
- window = DEVCS_2_WINDOW;
- break;
- case DEVICE3:
- sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
- window = DEVCS_3_WINDOW;
- break;
- case BOOT_DEVICE:
- sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
- window = BOOT_CS_WINDOW;
- break;
- default:
- return 0;
- break;
- }
- /* If the window is closed, a size of 0 is returned */
- if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
- return 0;
- GT_REG_READ (sizeReg, &size);
- size = ((size << 16) | 0xffff) + 1;
- return size;
-}
-
-/*******************************************************************************
-* MemoryGetPciWindowSize - Returns the size of a PCI memory window.
-* DESCRIPTION:
-* This function returns the size of a PCI window.
-* INPUT:
-* pciWindow - Selects one of the PCI memory windows as defined in
-* Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit size of a PCI memory window.
-*******************************************************************************/
-unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
-{
- unsigned int sizeReg, size;
-
- switch (pciWindow) {
- case PCI_0_IO:
- sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
- break;
- case PCI_0_MEM0:
- sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
- break;
- case PCI_0_MEM1:
- sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
- break;
- case PCI_0_MEM2:
- sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
- break;
- case PCI_0_MEM3:
- sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
- break;
- case PCI_1_MEM0:
- sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
- break;
- case PCI_1_MEM1:
- sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
- break;
- case PCI_1_MEM2:
- sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
- break;
- case PCI_1_MEM3:
- sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- return 0x0;
- }
- /* If the memory window is disabled, retrun size = 0 */
- if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
- == MEM_WINDOW_DISABLED)
- return 0;
- GT_REG_READ (sizeReg, &size);
- size = ((size << 16) | 0xffff) + 1;
- return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceWidth - Returns the width of a given device.
-* DESCRIPTION:
-* The MV's device interface supports up to 32 Bit wide devices. A device
-* can have a 1, 2, 4 or 8 Bytes data width. This function returns the
-* width of a device as defined by the user or the operating system.
-* INPUT:
-* device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
-*******************************************************************************/
-unsigned int memoryGetDeviceWidth (DEVICE device)
-{
- unsigned int width;
- unsigned int regValue;
-
- GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, ®Value);
- width = (regValue & (BIT20 | BIT21)) >> 20;
- return (BIT0 << width);
-}
-
-/*******************************************************************************
-* memoryMapBank - Set new base address and size for one of the memory
-* banks.
-*
-* DESCRIPTION:
-* The CPU interface address decoding map consists of 21 address windows
-* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-* space. Each address window is defined by two registers - base and size.
-* The CPU address is compared with the values in the various CPU windows
-* until a match is found and the address is than targeted to that window.
-* This function sets new base and size for one the memory banks
-* (CS0 - CS3). It is the programmer`s responsibility to make sure that
-* there are no conflicts with other memory spaces. When two memory spaces
-* overlap, the MV's behavior is not defined .If a bank needs to be closed,
-* set the 'bankLength' parameter size to 0x0.
-*
-* INPUT:
-* bank - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
-* bankBase - The memory bank base address.
-* bankLength - The memory bank size. This function will decrement the
-* 'bankLength' parameter by one and then check if the size is
-* valid. A valid size must be programed from LSB to MSB as
-* sequence of '1's followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-* OUTPUT:
-* None.
-* RETURN:
-* false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
- unsigned int bankLength)
-{
- unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/* PCI_INTERNAL_BAR pciBAR; */
-
- switch (bank) {
- case BANK0:
- baseReg = SCS_0_LOW_DECODE_ADDRESS; /*CS_0_BASE_ADDR; */
- sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /*CS_0_SIZE; */
-/* pciBAR = PCI_CS0_BAR; */
- break;
- case BANK1:
- baseReg = SCS_1_LOW_DECODE_ADDRESS; /*CS_1_BASE_ADDR; */
- sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /*CS_1_SIZE; */
- /* pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
- break;
- case BANK2:
- baseReg = SCS_2_LOW_DECODE_ADDRESS; /*CS_2_BASE_ADDR; */
- sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /*CS_2_SIZE; */
-/* pciBAR = PCI_CS2_BAR;*/
- break;
- case BANK3:
- baseReg = SCS_3_LOW_DECODE_ADDRESS; /*CS_3_BASE_ADDR; */
- sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /*CS_3_SIZE; */
-/* pciBAR = PCI_CS3_BAR; */
- break;
- default:
- return false;
- }
- /* If the size is 0, the window will be disabled */
- if (bankLength == 0) {
- MemoryDisableWindow (CS_0_WINDOW << bank);
- /* Disable the BAR from the PCI slave side */
-/* gtPci0DisableInternalBAR(pciBAR); */
-/* gtPci1DisableInternalBAR(pciBAR); */
- return true;
- }
- /* The base address must be aligned to the size */
- if ((bankBase % bankLength) != 0) {
- return false;
- }
- if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
- newBase = bankBase >> 16;
- newSize = bankLength >> 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = newSize - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
-#ifdef DEBUG
- {
- unsigned int oldBase, oldSize;
-
- GT_REG_READ (baseReg, &oldBase);
- GT_REG_READ (sizeReg + 8, &oldSize);
-
- printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
- bank, oldBase, oldSize, newBase, newSize);
- }
-#endif
- /* writing the new values */
- GT_REG_WRITE (baseReg, newBase);
- GT_REG_WRITE (sizeReg, newSize - 1);
- /* Enable back the window */
- MemoryEnableWindow (CS_0_WINDOW << bank);
- /* Enable the BAR from the PCI slave side */
-/* gtPci0EnableInternalBAR(pciBAR); */
-/* gtPci1EnableInternalBAR(pciBAR); */
- return true;
- }
- return false;
-}
-
-
-/*******************************************************************************
-* memoryMapDeviceSpace - Set new base address and size for one of the device
-* windows.
-*
-* DESCRIPTION:
-* The CPU interface address decoding map consists of 21 address windows
-* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-* space. Each address window is defined by two registers - base and size.
-* The CPU address is compared with the values in the various CPU windows
-* until a match is found and the address is than targeted to that window.
-* This function sets new base and size for one the device windows
-* (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
-* that there are no conflicts with other memory spaces. When two memory
-* spaces overlap, the MV's behavior is not defined .If a device window
-* needs to be closed, set the 'deviceLength' parameter size to 0x0.
-*
-* INPUT:
-* device - One of the device windows (DEV_CS0-DEV_CS3) as
-* defined in gtMemory.h.
-* deviceBase - The device window base address.
-* deviceLength - The device window size. This function will decrement
-* the 'deviceLength' parameter by one and then
-* check if the size is valid. A valid size must be
-* programed from LSB to MSB as sequence of '1's
-* followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
- unsigned int deviceLength)
-{
- unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/* PCI_INTERNAL_BAR pciBAR;*/
-
- switch (device) {
- case DEVICE0:
- baseReg = CS_0_LOW_DECODE_ADDRESS; /*DEV_CS0_BASE_ADDR; */
- sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
-/* pciBAR = PCI_DEV_CS0_BAR; */
- break;
- case DEVICE1:
- baseReg = CS_1_LOW_DECODE_ADDRESS; /*DEV_CS1_BASE_ADDR; */
- sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
-/* pciBAR = PCI_DEV_CS1_BAR; */
- break;
- case DEVICE2:
- baseReg = CS_2_LOW_DECODE_ADDRESS; /*DEV_CS2_BASE_ADDR; */
- sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
-/* pciBAR = PCI_DEV_CS2_BAR; */
- break;
- case DEVICE3:
- baseReg = CS_3_LOW_DECODE_ADDRESS; /*DEV_CS3_BASE_ADDR; */
- sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
-/* pciBAR = PCI_DEV_CS3_BAR; */
- break;
- case BOOT_DEVICE:
- baseReg = BOOTCS_LOW_DECODE_ADDRESS; /*BOOTCS_BASE_ADDR; */
- sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
-/* pciBAR = PCI_BOOT_CS_BAR; */
- break;
- default:
- return false;
- }
- if (deviceLength == 0) {
- MemoryDisableWindow (DEVCS_0_WINDOW << device);
- /* Disable the BAR from the PCI slave side */
-/* gtPci0DisableInternalBAR(pciBAR); */
-/* gtPci1DisableInternalBAR(pciBAR); */
- return true;
- }
- /* The base address must be aligned to the size */
- if ((deviceBase % deviceLength) != 0) {
- return false;
- }
- if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
- newBase = deviceBase >> 16;
- newSize = deviceLength >> 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = newSize - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
- /* writing the new values */
- GT_REG_WRITE (baseReg, newBase);
- GT_REG_WRITE (sizeReg, newSize - 1);
- MemoryEnableWindow (DEVCS_0_WINDOW << device);
- /* Enable the BAR from the PCI slave side */
-/* gtPci0EnableInternalBAR(pciBAR); */
-/* gtPci1EnableInternalBAR(pciBAR); */
- return true;
- }
- return false;
-}
-
-/*******************************************************************************
-* MemorySetPciWindow - Set new base address and size for one of the PCI
-* windows.
-*
-* DESCRIPTION:
-* The CPU interface address decoding map consists of 21 address windows
-* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-* space. Each address window is defined by two registers - base and size.
-* The CPU address is compared with the values in the various CPU windows
-* until a match is found and the address is than targeted to that window.
-* This function sets new base and size for one the PCI windows
-* (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
-* that there are no conflicts with other memory spaces. When two memory
-* spaces overlap, the MV's behavior is not defined. If a PCI window
-* needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
-*
-* INPUT:
-* pciWindow - One of the PCI windows as defined in gtMemory.h.
-* pciWindowBase - The PCI window base address.
-* pciWindowSize - The PCI window size. This function will decrement the
-* 'pciWindowSize' parameter by one and then check if the
-* size is valid. A valid size must be programed from LSB
-* to MSB as sequence of '1's followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
- unsigned int pciWindowSize)
-{
- unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
-
- switch (pciWindow) {
- case PCI_0_IO:
- baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
- sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
- break;
- case PCI_0_MEM0:
- baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
- sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
- break;
- case PCI_0_MEM1:
- baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
- sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
- break;
- case PCI_0_MEM2:
- baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
- sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
- break;
- case PCI_0_MEM3:
- baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
- sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
- sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
- break;
- case PCI_1_MEM0:
- baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
- sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
- break;
- case PCI_1_MEM1:
- baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
- sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
- break;
- case PCI_1_MEM2:
- baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
- sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
- break;
- case PCI_1_MEM3:
- baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
- sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- return false;
- }
- if (pciWindowSize == 0) {
- MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
- return true;
- }
- /* The base address must be aligned to the size */
- if ((pciWindowBase % pciWindowSize) != 0) {
- return false;
- }
- if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
- pciWindowBase >>= 16;
- pciWindowSize >>= 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = pciWindowSize - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
- GT_REG_WRITE (sizeReg, pciWindowSize - 1);
- GT_REG_READ (baseAddrReg, ¤tLow);
- pciWindowBase =
- (pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
- GT_REG_WRITE (baseAddrReg, pciWindowBase);
- MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
- return true;
- }
- return false;
-}
-
-/*******************************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internal
-* registers memory space.
-*
-* DESCRIPTION:
-* This function set new base address for the internal registers memory
-* space (the size is fixed and cannot be modified). The function does not
-* handle overlapping with other memory spaces, it is the programer's
-* responsibility to ensure that overlapping does not occur.
-* When two memory spaces overlap, the MV's behavior is not defined.
-*
-* INPUT:
-* internalRegBase - new base address for the internal registers memory
-* space.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* true on success, false on failure
-*
-*******************************************************************************/
-/********************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internals
-* registers.
-*
-* INPUTS: unsigned int internalRegBase - The new base address.
-* RETURNS: true on success, false on failure
-*********************************************************************/
-bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
-{
- unsigned int currentValue;
- unsigned int internalValue = internalRegBase;
-
- internalRegBase = (internalRegBase >> 16);
- GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue);
- internalRegBase = (currentValue & 0xff000000) | internalRegBase;
- GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
- /* initializing also the global variable 'internalRegBaseAddr' */
-/* gtInternalRegBaseAddr = internalValue; */
- INTERNAL_REG_BASE_ADDR = internalValue;
- return true;
-}
-
-/*******************************************************************************
-* memoryGetInternalRegistersSpace - Returns the internal registers Base
-* address.
-*
-* DESCRIPTION:
-* This function returns the base address of the internal registers
-* memory space .
-*
-* INPUT:
-* None.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* 32 bit base address of the internal registers memory space.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalRegistersSpace (void)
-{
- unsigned int currentValue = 0;
-
- GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue);
- return ((currentValue & 0x000fffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
-*
-* DESCRIPTION:
-* The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-* funcnion return the SRAM's base address.
-* INPUT:
-* None.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit SRAM's base address.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalSramBaseAddr (void)
-{
- return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
-*
-* DESCRIPTION:
-* The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-* function sets a new base address to the SRAM .
-* INPUT:
-* sramBaseAddress - The SRAM's base address.
-* OUTPUT:
-* None.
-* RETURN:
-* None.
-*
-*******************************************************************************/
-void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
-{
- GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
-}
-
-/*******************************************************************************
-* memorySetProtectRegion - Set protection mode for one of the 8 regions.
-*
-* DESCRIPTION:
-* The CPU interface supports configurable access protection. This includes
-* up to eight address ranges defined to a different protection type :
-* whether the address range is cacheable or not, whether it is writable or
-* not , and whether it is accessible or not. A Low and High registers
-* define each window while the minimum address range of each window is
-* 1Mbyte. An address driven by the CPU, in addition to the address
-* decoding and remapping process, is compared against the eight Access
-* Protection Low/High registers , if an address matches one of the windows
-* , the MV device checks the transaction type against the protection bits
-* defined in CPU Access Protection register, to determine if the access is
-* allowed. This function set a protection mode to one of the 8 possible
-* regions.
-* NOTE:
-* The CPU address windows are restricted to a size of 2 power n and the
-* start address must be aligned to the window size. For example, if using
-* a 16 MB window, the start address bits [23:0] must be 0.The MV's
-* internal registers space is not protected, even if the access protection
-* windows contain this space.
-*
-* INPUT:
-* region - selects which region to be configured. The values defined in
-* gtMemory.h:
-*
-* - MEM_REGION0
-* - MEM_REGION1
-* - etc.
-*
-* memAccess - Allows or forbids access (read or write ) to the region. The
-* values defined in gtMemory.h:
-*
-* - MEM_ACCESS_ALLOWED
-* - MEM_ACCESS_FORBIDEN
-*
-* memWrite - CPU write protection to the region. The values defined in
-* gtMemory.h:
-*
-* - MEM_WRITE_ALLOWED
-* - MEM_WRITE_FORBIDEN
-*
-* cacheProtection - Defines whether caching the region is allowed or not.
-* The values defined in gtMemory.h:
-*
-* - MEM_CACHE_ALLOWED
-* - MEM_CACHE_FORBIDEN
-*
-* baseAddress - the region's base Address.
-* regionSize - The region's size. This function will decrement the
-* 'regionSize' parameter by one and then check if the size
-* is valid. A valid size must be programed from LSB to MSB
-* as sequence of '1's followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
- MEMORY_ACCESS memAccess,
- MEMORY_ACCESS_WRITE memWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress, unsigned int size)
-{
- unsigned int dataForReg, temp, rShift;
-
- if (size == 0) {
- GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
- 0x0);
- return true;
- }
- /* The base address must be aligned to the size. */
- if (baseAddress % size != 0) {
- return false;
- }
- if (size >= MINIMUM_ACCESS_WIN_SIZE) {
- baseAddress = ((baseAddress >> 16) & 0xfffff);
- dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
- ((memWrite << 21) & BIT21) | ((cacheProtection << 22)
- & BIT22) | BIT31;
- GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
- dataForReg);
- size >>= 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = size - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
- GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
- size - 1);
- return true;
- }
- return false;
-}
-
-/*******************************************************************************
-* gtMemoryDisableProtectRegion - Disable a protected window.
-*
-* DESCRIPTION:
-* This function disable a protected window set by
-* 'gtMemorySetProtectRegion' function.
-*
-* INPUT:
-* window - one of the 4 windows ( defined in gtMemory.h ).
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
-{
- RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
- BIT31);
-}
-
-/*******************************************************************************
-* memorySetPciRemapValue - Set a remap value to a PCI memory space target.
-*
-* DESCRIPTION:
-* In addition to the address decoding mechanism, the CPU has an address
-* remapping mechanism to be used by every PCI decoding window. Each PCI
-* window can be remaped to a desired address target according to the remap
-* value within the remap register. The address remapping is useful when a
-* CPU address range must be reallocated to a different location on the
-* PCI bus. Also, it enables CPU access to a PCI agent located above the
-* 4Gbyte space. On system boot, each of the PCI memory spaces is maped to
-* a defualt value (see CPU interface section in the MV spec for the
-* default values). The remap mechanism does not always produce the desired
-* address on the PCI bus because of the remap mechanism way of working
-* (to fully understand why, please see the 'Address Remapping' section in
-* the MV's spec). Therefor, this function sets a desired remap value to
-* one of the PCI memory windows and return the effective address that
-* should be used when exiting the PCI memory window. You should ALWAYS use
-* the returned value by this function when remapping a PCI window and
-* exiting it. If for example the base address of PCI0 memory 0 is
-* 0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
-* the function will return the value of 0x91000000 that MUST
-* be used to exit this memory window in order to achive the deisred
-* remapping.
-*
-* INPUT:
-* memoryWindow - One of the PCI memory windows as defined in Memory.h
-* remapValueLow - The low remap value.
-* remapValueHigh - The high remap value.
-* OUTPUT:
-* None.
-*
-* RETURN:
-* The effective base address to exit the PCI, or 0xffffffff if one of the
-* parameters is erroneous or the effective base address is higher the top
-* decode value.
-*
-*******************************************************************************/
-unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
- unsigned int remapValueHigh,
- unsigned int remapValueLow)
-{
- unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
- unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
- unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
-
- /* Initializing the base and size variables of the PCI
- memory windows */
- switch (memoryWindow) {
- case PCI_0_IO:
- pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_IO_SIZE;
- remapRegLow = PCI_0_IO_ADDR_REMAP;
- remapRegHigh = PCI_0_IO_ADDR_REMAP;
- break;
- case PCI_0_MEM0:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
- remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
- break;
- case PCI_0_MEM1:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
- remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
- break;
- case PCI_0_MEM2:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
- remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
- break;
- case PCI_0_MEM3:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
- remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_IO_SIZE;
- remapRegLow = PCI_1_IO_ADDR_REMAP;
- remapRegHigh = PCI_1_IO_ADDR_REMAP;
- break;
- case PCI_1_MEM0:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
- remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
- break;
- case PCI_1_MEM1:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
- remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
- break;
- case PCI_1_MEM2:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
- remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
- break;
- case PCI_1_MEM3:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
- remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- /* Retrun an invalid effective base address */
- return 0xffffffff;
- }
- /* Writing the remap value to the remap regisers */
- GT_REG_WRITE (remapRegHigh, remapValueHigh);
- GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
- /* Reading the values from the base address and size registers */
- baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
- windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
- /* Start calculating the effective Base Address */
- effectiveBaseAddress = baseAddrValue << 16;
- /* The effective base address will be combined from the chopped (if any)
- remap value (according to the size value and remap mechanism) and the
- window's base address */
- effectiveBaseAddress |=
- (((windowSizeValue << 16) | 0xffff) & remapValueLow);
- /* If the effectiveBaseAddress exceed the window boundaries return an
- invalid value. */
- if (effectiveBaseAddress >
- ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
- return 0xffffffff;
- return effectiveBaseAddress;
-}
-
-/********************************************************************
-* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
-* supports Cache Coherency.
-*
-*
-* Inputs: SNOOP_REGION region - One of the four regions.
-* SNOOP_TYPE snoopType - There is four optional Types:
-* 1. No Snoop.
-* 2. Snoop to WT region.
-* 3. Snoop to WB region.
-* 4. Snoop & Invalidate to WB region.
-* unsigned int baseAddress - Base Address of this region.
-* unsigned int topAddress - Top Address of this region.
-* Returns: false if one of the parameters is wrong and true else
-*********************************************************************/
-/* evb6260 code */
-#if 0
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
- MEMORY_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
-
- if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
- return false;
- snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
- snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
- if(regionLength == 0) /* closing the region */
- {
- GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
- GT_REG_WRITE(snoopXtopAddress,0);
- return true;
- }
- baseAddress = baseAddress & 0xffff0000;
- data = (baseAddress >> 16) | snoopType << 16;
- GT_REG_WRITE(snoopXbaseAddress,data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
- return true;
-}
-#endif
-
-/********************************************************************
-* memoryRemapAddress - This fubction used for address remapping.
-*
-*
-* Inputs: regOffset: remap register
-* remapValue :
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*
-* Not needed function To_do !!!!
-*********************************************************************/
-bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
-{
- unsigned int valueForReg;
-
- valueForReg = (remapValue & 0xfff00000) >> 20;
- GT_REG_WRITE (remapReg, valueForReg);
- return true;
-}
-
-/*******************************************************************************
-* memoryGetDeviceParam - Extract the device parameters from the device bank
-* parameters register.
-*
-* DESCRIPTION:
-* To allow interfacing with very slow devices and fast synchronous SRAMs,
-* each device can be programed to different timing parameters. Each bank
-* has its own parameters register. Bank width can be programmed to 8, 16,
-* or 32-bits. Bank timing parameters can be programmed to support
-* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-* Controllers). The MV allows you to set timing parameters and width for
-* each device through parameters register .
-* This function extracts the parameters described from the Device Bank
-* parameters register and fills the given 'deviceParam' (defined in
-* gtMemory.h) structure with the read data.
-*
-* INPUT:
-* deviceParam - pointer to a structure DEVICE_PARAM (defined in
-* Memory.h).For details about each structure field please
-* see the device timing parameter section in the MV
-* datasheet.
-* deviceNum - Select on of the five device banks (defined in
-* Memory.h) :
-*
-* - DEVICE0
-* - DEVICE1
-* - DEVICE2
-* - etc.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memoryGetDeviceParam - This function used for getting device parameters from
-* DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK
-* PARAMETERS REGISTER
-* - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-
-bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
- unsigned int valueOfReg;
- unsigned int calcData;
-
- if (deviceNum > 4)
- return false;
- GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
- calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
- deviceParam->turnOff = calcData; /* Turn Off */
-
- calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
- deviceParam->acc2First = calcData; /* Access To First */
-
- calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
- deviceParam->acc2Next = calcData; /* Access To Next */
-
- calcData =
- ((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
- deviceParam->ale2Wr = calcData; /* Ale To Write */
-
- calcData = ((0x1c000 & valueOfReg) >> 14) +
- ((BIT26 & valueOfReg) >> 23);
- deviceParam->wrLow = calcData; /* Write Active */
-
- calcData = ((0xe0000 & valueOfReg) >> 17) +
- ((BIT27 & valueOfReg) >> 24);
- deviceParam->wrHigh = calcData; /* Write High */
-
- calcData = ((0x300000 & valueOfReg) >> 20);
- deviceParam->deviceWidth = (BIT0 << calcData); /* In bytes */
- calcData = ((0x30000000 & valueOfReg) >> 28);
- deviceParam->badrSkew = calcData; /* Cycles gap between BAdr
- toggle to read data sample. */
- calcData = ((0x40000000 & valueOfReg) >> 30);
- deviceParam->DPEn = calcData; /* Data Parity enable */
- return true;
-}
-
-/*******************************************************************************
-* memorySetDeviceParam - Set new parameters for a device.
-*
-*
-* DESCRIPTION:
-* To allow interfacing with very slow devices and fast synchronous SRAMs,
-* each device can be programed to different timing parameters. Each bank
-* has its own parameters register. Bank width can be programmed to 8, 16,
-* or 32-bits. Bank timing parameters can be programmed to support
-* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-* Controllers). The MV allows you to set timing parameters and width for
-* each device through parameters register. This function set new
-* parameters to a device Bank from the delivered structure 'deviceParam'
-* (defined in gtMemory.h). The structure must be initialized with data
-* prior to the use of these function.
-*
-* INPUT:
-* deviceParam - pointer to a structure DEVICE_PARAM (defined in
-* Memory.h).For details about each structure field please
-* see the device timing parameter section in the MV
-* datasheet.
-* deviceNum - Select on of the five device banks (defined in
-* Memory.h) :
-*
-* - DEVICE0
-* - DEVICE1
-* - DEVICE2
-* - etc.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memorySetDeviceParam - This function used for setting device parameters to
-* DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK
-* PARAMETERS REGISTER
-* - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
- unsigned int valueForReg;
-
- if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
- (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
- (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
- (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
- return false;
- }
- valueForReg = (((deviceParam->turnOff) & 0x7) |
- (((deviceParam->turnOff) & 0x8) << 19) |
- (((deviceParam->acc2First) & 0xf) << 3) |
- (((deviceParam->acc2First) & 0x10) << 19) |
- (((deviceParam->acc2Next) & 0xf) << 7) |
- (((deviceParam->acc2Next) & 0x10) << 20) |
- (((deviceParam->ale2Wr) & 0x7) << 11) |
- (((deviceParam->ale2Wr) & 0xf) << 22) |
- (((deviceParam->wrLow) & 0x7) << 14) |
- (((deviceParam->wrLow) & 0xf) << 23) |
- (((deviceParam->wrHigh) & 0x7) << 17) |
- (((deviceParam->wrHigh) & 0xf) << 24) |
- (((deviceParam->badrSkew) & 0x3) << 28) |
- (((deviceParam->DPEn) & 0x1) << 30));
-
- /* insert the device width: */
- switch (deviceParam->deviceWidth) {
- case 1:
- valueForReg = valueForReg | _8BIT;
- break;
- case 2:
- valueForReg = valueForReg | _16BIT;
- break;
- case 4:
- valueForReg = valueForReg | _32BIT;
- break;
- default:
- valueForReg = valueForReg | _8BIT;
- break;
- }
- GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
- return true;
-}
-
-/*******************************************************************************
-* MemoryDisableWindow - Disable a memory space by the disable bit.
-* DESCRIPTION:
-* This function disables one of the 21 availiable windows dedicated for
-* the CPU decoding mechanism. Its possible to combine several windows with
-* the OR command.
-* INPUT:
-* window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-* None.
-* RETURN:
-* None.
-*******************************************************************************/
-void MemoryDisableWindow (MEMORY_WINDOW window)
-{
- SET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryEnableWindow - Enable a memory space that was disabled by
-* 'MemoryDisableWindow'.
-* DESCRIPTION:
-* This function enables one of the 21 availiable windows dedicated for the
-* CPU decoding mechanism. Its possible to combine several windows with the
-* OR command.
-* INPUT:
-* window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-* None.
-* RETURN:
-* None.
-*******************************************************************************/
-void MemoryEnableWindow (MEMORY_WINDOW window)
-{
- RESET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryGetMemWindowStatus - This function check whether the memory window is
-* disabled or not.
-* DESCRIPTION:
-* This function checks if the given memory window is closed .
-* INPUT:
-* window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-* None.
-* RETURN:
-* true for a closed window, false otherwise .
-*******************************************************************************/
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
-{
- if (GTREGREAD (BASE_ADDR_ENABLE) & window)
- return MEM_WINDOW_DISABLED;
- return MEM_WINDOW_ENABLED;
-}
+++ /dev/null
-/*
- * COM1 NS16550 support
- * originally from linux source (arch/powerpc/boot/ns16550.c)
- * modified to use CONFIG_SYS_ISA_MEM and new defines
- *
- * further modified by Josh Huber <huber@mclx.com> to support
- * the DUART on the Galileo Eval board. (db64360)
- */
-
-#include <config.h>
-#include "ns16550.h"
-
-#ifdef ZUMA_NTL
-/* no 16550 device */
-#else
-const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
- (NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
-};
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
-{
- volatile struct NS16550 *com_port;
-
- com_port = (struct NS16550 *) COM_PORTS[chan];
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
-
- /* Clear & enable FIFOs */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
- return (com_port);
-}
-
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
-{
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
-
- /* Clear & enable FIFOs */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
-}
-
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
-{
- while ((com_port->lsr & LSR_THRE) == 0);
- com_port->thr = c;
-}
-
-unsigned char NS16550_getc (volatile struct NS16550 *com_port)
-{
- while ((com_port->lsr & LSR_DR) == 0);
- return (com_port->rbr);
-}
-
-int NS16550_tstc (volatile struct NS16550 *com_port)
-{
- return ((com_port->lsr & LSR_DR) != 0);
-}
-#endif
+++ /dev/null
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/powerpc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CONFIG_SYS_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- *
- * further modified to support the DUART in the Galileo eval board
- * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- */
-
-#ifndef __NS16550_H__
-#define __NS16550_H__
-
-/* the padding is necessary because on the galileo board the UART is
- wired in with the 3 address lines shifted over by 2 bits */
-struct NS16550
-{
- unsigned char rbr; /* 0 = 0-3*/
- int pad1:24;
-
- unsigned char ier; /* 1 = 4-7*/
- int pad2:24;
-
- unsigned char fcr; /* 2 = 8-b*/
- int pad3:24;
-
- unsigned char lcr; /* 3 = c-f*/
- int pad4:24;
-
- unsigned char mcr; /* 4 = 10-13*/
- int pad5:24;
-
- unsigned char lsr; /* 5 = 14-17*/
- int pad6:24;
-
- unsigned char msr; /* 6 =18-1b*/
- int pad7:24;
-
- unsigned char scr; /* 7 =1c-1f*/
- int pad8:24;
-} __attribute__ ((packed));
-
-/* aliases */
-#define thr rbr
-#define iir fcr
-#define dll rbr
-#define dlm ier
-
-#define FCR_FIFO_EN 0x01 /*fifo enable*/
-#define FCR_RXSR 0x02 /*receiver soft reset*/
-#define FCR_TXSR 0x04 /*transmitter soft reset*/
-
-
-#define MCR_DTR 0x01
-#define MCR_RTS 0x02
-#define MCR_DMA_EN 0x04
-#define MCR_TX_DFR 0x08
-
-
-#define LCR_WLS_MSK 0x03 /* character length slect mask*/
-#define LCR_WLS_5 0x00 /* 5 bit character length */
-#define LCR_WLS_6 0x01 /* 6 bit character length */
-#define LCR_WLS_7 0x02 /* 7 bit character length */
-#define LCR_WLS_8 0x03 /* 8 bit character length */
-#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN 0x08 /* Parity eneble*/
-#define LCR_EPS 0x10 /* Even Parity Select*/
-#define LCR_STKP 0x20 /* Stick Parity*/
-#define LCR_SBRK 0x40 /* Set Break*/
-#define LCR_BKSE 0x80 /* Bank select enable*/
-
-#define LSR_DR 0x01 /* Data ready */
-#define LSR_OE 0x02 /* Overrun */
-#define LSR_PE 0x04 /* Parity error */
-#define LSR_FE 0x08 /* Framing error */
-#define LSR_BI 0x10 /* Break */
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR_TEMT 0x40 /* Xmitter empty */
-#define LSR_ERR 0x80 /* Error */
-
-/* useful defaults for LCR*/
-#define LCR_8N1 0x03
-
-
-#define COM1 0x03F8
-#define COM2 0x02F8
-
-volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc(volatile struct NS16550 *com_port);
-int NS16550_tstc(volatile struct NS16550 *com_port);
-void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
-
-typedef struct NS16550 *NS16550_t;
-
-extern const NS16550_t COM_PORTS[];
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * serial.c - serial support for the gal ev board
- */
-
-/* supports both the 16650 duart and the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "../include/memory.h"
-
-#include "ns16550.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_MPSC
-static int marvell_serial_init(void)
-{
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
- int clock_divisor = 230400 / gd->baudrate;
-#endif
-
- mpsc_init (gd->baudrate);
-
- /* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
- return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
- if (c == '\n')
- mpsc_putchar ('\r');
-
- mpsc_putchar (c);
-}
-
-static int marvell_serial_getc(void)
-{
- return mpsc_getchar ();
-}
-
-static int marvell_serial_tstc(void)
-{
- return mpsc_test_char ();
-}
-
-static void marvell_serial_setbrg(void)
-{
- galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-#else /* ! CONFIG_MPSC */
-
-static int marvell_serial_init(void)
-{
- int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- (void) NS16550_init (0, clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- (void) NS16550_init (1, clock_divisor);
-#endif
- return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
- if (c == '\n')
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-static int marvell_serial_getc(void)
-{
- return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static int marvell_serial_tstc(void)
-{
- return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static void marvell_serial_setbrg(void)
-{
- int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-#endif /* CONFIG_MPSC */
-
-static struct serial_device marvell_serial_drv = {
- .name = "marvell_serial",
- .start = marvell_serial_init,
- .stop = NULL,
- .setbrg = marvell_serial_setbrg,
- .putc = marvell_serial_putc,
- .puts = default_serial_puts,
- .getc = marvell_serial_getc,
- .tstc = marvell_serial_tstc,
-};
-
-void marvell_serial_initialize(void)
-{
- serial_register(&marvell_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &marvell_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
+++ /dev/null
-/* Memory.h - Memory mappings and remapping functions declarations */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCmemoryh
-#define __INCmemoryh
-
-/* includes */
-
-#include "core.h"
-
-/* defines */
-
-#define DONT_MODIFY 0xffffffff
-#define PARITY_SUPPORT 0x40000000
-#define MINIMUM_MEM_BANK_SIZE 0x10000
-#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000
-#define MINIMUM_PCI_WINDOW_SIZE 0x10000
-#define MINIMUM_ACCESS_WIN_SIZE 0x10000
-
-#define _8BIT 0x00000000
-#define _16BIT 0x00100000
-#define _32BIT 0x00200000
-#define _64BIT 0x00300000
-
-/* typedefs */
-
- typedef struct deviceParam
-{ /* boundary values */
- unsigned int turnOff; /* 0x0 - 0xf */
- unsigned int acc2First; /* 0x0 - 0x1f */
- unsigned int acc2Next; /* 0x0 - 0x1f */
- unsigned int ale2Wr; /* 0x0 - 0xf */
- unsigned int wrLow; /* 0x0 - 0xf */
- unsigned int wrHigh; /* 0x0 - 0xf */
- unsigned int badrSkew; /* 0x0 - 0x2 */
- unsigned int DPEn; /* 0x0 - 0x1 */
- unsigned int deviceWidth; /* in Bytes */
-} DEVICE_PARAM;
-
-
-typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
-typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
-
-/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
- MEM_REGION3,MEM_REGION4,MEM_REGION5, \
- MEM_REGION6,MEM_REGION7} \
- MEMORY_PROTECT_REGION;*/
-/* There are four possible windows that can be defined as protected */
-typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
- MEM_WINDOW3
- } MEMORY_PROTECT_WINDOW;
-/* When defining a protected window , this paramter indicates whether it
- is accessible or not */
-typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
- MEMORY_ACCESS;
-typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
- MEMORY_ACCESS_WRITE;
-typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
- MEMORY_CACHE_PROTECT;
-typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
- MEMORY_SNOOP_TYPE;
-typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
- MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
- MEMORY_SNOOP_REGION;
-
-/* There are 21 memory windows dedicated for the varios interfaces (PCI,
- devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
- address decoding mechanism. */
-typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
- CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
- DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
- DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
- BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
- PCI_0_MEM0_WINDOW = BIT10,
- PCI_0_MEM1_WINDOW = BIT11,
- PCI_0_MEM2_WINDOW = BIT12,
- PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
- PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
- PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
- INTEGRATED_SRAM_WINDOW = BIT19,
- INTERNAL_SPACE_WINDOW = BIT20,
- ALL_WINDOWS = 0X1FFFFF
- } MEMORY_WINDOW;
-
-typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
- } MEMORY_WINDOW_STATUS;
-
-
-typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
-#ifdef INCLUDE_PCI_1
- ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
-#endif /* INCLUDE_PCI_1 */
- } PCI_MEM_WINDOW;
-
-
-/* -------------------------------------------------------------------------------------------------*/
-
-/* functions */
-unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
-unsigned int memoryGetDeviceBaseAddress(DEVICE device);
-/* New at MV6436x */
-unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
-unsigned int memoryGetBankSize(MEMORY_BANK bank);
-unsigned int memoryGetDeviceSize(DEVICE device);
-unsigned int memoryGetDeviceWidth(DEVICE device);
-/* New at MV6436x */
-unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
-
-/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
-bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
-/* Set a new base and size for one of the memory banks (CS0 - CS3) */
-bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
- unsigned int bankSize);
-bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
-
-/* Change the Internal Register Base Address to a new given Address. */
-bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
-/* returns internal Register Space Base Address. */
-unsigned int memoryGetInternalRegistersSpace(void);
-
-/* Returns the integrated SRAM Base Address. */
-unsigned int memoryGetInternalSramBaseAddr(void);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Set new base address for the integrated SRAM. */
-void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Delete a protection feature to a given space. */
-void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Writes a new remap value to the remap register */
-unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
- unsigned int remapValueHigh,
- unsigned int remapValueLow);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Configurate the protection feature to a given space. */
-bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
- MEMORY_ACCESS gtMemoryAccess,
- MEMORY_ACCESS_WRITE gtMemoryWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress,
- unsigned int size);
-
-/* Configurate the protection feature to a given space. */
-/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
- MEMORY_ACCESS memoryAccess,
- MEMORY_ACCESS_WRITE memoryWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress,
- unsigned int regionLength); */
-/* Configurate the snoop feature to a given space. */
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
- MEMORY_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength);
-
-bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
-bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-/* Set a new base and size for one of the PCI windows. */
-bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
- unsigned int pciWindowSize);
-
-/* Disable or enable one of the 21 windows dedicated for the CPU's
- address decoding mechanism */
-void MemoryDisableWindow(MEMORY_WINDOW window);
-void MemoryEnableWindow (MEMORY_WINDOW window);
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
-#endif /* __INCmemoryh */
+++ /dev/null
-/* PCI.h - PCI functions header file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCpcih
-#define __INCpcih
-
-/* includes */
-
-#include "core.h"
-#include "memory.h"
-
-/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
-#define PCI_MAX_DEVICES 22
-
-
-/* Macros */
-
-/* The next Macros configurate the initiator board (SELF) or any any agent on
- the PCI to become: MASTER, response to MEMORY transactions , response to
- IO transactions or TWO both MEMORY_IO transactions. Those configuration
- are for both PCI0 and PCI1. */
-
-#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
-
-#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
- pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
- pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define MASTER_ENABLE BIT2
-#define MEMORY_ENABLE BIT1
-#define I_O_ENABLE BIT0
-#define SELF 32
-
-/* Agent on the PCI bus may have up to 6 BARS. */
-#define BAR0 0x10
-#define BAR1 0x14
-#define BAR2 0x18
-#define BAR3 0x1c
-#define BAR4 0x20
-#define BAR5 0x24
-#define BAR_SEL_MEM_IO BIT0
-#define BAR_MEM_TYPE_32_BIT NO_BIT
-#define BAR_MEM_TYPE_BELOW_1M BIT1
-#define BAR_MEM_TYPE_64_BIT BIT2
-#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2)
-#define BAR_MEM_TYPE_MASK (BIT1 | BIT2)
-#define BAR_PREFETCHABLE BIT3
-#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3)
-
-/* Defines for the access regions. */
-#define PREFETCH_ENABLE BIT12
-#define PREFETCH_DISABLE NO_BIT
-#define DELAYED_READ_ENABLE BIT13
-/* #define CACHING_ENABLE BIT14 */
-/* aggressive prefetch: PCI slave prefetch two burst in advance*/
-#define AGGRESSIVE_PREFETCH BIT16
-/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
-/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
-#define MAX_BURST_4 NO_BIT
-#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
-#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
-#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
-#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
-#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
-#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
-#define PCI_ACCESS_PROTECT BIT28
-#define PCI_WRITE_PROTECT BIT29
-
-/* typedefs */
-
-typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
- REGION6,REGION7} PCI_ACCESS_REGIONS;
-
-typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
-typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
-
-typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
- PCI_SNOOP_TYPE;
-typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
- PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
- PCI_SNOOP_REGION;
-
-typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
-typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
- PCI_REGION2,PCI_REGION3,
- PCI_IO}
- PCI_REGION;
-
-/*ronen 7/Dec/03 */
-typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
- PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
- PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
- PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
- PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
- PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
- PCI_LAST_BAR} PCI_INTERNAL_BAR;
-
-typedef struct pciBar {
- unsigned int detectBase;
- unsigned int base;
- unsigned int size;
- unsigned int type;
-} PCI_BAR;
-
-typedef struct pciDevice {
- PCI_HOST host;
- char type[40];
- unsigned int deviceNum;
- unsigned int venID;
- unsigned int deviceID;
- PCI_BAR bar[6];
-} PCI_DEVICE;
-
-typedef struct pciSelfBars {
- unsigned int SCS0Base;
- unsigned int SCS0Size;
- unsigned int SCS1Base;
- unsigned int SCS1Size;
- unsigned int SCS2Base;
- unsigned int SCS2Size;
- unsigned int SCS3Base;
- unsigned int SCS3Size;
- unsigned int internalMemBase;
- unsigned int internalIOBase;
- unsigned int CS0Base;
- unsigned int CS0Size;
- unsigned int CS1Base;
- unsigned int CS1Size;
- unsigned int CS2Base;
- unsigned int CS2Size;
- unsigned int CS3Base;
- unsigned int CS3Size;
- unsigned int CSBootBase;
- unsigned int CSBootSize;
- unsigned int P2PMem0Base;
- unsigned int P2PMem0Size;
- unsigned int P2PMem1Base;
- unsigned int P2PMem1Size;
- unsigned int P2PIOBase;
- unsigned int P2PIOSize;
- unsigned int CPUBase;
- unsigned int CPUSize;
-} PCI_SELF_BARS;
-
-/* read/write configuration registers on local PCI bus. */
-void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum, unsigned int data);
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum);
-
-/* read/write configuration registers on another PCI bus. */
-void pciOverBridgeWriteConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum,unsigned int data);
-unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum);
-
-/* Performs full scane on both PCI and returns all detail possible on the
- agents which exist on the bus. */
-void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
- unsigned int numberOfElment);
-
-/* Master`s memory space */
-bool pciMapSpace(PCI_HOST host, PCI_REGION region,
- unsigned int remapBase,
- unsigned int deviceBase,
- unsigned int deviceLength);
-unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
-unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
-
-/* Slave`s memory space */
-void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
- unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
-
-#if 0 /* GARBAGE routines - dont use till they get cleaned up */
-void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
-void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
-void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
-void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
-void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
- unsigned int pci0Dev0Length);
-void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
- unsigned int pci1Dev0Length);
-void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
- unsigned int pci0Dev1Length);
-void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
- unsigned int pci1Dev1Length);
-void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
- unsigned int pci0Dev2Length);
-void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
- unsigned int pci1Dev2Length);
-void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
- unsigned int pci0Dev3Length);
-void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
- unsigned int pci1Dev3Length);
-void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
- unsigned int pci0DevBootLength);
-void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
- unsigned int pci1DevBootLength);
-void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
- unsigned int pci0P2pMem0Length);
-void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
- unsigned int pci1P2pMem0Length);
-void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
- unsigned int pci0P2pMem1Length);
-void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
- unsigned int pci1P2pMem1Length);
-void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
- unsigned int pci0P2pIoLength);
-void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
- unsigned int pci1P2pIoLength);
-
-void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
-void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
-#endif
-
-/* PCI region options */
-
-bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
- unsigned int features, unsigned int baseAddress,
- unsigned int regionLength);
-
-void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
-
-/* PCI arbiter */
-
-bool pciArbiterEnable(PCI_HOST host);
-bool pciArbiterDisable(PCI_HOST host);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5);
-bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
- PCI_AGENT_PARK externalAgent0,
- PCI_AGENT_PARK externalAgent1,
- PCI_AGENT_PARK externalAgent2,
- PCI_AGENT_PARK externalAgent3,
- PCI_AGENT_PARK externalAgent4,
- PCI_AGENT_PARK externalAgent5);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-
-/* PCI-to-PCI (P2P) */
-
-bool pciP2PConfig(PCI_HOST host,
- unsigned int SecondBusLow,unsigned int SecondBusHigh,
- unsigned int busNum,unsigned int devNum);
-/* PCI Cache-coherency */
-
-bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
- PCI_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength);
-
-PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
-
-#endif /* __INCpcih */
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#ifdef CONFIG_SPL_OS_BOOT
/*
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
int board_eth_init(bd_t *bis)
{
}
#endif /* !defined(CONFIG_ARCHES) */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
extern int __ft_board_setup(void *blob, bd_t *bd);
int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
}
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#ifdef CONFIG_OF_BOARD_SETUP
/*
* Update 'model' and 'memory' properties in the blob according to the module
* that we are running on.
printf("ft_blob_update(): cannot set /model property err:%s\n",
fdt_strerror(ret));
}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+#endif /* CONFIG_OF_BOARD_SETUP */
/*
#endif /* CONFIG_LAST_STAGE_INIT */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
}
#endif /* defined(CONFIG_PCI) */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
return 1;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
static int ft_sethdmiinfmt(void *blob, char *mode)
{
return 0;
}
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
static struct mxc_serial_platdata ventana_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART2_BASE,
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
extern void __ft_board_setup(void *blob, bd_t *bd);
int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
+if TARGET_ODROID_C2
+
+config SYS_BOARD
+ default "odroid-c2"
+
+config SYS_VENDOR
+ default "hardkernel"
+
+config SYS_CONFIG_NAME
+ default "odroid-c2"
+
+endif
--- /dev/null
+ODROID-C2
+M: Beniamino Galvani <b.galvani@gmail.com>
+S: Maintained
+F: board/hardkernel/odroid-c2/
+F: include/configs/odroid-c2.h
+F: configs/odroid-c2_defconfig
--- /dev/null
+#
+# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := odroid-c2.o
--- /dev/null
+U-Boot for ODROID-C2
+====================
+
+ODROID-C2 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make odroid-c2_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > DIR=odroid-c2
+ > git clone --depth 1 \
+ https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
+ $DIR
+ > $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \
+ --bl301 $DIR/fip/gxb/bl301.bin \
+ --bl31 $DIR/fip/gxb/bl31.bin \
+ --bl33 u-boot.bin \
+ $DIR/fip.bin
+ > $DIR/fip/fip_create --dump $DIR/fip.bin
+ > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
+ > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
+ --input $DIR/boot_new.bin \
+ --output $DIR/u-boot.img
+ > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > BL1=$DIR/sd_fuse/bl1.bin.hardkernel
+ > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
+ > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
+ > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97
--- /dev/null
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <dm/platdata.h>
+#include <phy.h>
+
+#define EFUSE_SN_OFFSET 20
+#define EFUSE_SN_SIZE 16
+#define EFUSE_MAC_OFFSET 52
+#define EFUSE_MAC_SIZE 6
+
+int board_init(void)
+{
+ return 0;
+}
+
+static const struct eth_pdata gxbb_eth_pdata = {
+ .iobase = GXBB_ETH_BASE,
+ .phy_interface = PHY_INTERFACE_MODE_RGMII,
+};
+
+U_BOOT_DEVICE(meson_eth) = {
+ .name = "eth_designware",
+ .platdata = &gxbb_eth_pdata,
+};
+
+int misc_init_r(void)
+{
+ u8 mac_addr[EFUSE_MAC_SIZE];
+ ssize_t len;
+
+ /* Select Ethernet function */
+ setbits_le32(GXBB_PINMUX(6), 0x3fff);
+
+ /* Set RGMII mode */
+ setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
+ GXBB_ETH_REG_0_TX_PHASE(1) |
+ GXBB_ETH_REG_0_TX_RATIO(4) |
+ GXBB_ETH_REG_0_PHY_CLK_EN |
+ GXBB_ETH_REG_0_CLK_EN);
+
+ /* Enable power and clock gate */
+ setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
+ clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+
+ /* Reset PHY on GPIOZ_14 */
+ clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
+ clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+ mdelay(10);
+ setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ mac_addr, EFUSE_MAC_SIZE);
+ if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ return 0;
+}
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
static void ft_adapt_flash_base(void *blob)
{
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CMD_IDE */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
static void ft_delete_node(void *fdt, const char *compat)
{
int off = -1;
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
int board_eth_init(bd_t *bis)
{
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#if defined(CONFIG_STATUS_LED)
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
struct node_info nodes[] = {
{ "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
/*
* If argument is NULL, set the LCD brightness to the
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
KEEP(*(SORT(.u_boot_list*)));
}
+ PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
KEEP(*(SORT(.u_boot_list*)));
}
+ PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
KEEP(*(SORT(.u_boot_list*)));
}
+ PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
A wide range of commands is implemented. Filesystems which use a block
device are supported.
-Also sandbox uses generic board (CONFIG_SYS_GENERIC_BOARD) and supports
-driver model (CONFIG_DM) and associated commands.
+Also sandbox supports driver model (CONFIG_DM) and associated commands.
Linux RAW Networking Bridge
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
u32 val[12];
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#define DEFAULT_BRIGHTNESS 25
#define BACKLIGHT_ENABLE (1 << 31)
F: configs/am335x_boneblack_defconfig
F: configs/am335x_boneblack_vboot_defconfig
F: configs/am335x_evm_defconfig
-F: configs/am335x_gp_evm_defconfig
F: configs/am335x_evm_nor_defconfig
F: configs/am335x_evm_norboot_defconfig
F: configs/am335x_evm_spiboot_defconfig
#include <common.h>
#include <errno.h>
#include <spl.h>
+#include <serial.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN 7
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
#if defined(CONFIG_SPL_BUILD) || \
(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
}
+#ifndef CONFIG_DM_SERIAL
+struct serial_device *default_serial_console(void)
+{
+ if (board_is_icev2())
+ return &eserial4_device;
+ else
+ return &eserial1_device;
+}
+#endif
+
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
};
+static const struct ddr_data ddr3_icev2_data = {
+ .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
+ .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
+ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
+ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
+};
+
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J128MJT125_RATIO,
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};
+static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
+ .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
+ .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+ .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
+ .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+ .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
+ .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+};
+
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41J128MJT125_EMIF_SDCFG,
.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
PHY_EN_DYN_PWRDN,
};
+static struct emif_regs ddr3_icev2_emif_reg_data = {
+ .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
+ .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
+ .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
+ .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
+ .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
+ .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
+ .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
+ PHY_EN_DYN_PWRDN,
+};
+
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
if (board_is_evm_sk())
return &dpll_ddr_evm_sk;
- else if (board_is_bone_lt())
+ else if (board_is_bone_lt() || board_is_icev2())
return &dpll_ddr_bone_black;
else if (board_is_evm_15_or_later())
return &dpll_ddr_evm_sk;
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
+ if (board_is_icev2()) {
+ gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
+ gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
+ }
+
if (board_is_evm_sk())
config_ddr(303, &ioregs_evmsk, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_evm_15_or_later())
config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
+ else if (board_is_icev2())
+ config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
+ &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
+ 0);
else
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
#endif
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void request_and_set_gpio(int gpio, char *name)
+{
+ int ret;
+
+ ret = gpio_request(gpio, name);
+ if (ret < 0) {
+ printf("%s: Unable to request %s\n", __func__, name);
+ return;
+ }
+
+ ret = gpio_direction_output(gpio, 0);
+ if (ret < 0) {
+ printf("%s: Unable to set %s as output\n", __func__, name);
+ goto err_free_gpio;
+ }
+
+ gpio_set_value(gpio, 1);
+
+ return;
+
+err_free_gpio:
+ gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N);
+
+/**
+ * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
+ * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
+ * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
+ * give 50MHz output for Eth0 and 1.
+ */
+static struct clk_synth cdce913_data = {
+ .id = 0x81,
+ .capacitor = 0x90,
+ .mux = 0x6d,
+ .pdiv2 = 0x2,
+ .pdiv3 = 0x2,
+};
+#endif
+
/*
* Basic board specific setup. Pinmux has been handled already.
*/
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
gpmc_init();
#endif
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
+ int rv;
+
+ if (board_is_icev2()) {
+ REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
+ REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
+ REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
+ REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
+
+ rv = setup_clock_synthesizer(&cdce913_data);
+ if (rv) {
+ printf("Clock synthesizer setup failed %d\n", rv);
+ return rv;
+ }
+ }
+#endif
+
return 0;
}
};
#endif
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+ defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+
/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
- && defined(CONFIG_SPL_BUILD)) || \
- ((defined(CONFIG_DRIVER_TI_CPSW) || \
- defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
+ } else if (board_is_icev2()) {
+ writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
+ cpsw_slaves[0].phy_addr = 1;
+ cpsw_slaves[1].phy_addr = 3;
} else {
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
#endif
#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
+ return 0;
+ else if (board_is_bone() && !strcmp(name, "am335x-bone"))
+ return 0;
+ else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
+ return 0;
+ else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
+ return 0;
+ else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
+ return 0;
+ else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
+ return 0;
+ else
+ return -1;
+}
+#endif
strncmp("1.5", board_ti_get_rev(), 3) <= 0);
}
+static inline int board_is_icev2(void)
+{
+ return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
+}
+
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
{-1},
};
+static struct module_pin_mux gpio0_18_pin_mux[] = {
+ {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */
+ {-1},
+};
+
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
{-1},
};
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+ {-1},
+};
+
#ifdef CONFIG_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
};
#endif
+static struct module_pin_mux uart3_icev2_pin_mux[] = {
+ {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */
+ {-1},
+};
+
#if defined(CONFIG_NOR_BOOT)
void enable_norboot_pin_mux(void)
{
#else
configure_module_pin_mux(mmc1_pin_mux);
#endif
+ } else if (board_is_icev2()) {
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(gpio0_18_pin_mux);
+ configure_module_pin_mux(uart3_icev2_pin_mux);
+ configure_module_pin_mux(rmii1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
} else {
puts("Unknown board, cannot configure pinmux.");
hang();
F: configs/am43xx_evm_qspiboot_defconfig
F: configs/am43xx_evm_ethboot_defconfig
F: configs/am43xx_evm_usbhost_boot_defconfig
-F: configs/am437x_gp_evm_defconfig
-F: configs/am437x_sk_evm_defconfig
if (board_is_eposevm())
return &epos_evm_dpll_ddr[ind];
- else if (board_is_gpevm() || board_is_sk())
+ else if (board_is_evm() || board_is_sk())
return &gp_evm_dpll_ddr;
else if (board_is_idk())
return &idk_dpll_ddr;
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz_beta, 0);
- } else if (board_is_gpevm()) {
+ } else if (board_is_evm()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz, 0);
return rv;
}
#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm"))
+ return 0;
+ else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
+ return 0;
+ else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
+ return 0;
+ else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
+ return 0;
+ else
+ return -1;
+}
+#endif
return board_ti_is("AM43_IDK");
}
+static inline int board_is_hsevm(void)
+{
+ return board_ti_is("AM43XXHS");
+}
+
+static inline int board_is_evm(void)
+{
+ return board_is_gpevm() || board_is_hsevm();
+}
+
static inline int board_is_evm_14_or_later(void)
{
- return (board_is_gpevm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0);
+ return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0;
}
static inline int board_is_evm_12_or_later(void)
{
- return (board_is_gpevm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0);
+ return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0;
}
void enable_uart0_pin_mux(void);
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mdio_pin_mux);
- if (board_is_gpevm()) {
+ if (board_is_evm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
return 0;
}
#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
S: Maintained
F: board/ti/dra7xx/
F: include/configs/dra7xx_evm.h
-F: configs/dra72_evm_defconfig
-F: configs/dra74_evm_defconfig
F: configs/dra7xx_evm_defconfig
-F: configs/dra7xx_evm_qspiboot_defconfig
-F: configs/dra7xx_evm_uart3_defconfig
return 0;
}
#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (is_dra72x() && !strcmp(name, "dra72-evm"))
+ return 0;
+ else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
+ return 0;
+ else
+ return -1;
+}
+#endif
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int lpae;
ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
#ifdef CONFIG_LCD
efi_gop_register();
#endif
+#ifdef CONFIG_NET
+ void *nethandle = loaded_image_info.device_handle;
+ efi_net_register(&nethandle);
+
+ if (!memcmp(bootefi_device_path[0].str, "N\0e\0t", 6))
+ loaded_image_info.device_handle = nethandle;
+#endif
/* Call our payload! */
#ifdef DEBUG_EFI
int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
char *const argv[])
{
- int dev, part;
+ __maybe_unused int dev;
+ int part;
ulong addr = CONFIG_SYS_LOAD_ADDR;
ulong cnt;
disk_partition_t info;
}
switch (w) {
case 1:
- l = (long)(*(unsigned char *)buf);
+ l = (long)(*(u8 *)buf);
break;
case 2:
- l = (long)(*(unsigned short *)buf);
+ l = (long)(*(u16 *)buf);
break;
case 4:
- l = (long)(*(unsigned long *)buf);
+ l = (long)(*(u32 *)buf);
break;
}
unmap_physmem(buf, w);
#include <mmc.h>
static int curr_device = -1;
-#ifndef CONFIG_GENERIC_MMC
-int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int dev;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- if (strcmp(argv[1], "init") == 0) {
- if (argc == 2) {
- if (curr_device < 0)
- dev = 1;
- else
- dev = curr_device;
- } else if (argc == 3) {
- dev = (int)simple_strtoul(argv[2], NULL, 10);
- } else {
- return CMD_RET_USAGE;
- }
-
- if (mmc_legacy_init(dev) != 0) {
- puts("No MMC card found\n");
- return 1;
- }
-
- curr_device = dev;
- printf("mmc%d is available\n", curr_device);
- } else if (strcmp(argv[1], "device") == 0) {
- if (argc == 2) {
- if (curr_device < 0) {
- puts("No MMC device available\n");
- return 1;
- }
- } else if (argc == 3) {
- dev = (int)simple_strtoul(argv[2], NULL, 10);
-
-#ifdef CONFIG_SYS_MMC_SET_DEV
- if (mmc_set_dev(dev) != 0)
- return 1;
-#endif
- curr_device = dev;
- } else {
- return CMD_RET_USAGE;
- }
-
- printf("mmc%d is current device\n", curr_device);
- } else {
- return CMD_RET_USAGE;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- mmc, 3, 1, do_mmc,
- "MMC sub-system",
- "init [dev] - init MMC sub system\n"
- "mmc device [dev] - show or set current device"
-);
-#else /* !CONFIG_GENERIC_MMC */
static void print_mmcinfo(struct mmc *mmc)
{
"display MMC info",
"- display info of the current MMC device"
);
-
-#endif /* !CONFIG_GENERIC_MMC */
endif
# boards
-obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
-obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
+obj-y += board_f.o
+obj-y += board_r.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
#elif defined(CONFIG_NDS32)
gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
-#else
+#elif defined(CONFIG_SYS_MONITOR_BASE)
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
#endif
state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
return 0;
bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
-#ifdef DEBUG
- puts("\n## Control returned to monitor - resetting...\n");
-#endif
+ debug("\n## Control returned to monitor - resetting...\n");
+
return BOOTM_ERR_RESET;
}
unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
+ struct blk_desc *desc = mmc_get_blk_desc(mmc);
blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
- n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
- blk_cnt, (u_char *)buffer);
+ n = blk_dwrite(desc, blk_start, blk_cnt, (u_char *)buffer);
return (n == blk_cnt) ? 0 : -1;
}
unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
+ struct blk_desc *desc = mmc_get_blk_desc(mmc);
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
- (uchar *)buffer);
+ n = blk_dread(desc, blk_start, blk_cnt, (uchar *)buffer);
return (n == blk_cnt) ? 0 : -1;
}
bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
-#ifndef CONFIG_SYS_GENERIC_BOARD
- puts("Warning: Your board does not use generic board. Please read\n");
- puts("doc/README.generic-board and take action. Boards not\n");
- puts("upgraded by the late 2014 may break or be removed.\n");
-#endif
-
#ifdef CONFIG_VERSION_VARIABLE
setenv("ver", version_string); /* set version variable */
#endif /* CONFIG_VERSION_VARIABLE */
#include <fat.h>
#include <errno.h>
#include <image.h>
+#include <libfdt.h>
static int fat_registered;
return err;
}
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+ ulong size, void *buf)
+{
+ loff_t actread;
+ int ret;
+ char *filename = (char *)load->filename;
+
+ ret = fat_read_file(filename, buf, file_offset, size, &actread);
+ if (ret)
+ return ret;
+
+ return actread;
+}
+
int spl_load_image_fat(struct blk_desc *block_dev,
int partition,
const char *filename)
if (err <= 0)
goto end;
- err = spl_parse_image_header(header);
- if (err)
- goto end;
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
+
+ debug("Found FIT\n");
+ load.read = spl_fit_read;
+ load.bl_len = 1;
+ load.filename = (void *)filename;
+ load.priv = NULL;
- err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+ return spl_load_simple_fit(&load, 0, header);
+ } else {
+ err = spl_parse_image_header(header);
+ if (err)
+ goto end;
+
+ err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+ }
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
*fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
len = fdt_getprop_u32(fdt, fdt_node, "data-size");
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("FIT: Selected '%s'\n", name);
-#endif
+ debug("FIT: Selected '%s'\n", name);
return len;
}
return -ENOENT;
}
+static int get_aligned_image_offset(struct spl_load_info *info, int offset)
+{
+ /*
+ * If it is a FS read, get the first address before offset which is
+ * aligned to ARCH_DMA_MINALIGN. If it is raw read return the
+ * block number to which offset belongs.
+ */
+ if (info->filename)
+ return offset & ~(ARCH_DMA_MINALIGN - 1);
+
+ return offset / info->bl_len;
+}
+
+static int get_aligned_image_overhead(struct spl_load_info *info, int offset)
+{
+ /*
+ * If it is a FS read, get the difference between the offset and
+ * the first address before offset which is aligned to
+ * ARCH_DMA_MINALIGN. If it is raw read return the offset within the
+ * block.
+ */
+ if (info->filename)
+ return offset & (ARCH_DMA_MINALIGN - 1);
+
+ return offset % info->bl_len;
+}
+
+static int get_aligned_image_size(struct spl_load_info *info, int data_size,
+ int offset)
+{
+ if (info->filename)
+ return data_size + get_aligned_image_overhead(info, offset);
+
+ return (data_size + info->bl_len - 1) / info->bl_len;
+}
+
int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
{
int sectors;
void *load_ptr;
int fdt_offset, fdt_len;
int data_offset, data_size;
- int base_offset;
+ int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
int src_sector;
void *dst;
* be before CONFIG_SYS_TEXT_BASE.
*/
fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len);
- sectors = (size + info->bl_len - 1) / info->bl_len;
+ fit = (void *)ALIGN((ulong)fit, 8);
+ sectors = get_aligned_image_size(info, size, 0);
count = info->read(info, sector, sectors, fit);
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
sector, sectors, fit, count);
* byte will be at 'load'. This may mean we need to load it starting
* before then, since we can only read whole blocks.
*/
- sectors = (data_size + info->bl_len - 1) / info->bl_len;
data_offset += base_offset;
+ sectors = get_aligned_image_size(info, data_size, data_offset);
load_ptr = (void *)load;
debug("U-Boot size %x, data %p\n", data_size, load_ptr);
- dst = load_ptr - (data_offset % info->bl_len);
+ dst = load_ptr;
/* Read the image */
- src_sector = sector + data_offset / info->bl_len;
- debug("image: data_offset=%x, dst=%p, src_sector=%x, sectors=%x\n",
- data_offset, dst, src_sector, sectors);
+ src_sector = sector + get_aligned_image_offset(info, data_offset);
+ debug("Aligned image read: dst=%p, src_sector=%x, sectors=%x\n",
+ dst, src_sector, sectors);
count = info->read(info, src_sector, sectors, dst);
if (count != sectors)
return -EIO;
+ debug("image: dst=%p, data_offset=%x, size=%x\n", dst, data_offset,
+ data_size);
+ memcpy(dst, dst + get_aligned_image_overhead(info, data_offset),
+ data_size);
/* Figure out which device tree the board wants to use */
fdt_len = spl_fit_select_fdt(fit, images, &fdt_offset);
/*
* Read the device tree and place it after the image. There may be
* some extra data before it since we can only read entire blocks.
+ * And also align the destination address to ARCH_DMA_MINALIGN.
*/
- dst = load_ptr + data_size;
+ dst = (void *)((load + data_size + align_len) & ~align_len);
fdt_offset += base_offset;
- count = info->read(info, sector + fdt_offset / info->bl_len, sectors,
- dst);
- debug("fit read %x sectors to %x, dst %p, data_offset %x\n",
- sectors, spl_image.load_addr, dst, fdt_offset);
+ sectors = get_aligned_image_size(info, fdt_len, fdt_offset);
+ src_sector = sector + get_aligned_image_offset(info, fdt_offset);
+ count = info->read(info, src_sector, sectors, dst);
+ debug("Aligned fdt read: dst %p, src_sector = %x, sectors %x\n",
+ dst, src_sector, sectors);
if (count != sectors)
return -EIO;
* After this we will have the U-Boot image and its device tree ready
* for us to start.
*/
- memcpy(dst, dst + fdt_offset % info->bl_len, fdt_len);
+ debug("fdt: dst=%p, data_offset=%x, size=%x\n", dst, fdt_offset,
+ fdt_len);
+ memcpy(load_ptr + data_size,
+ dst + get_aligned_image_overhead(info, fdt_offset), fdt_len);
return 0;
}
mmc->read_bl_len;
/* Read the header too to avoid extra memcpy */
- count = mmc->block_dev.block_read(&mmc->block_dev, sector,
- image_size_sectors,
- (void *)(ulong)spl_image.load_addr);
+ count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
+ (void *)(ulong)spl_image.load_addr);
debug("read %x sectors to %x\n", image_size_sectors,
spl_image.load_addr);
if (count != image_size_sectors)
{
struct mmc *mmc = load->dev;
- return mmc->block_dev.block_read(&mmc->block_dev, sector, count, buf);
+ return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf);
}
static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
sizeof(struct image_header));
/* read image header to find the image size & load address */
- count = mmc->block_dev.block_read(&mmc->block_dev, sector, 1, header);
+ count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, header);
debug("hdr read sector %lx, count=%lu\n", sector, count);
if (count == 0) {
ret = -EIO;
debug("Found FIT\n");
load.dev = mmc;
load.priv = NULL;
+ load.filename = NULL;
load.bl_len = mmc->read_bl_len;
load.read = h_spl_load_read;
ret = spl_load_simple_fit(&load, sector, header);
#include <spl.h>
#include <asm/io.h>
#include <nand.h>
+#include <libfdt_env.h>
+#include <fdt.h>
#if defined(CONFIG_SPL_NAND_RAW_ONLY)
int spl_nand_load_image(void)
return 0;
}
#else
+
+static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
+ ulong size, void *dst)
+{
+ int ret;
+
+ ret = nand_spl_load_image(offs, size, dst);
+ if (!ret)
+ return size;
+ else
+ return 0;
+}
+
static int spl_nand_load_element(int offset, struct image_header *header)
{
int err;
if (err)
return err;
- err = spl_parse_image_header(header);
- if (err)
- return err;
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
- return nand_spl_load_image(offset, spl_image.size,
- (void *)(unsigned long)spl_image.load_addr);
+ debug("Found FIT\n");
+ load.dev = NULL;
+ load.priv = NULL;
+ load.filename = NULL;
+ load.bl_len = 1;
+ load.read = spl_nand_fit_read;
+ return spl_load_simple_fit(&load, offset, header);
+ } else {
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
+ return nand_spl_load_image(offset, spl_image.size,
+ (void *)(ulong)spl_image.load_addr);
+ }
}
int spl_nand_load_image(void)
#include <xyzModem.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
+#include <libfdt.h>
#define BUF_SIZE 1024
+/*
+ * Information required to load image using ymodem.
+ *
+ * @image_read: Now of bytes read from the image.
+ * @buf: pointer to the previous read block.
+ */
+struct ymodem_fit_info {
+ int image_read;
+ char *buf;
+};
+
static int getcymodem(void) {
if (tstc())
return (getc());
return -1;
}
+static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset,
+ ulong size, void *addr)
+{
+ int res, err;
+ struct ymodem_fit_info *info = load->priv;
+ char *buf = info->buf;
+
+ while (info->image_read < offset) {
+ res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+ if (res <= 0)
+ return res;
+ info->image_read += res;
+ }
+
+ if (info->image_read > offset) {
+ res = info->image_read - offset;
+ memcpy(addr, &buf[BUF_SIZE - res], res);
+ addr = addr + res;
+ }
+
+ while (info->image_read < offset + size) {
+ res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+ if (res <= 0)
+ return res;
+
+ memcpy(addr, buf, res);
+ info->image_read += res;
+ addr += res;
+ }
+
+ return size;
+}
+
int spl_ymodem_load_image(void)
{
int size = 0;
int ret;
connection_info_t info;
char buf[BUF_SIZE];
- ulong store_addr = ~0;
ulong addr = 0;
info.mode = xyzModem_ymodem;
ret = xyzModem_stream_open(&info, &err);
+ if (ret) {
+ printf("spl: ymodem err - %s\n", xyzModem_error(err));
+ return ret;
+ }
+
+ res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+ if (res <= 0)
+ goto end_stream;
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic((struct image_header *)buf) == FDT_MAGIC) {
+ struct spl_load_info load;
+ struct ymodem_fit_info info;
+
+ debug("Found FIT\n");
+ load.dev = NULL;
+ load.priv = (void *)&info;
+ load.filename = NULL;
+ load.bl_len = 1;
+ info.buf = buf;
+ info.image_read = BUF_SIZE;
+ load.read = ymodem_read_fit;
+ ret = spl_load_simple_fit(&load, 0, (void *)buf);
+ size = info.image_read;
- if (!ret) {
- while ((res =
- xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
- if (addr == 0) {
- ret = spl_parse_image_header((struct image_header *)buf);
- if (ret)
- return ret;
- }
- store_addr = addr + spl_image.load_addr;
+ while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0)
+ size += res;
+ } else {
+ spl_parse_image_header((struct image_header *)buf);
+ ret = spl_parse_image_header((struct image_header *)buf);
+ if (ret)
+ return ret;
+ addr = spl_image.load_addr;
+ memcpy((void *)addr, buf, res);
+ size += res;
+ addr += res;
+
+ while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
+ memcpy((void *)addr, buf, res);
size += res;
addr += res;
- memcpy((char *)(store_addr), buf, res);
}
- } else {
- printf("spl: ymodem err - %s\n", xyzModem_error(err));
- return ret;
}
+end_stream:
xyzModem_stream_close(&err);
xyzModem_stream_terminate(false, &getcymodem);
CONFIG_ARM=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
+CONFIG_RSA=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_AM335X_EVM=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_RSA=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+# Device tree file can be same on HS evm
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL=y
+CONFIG_ISW_ENTRY_ADDR=0x40302ae0
CONFIG_SPL_STACK_R=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
CONFIG_HUSH_PARSER=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_DM_ETH=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DMA=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0403
-CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_DM_ETH=y
CONFIG_ARM=y
+CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
+CONFIG_SPL_LOAD_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_OF_LIBFDT=y
+CONFIG_SPL_OF_LIBFDT=y
CONFIG_ARM=y
+CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_ARM=y
+CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x30000000
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_ARM=y
+CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL=y
+CONFIG_ISW_ENTRY_ADDR=0x40300350
+CONFIG_SPL_STACK_R=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_DM_SERIAL=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_DM_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_DM_ETH=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_GPIO=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_CONS_INDEX=3
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="SPL_YMODEM_SUPPORT"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
CONFIG_PM8916_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_MSM_SDHCI=y
CONFIG_DM_PMIC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
# CONFIG_CMD_MISC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-EMU"
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-SIMU"
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_MESON_GXBB=y
+CONFIG_TARGET_ODROID_C2=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_SANDBOX_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
+CONFIG_MISC=y
+CONFIG_DM_MAILBOX=y
+CONFIG_SANDBOX_MBOX=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_REGEX=y
+CONFIG_BOOTP_VCI_STRING="Diagnostics"
CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca15x2_tc2"
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca5x2"
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca9x4"
CONFIG_G_DNL_VENDOR_NUM=0x03fd
CONFIG_G_DNL_PRODUCT_NUM=0x0300
# CONFIG_REGEX is not set
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_G_DNL_MANUFACTURER="Xilinx"
CONFIG_G_DNL_VENDOR_NUM=0x03FD
CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_G_DNL_MANUFACTURER="Xilinx"
CONFIG_G_DNL_VENDOR_NUM=0x03FD
CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_DM_ETH=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_G_DNL_MANUFACTURER="Xilinx"
CONFIG_G_DNL_VENDOR_NUM=0x03FD
CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_G_DNL_MANUFACTURER="Xilinx"
CONFIG_G_DNL_VENDOR_NUM=0x03FD
CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
gpt_e[i].starting_lba = cpu_to_le64(offset);
offset += partitions[i].size;
}
- if (offset >= last_usable_lba) {
+ if (offset > (last_usable_lba + 1)) {
printf("Partitions layout exceds disk size\n");
return -1;
}
generic source base.
To enable this feature, add CONFIG_OF_CONTROL to your board config file.
-It is currently supported on ARM, x86 and Microblaze - other architectures
-will need to add code to their arch/xxx/lib/board.c file to locate the
-FDT. Alternatively you can enable generic board support on your board
-(with CONFIG_SYS_GENERIC_BOARD) if this is available (as it is for
-PowerPC). For ARM, Tegra and Exynos5 have device trees available for
-common devices.
What is a Flat Device Tree?
# SPDX-License-Identifier: GPL-2.0+
#
-DEPRECATION NOTICE FOR arch/<arch>/lib/board.c
-
-For board maintainers: Please submit patches for boards you maintain before
-July 2014, to make them use generic board.
-
-For architecture maintainers: Please submit patches to remove your
-architecture-specific board.c file before October 2014.
-
-
Background
----------
-U-Boot has traditionally had a board.c file for each architecture. This has
-introduced quite a lot of duplication, with each architecture tending to do
+U-Boot traditionally had a board.c file for each architecture. This introduced
+quite a lot of duplication, with each architecture tending to do
initialisation slightly differently. To address this, a new 'generic board
-init' feature was introduced a year ago in March 2013 (further motivation is
+init' feature was introduced in March 2013 (further motivation is
provided in the cover letter below).
+All boards and architectures have moved to this as of mid 2016.
+
What has changed?
-----------------
-The main change is that the arch/<arch>/lib/board.c file is being removed in
+The main change is that the arch/<arch>/lib/board.c file is removed in
favour of common/board_f.c (for pre-relocation init) and common/board_r.c
(for post-relocation init).
have been moved to separate structures.
-Supported Architectures
-------------------------
-
-If you are unlucky then your architecture may not support generic board.
-The following architectures are supported now:
-
- arc
- arm
- avr32
- blackfin
- m68k
- microblaze
- mips
- nios2
- powerpc
- sandbox
- x86
-
-If your architecture is not supported, you need to select
-HAVE_GENERIC_BOARD in arch/Kconfig
-and test it with a suitable board, as follows.
-
-
-Adding Support for your Board
------------------------------
-
-To enable generic board for your board, define CONFIG_SYS_GENERIC_BOARD in
-your board config header file.
-
-Test that U-Boot still functions correctly on your board, and fix any
-problems you find. Don't be surprised if there are no problems - generic
-board has had a reasonable amount of testing with common boards.
-
-
-DeadLine
---------
-
-Please don't take this the wrong way - there is no intent to make your life
-miserable, and we have the greatest respect and admiration for U-Boot users.
-However, with any migration there has to be a period where the old way is
-deprecated and removed. Every patch to the deprecated code introduces a
-potential breakage in the new unused code. Therefore:
-
-Boards or architectures not converted over to general board by the
-end of 2014 may be forcibly changed over (potentially causing run-time
-breakage) or removed.
-
-
-
Further Background
------------------
Simon Glass, sjg@chromium.org
March 2014
+Updated after final removal, May 2016
--- /dev/null
+README on how boot images are created for secure TI devices
+
+CONFIG_TI_SECURE_DEVICE:
+Secure TI devices require a boot image that is authenticated by ROM
+code to function. Without this, even JTAG remains locked and the
+device is essentially useless. In order to create a valid boot image for
+a secure device from TI, the initial public software image must be signed
+and combined with various headers, certificates, and other binary images.
+
+Information on the details on the complete boot image format can be obtained
+from Texas Instruments. The tools used to generate boot images for secure
+devices are part of a secure development package (SECDEV) that can be
+downloaded from:
+
+ http://www.ti.com/mysecuresoftware (login required)
+
+The secure development package is access controlled due to NDA and export
+control restrictions. Access must be requested and granted by TI before the
+package is viewable and downloadable. Contact TI, either online or by way
+of a local TI representative, to request access.
+
+When CONFIG_TI_SECURE_DEVICE is set, the U-Boot SPL build process requires
+the presence and use of these tools in order to create a viable boot image.
+The build process will look for the environment variable TI_SECURE_DEV_PKG,
+which should be the path of the installed SECDEV package. If the
+TI_SECURE_DEV_PKG variable is not defined or if it is defined but doesn't
+point to a valid SECDEV package, a warning is issued during the build to
+indicate that a final secure bootable image was not created.
+
+Within the SECDEV package exists an image creation script:
+
+${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
+
+This is called as part of the SPL/u-boot build process. As the secure boot
+image formats and requirements differ between secure SOC from TI, the
+purpose of this script is to abstract these details as much as possible.
+
+The script is basically the only required interface to the TI SECDEV package
+for secure TI devices.
+
+Invoking the script for AM43xx Secure Devices
+=============================================
+
+create-boot-image.sh <IMAGE_FLAG> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR>
+
+<IMAGE_FLAG> is a value that specifies the type of the image to generate OR
+the action the image generation tool will take. Valid values are:
+ SPI_X-LOADER - Generates an image for SPI flash (byte swapped)
+ XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
+ ISSW - Generates an image for all other boot modes
+
+<INPUT_FILE> is the full path and filename of the public world boot loader
+binary file (depending on the boot media, this is usually either
+u-boot-spl.bin or u-boot.bin).
+
+<OUTPUT_FILE> is the full path and filename of the final secure image. The
+output binary images should be used in place of the standard non-secure
+binary images (see the platform-specific user's guides and releases notes
+for how the non-secure images are typically used)
+ u-boot-spl_HS_SPI_X-LOADER - byte swapped boot image for SPI flash
+ u-boot_HS_XIP_X-LOADER - boot image for NOR or QSPI flash
+ u-boot-spl_HS_ISSW - boot image for all other boot media
+
+<SPL_LOAD_ADDR> is the address at which SOC ROM should load the <INPUT_FILE>
+
+Invoking the script for DRA7xx/AM57xx Secure Devices
+====================================================
+
+create-boot-image.sh <IMAGE_TYPE> <INPUT_FILE> <OUTPUT_FILE>
+
+<IMAGE_TYPE> is a value that specifies the type of the image to generate OR
+the action the image generation tool will take. Valid values are:
+ X-LOADER - Generates an image for NOR or QSPI boot modes
+ MLO - Generates an image for SD/MMC/eMMC boot modes
+ ULO - Generates an image for USB/UART peripheral boot modes
+ Note: ULO is not yet used by the u-boot build process
+
+<INPUT_FILE> is the full path and filename of the public world boot loader
+binary file (for this platform, this is always u-boot-spl.bin).
+
+<OUTPUT_FILE> is the full path and filename of the final secure image. The
+output binary images should be used in place of the standard non-secure
+binary images (see the platform-specific user's guides and releases notes
+for how the non-secure images are typically used)
+ u-boot-spl_HS_MLO - boot image for SD/MMC/eMMC. This image is
+ copied to a file named MLO, which is the name that
+ the device ROM bootloader requires for loading from
+ the FAT partition of an SD card (same as on
+ non-secure devices)
+ u-boot-spl_HS_X-LOADER - boot image for all other flash memories
+ including QSPI and NOR flash
--- /dev/null
+* Generic Mailbox Controller and client driver bindings
+
+Generic binding to provide a way for Mailbox controller drivers to
+assign appropriate mailbox channel to client drivers.
+
+* Mailbox Controller
+
+Required property:
+- #mbox-cells: Must be at least 1. Number of cells in a mailbox
+ specifier.
+
+Example:
+ mailbox: mailbox {
+ ...
+ #mbox-cells = <1>;
+ };
+
+
+* Mailbox Client
+
+Required property:
+- mboxes: List of phandle and mailbox channel specifiers.
+
+Optional property:
+- mbox-names: List of identifier strings for each mailbox channel.
+
+Example:
+ pwr_cntrl: power {
+ ...
+ mbox-names = "pwr-ctrl", "rpc";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ };
1. Bind stage
-A device and its driver are bound using one of these two methods:
+U-Boot discovers devices using one of these two methods:
- - Scan the U_BOOT_DEVICE() definitions. U-Boot It looks up the
-name specified by each, to find the appropriate driver. It then calls
-device_bind() to create a new device and bind' it to its driver. This will
-call the device's bind() method.
+ - Scan the U_BOOT_DEVICE() definitions. U-Boot looks up the name specified
+by each, to find the appropriate U_BOOT_DRIVER() definition. In this case,
+there is no path by which driver_data may be provided, but the U_BOOT_DEVICE()
+may provide platdata.
- Scan through the device tree definitions. U-Boot looks at top-level
nodes in the the device tree. It looks at the compatible string in each node
-and uses the of_match part of the U_BOOT_DRIVER() structure to find the
-right driver for each node. It then calls device_bind() to bind the
-newly-created device to its driver (thereby creating a device structure).
-This will also call the device's bind() method.
+and uses the of_match table of the U_BOOT_DRIVER() structure to find the
+right driver for each node. In this case, the of_match table may provide a
+driver_data value, but platdata cannot be provided until later.
+
+For each device that is discovered, U-Boot then calls device_bind() to create a
+new device, initializes various core fields of the device object such as name,
+uclass & driver, initializes any optional fields of the device object that are
+applicable such as of_offset, driver_data & platdata, and finally calls the
+driver's bind() method if one is defined.
At this point all the devices are known, and bound to their drivers. There
is a 'struct udevice' allocated for all devices. However, nothing has been
source "drivers/led/Kconfig"
+source "drivers/mailbox/Kconfig"
+
source "drivers/memory/Kconfig"
source "drivers/misc/Kconfig"
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
obj-$(CONFIG_U_QE) += qe/
+obj-y += mailbox/
obj-y += memory/
obj-y += pwm/
obj-y += input/
}
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev);
+ ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev);
if (ret)
debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
return 0;
}
+static int rockchip_mac_set_clk(struct rk3288_cru *cru,
+ int periph, uint freq)
+{
+ /* Assuming mac_clk is fed by an external clock */
+ rk_clrsetreg(&cru->cru_clksel_con[21],
+ RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
+ RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+
+ return 0;
+}
+
static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
int periph, unsigned int rate_hz)
{
new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
break;
#ifndef CONFIG_SPL_BUILD
+ case SCLK_MAC:
+ new_rate = rockchip_mac_set_clk(priv->cru, periph, rate);
+ break;
case DCLK_VOP0:
case DCLK_VOP1:
new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
}
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
+ ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
if (ret)
debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
DECLARE_GLOBAL_DATA_PTR;
-int device_bind(struct udevice *parent, const struct driver *drv,
- const char *name, void *platdata, int of_offset,
- struct udevice **devp)
+static int device_bind_common(struct udevice *parent, const struct driver *drv,
+ const char *name, void *platdata,
+ ulong driver_data, int of_offset,
+ struct udevice **devp)
{
struct udevice *dev;
struct uclass *uc;
INIT_LIST_HEAD(&dev->devres_head);
#endif
dev->platdata = platdata;
+ dev->driver_data = driver_data;
dev->name = name;
dev->of_offset = of_offset;
dev->parent = parent;
return ret;
}
+int device_bind_with_driver_data(struct udevice *parent,
+ const struct driver *drv, const char *name,
+ ulong driver_data, int of_offset,
+ struct udevice **devp)
+{
+ return device_bind_common(parent, drv, name, NULL, driver_data,
+ of_offset, devp);
+}
+
+int device_bind(struct udevice *parent, const struct driver *drv,
+ const char *name, void *platdata, int of_offset,
+ struct udevice **devp)
+{
+ return device_bind_common(parent, drv, name, platdata, 0, of_offset,
+ devp);
+}
+
int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
const struct driver_info *info, struct udevice **devp)
{
}
dm_dbg(" - found match at '%s'\n", entry->name);
- ret = device_bind(parent, entry, name, NULL, offset, &dev);
+ ret = device_bind_with_driver_data(parent, entry, name,
+ id->data, offset, &dev);
if (ret == -ENODEV) {
dm_dbg("Driver '%s' refuses to bind\n", entry->name);
continue;
ret);
return ret;
} else {
- dev->driver_data = id->data;
found = true;
if (devp)
*devp = dev;
*
* TODO:
* 1. Support PCA957X_TYPE
- * 2. Support max 40 gpio pins
- * 3. Support Plolarity Inversion
+ * 2. Support 24 gpio pins
+ * 3. Support Polarity Inversion
*/
#include <common.h>
PCA953X_DIRECTION_OUT,
};
-#define MAX_BANK 3
+#define MAX_BANK 5
#define BANK_SZ 8
DECLARE_GLOBAL_DATA_PTR;
ret = dm_i2c_read(dev, reg, val, 1);
} else if (info->gpio_count <= 16) {
ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
+ } else if (info->gpio_count == 40) {
+ /* Auto increment */
+ ret = dm_i2c_read(dev, (reg << 3) | 0x80, val, info->bank_count);
} else {
dev_err(dev, "Unsupported now\n");
return -EINVAL;
return 0;
}
+
+struct sunxi_gpio_soc_data {
+ int start;
+ int no_banks;
+};
+
/**
* We have a top-level GPIO device with no actual GPIOs. It has a child
* device for each Sunxi bank.
*/
static int gpio_sunxi_bind(struct udevice *parent)
{
+ struct sunxi_gpio_soc_data *soc_data =
+ (struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
struct sunxi_gpio_platdata *plat = parent->platdata;
struct sunxi_gpio_reg *ctlr;
- int bank, no_banks, ret, start;
+ int bank, ret;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
- if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun6i-a31-r-pinctrl") == 0) {
- start = 'L' - 'A';
- no_banks = 2; /* L & M */
- } else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun8i-a23-r-pinctrl") == 0 ||
- fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun8i-a83t-r-pinctrl") == 0 ||
- fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun8i-h3-r-pinctrl") == 0) {
- start = 'L' - 'A';
- no_banks = 1; /* L only */
- } else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun9i-a80-r-pinctrl") == 0) {
- start = 'L' - 'A';
- no_banks = 3; /* L, M & N */
- } else {
- start = 0;
- no_banks = SUNXI_GPIO_BANKS;
- }
-
ctlr = (struct sunxi_gpio_reg *)dev_get_addr(parent);
- for (bank = 0; bank < no_banks; bank++) {
+ for (bank = 0; bank < soc_data->no_banks; bank++) {
struct sunxi_gpio_platdata *plat;
struct udevice *dev;
if (!plat)
return -ENOMEM;
plat->regs = &ctlr->gpio_bank[bank];
- plat->bank_name = gpio_bank_name(start + bank);
+ plat->bank_name = gpio_bank_name(soc_data->start + bank);
plat->gpio_count = SUNXI_GPIOS_PER_BANK;
ret = device_bind(parent, parent->driver,
return 0;
}
+static const struct sunxi_gpio_soc_data soc_data_a_all = {
+ .start = 0,
+ .no_banks = SUNXI_GPIO_BANKS,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_1 = {
+ .start = 'L' - 'A',
+ .no_banks = 1,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_2 = {
+ .start = 'L' - 'A',
+ .no_banks = 2,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_3 = {
+ .start = 'L' - 'A',
+ .no_banks = 3,
+};
+
+#define ID(_compat_, _soc_data_) \
+ { .compatible = _compat_, .data = (ulong)&soc_data_##_soc_data_ }
+
static const struct udevice_id sunxi_gpio_ids[] = {
- { .compatible = "allwinner,sun4i-a10-pinctrl" },
- { .compatible = "allwinner,sun5i-a10s-pinctrl" },
- { .compatible = "allwinner,sun5i-a13-pinctrl" },
- { .compatible = "allwinner,sun6i-a31-pinctrl" },
- { .compatible = "allwinner,sun6i-a31s-pinctrl" },
- { .compatible = "allwinner,sun7i-a20-pinctrl" },
- { .compatible = "allwinner,sun8i-a23-pinctrl" },
- { .compatible = "allwinner,sun8i-a33-pinctrl" },
- { .compatible = "allwinner,sun8i-a83t-pinctrl", },
- { .compatible = "allwinner,sun8i-h3-pinctrl" },
- { .compatible = "allwinner,sun9i-a80-pinctrl" },
- { .compatible = "allwinner,sun6i-a31-r-pinctrl" },
- { .compatible = "allwinner,sun8i-a23-r-pinctrl" },
- { .compatible = "allwinner,sun8i-a83t-r-pinctrl" },
- { .compatible = "allwinner,sun8i-h3-r-pinctrl", },
- { .compatible = "allwinner,sun9i-a80-r-pinctrl", },
+ ID("allwinner,sun4i-a10-pinctrl", a_all),
+ ID("allwinner,sun5i-a10s-pinctrl", a_all),
+ ID("allwinner,sun5i-a13-pinctrl", a_all),
+ ID("allwinner,sun6i-a31-pinctrl", a_all),
+ ID("allwinner,sun6i-a31s-pinctrl", a_all),
+ ID("allwinner,sun7i-a20-pinctrl", a_all),
+ ID("allwinner,sun8i-a23-pinctrl", a_all),
+ ID("allwinner,sun8i-a33-pinctrl", a_all),
+ ID("allwinner,sun8i-a83t-pinctrl", a_all),
+ ID("allwinner,sun8i-h3-pinctrl", a_all),
+ ID("allwinner,sun9i-a80-pinctrl", a_all),
+ ID("allwinner,sun6i-a31-r-pinctrl", l_2),
+ ID("allwinner,sun8i-a23-r-pinctrl", l_1),
+ ID("allwinner,sun8i-a83t-r-pinctrl", l_1),
+ ID("allwinner,sun8i-h3-r-pinctrl", l_1),
+ ID("allwinner,sun9i-a80-r-pinctrl", l_3),
{ }
};
--- /dev/null
+menu "Mailbox Controller Support"
+
+config DM_MAILBOX
+ bool "Enable mailbox controllers using Driver Model"
+ depends on DM && OF_CONTROL
+ help
+ Enable support for the mailbox driver class. Mailboxes provide the
+ ability to transfer small messages and/or notifications from one
+ CPU to another CPU, or sometimes to dedicated HW modules. They form
+ the basis of a variety of inter-process/inter-CPU communication
+ protocols.
+
+config SANDBOX_MBOX
+ bool "Enable the sandbox mailbox test driver"
+ depends on DM_MAILBOX && SANDBOX
+ help
+ Enable support for a test mailbox implementation, which simply echos
+ back a modified version of any message that is sent.
+
+endmenu
--- /dev/null
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_DM_MAILBOX) += mailbox-uclass.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <mailbox_client.h>
+#include <mailbox_uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline struct mbox_ops *mbox_dev_ops(struct udevice *dev)
+{
+ return (struct mbox_ops *)dev->driver->ops;
+}
+
+static int mbox_of_xlate_default(struct mbox_chan *chan,
+ struct fdtdec_phandle_args *args)
+{
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ if (args->args_count != 1) {
+ debug("Invaild args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ chan->id = args->args[0];
+
+ return 0;
+}
+
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan)
+{
+ struct fdtdec_phandle_args args;
+ int ret;
+ struct udevice *dev_mbox;
+ struct mbox_ops *ops;
+
+ debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan);
+
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ "mboxes", "#mbox-cells", 0,
+ index, &args);
+ if (ret) {
+ debug("%s: fdtdec_parse_phandle_with_args failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MAILBOX, args.node,
+ &dev_mbox);
+ if (ret) {
+ debug("%s: uclass_get_device_by_of_offset failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ ops = mbox_dev_ops(dev_mbox);
+
+ chan->dev = dev_mbox;
+ if (ops->of_xlate)
+ ret = ops->of_xlate(chan, &args);
+ else
+ ret = mbox_of_xlate_default(chan, &args);
+ if (ret) {
+ debug("of_xlate() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = ops->request(chan);
+ if (ret) {
+ debug("ops->request() failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int mbox_get_by_name(struct udevice *dev, const char *name,
+ struct mbox_chan *chan)
+{
+ int index;
+
+ debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan);
+
+ index = fdt_find_string(gd->fdt_blob, dev->of_offset, "mbox-names",
+ name);
+ if (index < 0) {
+ debug("fdt_find_string() failed: %d\n", index);
+ return index;
+ }
+
+ return mbox_get_by_index(dev, index, chan);
+}
+
+int mbox_free(struct mbox_chan *chan)
+{
+ struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ return ops->free(chan);
+}
+
+int mbox_send(struct mbox_chan *chan, const void *data)
+{
+ struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ return ops->send(chan, data);
+}
+
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us)
+{
+ struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+ ulong start_time;
+ int ret;
+
+ debug("%s(chan=%p, data=%p, timeout_us=%ld)\n", __func__, chan, data,
+ timeout_us);
+
+ start_time = timer_get_us();
+ /*
+ * Account for partial us ticks, but if timeout_us is 0, ensure we
+ * still don't wait at all.
+ */
+ if (timeout_us)
+ timeout_us++;
+
+ for (;;) {
+ ret = ops->recv(chan, data);
+ if (ret != -ENODATA)
+ return ret;
+ if ((timer_get_us() - start_time) >= timeout_us)
+ return -ETIMEDOUT;
+ }
+}
+
+UCLASS_DRIVER(mailbox) = {
+ .id = UCLASS_MAILBOX,
+ .name = "mailbox",
+};
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox_client.h>
+#include <asm/io.h>
+
+struct sandbox_mbox_test {
+ struct mbox_chan chan;
+};
+
+int sandbox_mbox_test_get(struct udevice *dev)
+{
+ struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+ return mbox_get_by_name(dev, "test", &sbmt->chan);
+}
+
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg)
+{
+ struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+ return mbox_send(&sbmt->chan, &msg);
+}
+
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg)
+{
+ struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+ return mbox_recv(&sbmt->chan, msg, 100);
+}
+
+int sandbox_mbox_test_free(struct udevice *dev)
+{
+ struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+ return mbox_free(&sbmt->chan);
+}
+
+static const struct udevice_id sandbox_mbox_test_ids[] = {
+ { .compatible = "sandbox,mbox-test" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_mbox_test) = {
+ .name = "sandbox_mbox_test",
+ .id = UCLASS_MISC,
+ .of_match = sandbox_mbox_test_ids,
+ .priv_auto_alloc_size = sizeof(struct sandbox_mbox_test),
+};
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox_uclass.h>
+#include <asm/io.h>
+#include <asm/mbox.h>
+
+#define SANDBOX_MBOX_CHANNELS 2
+
+struct sandbox_mbox_chan {
+ bool rx_msg_valid;
+ uint32_t rx_msg;
+};
+
+struct sandbox_mbox {
+ struct sandbox_mbox_chan chans[SANDBOX_MBOX_CHANNELS];
+};
+
+static int sandbox_mbox_request(struct mbox_chan *chan)
+{
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ if (chan->id >= SANDBOX_MBOX_CHANNELS)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int sandbox_mbox_free(struct mbox_chan *chan)
+{
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ return 0;
+}
+
+static int sandbox_mbox_send(struct mbox_chan *chan, const void *data)
+{
+ struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+ const uint32_t *pmsg = data;
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ sbm->chans[chan->id].rx_msg = *pmsg ^ SANDBOX_MBOX_PING_XOR;
+ sbm->chans[chan->id].rx_msg_valid = true;
+
+ return 0;
+}
+
+static int sandbox_mbox_recv(struct mbox_chan *chan, void *data)
+{
+ struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+ uint32_t *pmsg = data;
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ if (!sbm->chans[chan->id].rx_msg_valid)
+ return -ENODATA;
+
+ *pmsg = sbm->chans[chan->id].rx_msg;
+ sbm->chans[chan->id].rx_msg_valid = false;
+
+ return 0;
+}
+
+static int sandbox_mbox_bind(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+static int sandbox_mbox_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+static const struct udevice_id sandbox_mbox_ids[] = {
+ { .compatible = "sandbox,mbox" },
+ { }
+};
+
+struct mbox_ops sandbox_mbox_mbox_ops = {
+ .request = sandbox_mbox_request,
+ .free = sandbox_mbox_free,
+ .send = sandbox_mbox_send,
+ .recv = sandbox_mbox_recv,
+};
+
+U_BOOT_DRIVER(sandbox_mbox) = {
+ .name = "sandbox_mbox",
+ .id = UCLASS_MAILBOX,
+ .of_match = sandbox_mbox_ids,
+ .bind = sandbox_mbox_bind,
+ .probe = sandbox_mbox_probe,
+ .priv_auto_alloc_size = sizeof(struct sandbox_mbox),
+ .ops = &sandbox_mbox_mbox_ops,
+};
help
The I2C address of the PCA9551 LED controller.
-config RESET
- bool "Enable support for reset drivers"
+config SYSRESET
+ bool "Enable support for system reset drivers"
depends on DM
help
- Enable reset drivers which can be used to reset the CPU or board.
- Each driver can provide a reset method which will be called to
- effect a reset. The uclass will try all available drivers when
+ Enable system reset drivers which can be used to reset the CPU or
+ board. Each driver can provide a reset method which will be called
+ to effect a reset. The uclass will try all available drivers when
reset_walk() is called.
config WINBOND_W83627
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_PDSP188x) += pdsp188x.o
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
-obj-$(CONFIG_SANDBOX) += reset_sandbox.o
+obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
ifdef CONFIG_DM_I2C
obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
endif
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
-obj-$(CONFIG_RESET) += reset-uclass.o
+obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
obj-$(CONFIG_QFW) += qfw.o
+++ /dev/null
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <reset.h>
-#include <asm/state.h>
-#include <asm/test.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int sandbox_warm_reset_request(struct udevice *dev, enum reset_t type)
-{
- struct sandbox_state *state = state_get_current();
-
- switch (type) {
- case RESET_WARM:
- state->last_reset = type;
- break;
- default:
- return -ENOSYS;
- }
- if (!state->reset_allowed[type])
- return -EACCES;
-
- return -EINPROGRESS;
-}
-
-static int sandbox_reset_request(struct udevice *dev, enum reset_t type)
-{
- struct sandbox_state *state = state_get_current();
-
- /*
- * If we have a device tree, the device we created from platform data
- * (see the U_BOOT_DEVICE() declaration below) should not do anything.
- * If we are that device, return an error.
- */
- if (state->fdt_fname && dev->of_offset == -1)
- return -ENODEV;
-
- switch (type) {
- case RESET_COLD:
- state->last_reset = type;
- break;
- case RESET_POWER:
- state->last_reset = type;
- if (!state->reset_allowed[type])
- return -EACCES;
- sandbox_exit();
- break;
- default:
- return -ENOSYS;
- }
- if (!state->reset_allowed[type])
- return -EACCES;
-
- return -EINPROGRESS;
-}
-
-static struct reset_ops sandbox_reset_ops = {
- .request = sandbox_reset_request,
-};
-
-static const struct udevice_id sandbox_reset_ids[] = {
- { .compatible = "sandbox,reset" },
- { }
-};
-
-U_BOOT_DRIVER(reset_sandbox) = {
- .name = "reset_sandbox",
- .id = UCLASS_RESET,
- .of_match = sandbox_reset_ids,
- .ops = &sandbox_reset_ops,
-};
-
-static struct reset_ops sandbox_warm_reset_ops = {
- .request = sandbox_warm_reset_request,
-};
-
-static const struct udevice_id sandbox_warm_reset_ids[] = {
- { .compatible = "sandbox,warm-reset" },
- { }
-};
-
-U_BOOT_DRIVER(warm_reset_sandbox) = {
- .name = "warm_reset_sandbox",
- .id = UCLASS_RESET,
- .of_match = sandbox_warm_reset_ids,
- .ops = &sandbox_warm_reset_ops,
-};
-
-/* This is here in case we don't have a device tree */
-U_BOOT_DEVICE(reset_sandbox_non_fdt) = {
- .name = "reset_sandbox",
-};
*/
#include <common.h>
-#include <reset.h>
+#include <sysreset.h>
#include <dm.h>
#include <errno.h>
#include <regmap.h>
#include <dm/root.h>
#include <linux/err.h>
-int reset_request(struct udevice *dev, enum reset_t type)
+int sysreset_request(struct udevice *dev, enum sysreset_t type)
{
- struct reset_ops *ops = reset_get_ops(dev);
+ struct sysreset_ops *ops = sysreset_get_ops(dev);
if (!ops->request)
return -ENOSYS;
return ops->request(dev, type);
}
-int reset_walk(enum reset_t type)
+int sysreset_walk(enum sysreset_t type)
{
struct udevice *dev;
int ret = -ENOSYS;
- while (ret != -EINPROGRESS && type < RESET_COUNT) {
- for (uclass_first_device(UCLASS_RESET, &dev);
+ while (ret != -EINPROGRESS && type < SYSRESET_COUNT) {
+ for (uclass_first_device(UCLASS_SYSRESET, &dev);
dev;
uclass_next_device(&dev)) {
- ret = reset_request(dev, type);
+ ret = sysreset_request(dev, type);
if (ret == -EINPROGRESS)
break;
}
return ret;
}
-void reset_walk_halt(enum reset_t type)
+void sysreset_walk_halt(enum sysreset_t type)
{
int ret;
- ret = reset_walk(type);
+ ret = sysreset_walk(type);
/* Wait for the reset to take effect */
if (ret == -EINPROGRESS)
mdelay(100);
/* Still no reset? Give up */
- printf("Reset not supported on this platform\n");
+ debug("System reset not supported on this platform\n");
hang();
}
/**
- * reset_cpu() - calls reset_walk(RESET_WARM)
+ * reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
*/
void reset_cpu(ulong addr)
{
- reset_walk_halt(RESET_WARM);
+ sysreset_walk_halt(SYSRESET_WARM);
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- reset_walk_halt(RESET_WARM);
+ sysreset_walk_halt(SYSRESET_WARM);
return 0;
}
-UCLASS_DRIVER(reset) = {
- .id = UCLASS_RESET,
- .name = "reset",
+UCLASS_DRIVER(sysreset) = {
+ .id = UCLASS_SYSRESET,
+ .name = "sysreset",
};
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/state.h>
+#include <asm/test.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_warm_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ struct sandbox_state *state = state_get_current();
+
+ switch (type) {
+ case SYSRESET_WARM:
+ state->last_sysreset = type;
+ break;
+ default:
+ return -ENOSYS;
+ }
+ if (!state->sysreset_allowed[type])
+ return -EACCES;
+
+ return -EINPROGRESS;
+}
+
+static int sandbox_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct sandbox_state *state = state_get_current();
+
+ /*
+ * If we have a device tree, the device we created from platform data
+ * (see the U_BOOT_DEVICE() declaration below) should not do anything.
+ * If we are that device, return an error.
+ */
+ if (state->fdt_fname && dev->of_offset == -1)
+ return -ENODEV;
+
+ switch (type) {
+ case SYSRESET_COLD:
+ state->last_sysreset = type;
+ break;
+ case SYSRESET_POWER:
+ state->last_sysreset = type;
+ if (!state->sysreset_allowed[type])
+ return -EACCES;
+ sandbox_exit();
+ break;
+ default:
+ return -ENOSYS;
+ }
+ if (!state->sysreset_allowed[type])
+ return -EACCES;
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops sandbox_sysreset_ops = {
+ .request = sandbox_sysreset_request,
+};
+
+static const struct udevice_id sandbox_sysreset_ids[] = {
+ { .compatible = "sandbox,reset" },
+ { }
+};
+
+U_BOOT_DRIVER(sysreset_sandbox) = {
+ .name = "sysreset_sandbox",
+ .id = UCLASS_SYSRESET,
+ .of_match = sandbox_sysreset_ids,
+ .ops = &sandbox_sysreset_ops,
+};
+
+static struct sysreset_ops sandbox_warm_sysreset_ops = {
+ .request = sandbox_warm_sysreset_request,
+};
+
+static const struct udevice_id sandbox_warm_sysreset_ids[] = {
+ { .compatible = "sandbox,warm-reset" },
+ { }
+};
+
+U_BOOT_DRIVER(warm_sysreset_sandbox) = {
+ .name = "warm_sysreset_sandbox",
+ .id = UCLASS_SYSRESET,
+ .of_match = sandbox_warm_sysreset_ids,
+ .ops = &sandbox_warm_sysreset_ops,
+};
+
+/* This is here in case we don't have a device tree */
+U_BOOT_DEVICE(sysreset_sandbox_non_fdt) = {
+ .name = "sysreset_sandbox",
+};
.init = dwmci_init,
};
-int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+ uint caps, u32 max_clk, u32 min_clk)
{
- host->cfg.name = host->name;
- host->cfg.ops = &dwmci_ops;
- host->cfg.f_min = min_clk;
- host->cfg.f_max = max_clk;
+ cfg->name = name;
+ cfg->ops = &dwmci_ops;
+ cfg->f_min = min_clk;
+ cfg->f_max = max_clk;
- host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- host->cfg.host_caps = host->caps;
+ cfg->host_caps = caps;
- if (host->buswidth == 8) {
- host->cfg.host_caps |= MMC_MODE_8BIT;
- host->cfg.host_caps &= ~MMC_MODE_4BIT;
+ if (buswidth == 8) {
+ cfg->host_caps |= MMC_MODE_8BIT;
+ cfg->host_caps &= ~MMC_MODE_4BIT;
} else {
- host->cfg.host_caps |= MMC_MODE_4BIT;
- host->cfg.host_caps &= ~MMC_MODE_8BIT;
+ cfg->host_caps |= MMC_MODE_4BIT;
+ cfg->host_caps &= ~MMC_MODE_8BIT;
}
- host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+ cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+}
- host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+#ifdef CONFIG_BLK
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+{
+ return mmc_bind(dev, mmc, cfg);
+}
+#else
+int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+{
+ dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
+ max_clk, min_clk);
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL)
return 0;
}
+#endif
/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
* to platforms without floating point.
*/
-static const int multipliers[] = {
+static const u8 multipliers[] = {
0, /* reserved */
10,
12,
return 0;
}
-/* not used any more */
-int __deprecated mmc_register(struct mmc *mmc)
-{
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("%s is deprecated! use mmc_create() instead.\n", __func__);
-#endif
- return -1;
-}
-
#ifdef CONFIG_BLK
int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
{
bdesc->removable = 1;
/* setup initial part type */
- bdesc->part_type = mmc->cfg->part_type;
+ bdesc->part_type = cfg->part_type;
mmc->dev = dev;
return 0;
/* SPL will never write or erase, declare dummies to reduce code size. */
+#ifdef CONFIG_BLK
+static inline unsigned long mmc_berase(struct udevice *dev,
+ lbaint_t start, lbaint_t blkcnt)
+{
+ return 0;
+}
+
+static inline ulong mmc_bwrite(struct udevice *dev, lbaint_t start,
+ lbaint_t blkcnt, const void *src)
+{
+ return 0;
+}
+#else
static inline unsigned long mmc_berase(struct blk_desc *block_dev,
lbaint_t start, lbaint_t blkcnt)
{
{
return 0;
}
+#endif
#endif /* CONFIG_SPL_BUILD */
DECLARE_GLOBAL_DATA_PTR;
+struct rockchip_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
struct rockchip_dwmmc_priv {
struct udevice *clk;
int periph;
static int rockchip_dwmmc_probe(struct udevice *dev)
{
+#ifdef CONFIG_BLK
+ struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+#endif
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
return ret;
}
#endif
+#ifdef CONFIG_BLK
+ dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
+ minmax[1], minmax[0]);
+ host->mmc = &plat->mmc;
+#else
ret = add_dwmci(host, minmax[1], minmax[0]);
if (ret)
return ret;
+#endif
+ host->mmc->priv = &priv->host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
return 0;
}
+static int rockchip_dwmmc_bind(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+ struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+
static const struct udevice_id rockchip_dwmmc_ids[] = {
{ .compatible = "rockchip,rk3288-dw-mshc" },
{ }
.id = UCLASS_MMC,
.of_match = rockchip_dwmmc_ids,
.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
+ .bind = rockchip_dwmmc_bind,
.probe = rockchip_dwmmc_probe,
.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
+ .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
};
#ifdef CONFIG_PWRSEQ
int trans_bytes = 0, is_aligned = 1;
u32 mask, flags, mode;
unsigned int time = 0, start_addr = 0;
- int mmc_dev = mmc->block_dev.devnum;
+ int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
unsigned start = get_timer(0);
/* Timeout unit - ms */
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
{
unsigned int block, lastblock;
- unsigned int page;
+ unsigned int page, page_offset;
/*
* offs has to be aligned to a page address!
block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+ page_offset = offs % CONFIG_SYS_NAND_PAGE_SIZE;
while (block <= lastblock) {
if (!nand_is_bad_block(block)) {
*/
while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
nand_read_page(block, page, dst);
+ /*
+ * When offs is not aligned to page address the
+ * extra offset is copied to dst as well. Copy
+ * the image such that its first byte will be
+ * at the dst.
+ */
+ if (unlikely(page_offset)) {
+ memmove(dst, dst + page_offset,
+ CONFIG_SYS_NAND_PAGE_SIZE);
+ dst = (void *)((int)dst - page_offset);
+ page_offset = 0;
+ }
dst += CONFIG_SYS_NAND_PAGE_SIZE;
page++;
}
}
#endif
+static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ struct spi_flash *flash = load->dev;
+ ulong ret;
+
+ ret = spi_flash_read(flash, sector, count, buf);
+ if (!ret)
+ return count;
+ else
+ return 0;
+}
/*
* The main entry for SPI booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
if (err)
return err;
- err = spl_parse_image_header(header);
- if (err)
- return err;
- err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
- spl_image.size, (void *)spl_image.load_addr);
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
+ struct spl_load_info load;
+
+ debug("Found FIT\n");
+ load.dev = flash;
+ load.priv = NULL;
+ load.filename = NULL;
+ load.bl_len = 1;
+ load.read = spl_spi_fit_read;
+ err = spl_load_simple_fit(&load,
+ CONFIG_SYS_SPI_U_BOOT_OFFS,
+ header);
+ } else {
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
+ err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+ spl_image.size,
+ (void *)spl_image.load_addr);
+ }
}
return err;
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
+#ifdef CONFIG_DM_ETH
+ struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
struct eth_mac_regs *mac_p = bus->priv;
+#endif
ulong start;
u16 miiaddr;
int timeout = CONFIG_MDIO_TIMEOUT;
static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 val)
{
+#ifdef CONFIG_DM_ETH
+ struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
struct eth_mac_regs *mac_p = bus->priv;
+#endif
ulong start;
u16 miiaddr;
int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
return ret;
}
-static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
+#if CONFIG_DM_ETH
+static int dw_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+ struct dw_eth_dev *priv = dev_get_priv(dev);
+ struct dw_eth_pdata *pdata = dev_get_platdata(dev);
+ int ret;
+
+ if (!dm_gpio_is_valid(&priv->reset_gpio))
+ return 0;
+
+ /* reset the phy */
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[0]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[1]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[2]);
+
+ return 0;
+}
+#endif
+
+static int dw_mdio_init(const char *name, void *priv)
{
struct mii_dev *bus = mdio_alloc();
bus->read = dw_mdio_read;
bus->write = dw_mdio_write;
snprintf(bus->name, sizeof(bus->name), "%s", name);
+#ifdef CONFIG_DM_ETH
+ bus->reset = dw_mdio_reset;
+#endif
- bus->priv = (void *)mac_regs_p;
+ bus->priv = priv;
return mdio_register(bus);
}
for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
- desc_p->dmamac_next = &desc_table_p[idx + 1];
+ desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
}
/* Correcting the last pointer of the chain */
- desc_p->dmamac_next = &desc_table_p[0];
+ desc_p->dmamac_next = (ulong)&desc_table_p[0];
/* Flush all Tx buffer descriptors at once */
- flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
- (unsigned int)priv->tx_mac_descrtable +
+ flush_dcache_range((ulong)priv->tx_mac_descrtable,
+ (ulong)priv->tx_mac_descrtable +
sizeof(priv->tx_mac_descrtable));
writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
* Otherwise there's a chance to get some of them flushed in RAM when
* GMAC is already pushing data to RAM via DMA. This way incoming from
* GMAC data will be corrupted. */
- flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
- RX_TOTAL_BUFSIZE);
+ flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
- desc_p->dmamac_next = &desc_table_p[idx + 1];
+ desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
desc_p->dmamac_cntl =
(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
}
/* Correcting the last pointer of the chain */
- desc_p->dmamac_next = &desc_table_p[0];
+ desc_p->dmamac_next = (ulong)&desc_table_p[0];
/* Flush all Rx buffer descriptors at once */
- flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
- (unsigned int)priv->rx_mac_descrtable +
+ flush_dcache_range((ulong)priv->rx_mac_descrtable,
+ (ulong)priv->rx_mac_descrtable +
sizeof(priv->rx_mac_descrtable));
writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 desc_num = priv->tx_currdescnum;
struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
- uint32_t desc_start = (uint32_t)desc_p;
- uint32_t desc_end = desc_start +
+ ulong desc_start = (ulong)desc_p;
+ ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
- uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
- uint32_t data_end = data_start +
- roundup(length, ARCH_DMA_MINALIGN);
+ ulong data_start = desc_p->dmamac_addr;
+ ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
/*
* Strictly we only need to invalidate the "txrx_status" field
* for the following check, but on some platforms we cannot
return -EPERM;
}
- memcpy(desc_p->dmamac_addr, packet, length);
+ memcpy((void *)data_start, packet, length);
/* Flush data to be sent */
flush_dcache_range(data_start, data_end);
u32 status, desc_num = priv->rx_currdescnum;
struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
int length = -EAGAIN;
- uint32_t desc_start = (uint32_t)desc_p;
- uint32_t desc_end = desc_start +
+ ulong desc_start = (ulong)desc_p;
+ ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
- uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
- uint32_t data_end;
+ ulong data_start = desc_p->dmamac_addr;
+ ulong data_end;
/* Invalidate entire buffer descriptor */
invalidate_dcache_range(desc_start, desc_end);
/* Invalidate received data */
data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
invalidate_dcache_range(data_start, data_end);
- *packetp = desc_p->dmamac_addr;
+ *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
}
return length;
{
u32 desc_num = priv->rx_currdescnum;
struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
- uint32_t desc_start = (uint32_t)desc_p;
- uint32_t desc_end = desc_start +
+ ulong desc_start = (ulong)desc_p;
+ ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
/*
return -ENOMEM;
}
+ if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
+ printf("designware: buffers are outside DMA memory\n");
+ return -EINVAL;
+ }
+
memset(dev, 0, sizeof(struct eth_device));
memset(priv, 0, sizeof(struct dw_eth_dev));
struct eth_pdata *pdata = dev_get_platdata(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
u32 iobase = pdata->iobase;
+ ulong ioaddr;
int ret;
#ifdef CONFIG_DM_PCI
#endif
debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
- priv->mac_regs_p = (struct eth_mac_regs *)iobase;
- priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
+ ioaddr = iobase;
+ priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
+ priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
priv->interface = pdata->phy_interface;
priv->max_speed = pdata->max_speed;
- dw_mdio_init(dev->name, priv->mac_regs_p);
+ dw_mdio_init(dev->name, dev);
priv->bus = miiphy_get_dev_by_name(dev->name);
ret = dw_phy_init(priv, dev);
static int designware_eth_ofdata_to_platdata(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct dw_eth_dev *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = &dw_pdata->eth_pdata;
const char *phy_mode;
const fdt32_t *cell;
+ int reset_flags = GPIOD_IS_OUT;
+ int ret = 0;
pdata->iobase = dev_get_addr(dev);
pdata->phy_interface = -1;
if (cell)
pdata->max_speed = fdt32_to_cpu(*cell);
- return 0;
+ if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &priv->reset_gpio, reset_flags);
+ if (ret == 0) {
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ "snps,reset-delays-us", dw_pdata->reset_delays, 3);
+ } else if (ret == -ENOENT) {
+ ret = 0;
+ }
+
+ return ret;
}
static const struct udevice_id designware_eth_ids[] = {
.remove = designware_eth_remove,
.ops = &designware_eth_ops,
.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#ifndef _DW_ETH_H
#define _DW_ETH_H
+#include <asm/gpio.h>
+
#define CONFIG_TX_DESCR_NUM 16
#define CONFIG_RX_DESCR_NUM 16
#define CONFIG_ETH_BUFSIZE 2048
struct dmamacdescr {
u32 txrx_status;
u32 dmamac_cntl;
- void *dmamac_addr;
- struct dmamacdescr *dmamac_next;
+ u32 dmamac_addr;
+ u32 dmamac_next;
} __aligned(ARCH_DMA_MINALIGN);
/*
#ifndef CONFIG_DM_ETH
struct eth_device *dev;
#endif
+ struct gpio_desc reset_gpio;
struct phy_device *phydev;
struct mii_dev *bus;
};
+#ifdef CONFIG_DM_ETH
+struct dw_eth_pdata {
+ struct eth_pdata eth_pdata;
+ u32 reset_delays[3];
+};
+#endif
+
#endif
{
const void *blob = gd->fdt_blob;
int pcfg_node, ret, flags, count, i;
- u32 cell[40], *ptr;
+ u32 cell[60], *ptr;
debug("%s: %s %s\n", __func__, dev->name, config->name);
ret = fdtdec_get_int_array_count(blob, config->of_offset,
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
+config DEBUG_UART_MESON
+ bool "Amlogic Meson"
+ depends on MESON_SERIAL
+ help
+ Select this to enable a debug UART using the serial_meson driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
config DEBUG_UART_UARTLITE
bool "Xilinx Uartlite"
help
If you have a Xilinx based board and want to use the uartlite
serial ports, say Y to this option. If unsure, say N.
+config MESON_SERIAL
+ bool "Support for Amlogic Meson UART"
+ depends on DM_SERIAL && ARCH_MESON
+ help
+ If you have an Amlogic Meson based board and want to use the on-chip
+ serial ports, say Y to this option. If unsure, say N.
+
config MSM_SERIAL
bool "Qualcomm on-chip UART"
depends on DM_SERIAL
obj-$(CONFIG_S5P) += serial_s5p.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
+obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
--- /dev/null
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/compiler.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct meson_uart {
+ u32 wfifo;
+ u32 rfifo;
+ u32 control;
+ u32 status;
+ u32 misc;
+};
+
+struct meson_serial_platdata {
+ struct meson_uart *reg;
+};
+
+/* AML_UART_STATUS bits */
+#define AML_UART_PARITY_ERR BIT(16)
+#define AML_UART_FRAME_ERR BIT(17)
+#define AML_UART_TX_FIFO_WERR BIT(18)
+#define AML_UART_RX_EMPTY BIT(20)
+#define AML_UART_TX_FULL BIT(21)
+#define AML_UART_TX_EMPTY BIT(22)
+#define AML_UART_XMIT_BUSY BIT(25)
+#define AML_UART_ERR (AML_UART_PARITY_ERR | \
+ AML_UART_FRAME_ERR | \
+ AML_UART_TX_FIFO_WERR)
+
+/* AML_UART_CONTROL bits */
+#define AML_UART_TX_EN BIT(12)
+#define AML_UART_RX_EN BIT(13)
+#define AML_UART_TX_RST BIT(22)
+#define AML_UART_RX_RST BIT(23)
+#define AML_UART_CLR_ERR BIT(24)
+
+static void meson_serial_init(struct meson_uart *uart)
+{
+ u32 val;
+
+ val = readl(&uart->control);
+ val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+ writel(val, &uart->control);
+ val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+ writel(val, &uart->control);
+ val |= (AML_UART_RX_EN | AML_UART_TX_EN);
+ writel(val, &uart->control);
+}
+
+static int meson_serial_probe(struct udevice *dev)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_uart *const uart = plat->reg;
+
+ meson_serial_init(uart);
+
+ return 0;
+}
+
+static int meson_serial_getc(struct udevice *dev)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_uart *const uart = plat->reg;
+
+ if (readl(&uart->status) & AML_UART_RX_EMPTY)
+ return -EAGAIN;
+
+ return readl(&uart->rfifo) & 0xff;
+}
+
+static int meson_serial_putc(struct udevice *dev, const char ch)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_uart *const uart = plat->reg;
+
+ if (readl(&uart->status) & AML_UART_TX_FULL)
+ return -EAGAIN;
+
+ writel(ch, &uart->wfifo);
+
+ return 0;
+}
+
+static int meson_serial_pending(struct udevice *dev, bool input)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_uart *const uart = plat->reg;
+ uint32_t status = readl(&uart->status);
+
+ if (input)
+ return !(status & AML_UART_RX_EMPTY);
+ else
+ return !(status & AML_UART_TX_FULL);
+}
+
+static int meson_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->reg = (struct meson_uart *)addr;
+
+ return 0;
+}
+
+static const struct dm_serial_ops meson_serial_ops = {
+ .putc = meson_serial_putc,
+ .pending = meson_serial_pending,
+ .getc = meson_serial_getc,
+};
+
+static const struct udevice_id meson_serial_ids[] = {
+ { .compatible = "amlogic,meson-uart" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_meson) = {
+ .name = "serial_meson",
+ .id = UCLASS_SERIAL,
+ .of_match = meson_serial_ids,
+ .probe = meson_serial_probe,
+ .ops = &meson_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ .ofdata_to_platdata = meson_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct meson_serial_platdata),
+};
+
+#ifdef CONFIG_DEBUG_UART_MESON
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE;
+
+ while (readl(®s->status) & AML_UART_TX_FULL)
+ ;
+
+ writel(ch, ®s->wfifo);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
dwc3-y := core.o
-dwc3-y += gadget.o ep0.o
+obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
if (!ret)
break;
}
+ video_set_flush_dcache(dev, 1);
return ret;
}
#endif
#if defined(CONFIG_CMD_DHCP)
+#if defined(CONFIG_EFI_LOADER)
+#if defined(CONFIG_ARM64)
+#define BOOTENV_EFI_PXE_ARCH "0xb"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"
+#elif defined(CONFIG_ARM)
+#define BOOTENV_EFI_PXE_ARCH "0xa"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000"
+#elif defined(CONFIG_X86)
+/* Always assume we're running 64bit */
+#define BOOTENV_EFI_PXE_ARCH "0x7"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"
+#else
+#error Please specify an EFI client identifier
+#endif
+
+/*
+ * Ask the dhcp server for an EFI binary. If we get one, check for a
+ * device tree in the same folder. Then boot everything. If the file was
+ * not an EFI binary, we just return from the bootefi command and continue.
+ */
+#define BOOTENV_EFI_RUN_DHCP \
+ "setenv efi_fdtfile ${fdtfile}; " \
+ BOOTENV_EFI_SET_FDTFILE_FALLBACK \
+ "setenv efi_old_vci ${bootp_vci};" \
+ "setenv efi_old_arch ${bootp_arch};" \
+ "setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";" \
+ "setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";" \
+ "if dhcp ${kernel_addr_r}; then " \
+ "tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};" \
+ "if fdt addr ${fdt_addr_r}; then " \
+ "bootefi ${kernel_addr_r} ${fdt_addr_r}; " \
+ "else " \
+ "bootefi ${kernel_addr_r} ${fdtcontroladdr};" \
+ "fi;" \
+ "fi;" \
+ "setenv bootp_vci ${efi_old_vci};" \
+ "setenv bootp_arch ${efi_old_arch};" \
+ "setenv efi_fdtfile;" \
+ "setenv efi_old_arch;" \
+ "setenv efi_old_vci;"
+#else
+#define BOOTENV_EFI_RUN_DHCP
+#endif
#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
"bootcmd_dhcp=" \
BOOTENV_RUN_NET_USB_START \
BOOTENV_RUN_NET_PCI_ENUM \
"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \
"source ${scriptaddr}; " \
- "fi\0"
+ "fi;" \
+ BOOTENV_EFI_RUN_DHCP \
+ "\0"
#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
"dhcp "
#else
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_SUBNETMASK
-#if defined(__arm__) || defined(__aarch64__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
-#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7"
-#endif
-#elif defined(__aarch64__)
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8"
-#endif
-#else
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.arm"
-#endif
-#endif
-#elif defined(__i386__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x0
-#elif defined(__x86_64__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x9
-#endif
-
#ifdef CONFIG_ARM64
#define CONFIG_CMD_BOOTI
#endif
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 64 MB of memory, since this is
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
+ "run init_console; " \
"run envboot; " \
"run distro_bootcmd"
"setenv fdtfile am335x-evm.dtb; fi; " \
"if test $board_name = A335X_SK; then " \
"setenv fdtfile am335x-evmsk.dtb; fi; " \
+ "if test $board_name = A335_ICE; then " \
+ "setenv fdtfile am335x-icev2.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
+ "init_console=" \
+ "if test $board_name = A335_ICE; then "\
+ "setenv console ttyO3,115200n8;" \
+ "else " \
+ "setenv console ttyO0,115200n8;" \
+ "fi;\0" \
NANDARGS \
NETARGS \
DFUARGS \
"8m(NAND.kernel)," \
"-(NAND.file-system)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_AM33XX_BCH
"128k(u-boot-env2),3464k(kernel)," \
"-(rootfs)"
#elif defined(CONFIG_EMMC_BOOT)
-#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_ENV_OFFSET 0x0
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#elif defined(CONFIG_NOR_BOOT)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
+ "512k(u-boot)," \
+ "128k(u-boot-env1)," \
+ "128k(u-boot-env2)," \
+ "4m(kernel),-(rootfs)"
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#elif !defined(CONFIG_ENV_IS_NOWHERE)
+/* Not NAND, SPI, NOR or eMMC env, so put ENV in a file on FAT */
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
#endif
/* SPI flash. */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_SIZE 0x01000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-/* Reduce SPL size by removing unlikey targets */
-#ifdef CONFIG_NOR_BOOT
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
-#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
- "512k(u-boot)," \
- "128k(u-boot-env1)," \
- "128k(u-boot-env2)," \
- "4m(kernel),-(rootfs)"
-#endif
#endif /* NOR support */
+#ifdef CONFIG_DRIVER_TI_CPSW
+#define CONFIG_CLOCK_SYNTHESIZER
+#define CLK_SYNTHESIZER_I2C_ADDR 0x65
+#endif
+
#endif /* ! __CONFIG_AM335X_EVM_H */
#ifndef __CONFIG_AM43XX_EVM_H
#define __CONFIG_AM43XX_EVM_H
-#define CONFIG_AM43XX
-
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_POWER_TPS62362
/* SPL defines. */
-#ifdef CONFIG_SPL_USB_HOST_SUPPORT
-/*
- * For USB host boot, ROM uses DMA for copying MLO from USB storage
- * and ARM internal ram is not accessible for DMA, so SPL text base
- * should be in OCMC ram
- */
-#define CONFIG_SPL_TEXT_BASE 0x40300350
-#else
-#define CONFIG_SPL_TEXT_BASE 0x402F4000
-#endif
-#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */
+#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
+#define CONFIG_SPL_MAX_SIZE (NON_SECURE_SRAM_END - \
+ CONFIG_PUB_ROM_DATA_SIZE - \
+ CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
#define CONFIG_SPL_POWER_SUPPORT
#endif
#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_SYS_TEXT_BASE 0x30000000
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
+#endif
#undef CONFIG_ENV_IS_IN_FAT
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
"setenv fdtfile am43x-epos-evm.dtb; fi; " \
"if test $board_name = AM43__GP; then " \
"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+ "if test $board_name = AM43XXHS; then " \
+ "setenv fdtfile am437x-gp-evm.dtb; fi; " \
"if test $board_name = AM43__SK; then " \
"setenv fdtfile am437x-sk-evm.dtb; fi; " \
"if test $board_name = AM43_IDK; then " \
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
#include "ls2080a_common.h"
#define CONFIG_IDENT_STRING " LS2080A-EMU"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
#include "ls2080a_common.h"
#define CONFIG_IDENT_STRING " LS2080A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-SIMU"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
--- /dev/null
+/*
+ * Configuration for ODROID-C2
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_CPU_ARMV8
+#define CONFIG_REMAKE_ELF
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_TEXT_BASE 0x01000000
+#define CONFIG_SYS_INIT_SP_ADDR 0x20000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0xc4301000
+#define GICC_BASE 0xc4302000
+
+#define CONFIG_IDENT_STRING " odroid-c2"
+
+/* Serial setup */
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_CMD_ENV
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#include <config_distro_defaults.h>
+
+#endif /* __CONFIG_H */
/*
* BOARD/CPU
*/
-
#define CONFIG_SYS_CLK_FREQ 50000000
#define CONFIG_SYS_RESET_ADDR 0x00000100
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_PINCTRL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_RAM_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_TFTP_TSIZE
#define CONFIG_MISC_INIT_R
#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_IDENT_STRING \
" for Cavium Thunder CN88XX ARM v8 Multi-Core"
-#define CONFIG_BOOTP_VCI_STRING "Diagnostics"
#define MEM_BASE 0x00500000
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
/*
* SPL related defines. The Public RAM memory map the ROM defines the
- * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
- * (dra7xx is larger, but we do not need to be larger at this time). We
- * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
+ * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
+ * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
+ * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
* print some information.
*/
-#define CONFIG_SPL_TEXT_BASE 0x40300000
-#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE)
+#ifdef CONFIG_TI_SECURE_DEVICE
+/*
+ * For memory booting on HS parts, the first 4KB of the internal RAM is
+ * reserved for secure world use and the flash loader image is
+ * preceded by a secure certificate. The SPL will therefore run in internal
+ * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
+ */
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
+#define CONFIG_SPL_TEXT_BASE 0x40301350
+#else
+/*
+ * For all booting on GP parts, the flash loader image is
+ * downloaded into internal RAM at address 0x40300000.
+ */
+#define CONFIG_SPL_TEXT_BASE 0x40300000
+#endif
+
+/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#define TI_ROM_BOOT_LOAD_END 0x4037E000
+#else
+#define TI_ROM_BOOT_LOAD_END 0x4031E000
+#endif
+#define CONFIG_SPL_MAX_SIZE (TI_ROM_BOOT_LOAD_END - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_IDENT_STRING " vexpress_aemv8a"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8.vexpress_aemv8a"
/* Link Definitions */
#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
#define __VEXPRESS_CA15X2_TC2_h
#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca15x2_tc2"
#include "vexpress_common.h"
#define CONFIG_SYSFLAGS_ADDR 0x1c010030
#define __VEXPRESS_CA5X2_h
#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca5x2"
#include "vexpress_common.h"
#endif /* __VEXPRESS_CA5X2_h */
#define __VEXPRESS_CA9X4_H
#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca9x4"
#include "vexpress_common.h"
#endif /* VEXPRESS_CA9X4_H */
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
/* Diff from config_distro_defaults.h */
#define CONFIG_SUPPORT_RAW_INITRD
const char *name, void *platdata, int of_offset,
struct udevice **devp);
+/**
+ * device_bind_with_driver_data() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver, in the case where the
+ * driver was matched to the device by means of a match table that provides
+ * driver_data.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @driver_data: The driver_data field from the driver's match table.
+ * @of_offset: Offset of device tree node for this device. This is -1 for
+ * devices which don't use device tree.
+ * @devp: if non-NULL, returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_with_driver_data(struct udevice *parent,
+ const struct driver *drv, const char *name,
+ ulong driver_data, int of_offset,
+ struct udevice **devp);
+
/**
* device_bind_by_name: Create a device and bind it to a driver
*
UCLASS_KEYBOARD, /* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
UCLASS_LPC, /* x86 'low pin count' interface */
+ UCLASS_MAILBOX, /* Mailbox controller */
UCLASS_MASS_STORAGE, /* Mass storage device */
UCLASS_MISC, /* Miscellaneous device */
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_PWM, /* Pulse-width modulator */
UCLASS_PWRSEQ, /* Power sequence device */
UCLASS_REGULATOR, /* Regulator device */
- UCLASS_RESET, /* Reset device */
UCLASS_REMOTEPROC, /* Remote Processor device */
UCLASS_RTC, /* Real time clock device */
UCLASS_SERIAL, /* Serial UART */
UCLASS_SPI_FLASH, /* SPI flash */
UCLASS_SPI_GENERIC, /* Generic SPI flash target */
UCLASS_SYSCON, /* System configuration device */
+ UCLASS_SYSRESET, /* System reset device */
UCLASS_THERMAL, /* Thermal sensor */
UCLASS_TIMER, /* Timer device */
UCLASS_TPM, /* Trusted Platform Module TIS interface */
#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN (INPUT_EN)
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val)
+
#endif
#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
+#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
+#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
+#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+
+/*
+ * Macros to allow using the offset from the padconf physical address
+ * instead of the offset from padconf base.
+ */
+#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
+
+#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+
+/*
+ * Define some commonly used pins configured by the boards.
+ * Note that some boards use alternative pins, so check
+ * the schematics before using these.
+ */
+#define OMAP3_UART1_RX 0x152
+#define OMAP3_UART2_RX 0x14a
+#define OMAP3_UART3_RX 0x16e
+#define OMAP4_UART2_RX 0xdc
+#define OMAP4_UART3_RX 0x104
+#define OMAP4_UART4_RX 0x11c
+
#endif
--- /dev/null
+#ifndef __DT_TLV320AIC31XX_MICBIAS_H
+#define __DT_TLV320AIC31XX_MICBIAS_H
+
+#define MICBIAS_2_0V 1
+#define MICBIAS_2_5V 2
+#define MICBIAS_AVDDV 3
+
+#endif /* __DT_TLV320AIC31XX_MICBIAS_H */
* @freq: Frequency the host is trying to achieve
*/
unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
-
+#ifndef CONFIG_BLK
struct mmc_config cfg;
+#endif
/* use fifo mode to read and write data */
bool fifo_mode;
return readb(host->ioaddr + reg);
}
+void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+ uint caps, u32 max_clk, u32 min_clk);
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
#endif /* __DWMMC_HW_H */
struct efi_gop_mode *mode;
};
+#define EFI_SIMPLE_NETWORK_GUID \
+ EFI_GUID(0xa19832b9, 0xac25, 0x11d3, \
+ 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_mac_address {
+ char mac_addr[32];
+};
+
+struct efi_ip_address {
+ u8 ip_addr[16];
+};
+
+enum efi_simple_network_state {
+ EFI_NETWORK_STOPPED,
+ EFI_NETWORK_STARTED,
+ EFI_NETWORK_INITIALIZED,
+};
+
+struct efi_simple_network_mode {
+ enum efi_simple_network_state state;
+ u32 hwaddr_size;
+ u32 media_header_size;
+ u32 max_packet_size;
+ u32 nvram_size;
+ u32 nvram_access_size;
+ u32 receive_filter_mask;
+ u32 receive_filter_setting;
+ u32 max_mcast_filter_count;
+ u32 mcast_filter_count;
+ struct efi_mac_address mcast_filter[16];
+ struct efi_mac_address current_address;
+ struct efi_mac_address broadcast_address;
+ struct efi_mac_address permanent_address;
+ u8 if_type;
+ u8 mac_changeable;
+ u8 multitx_supported;
+ u8 media_present_supported;
+ u8 media_present;
+};
+
+#define EFI_SIMPLE_NETWORK_RECEIVE_UNICAST 0x01,
+#define EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST 0x02,
+#define EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST 0x04,
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS 0x08,
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10,
+
+struct efi_simple_network
+{
+ u64 revision;
+ efi_status_t (EFIAPI *start)(struct efi_simple_network *this);
+ efi_status_t (EFIAPI *stop)(struct efi_simple_network *this);
+ efi_status_t (EFIAPI *initialize)(struct efi_simple_network *this,
+ ulong extra_rx, ulong extra_tx);
+ efi_status_t (EFIAPI *reset)(struct efi_simple_network *this,
+ int extended_verification);
+ efi_status_t (EFIAPI *shutdown)(struct efi_simple_network *this);
+ efi_status_t (EFIAPI *receive_filters)(struct efi_simple_network *this,
+ u32 enable, u32 disable, int reset_mcast_filter,
+ ulong mcast_filter_count,
+ struct efi_mac_address *mcast_filter);
+ efi_status_t (EFIAPI *station_address)(struct efi_simple_network *this,
+ int reset, struct efi_mac_address *new_mac);
+ efi_status_t (EFIAPI *statistics)(struct efi_simple_network *this,
+ int reset, ulong *stat_size, void *stat_table);
+ efi_status_t (EFIAPI *mcastiptomac)(struct efi_simple_network *this,
+ int ipv6, struct efi_ip_address *ip,
+ struct efi_mac_address *mac);
+ efi_status_t (EFIAPI *nvdata)(struct efi_simple_network *this,
+ int read_write, ulong offset, ulong buffer_size,
+ char *buffer);
+ efi_status_t (EFIAPI *get_status)(struct efi_simple_network *this,
+ u32 *int_status, void **txbuf);
+ efi_status_t (EFIAPI *transmit)(struct efi_simple_network *this,
+ ulong header_size, ulong buffer_size, void *buffer,
+ struct efi_mac_address *src_addr,
+ struct efi_mac_address *dest_addr, u16 *protocol);
+ efi_status_t (EFIAPI *receive)(struct efi_simple_network *this,
+ ulong *header_size, ulong *buffer_size, void *buffer,
+ struct efi_mac_address *src_addr,
+ struct efi_mac_address *dest_addr, u16 *protocol);
+ void (EFIAPI *waitforpacket)(void);
+ struct efi_simple_network_mode *mode;
+};
+
+#define EFI_PXE_GUID \
+ EFI_GUID(0x03c4e603, 0xac28, 0x11d3, \
+ 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_pxe_packet {
+ u8 packet[1472];
+};
+
+struct efi_pxe_mode
+{
+ u8 unused[52];
+ struct efi_pxe_packet dhcp_discover;
+ struct efi_pxe_packet dhcp_ack;
+ struct efi_pxe_packet proxy_offer;
+ struct efi_pxe_packet pxe_discover;
+ struct efi_pxe_packet pxe_reply;
+};
+
+struct efi_pxe {
+ u64 rev;
+ void (EFIAPI *start)(void);
+ void (EFIAPI *stop)(void);
+ void (EFIAPI *dhcp)(void);
+ void (EFIAPI *discover)(void);
+ void (EFIAPI *mftp)(void);
+ void (EFIAPI *udpwrite)(void);
+ void (EFIAPI *udpread)(void);
+ void (EFIAPI *setipfilter)(void);
+ void (EFIAPI *arp)(void);
+ void (EFIAPI *setparams)(void);
+ void (EFIAPI *setstationip)(void);
+ void (EFIAPI *setpackets)(void);
+ struct efi_pxe_mode *mode;
+};
+
#endif
int efi_disk_register(void);
/* Called by bootefi to make GOP (graphical) interface available */
int efi_gop_register(void);
+/* Called by bootefi to make the network interface available */
+int efi_net_register(void **handle);
+
+/* Called by networking code to memorize the dhcp ack package */
+void efi_net_set_dhcp_ack(void *pkt, int len);
+
/*
* Stub implementation for a protocol opener that just returns the handle as
* interface
/* Called by board init to initialize the EFI memory map */
int efi_memory_init(void);
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+extern void *efi_bounce_buffer;
+#define EFI_LOADER_BOUNCE_BUFFER_SIZE (64 * 1024 * 1024)
+#endif
+
/* Convert strings from normal C strings to uEFI strings */
-static inline void ascii2unicode(u16 *unicode, char *ascii)
+static inline void ascii2unicode(u16 *unicode, const char *ascii)
{
while (*ascii)
*(unicode++) = *(ascii++);
static inline void efi_restore_gd(void) { }
static inline void efi_set_bootdev(const char *dev, const char *devnr,
const char *path) { }
+static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
#endif
#include <hash.h>
#include <libfdt.h>
#include <fdt_support.h>
+# ifdef CONFIG_FIT_DISABLE_SHA256
+# undef CONFIG_SHA256
+# undef IMAGE_ENABLE_SHA256
+# endif
# ifdef CONFIG_SPL_BUILD
-# ifdef CONFIG_SPL_CRC32_SUPPORT
-# define IMAGE_ENABLE_CRC32 1
-# endif
-# ifdef CONFIG_SPL_MD5_SUPPORT
-# define IMAGE_ENABLE_MD5 1
-# endif
-# ifdef CONFIG_SPL_SHA1_SUPPORT
-# define IMAGE_ENABLE_SHA1 1
-# endif
-# ifdef CONFIG_SPL_SHA256_SUPPORT
-# define IMAGE_ENABLE_SHA256 1
-# endif
+# define IMAGE_ENABLE_CRC32 CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT)
+# define IMAGE_ENABLE_MD5 CONFIG_IS_ENABLED(SPL_MD5_SUPPORT)
+# define IMAGE_ENABLE_SHA1 CONFIG_IS_ENABLED(SPL_SHA1_SUPPORT)
+# define IMAGE_ENABLE_SHA256 CONFIG_IS_ENABLED(SPL_SHA256_SUPPORT)
# else
# define CONFIG_CRC32 /* FIT images need CRC32 support */
# define CONFIG_MD5 /* and MD5 */
# define IMAGE_ENABLE_SHA1 1
# define IMAGE_ENABLE_SHA256 1
# endif
-
-#ifdef CONFIG_FIT_DISABLE_SHA256
-#undef CONFIG_SHA256
-#undef IMAGE_ENABLE_SHA256
-#endif
-
-#ifndef IMAGE_ENABLE_CRC32
-#define IMAGE_ENABLE_CRC32 0
-#endif
-
-#ifndef IMAGE_ENABLE_MD5
-#define IMAGE_ENABLE_MD5 0
-#endif
-
-#ifndef IMAGE_ENABLE_SHA1
-#define IMAGE_ENABLE_SHA1 0
-#endif
-
-#ifndef IMAGE_ENABLE_SHA256
-#define IMAGE_ENABLE_SHA256 0
-#endif
-
#endif /* IMAGE_ENABLE_FIT */
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
-# define IMAGE_ENABLE_RAMDISK_HIGH 1
-#else
-# define IMAGE_ENABLE_RAMDISK_HIGH 0
-#endif
-
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
-# define IMAGE_BOOT_GET_CMDLINE 1
-#else
-# define IMAGE_BOOT_GET_CMDLINE 0
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-# define IMAGE_OF_BOARD_SETUP 1
-#else
-# define IMAGE_OF_BOARD_SETUP 0
-#endif
-
-#ifdef CONFIG_OF_SYSTEM_SETUP
-# define IMAGE_OF_SYSTEM_SETUP 1
-#else
-# define IMAGE_OF_SYSTEM_SETUP 0
-#endif
+#define IMAGE_ENABLE_RAMDISK_HIGH CONFIG_IS_ENABLED(SYS_BOOT_RAMDISK_HIGH)
+#define IMAGE_BOOT_GET_CMDLINE CONFIG_IS_ENABLED(SYS_BOOT_GET_CMDLINE)
+#define IMAGE_OF_BOARD_SETUP CONFIG_IS_ENABLED(OF_BOARD_SETUP)
+#define IMAGE_OF_SYSTEM_SETUP CONFIG_IS_ENABLED(OF_SYSTEM_SETUP)
/*
* Operating System Codes
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_CLIENT_H
+#define _MAILBOX_CLIENT_H
+
+/**
+ * A mailbox is a hardware mechanism for transferring small fixed-size messages
+ * and/or notifications between the CPU on which U-Boot runs and some other
+ * device such as an auxiliary CPU running firmware or a hardware module.
+ *
+ * Data transfer is optional; a mailbox may consist solely of a notification
+ * mechanism. When data transfer is implemented, it is via HW registers or
+ * FIFOs, rather than via RAM-based buffers. The mailbox API generally
+ * implements any communication protocol enforced solely by hardware, and
+ * leaves any higher-level protocols to other layers.
+ *
+ * A mailbox channel is a bi-directional mechanism that can send a message or
+ * notification to a single specific remote entity, and receive messages or
+ * notifications from that entity. The size, content, and format of such
+ * messages is defined by the mailbox implementation, or the remote entity with
+ * which it communicates; there is no general standard at this API level.
+ *
+ * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider
+ * will often implement multiple separate mailbox channels, since the hardware
+ * it manages often has this capability. mailbox_uclass.h describes the
+ * interface which mailbox providers must implement.
+ *
+ * Mailbox consumers/clients generate and send, or receive and process,
+ * messages. This header file describes the API used by clients.
+ */
+
+struct udevice;
+
+/**
+ * struct mbox_chan - A handle to a single mailbox channel.
+ *
+ * Clients provide storage for channels. The content of the channel structure
+ * is managed solely by the mailbox API and mailbox drivers. A mailbox channel
+ * is initialized by "get"ing the mailbox. The channel struct is passed to all
+ * other mailbox APIs to identify which mailbox to operate upon.
+ *
+ * @dev: The device which implements the mailbox.
+ * @id: The mailbox channel ID within the provider.
+ *
+ * Currently, the mailbox API assumes that a single integer ID is enough to
+ * identify and configure any mailbox channel for any mailbox provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow mailbox providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct mbox_chan {
+ struct udevice *dev;
+ /*
+ * Written by of_xlate. We assume a single id is enough for now. In the
+ * future, we might add more fields here.
+ */
+ unsigned long id;
+};
+
+/**
+ * mbox_get_by_index - Get/request a mailbox by integer index
+ *
+ * This looks up and requests a mailbox channel. The index is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel indices to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev: The client device.
+ * @index: The index of the mailbox channel to request, within the
+ * client's list of channels.
+ * @chan A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan);
+
+/**
+ * mbox_get_by_name - Get/request a mailbox by name
+ *
+ * This looks up and requests a mailbox channel. The name is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel names to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev: The client device.
+ * @name: The name of the mailbox channel to request, within the client's
+ * list of channels.
+ * @chan A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_name(struct udevice *dev, const char *name,
+ struct mbox_chan *chan);
+
+/**
+ * mbox_free - Free a previously requested mailbox channel.
+ *
+ * @chan: A channel object that was previously successfully requested by
+ * calling mbox_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_free(struct mbox_chan *chan);
+
+/**
+ * mbox_send - Send a message over a mailbox channel
+ *
+ * This function will send a message to the remote entity. It may return before
+ * the remote entity has received and/or processed the message.
+ *
+ * @chan: A channel object that was previously successfully requested by
+ * calling mbox_get_by_*().
+ * @data: A pointer to the message to transfer. The format and size of
+ * the memory region pointed at by @data is determined by the
+ * mailbox provider. Providers that solely transfer notifications
+ * will ignore this parameter.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_send(struct mbox_chan *chan, const void *data);
+
+/**
+ * mbox_recv - Receive any available message from a mailbox channel
+ *
+ * This function will wait (up to the specified @timeout_us) for a message to
+ * be sent by the remote entity, and write the content of any such message
+ * into a caller-provided buffer.
+ *
+ * @chan: A channel object that was previously successfully requested by
+ * calling mbox_get_by_*().
+ * @data: A pointer to the buffer to receive the message. The format and
+ * size of the memory region pointed at by @data is determined by
+ * the mailbox provider. Providers that solely transfer
+ * notifications will ignore this parameter.
+ * @timeout_us: The maximum time to wait for a message to be available, in
+ * micro-seconds. A value of 0 does not wait at all.
+ * @return 0 if OK, -ENODATA if no message was available, or a negative error
+ * code.
+ */
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_UCLASS_H
+#define _MAILBOX_UCLASS_H
+
+/* See mailbox_client.h for background documentation. */
+
+#include <mailbox_client.h>
+
+struct udevice;
+
+/**
+ * struct mbox_ops - The functions that a mailbox driver must implement.
+ */
+struct mbox_ops {
+ /**
+ * of_xlate - Translate a client's device-tree (OF) mailbox specifier.
+ *
+ * The mailbox core calls this function as the first step in
+ * implementing a client's mbox_get_by_*() call.
+ *
+ * If this function pointer is set to NULL, the mailbox core will use
+ * a default implementation, which assumes #mbox-cells = <1>, and that
+ * the DT cell contains a simple integer channel ID.
+ *
+ * At present, the mailbox API solely supports device-tree. If this
+ * changes, other xxx_xlate() functions may be added to support those
+ * other mechanisms.
+ *
+ * @chan: The channel to hold the translation result.
+ * @args: The mailbox specifier values from device tree.
+ * @return 0 if OK, or a negative error code.
+ */
+ int (*of_xlate)(struct mbox_chan *chan,
+ struct fdtdec_phandle_args *args);
+ /**
+ * request - Request a translated channel.
+ *
+ * The mailbox core calls this function as the second step in
+ * implementing a client's mbox_get_by_*() call, following a successful
+ * xxx_xlate() call.
+ *
+ * @chan: The channel to request; this has been filled in by a
+ * previoux xxx_xlate() function call.
+ * @return 0 if OK, or a negative error code.
+ */
+ int (*request)(struct mbox_chan *chan);
+ /**
+ * free - Free a previously requested channel.
+ *
+ * This is the implementation of the client mbox_free() API.
+ *
+ * @chan: The channel to free.
+ * @return 0 if OK, or a negative error code.
+ */
+ int (*free)(struct mbox_chan *chan);
+ /**
+ * send - Send a message over a mailbox channel
+ *
+ * @chan: The channel to send to the message to.
+ * @data: A pointer to the message to send.
+ * @return 0 if OK, or a negative error code.
+ */
+ int (*send)(struct mbox_chan *chan, const void *data);
+ /**
+ * recv - Receive any available message from the channel.
+ *
+ * This function does not block. If not message is immediately
+ * available, the function should return an error.
+ *
+ * @chan: The channel to receive to the message from.
+ * @data: A pointer to the buffer to hold the received message.
+ * @return 0 if OK, -ENODATA if no message was available, or a negative
+ * error code.
+ */
+ int (*recv)(struct mbox_chan *chan, void *data);
+};
+
+#endif
MMC_HWPART_CONF_COMPLETE,
};
-int mmc_register(struct mmc *mmc);
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
/**
*/
void mmc_set_preinit(struct mmc *mmc, int preinit);
-#ifdef CONFIG_GENERIC_MMC
#ifdef CONFIG_MMC_SPI
#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
#else
#define mmc_host_is_spi(mmc) 0
#endif
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
-#else
-int mmc_legacy_init(int verbose);
-#endif
void board_mmc_power_init(void);
int board_mmc_init(bd_t *bis);
int eth_init(void); /* Initialize the device */
int eth_send(void *packet, int length); /* Send a packet */
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
int eth_receive(void *packet, int length); /* Receive a packet*/
extern void (*push_packet)(void *packet, int length);
#endif
+++ /dev/null
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __RESET_H
-#define __RESET_H
-
-enum reset_t {
- RESET_WARM, /* Reset CPU, keep GPIOs active */
- RESET_COLD, /* Reset CPU and GPIOs */
- RESET_POWER, /* Reset PMIC (remove and restore power) */
-
- RESET_COUNT,
-};
-
-struct reset_ops {
- /**
- * request() - request a reset of the given type
- *
- * Note that this function may return before the reset takes effect.
- *
- * @type: Reset type to request
- * @return -EINPROGRESS if the reset has been started and
- * will complete soon, -EPROTONOSUPPORT if not supported
- * by this device, 0 if the reset has already happened
- * (in which case this method will not actually return)
- */
- int (*request)(struct udevice *dev, enum reset_t type);
-};
-
-#define reset_get_ops(dev) ((struct reset_ops *)(dev)->driver->ops)
-
-/**
- * reset_request() - request a reset
- *
- * @type: Reset type to request
- * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
- */
-int reset_request(struct udevice *dev, enum reset_t type);
-
-/**
- * reset_walk() - cause a reset
- *
- * This works through the available reset devices until it finds one that can
- * perform a reset. If the provided reset type is not available, the next one
- * will be tried.
- *
- * If this function fails to reset, it will display a message and halt
- *
- * @type: Reset type to request
- * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
- */
-int reset_walk(enum reset_t type);
-
-/**
- * reset_walk_halt() - try to reset, otherwise halt
- *
- * This calls reset_walk(). If it returns, indicating that reset is not
- * supported, it prints a message and halts.
- */
-void reset_walk_halt(enum reset_t type);
-
-/**
- * reset_cpu() - calls reset_walk(RESET_WARM)
- */
-void reset_cpu(ulong addr);
-
-#endif
extern struct serial_device eserial1_device;
extern struct serial_device eserial2_device;
+extern struct serial_device eserial3_device;
+extern struct serial_device eserial4_device;
+extern struct serial_device eserial5_device;
+extern struct serial_device eserial6_device;
extern void serial_register(struct serial_device *);
extern void serial_initialize(void);
* @dev: Pointer to the device, e.g. struct mmc *
* @priv: Private data for the device
* @bl_len: Block length for reading in bytes
+ * @filename: Name of the fit image file.
* @read: Function to call to read from the device
*/
struct spl_load_info {
void *dev;
void *priv;
int bl_len;
+ const char *filename;
ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
void *buf);
};
+/**
+ * spl_load_simple_fit() - Loads a fit image from a device.
+ * @info: Structure containing the information required to load data.
+ * @sector: Sector number where FIT image is located in the device
+ * @fdt: Pointer to the copied FIT header.
+ *
+ * Reads the FIT image @sector in the device. Loads u-boot image to
+ * specified load address and copies the dtb to end of u-boot image.
+ * Returns 0 on success.
+ */
int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fdt);
#define SPL_COPY_PAYLOAD_ONLY 1
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SYSRESET_H
+#define __SYSRESET_H
+
+enum sysreset_t {
+ SYSRESET_WARM, /* Reset CPU, keep GPIOs active */
+ SYSRESET_COLD, /* Reset CPU and GPIOs */
+ SYSRESET_POWER, /* Reset PMIC (remove and restore power) */
+
+ SYSRESET_COUNT,
+};
+
+struct sysreset_ops {
+ /**
+ * request() - request a sysreset of the given type
+ *
+ * Note that this function may return before the reset takes effect.
+ *
+ * @type: Reset type to request
+ * @return -EINPROGRESS if the reset has been started and
+ * will complete soon, -EPROTONOSUPPORT if not supported
+ * by this device, 0 if the reset has already happened
+ * (in which case this method will not actually return)
+ */
+ int (*request)(struct udevice *dev, enum sysreset_t type);
+};
+
+#define sysreset_get_ops(dev) ((struct sysreset_ops *)(dev)->driver->ops)
+
+/**
+ * sysreset_request() - request a sysreset
+ *
+ * @type: Reset type to request
+ * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
+ */
+int sysreset_request(struct udevice *dev, enum sysreset_t type);
+
+/**
+ * sysreset_walk() - cause a system reset
+ *
+ * This works through the available sysreset devices until it finds one that can
+ * perform a reset. If the provided sysreset type is not available, the next one
+ * will be tried.
+ *
+ * If this function fails to reset, it will display a message and halt
+ *
+ * @type: Reset type to request
+ * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
+ */
+int sysreset_walk(enum sysreset_t type);
+
+/**
+ * sysreset_walk_halt() - try to reset, otherwise halt
+ *
+ * This calls sysreset_walk(). If it returns, indicating that reset is not
+ * supported, it prints a message and halts.
+ */
+void sysreset_walk_halt(enum sysreset_t type);
+
+/**
+ * reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
+ */
+void reset_cpu(ulong addr);
+
+#endif
int init_func_watchdog_reset(void);
#endif
-#if defined(CONFIG_SYS_GENERIC_BOARD) && \
- (defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG))
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
#else
on top of U-Boot. If this option is enabled, U-Boot will expose EFI
interfaces to a loaded EFI application, enabling it to reuse U-Boot's
device drivers.
+
+config EFI_LOADER_BOUNCE_BUFFER
+ bool "EFI Applications use bounce buffers for DMA operations"
+ depends on EFI_LOADER && ARM64
+ default n
+ help
+ Some hardware does not support DMA to full 64bit addresses. For this
+ hardware we can create a bounce buffer so that payloads don't have to
+ worry about platform details.
obj-y += efi_memory.o
obj-$(CONFIG_LCD) += efi_gop.o
obj-$(CONFIG_PARTITIONS) += efi_disk.o
+obj-$(CONFIG_NET) += efi_net.o
#include <common.h>
#include <blk.h>
+#include <dm.h>
#include <efi_loader.h>
#include <inttypes.h>
#include <part.h>
int blocks;
unsigned long n;
- EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
- buffer_size, buffer);
-
diskobj = container_of(this, struct efi_disk_obj, ops);
if (!(desc = blk_get_dev(diskobj->ifname, diskobj->dev_index)))
return EFI_EXIT(EFI_DEVICE_ERROR);
return EFI_EXIT(EFI_DEVICE_ERROR);
if (direction == EFI_DISK_READ)
- n = desc->block_read(desc, lba, blocks, buffer);
+ n = blk_dread(desc, lba, blocks, buffer);
else
- n = desc->block_write(desc, lba, blocks, buffer);
+ n = blk_dwrite(desc, lba, blocks, buffer);
/* We don't do interrupts, so check for timers cooperatively */
efi_timer_check();
u32 media_id, u64 lba, unsigned long buffer_size,
void *buffer)
{
- return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
- EFI_DISK_READ);
+ void *real_buffer = buffer;
+ efi_status_t r;
+
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+ if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
+ r = efi_disk_read_blocks(this, media_id, lba,
+ EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer);
+ if (r != EFI_SUCCESS)
+ return r;
+ return efi_disk_read_blocks(this, media_id, lba +
+ EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size,
+ buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE,
+ buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE);
+ }
+
+ real_buffer = efi_bounce_buffer;
+#endif
+
+ EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+ buffer_size, buffer);
+
+ r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
+ EFI_DISK_READ);
+
+ /* Copy from bounce buffer to real buffer if necessary */
+ if ((r == EFI_SUCCESS) && (real_buffer != buffer))
+ memcpy(buffer, real_buffer, buffer_size);
+
+ return EFI_EXIT(r);
}
static efi_status_t efi_disk_write_blocks(struct efi_block_io *this,
u32 media_id, u64 lba, unsigned long buffer_size,
void *buffer)
{
- return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
- EFI_DISK_WRITE);
+ void *real_buffer = buffer;
+ efi_status_t r;
+
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+ if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
+ r = efi_disk_write_blocks(this, media_id, lba,
+ EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer);
+ if (r != EFI_SUCCESS)
+ return r;
+ return efi_disk_write_blocks(this, media_id, lba +
+ EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size,
+ buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE,
+ buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE);
+ }
+
+ real_buffer = efi_bounce_buffer;
+#endif
+
+ EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+ buffer_size, buffer);
+
+ /* Populate bounce buffer if necessary */
+ if (real_buffer != buffer)
+ memcpy(real_buffer, buffer, buffer_size);
+
+ r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
+ EFI_DISK_WRITE);
+
+ return EFI_EXIT(r);
}
static efi_status_t EFIAPI efi_disk_flush_blocks(struct efi_block_io *this)
.flush_blocks = &efi_disk_flush_blocks,
};
-static void efi_disk_add_dev(char *name,
- const struct blk_driver *cur_drvr,
+static void efi_disk_add_dev(const char *name,
+ const char *if_typename,
const struct blk_desc *desc,
int dev_index,
lbaint_t offset)
diskobj->parent.protocols[1].open = efi_disk_open_dp;
diskobj->parent.handle = diskobj;
diskobj->ops = block_io_disk_template;
- diskobj->ifname = cur_drvr->if_typename;
+ diskobj->ifname = if_typename;
diskobj->dev_index = dev_index;
diskobj->offset = offset;
}
static int efi_disk_create_eltorito(struct blk_desc *desc,
- const struct blk_driver *cur_drvr,
+ const char *if_typename,
int diskid)
{
int disks = 0;
return 0;
while (!part_get_info(desc, part, &info)) {
- snprintf(devname, sizeof(devname), "%s%d:%d",
- cur_drvr->if_typename, diskid, part);
- efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start);
+ snprintf(devname, sizeof(devname), "%s%d:%d", if_typename,
+ diskid, part);
+ efi_disk_add_dev(devname, if_typename, desc, diskid,
+ info.start);
part++;
disks++;
}
* EFI payload, we scan through all of the potentially available ones and
* store them in our object pool.
*
+ * TODO(sjg@chromium.org): Actually with CONFIG_BLK, U-Boot does have this.
+ * Consider converting the code to look up devices as needed. The EFI device
+ * could be a child of the UCLASS_BLK block device, perhaps.
+ *
* This gets called from do_bootefi_exec().
*/
int efi_disk_register(void)
{
- const struct blk_driver *cur_drvr;
- int i, if_type;
int disks = 0;
+#ifdef CONFIG_BLK
+ struct udevice *dev;
+
+ for (uclass_first_device(UCLASS_BLK, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ const char *if_typename = dev->driver->name;
+
+ printf("Scanning disk %s...\n", dev->name);
+ efi_disk_add_dev(dev->name, if_typename, desc, desc->devnum, 0);
+ disks++;
+
+ /*
+ * El Torito images show up as block devices in an EFI world,
+ * so let's create them here
+ */
+ disks += efi_disk_create_eltorito(desc, if_typename,
+ desc->devnum);
+ }
+#else
+ int i, if_type;
/* Search for all available disk devices */
for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) {
+ const struct blk_driver *cur_drvr;
+ const char *if_typename;
+
cur_drvr = blk_driver_lookup_type(if_type);
if (!cur_drvr)
continue;
- printf("Scanning disks on %s...\n", cur_drvr->if_typename);
+ if_typename = cur_drvr->if_typename;
+ printf("Scanning disks on %s...\n", if_typename);
for (i = 0; i < 4; i++) {
struct blk_desc *desc;
char devname[32] = { 0 }; /* dp->str is u16[32] long */
continue;
snprintf(devname, sizeof(devname), "%s%d",
- cur_drvr->if_typename, i);
- efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
+ if_typename, i);
+ efi_disk_add_dev(devname, if_typename, desc, i, 0);
disks++;
/*
* El Torito images show up as block devices
* in an EFI world, so let's create them here
*/
- disks += efi_disk_create_eltorito(desc, cur_drvr, i);
+ disks += efi_disk_create_eltorito(desc, if_typename, i);
}
}
+#endif
printf("Found %d disks\n", disks);
return 0;
int efi_gop_register(void)
{
struct efi_gop_obj *gopobj;
- int line_len;
switch (panel_info.vl_bpix) {
case LCD_COLOR32:
gopobj->mode.max_mode = 1;
gopobj->mode.info = &gopobj->info;
gopobj->mode.info_size = sizeof(gopobj->info);
- gopobj->mode.fb_base = gd->fb_base;
- gopobj->mode.fb_size = lcd_get_size(&line_len);
gopobj->info.version = 0;
gopobj->info.width = panel_info.vl_col;
/* This list contains all memory map items */
LIST_HEAD(efi_mem);
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+void *efi_bounce_buffer;
+#endif
+
/*
* Sorts the memory list from highest address to lowest address
*
efi_add_memory_map(runtime_start, runtime_pages,
EFI_RUNTIME_SERVICES_CODE, false);
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+ /* Request a 32bit 64MB bounce buffer region */
+ uint64_t efi_bounce_buffer_addr = 0xffffffff;
+
+ if (efi_allocate_pages(1, EFI_LOADER_DATA,
+ (64 * 1024 * 1024) >> EFI_PAGE_SHIFT,
+ &efi_bounce_buffer_addr) != EFI_SUCCESS)
+ return -1;
+
+ efi_bounce_buffer = (void*)(uintptr_t)efi_bounce_buffer_addr;
+#endif
+
return 0;
}
--- /dev/null
+/*
+ * EFI application network access support
+ *
+ * Copyright (c) 2016 Alexander Graf
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <inttypes.h>
+#include <lcd.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_GUID;
+static const efi_guid_t efi_pxe_guid = EFI_PXE_GUID;
+static struct efi_pxe_packet *dhcp_ack;
+static bool new_rx_packet;
+static void *new_tx_packet;
+
+struct efi_net_obj {
+ /* Generic EFI object parent class data */
+ struct efi_object parent;
+ /* EFI Interface callback struct for network */
+ struct efi_simple_network net;
+ struct efi_simple_network_mode net_mode;
+ /* Device path to the network adapter */
+ struct efi_device_path_file_path dp[2];
+ /* PXE struct to transmit dhcp data */
+ struct efi_pxe pxe;
+ struct efi_pxe_mode pxe_mode;
+};
+
+static efi_status_t EFIAPI efi_net_start(struct efi_simple_network *this)
+{
+ EFI_ENTRY("%p", this);
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this)
+{
+ EFI_ENTRY("%p", this);
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this,
+ ulong extra_rx, ulong extra_tx)
+{
+ EFI_ENTRY("%p, %lx, %lx", this, extra_rx, extra_tx);
+
+ eth_init();
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_reset(struct efi_simple_network *this,
+ int extended_verification)
+{
+ EFI_ENTRY("%p, %x", this, extended_verification);
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_shutdown(struct efi_simple_network *this)
+{
+ EFI_ENTRY("%p", this);
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_receive_filters(
+ struct efi_simple_network *this, u32 enable, u32 disable,
+ int reset_mcast_filter, ulong mcast_filter_count,
+ struct efi_mac_address *mcast_filter)
+{
+ EFI_ENTRY("%p, %x, %x, %x, %lx, %p", this, enable, disable,
+ reset_mcast_filter, mcast_filter_count, mcast_filter);
+
+ /* XXX Do we care? */
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_station_address(
+ struct efi_simple_network *this, int reset,
+ struct efi_mac_address *new_mac)
+{
+ EFI_ENTRY("%p, %x, %p", this, reset, new_mac);
+
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_statistics(struct efi_simple_network *this,
+ int reset, ulong *stat_size,
+ void *stat_table)
+{
+ EFI_ENTRY("%p, %x, %p, %p", this, reset, stat_size, stat_table);
+
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_mcastiptomac(struct efi_simple_network *this,
+ int ipv6,
+ struct efi_ip_address *ip,
+ struct efi_mac_address *mac)
+{
+ EFI_ENTRY("%p, %x, %p, %p", this, ipv6, ip, mac);
+
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_nvdata(struct efi_simple_network *this,
+ int read_write, ulong offset,
+ ulong buffer_size, char *buffer)
+{
+ EFI_ENTRY("%p, %x, %lx, %lx, %p", this, read_write, offset, buffer_size,
+ buffer);
+
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this,
+ u32 *int_status, void **txbuf)
+{
+ EFI_ENTRY("%p, %p, %p", this, int_status, txbuf);
+
+ /* We send packets synchronously, so nothing is outstanding */
+ if (int_status)
+ *int_status = 0;
+ if (txbuf)
+ *txbuf = new_tx_packet;
+
+ new_tx_packet = NULL;
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_transmit(struct efi_simple_network *this,
+ ulong header_size, ulong buffer_size, void *buffer,
+ struct efi_mac_address *src_addr,
+ struct efi_mac_address *dest_addr, u16 *protocol)
+{
+ EFI_ENTRY("%p, %lx, %lx, %p, %p, %p, %p", this, header_size,
+ buffer_size, buffer, src_addr, dest_addr, protocol);
+
+ if (header_size) {
+ /* We would need to create the header if header_size != 0 */
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+ }
+
+ net_send_packet(buffer, buffer_size);
+ new_tx_packet = buffer;
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static void efi_net_push(void *pkt, int len)
+{
+ new_rx_packet = true;
+}
+
+static efi_status_t EFIAPI efi_net_receive(struct efi_simple_network *this,
+ ulong *header_size, ulong *buffer_size, void *buffer,
+ struct efi_mac_address *src_addr,
+ struct efi_mac_address *dest_addr, u16 *protocol)
+{
+ EFI_ENTRY("%p, %p, %p, %p, %p, %p, %p", this, header_size,
+ buffer_size, buffer, src_addr, dest_addr, protocol);
+
+ push_packet = efi_net_push;
+ eth_rx();
+ push_packet = NULL;
+
+ if (!new_rx_packet)
+ return EFI_EXIT(EFI_NOT_READY);
+
+ if (*buffer_size < net_rx_packet_len) {
+ /* Packet doesn't fit, try again with bigger buf */
+ *buffer_size = net_rx_packet_len;
+ return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+ }
+
+ memcpy(buffer, net_rx_packet, net_rx_packet_len);
+ *buffer_size = net_rx_packet_len;
+ new_rx_packet = false;
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t efi_net_open_dp(void *handle, efi_guid_t *protocol,
+ void **protocol_interface, void *agent_handle,
+ void *controller_handle, uint32_t attributes)
+{
+ struct efi_simple_network *net = handle;
+ struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
+
+ *protocol_interface = netobj->dp;
+
+ return EFI_SUCCESS;
+}
+
+static efi_status_t efi_net_open_pxe(void *handle, efi_guid_t *protocol,
+ void **protocol_interface, void *agent_handle,
+ void *controller_handle, uint32_t attributes)
+{
+ struct efi_simple_network *net = handle;
+ struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
+
+ *protocol_interface = &netobj->pxe;
+
+ return EFI_SUCCESS;
+}
+
+void efi_net_set_dhcp_ack(void *pkt, int len)
+{
+ int maxsize = sizeof(*dhcp_ack);
+
+ if (!dhcp_ack)
+ dhcp_ack = malloc(maxsize);
+
+ memcpy(dhcp_ack, pkt, min(len, maxsize));
+}
+
+/* This gets called from do_bootefi_exec(). */
+int efi_net_register(void **handle)
+{
+ struct efi_net_obj *netobj;
+ struct efi_device_path_file_path dp_net = {
+ .dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ .dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+ .dp.length = sizeof(dp_net),
+ .str = { 'N', 'e', 't' },
+ };
+ struct efi_device_path_file_path dp_end = {
+ .dp.type = DEVICE_PATH_TYPE_END,
+ .dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
+ .dp.length = sizeof(dp_end),
+ };
+
+ if (!eth_get_dev()) {
+ /* No eth device active, don't expose any */
+ return 0;
+ }
+
+ /* We only expose the "active" eth device, so one is enough */
+ netobj = calloc(1, sizeof(*netobj));
+
+ /* Fill in object data */
+ netobj->parent.protocols[0].guid = &efi_net_guid;
+ netobj->parent.protocols[0].open = efi_return_handle;
+ netobj->parent.protocols[1].guid = &efi_guid_device_path;
+ netobj->parent.protocols[1].open = efi_net_open_dp;
+ netobj->parent.protocols[2].guid = &efi_pxe_guid;
+ netobj->parent.protocols[2].open = efi_net_open_pxe;
+ netobj->parent.handle = &netobj->net;
+ netobj->net.start = efi_net_start;
+ netobj->net.stop = efi_net_stop;
+ netobj->net.initialize = efi_net_initialize;
+ netobj->net.reset = efi_net_reset;
+ netobj->net.shutdown = efi_net_shutdown;
+ netobj->net.receive_filters = efi_net_receive_filters;
+ netobj->net.station_address = efi_net_station_address;
+ netobj->net.statistics = efi_net_statistics;
+ netobj->net.mcastiptomac = efi_net_mcastiptomac;
+ netobj->net.nvdata = efi_net_nvdata;
+ netobj->net.get_status = efi_net_get_status;
+ netobj->net.transmit = efi_net_transmit;
+ netobj->net.receive = efi_net_receive;
+ netobj->net.mode = &netobj->net_mode;
+ netobj->net_mode.state = EFI_NETWORK_STARTED;
+ netobj->dp[0] = dp_net;
+ netobj->dp[1] = dp_end;
+ memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
+ netobj->net_mode.max_packet_size = PKTSIZE;
+
+ netobj->pxe.mode = &netobj->pxe_mode;
+ if (dhcp_ack)
+ netobj->pxe_mode.dhcp_ack = *dhcp_ack;
+
+ /* Hook net up to the device list */
+ list_add_tail(&netobj->parent.link, &efi_obj_list);
+
+ if (handle)
+ *handle = &netobj->net;
+
+ return 0;
+}
/* RTC accessors are gone */
.ptr = &efi_runtime_services.get_time,
.patchto = &efi_device_error,
+ }, {
+ /* Clean up system table */
+ .ptr = &systab.con_in,
+ .patchto = NULL,
+ }, {
+ /* Clean up system table */
+ .ptr = &systab.con_out,
+ .patchto = NULL,
+ }, {
+ /* Clean up system table */
+ .ptr = &systab.std_err,
+ .patchto = NULL,
+ }, {
+ /* Clean up system table */
+ .ptr = &systab.boottime,
+ .patchto = NULL,
},
};
static char *bf;
static char zs;
+/* Current position in sprintf() output string */
+static char *outstr;
+
static void out(char c)
{
*bf++ = c;
out_dgt(dgt);
}
-int vprintf(const char *fmt, va_list va)
+int _vprintf(const char *fmt, va_list va, void (*putc)(const char ch))
{
char ch;
char *p;
if (ch != '%') {
putc(ch);
} else {
- char lz = 0;
- char w = 0;
+ bool lz = false;
+ int width = 0;
ch = *(fmt++);
if (ch == '0') {
}
if (ch >= '0' && ch <= '9') {
- w = 0;
+ width = 0;
while (ch >= '0' && ch <= '9') {
- w = (w * 10) + ch - '0';
+ width = (width * 10) + ch - '0';
ch = *fmt++;
}
}
zs = 0;
switch (ch) {
- case 0:
+ case '\0':
goto abort;
case 'u':
case 'd':
*bf = 0;
bf = p;
- while (*bf++ && w > 0)
- w--;
- while (w-- > 0)
+ while (*bf++ && width > 0)
+ width--;
+ while (width-- > 0)
putc(lz ? '0' : ' ');
if (p) {
while ((ch = *p++))
int ret;
va_start(va, fmt);
- ret = vprintf(fmt, va);
+ ret = _vprintf(fmt, va, putc);
+ va_end(va);
+
+ return ret;
+}
+
+static void putc_outstr(char ch)
+{
+ *outstr++ = ch;
+}
+
+/* Note that size is ignored */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+{
+ va_list va;
+ int ret;
+
+ va_start(va, fmt);
+ outstr = buf;
+ ret = _vprintf(fmt, va, putc_outstr);
va_end(va);
+ *outstr = '\0';
return ret;
}
If unset, timeout and maximum are hard-defined as 1 second
and 10 timouts per TFTP transfer.
+config BOOTP_PXE_CLIENTARCH
+ hex
+ default 0x16 if ARM64
+ default 0x15 if ARM
+ default 0 if X86
+
+config BOOTP_VCI_STRING
+ string
+ default "U-Boot.armv7" if CPU_V7 || CPU_V7M
+ default "U-Boot.armv8" if ARM64
+ default "U-Boot.arm" if ARM
+ default "U-Boot"
+
+config SPL_NET_VCI_STRING
+ string
+
endif # if NET
#include <common.h>
#include <command.h>
+#include <efi_loader.h>
#include <net.h>
#include <net/tftp.h>
#include "bootp.h"
e += vci_strlen; \
} while (0)
+static u8 *add_vci(u8 *e)
+{
+ char *vci = NULL;
+ char *env_vci = getenv("bootp_vci");
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)
+ vci = CONFIG_SPL_NET_VCI_STRING;
+#elif defined(CONFIG_BOOTP_VCI_STRING)
+ vci = CONFIG_BOOTP_VCI_STRING;
+#endif
+
+ if (env_vci)
+ vci = env_vci;
+
+ if (vci)
+ put_vci(e, vci);
+
+ return e;
+}
+
/*
* Initialize BOOTP extension fields in the request.
*/
{
u8 *start = e;
u8 *cnt;
-#if defined(CONFIG_BOOTP_PXE)
+#ifdef CONFIG_LIB_UUID
char *uuid;
- u16 clientarch;
#endif
+ int clientarch = -1;
#if defined(CONFIG_BOOTP_VENDOREX)
u8 *x;
}
#endif
-#if defined(CONFIG_BOOTP_PXE)
+#ifdef CONFIG_BOOTP_PXE_CLIENTARCH
clientarch = CONFIG_BOOTP_PXE_CLIENTARCH;
- *e++ = 93; /* Client System Architecture */
- *e++ = 2;
- *e++ = (clientarch >> 8) & 0xff;
- *e++ = clientarch & 0xff;
+#endif
+
+ if (getenv("bootp_arch"))
+ clientarch = getenv_ulong("bootp_arch", 16, clientarch);
+
+ if (clientarch > 0) {
+ *e++ = 93; /* Client System Architecture */
+ *e++ = 2;
+ *e++ = (clientarch >> 8) & 0xff;
+ *e++ = clientarch & 0xff;
+ }
*e++ = 94; /* Client Network Interface Identifier */
*e++ = 3;
*e++ = 0; /* major revision */
*e++ = 0; /* minor revision */
+#ifdef CONFIG_LIB_UUID
uuid = getenv("pxeuuid");
if (uuid) {
}
#endif
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)
- put_vci(e, CONFIG_SPL_NET_VCI_STRING);
-#elif defined(CONFIG_BOOTP_VCI_STRING)
- put_vci(e, CONFIG_BOOTP_VCI_STRING);
-#endif
+ e = add_vci(e);
#if defined(CONFIG_BOOTP_VENDOREX)
x = dhcp_vendorex_prep(e);
*e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff;
#endif
-#if defined(CONFIG_BOOTP_VCI_STRING) || \
- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING))
-#ifdef CONFIG_SPL_BUILD
- put_vci(e, CONFIG_SPL_NET_VCI_STRING);
-#else
- put_vci(e, CONFIG_BOOTP_VCI_STRING);
-#endif
-#endif
+ add_vci(e);
#if defined(CONFIG_BOOTP_SUBNETMASK)
*e++ = 1; /* Subnet mask request */
strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0) {
#endif /* CONFIG_SYS_BOOTFILE_PREFIX */
dhcp_packet_process_options(bp);
+ efi_net_set_dhcp_ack(pkt, len);
debug("TRANSITIONING TO REQUESTING STATE\n");
dhcp_state = REQUESTING;
/* Ethernet bcast address */
const u8 net_bcast_ethaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
const u8 net_null_ethaddr[6];
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
void (*push_packet)(void *, int len) = 0;
#endif
/* Network loop state */
if (len < ETHER_HDR_SIZE)
return;
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
if (push_packet) {
(*push_packet)(in_packet, len);
return;
#include <common.h>
#include <command.h>
+#include <efi_loader.h>
#include <mapmem.h>
#include <net.h>
#include <net/tftp.h>
printf("Load address: 0x%lx\n", load_addr);
puts("Loading: *\b");
tftp_state = STATE_SEND_RRQ;
+ efi_set_bootdev("Net", "", tftp_filename);
}
time_start = get_timer(0);
obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_I2C) += i2c.o
obj-$(CONFIG_LED) += led.o
+obj-$(CONFIG_DM_MAILBOX) += mailbox.o
obj-$(CONFIG_DM_MMC) += mmc.o
obj-$(CONFIG_DM_PCI) += pci.o
obj-$(CONFIG_RAM) += ram.o
obj-y += regmap.o
obj-$(CONFIG_REMOTEPROC) += remoteproc.o
-obj-$(CONFIG_RESET) += reset.o
+obj-$(CONFIG_SYSRESET) += sysreset.o
obj-$(CONFIG_DM_RTC) += rtc.o
obj-$(CONFIG_DM_SPI_FLASH) += sf.o
obj-$(CONFIG_DM_SPI) += spi.o
--- /dev/null
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <asm/mbox.h>
+#include <test/ut.h>
+
+static int dm_test_mailbox(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ uint32_t msg;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "mbox-test", &dev));
+ ut_assertok(sandbox_mbox_test_get(dev));
+
+ ut_asserteq(-ETIMEDOUT, sandbox_mbox_test_recv(dev, &msg));
+ ut_assertok(sandbox_mbox_test_send(dev, 0xaaff9955UL));
+ ut_assertok(sandbox_mbox_test_recv(dev, &msg));
+ ut_asserteq(msg, 0xaaff9955UL ^ SANDBOX_MBOX_PING_XOR);
+ ut_asserteq(-ETIMEDOUT, sandbox_mbox_test_recv(dev, &msg));
+
+ ut_assertok(sandbox_mbox_test_free(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_mailbox, DM_TESTF_SCAN_FDT);
+++ /dev/null
-/*
- * Copyright (C) 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <reset.h>
-#include <asm/state.h>
-#include <asm/test.h>
-#include <dm/test.h>
-#include <test/ut.h>
-
-/* Test that we can use particular reset devices */
-static int dm_test_reset_base(struct unit_test_state *uts)
-{
- struct sandbox_state *state = state_get_current();
- struct udevice *dev;
-
- /* Device 0 is the platform data device - it should never respond */
- ut_assertok(uclass_get_device(UCLASS_RESET, 0, &dev));
- ut_asserteq(-ENODEV, reset_request(dev, RESET_WARM));
- ut_asserteq(-ENODEV, reset_request(dev, RESET_COLD));
- ut_asserteq(-ENODEV, reset_request(dev, RESET_POWER));
-
- /* Device 1 is the warm reset device */
- ut_assertok(uclass_get_device(UCLASS_RESET, 1, &dev));
- ut_asserteq(-EACCES, reset_request(dev, RESET_WARM));
- ut_asserteq(-ENOSYS, reset_request(dev, RESET_COLD));
- ut_asserteq(-ENOSYS, reset_request(dev, RESET_POWER));
-
- state->reset_allowed[RESET_WARM] = true;
- ut_asserteq(-EINPROGRESS, reset_request(dev, RESET_WARM));
- state->reset_allowed[RESET_WARM] = false;
-
- /* Device 2 is the cold reset device */
- ut_assertok(uclass_get_device(UCLASS_RESET, 2, &dev));
- ut_asserteq(-ENOSYS, reset_request(dev, RESET_WARM));
- ut_asserteq(-EACCES, reset_request(dev, RESET_COLD));
- state->reset_allowed[RESET_POWER] = false;
- ut_asserteq(-EACCES, reset_request(dev, RESET_POWER));
- state->reset_allowed[RESET_POWER] = true;
-
- return 0;
-}
-DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-
-/* Test that we can walk through the reset devices */
-static int dm_test_reset_walk(struct unit_test_state *uts)
-{
- struct sandbox_state *state = state_get_current();
-
- /* If we generate a power reset, we will exit sandbox! */
- state->reset_allowed[RESET_POWER] = false;
- ut_asserteq(-EACCES, reset_walk(RESET_WARM));
- ut_asserteq(-EACCES, reset_walk(RESET_COLD));
- ut_asserteq(-EACCES, reset_walk(RESET_POWER));
-
- /*
- * Enable cold reset - this should make cold reset work, plus a warm
- * reset should be promoted to cold, since this is the next step
- * along.
- */
- state->reset_allowed[RESET_COLD] = true;
- ut_asserteq(-EINPROGRESS, reset_walk(RESET_WARM));
- ut_asserteq(-EINPROGRESS, reset_walk(RESET_COLD));
- ut_asserteq(-EACCES, reset_walk(RESET_POWER));
- state->reset_allowed[RESET_COLD] = false;
- state->reset_allowed[RESET_POWER] = true;
-
- return 0;
-}
-DM_TEST(dm_test_reset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
--- /dev/null
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <sysreset.h>
+#include <asm/state.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Test that we can use particular sysreset devices */
+static int dm_test_sysreset_base(struct unit_test_state *uts)
+{
+ struct sandbox_state *state = state_get_current();
+ struct udevice *dev;
+
+ /* Device 0 is the platform data device - it should never respond */
+ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 0, &dev));
+ ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_WARM));
+ ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_COLD));
+ ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_POWER));
+
+ /* Device 1 is the warm sysreset device */
+ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev));
+ ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM));
+ ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD));
+ ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER));
+
+ state->sysreset_allowed[SYSRESET_WARM] = true;
+ ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM));
+ state->sysreset_allowed[SYSRESET_WARM] = false;
+
+ /* Device 2 is the cold sysreset device */
+ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev));
+ ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM));
+ ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD));
+ state->sysreset_allowed[SYSRESET_POWER] = false;
+ ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_POWER));
+ state->sysreset_allowed[SYSRESET_POWER] = true;
+
+ return 0;
+}
+DM_TEST(dm_test_sysreset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can walk through the sysreset devices */
+static int dm_test_sysreset_walk(struct unit_test_state *uts)
+{
+ struct sandbox_state *state = state_get_current();
+
+ /* If we generate a power sysreset, we will exit sandbox! */
+ state->sysreset_allowed[SYSRESET_POWER] = false;
+ ut_asserteq(-EACCES, sysreset_walk(SYSRESET_WARM));
+ ut_asserteq(-EACCES, sysreset_walk(SYSRESET_COLD));
+ ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER));
+
+ /*
+ * Enable cold system reset - this should make cold system reset work,
+ * plus a warm system reset should be promoted to cold, since this is
+ * the next step along.
+ */
+ state->sysreset_allowed[SYSRESET_COLD] = true;
+ ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_WARM));
+ ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_COLD));
+ ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER));
+ state->sysreset_allowed[SYSRESET_COLD] = false;
+ state->sysreset_allowed[SYSRESET_POWER] = true;
+
+ return 0;
+}
+DM_TEST(dm_test_sysreset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
self.console.disable_check_count[self.check_type] -= 1
self.console.eval_bad_patterns()
+class ConsoleSetupTimeout(object):
+ """Context manager (for Python's with statement) that temporarily sets up
+ timeout for specific command. This is useful when execution time is greater
+ then default 30s."""
+
+ def __init__(self, console, timeout):
+ self.p = console.p
+ self.orig_timeout = self.p.timeout
+ self.p.timeout = timeout
+
+ def __enter__(self):
+ return self
+
+ def __exit__(self, extype, value, traceback):
+ self.p.timeout = self.orig_timeout
+
class ConsoleBase(object):
"""The interface through which test functions interact with the U-Boot
console. This primarily involves executing shell commands, capturing their
"""
return ConsoleDisableCheck(self, check_type)
+
+ def temporary_timeout(self, timeout):
+ """Temporarily set up different timeout for commands.
+
+ Create a new context manager (for use with the "with" statement) which
+ temporarily change timeout.
+
+ Args:
+ timeout: Time in milliseconds.
+
+ Returns:
+ A context manager object.
+ """
+
+ return ConsoleSetupTimeout(self, timeout)
import pytest
import sys
import time
+import pytest
def md5sum_data(data):
"""Calculate the MD5 hash of some data.
/atmel_pmecc_params
+/bin2header
/bmp_logo
/envcrc
/fdtgrep
#include "fw_env.h"
-struct common_args common_args;
-struct printenv_args printenv_args;
-struct setenv_args setenv_args;
-
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define min(x, y) ({ \
#define CUR_ENVSIZE ENVSIZE(dev_current)
-#define ENV_SIZE getenvsize()
+static unsigned long usable_envsize;
+#define ENV_SIZE usable_envsize
struct env_image_single {
uint32_t crc; /* CRC32 over data bytes */
.flag_scheme = FLAG_NONE,
};
-static int env_aes_cbc_crypt(char *data, const int enc);
+static int env_aes_cbc_crypt(char *data, const int enc, uint8_t *key);
static int HaveRedundEnv = 0;
static int flash_io (int mode);
static char *envmatch (char * s1, char * s2);
-static int parse_config (void);
+static int parse_config(struct env_opts *opts);
#if defined(CONFIG_FILE)
static int get_config (char *);
#endif
-static inline ulong getenvsize (void)
-{
- ulong rc = CUR_ENVSIZE - sizeof(uint32_t);
-
- if (HaveRedundEnv)
- rc -= sizeof (char);
-
- if (common_args.aes_flag)
- rc &= ~(AES_KEY_LENGTH - 1);
-
- return rc;
-}
static char *skip_chars(char *s)
{
* Print the current definition of one, or more, or all
* environment variables
*/
-int fw_printenv (int argc, char *argv[])
+int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
{
char *env, *nxt;
int i, rc = 0;
- if (fw_env_open())
+ if (fw_env_open(opts))
return -1;
if (argc == 0) { /* Print all env variables */
return 0;
}
- if (printenv_args.name_suppress && argc != 1) {
+ if (value_only && argc != 1) {
fprintf(stderr,
"## Error: `-n' option requires exactly one argument\n");
return -1;
}
val = envmatch (name, env);
if (val) {
- if (!printenv_args.name_suppress) {
+ if (!value_only) {
fputs (name, stdout);
putc ('=', stdout);
}
return rc;
}
-int fw_env_close(void)
+int fw_env_close(struct env_opts *opts)
{
int ret;
- if (common_args.aes_flag) {
- ret = env_aes_cbc_crypt(environment.data, 1);
+
+ if (opts->aes_flag) {
+ ret = env_aes_cbc_crypt(environment.data, 1,
+ opts->aes_key);
if (ret) {
fprintf(stderr,
"Error: can't encrypt env for flash\n");
* modified or deleted
*
*/
-int fw_setenv(int argc, char *argv[])
+int fw_setenv(int argc, char *argv[], struct env_opts *opts)
{
int i;
size_t len;
return -1;
}
- if (fw_env_open()) {
+ if (fw_env_open(opts)) {
fprintf(stderr, "Error: environment not initialized\n");
return -1;
}
free(value);
- return fw_env_close();
+ return fw_env_close(opts);
}
/*
* 0 - OK
* -1 - Error
*/
-int fw_parse_script(char *fname)
+int fw_parse_script(char *fname, struct env_opts *opts)
{
FILE *fp;
char dump[1024]; /* Maximum line length in the file */
int len;
int ret = 0;
- if (fw_env_open()) {
+ if (fw_env_open(opts)) {
fprintf(stderr, "Error: environment not initialized\n");
return -1;
}
if (strcmp(fname, "-") != 0)
fclose(fp);
- ret |= fw_env_close();
+ ret |= fw_env_close(opts);
return ret;
-
}
/*
}
/* Encrypt or decrypt the environment before writing or reading it. */
-static int env_aes_cbc_crypt(char *payload, const int enc)
+static int env_aes_cbc_crypt(char *payload, const int enc, uint8_t *key)
{
uint8_t *data = (uint8_t *)payload;
- const int len = getenvsize();
+ const int len = usable_envsize;
uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
uint32_t aes_blocks;
/* First we expand the key. */
- aes_expand_key(common_args.aes_key, key_exp);
+ aes_expand_key(key, key_exp);
/* Calculate the number of AES blocks to encrypt. */
aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH);
/*
* Prevent confusion if running from erased flash memory
*/
-int fw_env_open(void)
+int fw_env_open(struct env_opts *opts)
{
int crc0, crc0_ok;
unsigned char flag0;
struct env_image_single *single;
struct env_image_redundant *redundant;
- if (parse_config ()) /* should fill envdevices */
+ if (parse_config(opts)) /* should fill envdevices */
return -1;
addr0 = calloc(1, CUR_ENVSIZE);
crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
- if (common_args.aes_flag) {
- ret = env_aes_cbc_crypt(environment.data, 0);
+ if (opts->aes_flag) {
+ ret = env_aes_cbc_crypt(environment.data, 0,
+ opts->aes_key);
if (ret)
return ret;
}
crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
- if (common_args.aes_flag) {
- ret = env_aes_cbc_crypt(redundant->data, 0);
+ if (opts->aes_flag) {
+ ret = env_aes_cbc_crypt(redundant->data, 0,
+ opts->aes_key);
if (ret)
return ret;
}
}
-static int parse_config ()
+static int parse_config(struct env_opts *opts)
{
struct stat st;
common_args.config_file = CONFIG_FILE;
/* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */
- if (get_config(common_args.config_file)) {
+ if (get_config(opts->config_file)) {
fprintf(stderr, "Cannot parse config file '%s': %m\n",
- common_args.config_file);
+ opts->config_file);
return -1;
}
#else
DEVNAME (1), strerror (errno));
return -1;
}
+
+ if (HaveRedundEnv && ENVSIZE(0) != ENVSIZE(1)) {
+ ENVSIZE(0) = ENVSIZE(1) = min(ENVSIZE(0), ENVSIZE(1));
+ fprintf(stderr,
+ "Redundant environments have inequal size, set to 0x%08lx\n",
+ ENVSIZE(1));
+ }
+
+ usable_envsize = CUR_ENVSIZE - sizeof(uint32_t);
+ if (HaveRedundEnv)
+ usable_envsize -= sizeof(char);
+
+ if (opts->aes_flag)
+ usable_envsize &= ~(AES_KEY_LENGTH - 1);
+
return 0;
}
"bootm"
#endif
-struct common_args {
+struct env_opts {
#ifdef CONFIG_FILE
char *config_file;
#endif
- uint8_t aes_key[AES_KEY_LENGTH];
int aes_flag; /* Is AES encryption used? */
+ uint8_t aes_key[AES_KEY_LENGTH];
};
-extern struct common_args common_args;
-
-struct printenv_args {
- int name_suppress;
-};
-extern struct printenv_args printenv_args;
-
-struct setenv_args {
- char *script_file;
-};
-extern struct setenv_args setenv_args;
int parse_aes_key(char *key, uint8_t *bin_key);
-extern int fw_printenv(int argc, char *argv[]);
-extern char *fw_getenv (char *name);
-extern int fw_setenv (int argc, char *argv[]);
-extern int fw_parse_script(char *fname);
-extern int fw_env_open(void);
-extern int fw_env_write(char *name, char *value);
-extern int fw_env_close(void);
+int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts);
+char *fw_getenv(char *name);
+int fw_setenv(int argc, char *argv[], struct env_opts *opts);
+int fw_parse_script(char *fname, struct env_opts *opts);
+int fw_env_open(struct env_opts *opts);
+int fw_env_write(char *name, char *value);
+int fw_env_close(struct env_opts *opts);
-extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned);
+unsigned long crc32(unsigned long, const unsigned char *, unsigned);
{NULL, 0, NULL, 0}
};
+static struct env_opts env_opts;
+
+/* setenv options */
+static int noheader;
+
+/* getenv options */
+static char *script_file;
+
void usage_printenv(void)
{
int c;
#ifdef CONFIG_FILE
- common_args.config_file = CONFIG_FILE;
+ env_opts.config_file = CONFIG_FILE;
#endif
while ((c = getopt_long(argc, argv, ":a:c:h", long_options, NULL)) !=
EOF) {
switch (c) {
case 'a':
- if (parse_aes_key(optarg, common_args.aes_key)) {
+ if (parse_aes_key(optarg, env_opts.aes_key)) {
fprintf(stderr, "AES key parse error\n");
exit(EXIT_FAILURE);
}
- common_args.aes_flag = 1;
+ env_opts.aes_flag = 1;
break;
#ifdef CONFIG_FILE
case 'c':
- common_args.config_file = optarg;
+ env_opts.config_file = optarg;
break;
#endif
case 'h':
EOF) {
switch (c) {
case 'n':
- printenv_args.name_suppress = 1;
+ noheader = 1;
break;
case 'a':
case 'c':
EOF) {
switch (c) {
case 's':
- setenv_args.script_file = optarg;
+ script_file = optarg;
break;
case 'a':
case 'c':
}
if (do_printenv) {
- if (fw_printenv(argc, argv) != 0)
+ if (fw_printenv(argc, argv, noheader, &env_opts) != 0)
retval = EXIT_FAILURE;
} else {
- if (!setenv_args.script_file) {
- if (fw_setenv(argc, argv) != 0)
+ if (!script_file) {
+ if (fw_setenv(argc, argv, &env_opts) != 0)
retval = EXIT_FAILURE;
} else {
- if (fw_parse_script(setenv_args.script_file) != 0)
+ if (fw_parse_script(script_file, &env_opts) != 0)
retval = EXIT_FAILURE;
}
}
import multiprocessing
import optparse
import os
-import subprocess
import sys
import tempfile
import time
static uint32_t header;
-static int rkimage_check_params(struct image_tool_params *params)
-{
- return 0;
-}
-
static int rkimage_verify_header(unsigned char *buf, int size,
struct image_tool_params *params)
{
"Rockchip Boot Image support",
4,
&header,
- rkimage_check_params,
+ rkcommon_check_params,
rkimage_verify_header,
rkimage_print_header,
rkimage_set_header,
projects / people / ms / u-boot.git / commitdiff
