]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
ARM: rmobile: salvator-x: Add DVFS and PMIC support
authorMarek Vasut <marek.vasut@gmail.com>
Sat, 13 May 2017 13:57:48 +0000 (15:57 +0200)
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Sun, 21 May 2017 19:38:27 +0000 (04:38 +0900)
Add support for rebooting the board using the ROHM BD9571MWV I2C PMIC,
but keep the CPU reboot option as a fallback.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
board/renesas/salvator-x/salvator-x.c
include/configs/salvator-x.h

index 38ff99a17c7ab8084b7ecc95bb11ba6c743d84b3..acc541df0cfc6703cba10052e69361459ac62870 100644 (file)
@@ -50,6 +50,7 @@ void s_init(void)
 #define TMU1_MSTP124           BIT(24) /* non-secure */
 #define SCIF2_MSTP310          BIT(10) /* SCIF2 */
 #define ETHERAVB_MSTP812       BIT(12)
+#define DVFS_MSTP926           BIT(26)
 #define SD0_MSTP314            BIT(14)
 #define SD1_MSTP313            BIT(13)
 #define SD2_MSTP312            BIT(12) /* either MMC0 */
@@ -78,6 +79,10 @@ int board_early_init_f(void)
        writel(0, SD2CKCR);
        writel(0, SD3CKCR);
 
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+       /* DVFS for reset */
+       mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
        return 0;
 }
 
@@ -235,8 +240,12 @@ const struct rmobile_sysinfo sysinfo = {
 
 void reset_cpu(ulong addr)
 {
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+       i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
+#else
        /* only CA57 ? */
        writel(RST_CODE, RST_CA57RESCNT);
+#endif
 }
 
 static const struct sh_serial_platdata serial_platdata = {
index b5a98d6db2b0ecb3943fc5a37f023681eea7a468..0e5c130b13a47f6bbb4829d596d4276ccb856935 100644 (file)
 #define GICD_BASE      0xF1010000
 #define GICC_BASE      0xF1020000
 
+/* i2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE           0x60
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS      1
+#define CONFIG_SYS_I2C_SH_SPEED0       400000
+#define CONFIG_SH_I2C_DATA_HIGH                4
+#define CONFIG_SH_I2C_DATA_LOW         5
+#define CONFIG_SH_I2C_CLOCK            10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR    0x30
+
 /* SDHI */
 #define CONFIG_SH_SDHI_FREQ            200000000