src/patches/u-boot/rockchip/add-nanopi-r2c-and-orangepi-r1-plus-lts.patch

   1 diff -Naur u-boot-2022.10.org/arch/arm/dts/Makefile u-boot-2022.10/arch/arm/dts/Makefile
   2 --- u-boot-2022.10.org/arch/arm/dts/Makefile    2022-10-03 19:25:32.000000000 +0000
   3 +++ u-boot-2022.10/arch/arm/dts/Makefile        2023-04-27 16:16:35.697116372 +0000
   4 @@ -124,7 +124,9 @@
   5
   6  dtb-$(CONFIG_ROCKCHIP_RK3328) += \
   7         rk3328-evb.dtb \
   8 +       rk3328-nanopi-r2c.dtb \
   9         rk3328-nanopi-r2s.dtb \
  10 +       rk3328-orangepi-r1-plus-lts.dtb \
  11         rk3328-roc-cc.dtb \
  12         rk3328-rock64.dtb \
  13         rk3328-rock-pi-e.dtb
  14 diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
  15 --- u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi       1970-01-01 00:00:00.000000000 +0000
  16 +++ u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi   2023-04-22 15:07:54.544953841 +0000
  17 @@ -0,0 +1,7 @@
  18 +// SPDX-License-Identifier: GPL-2.0+
  19 +/*
  20 + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
  21 + * (http://www.friendlyarm.com)
  22 + */
  23 +
  24 +#include "rk3328-nanopi-r2s-u-boot.dtsi"
  25 diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c.dts u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c.dts
  26 --- u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c.dts       1970-01-01 00:00:00.000000000 +0000
  27 +++ u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c.dts   2023-04-22 15:07:07.861614679 +0000
  28 @@ -0,0 +1,27 @@
  29 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  30 +/*
  31 + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
  32 + * (http://www.friendlyarm.com)
  33 + */
  34 +
  35 +/dts-v1/;
  36 +#include "rk3328-nanopi-r2s.dts"
  37 +
  38 +/ {
  39 +       model = "FriendlyElec NanoPi R2C";
  40 +       compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
  41 +};
  42 +
  43 +&emmc {
  44 +       bus-width = <8>;
  45 +       cap-mmc-highspeed;
  46 +       max-frequency = <150000000>;
  47 +       mmc-ddr-1_8v;
  48 +       mmc-hs200-1_8v;
  49 +       non-removable;
  50 +       pinctrl-names = "default";
  51 +       pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
  52 +       vmmc-supply = <&vcc_io_33>;
  53 +       vqmmc-supply = <&vcc18_emmc>;
  54 +       status = "okay";
  55 +};
  56 diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi u-boot-2022.10/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
  57 --- u-boot-2022.10.org/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi     1970-01-01 00:00:00.000000000 +0000
  58 +++ u-boot-2022.10/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi 2023-04-27 16:12:50.320850145 +0000
  59 @@ -0,0 +1,6 @@
  60 +// SPDX-License-Identifier: GPL-2.0+
  61 +/*
  62 + */
  63 +
  64 +#include "rk3328-nanopi-r2s-u-boot.dtsi"
  65 +#include "rk3328-sdram-lpddr3-666.dtsi"
  66 diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts u-boot-2022.10/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
  67 --- u-boot-2022.10.org/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts     1970-01-01 00:00:00.000000000 +0000
  68 +++ u-boot-2022.10/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts 2023-04-27 16:14:56.582755127 +0000
  69 @@ -0,0 +1,12 @@
  70 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  71 +/*
  72 + */
  73 +
  74 +/dts-v1/;
  75 +#include "rk3328-nanopi-r2s.dts"
  76 +
  77 +/ {
  78 +       model = "Xunlong Orange Pi R1 Plus";
  79 +       compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
  80 +};
  81 +
  82 diff -Naur u-boot-2022.10.org/configs/nanopi-r2c-rk3328_defconfig u-boot-2022.10/configs/nanopi-r2c-rk3328_defconfig
  83 --- u-boot-2022.10.org/configs/nanopi-r2c-rk3328_defconfig      1970-01-01 00:00:00.000000000 +0000
  84 +++ u-boot-2022.10/configs/nanopi-r2c-rk3328_defconfig  2023-04-22 15:09:20.843584447 +0000
  85 @@ -0,0 +1,112 @@
  86 +CONFIG_ARM=y
  87 +CONFIG_SKIP_LOWLEVEL_INIT=y
  88 +CONFIG_COUNTER_FREQUENCY=24000000
  89 +CONFIG_ARCH_ROCKCHIP=y
  90 +CONFIG_SYS_TEXT_BASE=0x00200000
  91 +CONFIG_SPL_GPIO=y
  92 +CONFIG_NR_DRAM_BANKS=1
  93 +CONFIG_ENV_OFFSET=0x3F8000
  94 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
  95 +CONFIG_ROCKCHIP_RK3328=y
  96 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
  97 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
  98 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
  99 +CONFIG_SPL_DRIVERS_MISC=y
 100 +CONFIG_SPL_STACK_R_ADDR=0x600000
 101 +CONFIG_DEBUG_UART_BASE=0xFF130000
 102 +CONFIG_DEBUG_UART_CLOCK=24000000
 103 +CONFIG_SYS_LOAD_ADDR=0x800800
 104 +CONFIG_DEBUG_UART=y
 105 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 106 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
 107 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 108 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 109 +CONFIG_FIT=y
 110 +CONFIG_FIT_VERBOSE=y
 111 +CONFIG_SPL_LOAD_FIT=y
 112 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
 113 +# CONFIG_DISPLAY_CPUINFO is not set
 114 +CONFIG_DISPLAY_BOARDINFO_LATE=y
 115 +CONFIG_MISC_INIT_R=y
 116 +CONFIG_SPL_MAX_SIZE=0x40000
 117 +CONFIG_SPL_PAD_TO=0x7f8000
 118 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 119 +CONFIG_SPL_BSS_START_ADDR=0x2000000
 120 +CONFIG_SPL_BSS_MAX_SIZE=0x2000
 121 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 122 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 123 +CONFIG_SPL_STACK=0x400000
 124 +CONFIG_SPL_STACK_R=y
 125 +CONFIG_SPL_I2C=y
 126 +CONFIG_SPL_POWER=y
 127 +CONFIG_SPL_ATF=y
 128 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 129 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 130 +CONFIG_CMD_BOOTZ=y
 131 +CONFIG_CMD_GPT=y
 132 +CONFIG_CMD_MMC=y
 133 +CONFIG_CMD_USB=y
 134 +# CONFIG_CMD_SETEXPR is not set
 135 +CONFIG_CMD_TIME=y
 136 +CONFIG_SPL_OF_CONTROL=y
 137 +CONFIG_TPL_OF_CONTROL=y
 138 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 139 +CONFIG_TPL_OF_PLATDATA=y
 140 +CONFIG_ENV_IS_IN_MMC=y
 141 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 142 +CONFIG_SYS_MMC_ENV_DEV=1
 143 +CONFIG_NET_RANDOM_ETHADDR=y
 144 +CONFIG_TPL_DM=y
 145 +CONFIG_REGMAP=y
 146 +CONFIG_SPL_REGMAP=y
 147 +CONFIG_TPL_REGMAP=y
 148 +CONFIG_SYSCON=y
 149 +CONFIG_SPL_SYSCON=y
 150 +CONFIG_TPL_SYSCON=y
 151 +CONFIG_CLK=y
 152 +CONFIG_SPL_CLK=y
 153 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
 154 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 155 +CONFIG_ROCKCHIP_GPIO=y
 156 +CONFIG_SYS_I2C_ROCKCHIP=y
 157 +CONFIG_MMC_DW=y
 158 +CONFIG_MMC_DW_ROCKCHIP=y
 159 +CONFIG_SF_DEFAULT_SPEED=20000000
 160 +CONFIG_ETH_DESIGNWARE=y
 161 +CONFIG_GMAC_ROCKCHIP=y
 162 +CONFIG_PINCTRL=y
 163 +CONFIG_SPL_PINCTRL=y
 164 +CONFIG_DM_PMIC=y
 165 +CONFIG_PMIC_RK8XX=y
 166 +CONFIG_SPL_PMIC_RK8XX=y
 167 +CONFIG_SPL_DM_REGULATOR=y
 168 +CONFIG_REGULATOR_PWM=y
 169 +CONFIG_DM_REGULATOR_FIXED=y
 170 +CONFIG_SPL_DM_REGULATOR_FIXED=y
 171 +CONFIG_REGULATOR_RK8XX=y
 172 +CONFIG_PWM_ROCKCHIP=y
 173 +CONFIG_RAM=y
 174 +CONFIG_SPL_RAM=y
 175 +CONFIG_TPL_RAM=y
 176 +CONFIG_DM_RESET=y
 177 +CONFIG_BAUDRATE=1500000
 178 +CONFIG_DEBUG_UART_SHIFT=2
 179 +CONFIG_SYSINFO=y
 180 +CONFIG_SYSRESET=y
 181 +# CONFIG_TPL_SYSRESET is not set
 182 +CONFIG_USB=y
 183 +CONFIG_USB_XHCI_HCD=y
 184 +CONFIG_USB_XHCI_DWC3=y
 185 +CONFIG_USB_EHCI_HCD=y
 186 +CONFIG_USB_EHCI_GENERIC=y
 187 +CONFIG_USB_OHCI_HCD=y
 188 +CONFIG_USB_OHCI_GENERIC=y
 189 +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
 190 +CONFIG_USB_DWC2=y
 191 +CONFIG_USB_DWC3=y
 192 +# CONFIG_USB_DWC3_GADGET is not set
 193 +CONFIG_USB_GADGET=y
 194 +CONFIG_USB_GADGET_DWC2_OTG=y
 195 +CONFIG_SPL_TINY_MEMSET=y
 196 +CONFIG_TPL_TINY_MEMSET=y
 197 +CONFIG_ERRNO_STR=y
 198 diff -Naur u-boot-2022.10.org/configs/orangepi-r1-plus-lts-rk3328_defconfig u-boot-2022.10/configs/orangepi-r1-plus-lts-rk3328_defconfig
 199 --- u-boot-2022.10.org/configs/orangepi-r1-plus-lts-rk3328_defconfig    1970-01-01 00:00:00.000000000 +0000
 200 +++ u-boot-2022.10/configs/orangepi-r1-plus-lts-rk3328_defconfig        2023-04-27 16:19:41.122065498 +0000
 201 @@ -0,0 +1,112 @@
 202 +CONFIG_ARM=y
 203 +CONFIG_SKIP_LOWLEVEL_INIT=y
 204 +CONFIG_COUNTER_FREQUENCY=24000000
 205 +CONFIG_ARCH_ROCKCHIP=y
 206 +CONFIG_SYS_TEXT_BASE=0x00200000
 207 +CONFIG_SPL_GPIO=y
 208 +CONFIG_NR_DRAM_BANKS=1
 209 +CONFIG_ENV_OFFSET=0x3F8000
 210 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
 211 +CONFIG_ROCKCHIP_RK3328=y
 212 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 213 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
 214 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
 215 +CONFIG_SPL_DRIVERS_MISC=y
 216 +CONFIG_SPL_STACK_R_ADDR=0x600000
 217 +CONFIG_DEBUG_UART_BASE=0xFF130000
 218 +CONFIG_DEBUG_UART_CLOCK=24000000
 219 +CONFIG_SYS_LOAD_ADDR=0x800800
 220 +CONFIG_DEBUG_UART=y
 221 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 222 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
 223 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 224 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 225 +CONFIG_FIT=y
 226 +CONFIG_FIT_VERBOSE=y
 227 +CONFIG_SPL_LOAD_FIT=y
 228 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
 229 +# CONFIG_DISPLAY_CPUINFO is not set
 230 +CONFIG_DISPLAY_BOARDINFO_LATE=y
 231 +CONFIG_MISC_INIT_R=y
 232 +CONFIG_SPL_MAX_SIZE=0x40000
 233 +CONFIG_SPL_PAD_TO=0x7f8000
 234 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 235 +CONFIG_SPL_BSS_START_ADDR=0x2000000
 236 +CONFIG_SPL_BSS_MAX_SIZE=0x2000
 237 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 238 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 239 +CONFIG_SPL_STACK=0x400000
 240 +CONFIG_SPL_STACK_R=y
 241 +CONFIG_SPL_I2C=y
 242 +CONFIG_SPL_POWER=y
 243 +CONFIG_SPL_ATF=y
 244 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 245 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 246 +CONFIG_CMD_BOOTZ=y
 247 +CONFIG_CMD_GPT=y
 248 +CONFIG_CMD_MMC=y
 249 +CONFIG_CMD_USB=y
 250 +# CONFIG_CMD_SETEXPR is not set
 251 +CONFIG_CMD_TIME=y
 252 +CONFIG_SPL_OF_CONTROL=y
 253 +CONFIG_TPL_OF_CONTROL=y
 254 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 255 +CONFIG_TPL_OF_PLATDATA=y
 256 +CONFIG_ENV_IS_IN_MMC=y
 257 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 258 +CONFIG_SYS_MMC_ENV_DEV=1
 259 +CONFIG_NET_RANDOM_ETHADDR=y
 260 +CONFIG_TPL_DM=y
 261 +CONFIG_REGMAP=y
 262 +CONFIG_SPL_REGMAP=y
 263 +CONFIG_TPL_REGMAP=y
 264 +CONFIG_SYSCON=y
 265 +CONFIG_SPL_SYSCON=y
 266 +CONFIG_TPL_SYSCON=y
 267 +CONFIG_CLK=y
 268 +CONFIG_SPL_CLK=y
 269 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
 270 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 271 +CONFIG_ROCKCHIP_GPIO=y
 272 +CONFIG_SYS_I2C_ROCKCHIP=y
 273 +CONFIG_MMC_DW=y
 274 +CONFIG_MMC_DW_ROCKCHIP=y
 275 +CONFIG_SF_DEFAULT_SPEED=20000000
 276 +CONFIG_ETH_DESIGNWARE=y
 277 +CONFIG_GMAC_ROCKCHIP=y
 278 +CONFIG_PINCTRL=y
 279 +CONFIG_SPL_PINCTRL=y
 280 +CONFIG_DM_PMIC=y
 281 +CONFIG_PMIC_RK8XX=y
 282 +CONFIG_SPL_PMIC_RK8XX=y
 283 +CONFIG_SPL_DM_REGULATOR=y
 284 +CONFIG_REGULATOR_PWM=y
 285 +CONFIG_DM_REGULATOR_FIXED=y
 286 +CONFIG_SPL_DM_REGULATOR_FIXED=y
 287 +CONFIG_REGULATOR_RK8XX=y
 288 +CONFIG_PWM_ROCKCHIP=y
 289 +CONFIG_RAM=y
 290 +CONFIG_SPL_RAM=y
 291 +CONFIG_TPL_RAM=y
 292 +CONFIG_DM_RESET=y
 293 +CONFIG_BAUDRATE=1500000
 294 +CONFIG_DEBUG_UART_SHIFT=2
 295 +CONFIG_SYSINFO=y
 296 +CONFIG_SYSRESET=y
 297 +# CONFIG_TPL_SYSRESET is not set
 298 +CONFIG_USB=y
 299 +CONFIG_USB_XHCI_HCD=y
 300 +CONFIG_USB_XHCI_DWC3=y
 301 +CONFIG_USB_EHCI_HCD=y
 302 +CONFIG_USB_EHCI_GENERIC=y
 303 +CONFIG_USB_OHCI_HCD=y
 304 +CONFIG_USB_OHCI_GENERIC=y
 305 +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
 306 +CONFIG_USB_DWC2=y
 307 +CONFIG_USB_DWC3=y
 308 +# CONFIG_USB_DWC3_GADGET is not set
 309 +CONFIG_USB_GADGET=y
 310 +CONFIG_USB_GADGET_DWC2_OTG=y
 311 +CONFIG_SPL_TINY_MEMSET=y
 312 +CONFIG_TPL_TINY_MEMSET=y
 313 +CONFIG_ERRNO_STR=y