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Fix sometimes-uninitialized warning in gdbscm_value_address
[thirdparty/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
2571583a 2 Copyright (C) 1998-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca
NC		 3161 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3162 asection *srelplt2;
00a97672 3163
0855e32b
NS		 3164 /* The offset into splt of the PLT entry for the TLS descriptor
3165 resolver. Special values are 0, if not necessary (or not found
3166 to be necessary yet), and -1 if needed but not determined
3167 yet. */
3168 bfd_vma dt_tlsdesc_plt;
3169
3170 /* The offset into sgot of the GOT entry used by the PLT entry
3171 above. */
b38cadfb 3172 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3173
3174 /* Offset in .plt section of tls_arm_trampoline. */
3175 bfd_vma tls_trampoline;
3176
906e58ca
NC		 3177 /* Data for R_ARM_TLS_LDM32 relocations. */
3178 union
3179 {
3180 bfd_signed_vma refcount;
3181 bfd_vma offset;
3182 } tls_ldm_got;
b7693d02 3183
87d72d41
AM		 3184 /* Small local sym cache. */
3185 struct sym_cache sym_cache;
906e58ca
NC		 3186
3187 /* For convenience in allocate_dynrelocs. */
3188 bfd * obfd;
3189
0855e32b
NS		 3190 /* The amount of space used by the reserved portion of the sgotplt
3191 section, plus whatever space is used by the jump slots. */
3192 bfd_vma sgotplt_jump_table_size;
3193
906e58ca
NC		 3194 /* The stub hash table. */
3195 struct bfd_hash_table stub_hash_table;
3196
3197 /* Linker stub bfd. */
3198 bfd *stub_bfd;
3199
3200 /* Linker call-backs. */
6bde4c52
TP		 3201 asection * (*add_stub_section) (const char *, asection *, asection *,
3202 unsigned int);
906e58ca
NC		 3203 void (*layout_sections_again) (void);
3204
3205 /* Array to keep track of which stub sections have been created, and
3206 information on stub grouping. */
21d799b5 3207 struct map_stub *stub_group;
906e58ca 3208
4ba2ef8f
TP		 3209 /* Input stub section holding secure gateway veneers. */
3210 asection *cmse_stub_sec;
3211
0955507f
TP		 3212 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3213 start to be allocated. */
3214 bfd_vma new_cmse_stub_offset;
3215
fe33d2fa 3216 /* Number of elements in stub_group. */
7292b3ac 3217 unsigned int top_id;
fe33d2fa 3218
906e58ca
NC		 3219 /* Assorted information used by elf32_arm_size_stubs. */
3220 unsigned int bfd_count;
7292b3ac 3221 unsigned int top_index;
906e58ca
NC		 3222 asection **input_list;
3223};
252b5132 3224
a504d23a
LA		 3225static inline int
3226ctz (unsigned int mask)
3227{
3228#if GCC_VERSION >= 3004
3229 return __builtin_ctz (mask);
3230#else
3231 unsigned int i;
3232
3233 for (i = 0; i < 8 * sizeof (mask); i++)
3234 {
3235 if (mask & 0x1)
3236 break;
3237 mask = (mask >> 1);
3238 }
3239 return i;
3240#endif
3241}
3242
3243static inline int
b25e998d 3244elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3245{
3246#if GCC_VERSION >= 3004
3247 return __builtin_popcount (mask);
3248#else
b25e998d
CG		 3249 unsigned int i;
3250 int sum = 0;
a504d23a
LA		 3251
3252 for (i = 0; i < 8 * sizeof (mask); i++)
3253 {
3254 if (mask & 0x1)
3255 sum++;
3256 mask = (mask >> 1);
3257 }
3258 return sum;
3259#endif
3260}
3261
780a67af
NC		 3262/* Create an entry in an ARM ELF linker hash table. */
3263
3264static struct bfd_hash_entry *
57e8b36a 3265elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3266 struct bfd_hash_table * table,
3267 const char * string)
780a67af
NC		 3268{
3269 struct elf32_arm_link_hash_entry * ret =
3270 (struct elf32_arm_link_hash_entry *) entry;
3271
3272 /* Allocate the structure if it has not already been allocated by a
3273 subclass. */
906e58ca 3274 if (ret == NULL)
21d799b5 3275 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3276 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3277 if (ret == NULL)
780a67af
NC		 3278 return (struct bfd_hash_entry *) ret;
3279
3280 /* Call the allocation method of the superclass. */
3281 ret = ((struct elf32_arm_link_hash_entry *)
3282 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3283 table, string));
57e8b36a 3284 if (ret != NULL)
b7693d02 3285 {
0bdcacaf 3286 ret->dyn_relocs = NULL;
ba93b8ac 3287 ret->tls_type = GOT_UNKNOWN;
0855e32b 3288 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3289 ret->plt.thumb_refcount = 0;
3290 ret->plt.maybe_thumb_refcount = 0;
3291 ret->plt.noncall_refcount = 0;
3292 ret->plt.got_offset = -1;
3293 ret->is_iplt = FALSE;
a4fd1a8e 3294 ret->export_glue = NULL;
906e58ca
NC		 3295
3296 ret->stub_cache = NULL;
b7693d02 3297 }
780a67af
NC		 3298
3299 return (struct bfd_hash_entry *) ret;
3300}
3301
34e77a92
RS		 3302/* Ensure that we have allocated bookkeeping structures for ABFD's local
3303 symbols. */
3304
3305static bfd_boolean
3306elf32_arm_allocate_local_sym_info (bfd *abfd)
3307{
3308 if (elf_local_got_refcounts (abfd) == NULL)
3309 {
3310 bfd_size_type num_syms;
3311 bfd_size_type size;
3312 char *data;
3313
3314 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3315 size = num_syms * (sizeof (bfd_signed_vma)
3316 + sizeof (struct arm_local_iplt_info *)
3317 + sizeof (bfd_vma)
3318 + sizeof (char));
3319 data = bfd_zalloc (abfd, size);
3320 if (data == NULL)
3321 return FALSE;
3322
3323 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3324 data += num_syms * sizeof (bfd_signed_vma);
3325
3326 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3327 data += num_syms * sizeof (struct arm_local_iplt_info *);
3328
3329 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3330 data += num_syms * sizeof (bfd_vma);
3331
3332 elf32_arm_local_got_tls_type (abfd) = data;
3333 }
3334 return TRUE;
3335}
3336
3337/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3338 to input bfd ABFD. Create the information if it doesn't already exist.
3339 Return null if an allocation fails. */
3340
3341static struct arm_local_iplt_info *
3342elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3343{
3344 struct arm_local_iplt_info **ptr;
3345
3346 if (!elf32_arm_allocate_local_sym_info (abfd))
3347 return NULL;
3348
3349 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3350 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3351 if (*ptr == NULL)
3352 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3353 return *ptr;
3354}
3355
3356/* Try to obtain PLT information for the symbol with index R_SYMNDX
3357 in ABFD's symbol table. If the symbol is global, H points to its
3358 hash table entry, otherwise H is null.
3359
3360 Return true if the symbol does have PLT information. When returning
3361 true, point *ROOT_PLT at the target-independent reference count/offset
3362 union and *ARM_PLT at the ARM-specific information. */
3363
3364static bfd_boolean
4ba2ef8f
TP		 3365elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3366 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3367 unsigned long r_symndx, union gotplt_union **root_plt,
3368 struct arm_plt_info **arm_plt)
3369{
3370 struct arm_local_iplt_info *local_iplt;
3371
4ba2ef8f
TP		 3372 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3373 return FALSE;
3374
34e77a92
RS		 3375 if (h != NULL)
3376 {
3377 *root_plt = &h->root.plt;
3378 *arm_plt = &h->plt;
3379 return TRUE;
3380 }
3381
3382 if (elf32_arm_local_iplt (abfd) == NULL)
3383 return FALSE;
3384
3385 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3386 if (local_iplt == NULL)
3387 return FALSE;
3388
3389 *root_plt = &local_iplt->root;
3390 *arm_plt = &local_iplt->arm;
3391 return TRUE;
3392}
3393
3394/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3395 before it. */
3396
3397static bfd_boolean
3398elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3399 struct arm_plt_info *arm_plt)
3400{
3401 struct elf32_arm_link_hash_table *htab;
3402
3403 htab = elf32_arm_hash_table (info);
3404 return (arm_plt->thumb_refcount != 0
3405 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3406}
3407
3408/* Return a pointer to the head of the dynamic reloc list that should
3409 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3410 ABFD's symbol table. Return null if an error occurs. */
3411
3412static struct elf_dyn_relocs **
3413elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3414 Elf_Internal_Sym *isym)
3415{
3416 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3417 {
3418 struct arm_local_iplt_info *local_iplt;
3419
3420 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3421 if (local_iplt == NULL)
3422 return NULL;
3423 return &local_iplt->dyn_relocs;
3424 }
3425 else
3426 {
3427 /* Track dynamic relocs needed for local syms too.
3428 We really need local syms available to do this
3429 easily. Oh well. */
3430 asection *s;
3431 void *vpp;
3432
3433 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3434 if (s == NULL)
3435 abort ();
3436
3437 vpp = &elf_section_data (s)->local_dynrel;
3438 return (struct elf_dyn_relocs **) vpp;
3439 }
3440}
3441
906e58ca
NC		 3442/* Initialize an entry in the stub hash table. */
3443
3444static struct bfd_hash_entry *
3445stub_hash_newfunc (struct bfd_hash_entry *entry,
3446 struct bfd_hash_table *table,
3447 const char *string)
3448{
3449 /* Allocate the structure if it has not already been allocated by a
3450 subclass. */
3451 if (entry == NULL)
3452 {
21d799b5 3453 entry = (struct bfd_hash_entry *)
99059e56 3454 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3455 if (entry == NULL)
3456 return entry;
3457 }
3458
3459 /* Call the allocation method of the superclass. */
3460 entry = bfd_hash_newfunc (entry, table, string);
3461 if (entry != NULL)
3462 {
3463 struct elf32_arm_stub_hash_entry *eh;
3464
3465 /* Initialize the local fields. */
3466 eh = (struct elf32_arm_stub_hash_entry *) entry;
3467 eh->stub_sec = NULL;
0955507f 3468 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3469 eh->source_value = 0;
906e58ca
NC		 3470 eh->target_value = 0;
3471 eh->target_section = NULL;
cedfb179 3472 eh->orig_insn = 0;
906e58ca 3473 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3474 eh->stub_size = 0;
3475 eh->stub_template = NULL;
0955507f 3476 eh->stub_template_size = -1;
906e58ca
NC		 3477 eh->h = NULL;
3478 eh->id_sec = NULL;
d8d2f433 3479 eh->output_name = NULL;
906e58ca
NC		 3480 }
3481
3482 return entry;
3483}
3484
00a97672 3485/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3486 shortcuts to them in our hash table. */
3487
3488static bfd_boolean
57e8b36a 3489create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3490{
3491 struct elf32_arm_link_hash_table *htab;
3492
e5a52504 3493 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3494 if (htab == NULL)
3495 return FALSE;
3496
e5a52504
MM		 3497 /* BPABI objects never have a GOT, or associated sections. */
3498 if (htab->symbian_p)
3499 return TRUE;
3500
5e681ec4
PB		 3501 if (! _bfd_elf_create_got_section (dynobj, info))
3502 return FALSE;
3503
5e681ec4
PB		 3504 return TRUE;
3505}
3506
34e77a92
RS		 3507/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3508
3509static bfd_boolean
3510create_ifunc_sections (struct bfd_link_info *info)
3511{
3512 struct elf32_arm_link_hash_table *htab;
3513 const struct elf_backend_data *bed;
3514 bfd *dynobj;
3515 asection *s;
3516 flagword flags;
b38cadfb 3517
34e77a92
RS		 3518 htab = elf32_arm_hash_table (info);
3519 dynobj = htab->root.dynobj;
3520 bed = get_elf_backend_data (dynobj);
3521 flags = bed->dynamic_sec_flags;
3522
3523 if (htab->root.iplt == NULL)
3524 {
3d4d4302
AM		 3525 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3526 flags | SEC_READONLY | SEC_CODE);
34e77a92 3527 if (s == NULL
a0f49396 3528 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3529 return FALSE;
3530 htab->root.iplt = s;
3531 }
3532
3533 if (htab->root.irelplt == NULL)
3534 {
3d4d4302
AM		 3535 s = bfd_make_section_anyway_with_flags (dynobj,
3536 RELOC_SECTION (htab, ".iplt"),
3537 flags | SEC_READONLY);
34e77a92 3538 if (s == NULL
a0f49396 3539 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3540 return FALSE;
3541 htab->root.irelplt = s;
3542 }
3543
3544 if (htab->root.igotplt == NULL)
3545 {
3d4d4302 3546 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3547 if (s == NULL
3548 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3549 return FALSE;
3550 htab->root.igotplt = s;
3551 }
3552 return TRUE;
3553}
3554
eed94f8f
NC		 3555/* Determine if we're dealing with a Thumb only architecture. */
3556
3557static bfd_boolean
3558using_thumb_only (struct elf32_arm_link_hash_table *globals)
3559{
2fd158eb
TP		 3560 int arch;
3561 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3562 Tag_CPU_arch_profile);
eed94f8f 3563
2fd158eb
TP		 3564 if (profile)
3565 return profile == 'M';
eed94f8f 3566
2fd158eb 3567 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3568
60a019a0 3569 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3570 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3571
2fd158eb
TP		 3572 if (arch == TAG_CPU_ARCH_V6_M
3573 || arch == TAG_CPU_ARCH_V6S_M
3574 || arch == TAG_CPU_ARCH_V7E_M
3575 || arch == TAG_CPU_ARCH_V8M_BASE
3576 || arch == TAG_CPU_ARCH_V8M_MAIN)
3577 return TRUE;
eed94f8f 3578
2fd158eb 3579 return FALSE;
eed94f8f
NC		 3580}
3581
3582/* Determine if we're dealing with a Thumb-2 object. */
3583
3584static bfd_boolean
3585using_thumb2 (struct elf32_arm_link_hash_table *globals)
3586{
60a019a0
TP		 3587 int arch;
3588 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3589 Tag_THUMB_ISA_use);
3590
3591 if (thumb_isa)
3592 return thumb_isa == 2;
3593
3594 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3595
3596 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3597 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3598
3599 return (arch == TAG_CPU_ARCH_V6T2
3600 || arch == TAG_CPU_ARCH_V7
3601 || arch == TAG_CPU_ARCH_V7E_M
3602 || arch == TAG_CPU_ARCH_V8
bff0500d 3603 || arch == TAG_CPU_ARCH_V8R
60a019a0 3604 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3605}
3606
5e866f5a
TP		 3607/* Determine whether Thumb-2 BL instruction is available. */
3608
3609static bfd_boolean
3610using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3611{
3612 int arch =
3613 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3614
3615 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3616 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3617
3618 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3619 return (arch == TAG_CPU_ARCH_V6T2
3620 || arch >= TAG_CPU_ARCH_V7);
3621}
3622
00a97672
RS		 3623/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3624 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3625 hash table. */
3626
3627static bfd_boolean
57e8b36a 3628elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3629{
3630 struct elf32_arm_link_hash_table *htab;
3631
3632 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3633 if (htab == NULL)
3634 return FALSE;
3635
362d30a1 3636 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3637 return FALSE;
3638
3639 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3640 return FALSE;
3641
00a97672
RS		 3642 if (htab->vxworks_p)
3643 {
3644 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3645 return FALSE;
3646
0e1862bb 3647 if (bfd_link_pic (info))
00a97672
RS		 3648 {
3649 htab->plt_header_size = 0;
3650 htab->plt_entry_size
3651 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3652 }
3653 else
3654 {
3655 htab->plt_header_size
3656 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3657 htab->plt_entry_size
3658 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3659 }
aebf9be7
NC		 3660
3661 if (elf_elfheader (dynobj))
3662 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3663 }
eed94f8f
NC		 3664 else
3665 {
3666 /* PR ld/16017
3667 Test for thumb only architectures. Note - we cannot just call
3668 using_thumb_only() as the attributes in the output bfd have not been
3669 initialised at this point, so instead we use the input bfd. */
3670 bfd * saved_obfd = htab->obfd;
3671
3672 htab->obfd = dynobj;
3673 if (using_thumb_only (htab))
3674 {
3675 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3676 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3677 }
3678 htab->obfd = saved_obfd;
3679 }
5e681ec4 3680
362d30a1
RS		 3681 if (!htab->root.splt
3682 || !htab->root.srelplt
9d19e4fd
AM		 3683 || !htab->root.sdynbss
3684 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3685 abort ();
3686
3687 return TRUE;
3688}
3689
906e58ca
NC		 3690/* Copy the extra info we tack onto an elf_link_hash_entry. */
3691
3692static void
3693elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3694 struct elf_link_hash_entry *dir,
3695 struct elf_link_hash_entry *ind)
3696{
3697 struct elf32_arm_link_hash_entry *edir, *eind;
3698
3699 edir = (struct elf32_arm_link_hash_entry *) dir;
3700 eind = (struct elf32_arm_link_hash_entry *) ind;
3701
0bdcacaf 3702 if (eind->dyn_relocs != NULL)
906e58ca 3703 {
0bdcacaf 3704 if (edir->dyn_relocs != NULL)
906e58ca 3705 {
0bdcacaf
RS		 3706 struct elf_dyn_relocs **pp;
3707 struct elf_dyn_relocs *p;
906e58ca
NC		 3708
3709 /* Add reloc counts against the indirect sym to the direct sym
3710 list. Merge any entries against the same section. */
0bdcacaf 3711 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3712 {
0bdcacaf 3713 struct elf_dyn_relocs *q;
906e58ca 3714
0bdcacaf
RS		 3715 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3716 if (q->sec == p->sec)
906e58ca
NC		 3717 {
3718 q->pc_count += p->pc_count;
3719 q->count += p->count;
3720 *pp = p->next;
3721 break;
3722 }
3723 if (q == NULL)
3724 pp = &p->next;
3725 }
0bdcacaf 3726 *pp = edir->dyn_relocs;
906e58ca
NC		 3727 }
3728
0bdcacaf
RS		 3729 edir->dyn_relocs = eind->dyn_relocs;
3730 eind->dyn_relocs = NULL;
906e58ca
NC		 3731 }
3732
3733 if (ind->root.type == bfd_link_hash_indirect)
3734 {
3735 /* Copy over PLT info. */
34e77a92
RS		 3736 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3737 eind->plt.thumb_refcount = 0;
3738 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3739 eind->plt.maybe_thumb_refcount = 0;
3740 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3741 eind->plt.noncall_refcount = 0;
3742
3743 /* We should only allocate a function to .iplt once the final
3744 symbol information is known. */
3745 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3746
3747 if (dir->got.refcount <= 0)
3748 {
3749 edir->tls_type = eind->tls_type;
3750 eind->tls_type = GOT_UNKNOWN;
3751 }
3752 }
3753
3754 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3755}
3756
68faa637
AM		 3757/* Destroy an ARM elf linker hash table. */
3758
3759static void
d495ab0d 3760elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3761{
3762 struct elf32_arm_link_hash_table *ret
d495ab0d 3763 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3764
3765 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3766 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3767}
3768
906e58ca
NC		 3769/* Create an ARM elf linker hash table. */
3770
3771static struct bfd_link_hash_table *
3772elf32_arm_link_hash_table_create (bfd *abfd)
3773{
3774 struct elf32_arm_link_hash_table *ret;
3775 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3776
7bf52ea2 3777 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3778 if (ret == NULL)
3779 return NULL;
3780
3781 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3782 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3783 sizeof (struct elf32_arm_link_hash_entry),
3784 ARM_ELF_DATA))
906e58ca
NC		 3785 {
3786 free (ret);
3787 return NULL;
3788 }
3789
906e58ca 3790 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3791 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3792#ifdef FOUR_WORD_PLT
3793 ret->plt_header_size = 16;
3794 ret->plt_entry_size = 16;
3795#else
3796 ret->plt_header_size = 20;
1db37fe6 3797 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3798#endif
906e58ca 3799 ret->use_rel = 1;
906e58ca 3800 ret->obfd = abfd;
906e58ca
NC		 3801
3802 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3803 sizeof (struct elf32_arm_stub_hash_entry)))
3804 {
d495ab0d 3805 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3806 return NULL;
3807 }
d495ab0d 3808 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3809
3810 return &ret->root.root;
3811}
3812
cd1dac3d
DG		 3813/* Determine what kind of NOPs are available. */
3814
3815static bfd_boolean
3816arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3817{
3818 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3819 Tag_CPU_arch);
cd1dac3d 3820
60a019a0 3821 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3822 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3823
3824 return (arch == TAG_CPU_ARCH_V6T2
3825 || arch == TAG_CPU_ARCH_V6K
3826 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 3827 || arch == TAG_CPU_ARCH_V8
3828 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 3829}
3830
f4ac8484
DJ		 3831static bfd_boolean
3832arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3833{
3834 switch (stub_type)
3835 {
fea2b4d6 3836 case arm_stub_long_branch_thumb_only:
80c135e5 3837 case arm_stub_long_branch_thumb2_only:
d5a67c02 3838 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3839 case arm_stub_long_branch_v4t_thumb_arm:
3840 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3841 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3842 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3843 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3844 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3845 return TRUE;
3846 case arm_stub_none:
3847 BFD_FAIL ();
3848 return FALSE;
3849 break;
3850 default:
3851 return FALSE;
3852 }
3853}
3854
906e58ca
NC		 3855/* Determine the type of stub needed, if any, for a call. */
3856
3857static enum elf32_arm_stub_type
3858arm_type_of_stub (struct bfd_link_info *info,
3859 asection *input_sec,
3860 const Elf_Internal_Rela *rel,
34e77a92 3861 unsigned char st_type,
35fc36a8 3862 enum arm_st_branch_type *actual_branch_type,
906e58ca 3863 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3864 bfd_vma destination,
3865 asection *sym_sec,
3866 bfd *input_bfd,
3867 const char *name)
906e58ca
NC		 3868{
3869 bfd_vma location;
3870 bfd_signed_vma branch_offset;
3871 unsigned int r_type;
3872 struct elf32_arm_link_hash_table * globals;
5e866f5a 3873 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3874 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3875 int use_plt = 0;
35fc36a8 3876 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3877 union gotplt_union *root_plt;
3878 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3879 int arch;
3880 int thumb2_movw;
906e58ca 3881
35fc36a8 3882 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3883 return stub_type;
3884
906e58ca 3885 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3886 if (globals == NULL)
3887 return stub_type;
906e58ca
NC		 3888
3889 thumb_only = using_thumb_only (globals);
906e58ca 3890 thumb2 = using_thumb2 (globals);
5e866f5a 3891 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3892
d5a67c02
AV		 3893 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3894
3895 /* True for architectures that implement the thumb2 movw instruction. */
3896 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3897
906e58ca
NC		 3898 /* Determine where the call point is. */
3899 location = (input_sec->output_offset
3900 + input_sec->output_section->vma
3901 + rel->r_offset);
3902
906e58ca
NC		 3903 r_type = ELF32_R_TYPE (rel->r_info);
3904
39f21624
NC		 3905 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3906 are considering a function call relocation. */
c5423981
TG		 3907 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3908 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3909 && branch_type == ST_BRANCH_TO_ARM)
3910 branch_type = ST_BRANCH_TO_THUMB;
3911
34e77a92
RS		 3912 /* For TLS call relocs, it is the caller's responsibility to provide
3913 the address of the appropriate trampoline. */
3914 if (r_type != R_ARM_TLS_CALL
3915 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3916 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3917 ELF32_R_SYM (rel->r_info), &root_plt,
3918 &arm_plt)
34e77a92 3919 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3920 {
34e77a92 3921 asection *splt;
fe33d2fa 3922
34e77a92
RS		 3923 if (hash == NULL || hash->is_iplt)
3924 splt = globals->root.iplt;
3925 else
3926 splt = globals->root.splt;
3927 if (splt != NULL)
b38cadfb 3928 {
34e77a92
RS		 3929 use_plt = 1;
3930
3931 /* Note when dealing with PLT entries: the main PLT stub is in
3932 ARM mode, so if the branch is in Thumb mode, another
3933 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3934 PLT stub. If a long branch stub is needed, we'll add a
3935 Thumb->Arm one and branch directly to the ARM PLT entry.
3936 Here, we have to check if a pre-PLT Thumb->ARM stub
3937 is needed and if it will be close enough. */
34e77a92
RS		 3938
3939 destination = (splt->output_section->vma
3940 + splt->output_offset
3941 + root_plt->offset);
3942 st_type = STT_FUNC;
2df2751d
CL		 3943
3944 /* Thumb branch/call to PLT: it can become a branch to ARM
3945 or to Thumb. We must perform the same checks and
3946 corrections as in elf32_arm_final_link_relocate. */
3947 if ((r_type == R_ARM_THM_CALL)
3948 || (r_type == R_ARM_THM_JUMP24))
3949 {
3950 if (globals->use_blx
3951 && r_type == R_ARM_THM_CALL
3952 && !thumb_only)
3953 {
3954 /* If the Thumb BLX instruction is available, convert
3955 the BL to a BLX instruction to call the ARM-mode
3956 PLT entry. */
3957 branch_type = ST_BRANCH_TO_ARM;
3958 }
3959 else
3960 {
3961 if (!thumb_only)
3962 /* Target the Thumb stub before the ARM PLT entry. */
3963 destination -= PLT_THUMB_STUB_SIZE;
3964 branch_type = ST_BRANCH_TO_THUMB;
3965 }
3966 }
3967 else
3968 {
3969 branch_type = ST_BRANCH_TO_ARM;
3970 }
34e77a92 3971 }
5fa9e92f 3972 }
34e77a92
RS		 3973 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3974 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3975
fe33d2fa
CL		 3976 branch_offset = (bfd_signed_vma)(destination - location);
3977
0855e32b 3978 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3979 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3980 {
5fa9e92f
CL		 3981 /* Handle cases where:
3982 - this call goes too far (different Thumb/Thumb2 max
99059e56 3983 distance)
155d87d7 3984 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3985 Thumb->Arm branch (not bl). A stub is needed in this case,
3986 but only if this call is not through a PLT entry. Indeed,
695344c0 3987 PLT stubs handle mode switching already. */
5e866f5a 3988 if ((!thumb2_bl
906e58ca
NC		 3989 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3990 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3991 || (thumb2_bl
906e58ca
NC		 3992 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3993 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3994 || (thumb2
3995 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3996 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3997 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3998 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3999 && (((r_type == R_ARM_THM_CALL
4000 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4001 || (r_type == R_ARM_THM_JUMP24)
4002 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4003 && !use_plt))
906e58ca 4004 {
2df2751d
CL		 4005 /* If we need to insert a Thumb-Thumb long branch stub to a
4006 PLT, use one that branches directly to the ARM PLT
4007 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4008 stub, undo this now. */
695344c0
NC		 4009 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4010 {
4011 branch_type = ST_BRANCH_TO_ARM;
4012 branch_offset += PLT_THUMB_STUB_SIZE;
4013 }
2df2751d 4014
35fc36a8 4015 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4016 {
4017 /* Thumb to thumb. */
4018 if (!thumb_only)
4019 {
d5a67c02 4020 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4021 _bfd_error_handler
4022 (_("%B(%A): warning: long branch veneers used in"
4023 " section with SHF_ARM_PURECODE section"
4024 " attribute is only supported for M-profile"
4025 " targets that implement the movw instruction."),
4026 input_bfd, input_sec);
d5a67c02 4027
0e1862bb 4028 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4029 /* PIC stubs. */
155d87d7 4030 ? ((globals->use_blx
9553db3c 4031 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4032 /* V5T and above. Stub starts with ARM code, so
4033 we must be able to switch mode before
4034 reaching it, which is only possible for 'bl'
4035 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4036 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4037 /* On V4T, use Thumb code only. */
d3626fb0 4038 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4039
4040 /* non-PIC stubs. */
155d87d7 4041 : ((globals->use_blx
9553db3c 4042 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4043 /* V5T and above. */
4044 ? arm_stub_long_branch_any_any
4045 /* V4T. */
d3626fb0 4046 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4047 }
4048 else
4049 {
d5a67c02
AV		 4050 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4051 stub_type = arm_stub_long_branch_thumb2_only_pure;
4052 else
4053 {
4054 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4055 _bfd_error_handler
4056 (_("%B(%A): warning: long branch veneers used in"
4057 " section with SHF_ARM_PURECODE section"
4058 " attribute is only supported for M-profile"
4059 " targets that implement the movw instruction."),
4060 input_bfd, input_sec);
d5a67c02
AV		 4061
4062 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4063 /* PIC stub. */
4064 ? arm_stub_long_branch_thumb_only_pic
4065 /* non-PIC stub. */
4066 : (thumb2 ? arm_stub_long_branch_thumb2_only
4067 : arm_stub_long_branch_thumb_only);
4068 }
906e58ca
NC		 4069 }
4070 }
4071 else
4072 {
d5a67c02 4073 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4074 _bfd_error_handler
4075 (_("%B(%A): warning: long branch veneers used in"
4076 " section with SHF_ARM_PURECODE section"
4077 " attribute is only supported" " for M-profile"
4078 " targets that implement the movw instruction."),
4079 input_bfd, input_sec);
d5a67c02 4080
906e58ca 4081 /* Thumb to arm. */
c820be07
NC		 4082 if (sym_sec != NULL
4083 && sym_sec->owner != NULL
4084 && !INTERWORK_FLAG (sym_sec->owner))
4085 {
4eca0228 4086 _bfd_error_handler
c820be07
NC		 4087 (_("%B(%s): warning: interworking not enabled.\n"
4088 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 4089 sym_sec->owner, name, input_bfd);
c820be07
NC		 4090 }
4091
0855e32b 4092 stub_type =
0e1862bb 4093 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4094 /* PIC stubs. */
0855e32b 4095 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4096 /* TLS PIC stubs. */
0855e32b
NS		 4097 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4098 : arm_stub_long_branch_v4t_thumb_tls_pic)
4099 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4100 /* V5T PIC and above. */
4101 ? arm_stub_long_branch_any_arm_pic
4102 /* V4T PIC stub. */
4103 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4104
4105 /* non-PIC stubs. */
0855e32b 4106 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4107 /* V5T and above. */
4108 ? arm_stub_long_branch_any_any
4109 /* V4T. */
4110 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4111
4112 /* Handle v4t short branches. */
fea2b4d6 4113 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4114 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4115 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4116 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4117 }
4118 }
4119 }
fe33d2fa
CL		 4120 else if (r_type == R_ARM_CALL
4121 || r_type == R_ARM_JUMP24
0855e32b
NS		 4122 || r_type == R_ARM_PLT32
4123 || r_type == R_ARM_TLS_CALL)
906e58ca 4124 {
d5a67c02 4125 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4126 _bfd_error_handler
4127 (_("%B(%A): warning: long branch veneers used in"
4128 " section with SHF_ARM_PURECODE section"
4129 " attribute is only supported for M-profile"
4130 " targets that implement the movw instruction."),
4131 input_bfd, input_sec);
35fc36a8 4132 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4133 {
4134 /* Arm to thumb. */
c820be07
NC		 4135
4136 if (sym_sec != NULL
4137 && sym_sec->owner != NULL
4138 && !INTERWORK_FLAG (sym_sec->owner))
4139 {
4eca0228 4140 _bfd_error_handler
c820be07 4141 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4142 " first occurrence: %B: ARM call to Thumb"),
d42c267e 4143 sym_sec->owner, name, input_bfd);
c820be07
NC		 4144 }
4145
4146 /* We have an extra 2-bytes reach because of
4147 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4148 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4149 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4150 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4151 || (r_type == R_ARM_JUMP24)
4152 || (r_type == R_ARM_PLT32))
906e58ca 4153 {
0e1862bb 4154 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4155 /* PIC stubs. */
ebe24dd4
CL		 4156 ? ((globals->use_blx)
4157 /* V5T and above. */
4158 ? arm_stub_long_branch_any_thumb_pic
4159 /* V4T stub. */
4160 : arm_stub_long_branch_v4t_arm_thumb_pic)
4161
c2b4a39d
CL		 4162 /* non-PIC stubs. */
4163 : ((globals->use_blx)
4164 /* V5T and above. */
4165 ? arm_stub_long_branch_any_any
4166 /* V4T. */
4167 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4168 }
4169 }
4170 else
4171 {
4172 /* Arm to arm. */
4173 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4174 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4175 {
0855e32b 4176 stub_type =
0e1862bb 4177 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4178 /* PIC stubs. */
0855e32b 4179 ? (r_type == R_ARM_TLS_CALL
6a631e86 4180 /* TLS PIC Stub. */
0855e32b 4181 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4182 : (globals->nacl_p
4183 ? arm_stub_long_branch_arm_nacl_pic
4184 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4185 /* non-PIC stubs. */
7a89b94e
NC		 4186 : (globals->nacl_p
4187 ? arm_stub_long_branch_arm_nacl
4188 : arm_stub_long_branch_any_any);
906e58ca
NC		 4189 }
4190 }
4191 }
4192
fe33d2fa
CL		 4193 /* If a stub is needed, record the actual destination type. */
4194 if (stub_type != arm_stub_none)
35fc36a8 4195 *actual_branch_type = branch_type;
fe33d2fa 4196
906e58ca
NC		 4197 return stub_type;
4198}
4199
4200/* Build a name for an entry in the stub hash table. */
4201
4202static char *
4203elf32_arm_stub_name (const asection *input_section,
4204 const asection *sym_sec,
4205 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4206 const Elf_Internal_Rela *rel,
4207 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4208{
4209 char *stub_name;
4210 bfd_size_type len;
4211
4212 if (hash)
4213 {
fe33d2fa 4214 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4215 stub_name = (char *) bfd_malloc (len);
906e58ca 4216 if (stub_name != NULL)
fe33d2fa 4217 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4218 input_section->id & 0xffffffff,
4219 hash->root.root.root.string,
fe33d2fa
CL		 4220 (int) rel->r_addend & 0xffffffff,
4221 (int) stub_type);
906e58ca
NC		 4222 }
4223 else
4224 {
fe33d2fa 4225 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4226 stub_name = (char *) bfd_malloc (len);
906e58ca 4227 if (stub_name != NULL)
fe33d2fa 4228 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4229 input_section->id & 0xffffffff,
4230 sym_sec->id & 0xffffffff,
0855e32b
NS		 4231 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4232 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4233 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4234 (int) rel->r_addend & 0xffffffff,
4235 (int) stub_type);
906e58ca
NC		 4236 }
4237
4238 return stub_name;
4239}
4240
4241/* Look up an entry in the stub hash. Stub entries are cached because
4242 creating the stub name takes a bit of time. */
4243
4244static struct elf32_arm_stub_hash_entry *
4245elf32_arm_get_stub_entry (const asection *input_section,
4246 const asection *sym_sec,
4247 struct elf_link_hash_entry *hash,
4248 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4249 struct elf32_arm_link_hash_table *htab,
4250 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4251{
4252 struct elf32_arm_stub_hash_entry *stub_entry;
4253 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4254 const asection *id_sec;
4255
4256 if ((input_section->flags & SEC_CODE) == 0)
4257 return NULL;
4258
4259 /* If this input section is part of a group of sections sharing one
4260 stub section, then use the id of the first section in the group.
4261 Stub names need to include a section id, as there may well be
4262 more than one stub used to reach say, printf, and we need to
4263 distinguish between them. */
c2abbbeb 4264 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4265 id_sec = htab->stub_group[input_section->id].link_sec;
4266
4267 if (h != NULL && h->stub_cache != NULL
4268 && h->stub_cache->h == h
fe33d2fa
CL		 4269 && h->stub_cache->id_sec == id_sec
4270 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4271 {
4272 stub_entry = h->stub_cache;
4273 }
4274 else
4275 {
4276 char *stub_name;
4277
fe33d2fa 4278 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4279 if (stub_name == NULL)
4280 return NULL;
4281
4282 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4283 stub_name, FALSE, FALSE);
4284 if (h != NULL)
4285 h->stub_cache = stub_entry;
4286
4287 free (stub_name);
4288 }
4289
4290 return stub_entry;
4291}
4292
daa4adae
TP		 4293/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4294 section. */
4295
4296static bfd_boolean
4297arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4298{
4299 if (stub_type >= max_stub_type)
4300 abort (); /* Should be unreachable. */
4301
4ba2ef8f
TP		 4302 switch (stub_type)
4303 {
4304 case arm_stub_cmse_branch_thumb_only:
4305 return TRUE;
4306
4307 default:
4308 return FALSE;
4309 }
4310
4311 abort (); /* Should be unreachable. */
daa4adae
TP		 4312}
4313
4314/* Required alignment (as a power of 2) for the dedicated section holding
4315 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4316 with input sections. */
4317
4318static int
4319arm_dedicated_stub_output_section_required_alignment
4320 (enum elf32_arm_stub_type stub_type)
4321{
4322 if (stub_type >= max_stub_type)
4323 abort (); /* Should be unreachable. */
4324
4ba2ef8f
TP		 4325 switch (stub_type)
4326 {
4327 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4328 boundary. */
4329 case arm_stub_cmse_branch_thumb_only:
4330 return 5;
4331
4332 default:
4333 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4334 return 0;
4335 }
4336
4337 abort (); /* Should be unreachable. */
daa4adae
TP		 4338}
4339
4340/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4341 NULL if veneers of this type are interspersed with input sections. */
4342
4343static const char *
4344arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4345{
4346 if (stub_type >= max_stub_type)
4347 abort (); /* Should be unreachable. */
4348
4ba2ef8f
TP		 4349 switch (stub_type)
4350 {
4351 case arm_stub_cmse_branch_thumb_only:
4352 return ".gnu.sgstubs";
4353
4354 default:
4355 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4356 return NULL;
4357 }
4358
4359 abort (); /* Should be unreachable. */
daa4adae
TP		 4360}
4361
4362/* If veneers of type STUB_TYPE should go in a dedicated output section,
4363 returns the address of the hash table field in HTAB holding a pointer to the
4364 corresponding input section. Otherwise, returns NULL. */
4365
4366static asection **
4ba2ef8f
TP		 4367arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4368 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4369{
4370 if (stub_type >= max_stub_type)
4371 abort (); /* Should be unreachable. */
4372
4ba2ef8f
TP		 4373 switch (stub_type)
4374 {
4375 case arm_stub_cmse_branch_thumb_only:
4376 return &htab->cmse_stub_sec;
4377
4378 default:
4379 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4380 return NULL;
4381 }
4382
4383 abort (); /* Should be unreachable. */
daa4adae
TP		 4384}
4385
4386/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4387 is the section that branch into veneer and can be NULL if stub should go in
4388 a dedicated output section. Returns a pointer to the stub section, and the
4389 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4390 LINK_SEC_P may be NULL. */
906e58ca 4391
48229727
JB		 4392static asection *
4393elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4394 struct elf32_arm_link_hash_table *htab,
4395 enum elf32_arm_stub_type stub_type)
906e58ca 4396{
daa4adae
TP		 4397 asection *link_sec, *out_sec, **stub_sec_p;
4398 const char *stub_sec_prefix;
4399 bfd_boolean dedicated_output_section =
4400 arm_dedicated_stub_output_section_required (stub_type);
4401 int align;
906e58ca 4402
daa4adae 4403 if (dedicated_output_section)
906e58ca 4404 {
daa4adae
TP		 4405 bfd *output_bfd = htab->obfd;
4406 const char *out_sec_name =
4407 arm_dedicated_stub_output_section_name (stub_type);
4408 link_sec = NULL;
4409 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4410 stub_sec_prefix = out_sec_name;
4411 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4412 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4413 if (out_sec == NULL)
906e58ca 4414 {
4eca0228
AM		 4415 _bfd_error_handler (_("No address assigned to the veneers output "
4416 "section %s"), out_sec_name);
daa4adae 4417 return NULL;
906e58ca 4418 }
daa4adae
TP		 4419 }
4420 else
4421 {
c2abbbeb 4422 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4423 link_sec = htab->stub_group[section->id].link_sec;
4424 BFD_ASSERT (link_sec != NULL);
4425 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4426 if (*stub_sec_p == NULL)
4427 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4428 stub_sec_prefix = link_sec->name;
4429 out_sec = link_sec->output_section;
4430 align = htab->nacl_p ? 4 : 3;
906e58ca 4431 }
b38cadfb 4432
daa4adae
TP		 4433 if (*stub_sec_p == NULL)
4434 {
4435 size_t namelen;
4436 bfd_size_type len;
4437 char *s_name;
4438
4439 namelen = strlen (stub_sec_prefix);
4440 len = namelen + sizeof (STUB_SUFFIX);
4441 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4442 if (s_name == NULL)
4443 return NULL;
4444
4445 memcpy (s_name, stub_sec_prefix, namelen);
4446 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4447 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4448 align);
4449 if (*stub_sec_p == NULL)
4450 return NULL;
4451
4452 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4453 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4454 | SEC_KEEP;
4455 }
4456
4457 if (!dedicated_output_section)
4458 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4459
48229727
JB		 4460 if (link_sec_p)
4461 *link_sec_p = link_sec;
b38cadfb 4462
daa4adae 4463 return *stub_sec_p;
48229727
JB		 4464}
4465
4466/* Add a new stub entry to the stub hash. Not all fields of the new
4467 stub entry are initialised. */
4468
4469static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4470elf32_arm_add_stub (const char *stub_name, asection *section,
4471 struct elf32_arm_link_hash_table *htab,
4472 enum elf32_arm_stub_type stub_type)
48229727
JB		 4473{
4474 asection *link_sec;
4475 asection *stub_sec;
4476 struct elf32_arm_stub_hash_entry *stub_entry;
4477
daa4adae
TP		 4478 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4479 stub_type);
48229727
JB		 4480 if (stub_sec == NULL)
4481 return NULL;
906e58ca
NC		 4482
4483 /* Enter this entry into the linker stub hash table. */
4484 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4485 TRUE, FALSE);
4486 if (stub_entry == NULL)
4487 {
6bde4c52
TP		 4488 if (section == NULL)
4489 section = stub_sec;
dae82561 4490 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 4491 section->owner, stub_name);
906e58ca
NC		 4492 return NULL;
4493 }
4494
4495 stub_entry->stub_sec = stub_sec;
0955507f 4496 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4497 stub_entry->id_sec = link_sec;
4498
906e58ca
NC		 4499 return stub_entry;
4500}
4501
4502/* Store an Arm insn into an output section not processed by
4503 elf32_arm_write_section. */
4504
4505static void
8029a119
NC		 4506put_arm_insn (struct elf32_arm_link_hash_table * htab,
4507 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4508{
4509 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4510 bfd_putl32 (val, ptr);
4511 else
4512 bfd_putb32 (val, ptr);
4513}
4514
4515/* Store a 16-bit Thumb insn into an output section not processed by
4516 elf32_arm_write_section. */
4517
4518static void
8029a119
NC		 4519put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4520 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4521{
4522 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4523 bfd_putl16 (val, ptr);
4524 else
4525 bfd_putb16 (val, ptr);
4526}
4527
a504d23a
LA		 4528/* Store a Thumb2 insn into an output section not processed by
4529 elf32_arm_write_section. */
4530
4531static void
4532put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4533 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4534{
4535 /* T2 instructions are 16-bit streamed. */
4536 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4537 {
4538 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4539 bfd_putl16 ((val & 0xffff), ptr + 2);
4540 }
4541 else
4542 {
4543 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4544 bfd_putb16 ((val & 0xffff), ptr + 2);
4545 }
4546}
4547
0855e32b
NS		 4548/* If it's possible to change R_TYPE to a more efficient access
4549 model, return the new reloc type. */
4550
4551static unsigned
b38cadfb 4552elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4553 struct elf_link_hash_entry *h)
4554{
4555 int is_local = (h == NULL);
4556
0e1862bb
L		 4557 if (bfd_link_pic (info)
4558 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4559 return r_type;
4560
b38cadfb 4561 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4562 switch (r_type)
4563 {
4564 case R_ARM_TLS_GOTDESC:
4565 case R_ARM_TLS_CALL:
4566 case R_ARM_THM_TLS_CALL:
4567 case R_ARM_TLS_DESCSEQ:
4568 case R_ARM_THM_TLS_DESCSEQ:
4569 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4570 }
4571
4572 return r_type;
4573}
4574
48229727
JB		 4575static bfd_reloc_status_type elf32_arm_final_link_relocate
4576 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4577 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4578 const char *, unsigned char, enum arm_st_branch_type,
4579 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4580
4563a860
JB		 4581static unsigned int
4582arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4583{
4584 switch (stub_type)
4585 {
4586 case arm_stub_a8_veneer_b_cond:
4587 case arm_stub_a8_veneer_b:
4588 case arm_stub_a8_veneer_bl:
4589 return 2;
4590
4591 case arm_stub_long_branch_any_any:
4592 case arm_stub_long_branch_v4t_arm_thumb:
4593 case arm_stub_long_branch_thumb_only:
80c135e5 4594 case arm_stub_long_branch_thumb2_only:
d5a67c02 4595 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4596 case arm_stub_long_branch_v4t_thumb_thumb:
4597 case arm_stub_long_branch_v4t_thumb_arm:
4598 case arm_stub_short_branch_v4t_thumb_arm:
4599 case arm_stub_long_branch_any_arm_pic:
4600 case arm_stub_long_branch_any_thumb_pic:
4601 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4602 case arm_stub_long_branch_v4t_arm_thumb_pic:
4603 case arm_stub_long_branch_v4t_thumb_arm_pic:
4604 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4605 case arm_stub_long_branch_any_tls_pic:
4606 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4607 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4608 case arm_stub_a8_veneer_blx:
4609 return 4;
b38cadfb 4610
7a89b94e
NC		 4611 case arm_stub_long_branch_arm_nacl:
4612 case arm_stub_long_branch_arm_nacl_pic:
4613 return 16;
4614
4563a860
JB		 4615 default:
4616 abort (); /* Should be unreachable. */
4617 }
4618}
4619
4f4faa4d
TP		 4620/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4621 veneering (TRUE) or have their own symbol (FALSE). */
4622
4623static bfd_boolean
4624arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4625{
4626 if (stub_type >= max_stub_type)
4627 abort (); /* Should be unreachable. */
4628
4ba2ef8f
TP		 4629 switch (stub_type)
4630 {
4631 case arm_stub_cmse_branch_thumb_only:
4632 return TRUE;
4633
4634 default:
4635 return FALSE;
4636 }
4637
4638 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4639}
4640
d7c5bd02
TP		 4641/* Returns the padding needed for the dedicated section used stubs of type
4642 STUB_TYPE. */
4643
4644static int
4645arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4646{
4647 if (stub_type >= max_stub_type)
4648 abort (); /* Should be unreachable. */
4649
4ba2ef8f
TP		 4650 switch (stub_type)
4651 {
4652 case arm_stub_cmse_branch_thumb_only:
4653 return 32;
4654
4655 default:
4656 return 0;
4657 }
4658
4659 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4660}
4661
0955507f
TP		 4662/* If veneers of type STUB_TYPE should go in a dedicated output section,
4663 returns the address of the hash table field in HTAB holding the offset at
4664 which new veneers should be layed out in the stub section. */
4665
4666static bfd_vma*
4667arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4668 enum elf32_arm_stub_type stub_type)
4669{
4670 switch (stub_type)
4671 {
4672 case arm_stub_cmse_branch_thumb_only:
4673 return &htab->new_cmse_stub_offset;
4674
4675 default:
4676 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4677 return NULL;
4678 }
4679}
4680
906e58ca
NC		 4681static bfd_boolean
4682arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4683 void * in_arg)
4684{
7a89b94e 4685#define MAXRELOCS 3
0955507f 4686 bfd_boolean removed_sg_veneer;
906e58ca 4687 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4688 struct elf32_arm_link_hash_table *globals;
906e58ca 4689 struct bfd_link_info *info;
906e58ca
NC		 4690 asection *stub_sec;
4691 bfd *stub_bfd;
906e58ca
NC		 4692 bfd_byte *loc;
4693 bfd_vma sym_value;
4694 int template_size;
4695 int size;
d3ce72d0 4696 const insn_sequence *template_sequence;
906e58ca 4697 int i;
48229727
JB		 4698 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4699 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4700 int nrelocs = 0;
0955507f 4701 int just_allocated = 0;
906e58ca
NC		 4702
4703 /* Massage our args to the form they really have. */
4704 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4705 info = (struct bfd_link_info *) in_arg;
4706
4707 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4708 if (globals == NULL)
4709 return FALSE;
906e58ca 4710
906e58ca
NC		 4711 stub_sec = stub_entry->stub_sec;
4712
4dfe6ac6 4713 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4714 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4715 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4716 return TRUE;
fe33d2fa 4717
0955507f
TP		 4718 /* Assign a slot at the end of section if none assigned yet. */
4719 if (stub_entry->stub_offset == (bfd_vma) -1)
4720 {
4721 stub_entry->stub_offset = stub_sec->size;
4722 just_allocated = 1;
4723 }
906e58ca
NC		 4724 loc = stub_sec->contents + stub_entry->stub_offset;
4725
4726 stub_bfd = stub_sec->owner;
4727
906e58ca
NC		 4728 /* This is the address of the stub destination. */
4729 sym_value = (stub_entry->target_value
4730 + stub_entry->target_section->output_offset
4731 + stub_entry->target_section->output_section->vma);
4732
d3ce72d0 4733 template_sequence = stub_entry->stub_template;
461a49ca 4734 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4735
4736 size = 0;
461a49ca 4737 for (i = 0; i < template_size; i++)
906e58ca 4738 {
d3ce72d0 4739 switch (template_sequence[i].type)
461a49ca
DJ		 4740 {
4741 case THUMB16_TYPE:
48229727 4742 {
d3ce72d0
NC		 4743 bfd_vma data = (bfd_vma) template_sequence[i].data;
4744 if (template_sequence[i].reloc_addend != 0)
48229727 4745 {
99059e56
RM		 4746 /* We've borrowed the reloc_addend field to mean we should
4747 insert a condition code into this (Thumb-1 branch)
4748 instruction. See THUMB16_BCOND_INSN. */
4749 BFD_ASSERT ((data & 0xff00) == 0xd000);
4750 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4751 }
fe33d2fa 4752 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4753 size += 2;
4754 }
461a49ca 4755 break;
906e58ca 4756
48229727 4757 case THUMB32_TYPE:
fe33d2fa
CL		 4758 bfd_put_16 (stub_bfd,
4759 (template_sequence[i].data >> 16) & 0xffff,
4760 loc + size);
4761 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4762 loc + size + 2);
99059e56
RM		 4763 if (template_sequence[i].r_type != R_ARM_NONE)
4764 {
4765 stub_reloc_idx[nrelocs] = i;
4766 stub_reloc_offset[nrelocs++] = size;
4767 }
4768 size += 4;
4769 break;
48229727 4770
461a49ca 4771 case ARM_TYPE:
fe33d2fa
CL		 4772 bfd_put_32 (stub_bfd, template_sequence[i].data,
4773 loc + size);
461a49ca
DJ		 4774 /* Handle cases where the target is encoded within the
4775 instruction. */
d3ce72d0 4776 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4777 {
48229727
JB		 4778 stub_reloc_idx[nrelocs] = i;
4779 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4780 }
4781 size += 4;
4782 break;
4783
4784 case DATA_TYPE:
d3ce72d0 4785 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4786 stub_reloc_idx[nrelocs] = i;
4787 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4788 size += 4;
4789 break;
4790
4791 default:
4792 BFD_FAIL ();
4793 return FALSE;
4794 }
906e58ca 4795 }
461a49ca 4796
0955507f
TP		 4797 if (just_allocated)
4798 stub_sec->size += size;
906e58ca 4799
461a49ca
DJ		 4800 /* Stub size has already been computed in arm_size_one_stub. Check
4801 consistency. */
4802 BFD_ASSERT (size == stub_entry->stub_size);
4803
906e58ca 4804 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4805 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4806 sym_value |= 1;
4807
0955507f
TP		 4808 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4809 to relocate in each stub. */
4810 removed_sg_veneer =
4811 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4812 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4813
48229727 4814 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4815 {
4816 Elf_Internal_Rela rel;
4817 bfd_boolean unresolved_reloc;
4818 char *error_message;
4819 bfd_vma points_to =
4820 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4821
4822 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4823 rel.r_info = ELF32_R_INFO (0,
4824 template_sequence[stub_reloc_idx[i]].r_type);
4825 rel.r_addend = 0;
4826
4827 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4828 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4829 template should refer back to the instruction after the original
4830 branch. We use target_section as Cortex-A8 erratum workaround stubs
4831 are only generated when both source and target are in the same
4832 section. */
4833 points_to = stub_entry->target_section->output_section->vma
4834 + stub_entry->target_section->output_offset
4835 + stub_entry->source_value;
4836
4837 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4838 (template_sequence[stub_reloc_idx[i]].r_type),
4839 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4840 points_to, info, stub_entry->target_section, "", STT_FUNC,
4841 stub_entry->branch_type,
4842 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4843 &error_message);
4844 }
906e58ca
NC		 4845
4846 return TRUE;
48229727 4847#undef MAXRELOCS
906e58ca
NC		 4848}
4849
48229727
JB		 4850/* Calculate the template, template size and instruction size for a stub.
4851 Return value is the instruction size. */
906e58ca 4852
48229727
JB		 4853static unsigned int
4854find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4855 const insn_sequence **stub_template,
4856 int *stub_template_size)
906e58ca 4857{
d3ce72d0 4858 const insn_sequence *template_sequence = NULL;
48229727
JB		 4859 int template_size = 0, i;
4860 unsigned int size;
906e58ca 4861
d3ce72d0 4862 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4863 if (stub_template)
4864 *stub_template = template_sequence;
4865
48229727 4866 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4867 if (stub_template_size)
4868 *stub_template_size = template_size;
906e58ca
NC		 4869
4870 size = 0;
461a49ca
DJ		 4871 for (i = 0; i < template_size; i++)
4872 {
d3ce72d0 4873 switch (template_sequence[i].type)
461a49ca
DJ		 4874 {
4875 case THUMB16_TYPE:
4876 size += 2;
4877 break;
4878
4879 case ARM_TYPE:
48229727 4880 case THUMB32_TYPE:
461a49ca
DJ		 4881 case DATA_TYPE:
4882 size += 4;
4883 break;
4884
4885 default:
4886 BFD_FAIL ();
2a229407 4887 return 0;
461a49ca
DJ		 4888 }
4889 }
4890
48229727
JB		 4891 return size;
4892}
4893
4894/* As above, but don't actually build the stub. Just bump offset so
4895 we know stub section sizes. */
4896
4897static bfd_boolean
4898arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4899 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4900{
4901 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4902 const insn_sequence *template_sequence;
48229727
JB		 4903 int template_size, size;
4904
4905 /* Massage our args to the form they really have. */
4906 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4907
4908 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4909 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4910
d3ce72d0 4911 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4912 &template_size);
4913
0955507f
TP		 4914 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4915 if (stub_entry->stub_template_size)
4916 {
4917 stub_entry->stub_size = size;
4918 stub_entry->stub_template = template_sequence;
4919 stub_entry->stub_template_size = template_size;
4920 }
4921
4922 /* Already accounted for. */
4923 if (stub_entry->stub_offset != (bfd_vma) -1)
4924 return TRUE;
461a49ca 4925
906e58ca
NC		 4926 size = (size + 7) & ~7;
4927 stub_entry->stub_sec->size += size;
461a49ca 4928
906e58ca
NC		 4929 return TRUE;
4930}
4931
4932/* External entry points for sizing and building linker stubs. */
4933
4934/* Set up various things so that we can make a list of input sections
4935 for each output section included in the link. Returns -1 on error,
4936 0 when no stubs will be needed, and 1 on success. */
4937
4938int
4939elf32_arm_setup_section_lists (bfd *output_bfd,
4940 struct bfd_link_info *info)
4941{
4942 bfd *input_bfd;
4943 unsigned int bfd_count;
7292b3ac 4944 unsigned int top_id, top_index;
906e58ca
NC		 4945 asection *section;
4946 asection **input_list, **list;
4947 bfd_size_type amt;
4948 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4949
4dfe6ac6
NC		 4950 if (htab == NULL)
4951 return 0;
906e58ca
NC		 4952 if (! is_elf_hash_table (htab))
4953 return 0;
4954
4955 /* Count the number of input BFDs and find the top input section id. */
4956 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4957 input_bfd != NULL;
c72f2fb2 4958 input_bfd = input_bfd->link.next)
906e58ca
NC		 4959 {
4960 bfd_count += 1;
4961 for (section = input_bfd->sections;
4962 section != NULL;
4963 section = section->next)
4964 {
4965 if (top_id < section->id)
4966 top_id = section->id;
4967 }
4968 }
4969 htab->bfd_count = bfd_count;
4970
4971 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4972 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4973 if (htab->stub_group == NULL)
4974 return -1;
fe33d2fa 4975 htab->top_id = top_id;
906e58ca
NC		 4976
4977 /* We can't use output_bfd->section_count here to find the top output
4978 section index as some sections may have been removed, and
4979 _bfd_strip_section_from_output doesn't renumber the indices. */
4980 for (section = output_bfd->sections, top_index = 0;
4981 section != NULL;
4982 section = section->next)
4983 {
4984 if (top_index < section->index)
4985 top_index = section->index;
4986 }
4987
4988 htab->top_index = top_index;
4989 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4990 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4991 htab->input_list = input_list;
4992 if (input_list == NULL)
4993 return -1;
4994
4995 /* For sections we aren't interested in, mark their entries with a
4996 value we can check later. */
4997 list = input_list + top_index;
4998 do
4999 *list = bfd_abs_section_ptr;
5000 while (list-- != input_list);
5001
5002 for (section = output_bfd->sections;
5003 section != NULL;
5004 section = section->next)
5005 {
5006 if ((section->flags & SEC_CODE) != 0)
5007 input_list[section->index] = NULL;
5008 }
5009
5010 return 1;
5011}
5012
5013/* The linker repeatedly calls this function for each input section,
5014 in the order that input sections are linked into output sections.
5015 Build lists of input sections to determine groupings between which
5016 we may insert linker stubs. */
5017
5018void
5019elf32_arm_next_input_section (struct bfd_link_info *info,
5020 asection *isec)
5021{
5022 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5023
4dfe6ac6
NC		 5024 if (htab == NULL)
5025 return;
5026
906e58ca
NC		 5027 if (isec->output_section->index <= htab->top_index)
5028 {
5029 asection **list = htab->input_list + isec->output_section->index;
5030
a7470592 5031 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5032 {
5033 /* Steal the link_sec pointer for our list. */
5034#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5035 /* This happens to make the list in reverse order,
07d72278 5036 which we reverse later. */
906e58ca
NC		 5037 PREV_SEC (isec) = *list;
5038 *list = isec;
5039 }
5040 }
5041}
5042
5043/* See whether we can group stub sections together. Grouping stub
5044 sections may result in fewer stubs. More importantly, we need to
07d72278 5045 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5046 .fini output sections respectively, because glibc splits the
5047 _init and _fini functions into multiple parts. Putting a stub in
5048 the middle of a function is not a good idea. */
5049
5050static void
5051group_sections (struct elf32_arm_link_hash_table *htab,
5052 bfd_size_type stub_group_size,
07d72278 5053 bfd_boolean stubs_always_after_branch)
906e58ca 5054{
07d72278 5055 asection **list = htab->input_list;
906e58ca
NC		 5056
5057 do
5058 {
5059 asection *tail = *list;
07d72278 5060 asection *head;
906e58ca
NC		 5061
5062 if (tail == bfd_abs_section_ptr)
5063 continue;
5064
07d72278
DJ		 5065 /* Reverse the list: we must avoid placing stubs at the
5066 beginning of the section because the beginning of the text
5067 section may be required for an interrupt vector in bare metal
5068 code. */
5069#define NEXT_SEC PREV_SEC
e780aef2
CL		 5070 head = NULL;
5071 while (tail != NULL)
99059e56
RM		 5072 {
5073 /* Pop from tail. */
5074 asection *item = tail;
5075 tail = PREV_SEC (item);
e780aef2 5076
99059e56
RM		 5077 /* Push on head. */
5078 NEXT_SEC (item) = head;
5079 head = item;
5080 }
07d72278
DJ		 5081
5082 while (head != NULL)
906e58ca
NC		 5083 {
5084 asection *curr;
07d72278 5085 asection *next;
e780aef2
CL		 5086 bfd_vma stub_group_start = head->output_offset;
5087 bfd_vma end_of_next;
906e58ca 5088
07d72278 5089 curr = head;
e780aef2 5090 while (NEXT_SEC (curr) != NULL)
8cd931b7 5091 {
e780aef2
CL		 5092 next = NEXT_SEC (curr);
5093 end_of_next = next->output_offset + next->size;
5094 if (end_of_next - stub_group_start >= stub_group_size)
5095 /* End of NEXT is too far from start, so stop. */
8cd931b7 5096 break;
e780aef2
CL		 5097 /* Add NEXT to the group. */
5098 curr = next;
8cd931b7 5099 }
906e58ca 5100
07d72278 5101 /* OK, the size from the start to the start of CURR is less
906e58ca 5102 than stub_group_size and thus can be handled by one stub
07d72278 5103 section. (Or the head section is itself larger than
906e58ca
NC		 5104 stub_group_size, in which case we may be toast.)
5105 We should really be keeping track of the total size of
5106 stubs added here, as stubs contribute to the final output
7fb9f789 5107 section size. */
906e58ca
NC		 5108 do
5109 {
07d72278 5110 next = NEXT_SEC (head);
906e58ca 5111 /* Set up this stub group. */
07d72278 5112 htab->stub_group[head->id].link_sec = curr;
906e58ca 5113 }
07d72278 5114 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5115
5116 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5117 bytes after the stub section can be handled by it too. */
5118 if (!stubs_always_after_branch)
906e58ca 5119 {
e780aef2
CL		 5120 stub_group_start = curr->output_offset + curr->size;
5121
8cd931b7 5122 while (next != NULL)
906e58ca 5123 {
e780aef2
CL		 5124 end_of_next = next->output_offset + next->size;
5125 if (end_of_next - stub_group_start >= stub_group_size)
5126 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5127 break;
e780aef2 5128 /* Add NEXT to the stub group. */
07d72278
DJ		 5129 head = next;
5130 next = NEXT_SEC (head);
5131 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5132 }
5133 }
07d72278 5134 head = next;
906e58ca
NC		 5135 }
5136 }
07d72278 5137 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5138
5139 free (htab->input_list);
5140#undef PREV_SEC
07d72278 5141#undef NEXT_SEC
906e58ca
NC		 5142}
5143
48229727
JB		 5144/* Comparison function for sorting/searching relocations relating to Cortex-A8
5145 erratum fix. */
5146
5147static int
5148a8_reloc_compare (const void *a, const void *b)
5149{
21d799b5
NC		 5150 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5151 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5152
5153 if (ra->from < rb->from)
5154 return -1;
5155 else if (ra->from > rb->from)
5156 return 1;
5157 else
5158 return 0;
5159}
5160
5161static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5162 const char *, char **);
5163
5164/* Helper function to scan code for sequences which might trigger the Cortex-A8
5165 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5166 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5167 otherwise. */
5168
81694485
NC		 5169static bfd_boolean
5170cortex_a8_erratum_scan (bfd *input_bfd,
5171 struct bfd_link_info *info,
48229727
JB		 5172 struct a8_erratum_fix **a8_fixes_p,
5173 unsigned int *num_a8_fixes_p,
5174 unsigned int *a8_fix_table_size_p,
5175 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5176 unsigned int num_a8_relocs,
5177 unsigned prev_num_a8_fixes,
5178 bfd_boolean *stub_changed_p)
48229727
JB		 5179{
5180 asection *section;
5181 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5182 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5183 unsigned int num_a8_fixes = *num_a8_fixes_p;
5184 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5185
4dfe6ac6
NC		 5186 if (htab == NULL)
5187 return FALSE;
5188
48229727
JB		 5189 for (section = input_bfd->sections;
5190 section != NULL;
5191 section = section->next)
5192 {
5193 bfd_byte *contents = NULL;
5194 struct _arm_elf_section_data *sec_data;
5195 unsigned int span;
5196 bfd_vma base_vma;
5197
5198 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5199 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5200 || (section->flags & SEC_EXCLUDE) != 0
5201 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5202 || (section->output_section == bfd_abs_section_ptr))
5203 continue;
48229727
JB		 5204
5205 base_vma = section->output_section->vma + section->output_offset;
5206
5207 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5208 contents = elf_section_data (section)->this_hdr.contents;
48229727 5209 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5210 return TRUE;
48229727
JB		 5211
5212 sec_data = elf32_arm_section_data (section);
5213
5214 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5215 {
5216 unsigned int span_start = sec_data->map[span].vma;
5217 unsigned int span_end = (span == sec_data->mapcount - 1)
5218 ? section->size : sec_data->map[span + 1].vma;
5219 unsigned int i;
5220 char span_type = sec_data->map[span].type;
5221 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5222
5223 if (span_type != 't')
5224 continue;
5225
5226 /* Span is entirely within a single 4KB region: skip scanning. */
5227 if (((base_vma + span_start) & ~0xfff)
48229727 5228 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5229 continue;
5230
5231 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5232
5233 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5234 * The branch target is in the same 4KB region as the
5235 first half of the branch.
5236 * The instruction before the branch is a 32-bit
5237 length non-branch instruction. */
5238 for (i = span_start; i < span_end;)
5239 {
5240 unsigned int insn = bfd_getl16 (&contents[i]);
5241 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5242 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5243
99059e56
RM		 5244 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5245 insn_32bit = TRUE;
48229727
JB		 5246
5247 if (insn_32bit)
99059e56
RM		 5248 {
5249 /* Load the rest of the insn (in manual-friendly order). */
5250 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5251
5252 /* Encoding T4: B<c>.W. */
5253 is_b = (insn & 0xf800d000) == 0xf0009000;
5254 /* Encoding T1: BL<c>.W. */
5255 is_bl = (insn & 0xf800d000) == 0xf000d000;
5256 /* Encoding T2: BLX<c>.W. */
5257 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5258 /* Encoding T3: B<c>.W (not permitted in IT block). */
5259 is_bcc = (insn & 0xf800d000) == 0xf0008000
5260 && (insn & 0x07f00000) != 0x03800000;
5261 }
5262
5263 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5264
99059e56 5265 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5266 && insn_32bit
5267 && is_32bit_branch
5268 && last_was_32bit
5269 && ! last_was_branch)
99059e56
RM		 5270 {
5271 bfd_signed_vma offset = 0;
5272 bfd_boolean force_target_arm = FALSE;
48229727 5273 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5274 bfd_vma target;
5275 enum elf32_arm_stub_type stub_type = arm_stub_none;
5276 struct a8_erratum_reloc key, *found;
5277 bfd_boolean use_plt = FALSE;
48229727 5278
99059e56
RM		 5279 key.from = base_vma + i;
5280 found = (struct a8_erratum_reloc *)
5281 bsearch (&key, a8_relocs, num_a8_relocs,
5282 sizeof (struct a8_erratum_reloc),
5283 &a8_reloc_compare);
48229727
JB		 5284
5285 if (found)
5286 {
5287 char *error_message = NULL;
5288 struct elf_link_hash_entry *entry;
5289
5290 /* We don't care about the error returned from this
99059e56 5291 function, only if there is glue or not. */
48229727
JB		 5292 entry = find_thumb_glue (info, found->sym_name,
5293 &error_message);
5294
5295 if (entry)
5296 found->non_a8_stub = TRUE;
5297
92750f34 5298 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5299 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5300 && found->hash->root.plt.offset != (bfd_vma) -1)
5301 use_plt = TRUE;
5302
5303 if (found->r_type == R_ARM_THM_CALL)
5304 {
35fc36a8
RS		 5305 if (found->branch_type == ST_BRANCH_TO_ARM
5306 || use_plt)
92750f34
DJ		 5307 force_target_arm = TRUE;
5308 else
5309 force_target_thumb = TRUE;
5310 }
48229727
JB		 5311 }
5312
99059e56 5313 /* Check if we have an offending branch instruction. */
48229727
JB		 5314
5315 if (found && found->non_a8_stub)
5316 /* We've already made a stub for this instruction, e.g.
5317 it's a long branch or a Thumb->ARM stub. Assume that
5318 stub will suffice to work around the A8 erratum (see
5319 setting of always_after_branch above). */
5320 ;
99059e56
RM		 5321 else if (is_bcc)
5322 {
5323 offset = (insn & 0x7ff) << 1;
5324 offset |= (insn & 0x3f0000) >> 4;
5325 offset |= (insn & 0x2000) ? 0x40000 : 0;
5326 offset |= (insn & 0x800) ? 0x80000 : 0;
5327 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5328 if (offset & 0x100000)
5329 offset |= ~ ((bfd_signed_vma) 0xfffff);
5330 stub_type = arm_stub_a8_veneer_b_cond;
5331 }
5332 else if (is_b || is_bl || is_blx)
5333 {
5334 int s = (insn & 0x4000000) != 0;
5335 int j1 = (insn & 0x2000) != 0;
5336 int j2 = (insn & 0x800) != 0;
5337 int i1 = !(j1 ^ s);
5338 int i2 = !(j2 ^ s);
5339
5340 offset = (insn & 0x7ff) << 1;
5341 offset |= (insn & 0x3ff0000) >> 4;
5342 offset |= i2 << 22;
5343 offset |= i1 << 23;
5344 offset |= s << 24;
5345 if (offset & 0x1000000)
5346 offset |= ~ ((bfd_signed_vma) 0xffffff);
5347
5348 if (is_blx)
5349 offset &= ~ ((bfd_signed_vma) 3);
5350
5351 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5352 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5353 }
5354
5355 if (stub_type != arm_stub_none)
5356 {
5357 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5358
5359 /* The original instruction is a BL, but the target is
99059e56 5360 an ARM instruction. If we were not making a stub,
48229727
JB		 5361 the BL would have been converted to a BLX. Use the
5362 BLX stub instead in that case. */
5363 if (htab->use_blx && force_target_arm
5364 && stub_type == arm_stub_a8_veneer_bl)
5365 {
5366 stub_type = arm_stub_a8_veneer_blx;
5367 is_blx = TRUE;
5368 is_bl = FALSE;
5369 }
5370 /* Conversely, if the original instruction was
5371 BLX but the target is Thumb mode, use the BL
5372 stub. */
5373 else if (force_target_thumb
5374 && stub_type == arm_stub_a8_veneer_blx)
5375 {
5376 stub_type = arm_stub_a8_veneer_bl;
5377 is_blx = FALSE;
5378 is_bl = TRUE;
5379 }
5380
99059e56
RM		 5381 if (is_blx)
5382 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5383
99059e56
RM		 5384 /* If we found a relocation, use the proper destination,
5385 not the offset in the (unrelocated) instruction.
48229727
JB		 5386 Note this is always done if we switched the stub type
5387 above. */
99059e56
RM		 5388 if (found)
5389 offset =
81694485 5390 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5391
99059e56
RM		 5392 /* If the stub will use a Thumb-mode branch to a
5393 PLT target, redirect it to the preceding Thumb
5394 entry point. */
5395 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5396 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5397
99059e56 5398 target = pc_for_insn + offset;
48229727 5399
99059e56
RM		 5400 /* The BLX stub is ARM-mode code. Adjust the offset to
5401 take the different PC value (+8 instead of +4) into
48229727 5402 account. */
99059e56
RM		 5403 if (stub_type == arm_stub_a8_veneer_blx)
5404 offset += 4;
5405
5406 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5407 {
5408 char *stub_name = NULL;
5409
5410 if (num_a8_fixes == a8_fix_table_size)
5411 {
5412 a8_fix_table_size *= 2;
5413 a8_fixes = (struct a8_erratum_fix *)
5414 bfd_realloc (a8_fixes,
5415 sizeof (struct a8_erratum_fix)
5416 * a8_fix_table_size);
5417 }
48229727 5418
eb7c4339
NS		 5419 if (num_a8_fixes < prev_num_a8_fixes)
5420 {
5421 /* If we're doing a subsequent scan,
5422 check if we've found the same fix as
5423 before, and try and reuse the stub
5424 name. */
5425 stub_name = a8_fixes[num_a8_fixes].stub_name;
5426 if ((a8_fixes[num_a8_fixes].section != section)
5427 || (a8_fixes[num_a8_fixes].offset != i))
5428 {
5429 free (stub_name);
5430 stub_name = NULL;
5431 *stub_changed_p = TRUE;
5432 }
5433 }
5434
5435 if (!stub_name)
5436 {
21d799b5 5437 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5438 if (stub_name != NULL)
5439 sprintf (stub_name, "%x:%x", section->id, i);
5440 }
48229727 5441
99059e56
RM		 5442 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5443 a8_fixes[num_a8_fixes].section = section;
5444 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5445 a8_fixes[num_a8_fixes].target_offset =
5446 target - base_vma;
99059e56
RM		 5447 a8_fixes[num_a8_fixes].orig_insn = insn;
5448 a8_fixes[num_a8_fixes].stub_name = stub_name;
5449 a8_fixes[num_a8_fixes].stub_type = stub_type;
5450 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5451 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5452
99059e56
RM		 5453 num_a8_fixes++;
5454 }
5455 }
5456 }
48229727 5457
99059e56
RM		 5458 i += insn_32bit ? 4 : 2;
5459 last_was_32bit = insn_32bit;
48229727 5460 last_was_branch = is_32bit_branch;
99059e56
RM		 5461 }
5462 }
48229727
JB		 5463
5464 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5465 free (contents);
48229727 5466 }
fe33d2fa 5467
48229727
JB		 5468 *a8_fixes_p = a8_fixes;
5469 *num_a8_fixes_p = num_a8_fixes;
5470 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5471
81694485 5472 return FALSE;
48229727
JB		 5473}
5474
b715f643
TP		 5475/* Create or update a stub entry depending on whether the stub can already be
5476 found in HTAB. The stub is identified by:
5477 - its type STUB_TYPE
5478 - its source branch (note that several can share the same stub) whose
5479 section and relocation (if any) are given by SECTION and IRELA
5480 respectively
5481 - its target symbol whose input section, hash, name, value and branch type
5482 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5483 respectively
5484
5485 If found, the value of the stub's target symbol is updated from SYM_VALUE
5486 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5487 TRUE and the stub entry is initialized.
5488
0955507f
TP		 5489 Returns the stub that was created or updated, or NULL if an error
5490 occurred. */
b715f643 5491
0955507f 5492static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5493elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5494 enum elf32_arm_stub_type stub_type, asection *section,
5495 Elf_Internal_Rela *irela, asection *sym_sec,
5496 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5497 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5498 bfd_boolean *new_stub)
5499{
5500 const asection *id_sec;
5501 char *stub_name;
5502 struct elf32_arm_stub_hash_entry *stub_entry;
5503 unsigned int r_type;
4f4faa4d 5504 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5505
5506 BFD_ASSERT (stub_type != arm_stub_none);
5507 *new_stub = FALSE;
5508
4f4faa4d
TP		 5509 if (sym_claimed)
5510 stub_name = sym_name;
5511 else
5512 {
5513 BFD_ASSERT (irela);
5514 BFD_ASSERT (section);
c2abbbeb 5515 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5516
4f4faa4d
TP		 5517 /* Support for grouping stub sections. */
5518 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5519
4f4faa4d
TP		 5520 /* Get the name of this stub. */
5521 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5522 stub_type);
5523 if (!stub_name)
0955507f 5524 return NULL;
4f4faa4d 5525 }
b715f643
TP		 5526
5527 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5528 FALSE);
5529 /* The proper stub has already been created, just update its value. */
5530 if (stub_entry != NULL)
5531 {
4f4faa4d
TP		 5532 if (!sym_claimed)
5533 free (stub_name);
b715f643 5534 stub_entry->target_value = sym_value;
0955507f 5535 return stub_entry;
b715f643
TP		 5536 }
5537
daa4adae 5538 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5539 if (stub_entry == NULL)
5540 {
4f4faa4d
TP		 5541 if (!sym_claimed)
5542 free (stub_name);
0955507f 5543 return NULL;
b715f643
TP		 5544 }
5545
5546 stub_entry->target_value = sym_value;
5547 stub_entry->target_section = sym_sec;
5548 stub_entry->stub_type = stub_type;
5549 stub_entry->h = hash;
5550 stub_entry->branch_type = branch_type;
5551
4f4faa4d
TP		 5552 if (sym_claimed)
5553 stub_entry->output_name = sym_name;
5554 else
b715f643 5555 {
4f4faa4d
TP		 5556 if (sym_name == NULL)
5557 sym_name = "unnamed";
5558 stub_entry->output_name = (char *)
5559 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5560 + strlen (sym_name));
5561 if (stub_entry->output_name == NULL)
5562 {
5563 free (stub_name);
0955507f 5564 return NULL;
4f4faa4d 5565 }
b715f643 5566
4f4faa4d
TP		 5567 /* For historical reasons, use the existing names for ARM-to-Thumb and
5568 Thumb-to-ARM stubs. */
5569 r_type = ELF32_R_TYPE (irela->r_info);
5570 if ((r_type == (unsigned int) R_ARM_THM_CALL
5571 || r_type == (unsigned int) R_ARM_THM_JUMP24
5572 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5573 && branch_type == ST_BRANCH_TO_ARM)
5574 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5575 else if ((r_type == (unsigned int) R_ARM_CALL
5576 || r_type == (unsigned int) R_ARM_JUMP24)
5577 && branch_type == ST_BRANCH_TO_THUMB)
5578 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5579 else
5580 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5581 }
b715f643
TP		 5582
5583 *new_stub = TRUE;
0955507f 5584 return stub_entry;
b715f643
TP		 5585}
5586
4ba2ef8f
TP		 5587/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5588 gateway veneer to transition from non secure to secure state and create them
5589 accordingly.
5590
5591 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5592 defines the conditions that govern Secure Gateway veneer creation for a
5593 given symbol <SYM> as follows:
5594 - it has function type
5595 - it has non local binding
5596 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5597 same type, binding and value as <SYM> (called normal symbol).
5598 An entry function can handle secure state transition itself in which case
5599 its special symbol would have a different value from the normal symbol.
5600
5601 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5602 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5603 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5604 created.
4ba2ef8f 5605
0955507f 5606 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5607
5608static bfd_boolean
5609cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5610 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5611 int *cmse_stub_created)
4ba2ef8f
TP		 5612{
5613 const struct elf_backend_data *bed;
5614 Elf_Internal_Shdr *symtab_hdr;
5615 unsigned i, j, sym_count, ext_start;
5616 Elf_Internal_Sym *cmse_sym, *local_syms;
5617 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5618 enum arm_st_branch_type branch_type;
5619 char *sym_name, *lsym_name;
5620 bfd_vma sym_value;
5621 asection *section;
0955507f
TP		 5622 struct elf32_arm_stub_hash_entry *stub_entry;
5623 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5624
5625 bed = get_elf_backend_data (input_bfd);
5626 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5627 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5628 ext_start = symtab_hdr->sh_info;
5629 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5630 && out_attr[Tag_CPU_arch_profile].i == 'M');
5631
5632 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5633 if (local_syms == NULL)
5634 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5635 symtab_hdr->sh_info, 0, NULL, NULL,
5636 NULL);
5637 if (symtab_hdr->sh_info && local_syms == NULL)
5638 return FALSE;
5639
5640 /* Scan symbols. */
5641 for (i = 0; i < sym_count; i++)
5642 {
5643 cmse_invalid = FALSE;
5644
5645 if (i < ext_start)
5646 {
5647 cmse_sym = &local_syms[i];
5648 /* Not a special symbol. */
5649 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5650 continue;
5651 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5652 symtab_hdr->sh_link,
5653 cmse_sym->st_name);
5654 /* Special symbol with local binding. */
5655 cmse_invalid = TRUE;
5656 }
5657 else
5658 {
5659 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5660 sym_name = (char *) cmse_hash->root.root.root.string;
5661
5662 /* Not a special symbol. */
5663 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5664 continue;
5665
5666 /* Special symbol has incorrect binding or type. */
5667 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5668 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5669 || cmse_hash->root.type != STT_FUNC)
5670 cmse_invalid = TRUE;
5671 }
5672
5673 if (!is_v8m)
5674 {
4eca0228
AM		 5675 _bfd_error_handler (_("%B: Special symbol `%s' only allowed for "
5676 "ARMv8-M architecture or later."),
5677 input_bfd, sym_name);
4ba2ef8f
TP		 5678 is_v8m = TRUE; /* Avoid multiple warning. */
5679 ret = FALSE;
5680 }
5681
5682 if (cmse_invalid)
5683 {
4eca0228
AM		 5684 _bfd_error_handler (_("%B: invalid special symbol `%s'."),
5685 input_bfd, sym_name);
5686 _bfd_error_handler (_("It must be a global or weak function "
5687 "symbol."));
4ba2ef8f
TP		 5688 ret = FALSE;
5689 if (i < ext_start)
5690 continue;
5691 }
5692
5693 sym_name += strlen (CMSE_PREFIX);
5694 hash = (struct elf32_arm_link_hash_entry *)
5695 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5696
5697 /* No associated normal symbol or it is neither global nor weak. */
5698 if (!hash
5699 || (hash->root.root.type != bfd_link_hash_defined
5700 && hash->root.root.type != bfd_link_hash_defweak)
5701 || hash->root.type != STT_FUNC)
5702 {
5703 /* Initialize here to avoid warning about use of possibly
5704 uninitialized variable. */
5705 j = 0;
5706
5707 if (!hash)
5708 {
5709 /* Searching for a normal symbol with local binding. */
5710 for (; j < ext_start; j++)
5711 {
5712 lsym_name =
5713 bfd_elf_string_from_elf_section (input_bfd,
5714 symtab_hdr->sh_link,
5715 local_syms[j].st_name);
5716 if (!strcmp (sym_name, lsym_name))
5717 break;
5718 }
5719 }
5720
5721 if (hash || j < ext_start)
5722 {
4eca0228 5723 _bfd_error_handler
4ba2ef8f 5724 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
4eca0228 5725 _bfd_error_handler
4ba2ef8f
TP		 5726 (_("It must be a global or weak function symbol."));
5727 }
5728 else
4eca0228 5729 _bfd_error_handler
4ba2ef8f
TP		 5730 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5731 ret = FALSE;
5732 if (!hash)
5733 continue;
5734 }
5735
5736 sym_value = hash->root.root.u.def.value;
5737 section = hash->root.root.u.def.section;
5738
5739 if (cmse_hash->root.root.u.def.section != section)
5740 {
4eca0228 5741 _bfd_error_handler
4ba2ef8f
TP		 5742 (_("%B: `%s' and its special symbol are in different sections."),
5743 input_bfd, sym_name);
5744 ret = FALSE;
5745 }
5746 if (cmse_hash->root.root.u.def.value != sym_value)
5747 continue; /* Ignore: could be an entry function starting with SG. */
5748
5749 /* If this section is a link-once section that will be discarded, then
5750 don't create any stubs. */
5751 if (section->output_section == NULL)
5752 {
4eca0228 5753 _bfd_error_handler
4ba2ef8f
TP		 5754 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5755 continue;
5756 }
5757
5758 if (hash->root.size == 0)
5759 {
4eca0228 5760 _bfd_error_handler
4ba2ef8f
TP		 5761 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5762 ret = FALSE;
5763 }
5764
5765 if (!ret)
5766 continue;
5767 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5768 stub_entry
4ba2ef8f
TP		 5769 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5770 NULL, NULL, section, hash, sym_name,
5771 sym_value, branch_type, &new_stub);
5772
0955507f 5773 if (stub_entry == NULL)
4ba2ef8f
TP		 5774 ret = FALSE;
5775 else
5776 {
5777 BFD_ASSERT (new_stub);
0955507f 5778 (*cmse_stub_created)++;
4ba2ef8f
TP		 5779 }
5780 }
5781
5782 if (!symtab_hdr->contents)
5783 free (local_syms);
5784 return ret;
5785}
5786
0955507f
TP		 5787/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5788 code entry function, ie can be called from non secure code without using a
5789 veneer. */
5790
5791static bfd_boolean
5792cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5793{
42484486 5794 bfd_byte contents[4];
0955507f
TP		 5795 uint32_t first_insn;
5796 asection *section;
5797 file_ptr offset;
5798 bfd *abfd;
5799
5800 /* Defined symbol of function type. */
5801 if (hash->root.root.type != bfd_link_hash_defined
5802 && hash->root.root.type != bfd_link_hash_defweak)
5803 return FALSE;
5804 if (hash->root.type != STT_FUNC)
5805 return FALSE;
5806
5807 /* Read first instruction. */
5808 section = hash->root.root.u.def.section;
5809 abfd = section->owner;
5810 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5811 if (!bfd_get_section_contents (abfd, section, contents, offset,
5812 sizeof (contents)))
0955507f
TP		 5813 return FALSE;
5814
42484486
TP		 5815 first_insn = bfd_get_32 (abfd, contents);
5816
5817 /* Starts by SG instruction. */
0955507f
TP		 5818 return first_insn == 0xe97fe97f;
5819}
5820
5821/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5822 secure gateway veneers (ie. the veneers was not in the input import library)
5823 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5824
5825static bfd_boolean
5826arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5827{
5828 struct elf32_arm_stub_hash_entry *stub_entry;
5829 struct bfd_link_info *info;
5830
5831 /* Massage our args to the form they really have. */
5832 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5833 info = (struct bfd_link_info *) gen_info;
5834
5835 if (info->out_implib_bfd)
5836 return TRUE;
5837
5838 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5839 return TRUE;
5840
5841 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5842 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5843
5844 return TRUE;
5845}
5846
5847/* Set offset of each secure gateway veneers so that its address remain
5848 identical to the one in the input import library referred by
5849 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5850 (present in input import library but absent from the executable being
5851 linked) or if new veneers appeared and there is no output import library
5852 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5853 number of secure gateway veneers found in the input import library.
5854
5855 The function returns whether an error occurred. If no error occurred,
5856 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5857 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5858 veneer observed set for new veneers to be layed out after. */
5859
5860static bfd_boolean
5861set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5862 struct elf32_arm_link_hash_table *htab,
5863 int *cmse_stub_created)
5864{
5865 long symsize;
5866 char *sym_name;
5867 flagword flags;
5868 long i, symcount;
5869 bfd *in_implib_bfd;
5870 asection *stub_out_sec;
5871 bfd_boolean ret = TRUE;
5872 Elf_Internal_Sym *intsym;
5873 const char *out_sec_name;
5874 bfd_size_type cmse_stub_size;
5875 asymbol **sympp = NULL, *sym;
5876 struct elf32_arm_link_hash_entry *hash;
5877 const insn_sequence *cmse_stub_template;
5878 struct elf32_arm_stub_hash_entry *stub_entry;
5879 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5880 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5881 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5882
5883 /* No input secure gateway import library. */
5884 if (!htab->in_implib_bfd)
5885 return TRUE;
5886
5887 in_implib_bfd = htab->in_implib_bfd;
5888 if (!htab->cmse_implib)
5889 {
4eca0228
AM		 5890 _bfd_error_handler (_("%B: --in-implib only supported for Secure "
5891 "Gateway import libraries."), in_implib_bfd);
0955507f
TP		 5892 return FALSE;
5893 }
5894
5895 /* Get symbol table size. */
5896 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5897 if (symsize < 0)
5898 return FALSE;
5899
5900 /* Read in the input secure gateway import library's symbol table. */
5901 sympp = (asymbol **) xmalloc (symsize);
5902 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5903 if (symcount < 0)
5904 {
5905 ret = FALSE;
5906 goto free_sym_buf;
5907 }
5908
5909 htab->new_cmse_stub_offset = 0;
5910 cmse_stub_size =
5911 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5912 &cmse_stub_template,
5913 &cmse_stub_template_size);
5914 out_sec_name =
5915 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5916 stub_out_sec =
5917 bfd_get_section_by_name (htab->obfd, out_sec_name);
5918 if (stub_out_sec != NULL)
5919 cmse_stub_sec_vma = stub_out_sec->vma;
5920
5921 /* Set addresses of veneers mentionned in input secure gateway import
5922 library's symbol table. */
5923 for (i = 0; i < symcount; i++)
5924 {
5925 sym = sympp[i];
5926 flags = sym->flags;
5927 sym_name = (char *) bfd_asymbol_name (sym);
5928 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5929
5930 if (sym->section != bfd_abs_section_ptr
5931 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5932 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5933 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5934 != ST_BRANCH_TO_THUMB))
5935 {
4eca0228
AM		 5936 _bfd_error_handler (_("%B: invalid import library entry: `%s'."),
5937 in_implib_bfd, sym_name);
5938 _bfd_error_handler (_("Symbol should be absolute, global and "
5939 "refer to Thumb functions."));
0955507f
TP		 5940 ret = FALSE;
5941 continue;
5942 }
5943
5944 veneer_value = bfd_asymbol_value (sym);
5945 stub_offset = veneer_value - cmse_stub_sec_vma;
5946 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5947 FALSE, FALSE);
5948 hash = (struct elf32_arm_link_hash_entry *)
5949 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5950
5951 /* Stub entry should have been created by cmse_scan or the symbol be of
5952 a secure function callable from non secure code. */
5953 if (!stub_entry && !hash)
5954 {
5955 bfd_boolean new_stub;
5956
4eca0228 5957 _bfd_error_handler
0955507f
TP		 5958 (_("Entry function `%s' disappeared from secure code."), sym_name);
5959 hash = (struct elf32_arm_link_hash_entry *)
5960 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5961 stub_entry
5962 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5963 NULL, NULL, bfd_abs_section_ptr, hash,
5964 sym_name, veneer_value,
5965 ST_BRANCH_TO_THUMB, &new_stub);
5966 if (stub_entry == NULL)
5967 ret = FALSE;
5968 else
5969 {
5970 BFD_ASSERT (new_stub);
5971 new_cmse_stubs_created++;
5972 (*cmse_stub_created)++;
5973 }
5974 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5975 stub_entry->stub_offset = stub_offset;
5976 }
5977 /* Symbol found is not callable from non secure code. */
5978 else if (!stub_entry)
5979 {
5980 if (!cmse_entry_fct_p (hash))
5981 {
4eca0228
AM		 5982 _bfd_error_handler (_("`%s' refers to a non entry function."),
5983 sym_name);
0955507f
TP		 5984 ret = FALSE;
5985 }
5986 continue;
5987 }
5988 else
5989 {
5990 /* Only stubs for SG veneers should have been created. */
5991 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5992
5993 /* Check visibility hasn't changed. */
5994 if (!!(flags & BSF_GLOBAL)
5995 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 5996 _bfd_error_handler
0955507f
TP		 5997 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
5998 sym_name);
5999
6000 stub_entry->stub_offset = stub_offset;
6001 }
6002
6003 /* Size should match that of a SG veneer. */
6004 if (intsym->st_size != cmse_stub_size)
6005 {
4eca0228
AM		 6006 _bfd_error_handler (_("%B: incorrect size for symbol `%s'."),
6007 in_implib_bfd, sym_name);
0955507f
TP		 6008 ret = FALSE;
6009 }
6010
6011 /* Previous veneer address is before current SG veneer section. */
6012 if (veneer_value < cmse_stub_sec_vma)
6013 {
6014 /* Avoid offset underflow. */
6015 if (stub_entry)
6016 stub_entry->stub_offset = 0;
6017 stub_offset = 0;
6018 ret = FALSE;
6019 }
6020
6021 /* Complain if stub offset not a multiple of stub size. */
6022 if (stub_offset % cmse_stub_size)
6023 {
4eca0228 6024 _bfd_error_handler
0955507f
TP		 6025 (_("Offset of veneer for entry function `%s' not a multiple of "
6026 "its size."), sym_name);
6027 ret = FALSE;
6028 }
6029
6030 if (!ret)
6031 continue;
6032
6033 new_cmse_stubs_created--;
6034 if (veneer_value < cmse_stub_array_start)
6035 cmse_stub_array_start = veneer_value;
6036 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6037 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6038 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6039 }
6040
6041 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6042 {
6043 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6044 _bfd_error_handler
0955507f
TP		 6045 (_("new entry function(s) introduced but no output import library "
6046 "specified:"));
6047 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6048 }
6049
6050 if (cmse_stub_array_start != cmse_stub_sec_vma)
6051 {
4eca0228 6052 _bfd_error_handler
0955507f
TP		 6053 (_("Start address of `%s' is different from previous link."),
6054 out_sec_name);
6055 ret = FALSE;
6056 }
6057
6058free_sym_buf:
6059 free (sympp);
6060 return ret;
6061}
6062
906e58ca
NC		 6063/* Determine and set the size of the stub section for a final link.
6064
6065 The basic idea here is to examine all the relocations looking for
6066 PC-relative calls to a target that is unreachable with a "bl"
6067 instruction. */
6068
6069bfd_boolean
6070elf32_arm_size_stubs (bfd *output_bfd,
6071 bfd *stub_bfd,
6072 struct bfd_link_info *info,
6073 bfd_signed_vma group_size,
7a89b94e 6074 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6075 asection *,
7a89b94e 6076 unsigned int),
906e58ca
NC		 6077 void (*layout_sections_again) (void))
6078{
0955507f 6079 bfd_boolean ret = TRUE;
4ba2ef8f 6080 obj_attribute *out_attr;
0955507f 6081 int cmse_stub_created = 0;
906e58ca 6082 bfd_size_type stub_group_size;
4ba2ef8f 6083 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6084 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6085 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6086 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6087 struct a8_erratum_reloc *a8_relocs = NULL;
6088 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6089
4dfe6ac6
NC		 6090 if (htab == NULL)
6091 return FALSE;
6092
48229727
JB		 6093 if (htab->fix_cortex_a8)
6094 {
21d799b5 6095 a8_fixes = (struct a8_erratum_fix *)
99059e56 6096 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6097 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6098 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6099 }
906e58ca
NC		 6100
6101 /* Propagate mach to stub bfd, because it may not have been
6102 finalized when we created stub_bfd. */
6103 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6104 bfd_get_mach (output_bfd));
6105
6106 /* Stash our params away. */
6107 htab->stub_bfd = stub_bfd;
6108 htab->add_stub_section = add_stub_section;
6109 htab->layout_sections_again = layout_sections_again;
07d72278 6110 stubs_always_after_branch = group_size < 0;
48229727 6111
4ba2ef8f
TP		 6112 out_attr = elf_known_obj_attributes_proc (output_bfd);
6113 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6114
48229727
JB		 6115 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6116 as the first half of a 32-bit branch straddling two 4K pages. This is a
6117 crude way of enforcing that. */
6118 if (htab->fix_cortex_a8)
6119 stubs_always_after_branch = 1;
6120
906e58ca
NC		 6121 if (group_size < 0)
6122 stub_group_size = -group_size;
6123 else
6124 stub_group_size = group_size;
6125
6126 if (stub_group_size == 1)
6127 {
6128 /* Default values. */
6129 /* Thumb branch range is +-4MB has to be used as the default
6130 maximum size (a given section can contain both ARM and Thumb
6131 code, so the worst case has to be taken into account).
6132
6133 This value is 24K less than that, which allows for 2025
6134 12-byte stubs. If we exceed that, then we will fail to link.
6135 The user will have to relink with an explicit group size
6136 option. */
6137 stub_group_size = 4170000;
6138 }
6139
07d72278 6140 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6141
3ae046cc
NS		 6142 /* If we're applying the cortex A8 fix, we need to determine the
6143 program header size now, because we cannot change it later --
6144 that could alter section placements. Notice the A8 erratum fix
6145 ends up requiring the section addresses to remain unchanged
6146 modulo the page size. That's something we cannot represent
6147 inside BFD, and we don't want to force the section alignment to
6148 be the page size. */
6149 if (htab->fix_cortex_a8)
6150 (*htab->layout_sections_again) ();
6151
906e58ca
NC		 6152 while (1)
6153 {
6154 bfd *input_bfd;
6155 unsigned int bfd_indx;
6156 asection *stub_sec;
d7c5bd02 6157 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6158 bfd_boolean stub_changed = FALSE;
6159 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6160
48229727 6161 num_a8_fixes = 0;
906e58ca
NC		 6162 for (input_bfd = info->input_bfds, bfd_indx = 0;
6163 input_bfd != NULL;
c72f2fb2 6164 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6165 {
6166 Elf_Internal_Shdr *symtab_hdr;
6167 asection *section;
6168 Elf_Internal_Sym *local_syms = NULL;
6169
99059e56
RM		 6170 if (!is_arm_elf (input_bfd))
6171 continue;
adbcc655 6172
48229727
JB		 6173 num_a8_relocs = 0;
6174
906e58ca
NC		 6175 /* We'll need the symbol table in a second. */
6176 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6177 if (symtab_hdr->sh_info == 0)
6178 continue;
6179
4ba2ef8f
TP		 6180 /* Limit scan of symbols to object file whose profile is
6181 Microcontroller to not hinder performance in the general case. */
6182 if (m_profile && first_veneer_scan)
6183 {
6184 struct elf_link_hash_entry **sym_hashes;
6185
6186 sym_hashes = elf_sym_hashes (input_bfd);
6187 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6188 &cmse_stub_created))
4ba2ef8f 6189 goto error_ret_free_local;
0955507f
TP		 6190
6191 if (cmse_stub_created != 0)
6192 stub_changed = TRUE;
4ba2ef8f
TP		 6193 }
6194
906e58ca
NC		 6195 /* Walk over each section attached to the input bfd. */
6196 for (section = input_bfd->sections;
6197 section != NULL;
6198 section = section->next)
6199 {
6200 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6201
6202 /* If there aren't any relocs, then there's nothing more
6203 to do. */
6204 if ((section->flags & SEC_RELOC) == 0
6205 || section->reloc_count == 0
6206 || (section->flags & SEC_CODE) == 0)
6207 continue;
6208
6209 /* If this section is a link-once section that will be
6210 discarded, then don't create any stubs. */
6211 if (section->output_section == NULL
6212 || section->output_section->owner != output_bfd)
6213 continue;
6214
6215 /* Get the relocs. */
6216 internal_relocs
6217 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6218 NULL, info->keep_memory);
6219 if (internal_relocs == NULL)
6220 goto error_ret_free_local;
6221
6222 /* Now examine each relocation. */
6223 irela = internal_relocs;
6224 irelaend = irela + section->reloc_count;
6225 for (; irela < irelaend; irela++)
6226 {
6227 unsigned int r_type, r_indx;
906e58ca
NC		 6228 asection *sym_sec;
6229 bfd_vma sym_value;
6230 bfd_vma destination;
6231 struct elf32_arm_link_hash_entry *hash;
7413f23f 6232 const char *sym_name;
34e77a92 6233 unsigned char st_type;
35fc36a8 6234 enum arm_st_branch_type branch_type;
48229727 6235 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6236
6237 r_type = ELF32_R_TYPE (irela->r_info);
6238 r_indx = ELF32_R_SYM (irela->r_info);
6239
6240 if (r_type >= (unsigned int) R_ARM_max)
6241 {
6242 bfd_set_error (bfd_error_bad_value);
6243 error_ret_free_internal:
6244 if (elf_section_data (section)->relocs == NULL)
6245 free (internal_relocs);
15dd01b1
TP		 6246 /* Fall through. */
6247 error_ret_free_local:
6248 if (local_syms != NULL
6249 && (symtab_hdr->contents
6250 != (unsigned char *) local_syms))
6251 free (local_syms);
6252 return FALSE;
906e58ca 6253 }
b38cadfb 6254
0855e32b
NS		 6255 hash = NULL;
6256 if (r_indx >= symtab_hdr->sh_info)
6257 hash = elf32_arm_hash_entry
6258 (elf_sym_hashes (input_bfd)
6259 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6260
0855e32b
NS		 6261 /* Only look for stubs on branch instructions, or
6262 non-relaxed TLSCALL */
906e58ca 6263 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6264 && (r_type != (unsigned int) R_ARM_THM_CALL)
6265 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6266 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6267 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6268 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6269 && (r_type != (unsigned int) R_ARM_PLT32)
6270 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6271 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6272 && r_type == elf32_arm_tls_transition
6273 (info, r_type, &hash->root)
6274 && ((hash ? hash->tls_type
6275 : (elf32_arm_local_got_tls_type
6276 (input_bfd)[r_indx]))
6277 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6278 continue;
6279
6280 /* Now determine the call target, its name, value,
6281 section. */
6282 sym_sec = NULL;
6283 sym_value = 0;
6284 destination = 0;
7413f23f 6285 sym_name = NULL;
b38cadfb 6286
0855e32b
NS		 6287 if (r_type == (unsigned int) R_ARM_TLS_CALL
6288 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6289 {
6290 /* A non-relaxed TLS call. The target is the
6291 plt-resident trampoline and nothing to do
6292 with the symbol. */
6293 BFD_ASSERT (htab->tls_trampoline > 0);
6294 sym_sec = htab->root.splt;
6295 sym_value = htab->tls_trampoline;
6296 hash = 0;
34e77a92 6297 st_type = STT_FUNC;
35fc36a8 6298 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6299 }
6300 else if (!hash)
906e58ca
NC		 6301 {
6302 /* It's a local symbol. */
6303 Elf_Internal_Sym *sym;
906e58ca
NC		 6304
6305 if (local_syms == NULL)
6306 {
6307 local_syms
6308 = (Elf_Internal_Sym *) symtab_hdr->contents;
6309 if (local_syms == NULL)
6310 local_syms
6311 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6312 symtab_hdr->sh_info, 0,
6313 NULL, NULL, NULL);
6314 if (local_syms == NULL)
6315 goto error_ret_free_internal;
6316 }
6317
6318 sym = local_syms + r_indx;
f6d250ce
TS		 6319 if (sym->st_shndx == SHN_UNDEF)
6320 sym_sec = bfd_und_section_ptr;
6321 else if (sym->st_shndx == SHN_ABS)
6322 sym_sec = bfd_abs_section_ptr;
6323 else if (sym->st_shndx == SHN_COMMON)
6324 sym_sec = bfd_com_section_ptr;
6325 else
6326 sym_sec =
6327 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6328
ffcb4889
NS		 6329 if (!sym_sec)
6330 /* This is an undefined symbol. It can never
6a631e86 6331 be resolved. */
ffcb4889 6332 continue;
fe33d2fa 6333
906e58ca
NC		 6334 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6335 sym_value = sym->st_value;
6336 destination = (sym_value + irela->r_addend
6337 + sym_sec->output_offset
6338 + sym_sec->output_section->vma);
34e77a92 6339 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6340 branch_type =
6341 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6342 sym_name
6343 = bfd_elf_string_from_elf_section (input_bfd,
6344 symtab_hdr->sh_link,
6345 sym->st_name);
906e58ca
NC		 6346 }
6347 else
6348 {
6349 /* It's an external symbol. */
906e58ca
NC		 6350 while (hash->root.root.type == bfd_link_hash_indirect
6351 || hash->root.root.type == bfd_link_hash_warning)
6352 hash = ((struct elf32_arm_link_hash_entry *)
6353 hash->root.root.u.i.link);
6354
6355 if (hash->root.root.type == bfd_link_hash_defined
6356 || hash->root.root.type == bfd_link_hash_defweak)
6357 {
6358 sym_sec = hash->root.root.u.def.section;
6359 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6360
6361 struct elf32_arm_link_hash_table *globals =
6362 elf32_arm_hash_table (info);
6363
6364 /* For a destination in a shared library,
6365 use the PLT stub as target address to
6366 decide whether a branch stub is
6367 needed. */
4dfe6ac6 6368 if (globals != NULL
362d30a1 6369 && globals->root.splt != NULL
4dfe6ac6 6370 && hash != NULL
022f8312
CL		 6371 && hash->root.plt.offset != (bfd_vma) -1)
6372 {
362d30a1 6373 sym_sec = globals->root.splt;
022f8312
CL		 6374 sym_value = hash->root.plt.offset;
6375 if (sym_sec->output_section != NULL)
6376 destination = (sym_value
6377 + sym_sec->output_offset
6378 + sym_sec->output_section->vma);
6379 }
6380 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6381 destination = (sym_value + irela->r_addend
6382 + sym_sec->output_offset
6383 + sym_sec->output_section->vma);
6384 }
69c5861e
CL		 6385 else if ((hash->root.root.type == bfd_link_hash_undefined)
6386 || (hash->root.root.type == bfd_link_hash_undefweak))
6387 {
6388 /* For a shared library, use the PLT stub as
6389 target address to decide whether a long
6390 branch stub is needed.
6391 For absolute code, they cannot be handled. */
6392 struct elf32_arm_link_hash_table *globals =
6393 elf32_arm_hash_table (info);
6394
4dfe6ac6 6395 if (globals != NULL
362d30a1 6396 && globals->root.splt != NULL
4dfe6ac6 6397 && hash != NULL
69c5861e
CL		 6398 && hash->root.plt.offset != (bfd_vma) -1)
6399 {
362d30a1 6400 sym_sec = globals->root.splt;
69c5861e
CL		 6401 sym_value = hash->root.plt.offset;
6402 if (sym_sec->output_section != NULL)
6403 destination = (sym_value
6404 + sym_sec->output_offset
6405 + sym_sec->output_section->vma);
6406 }
6407 else
6408 continue;
6409 }
906e58ca
NC		 6410 else
6411 {
6412 bfd_set_error (bfd_error_bad_value);
6413 goto error_ret_free_internal;
6414 }
34e77a92 6415 st_type = hash->root.type;
39d911fc
TP		 6416 branch_type =
6417 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6418 sym_name = hash->root.root.root.string;
906e58ca
NC		 6419 }
6420
48229727 6421 do
7413f23f 6422 {
b715f643 6423 bfd_boolean new_stub;
0955507f 6424 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6425
48229727
JB		 6426 /* Determine what (if any) linker stub is needed. */
6427 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6428 st_type, &branch_type,
6429 hash, destination, sym_sec,
48229727
JB		 6430 input_bfd, sym_name);
6431 if (stub_type == arm_stub_none)
6432 break;
6433
48229727
JB		 6434 /* We've either created a stub for this reloc already,
6435 or we are about to. */
0955507f 6436 stub_entry =
b715f643
TP		 6437 elf32_arm_create_stub (htab, stub_type, section, irela,
6438 sym_sec, hash,
6439 (char *) sym_name, sym_value,
6440 branch_type, &new_stub);
7413f23f 6441
0955507f 6442 created_stub = stub_entry != NULL;
b715f643
TP		 6443 if (!created_stub)
6444 goto error_ret_free_internal;
6445 else if (!new_stub)
6446 break;
99059e56 6447 else
b715f643 6448 stub_changed = TRUE;
99059e56
RM		 6449 }
6450 while (0);
6451
6452 /* Look for relocations which might trigger Cortex-A8
6453 erratum. */
6454 if (htab->fix_cortex_a8
6455 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6456 || r_type == (unsigned int) R_ARM_THM_JUMP19
6457 || r_type == (unsigned int) R_ARM_THM_CALL
6458 || r_type == (unsigned int) R_ARM_THM_XPC22))
6459 {
6460 bfd_vma from = section->output_section->vma
6461 + section->output_offset
6462 + irela->r_offset;
6463
6464 if ((from & 0xfff) == 0xffe)
6465 {
6466 /* Found a candidate. Note we haven't checked the
6467 destination is within 4K here: if we do so (and
6468 don't create an entry in a8_relocs) we can't tell
6469 that a branch should have been relocated when
6470 scanning later. */
6471 if (num_a8_relocs == a8_reloc_table_size)
6472 {
6473 a8_reloc_table_size *= 2;
6474 a8_relocs = (struct a8_erratum_reloc *)
6475 bfd_realloc (a8_relocs,
6476 sizeof (struct a8_erratum_reloc)
6477 * a8_reloc_table_size);
6478 }
6479
6480 a8_relocs[num_a8_relocs].from = from;
6481 a8_relocs[num_a8_relocs].destination = destination;
6482 a8_relocs[num_a8_relocs].r_type = r_type;
6483 a8_relocs[num_a8_relocs].branch_type = branch_type;
6484 a8_relocs[num_a8_relocs].sym_name = sym_name;
6485 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6486 a8_relocs[num_a8_relocs].hash = hash;
6487
6488 num_a8_relocs++;
6489 }
6490 }
906e58ca
NC		 6491 }
6492
99059e56
RM		 6493 /* We're done with the internal relocs, free them. */
6494 if (elf_section_data (section)->relocs == NULL)
6495 free (internal_relocs);
6496 }
48229727 6497
99059e56 6498 if (htab->fix_cortex_a8)
48229727 6499 {
99059e56
RM		 6500 /* Sort relocs which might apply to Cortex-A8 erratum. */
6501 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6502 sizeof (struct a8_erratum_reloc),
99059e56 6503 &a8_reloc_compare);
48229727 6504
99059e56
RM		 6505 /* Scan for branches which might trigger Cortex-A8 erratum. */
6506 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6507 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6508 a8_relocs, num_a8_relocs,
6509 prev_num_a8_fixes, &stub_changed)
6510 != 0)
48229727 6511 goto error_ret_free_local;
5e681ec4 6512 }
7f991970
AM		 6513
6514 if (local_syms != NULL
6515 && symtab_hdr->contents != (unsigned char *) local_syms)
6516 {
6517 if (!info->keep_memory)
6518 free (local_syms);
6519 else
6520 symtab_hdr->contents = (unsigned char *) local_syms;
6521 }
5e681ec4
PB		 6522 }
6523
0955507f
TP		 6524 if (first_veneer_scan
6525 && !set_cmse_veneer_addr_from_implib (info, htab,
6526 &cmse_stub_created))
6527 ret = FALSE;
6528
eb7c4339 6529 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6530 stub_changed = TRUE;
48229727 6531
906e58ca
NC		 6532 if (!stub_changed)
6533 break;
5e681ec4 6534
906e58ca
NC		 6535 /* OK, we've added some stubs. Find out the new size of the
6536 stub sections. */
6537 for (stub_sec = htab->stub_bfd->sections;
6538 stub_sec != NULL;
6539 stub_sec = stub_sec->next)
3e6b1042
DJ		 6540 {
6541 /* Ignore non-stub sections. */
6542 if (!strstr (stub_sec->name, STUB_SUFFIX))
6543 continue;
6544
6545 stub_sec->size = 0;
6546 }
b34b2d70 6547
0955507f
TP		 6548 /* Add new SG veneers after those already in the input import
6549 library. */
6550 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6551 stub_type++)
6552 {
6553 bfd_vma *start_offset_p;
6554 asection **stub_sec_p;
6555
6556 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6557 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6558 if (start_offset_p == NULL)
6559 continue;
6560
6561 BFD_ASSERT (stub_sec_p != NULL);
6562 if (*stub_sec_p != NULL)
6563 (*stub_sec_p)->size = *start_offset_p;
6564 }
6565
d7c5bd02 6566 /* Compute stub section size, considering padding. */
906e58ca 6567 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6568 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6569 stub_type++)
6570 {
6571 int size, padding;
6572 asection **stub_sec_p;
6573
6574 padding = arm_dedicated_stub_section_padding (stub_type);
6575 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6576 /* Skip if no stub input section or no stub section padding
6577 required. */
6578 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6579 continue;
6580 /* Stub section padding required but no dedicated section. */
6581 BFD_ASSERT (stub_sec_p);
6582
6583 size = (*stub_sec_p)->size;
6584 size = (size + padding - 1) & ~(padding - 1);
6585 (*stub_sec_p)->size = size;
6586 }
906e58ca 6587
48229727
JB		 6588 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6589 if (htab->fix_cortex_a8)
99059e56
RM		 6590 for (i = 0; i < num_a8_fixes; i++)
6591 {
48229727 6592 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6593 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6594
6595 if (stub_sec == NULL)
7f991970 6596 return FALSE;
48229727 6597
99059e56
RM		 6598 stub_sec->size
6599 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6600 NULL);
6601 }
48229727
JB		 6602
6603
906e58ca
NC		 6604 /* Ask the linker to do its stuff. */
6605 (*htab->layout_sections_again) ();
4ba2ef8f 6606 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6607 }
6608
48229727
JB		 6609 /* Add stubs for Cortex-A8 erratum fixes now. */
6610 if (htab->fix_cortex_a8)
6611 {
6612 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6613 {
6614 struct elf32_arm_stub_hash_entry *stub_entry;
6615 char *stub_name = a8_fixes[i].stub_name;
6616 asection *section = a8_fixes[i].section;
6617 unsigned int section_id = a8_fixes[i].section->id;
6618 asection *link_sec = htab->stub_group[section_id].link_sec;
6619 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6620 const insn_sequence *template_sequence;
6621 int template_size, size = 0;
6622
6623 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6624 TRUE, FALSE);
6625 if (stub_entry == NULL)
6626 {
dae82561 6627 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 6628 section->owner, stub_name);
99059e56
RM		 6629 return FALSE;
6630 }
6631
6632 stub_entry->stub_sec = stub_sec;
0955507f 6633 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6634 stub_entry->id_sec = link_sec;
6635 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6636 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6637 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6638 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6639 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6640 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6641
99059e56
RM		 6642 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6643 &template_sequence,
6644 &template_size);
48229727 6645
99059e56
RM		 6646 stub_entry->stub_size = size;
6647 stub_entry->stub_template = template_sequence;
6648 stub_entry->stub_template_size = template_size;
6649 }
48229727
JB		 6650
6651 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6652 elf32_arm_write_section(). */
48229727
JB		 6653 htab->a8_erratum_fixes = a8_fixes;
6654 htab->num_a8_erratum_fixes = num_a8_fixes;
6655 }
6656 else
6657 {
6658 htab->a8_erratum_fixes = NULL;
6659 htab->num_a8_erratum_fixes = 0;
6660 }
0955507f 6661 return ret;
5e681ec4
PB		 6662}
6663
906e58ca
NC		 6664/* Build all the stubs associated with the current output file. The
6665 stubs are kept in a hash table attached to the main linker hash
6666 table. We also set up the .plt entries for statically linked PIC
6667 functions here. This function is called via arm_elf_finish in the
6668 linker. */
252b5132 6669
906e58ca
NC		 6670bfd_boolean
6671elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6672{
906e58ca
NC		 6673 asection *stub_sec;
6674 struct bfd_hash_table *table;
0955507f 6675 enum elf32_arm_stub_type stub_type;
906e58ca 6676 struct elf32_arm_link_hash_table *htab;
252b5132 6677
906e58ca 6678 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6679 if (htab == NULL)
6680 return FALSE;
252b5132 6681
906e58ca
NC		 6682 for (stub_sec = htab->stub_bfd->sections;
6683 stub_sec != NULL;
6684 stub_sec = stub_sec->next)
252b5132 6685 {
906e58ca
NC		 6686 bfd_size_type size;
6687
8029a119 6688 /* Ignore non-stub sections. */
906e58ca
NC		 6689 if (!strstr (stub_sec->name, STUB_SUFFIX))
6690 continue;
6691
d7c5bd02 6692 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6693 must at least be done for stub section requiring padding and for SG
6694 veneers to ensure that a non secure code branching to a removed SG
6695 veneer causes an error. */
906e58ca 6696 size = stub_sec->size;
21d799b5 6697 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6698 if (stub_sec->contents == NULL && size != 0)
6699 return FALSE;
0955507f 6700
906e58ca 6701 stub_sec->size = 0;
252b5132
RH		 6702 }
6703
0955507f
TP		 6704 /* Add new SG veneers after those already in the input import library. */
6705 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6706 {
6707 bfd_vma *start_offset_p;
6708 asection **stub_sec_p;
6709
6710 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6711 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6712 if (start_offset_p == NULL)
6713 continue;
6714
6715 BFD_ASSERT (stub_sec_p != NULL);
6716 if (*stub_sec_p != NULL)
6717 (*stub_sec_p)->size = *start_offset_p;
6718 }
6719
906e58ca
NC		 6720 /* Build the stubs as directed by the stub hash table. */
6721 table = &htab->stub_hash_table;
6722 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6723 if (htab->fix_cortex_a8)
6724 {
6725 /* Place the cortex a8 stubs last. */
6726 htab->fix_cortex_a8 = -1;
6727 bfd_hash_traverse (table, arm_build_one_stub, info);
6728 }
252b5132 6729
906e58ca 6730 return TRUE;
252b5132
RH		 6731}
6732
9b485d32
NC		 6733/* Locate the Thumb encoded calling stub for NAME. */
6734
252b5132 6735static struct elf_link_hash_entry *
57e8b36a
NC		 6736find_thumb_glue (struct bfd_link_info *link_info,
6737 const char *name,
f2a9dd69 6738 char **error_message)
252b5132
RH		 6739{
6740 char *tmp_name;
6741 struct elf_link_hash_entry *hash;
6742 struct elf32_arm_link_hash_table *hash_table;
6743
6744 /* We need a pointer to the armelf specific hash table. */
6745 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6746 if (hash_table == NULL)
6747 return NULL;
252b5132 6748
21d799b5 6749 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6750 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6751
6752 BFD_ASSERT (tmp_name);
6753
6754 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6755
6756 hash = elf_link_hash_lookup
b34976b6 6757 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6758
b1657152
AM		 6759 if (hash == NULL
6760 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6761 tmp_name, name) == -1)
6762 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6763
6764 free (tmp_name);
6765
6766 return hash;
6767}
6768
9b485d32
NC		 6769/* Locate the ARM encoded calling stub for NAME. */
6770
252b5132 6771static struct elf_link_hash_entry *
57e8b36a
NC		 6772find_arm_glue (struct bfd_link_info *link_info,
6773 const char *name,
f2a9dd69 6774 char **error_message)
252b5132
RH		 6775{
6776 char *tmp_name;
6777 struct elf_link_hash_entry *myh;
6778 struct elf32_arm_link_hash_table *hash_table;
6779
6780 /* We need a pointer to the elfarm specific hash table. */
6781 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6782 if (hash_table == NULL)
6783 return NULL;
252b5132 6784
21d799b5 6785 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6786 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6787
6788 BFD_ASSERT (tmp_name);
6789
6790 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6791
6792 myh = elf_link_hash_lookup
b34976b6 6793 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6794
b1657152
AM		 6795 if (myh == NULL
6796 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6797 tmp_name, name) == -1)
6798 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6799
6800 free (tmp_name);
6801
6802 return myh;
6803}
6804
8f6277f5 6805/* ARM->Thumb glue (static images):
252b5132
RH		 6806
6807 .arm
6808 __func_from_arm:
6809 ldr r12, __func_addr
6810 bx r12
6811 __func_addr:
906e58ca 6812 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6813
26079076
PB		 6814 (v5t static images)
6815 .arm
6816 __func_from_arm:
6817 ldr pc, __func_addr
6818 __func_addr:
906e58ca 6819 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6820
8f6277f5
PB		 6821 (relocatable images)
6822 .arm
6823 __func_from_arm:
6824 ldr r12, __func_offset
6825 add r12, r12, pc
6826 bx r12
6827 __func_offset:
8029a119 6828 .word func - . */
8f6277f5
PB		 6829
6830#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6831static const insn32 a2t1_ldr_insn = 0xe59fc000;
6832static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6833static const insn32 a2t3_func_addr_insn = 0x00000001;
6834
26079076
PB		 6835#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6836static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6837static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6838
8f6277f5
PB		 6839#define ARM2THUMB_PIC_GLUE_SIZE 16
6840static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6841static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6842static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6843
9b485d32 6844/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6845
8029a119
NC		 6846 .thumb .thumb
6847 .align 2 .align 2
6848 __func_from_thumb: __func_from_thumb:
6849 bx pc push {r6, lr}
6850 nop ldr r6, __func_addr
6851 .arm mov lr, pc
6852 b func bx r6
99059e56
RM		 6853 .arm
6854 ;; back_to_thumb
6855 ldmia r13! {r6, lr}
6856 bx lr
6857 __func_addr:
6858 .word func */
252b5132
RH		 6859
6860#define THUMB2ARM_GLUE_SIZE 8
6861static const insn16 t2a1_bx_pc_insn = 0x4778;
6862static const insn16 t2a2_noop_insn = 0x46c0;
6863static const insn32 t2a3_b_insn = 0xea000000;
6864
c7b8f16e 6865#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6866#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6867#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6868
845b51d6
PB		 6869#define ARM_BX_VENEER_SIZE 12
6870static const insn32 armbx1_tst_insn = 0xe3100001;
6871static const insn32 armbx2_moveq_insn = 0x01a0f000;
6872static const insn32 armbx3_bx_insn = 0xe12fff10;
6873
7e392df6 6874#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6875static void
6876arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6877{
6878 asection * s;
8029a119 6879 bfd_byte * contents;
252b5132 6880
8029a119 6881 if (size == 0)
3e6b1042
DJ		 6882 {
6883 /* Do not include empty glue sections in the output. */
6884 if (abfd != NULL)
6885 {
3d4d4302 6886 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6887 if (s != NULL)
6888 s->flags |= SEC_EXCLUDE;
6889 }
6890 return;
6891 }
252b5132 6892
8029a119 6893 BFD_ASSERT (abfd != NULL);
252b5132 6894
3d4d4302 6895 s = bfd_get_linker_section (abfd, name);
8029a119 6896 BFD_ASSERT (s != NULL);
252b5132 6897
21d799b5 6898 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6899
8029a119
NC		 6900 BFD_ASSERT (s->size == size);
6901 s->contents = contents;
6902}
906e58ca 6903
8029a119
NC		 6904bfd_boolean
6905bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6906{
6907 struct elf32_arm_link_hash_table * globals;
906e58ca 6908
8029a119
NC		 6909 globals = elf32_arm_hash_table (info);
6910 BFD_ASSERT (globals != NULL);
906e58ca 6911
8029a119
NC		 6912 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6913 globals->arm_glue_size,
6914 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6915
8029a119
NC		 6916 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6917 globals->thumb_glue_size,
6918 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6919
8029a119
NC		 6920 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6921 globals->vfp11_erratum_glue_size,
6922 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6923
a504d23a
LA		 6924 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6925 globals->stm32l4xx_erratum_glue_size,
6926 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6927
8029a119
NC		 6928 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6929 globals->bx_glue_size,
845b51d6
PB		 6930 ARM_BX_GLUE_SECTION_NAME);
6931
b34976b6 6932 return TRUE;
252b5132
RH		 6933}
6934
a4fd1a8e 6935/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6936 returns the symbol identifying the stub. */
6937
a4fd1a8e 6938static struct elf_link_hash_entry *
57e8b36a
NC		 6939record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6940 struct elf_link_hash_entry * h)
252b5132
RH		 6941{
6942 const char * name = h->root.root.string;
63b0f745 6943 asection * s;
252b5132
RH		 6944 char * tmp_name;
6945 struct elf_link_hash_entry * myh;
14a793b2 6946 struct bfd_link_hash_entry * bh;
252b5132 6947 struct elf32_arm_link_hash_table * globals;
dc810e39 6948 bfd_vma val;
2f475487 6949 bfd_size_type size;
252b5132
RH		 6950
6951 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6952 BFD_ASSERT (globals != NULL);
6953 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6954
3d4d4302 6955 s = bfd_get_linker_section
252b5132
RH		 6956 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6957
252b5132
RH		 6958 BFD_ASSERT (s != NULL);
6959
21d799b5 6960 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6961 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6962
6963 BFD_ASSERT (tmp_name);
6964
6965 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6966
6967 myh = elf_link_hash_lookup
b34976b6 6968 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6969
6970 if (myh != NULL)
6971 {
9b485d32 6972 /* We've already seen this guy. */
252b5132 6973 free (tmp_name);
a4fd1a8e 6974 return myh;
252b5132
RH		 6975 }
6976
57e8b36a
NC		 6977 /* The only trick here is using hash_table->arm_glue_size as the value.
6978 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6979 putting it. The +1 on the value marks that the stub has not been
6980 output yet - not that it is a Thumb function. */
14a793b2 6981 bh = NULL;
dc810e39
AM		 6982 val = globals->arm_glue_size + 1;
6983 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6984 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6985 NULL, TRUE, FALSE, &bh);
252b5132 6986
b7693d02
DJ		 6987 myh = (struct elf_link_hash_entry *) bh;
6988 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6989 myh->forced_local = 1;
6990
252b5132
RH		 6991 free (tmp_name);
6992
0e1862bb
L		 6993 if (bfd_link_pic (link_info)
6994 || globals->root.is_relocatable_executable
27e55c4d 6995 || globals->pic_veneer)
2f475487 6996 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6997 else if (globals->use_blx)
6998 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6999 else
2f475487
AM		 7000 size = ARM2THUMB_STATIC_GLUE_SIZE;
7001
7002 s->size += size;
7003 globals->arm_glue_size += size;
252b5132 7004
a4fd1a8e 7005 return myh;
252b5132
RH		 7006}
7007
845b51d6
PB		 7008/* Allocate space for ARMv4 BX veneers. */
7009
7010static void
7011record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7012{
7013 asection * s;
7014 struct elf32_arm_link_hash_table *globals;
7015 char *tmp_name;
7016 struct elf_link_hash_entry *myh;
7017 struct bfd_link_hash_entry *bh;
7018 bfd_vma val;
7019
7020 /* BX PC does not need a veneer. */
7021 if (reg == 15)
7022 return;
7023
7024 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7025 BFD_ASSERT (globals != NULL);
7026 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7027
7028 /* Check if this veneer has already been allocated. */
7029 if (globals->bx_glue_offset[reg])
7030 return;
7031
3d4d4302 7032 s = bfd_get_linker_section
845b51d6
PB		 7033 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7034
7035 BFD_ASSERT (s != NULL);
7036
7037 /* Add symbol for veneer. */
21d799b5
NC		 7038 tmp_name = (char *)
7039 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7040
845b51d6 7041 BFD_ASSERT (tmp_name);
906e58ca 7042
845b51d6 7043 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7044
845b51d6
PB		 7045 myh = elf_link_hash_lookup
7046 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7047
845b51d6 7048 BFD_ASSERT (myh == NULL);
906e58ca 7049
845b51d6
PB		 7050 bh = NULL;
7051 val = globals->bx_glue_size;
7052 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7053 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7054 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7055
7056 myh = (struct elf_link_hash_entry *) bh;
7057 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7058 myh->forced_local = 1;
7059
7060 s->size += ARM_BX_VENEER_SIZE;
7061 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7062 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7063}
7064
7065
c7b8f16e
JB		 7066/* Add an entry to the code/data map for section SEC. */
7067
7068static void
7069elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7070{
7071 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7072 unsigned int newidx;
906e58ca 7073
c7b8f16e
JB		 7074 if (sec_data->map == NULL)
7075 {
21d799b5 7076 sec_data->map = (elf32_arm_section_map *)
99059e56 7077 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7078 sec_data->mapcount = 0;
7079 sec_data->mapsize = 1;
7080 }
906e58ca 7081
c7b8f16e 7082 newidx = sec_data->mapcount++;
906e58ca 7083
c7b8f16e
JB		 7084 if (sec_data->mapcount > sec_data->mapsize)
7085 {
7086 sec_data->mapsize *= 2;
21d799b5 7087 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7088 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7089 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7090 }
7091
7092 if (sec_data->map)
7093 {
7094 sec_data->map[newidx].vma = vma;
7095 sec_data->map[newidx].type = type;
c7b8f16e 7096 }
c7b8f16e
JB		 7097}
7098
7099
7100/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7101 veneers are handled for now. */
7102
7103static bfd_vma
7104record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7105 elf32_vfp11_erratum_list *branch,
7106 bfd *branch_bfd,
7107 asection *branch_sec,
7108 unsigned int offset)
c7b8f16e
JB		 7109{
7110 asection *s;
7111 struct elf32_arm_link_hash_table *hash_table;
7112 char *tmp_name;
7113 struct elf_link_hash_entry *myh;
7114 struct bfd_link_hash_entry *bh;
7115 bfd_vma val;
7116 struct _arm_elf_section_data *sec_data;
c7b8f16e 7117 elf32_vfp11_erratum_list *newerr;
906e58ca 7118
c7b8f16e 7119 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7120 BFD_ASSERT (hash_table != NULL);
7121 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7122
3d4d4302 7123 s = bfd_get_linker_section
c7b8f16e 7124 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7125
c7b8f16e 7126 sec_data = elf32_arm_section_data (s);
906e58ca 7127
c7b8f16e 7128 BFD_ASSERT (s != NULL);
906e58ca 7129
21d799b5 7130 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7131 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7132
c7b8f16e 7133 BFD_ASSERT (tmp_name);
906e58ca 7134
c7b8f16e
JB		 7135 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7136 hash_table->num_vfp11_fixes);
906e58ca 7137
c7b8f16e
JB		 7138 myh = elf_link_hash_lookup
7139 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7140
c7b8f16e 7141 BFD_ASSERT (myh == NULL);
906e58ca 7142
c7b8f16e
JB		 7143 bh = NULL;
7144 val = hash_table->vfp11_erratum_glue_size;
7145 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7146 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7147 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7148
7149 myh = (struct elf_link_hash_entry *) bh;
7150 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7151 myh->forced_local = 1;
7152
7153 /* Link veneer back to calling location. */
c7e2358a 7154 sec_data->erratumcount += 1;
21d799b5
NC		 7155 newerr = (elf32_vfp11_erratum_list *)
7156 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7157
c7b8f16e
JB		 7158 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7159 newerr->vma = -1;
7160 newerr->u.v.branch = branch;
7161 newerr->u.v.id = hash_table->num_vfp11_fixes;
7162 branch->u.b.veneer = newerr;
7163
7164 newerr->next = sec_data->erratumlist;
7165 sec_data->erratumlist = newerr;
7166
7167 /* A symbol for the return from the veneer. */
7168 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7169 hash_table->num_vfp11_fixes);
7170
7171 myh = elf_link_hash_lookup
7172 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7173
c7b8f16e
JB		 7174 if (myh != NULL)
7175 abort ();
7176
7177 bh = NULL;
7178 val = offset + 4;
7179 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7180 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7181
c7b8f16e
JB		 7182 myh = (struct elf_link_hash_entry *) bh;
7183 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7184 myh->forced_local = 1;
7185
7186 free (tmp_name);
906e58ca 7187
c7b8f16e
JB		 7188 /* Generate a mapping symbol for the veneer section, and explicitly add an
7189 entry for that symbol to the code/data map for the section. */
7190 if (hash_table->vfp11_erratum_glue_size == 0)
7191 {
7192 bh = NULL;
7193 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7194 ever requires this erratum fix. */
c7b8f16e
JB		 7195 _bfd_generic_link_add_one_symbol (link_info,
7196 hash_table->bfd_of_glue_owner, "$a",
7197 BSF_LOCAL, s, 0, NULL,
99059e56 7198 TRUE, FALSE, &bh);
c7b8f16e
JB		 7199
7200 myh = (struct elf_link_hash_entry *) bh;
7201 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7202 myh->forced_local = 1;
906e58ca 7203
c7b8f16e 7204 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7205 BFDs. We must make a note of this generated mapping symbol
7206 ourselves so that code byteswapping works properly in
7207 elf32_arm_write_section. */
c7b8f16e
JB		 7208 elf32_arm_section_map_add (s, 'a', 0);
7209 }
906e58ca 7210
c7b8f16e
JB		 7211 s->size += VFP11_ERRATUM_VENEER_SIZE;
7212 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7213 hash_table->num_vfp11_fixes++;
906e58ca 7214
c7b8f16e
JB		 7215 /* The offset of the veneer. */
7216 return val;
7217}
7218
a504d23a
LA		 7219/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7220 veneers need to be handled because used only in Cortex-M. */
7221
7222static bfd_vma
7223record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7224 elf32_stm32l4xx_erratum_list *branch,
7225 bfd *branch_bfd,
7226 asection *branch_sec,
7227 unsigned int offset,
7228 bfd_size_type veneer_size)
7229{
7230 asection *s;
7231 struct elf32_arm_link_hash_table *hash_table;
7232 char *tmp_name;
7233 struct elf_link_hash_entry *myh;
7234 struct bfd_link_hash_entry *bh;
7235 bfd_vma val;
7236 struct _arm_elf_section_data *sec_data;
7237 elf32_stm32l4xx_erratum_list *newerr;
7238
7239 hash_table = elf32_arm_hash_table (link_info);
7240 BFD_ASSERT (hash_table != NULL);
7241 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7242
7243 s = bfd_get_linker_section
7244 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7245
7246 BFD_ASSERT (s != NULL);
7247
7248 sec_data = elf32_arm_section_data (s);
7249
7250 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7251 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7252
7253 BFD_ASSERT (tmp_name);
7254
7255 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7256 hash_table->num_stm32l4xx_fixes);
7257
7258 myh = elf_link_hash_lookup
7259 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7260
7261 BFD_ASSERT (myh == NULL);
7262
7263 bh = NULL;
7264 val = hash_table->stm32l4xx_erratum_glue_size;
7265 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7266 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7267 NULL, TRUE, FALSE, &bh);
7268
7269 myh = (struct elf_link_hash_entry *) bh;
7270 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7271 myh->forced_local = 1;
7272
7273 /* Link veneer back to calling location. */
7274 sec_data->stm32l4xx_erratumcount += 1;
7275 newerr = (elf32_stm32l4xx_erratum_list *)
7276 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7277
7278 newerr->type = STM32L4XX_ERRATUM_VENEER;
7279 newerr->vma = -1;
7280 newerr->u.v.branch = branch;
7281 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7282 branch->u.b.veneer = newerr;
7283
7284 newerr->next = sec_data->stm32l4xx_erratumlist;
7285 sec_data->stm32l4xx_erratumlist = newerr;
7286
7287 /* A symbol for the return from the veneer. */
7288 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7289 hash_table->num_stm32l4xx_fixes);
7290
7291 myh = elf_link_hash_lookup
7292 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7293
7294 if (myh != NULL)
7295 abort ();
7296
7297 bh = NULL;
7298 val = offset + 4;
7299 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7300 branch_sec, val, NULL, TRUE, FALSE, &bh);
7301
7302 myh = (struct elf_link_hash_entry *) bh;
7303 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7304 myh->forced_local = 1;
7305
7306 free (tmp_name);
7307
7308 /* Generate a mapping symbol for the veneer section, and explicitly add an
7309 entry for that symbol to the code/data map for the section. */
7310 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7311 {
7312 bh = NULL;
7313 /* Creates a THUMB symbol since there is no other choice. */
7314 _bfd_generic_link_add_one_symbol (link_info,
7315 hash_table->bfd_of_glue_owner, "$t",
7316 BSF_LOCAL, s, 0, NULL,
7317 TRUE, FALSE, &bh);
7318
7319 myh = (struct elf_link_hash_entry *) bh;
7320 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7321 myh->forced_local = 1;
7322
7323 /* The elf32_arm_init_maps function only cares about symbols from input
7324 BFDs. We must make a note of this generated mapping symbol
7325 ourselves so that code byteswapping works properly in
7326 elf32_arm_write_section. */
7327 elf32_arm_section_map_add (s, 't', 0);
7328 }
7329
7330 s->size += veneer_size;
7331 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7332 hash_table->num_stm32l4xx_fixes++;
7333
7334 /* The offset of the veneer. */
7335 return val;
7336}
7337
8029a119 7338#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7339 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7340 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7341
7342/* Create a fake section for use by the ARM backend of the linker. */
7343
7344static bfd_boolean
7345arm_make_glue_section (bfd * abfd, const char * name)
7346{
7347 asection * sec;
7348
3d4d4302 7349 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7350 if (sec != NULL)
7351 /* Already made. */
7352 return TRUE;
7353
3d4d4302 7354 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7355
7356 if (sec == NULL
7357 || !bfd_set_section_alignment (abfd, sec, 2))
7358 return FALSE;
7359
7360 /* Set the gc mark to prevent the section from being removed by garbage
7361 collection, despite the fact that no relocs refer to this section. */
7362 sec->gc_mark = 1;
7363
7364 return TRUE;
7365}
7366
1db37fe6
YG		 7367/* Set size of .plt entries. This function is called from the
7368 linker scripts in ld/emultempl/{armelf}.em. */
7369
7370void
7371bfd_elf32_arm_use_long_plt (void)
7372{
7373 elf32_arm_use_long_plt_entry = TRUE;
7374}
7375
8afb0e02
NC		 7376/* Add the glue sections to ABFD. This function is called from the
7377 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7378
b34976b6 7379bfd_boolean
57e8b36a
NC		 7380bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7381 struct bfd_link_info *info)
252b5132 7382{
a504d23a
LA		 7383 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7384 bfd_boolean dostm32l4xx = globals
7385 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7386 bfd_boolean addglue;
7387
8afb0e02
NC		 7388 /* If we are only performing a partial
7389 link do not bother adding the glue. */
0e1862bb 7390 if (bfd_link_relocatable (info))
b34976b6 7391 return TRUE;
252b5132 7392
a504d23a 7393 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7394 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7395 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7396 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7397
7398 if (!dostm32l4xx)
7399 return addglue;
7400
7401 return addglue
7402 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7403}
7404
daa4adae
TP		 7405/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7406 ensures they are not marked for deletion by
7407 strip_excluded_output_sections () when veneers are going to be created
7408 later. Not doing so would trigger assert on empty section size in
7409 lang_size_sections_1 (). */
7410
7411void
7412bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7413{
7414 enum elf32_arm_stub_type stub_type;
7415
7416 /* If we are only performing a partial
7417 link do not bother adding the glue. */
7418 if (bfd_link_relocatable (info))
7419 return;
7420
7421 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7422 {
7423 asection *out_sec;
7424 const char *out_sec_name;
7425
7426 if (!arm_dedicated_stub_output_section_required (stub_type))
7427 continue;
7428
7429 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7430 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7431 if (out_sec != NULL)
7432 out_sec->flags |= SEC_KEEP;
7433 }
7434}
7435
8afb0e02
NC		 7436/* Select a BFD to be used to hold the sections used by the glue code.
7437 This function is called from the linker scripts in ld/emultempl/
8029a119 7438 {armelf/pe}.em. */
8afb0e02 7439
b34976b6 7440bfd_boolean
57e8b36a 7441bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7442{
7443 struct elf32_arm_link_hash_table *globals;
7444
7445 /* If we are only performing a partial link
7446 do not bother getting a bfd to hold the glue. */
0e1862bb 7447 if (bfd_link_relocatable (info))
b34976b6 7448 return TRUE;
8afb0e02 7449
b7693d02
DJ		 7450 /* Make sure we don't attach the glue sections to a dynamic object. */
7451 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7452
8afb0e02 7453 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7454 BFD_ASSERT (globals != NULL);
7455
7456 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7457 return TRUE;
8afb0e02 7458
252b5132
RH		 7459 /* Save the bfd for later use. */
7460 globals->bfd_of_glue_owner = abfd;
cedb70c5 7461
b34976b6 7462 return TRUE;
252b5132
RH		 7463}
7464
906e58ca
NC		 7465static void
7466check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7467{
2de70689
MGD		 7468 int cpu_arch;
7469
b38cadfb 7470 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7471 Tag_CPU_arch);
7472
7473 if (globals->fix_arm1176)
7474 {
7475 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7476 globals->use_blx = 1;
7477 }
7478 else
7479 {
7480 if (cpu_arch > TAG_CPU_ARCH_V4T)
7481 globals->use_blx = 1;
7482 }
39b41c9c
PB		 7483}
7484
b34976b6 7485bfd_boolean
57e8b36a 7486bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7487 struct bfd_link_info *link_info)
252b5132
RH		 7488{
7489 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7490 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7491 Elf_Internal_Rela *irel, *irelend;
7492 bfd_byte *contents = NULL;
252b5132
RH		 7493
7494 asection *sec;
7495 struct elf32_arm_link_hash_table *globals;
7496
7497 /* If we are only performing a partial link do not bother
7498 to construct any glue. */
0e1862bb 7499 if (bfd_link_relocatable (link_info))
b34976b6 7500 return TRUE;
252b5132 7501
39ce1a6a
NC		 7502 /* Here we have a bfd that is to be included on the link. We have a
7503 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7504 globals = elf32_arm_hash_table (link_info);
252b5132 7505 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7506
7507 check_use_blx (globals);
252b5132 7508
d504ffc8 7509 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7510 {
d003868e
AM		 7511 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7512 abfd);
e489d0ae
PB		 7513 return FALSE;
7514 }
f21f3fe0 7515
39ce1a6a
NC		 7516 /* PR 5398: If we have not decided to include any loadable sections in
7517 the output then we will not have a glue owner bfd. This is OK, it
7518 just means that there is nothing else for us to do here. */
7519 if (globals->bfd_of_glue_owner == NULL)
7520 return TRUE;
7521
252b5132
RH		 7522 /* Rummage around all the relocs and map the glue vectors. */
7523 sec = abfd->sections;
7524
7525 if (sec == NULL)
b34976b6 7526 return TRUE;
252b5132
RH		 7527
7528 for (; sec != NULL; sec = sec->next)
7529 {
7530 if (sec->reloc_count == 0)
7531 continue;
7532
2f475487
AM		 7533 if ((sec->flags & SEC_EXCLUDE) != 0)
7534 continue;
7535
0ffa91dd 7536 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7537
9b485d32 7538 /* Load the relocs. */
6cdc0ccc 7539 internal_relocs
906e58ca 7540 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7541
6cdc0ccc
AM		 7542 if (internal_relocs == NULL)
7543 goto error_return;
252b5132 7544
6cdc0ccc
AM		 7545 irelend = internal_relocs + sec->reloc_count;
7546 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7547 {
7548 long r_type;
7549 unsigned long r_index;
252b5132
RH		 7550
7551 struct elf_link_hash_entry *h;
7552
7553 r_type = ELF32_R_TYPE (irel->r_info);
7554 r_index = ELF32_R_SYM (irel->r_info);
7555
9b485d32 7556 /* These are the only relocation types we care about. */
ba96a88f 7557 if ( r_type != R_ARM_PC24
845b51d6 7558 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7559 continue;
7560
7561 /* Get the section contents if we haven't done so already. */
7562 if (contents == NULL)
7563 {
7564 /* Get cached copy if it exists. */
7565 if (elf_section_data (sec)->this_hdr.contents != NULL)
7566 contents = elf_section_data (sec)->this_hdr.contents;
7567 else
7568 {
7569 /* Go get them off disk. */
57e8b36a 7570 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7571 goto error_return;
7572 }
7573 }
7574
845b51d6
PB		 7575 if (r_type == R_ARM_V4BX)
7576 {
7577 int reg;
7578
7579 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7580 record_arm_bx_glue (link_info, reg);
7581 continue;
7582 }
7583
a7c10850 7584 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7585 h = NULL;
7586
9b485d32 7587 /* We don't care about local symbols. */
252b5132
RH		 7588 if (r_index < symtab_hdr->sh_info)
7589 continue;
7590
9b485d32 7591 /* This is an external symbol. */
252b5132
RH		 7592 r_index -= symtab_hdr->sh_info;
7593 h = (struct elf_link_hash_entry *)
7594 elf_sym_hashes (abfd)[r_index];
7595
7596 /* If the relocation is against a static symbol it must be within
7597 the current section and so cannot be a cross ARM/Thumb relocation. */
7598 if (h == NULL)
7599 continue;
7600
d504ffc8
DJ		 7601 /* If the call will go through a PLT entry then we do not need
7602 glue. */
362d30a1 7603 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7604 continue;
7605
252b5132
RH		 7606 switch (r_type)
7607 {
7608 case R_ARM_PC24:
7609 /* This one is a call from arm code. We need to look up
99059e56
RM		 7610 the target of the call. If it is a thumb target, we
7611 insert glue. */
39d911fc
TP		 7612 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7613 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7614 record_arm_to_thumb_glue (link_info, h);
7615 break;
7616
252b5132 7617 default:
c6596c5e 7618 abort ();
252b5132
RH		 7619 }
7620 }
6cdc0ccc
AM		 7621
7622 if (contents != NULL
7623 && elf_section_data (sec)->this_hdr.contents != contents)
7624 free (contents);
7625 contents = NULL;
7626
7627 if (internal_relocs != NULL
7628 && elf_section_data (sec)->relocs != internal_relocs)
7629 free (internal_relocs);
7630 internal_relocs = NULL;
252b5132
RH		 7631 }
7632
b34976b6 7633 return TRUE;
9a5aca8c 7634
252b5132 7635error_return:
6cdc0ccc
AM		 7636 if (contents != NULL
7637 && elf_section_data (sec)->this_hdr.contents != contents)
7638 free (contents);
7639 if (internal_relocs != NULL
7640 && elf_section_data (sec)->relocs != internal_relocs)
7641 free (internal_relocs);
9a5aca8c 7642
b34976b6 7643 return FALSE;
252b5132 7644}
7e392df6 7645#endif
252b5132 7646
eb043451 7647
c7b8f16e
JB		 7648/* Initialise maps of ARM/Thumb/data for input BFDs. */
7649
7650void
7651bfd_elf32_arm_init_maps (bfd *abfd)
7652{
7653 Elf_Internal_Sym *isymbuf;
7654 Elf_Internal_Shdr *hdr;
7655 unsigned int i, localsyms;
7656
af1f4419
NC		 7657 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7658 if (! is_arm_elf (abfd))
7659 return;
7660
c7b8f16e
JB		 7661 if ((abfd->flags & DYNAMIC) != 0)
7662 return;
7663
0ffa91dd 7664 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7665 localsyms = hdr->sh_info;
7666
7667 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7668 should contain the number of local symbols, which should come before any
7669 global symbols. Mapping symbols are always local. */
7670 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7671 NULL);
7672
7673 /* No internal symbols read? Skip this BFD. */
7674 if (isymbuf == NULL)
7675 return;
7676
7677 for (i = 0; i < localsyms; i++)
7678 {
7679 Elf_Internal_Sym *isym = &isymbuf[i];
7680 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7681 const char *name;
906e58ca 7682
c7b8f16e 7683 if (sec != NULL
99059e56
RM		 7684 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7685 {
7686 name = bfd_elf_string_from_elf_section (abfd,
7687 hdr->sh_link, isym->st_name);
906e58ca 7688
99059e56 7689 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7690 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7691 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7692 }
c7b8f16e
JB		 7693 }
7694}
7695
7696
48229727
JB		 7697/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7698 say what they wanted. */
7699
7700void
7701bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7702{
7703 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7704 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7705
4dfe6ac6
NC		 7706 if (globals == NULL)
7707 return;
7708
48229727
JB		 7709 if (globals->fix_cortex_a8 == -1)
7710 {
7711 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7712 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7713 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7714 || out_attr[Tag_CPU_arch_profile].i == 0))
7715 globals->fix_cortex_a8 = 1;
7716 else
7717 globals->fix_cortex_a8 = 0;
7718 }
7719}
7720
7721
c7b8f16e
JB		 7722void
7723bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7724{
7725 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7726 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7727
4dfe6ac6
NC		 7728 if (globals == NULL)
7729 return;
c7b8f16e
JB		 7730 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7731 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7732 {
7733 switch (globals->vfp11_fix)
99059e56
RM		 7734 {
7735 case BFD_ARM_VFP11_FIX_DEFAULT:
7736 case BFD_ARM_VFP11_FIX_NONE:
7737 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7738 break;
7739
7740 default:
7741 /* Give a warning, but do as the user requests anyway. */
4eca0228 7742 _bfd_error_handler (_("%B: warning: selected VFP11 erratum "
99059e56
RM		 7743 "workaround is not necessary for target architecture"), obfd);
7744 }
c7b8f16e
JB		 7745 }
7746 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7747 /* For earlier architectures, we might need the workaround, but do not
7748 enable it by default. If users is running with broken hardware, they
7749 must enable the erratum fix explicitly. */
7750 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7751}
7752
a504d23a
LA		 7753void
7754bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7755{
7756 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7757 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7758
7759 if (globals == NULL)
7760 return;
7761
7762 /* We assume only Cortex-M4 may require the fix. */
7763 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7764 || out_attr[Tag_CPU_arch_profile].i != 'M')
7765 {
7766 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7767 /* Give a warning, but do as the user requests anyway. */
4eca0228 7768 _bfd_error_handler
a504d23a
LA		 7769 (_("%B: warning: selected STM32L4XX erratum "
7770 "workaround is not necessary for target architecture"), obfd);
7771 }
7772}
c7b8f16e 7773
906e58ca
NC		 7774enum bfd_arm_vfp11_pipe
7775{
c7b8f16e
JB		 7776 VFP11_FMAC,
7777 VFP11_LS,
7778 VFP11_DS,
7779 VFP11_BAD
7780};
7781
7782/* Return a VFP register number. This is encoded as RX:X for single-precision
7783 registers, or X:RX for double-precision registers, where RX is the group of
7784 four bits in the instruction encoding and X is the single extension bit.
7785 RX and X fields are specified using their lowest (starting) bit. The return
7786 value is:
7787
7788 0...31: single-precision registers s0...s31
7789 32...63: double-precision registers d0...d31.
906e58ca 7790
c7b8f16e
JB		 7791 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7792 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7793
c7b8f16e
JB		 7794static unsigned int
7795bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7796 unsigned int x)
c7b8f16e
JB		 7797{
7798 if (is_double)
7799 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7800 else
7801 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7802}
7803
7804/* Set bits in *WMASK according to a register number REG as encoded by
7805 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7806
7807static void
7808bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7809{
7810 if (reg < 32)
7811 *wmask |= 1 << reg;
7812 else if (reg < 48)
7813 *wmask |= 3 << ((reg - 32) * 2);
7814}
7815
7816/* Return TRUE if WMASK overwrites anything in REGS. */
7817
7818static bfd_boolean
7819bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7820{
7821 int i;
906e58ca 7822
c7b8f16e
JB		 7823 for (i = 0; i < numregs; i++)
7824 {
7825 unsigned int reg = regs[i];
7826
7827 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7828 return TRUE;
906e58ca 7829
c7b8f16e
JB		 7830 reg -= 32;
7831
7832 if (reg >= 16)
99059e56 7833 continue;
906e58ca 7834
c7b8f16e 7835 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7836 return TRUE;
c7b8f16e 7837 }
906e58ca 7838
c7b8f16e
JB		 7839 return FALSE;
7840}
7841
7842/* In this function, we're interested in two things: finding input registers
7843 for VFP data-processing instructions, and finding the set of registers which
7844 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7845 hold the written set, so FLDM etc. are easy to deal with (we're only
7846 interested in 32 SP registers or 16 dp registers, due to the VFP version
7847 implemented by the chip in question). DP registers are marked by setting
7848 both SP registers in the write mask). */
7849
7850static enum bfd_arm_vfp11_pipe
7851bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7852 int *numregs)
c7b8f16e 7853{
91d6fa6a 7854 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7855 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7856
7857 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7858 {
7859 unsigned int pqrs;
7860 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7861 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7862
7863 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7864 | ((insn & 0x00300000) >> 19)
7865 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7866
7867 switch (pqrs)
99059e56
RM		 7868 {
7869 case 0: /* fmac[sd]. */
7870 case 1: /* fnmac[sd]. */
7871 case 2: /* fmsc[sd]. */
7872 case 3: /* fnmsc[sd]. */
7873 vpipe = VFP11_FMAC;
7874 bfd_arm_vfp11_write_mask (destmask, fd);
7875 regs[0] = fd;
7876 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7877 regs[2] = fm;
7878 *numregs = 3;
7879 break;
7880
7881 case 4: /* fmul[sd]. */
7882 case 5: /* fnmul[sd]. */
7883 case 6: /* fadd[sd]. */
7884 case 7: /* fsub[sd]. */
7885 vpipe = VFP11_FMAC;
7886 goto vfp_binop;
7887
7888 case 8: /* fdiv[sd]. */
7889 vpipe = VFP11_DS;
7890 vfp_binop:
7891 bfd_arm_vfp11_write_mask (destmask, fd);
7892 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7893 regs[1] = fm;
7894 *numregs = 2;
7895 break;
7896
7897 case 15: /* extended opcode. */
7898 {
7899 unsigned int extn = ((insn >> 15) & 0x1e)
7900 | ((insn >> 7) & 1);
7901
7902 switch (extn)
7903 {
7904 case 0: /* fcpy[sd]. */
7905 case 1: /* fabs[sd]. */
7906 case 2: /* fneg[sd]. */
7907 case 8: /* fcmp[sd]. */
7908 case 9: /* fcmpe[sd]. */
7909 case 10: /* fcmpz[sd]. */
7910 case 11: /* fcmpez[sd]. */
7911 case 16: /* fuito[sd]. */
7912 case 17: /* fsito[sd]. */
7913 case 24: /* ftoui[sd]. */
7914 case 25: /* ftouiz[sd]. */
7915 case 26: /* ftosi[sd]. */
7916 case 27: /* ftosiz[sd]. */
7917 /* These instructions will not bounce due to underflow. */
7918 *numregs = 0;
7919 vpipe = VFP11_FMAC;
7920 break;
7921
7922 case 3: /* fsqrt[sd]. */
7923 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7924 registers to cause the erratum in previous instructions. */
7925 bfd_arm_vfp11_write_mask (destmask, fd);
7926 vpipe = VFP11_DS;
7927 break;
7928
7929 case 15: /* fcvt{ds,sd}. */
7930 {
7931 int rnum = 0;
7932
7933 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7934
7935 /* Only FCVTSD can underflow. */
99059e56
RM		 7936 if ((insn & 0x100) != 0)
7937 regs[rnum++] = fm;
c7b8f16e 7938
99059e56 7939 *numregs = rnum;
c7b8f16e 7940
99059e56
RM		 7941 vpipe = VFP11_FMAC;
7942 }
7943 break;
c7b8f16e 7944
99059e56
RM		 7945 default:
7946 return VFP11_BAD;
7947 }
7948 }
7949 break;
c7b8f16e 7950
99059e56
RM		 7951 default:
7952 return VFP11_BAD;
7953 }
c7b8f16e
JB		 7954 }
7955 /* Two-register transfer. */
7956 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7957 {
7958 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7959
c7b8f16e
JB		 7960 if ((insn & 0x100000) == 0)
7961 {
99059e56
RM		 7962 if (is_double)
7963 bfd_arm_vfp11_write_mask (destmask, fm);
7964 else
7965 {
7966 bfd_arm_vfp11_write_mask (destmask, fm);
7967 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7968 }
c7b8f16e
JB		 7969 }
7970
91d6fa6a 7971 vpipe = VFP11_LS;
c7b8f16e
JB		 7972 }
7973 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7974 {
7975 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7976 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7977
c7b8f16e 7978 switch (puw)
99059e56
RM		 7979 {
7980 case 0: /* Two-reg transfer. We should catch these above. */
7981 abort ();
906e58ca 7982
99059e56
RM		 7983 case 2: /* fldm[sdx]. */
7984 case 3:
7985 case 5:
7986 {
7987 unsigned int i, offset = insn & 0xff;
c7b8f16e 7988
99059e56
RM		 7989 if (is_double)
7990 offset >>= 1;
c7b8f16e 7991
99059e56
RM		 7992 for (i = fd; i < fd + offset; i++)
7993 bfd_arm_vfp11_write_mask (destmask, i);
7994 }
7995 break;
906e58ca 7996
99059e56
RM		 7997 case 4: /* fld[sd]. */
7998 case 6:
7999 bfd_arm_vfp11_write_mask (destmask, fd);
8000 break;
906e58ca 8001
99059e56
RM		 8002 default:
8003 return VFP11_BAD;
8004 }
c7b8f16e 8005
91d6fa6a 8006 vpipe = VFP11_LS;
c7b8f16e
JB		 8007 }
8008 /* Single-register transfer. Note L==0. */
8009 else if ((insn & 0x0f100e10) == 0x0e000a10)
8010 {
8011 unsigned int opcode = (insn >> 21) & 7;
8012 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8013
8014 switch (opcode)
99059e56
RM		 8015 {
8016 case 0: /* fmsr/fmdlr. */
8017 case 1: /* fmdhr. */
8018 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8019 destination register. I don't know if this is exactly right,
8020 but it is the conservative choice. */
8021 bfd_arm_vfp11_write_mask (destmask, fn);
8022 break;
8023
8024 case 7: /* fmxr. */
8025 break;
8026 }
c7b8f16e 8027
91d6fa6a 8028 vpipe = VFP11_LS;
c7b8f16e
JB		 8029 }
8030
91d6fa6a 8031 return vpipe;
c7b8f16e
JB		 8032}
8033
8034
8035static int elf32_arm_compare_mapping (const void * a, const void * b);
8036
8037
8038/* Look for potentially-troublesome code sequences which might trigger the
8039 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8040 (available from ARM) for details of the erratum. A short version is
8041 described in ld.texinfo. */
8042
8043bfd_boolean
8044bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8045{
8046 asection *sec;
8047 bfd_byte *contents = NULL;
8048 int state = 0;
8049 int regs[3], numregs = 0;
8050 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8051 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8052
4dfe6ac6
NC		 8053 if (globals == NULL)
8054 return FALSE;
8055
c7b8f16e
JB		 8056 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8057 The states transition as follows:
906e58ca 8058
c7b8f16e 8059 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8060 A VFP FMAC-pipeline instruction has been seen. Fill
8061 regs[0]..regs[numregs-1] with its input operands. Remember this
8062 instruction in 'first_fmac'.
c7b8f16e
JB		 8063
8064 1 -> 2
99059e56
RM		 8065 Any instruction, except for a VFP instruction which overwrites
8066 regs[*].
906e58ca 8067
c7b8f16e
JB		 8068 1 -> 3 [ -> 0 ] or
8069 2 -> 3 [ -> 0 ]
99059e56
RM		 8070 A VFP instruction has been seen which overwrites any of regs[*].
8071 We must make a veneer! Reset state to 0 before examining next
8072 instruction.
906e58ca 8073
c7b8f16e 8074 2 -> 0
99059e56
RM		 8075 If we fail to match anything in state 2, reset to state 0 and reset
8076 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8077
8078 If the VFP11 vector mode is in use, there must be at least two unrelated
8079 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8080 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8081
8082 /* If we are only performing a partial link do not bother
8083 to construct any glue. */
0e1862bb 8084 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8085 return TRUE;
8086
0ffa91dd
NC		 8087 /* Skip if this bfd does not correspond to an ELF image. */
8088 if (! is_arm_elf (abfd))
8089 return TRUE;
906e58ca 8090
c7b8f16e
JB		 8091 /* We should have chosen a fix type by the time we get here. */
8092 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8093
8094 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8095 return TRUE;
2e6030b9 8096
33a7ffc2
JM		 8097 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8098 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8099 return TRUE;
8100
c7b8f16e
JB		 8101 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8102 {
8103 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8104 struct _arm_elf_section_data *sec_data;
8105
8106 /* If we don't have executable progbits, we're not interested in this
99059e56 8107 section. Also skip if section is to be excluded. */
c7b8f16e 8108 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8109 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8110 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8111 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8112 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8113 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8114 continue;
c7b8f16e
JB		 8115
8116 sec_data = elf32_arm_section_data (sec);
906e58ca 8117
c7b8f16e 8118 if (sec_data->mapcount == 0)
99059e56 8119 continue;
906e58ca 8120
c7b8f16e
JB		 8121 if (elf_section_data (sec)->this_hdr.contents != NULL)
8122 contents = elf_section_data (sec)->this_hdr.contents;
8123 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8124 goto error_return;
8125
8126 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8127 elf32_arm_compare_mapping);
8128
8129 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8130 {
8131 unsigned int span_start = sec_data->map[span].vma;
8132 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8133 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8134 char span_type = sec_data->map[span].type;
8135
8136 /* FIXME: Only ARM mode is supported at present. We may need to
8137 support Thumb-2 mode also at some point. */
8138 if (span_type != 'a')
8139 continue;
8140
8141 for (i = span_start; i < span_end;)
8142 {
8143 unsigned int next_i = i + 4;
8144 unsigned int insn = bfd_big_endian (abfd)
8145 ? (contents[i] << 24)
8146 | (contents[i + 1] << 16)
8147 | (contents[i + 2] << 8)
8148 | contents[i + 3]
8149 : (contents[i + 3] << 24)
8150 | (contents[i + 2] << 16)
8151 | (contents[i + 1] << 8)
8152 | contents[i];
8153 unsigned int writemask = 0;
8154 enum bfd_arm_vfp11_pipe vpipe;
8155
8156 switch (state)
8157 {
8158 case 0:
8159 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8160 &numregs);
8161 /* I'm assuming the VFP11 erratum can trigger with denorm
8162 operands on either the FMAC or the DS pipeline. This might
8163 lead to slightly overenthusiastic veneer insertion. */
8164 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8165 {
8166 state = use_vector ? 1 : 2;
8167 first_fmac = i;
8168 veneer_of_insn = insn;
8169 }
8170 break;
8171
8172 case 1:
8173 {
8174 int other_regs[3], other_numregs;
8175 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8176 other_regs,
99059e56
RM		 8177 &other_numregs);
8178 if (vpipe != VFP11_BAD
8179 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8180 numregs))
99059e56
RM		 8181 state = 3;
8182 else
8183 state = 2;
8184 }
8185 break;
8186
8187 case 2:
8188 {
8189 int other_regs[3], other_numregs;
8190 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8191 other_regs,
99059e56
RM		 8192 &other_numregs);
8193 if (vpipe != VFP11_BAD
8194 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8195 numregs))
99059e56
RM		 8196 state = 3;
8197 else
8198 {
8199 state = 0;
8200 next_i = first_fmac + 4;
8201 }
8202 }
8203 break;
8204
8205 case 3:
8206 abort (); /* Should be unreachable. */
8207 }
8208
8209 if (state == 3)
8210 {
8211 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8212 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8213
8214 elf32_arm_section_data (sec)->erratumcount += 1;
8215
8216 newerr->u.b.vfp_insn = veneer_of_insn;
8217
8218 switch (span_type)
8219 {
8220 case 'a':
8221 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8222 break;
8223
8224 default:
8225 abort ();
8226 }
8227
8228 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8229 first_fmac);
8230
99059e56 8231 newerr->vma = -1;
c7b8f16e 8232
99059e56
RM		 8233 newerr->next = sec_data->erratumlist;
8234 sec_data->erratumlist = newerr;
c7b8f16e 8235
99059e56
RM		 8236 state = 0;
8237 }
c7b8f16e 8238
99059e56
RM		 8239 i = next_i;
8240 }
8241 }
906e58ca 8242
c7b8f16e 8243 if (contents != NULL
99059e56
RM		 8244 && elf_section_data (sec)->this_hdr.contents != contents)
8245 free (contents);
c7b8f16e
JB		 8246 contents = NULL;
8247 }
8248
8249 return TRUE;
8250
8251error_return:
8252 if (contents != NULL
8253 && elf_section_data (sec)->this_hdr.contents != contents)
8254 free (contents);
906e58ca 8255
c7b8f16e
JB		 8256 return FALSE;
8257}
8258
8259/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8260 after sections have been laid out, using specially-named symbols. */
8261
8262void
8263bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8264 struct bfd_link_info *link_info)
8265{
8266 asection *sec;
8267 struct elf32_arm_link_hash_table *globals;
8268 char *tmp_name;
906e58ca 8269
0e1862bb 8270 if (bfd_link_relocatable (link_info))
c7b8f16e 8271 return;
2e6030b9
MS		 8272
8273 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8274 if (! is_arm_elf (abfd))
2e6030b9
MS		 8275 return;
8276
c7b8f16e 8277 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8278 if (globals == NULL)
8279 return;
906e58ca 8280
21d799b5 8281 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8282 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8283
8284 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8285 {
8286 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8287 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8288
c7b8f16e 8289 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8290 {
8291 struct elf_link_hash_entry *myh;
8292 bfd_vma vma;
8293
8294 switch (errnode->type)
8295 {
8296 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8297 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8298 /* Find veneer symbol. */
8299 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8300 errnode->u.b.veneer->u.v.id);
8301
99059e56
RM		 8302 myh = elf_link_hash_lookup
8303 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8304
a504d23a 8305 if (myh == NULL)
4eca0228
AM		 8306 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8307 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8308
8309 vma = myh->root.u.def.section->output_section->vma
8310 + myh->root.u.def.section->output_offset
8311 + myh->root.u.def.value;
8312
8313 errnode->u.b.veneer->vma = vma;
8314 break;
8315
8316 case VFP11_ERRATUM_ARM_VENEER:
8317 case VFP11_ERRATUM_THUMB_VENEER:
8318 /* Find return location. */
8319 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8320 errnode->u.v.id);
8321
8322 myh = elf_link_hash_lookup
8323 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8324
8325 if (myh == NULL)
4eca0228
AM		 8326 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8327 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8328
8329 vma = myh->root.u.def.section->output_section->vma
8330 + myh->root.u.def.section->output_offset
8331 + myh->root.u.def.value;
8332
8333 errnode->u.v.branch->vma = vma;
8334 break;
8335
8336 default:
8337 abort ();
8338 }
8339 }
8340 }
8341
8342 free (tmp_name);
8343}
8344
8345/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8346 return locations after sections have been laid out, using
8347 specially-named symbols. */
8348
8349void
8350bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8351 struct bfd_link_info *link_info)
8352{
8353 asection *sec;
8354 struct elf32_arm_link_hash_table *globals;
8355 char *tmp_name;
8356
8357 if (bfd_link_relocatable (link_info))
8358 return;
8359
8360 /* Skip if this bfd does not correspond to an ELF image. */
8361 if (! is_arm_elf (abfd))
8362 return;
8363
8364 globals = elf32_arm_hash_table (link_info);
8365 if (globals == NULL)
8366 return;
8367
8368 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8369 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8370
8371 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8372 {
8373 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8374 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8375
8376 for (; errnode != NULL; errnode = errnode->next)
8377 {
8378 struct elf_link_hash_entry *myh;
8379 bfd_vma vma;
8380
8381 switch (errnode->type)
8382 {
8383 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8384 /* Find veneer symbol. */
8385 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8386 errnode->u.b.veneer->u.v.id);
8387
8388 myh = elf_link_hash_lookup
8389 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8390
8391 if (myh == NULL)
4eca0228
AM		 8392 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8393 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8394
8395 vma = myh->root.u.def.section->output_section->vma
8396 + myh->root.u.def.section->output_offset
8397 + myh->root.u.def.value;
8398
8399 errnode->u.b.veneer->vma = vma;
8400 break;
8401
8402 case STM32L4XX_ERRATUM_VENEER:
8403 /* Find return location. */
8404 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8405 errnode->u.v.id);
8406
8407 myh = elf_link_hash_lookup
8408 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8409
8410 if (myh == NULL)
4eca0228
AM		 8411 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8412 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8413
8414 vma = myh->root.u.def.section->output_section->vma
8415 + myh->root.u.def.section->output_offset
8416 + myh->root.u.def.value;
8417
8418 errnode->u.v.branch->vma = vma;
8419 break;
8420
8421 default:
8422 abort ();
8423 }
8424 }
8425 }
8426
8427 free (tmp_name);
8428}
8429
8430static inline bfd_boolean
8431is_thumb2_ldmia (const insn32 insn)
8432{
8433 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8434 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8435 return (insn & 0xffd02000) == 0xe8900000;
8436}
8437
8438static inline bfd_boolean
8439is_thumb2_ldmdb (const insn32 insn)
8440{
8441 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8442 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8443 return (insn & 0xffd02000) == 0xe9100000;
8444}
8445
8446static inline bfd_boolean
8447is_thumb2_vldm (const insn32 insn)
8448{
8449 /* A6.5 Extension register load or store instruction
8450 A7.7.229
9239bbd3
CM		 8451 We look for SP 32-bit and DP 64-bit registers.
8452 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8453 <list> is consecutive 64-bit registers
8454 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8455 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8456 <list> is consecutive 32-bit registers
8457 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8458 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8459 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8460 return
9239bbd3
CM		 8461 (((insn & 0xfe100f00) == 0xec100b00) ||
8462 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8463 && /* (IA without !). */
8464 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8465 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8466 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8467 /* (DB with !). */
8468 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8469}
8470
8471/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8472 VLDM opcode and:
8473 - computes the number and the mode of memory accesses
8474 - decides if the replacement should be done:
8475 . replaces only if > 8-word accesses
8476 . or (testing purposes only) replaces all accesses. */
8477
8478static bfd_boolean
8479stm32l4xx_need_create_replacing_stub (const insn32 insn,
8480 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8481{
9239bbd3 8482 int nb_words = 0;
a504d23a
LA		 8483
8484 /* The field encoding the register list is the same for both LDMIA
8485 and LDMDB encodings. */
8486 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8487 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8488 else if (is_thumb2_vldm (insn))
9239bbd3 8489 nb_words = (insn & 0xff);
a504d23a
LA		 8490
8491 /* DEFAULT mode accounts for the real bug condition situation,
8492 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8493 return
9239bbd3 8494 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8495 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8496}
8497
8498/* Look for potentially-troublesome code sequences which might trigger
8499 the STM STM32L4XX erratum. */
8500
8501bfd_boolean
8502bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8503 struct bfd_link_info *link_info)
8504{
8505 asection *sec;
8506 bfd_byte *contents = NULL;
8507 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8508
8509 if (globals == NULL)
8510 return FALSE;
8511
8512 /* If we are only performing a partial link do not bother
8513 to construct any glue. */
8514 if (bfd_link_relocatable (link_info))
8515 return TRUE;
8516
8517 /* Skip if this bfd does not correspond to an ELF image. */
8518 if (! is_arm_elf (abfd))
8519 return TRUE;
8520
8521 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8522 return TRUE;
8523
8524 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8525 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8526 return TRUE;
8527
8528 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8529 {
8530 unsigned int i, span;
8531 struct _arm_elf_section_data *sec_data;
8532
8533 /* If we don't have executable progbits, we're not interested in this
8534 section. Also skip if section is to be excluded. */
8535 if (elf_section_type (sec) != SHT_PROGBITS
8536 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8537 || (sec->flags & SEC_EXCLUDE) != 0
8538 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8539 || sec->output_section == bfd_abs_section_ptr
8540 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8541 continue;
8542
8543 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8544
a504d23a
LA		 8545 if (sec_data->mapcount == 0)
8546 continue;
c7b8f16e 8547
a504d23a
LA		 8548 if (elf_section_data (sec)->this_hdr.contents != NULL)
8549 contents = elf_section_data (sec)->this_hdr.contents;
8550 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8551 goto error_return;
c7b8f16e 8552
a504d23a
LA		 8553 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8554 elf32_arm_compare_mapping);
c7b8f16e 8555
a504d23a
LA		 8556 for (span = 0; span < sec_data->mapcount; span++)
8557 {
8558 unsigned int span_start = sec_data->map[span].vma;
8559 unsigned int span_end = (span == sec_data->mapcount - 1)
8560 ? sec->size : sec_data->map[span + 1].vma;
8561 char span_type = sec_data->map[span].type;
8562 int itblock_current_pos = 0;
c7b8f16e 8563
a504d23a
LA		 8564 /* Only Thumb2 mode need be supported with this CM4 specific
8565 code, we should not encounter any arm mode eg span_type
8566 != 'a'. */
8567 if (span_type != 't')
8568 continue;
c7b8f16e 8569
a504d23a
LA		 8570 for (i = span_start; i < span_end;)
8571 {
8572 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8573 bfd_boolean insn_32bit = FALSE;
8574 bfd_boolean is_ldm = FALSE;
8575 bfd_boolean is_vldm = FALSE;
8576 bfd_boolean is_not_last_in_it_block = FALSE;
8577
8578 /* The first 16-bits of all 32-bit thumb2 instructions start
8579 with opcode[15..13]=0b111 and the encoded op1 can be anything
8580 except opcode[12..11]!=0b00.
8581 See 32-bit Thumb instruction encoding. */
8582 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8583 insn_32bit = TRUE;
c7b8f16e 8584
a504d23a
LA		 8585 /* Compute the predicate that tells if the instruction
8586 is concerned by the IT block
8587 - Creates an error if there is a ldm that is not
8588 last in the IT block thus cannot be replaced
8589 - Otherwise we can create a branch at the end of the
8590 IT block, it will be controlled naturally by IT
8591 with the proper pseudo-predicate
8592 - So the only interesting predicate is the one that
8593 tells that we are not on the last item of an IT
8594 block. */
8595 if (itblock_current_pos != 0)
8596 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8597
a504d23a
LA		 8598 if (insn_32bit)
8599 {
8600 /* Load the rest of the insn (in manual-friendly order). */
8601 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8602 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8603 is_vldm = is_thumb2_vldm (insn);
8604
8605 /* Veneers are created for (v)ldm depending on
8606 option flags and memory accesses conditions; but
8607 if the instruction is not the last instruction of
8608 an IT block, we cannot create a jump there, so we
8609 bail out. */
5025eb7c
AO		 8610 if ((is_ldm || is_vldm)
8611 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8612 (insn, globals->stm32l4xx_fix))
8613 {
8614 if (is_not_last_in_it_block)
8615 {
4eca0228 8616 _bfd_error_handler
695344c0 8617 /* xgettext:c-format */
d42c267e 8618 (_("%B(%A+%#x): error: multiple load detected"
63a5468a
AM		 8619 " in non-last IT block instruction :"
8620 " STM32L4XX veneer cannot be generated.\n"
8621 "Use gcc option -mrestrict-it to generate"
8622 " only one instruction per IT block.\n"),
d42c267e 8623 abfd, sec, i);
a504d23a
LA		 8624 }
8625 else
8626 {
8627 elf32_stm32l4xx_erratum_list *newerr =
8628 (elf32_stm32l4xx_erratum_list *)
8629 bfd_zmalloc
8630 (sizeof (elf32_stm32l4xx_erratum_list));
8631
8632 elf32_arm_section_data (sec)
8633 ->stm32l4xx_erratumcount += 1;
8634 newerr->u.b.insn = insn;
8635 /* We create only thumb branches. */
8636 newerr->type =
8637 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8638 record_stm32l4xx_erratum_veneer
8639 (link_info, newerr, abfd, sec,
8640 i,
8641 is_ldm ?
8642 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8643 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8644 newerr->vma = -1;
8645 newerr->next = sec_data->stm32l4xx_erratumlist;
8646 sec_data->stm32l4xx_erratumlist = newerr;
8647 }
8648 }
8649 }
8650 else
8651 {
8652 /* A7.7.37 IT p208
8653 IT blocks are only encoded in T1
8654 Encoding T1: IT{x{y{z}}} <firstcond>
8655 1 0 1 1 - 1 1 1 1 - firstcond - mask
8656 if mask = '0000' then see 'related encodings'
8657 We don't deal with UNPREDICTABLE, just ignore these.
8658 There can be no nested IT blocks so an IT block
8659 is naturally a new one for which it is worth
8660 computing its size. */
5025eb7c
AO		 8661 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8662 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8663 /* If we have a new IT block we compute its size. */
8664 if (is_newitblock)
8665 {
8666 /* Compute the number of instructions controlled
8667 by the IT block, it will be used to decide
8668 whether we are inside an IT block or not. */
8669 unsigned int mask = insn & 0x000f;
8670 itblock_current_pos = 4 - ctz (mask);
8671 }
8672 }
8673
8674 i += insn_32bit ? 4 : 2;
99059e56
RM		 8675 }
8676 }
a504d23a
LA		 8677
8678 if (contents != NULL
8679 && elf_section_data (sec)->this_hdr.contents != contents)
8680 free (contents);
8681 contents = NULL;
c7b8f16e 8682 }
906e58ca 8683
a504d23a
LA		 8684 return TRUE;
8685
8686error_return:
8687 if (contents != NULL
8688 && elf_section_data (sec)->this_hdr.contents != contents)
8689 free (contents);
c7b8f16e 8690
a504d23a
LA		 8691 return FALSE;
8692}
c7b8f16e 8693
eb043451
PB		 8694/* Set target relocation values needed during linking. */
8695
8696void
68c39892 8697bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8698 struct bfd_link_info *link_info,
68c39892 8699 struct elf32_arm_params *params)
eb043451
PB		 8700{
8701 struct elf32_arm_link_hash_table *globals;
8702
8703 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8704 if (globals == NULL)
8705 return;
eb043451 8706
68c39892
TP		 8707 globals->target1_is_rel = params->target1_is_rel;
8708 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8709 globals->target2_reloc = R_ARM_REL32;
68c39892 8710 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8711 globals->target2_reloc = R_ARM_ABS32;
68c39892 8712 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8713 globals->target2_reloc = R_ARM_GOT_PREL;
8714 else
8715 {
8716 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8717 params->target2_type);
eb043451 8718 }
68c39892
TP		 8719 globals->fix_v4bx = params->fix_v4bx;
8720 globals->use_blx |= params->use_blx;
8721 globals->vfp11_fix = params->vfp11_denorm_fix;
8722 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8723 globals->pic_veneer = params->pic_veneer;
8724 globals->fix_cortex_a8 = params->fix_cortex_a8;
8725 globals->fix_arm1176 = params->fix_arm1176;
8726 globals->cmse_implib = params->cmse_implib;
8727 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8728
0ffa91dd 8729 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8730 elf_arm_tdata (output_bfd)->no_enum_size_warning
8731 = params->no_enum_size_warning;
8732 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8733 = params->no_wchar_size_warning;
eb043451 8734}
eb043451 8735
12a0a0fd 8736/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8737
12a0a0fd
PB		 8738static void
8739insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8740{
8741 bfd_vma upper;
8742 bfd_vma lower;
8743 int reloc_sign;
8744
8745 BFD_ASSERT ((offset & 1) == 0);
8746
8747 upper = bfd_get_16 (abfd, insn);
8748 lower = bfd_get_16 (abfd, insn + 2);
8749 reloc_sign = (offset < 0) ? 1 : 0;
8750 upper = (upper & ~(bfd_vma) 0x7ff)
8751 | ((offset >> 12) & 0x3ff)
8752 | (reloc_sign << 10);
906e58ca 8753 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8754 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8755 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8756 | ((offset >> 1) & 0x7ff);
8757 bfd_put_16 (abfd, upper, insn);
8758 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8759}
8760
9b485d32
NC		 8761/* Thumb code calling an ARM function. */
8762
252b5132 8763static int
57e8b36a
NC		 8764elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8765 const char * name,
8766 bfd * input_bfd,
8767 bfd * output_bfd,
8768 asection * input_section,
8769 bfd_byte * hit_data,
8770 asection * sym_sec,
8771 bfd_vma offset,
8772 bfd_signed_vma addend,
f2a9dd69
DJ		 8773 bfd_vma val,
8774 char **error_message)
252b5132 8775{
bcbdc74c 8776 asection * s = 0;
dc810e39 8777 bfd_vma my_offset;
252b5132 8778 long int ret_offset;
bcbdc74c
NC		 8779 struct elf_link_hash_entry * myh;
8780 struct elf32_arm_link_hash_table * globals;
252b5132 8781
f2a9dd69 8782 myh = find_thumb_glue (info, name, error_message);
252b5132 8783 if (myh == NULL)
b34976b6 8784 return FALSE;
252b5132
RH		 8785
8786 globals = elf32_arm_hash_table (info);
252b5132
RH		 8787 BFD_ASSERT (globals != NULL);
8788 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8789
8790 my_offset = myh->root.u.def.value;
8791
3d4d4302
AM		 8792 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8793 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8794
8795 BFD_ASSERT (s != NULL);
8796 BFD_ASSERT (s->contents != NULL);
8797 BFD_ASSERT (s->output_section != NULL);
8798
8799 if ((my_offset & 0x01) == 0x01)
8800 {
8801 if (sym_sec != NULL
8802 && sym_sec->owner != NULL
8803 && !INTERWORK_FLAG (sym_sec->owner))
8804 {
4eca0228 8805 _bfd_error_handler
d003868e 8806 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8807 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 8808 sym_sec->owner, name, input_bfd);
252b5132 8809
b34976b6 8810 return FALSE;
252b5132
RH		 8811 }
8812
8813 --my_offset;
8814 myh->root.u.def.value = my_offset;
8815
52ab56c2
PB		 8816 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8817 s->contents + my_offset);
252b5132 8818
52ab56c2
PB		 8819 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8820 s->contents + my_offset + 2);
252b5132
RH		 8821
8822 ret_offset =
9b485d32
NC		 8823 /* Address of destination of the stub. */
8824 ((bfd_signed_vma) val)
252b5132 8825 - ((bfd_signed_vma)
57e8b36a
NC		 8826 /* Offset from the start of the current section
8827 to the start of the stubs. */
9b485d32
NC		 8828 (s->output_offset
8829 /* Offset of the start of this stub from the start of the stubs. */
8830 + my_offset
8831 /* Address of the start of the current section. */
8832 + s->output_section->vma)
8833 /* The branch instruction is 4 bytes into the stub. */
8834 + 4
8835 /* ARM branches work from the pc of the instruction + 8. */
8836 + 8);
252b5132 8837
52ab56c2
PB		 8838 put_arm_insn (globals, output_bfd,
8839 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8840 s->contents + my_offset + 4);
252b5132
RH		 8841 }
8842
8843 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8844
427bfd90
NC		 8845 /* Now go back and fix up the original BL insn to point to here. */
8846 ret_offset =
8847 /* Address of where the stub is located. */
8848 (s->output_section->vma + s->output_offset + my_offset)
8849 /* Address of where the BL is located. */
57e8b36a
NC		 8850 - (input_section->output_section->vma + input_section->output_offset
8851 + offset)
427bfd90
NC		 8852 /* Addend in the relocation. */
8853 - addend
8854 /* Biassing for PC-relative addressing. */
8855 - 8;
252b5132 8856
12a0a0fd 8857 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8858
b34976b6 8859 return TRUE;
252b5132
RH		 8860}
8861
a4fd1a8e 8862/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8863
a4fd1a8e
PB		 8864static struct elf_link_hash_entry *
8865elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8866 const char * name,
8867 bfd * input_bfd,
8868 bfd * output_bfd,
8869 asection * sym_sec,
8870 bfd_vma val,
8029a119
NC		 8871 asection * s,
8872 char ** error_message)
252b5132 8873{
dc810e39 8874 bfd_vma my_offset;
252b5132 8875 long int ret_offset;
bcbdc74c
NC		 8876 struct elf_link_hash_entry * myh;
8877 struct elf32_arm_link_hash_table * globals;
252b5132 8878
f2a9dd69 8879 myh = find_arm_glue (info, name, error_message);
252b5132 8880 if (myh == NULL)
a4fd1a8e 8881 return NULL;
252b5132
RH		 8882
8883 globals = elf32_arm_hash_table (info);
252b5132
RH		 8884 BFD_ASSERT (globals != NULL);
8885 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8886
8887 my_offset = myh->root.u.def.value;
252b5132
RH		 8888
8889 if ((my_offset & 0x01) == 0x01)
8890 {
8891 if (sym_sec != NULL
8892 && sym_sec->owner != NULL
8893 && !INTERWORK_FLAG (sym_sec->owner))
8894 {
4eca0228 8895 _bfd_error_handler
d003868e
AM		 8896 (_("%B(%s): warning: interworking not enabled.\n"
8897 " first occurrence: %B: arm call to thumb"),
c08bb8dd 8898 sym_sec->owner, name, input_bfd);
252b5132 8899 }
9b485d32 8900
252b5132
RH		 8901 --my_offset;
8902 myh->root.u.def.value = my_offset;
8903
0e1862bb
L		 8904 if (bfd_link_pic (info)
8905 || globals->root.is_relocatable_executable
27e55c4d 8906 || globals->pic_veneer)
8f6277f5
PB		 8907 {
8908 /* For relocatable objects we can't use absolute addresses,
8909 so construct the address from a relative offset. */
8910 /* TODO: If the offset is small it's probably worth
8911 constructing the address with adds. */
52ab56c2
PB		 8912 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8913 s->contents + my_offset);
8914 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8915 s->contents + my_offset + 4);
8916 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8917 s->contents + my_offset + 8);
8f6277f5
PB		 8918 /* Adjust the offset by 4 for the position of the add,
8919 and 8 for the pipeline offset. */
8920 ret_offset = (val - (s->output_offset
8921 + s->output_section->vma
8922 + my_offset + 12))
8923 | 1;
8924 bfd_put_32 (output_bfd, ret_offset,
8925 s->contents + my_offset + 12);
8926 }
26079076
PB		 8927 else if (globals->use_blx)
8928 {
8929 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8930 s->contents + my_offset);
8931
8932 /* It's a thumb address. Add the low order bit. */
8933 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8934 s->contents + my_offset + 4);
8935 }
8f6277f5
PB		 8936 else
8937 {
52ab56c2
PB		 8938 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8939 s->contents + my_offset);
252b5132 8940
52ab56c2
PB		 8941 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8942 s->contents + my_offset + 4);
252b5132 8943
8f6277f5
PB		 8944 /* It's a thumb address. Add the low order bit. */
8945 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8946 s->contents + my_offset + 8);
8029a119
NC		 8947
8948 my_offset += 12;
8f6277f5 8949 }
252b5132
RH		 8950 }
8951
8952 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8953
a4fd1a8e
PB		 8954 return myh;
8955}
8956
8957/* Arm code calling a Thumb function. */
8958
8959static int
8960elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8961 const char * name,
8962 bfd * input_bfd,
8963 bfd * output_bfd,
8964 asection * input_section,
8965 bfd_byte * hit_data,
8966 asection * sym_sec,
8967 bfd_vma offset,
8968 bfd_signed_vma addend,
f2a9dd69
DJ		 8969 bfd_vma val,
8970 char **error_message)
a4fd1a8e
PB		 8971{
8972 unsigned long int tmp;
8973 bfd_vma my_offset;
8974 asection * s;
8975 long int ret_offset;
8976 struct elf_link_hash_entry * myh;
8977 struct elf32_arm_link_hash_table * globals;
8978
8979 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8980 BFD_ASSERT (globals != NULL);
8981 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8982
3d4d4302
AM		 8983 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8984 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8985 BFD_ASSERT (s != NULL);
8986 BFD_ASSERT (s->contents != NULL);
8987 BFD_ASSERT (s->output_section != NULL);
8988
8989 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8990 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8991 if (!myh)
8992 return FALSE;
8993
8994 my_offset = myh->root.u.def.value;
252b5132
RH		 8995 tmp = bfd_get_32 (input_bfd, hit_data);
8996 tmp = tmp & 0xFF000000;
8997
9b485d32 8998 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8999 ret_offset = (s->output_offset
9000 + my_offset
9001 + s->output_section->vma
9002 - (input_section->output_offset
9003 + input_section->output_section->vma
9004 + offset + addend)
9005 - 8);
9a5aca8c 9006
252b5132
RH		 9007 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9008
dc810e39 9009 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9010
b34976b6 9011 return TRUE;
252b5132
RH		 9012}
9013
a4fd1a8e
PB		 9014/* Populate Arm stub for an exported Thumb function. */
9015
9016static bfd_boolean
9017elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9018{
9019 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9020 asection * s;
9021 struct elf_link_hash_entry * myh;
9022 struct elf32_arm_link_hash_entry *eh;
9023 struct elf32_arm_link_hash_table * globals;
9024 asection *sec;
9025 bfd_vma val;
f2a9dd69 9026 char *error_message;
a4fd1a8e 9027
906e58ca 9028 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9029 /* Allocate stubs for exported Thumb functions on v4t. */
9030 if (eh->export_glue == NULL)
9031 return TRUE;
9032
9033 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9034 BFD_ASSERT (globals != NULL);
9035 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9036
3d4d4302
AM		 9037 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9038 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9039 BFD_ASSERT (s != NULL);
9040 BFD_ASSERT (s->contents != NULL);
9041 BFD_ASSERT (s->output_section != NULL);
9042
9043 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9044
9045 BFD_ASSERT (sec->output_section != NULL);
9046
a4fd1a8e
PB		 9047 val = eh->export_glue->root.u.def.value + sec->output_offset
9048 + sec->output_section->vma;
8029a119 9049
a4fd1a8e
PB		 9050 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9051 h->root.u.def.section->owner,
f2a9dd69
DJ		 9052 globals->obfd, sec, val, s,
9053 &error_message);
a4fd1a8e
PB		 9054 BFD_ASSERT (myh);
9055 return TRUE;
9056}
9057
845b51d6
PB		 9058/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9059
9060static bfd_vma
9061elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9062{
9063 bfd_byte *p;
9064 bfd_vma glue_addr;
9065 asection *s;
9066 struct elf32_arm_link_hash_table *globals;
9067
9068 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9069 BFD_ASSERT (globals != NULL);
9070 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9071
3d4d4302
AM		 9072 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9073 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9074 BFD_ASSERT (s != NULL);
9075 BFD_ASSERT (s->contents != NULL);
9076 BFD_ASSERT (s->output_section != NULL);
9077
9078 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9079
9080 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9081
9082 if ((globals->bx_glue_offset[reg] & 1) == 0)
9083 {
9084 p = s->contents + glue_addr;
9085 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9086 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9087 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9088 globals->bx_glue_offset[reg] |= 1;
9089 }
9090
9091 return glue_addr + s->output_section->vma + s->output_offset;
9092}
9093
a4fd1a8e
PB		 9094/* Generate Arm stubs for exported Thumb symbols. */
9095static void
906e58ca 9096elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9097 struct bfd_link_info *link_info)
9098{
9099 struct elf32_arm_link_hash_table * globals;
9100
8029a119
NC		 9101 if (link_info == NULL)
9102 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9103 return;
9104
9105 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9106 if (globals == NULL)
9107 return;
9108
84c08195
PB		 9109 /* If blx is available then exported Thumb symbols are OK and there is
9110 nothing to do. */
a4fd1a8e
PB		 9111 if (globals->use_blx)
9112 return;
9113
9114 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9115 link_info);
9116}
9117
47beaa6a
RS		 9118/* Reserve space for COUNT dynamic relocations in relocation selection
9119 SRELOC. */
9120
9121static void
9122elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9123 bfd_size_type count)
9124{
9125 struct elf32_arm_link_hash_table *htab;
9126
9127 htab = elf32_arm_hash_table (info);
9128 BFD_ASSERT (htab->root.dynamic_sections_created);
9129 if (sreloc == NULL)
9130 abort ();
9131 sreloc->size += RELOC_SIZE (htab) * count;
9132}
9133
34e77a92
RS		 9134/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9135 dynamic, the relocations should go in SRELOC, otherwise they should
9136 go in the special .rel.iplt section. */
9137
9138static void
9139elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9140 bfd_size_type count)
9141{
9142 struct elf32_arm_link_hash_table *htab;
9143
9144 htab = elf32_arm_hash_table (info);
9145 if (!htab->root.dynamic_sections_created)
9146 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9147 else
9148 {
9149 BFD_ASSERT (sreloc != NULL);
9150 sreloc->size += RELOC_SIZE (htab) * count;
9151 }
9152}
9153
47beaa6a
RS		 9154/* Add relocation REL to the end of relocation section SRELOC. */
9155
9156static void
9157elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9158 asection *sreloc, Elf_Internal_Rela *rel)
9159{
9160 bfd_byte *loc;
9161 struct elf32_arm_link_hash_table *htab;
9162
9163 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9164 if (!htab->root.dynamic_sections_created
9165 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9166 sreloc = htab->root.irelplt;
47beaa6a
RS		 9167 if (sreloc == NULL)
9168 abort ();
9169 loc = sreloc->contents;
9170 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9171 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9172 abort ();
9173 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9174}
9175
34e77a92
RS		 9176/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9177 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9178 to .plt. */
9179
9180static void
9181elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9182 bfd_boolean is_iplt_entry,
9183 union gotplt_union *root_plt,
9184 struct arm_plt_info *arm_plt)
9185{
9186 struct elf32_arm_link_hash_table *htab;
9187 asection *splt;
9188 asection *sgotplt;
9189
9190 htab = elf32_arm_hash_table (info);
9191
9192 if (is_iplt_entry)
9193 {
9194 splt = htab->root.iplt;
9195 sgotplt = htab->root.igotplt;
9196
99059e56
RM		 9197 /* NaCl uses a special first entry in .iplt too. */
9198 if (htab->nacl_p && splt->size == 0)
9199 splt->size += htab->plt_header_size;
9200
34e77a92
RS		 9201 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9202 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9203 }
9204 else
9205 {
9206 splt = htab->root.splt;
9207 sgotplt = htab->root.sgotplt;
9208
9209 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9210 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9211
9212 /* If this is the first .plt entry, make room for the special
9213 first entry. */
9214 if (splt->size == 0)
9215 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9216
9217 htab->next_tls_desc_index++;
34e77a92
RS		 9218 }
9219
9220 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9221 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9222 splt->size += PLT_THUMB_STUB_SIZE;
9223 root_plt->offset = splt->size;
9224 splt->size += htab->plt_entry_size;
9225
9226 if (!htab->symbian_p)
9227 {
9228 /* We also need to make an entry in the .got.plt section, which
9229 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9230 if (is_iplt_entry)
9231 arm_plt->got_offset = sgotplt->size;
9232 else
9233 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9234 sgotplt->size += 4;
9235 }
9236}
9237
b38cadfb
NC		 9238static bfd_vma
9239arm_movw_immediate (bfd_vma value)
9240{
9241 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9242}
9243
9244static bfd_vma
9245arm_movt_immediate (bfd_vma value)
9246{
9247 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9248}
9249
34e77a92
RS		 9250/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9251 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9252 Otherwise, DYNINDX is the index of the symbol in the dynamic
9253 symbol table and SYM_VALUE is undefined.
9254
9255 ROOT_PLT points to the offset of the PLT entry from the start of its
9256 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9257 bookkeeping information.
34e77a92 9258
57460bcf
NC		 9259 Returns FALSE if there was a problem. */
9260
9261static bfd_boolean
34e77a92
RS		 9262elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9263 union gotplt_union *root_plt,
9264 struct arm_plt_info *arm_plt,
9265 int dynindx, bfd_vma sym_value)
9266{
9267 struct elf32_arm_link_hash_table *htab;
9268 asection *sgot;
9269 asection *splt;
9270 asection *srel;
9271 bfd_byte *loc;
9272 bfd_vma plt_index;
9273 Elf_Internal_Rela rel;
9274 bfd_vma plt_header_size;
9275 bfd_vma got_header_size;
9276
9277 htab = elf32_arm_hash_table (info);
9278
9279 /* Pick the appropriate sections and sizes. */
9280 if (dynindx == -1)
9281 {
9282 splt = htab->root.iplt;
9283 sgot = htab->root.igotplt;
9284 srel = htab->root.irelplt;
9285
9286 /* There are no reserved entries in .igot.plt, and no special
9287 first entry in .iplt. */
9288 got_header_size = 0;
9289 plt_header_size = 0;
9290 }
9291 else
9292 {
9293 splt = htab->root.splt;
9294 sgot = htab->root.sgotplt;
9295 srel = htab->root.srelplt;
9296
9297 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9298 plt_header_size = htab->plt_header_size;
9299 }
9300 BFD_ASSERT (splt != NULL && srel != NULL);
9301
9302 /* Fill in the entry in the procedure linkage table. */
9303 if (htab->symbian_p)
9304 {
9305 BFD_ASSERT (dynindx >= 0);
9306 put_arm_insn (htab, output_bfd,
9307 elf32_arm_symbian_plt_entry[0],
9308 splt->contents + root_plt->offset);
9309 bfd_put_32 (output_bfd,
9310 elf32_arm_symbian_plt_entry[1],
9311 splt->contents + root_plt->offset + 4);
9312
9313 /* Fill in the entry in the .rel.plt section. */
9314 rel.r_offset = (splt->output_section->vma
9315 + splt->output_offset
9316 + root_plt->offset + 4);
9317 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9318
9319 /* Get the index in the procedure linkage table which
9320 corresponds to this symbol. This is the index of this symbol
9321 in all the symbols for which we are making plt entries. The
9322 first entry in the procedure linkage table is reserved. */
9323 plt_index = ((root_plt->offset - plt_header_size)
9324 / htab->plt_entry_size);
9325 }
9326 else
9327 {
9328 bfd_vma got_offset, got_address, plt_address;
9329 bfd_vma got_displacement, initial_got_entry;
9330 bfd_byte * ptr;
9331
9332 BFD_ASSERT (sgot != NULL);
9333
9334 /* Get the offset into the .(i)got.plt table of the entry that
9335 corresponds to this function. */
9336 got_offset = (arm_plt->got_offset & -2);
9337
9338 /* Get the index in the procedure linkage table which
9339 corresponds to this symbol. This is the index of this symbol
9340 in all the symbols for which we are making plt entries.
9341 After the reserved .got.plt entries, all symbols appear in
9342 the same order as in .plt. */
9343 plt_index = (got_offset - got_header_size) / 4;
9344
9345 /* Calculate the address of the GOT entry. */
9346 got_address = (sgot->output_section->vma
9347 + sgot->output_offset
9348 + got_offset);
9349
9350 /* ...and the address of the PLT entry. */
9351 plt_address = (splt->output_section->vma
9352 + splt->output_offset
9353 + root_plt->offset);
9354
9355 ptr = splt->contents + root_plt->offset;
0e1862bb 9356 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9357 {
9358 unsigned int i;
9359 bfd_vma val;
9360
9361 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9362 {
9363 val = elf32_arm_vxworks_shared_plt_entry[i];
9364 if (i == 2)
9365 val |= got_address - sgot->output_section->vma;
9366 if (i == 5)
9367 val |= plt_index * RELOC_SIZE (htab);
9368 if (i == 2 || i == 5)
9369 bfd_put_32 (output_bfd, val, ptr);
9370 else
9371 put_arm_insn (htab, output_bfd, val, ptr);
9372 }
9373 }
9374 else if (htab->vxworks_p)
9375 {
9376 unsigned int i;
9377 bfd_vma val;
9378
9379 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9380 {
9381 val = elf32_arm_vxworks_exec_plt_entry[i];
9382 if (i == 2)
9383 val |= got_address;
9384 if (i == 4)
9385 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9386 if (i == 5)
9387 val |= plt_index * RELOC_SIZE (htab);
9388 if (i == 2 || i == 5)
9389 bfd_put_32 (output_bfd, val, ptr);
9390 else
9391 put_arm_insn (htab, output_bfd, val, ptr);
9392 }
9393
9394 loc = (htab->srelplt2->contents
9395 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9396
9397 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9398 referencing the GOT for this PLT entry. */
9399 rel.r_offset = plt_address + 8;
9400 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9401 rel.r_addend = got_offset;
9402 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9403 loc += RELOC_SIZE (htab);
9404
9405 /* Create the R_ARM_ABS32 relocation referencing the
9406 beginning of the PLT for this GOT entry. */
9407 rel.r_offset = got_address;
9408 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9409 rel.r_addend = 0;
9410 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9411 }
b38cadfb
NC		 9412 else if (htab->nacl_p)
9413 {
9414 /* Calculate the displacement between the PLT slot and the
9415 common tail that's part of the special initial PLT slot. */
6034aab8 9416 int32_t tail_displacement
b38cadfb
NC		 9417 = ((splt->output_section->vma + splt->output_offset
9418 + ARM_NACL_PLT_TAIL_OFFSET)
9419 - (plt_address + htab->plt_entry_size + 4));
9420 BFD_ASSERT ((tail_displacement & 3) == 0);
9421 tail_displacement >>= 2;
9422
9423 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9424 || (-tail_displacement & 0xff000000) == 0);
9425
9426 /* Calculate the displacement between the PLT slot and the entry
9427 in the GOT. The offset accounts for the value produced by
9428 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9429 got_displacement = (got_address
99059e56 9430 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9431
9432 /* NaCl does not support interworking at all. */
9433 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9434
9435 put_arm_insn (htab, output_bfd,
9436 elf32_arm_nacl_plt_entry[0]
9437 | arm_movw_immediate (got_displacement),
9438 ptr + 0);
9439 put_arm_insn (htab, output_bfd,
9440 elf32_arm_nacl_plt_entry[1]
9441 | arm_movt_immediate (got_displacement),
9442 ptr + 4);
9443 put_arm_insn (htab, output_bfd,
9444 elf32_arm_nacl_plt_entry[2],
9445 ptr + 8);
9446 put_arm_insn (htab, output_bfd,
9447 elf32_arm_nacl_plt_entry[3]
9448 | (tail_displacement & 0x00ffffff),
9449 ptr + 12);
9450 }
57460bcf
NC		 9451 else if (using_thumb_only (htab))
9452 {
eed94f8f 9453 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9454 if (!using_thumb2 (htab))
eed94f8f
NC		 9455 {
9456 /* FIXME: We ought to be able to generate thumb-1 PLT
9457 instructions... */
9458 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9459 output_bfd);
9460 return FALSE;
9461 }
57460bcf 9462
eed94f8f
NC		 9463 /* Calculate the displacement between the PLT slot and the entry in
9464 the GOT. The 12-byte offset accounts for the value produced by
9465 adding to pc in the 3rd instruction of the PLT stub. */
9466 got_displacement = got_address - (plt_address + 12);
9467
9468 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9469 instead of 'put_thumb_insn'. */
9470 put_arm_insn (htab, output_bfd,
9471 elf32_thumb2_plt_entry[0]
9472 | ((got_displacement & 0x000000ff) << 16)
9473 | ((got_displacement & 0x00000700) << 20)
9474 | ((got_displacement & 0x00000800) >> 1)
9475 | ((got_displacement & 0x0000f000) >> 12),
9476 ptr + 0);
9477 put_arm_insn (htab, output_bfd,
9478 elf32_thumb2_plt_entry[1]
9479 | ((got_displacement & 0x00ff0000) )
9480 | ((got_displacement & 0x07000000) << 4)
9481 | ((got_displacement & 0x08000000) >> 17)
9482 | ((got_displacement & 0xf0000000) >> 28),
9483 ptr + 4);
9484 put_arm_insn (htab, output_bfd,
9485 elf32_thumb2_plt_entry[2],
9486 ptr + 8);
9487 put_arm_insn (htab, output_bfd,
9488 elf32_thumb2_plt_entry[3],
9489 ptr + 12);
57460bcf 9490 }
34e77a92
RS		 9491 else
9492 {
9493 /* Calculate the displacement between the PLT slot and the
9494 entry in the GOT. The eight-byte offset accounts for the
9495 value produced by adding to pc in the first instruction
9496 of the PLT stub. */
9497 got_displacement = got_address - (plt_address + 8);
9498
34e77a92
RS		 9499 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9500 {
9501 put_thumb_insn (htab, output_bfd,
9502 elf32_arm_plt_thumb_stub[0], ptr - 4);
9503 put_thumb_insn (htab, output_bfd,
9504 elf32_arm_plt_thumb_stub[1], ptr - 2);
9505 }
9506
1db37fe6
YG		 9507 if (!elf32_arm_use_long_plt_entry)
9508 {
9509 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9510
9511 put_arm_insn (htab, output_bfd,
9512 elf32_arm_plt_entry_short[0]
9513 | ((got_displacement & 0x0ff00000) >> 20),
9514 ptr + 0);
9515 put_arm_insn (htab, output_bfd,
9516 elf32_arm_plt_entry_short[1]
9517 | ((got_displacement & 0x000ff000) >> 12),
9518 ptr+ 4);
9519 put_arm_insn (htab, output_bfd,
9520 elf32_arm_plt_entry_short[2]
9521 | (got_displacement & 0x00000fff),
9522 ptr + 8);
34e77a92 9523#ifdef FOUR_WORD_PLT
1db37fe6 9524 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9525#endif
1db37fe6
YG		 9526 }
9527 else
9528 {
9529 put_arm_insn (htab, output_bfd,
9530 elf32_arm_plt_entry_long[0]
9531 | ((got_displacement & 0xf0000000) >> 28),
9532 ptr + 0);
9533 put_arm_insn (htab, output_bfd,
9534 elf32_arm_plt_entry_long[1]
9535 | ((got_displacement & 0x0ff00000) >> 20),
9536 ptr + 4);
9537 put_arm_insn (htab, output_bfd,
9538 elf32_arm_plt_entry_long[2]
9539 | ((got_displacement & 0x000ff000) >> 12),
9540 ptr+ 8);
9541 put_arm_insn (htab, output_bfd,
9542 elf32_arm_plt_entry_long[3]
9543 | (got_displacement & 0x00000fff),
9544 ptr + 12);
9545 }
34e77a92
RS		 9546 }
9547
9548 /* Fill in the entry in the .rel(a).(i)plt section. */
9549 rel.r_offset = got_address;
9550 rel.r_addend = 0;
9551 if (dynindx == -1)
9552 {
9553 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9554 The dynamic linker or static executable then calls SYM_VALUE
9555 to determine the correct run-time value of the .igot.plt entry. */
9556 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9557 initial_got_entry = sym_value;
9558 }
9559 else
9560 {
9561 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9562 initial_got_entry = (splt->output_section->vma
9563 + splt->output_offset);
9564 }
9565
9566 /* Fill in the entry in the global offset table. */
9567 bfd_put_32 (output_bfd, initial_got_entry,
9568 sgot->contents + got_offset);
9569 }
9570
aba8c3de
WN		 9571 if (dynindx == -1)
9572 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9573 else
9574 {
9575 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9576 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9577 }
57460bcf
NC		 9578
9579 return TRUE;
34e77a92
RS		 9580}
9581
eb043451
PB		 9582/* Some relocations map to different relocations depending on the
9583 target. Return the real relocation. */
8029a119 9584
eb043451
PB		 9585static int
9586arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9587 int r_type)
9588{
9589 switch (r_type)
9590 {
9591 case R_ARM_TARGET1:
9592 if (globals->target1_is_rel)
9593 return R_ARM_REL32;
9594 else
9595 return R_ARM_ABS32;
9596
9597 case R_ARM_TARGET2:
9598 return globals->target2_reloc;
9599
9600 default:
9601 return r_type;
9602 }
9603}
eb043451 9604
ba93b8ac
DJ		 9605/* Return the base VMA address which should be subtracted from real addresses
9606 when resolving @dtpoff relocation.
9607 This is PT_TLS segment p_vaddr. */
9608
9609static bfd_vma
9610dtpoff_base (struct bfd_link_info *info)
9611{
9612 /* If tls_sec is NULL, we should have signalled an error already. */
9613 if (elf_hash_table (info)->tls_sec == NULL)
9614 return 0;
9615 return elf_hash_table (info)->tls_sec->vma;
9616}
9617
9618/* Return the relocation value for @tpoff relocation
9619 if STT_TLS virtual address is ADDRESS. */
9620
9621static bfd_vma
9622tpoff (struct bfd_link_info *info, bfd_vma address)
9623{
9624 struct elf_link_hash_table *htab = elf_hash_table (info);
9625 bfd_vma base;
9626
9627 /* If tls_sec is NULL, we should have signalled an error already. */
9628 if (htab->tls_sec == NULL)
9629 return 0;
9630 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9631 return address - htab->tls_sec->vma + base;
9632}
9633
00a97672
RS		 9634/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9635 VALUE is the relocation value. */
9636
9637static bfd_reloc_status_type
9638elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9639{
9640 if (value > 0xfff)
9641 return bfd_reloc_overflow;
9642
9643 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9644 bfd_put_32 (abfd, value, data);
9645 return bfd_reloc_ok;
9646}
9647
0855e32b
NS		 9648/* Handle TLS relaxations. Relaxing is possible for symbols that use
9649 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9650 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9651
9652 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9653 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9654 case of error.
9655
9656 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9657 the pre-relaxed code. It would be nice if the relocs were updated
9658 to match the optimization. */
0855e32b 9659
b38cadfb 9660static bfd_reloc_status_type
0855e32b 9661elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9662 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9663 Elf_Internal_Rela *rel, unsigned long is_local)
9664{
9665 unsigned long insn;
b38cadfb 9666
0855e32b
NS		 9667 switch (ELF32_R_TYPE (rel->r_info))
9668 {
9669 default:
9670 return bfd_reloc_notsupported;
b38cadfb 9671
0855e32b
NS		 9672 case R_ARM_TLS_GOTDESC:
9673 if (is_local)
9674 insn = 0;
9675 else
9676 {
9677 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9678 if (insn & 1)
9679 insn -= 5; /* THUMB */
9680 else
9681 insn -= 8; /* ARM */
9682 }
9683 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9684 return bfd_reloc_continue;
9685
9686 case R_ARM_THM_TLS_DESCSEQ:
9687 /* Thumb insn. */
9688 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9689 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9690 {
9691 if (is_local)
9692 /* nop */
9693 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9694 }
9695 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9696 {
9697 if (is_local)
9698 /* nop */
9699 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9700 else
9701 /* ldr rx,[ry] */
9702 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9703 }
9704 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9705 {
9706 if (is_local)
9707 /* nop */
9708 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9709 else
9710 /* mov r0, rx */
9711 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9712 contents + rel->r_offset);
9713 }
9714 else
9715 {
9716 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9717 /* It's a 32 bit instruction, fetch the rest of it for
9718 error generation. */
9719 insn = (insn << 16)
9720 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9721 _bfd_error_handler
695344c0 9722 /* xgettext:c-format */
d42c267e
AM		 9723 (_("%B(%A+%#Lx): unexpected Thumb instruction '%#lx' in TLS trampoline"),
9724 input_bfd, input_sec, rel->r_offset, insn);
0855e32b
NS		 9725 return bfd_reloc_notsupported;
9726 }
9727 break;
b38cadfb 9728
0855e32b
NS		 9729 case R_ARM_TLS_DESCSEQ:
9730 /* arm insn. */
9731 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9732 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9733 {
9734 if (is_local)
9735 /* mov rx, ry */
9736 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9737 contents + rel->r_offset);
9738 }
9739 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9740 {
9741 if (is_local)
9742 /* nop */
9743 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9744 else
9745 /* ldr rx,[ry] */
9746 bfd_put_32 (input_bfd, insn & 0xfffff000,
9747 contents + rel->r_offset);
9748 }
9749 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9750 {
9751 if (is_local)
9752 /* nop */
9753 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9754 else
9755 /* mov r0, rx */
9756 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9757 contents + rel->r_offset);
9758 }
9759 else
9760 {
4eca0228 9761 _bfd_error_handler
695344c0 9762 /* xgettext:c-format */
d42c267e
AM		 9763 (_("%B(%A+%#Lx): unexpected ARM instruction '%#lx' in TLS trampoline"),
9764 input_bfd, input_sec, rel->r_offset, insn);
0855e32b
NS		 9765 return bfd_reloc_notsupported;
9766 }
9767 break;
9768
9769 case R_ARM_TLS_CALL:
9770 /* GD->IE relaxation, turn the instruction into 'nop' or
9771 'ldr r0, [pc,r0]' */
9772 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9773 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9774 break;
b38cadfb 9775
0855e32b 9776 case R_ARM_THM_TLS_CALL:
6a631e86 9777 /* GD->IE relaxation. */
0855e32b
NS		 9778 if (!is_local)
9779 /* add r0,pc; ldr r0, [r0] */
9780 insn = 0x44786800;
60a019a0 9781 else if (using_thumb2 (globals))
0855e32b
NS		 9782 /* nop.w */
9783 insn = 0xf3af8000;
9784 else
9785 /* nop; nop */
9786 insn = 0xbf00bf00;
b38cadfb 9787
0855e32b
NS		 9788 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9789 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9790 break;
9791 }
9792 return bfd_reloc_ok;
9793}
9794
4962c51a
MS		 9795/* For a given value of n, calculate the value of G_n as required to
9796 deal with group relocations. We return it in the form of an
9797 encoded constant-and-rotation, together with the final residual. If n is
9798 specified as less than zero, then final_residual is filled with the
9799 input value and no further action is performed. */
9800
9801static bfd_vma
9802calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9803{
9804 int current_n;
9805 bfd_vma g_n;
9806 bfd_vma encoded_g_n = 0;
9807 bfd_vma residual = value; /* Also known as Y_n. */
9808
9809 for (current_n = 0; current_n <= n; current_n++)
9810 {
9811 int shift;
9812
9813 /* Calculate which part of the value to mask. */
9814 if (residual == 0)
99059e56 9815 shift = 0;
4962c51a 9816 else
99059e56
RM		 9817 {
9818 int msb;
9819
9820 /* Determine the most significant bit in the residual and
9821 align the resulting value to a 2-bit boundary. */
9822 for (msb = 30; msb >= 0; msb -= 2)
9823 if (residual & (3 << msb))
9824 break;
9825
9826 /* The desired shift is now (msb - 6), or zero, whichever
9827 is the greater. */
9828 shift = msb - 6;
9829 if (shift < 0)
9830 shift = 0;
9831 }
4962c51a
MS		 9832
9833 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9834 g_n = residual & (0xff << shift);
9835 encoded_g_n = (g_n >> shift)
99059e56 9836 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9837
9838 /* Calculate the residual for the next time around. */
9839 residual &= ~g_n;
9840 }
9841
9842 *final_residual = residual;
9843
9844 return encoded_g_n;
9845}
9846
9847/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9848 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9849
4962c51a 9850static int
906e58ca 9851identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9852{
9853 int opcode = insn & 0x1e00000;
9854
9855 if (opcode == 1 << 23) /* ADD */
9856 return 1;
9857
9858 if (opcode == 1 << 22) /* SUB */
9859 return -1;
9860
9861 return 0;
9862}
9863
252b5132 9864/* Perform a relocation as part of a final link. */
9b485d32 9865
252b5132 9866static bfd_reloc_status_type
57e8b36a
NC		 9867elf32_arm_final_link_relocate (reloc_howto_type * howto,
9868 bfd * input_bfd,
9869 bfd * output_bfd,
9870 asection * input_section,
9871 bfd_byte * contents,
9872 Elf_Internal_Rela * rel,
9873 bfd_vma value,
9874 struct bfd_link_info * info,
9875 asection * sym_sec,
9876 const char * sym_name,
34e77a92
RS		 9877 unsigned char st_type,
9878 enum arm_st_branch_type branch_type,
0945cdfd 9879 struct elf_link_hash_entry * h,
f2a9dd69 9880 bfd_boolean * unresolved_reloc_p,
8029a119 9881 char ** error_message)
252b5132
RH		 9882{
9883 unsigned long r_type = howto->type;
9884 unsigned long r_symndx;
9885 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9886 bfd_vma * local_got_offsets;
0855e32b 9887 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9888 asection * sgot;
9889 asection * splt;
252b5132 9890 asection * sreloc = NULL;
362d30a1 9891 asection * srelgot;
252b5132 9892 bfd_vma addend;
ba96a88f 9893 bfd_signed_vma signed_addend;
34e77a92
RS		 9894 unsigned char dynreloc_st_type;
9895 bfd_vma dynreloc_value;
ba96a88f 9896 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9897 struct elf32_arm_link_hash_entry *eh;
9898 union gotplt_union *root_plt;
9899 struct arm_plt_info *arm_plt;
9900 bfd_vma plt_offset;
9901 bfd_vma gotplt_offset;
9902 bfd_boolean has_iplt_entry;
f21f3fe0 9903
9c504268 9904 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9905 if (globals == NULL)
9906 return bfd_reloc_notsupported;
9c504268 9907
0ffa91dd 9908 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 9909 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 9910
9911 /* Some relocation types map to different relocations depending on the
9c504268 9912 target. We pick the right one here. */
eb043451 9913 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9914
9915 /* It is possible to have linker relaxations on some TLS access
9916 models. Update our information here. */
9917 r_type = elf32_arm_tls_transition (info, r_type, h);
9918
eb043451
PB		 9919 if (r_type != howto->type)
9920 howto = elf32_arm_howto_from_type (r_type);
9c504268 9921
34e77a92 9922 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9923 sgot = globals->root.sgot;
252b5132 9924 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9925 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9926
34e77a92
RS		 9927 if (globals->root.dynamic_sections_created)
9928 srelgot = globals->root.srelgot;
9929 else
9930 srelgot = NULL;
9931
252b5132
RH		 9932 r_symndx = ELF32_R_SYM (rel->r_info);
9933
4e7fd91e 9934 if (globals->use_rel)
ba96a88f 9935 {
4e7fd91e
PB		 9936 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9937
9938 if (addend & ((howto->src_mask + 1) >> 1))
9939 {
9940 signed_addend = -1;
9941 signed_addend &= ~ howto->src_mask;
9942 signed_addend |= addend;
9943 }
9944 else
9945 signed_addend = addend;
ba96a88f
NC		 9946 }
9947 else
4e7fd91e 9948 addend = signed_addend = rel->r_addend;
f21f3fe0 9949
39f21624
NC		 9950 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9951 are resolving a function call relocation. */
9952 if (using_thumb_only (globals)
9953 && (r_type == R_ARM_THM_CALL
9954 || r_type == R_ARM_THM_JUMP24)
9955 && branch_type == ST_BRANCH_TO_ARM)
9956 branch_type = ST_BRANCH_TO_THUMB;
9957
34e77a92
RS		 9958 /* Record the symbol information that should be used in dynamic
9959 relocations. */
9960 dynreloc_st_type = st_type;
9961 dynreloc_value = value;
9962 if (branch_type == ST_BRANCH_TO_THUMB)
9963 dynreloc_value |= 1;
9964
9965 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9966 VALUE appropriately for relocations that we resolve at link time. */
9967 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9968 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9969 &arm_plt)
34e77a92
RS		 9970 && root_plt->offset != (bfd_vma) -1)
9971 {
9972 plt_offset = root_plt->offset;
9973 gotplt_offset = arm_plt->got_offset;
9974
9975 if (h == NULL || eh->is_iplt)
9976 {
9977 has_iplt_entry = TRUE;
9978 splt = globals->root.iplt;
9979
9980 /* Populate .iplt entries here, because not all of them will
9981 be seen by finish_dynamic_symbol. The lower bit is set if
9982 we have already populated the entry. */
9983 if (plt_offset & 1)
9984 plt_offset--;
9985 else
9986 {
57460bcf
NC		 9987 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9988 -1, dynreloc_value))
9989 root_plt->offset |= 1;
9990 else
9991 return bfd_reloc_notsupported;
34e77a92
RS		 9992 }
9993
9994 /* Static relocations always resolve to the .iplt entry. */
9995 st_type = STT_FUNC;
9996 value = (splt->output_section->vma
9997 + splt->output_offset
9998 + plt_offset);
9999 branch_type = ST_BRANCH_TO_ARM;
10000
10001 /* If there are non-call relocations that resolve to the .iplt
10002 entry, then all dynamic ones must too. */
10003 if (arm_plt->noncall_refcount != 0)
10004 {
10005 dynreloc_st_type = st_type;
10006 dynreloc_value = value;
10007 }
10008 }
10009 else
10010 /* We populate the .plt entry in finish_dynamic_symbol. */
10011 splt = globals->root.splt;
10012 }
10013 else
10014 {
10015 splt = NULL;
10016 plt_offset = (bfd_vma) -1;
10017 gotplt_offset = (bfd_vma) -1;
10018 }
10019
252b5132
RH		 10020 switch (r_type)
10021 {
10022 case R_ARM_NONE:
28a094c2
DJ		 10023 /* We don't need to find a value for this symbol. It's just a
10024 marker. */
10025 *unresolved_reloc_p = FALSE;
252b5132
RH		 10026 return bfd_reloc_ok;
10027
00a97672
RS		 10028 case R_ARM_ABS12:
10029 if (!globals->vxworks_p)
10030 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10031 /* Fall through. */
00a97672 10032
252b5132
RH		 10033 case R_ARM_PC24:
10034 case R_ARM_ABS32:
bb224fc3 10035 case R_ARM_ABS32_NOI:
252b5132 10036 case R_ARM_REL32:
bb224fc3 10037 case R_ARM_REL32_NOI:
5b5bb741
PB		 10038 case R_ARM_CALL:
10039 case R_ARM_JUMP24:
dfc5f959 10040 case R_ARM_XPC25:
eb043451 10041 case R_ARM_PREL31:
7359ea65 10042 case R_ARM_PLT32:
7359ea65
DJ		 10043 /* Handle relocations which should use the PLT entry. ABS32/REL32
10044 will use the symbol's value, which may point to a PLT entry, but we
10045 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10046 branches in this object should go to it, except if the PLT is too
10047 far away, in which case a long branch stub should be inserted. */
bb224fc3 10048 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10049 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10050 && r_type != R_ARM_CALL
10051 && r_type != R_ARM_JUMP24
10052 && r_type != R_ARM_PLT32)
34e77a92 10053 && plt_offset != (bfd_vma) -1)
7359ea65 10054 {
34e77a92
RS		 10055 /* If we've created a .plt section, and assigned a PLT entry
10056 to this function, it must either be a STT_GNU_IFUNC reference
10057 or not be known to bind locally. In other cases, we should
10058 have cleared the PLT entry by now. */
10059 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10060
10061 value = (splt->output_section->vma
10062 + splt->output_offset
34e77a92 10063 + plt_offset);
0945cdfd 10064 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10065 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10066 contents, rel->r_offset, value,
00a97672 10067 rel->r_addend);
7359ea65
DJ		 10068 }
10069
67687978
PB		 10070 /* When generating a shared object or relocatable executable, these
10071 relocations are copied into the output file to be resolved at
10072 run time. */
0e1862bb
L		 10073 if ((bfd_link_pic (info)
10074 || globals->root.is_relocatable_executable)
7359ea65 10075 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10076 && !(globals->vxworks_p
3348747a
NS		 10077 && strcmp (input_section->output_section->name,
10078 ".tls_vars") == 0)
bb224fc3 10079 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10080 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10081 && !(input_bfd == globals->stub_bfd
10082 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10083 && (h == NULL
10084 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10085 || h->root.type != bfd_link_hash_undefweak)
10086 && r_type != R_ARM_PC24
5b5bb741
PB		 10087 && r_type != R_ARM_CALL
10088 && r_type != R_ARM_JUMP24
ee06dc07 10089 && r_type != R_ARM_PREL31
7359ea65 10090 && r_type != R_ARM_PLT32)
252b5132 10091 {
947216bf 10092 Elf_Internal_Rela outrel;
b34976b6 10093 bfd_boolean skip, relocate;
f21f3fe0 10094
52db4ec2
JW		 10095 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10096 && !h->def_regular)
10097 {
10098 char *v = _("shared object");
10099
0e1862bb 10100 if (bfd_link_executable (info))
52db4ec2
JW		 10101 v = _("PIE executable");
10102
4eca0228 10103 _bfd_error_handler
52db4ec2
JW		 10104 (_("%B: relocation %s against external or undefined symbol `%s'"
10105 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10106 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10107 return bfd_reloc_notsupported;
10108 }
10109
0945cdfd
DJ		 10110 *unresolved_reloc_p = FALSE;
10111
34e77a92 10112 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10113 {
83bac4b0
NC		 10114 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10115 ! globals->use_rel);
f21f3fe0 10116
83bac4b0 10117 if (sreloc == NULL)
252b5132 10118 return bfd_reloc_notsupported;
252b5132 10119 }
f21f3fe0 10120
b34976b6
AM		 10121 skip = FALSE;
10122 relocate = FALSE;
f21f3fe0 10123
00a97672 10124 outrel.r_addend = addend;
c629eae0
JJ		 10125 outrel.r_offset =
10126 _bfd_elf_section_offset (output_bfd, info, input_section,
10127 rel->r_offset);
10128 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10129 skip = TRUE;
0bb2d96a 10130 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10131 skip = TRUE, relocate = TRUE;
252b5132
RH		 10132 outrel.r_offset += (input_section->output_section->vma
10133 + input_section->output_offset);
f21f3fe0 10134
252b5132 10135 if (skip)
0bb2d96a 10136 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10137 else if (h != NULL
10138 && h->dynindx != -1
0e1862bb 10139 && (!bfd_link_pic (info)
1dcb9720
JW		 10140 || !(bfd_link_pie (info)
10141 || SYMBOLIC_BIND (info, h))
f5385ebf 10142 || !h->def_regular))
5e681ec4 10143 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10144 else
10145 {
a16385dc
MM		 10146 int symbol;
10147
5e681ec4 10148 /* This symbol is local, or marked to become local. */
34e77a92 10149 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10150 if (globals->symbian_p)
6366ff1e 10151 {
74541ad4
AM		 10152 asection *osec;
10153
6366ff1e
MM		 10154 /* On Symbian OS, the data segment and text segement
10155 can be relocated independently. Therefore, we
10156 must indicate the segment to which this
10157 relocation is relative. The BPABI allows us to
10158 use any symbol in the right segment; we just use
10159 the section symbol as it is convenient. (We
10160 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10161 will not appear in the dynamic symbol table.)
10162
10163 Note that the dynamic linker ignores the section
10164 symbol value, so we don't subtract osec->vma
10165 from the emitted reloc addend. */
10dbd1f3 10166 if (sym_sec)
74541ad4 10167 osec = sym_sec->output_section;
10dbd1f3 10168 else
74541ad4
AM		 10169 osec = input_section->output_section;
10170 symbol = elf_section_data (osec)->dynindx;
10171 if (symbol == 0)
10172 {
10173 struct elf_link_hash_table *htab = elf_hash_table (info);
10174
10175 if ((osec->flags & SEC_READONLY) == 0
10176 && htab->data_index_section != NULL)
10177 osec = htab->data_index_section;
10178 else
10179 osec = htab->text_index_section;
10180 symbol = elf_section_data (osec)->dynindx;
10181 }
6366ff1e
MM		 10182 BFD_ASSERT (symbol != 0);
10183 }
a16385dc
MM		 10184 else
10185 /* On SVR4-ish systems, the dynamic loader cannot
10186 relocate the text and data segments independently,
10187 so the symbol does not matter. */
10188 symbol = 0;
34e77a92
RS		 10189 if (dynreloc_st_type == STT_GNU_IFUNC)
10190 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10191 to the .iplt entry. Instead, every non-call reference
10192 must use an R_ARM_IRELATIVE relocation to obtain the
10193 correct run-time address. */
10194 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10195 else
10196 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10197 if (globals->use_rel)
10198 relocate = TRUE;
10199 else
34e77a92 10200 outrel.r_addend += dynreloc_value;
252b5132 10201 }
f21f3fe0 10202
47beaa6a 10203 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10204
f21f3fe0 10205 /* If this reloc is against an external symbol, we do not want to
252b5132 10206 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10207 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10208 if (! relocate)
10209 return bfd_reloc_ok;
9a5aca8c 10210
f21f3fe0 10211 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10212 contents, rel->r_offset,
10213 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10214 }
10215 else switch (r_type)
10216 {
00a97672
RS		 10217 case R_ARM_ABS12:
10218 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10219
dfc5f959 10220 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10221 case R_ARM_CALL:
10222 case R_ARM_JUMP24:
8029a119 10223 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10224 case R_ARM_PLT32:
906e58ca 10225 {
906e58ca
NC		 10226 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10227
dfc5f959 10228 if (r_type == R_ARM_XPC25)
252b5132 10229 {
dfc5f959
NC		 10230 /* Check for Arm calling Arm function. */
10231 /* FIXME: Should we translate the instruction into a BL
10232 instruction instead ? */
35fc36a8 10233 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10234 _bfd_error_handler
d003868e
AM		 10235 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10236 input_bfd,
10237 h ? h->root.root.string : "(local)");
dfc5f959 10238 }
155d87d7 10239 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10240 {
10241 /* Check for Arm calling Thumb function. */
35fc36a8 10242 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10243 {
f2a9dd69
DJ		 10244 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10245 output_bfd, input_section,
10246 hit_data, sym_sec, rel->r_offset,
10247 signed_addend, value,
10248 error_message))
10249 return bfd_reloc_ok;
10250 else
10251 return bfd_reloc_dangerous;
dfc5f959 10252 }
252b5132 10253 }
ba96a88f 10254
906e58ca 10255 /* Check if a stub has to be inserted because the
8029a119 10256 destination is too far or we are changing mode. */
155d87d7
CL		 10257 if ( r_type == R_ARM_CALL
10258 || r_type == R_ARM_JUMP24
10259 || r_type == R_ARM_PLT32)
906e58ca 10260 {
fe33d2fa
CL		 10261 enum elf32_arm_stub_type stub_type = arm_stub_none;
10262 struct elf32_arm_link_hash_entry *hash;
10263
10264 hash = (struct elf32_arm_link_hash_entry *) h;
10265 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10266 st_type, &branch_type,
10267 hash, value, sym_sec,
fe33d2fa 10268 input_bfd, sym_name);
5fa9e92f 10269
fe33d2fa 10270 if (stub_type != arm_stub_none)
906e58ca
NC		 10271 {
10272 /* The target is out of reach, so redirect the
10273 branch to the local stub for this function. */
906e58ca
NC		 10274 stub_entry = elf32_arm_get_stub_entry (input_section,
10275 sym_sec, h,
fe33d2fa
CL		 10276 rel, globals,
10277 stub_type);
9cd3e4e5
NC		 10278 {
10279 if (stub_entry != NULL)
10280 value = (stub_entry->stub_offset
10281 + stub_entry->stub_sec->output_offset
10282 + stub_entry->stub_sec->output_section->vma);
10283
10284 if (plt_offset != (bfd_vma) -1)
10285 *unresolved_reloc_p = FALSE;
10286 }
906e58ca 10287 }
fe33d2fa
CL		 10288 else
10289 {
10290 /* If the call goes through a PLT entry, make sure to
10291 check distance to the right destination address. */
34e77a92 10292 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10293 {
10294 value = (splt->output_section->vma
10295 + splt->output_offset
34e77a92 10296 + plt_offset);
fe33d2fa
CL		 10297 *unresolved_reloc_p = FALSE;
10298 /* The PLT entry is in ARM mode, regardless of the
10299 target function. */
35fc36a8 10300 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10301 }
10302 }
906e58ca
NC		 10303 }
10304
dea514f5
PB		 10305 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10306 where:
10307 S is the address of the symbol in the relocation.
10308 P is address of the instruction being relocated.
10309 A is the addend (extracted from the instruction) in bytes.
10310
10311 S is held in 'value'.
10312 P is the base address of the section containing the
10313 instruction plus the offset of the reloc into that
10314 section, ie:
10315 (input_section->output_section->vma +
10316 input_section->output_offset +
10317 rel->r_offset).
10318 A is the addend, converted into bytes, ie:
10319 (signed_addend * 4)
10320
10321 Note: None of these operations have knowledge of the pipeline
10322 size of the processor, thus it is up to the assembler to
10323 encode this information into the addend. */
10324 value -= (input_section->output_section->vma
10325 + input_section->output_offset);
10326 value -= rel->r_offset;
4e7fd91e
PB		 10327 if (globals->use_rel)
10328 value += (signed_addend << howto->size);
10329 else
10330 /* RELA addends do not have to be adjusted by howto->size. */
10331 value += signed_addend;
23080146 10332
dcb5e6e6
NC		 10333 signed_addend = value;
10334 signed_addend >>= howto->rightshift;
9a5aca8c 10335
5ab79981 10336 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10337 the next instruction unless a PLT entry will be created.
77b4f08f 10338 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10339 The jump to the next instruction is optimized as a NOP depending
10340 on the architecture. */
ffcb4889 10341 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10342 && plt_offset == (bfd_vma) -1)
77b4f08f 10343 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10344 {
cd1dac3d
DG		 10345 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10346
10347 if (arch_has_arm_nop (globals))
10348 value |= 0x0320f000;
10349 else
10350 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10351 }
10352 else
59f2c4e7 10353 {
9b485d32 10354 /* Perform a signed range check. */
dcb5e6e6 10355 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10356 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10357 return bfd_reloc_overflow;
9a5aca8c 10358
5ab79981 10359 addend = (value & 2);
39b41c9c 10360
5ab79981
PB		 10361 value = (signed_addend & howto->dst_mask)
10362 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10363
5ab79981
PB		 10364 if (r_type == R_ARM_CALL)
10365 {
155d87d7 10366 /* Set the H bit in the BLX instruction. */
35fc36a8 10367 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10368 {
10369 if (addend)
10370 value |= (1 << 24);
10371 else
10372 value &= ~(bfd_vma)(1 << 24);
10373 }
10374
5ab79981 10375 /* Select the correct instruction (BL or BLX). */
906e58ca 10376 /* Only if we are not handling a BL to a stub. In this
8029a119 10377 case, mode switching is performed by the stub. */
35fc36a8 10378 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10379 value |= (1 << 28);
63e1a0fc 10380 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10381 {
10382 value &= ~(bfd_vma)(1 << 28);
10383 value |= (1 << 24);
10384 }
39b41c9c
PB		 10385 }
10386 }
906e58ca 10387 }
252b5132 10388 break;
f21f3fe0 10389
252b5132
RH		 10390 case R_ARM_ABS32:
10391 value += addend;
35fc36a8 10392 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10393 value |= 1;
10394 break;
f21f3fe0 10395
bb224fc3
MS		 10396 case R_ARM_ABS32_NOI:
10397 value += addend;
10398 break;
10399
252b5132 10400 case R_ARM_REL32:
a8bc6c78 10401 value += addend;
35fc36a8 10402 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10403 value |= 1;
252b5132 10404 value -= (input_section->output_section->vma
62efb346 10405 + input_section->output_offset + rel->r_offset);
252b5132 10406 break;
eb043451 10407
bb224fc3
MS		 10408 case R_ARM_REL32_NOI:
10409 value += addend;
10410 value -= (input_section->output_section->vma
10411 + input_section->output_offset + rel->r_offset);
10412 break;
10413
eb043451
PB		 10414 case R_ARM_PREL31:
10415 value -= (input_section->output_section->vma
10416 + input_section->output_offset + rel->r_offset);
10417 value += signed_addend;
10418 if (! h || h->root.type != bfd_link_hash_undefweak)
10419 {
8029a119 10420 /* Check for overflow. */
eb043451
PB		 10421 if ((value ^ (value >> 1)) & (1 << 30))
10422 return bfd_reloc_overflow;
10423 }
10424 value &= 0x7fffffff;
10425 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10426 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10427 value |= 1;
10428 break;
252b5132 10429 }
f21f3fe0 10430
252b5132
RH		 10431 bfd_put_32 (input_bfd, value, hit_data);
10432 return bfd_reloc_ok;
10433
10434 case R_ARM_ABS8:
fd0fd00c
MJ		 10435 /* PR 16202: Refectch the addend using the correct size. */
10436 if (globals->use_rel)
10437 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10438 value += addend;
4e67d4ca
DG		 10439
10440 /* There is no way to tell whether the user intended to use a signed or
10441 unsigned addend. When checking for overflow we accept either,
10442 as specified by the AAELF. */
10443 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10444 return bfd_reloc_overflow;
10445
10446 bfd_put_8 (input_bfd, value, hit_data);
10447 return bfd_reloc_ok;
10448
10449 case R_ARM_ABS16:
fd0fd00c
MJ		 10450 /* PR 16202: Refectch the addend using the correct size. */
10451 if (globals->use_rel)
10452 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10453 value += addend;
10454
4e67d4ca
DG		 10455 /* See comment for R_ARM_ABS8. */
10456 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10457 return bfd_reloc_overflow;
10458
10459 bfd_put_16 (input_bfd, value, hit_data);
10460 return bfd_reloc_ok;
10461
252b5132 10462 case R_ARM_THM_ABS5:
9b485d32 10463 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10464 if (globals->use_rel)
10465 {
10466 /* Need to refetch addend. */
10467 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10468 /* ??? Need to determine shift amount from operand size. */
10469 addend >>= howto->rightshift;
10470 }
252b5132
RH		 10471 value += addend;
10472
10473 /* ??? Isn't value unsigned? */
10474 if ((long) value > 0x1f || (long) value < -0x10)
10475 return bfd_reloc_overflow;
10476
10477 /* ??? Value needs to be properly shifted into place first. */
10478 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10479 bfd_put_16 (input_bfd, value, hit_data);
10480 return bfd_reloc_ok;
10481
2cab6cc3
MS		 10482 case R_ARM_THM_ALU_PREL_11_0:
10483 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10484 {
10485 bfd_vma insn;
10486 bfd_signed_vma relocation;
10487
10488 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10489 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10490
99059e56
RM		 10491 if (globals->use_rel)
10492 {
10493 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10494 | ((insn & (1 << 26)) >> 15);
10495 if (insn & 0xf00000)
10496 signed_addend = -signed_addend;
10497 }
2cab6cc3
MS		 10498
10499 relocation = value + signed_addend;
79f08007 10500 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10501 + input_section->output_offset
10502 + rel->r_offset);
2cab6cc3 10503
8c65b54f
CS		 10504 /* PR 21523: Use an absolute value. The user of this reloc will
10505 have already selected an ADD or SUB insn appropriately. */
e652757b 10506 value = labs (relocation);
2cab6cc3 10507
99059e56
RM		 10508 if (value >= 0x1000)
10509 return bfd_reloc_overflow;
2cab6cc3 10510
e645cf40
AG		 10511 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10512 if (branch_type == ST_BRANCH_TO_THUMB)
10513 value |= 1;
10514
2cab6cc3 10515 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10516 | ((value & 0x700) << 4)
10517 | ((value & 0x800) << 15);
10518 if (relocation < 0)
10519 insn |= 0xa00000;
2cab6cc3
MS		 10520
10521 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10522 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10523
99059e56 10524 return bfd_reloc_ok;
2cab6cc3
MS		 10525 }
10526
e1ec24c6
NC		 10527 case R_ARM_THM_PC8:
10528 /* PR 10073: This reloc is not generated by the GNU toolchain,
10529 but it is supported for compatibility with third party libraries
10530 generated by other compilers, specifically the ARM/IAR. */
10531 {
10532 bfd_vma insn;
10533 bfd_signed_vma relocation;
10534
10535 insn = bfd_get_16 (input_bfd, hit_data);
10536
99059e56 10537 if (globals->use_rel)
79f08007 10538 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10539
10540 relocation = value + addend;
79f08007 10541 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10542 + input_section->output_offset
10543 + rel->r_offset);
e1ec24c6 10544
b6518b38 10545 value = relocation;
e1ec24c6
NC		 10546
10547 /* We do not check for overflow of this reloc. Although strictly
10548 speaking this is incorrect, it appears to be necessary in order
10549 to work with IAR generated relocs. Since GCC and GAS do not
10550 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10551 a problem for them. */
10552 value &= 0x3fc;
10553
10554 insn = (insn & 0xff00) | (value >> 2);
10555
10556 bfd_put_16 (input_bfd, insn, hit_data);
10557
99059e56 10558 return bfd_reloc_ok;
e1ec24c6
NC		 10559 }
10560
2cab6cc3
MS		 10561 case R_ARM_THM_PC12:
10562 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10563 {
10564 bfd_vma insn;
10565 bfd_signed_vma relocation;
10566
10567 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10568 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10569
99059e56
RM		 10570 if (globals->use_rel)
10571 {
10572 signed_addend = insn & 0xfff;
10573 if (!(insn & (1 << 23)))
10574 signed_addend = -signed_addend;
10575 }
2cab6cc3
MS		 10576
10577 relocation = value + signed_addend;
79f08007 10578 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10579 + input_section->output_offset
10580 + rel->r_offset);
2cab6cc3 10581
b6518b38 10582 value = relocation;
2cab6cc3 10583
99059e56
RM		 10584 if (value >= 0x1000)
10585 return bfd_reloc_overflow;
2cab6cc3
MS		 10586
10587 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10588 if (relocation >= 0)
10589 insn |= (1 << 23);
2cab6cc3
MS		 10590
10591 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10592 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10593
99059e56 10594 return bfd_reloc_ok;
2cab6cc3
MS		 10595 }
10596
dfc5f959 10597 case R_ARM_THM_XPC22:
c19d1205 10598 case R_ARM_THM_CALL:
bd97cb95 10599 case R_ARM_THM_JUMP24:
dfc5f959 10600 /* Thumb BL (branch long instruction). */
252b5132 10601 {
b34976b6 10602 bfd_vma relocation;
99059e56 10603 bfd_vma reloc_sign;
b34976b6
AM		 10604 bfd_boolean overflow = FALSE;
10605 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10606 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10607 bfd_signed_vma reloc_signed_max;
10608 bfd_signed_vma reloc_signed_min;
b34976b6 10609 bfd_vma check;
252b5132 10610 bfd_signed_vma signed_check;
e95de063 10611 int bitsize;
cd1dac3d 10612 const int thumb2 = using_thumb2 (globals);
5e866f5a 10613 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10614
5ab79981 10615 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10616 the next instruction unless a PLT entry will be created.
10617 The jump to the next instruction is optimized as a NOP.W for
10618 Thumb-2 enabled architectures. */
19540007 10619 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10620 && plt_offset == (bfd_vma) -1)
5ab79981 10621 {
60a019a0 10622 if (thumb2)
cd1dac3d
DG		 10623 {
10624 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10625 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10626 }
10627 else
10628 {
10629 bfd_put_16 (input_bfd, 0xe000, hit_data);
10630 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10631 }
5ab79981
PB		 10632 return bfd_reloc_ok;
10633 }
10634
e95de063 10635 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10636 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10637 if (globals->use_rel)
10638 {
99059e56
RM		 10639 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10640 bfd_vma upper = upper_insn & 0x3ff;
10641 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10642 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10643 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10644 bfd_vma i1 = j1 ^ s ? 0 : 1;
10645 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10646
99059e56
RM		 10647 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10648 /* Sign extend. */
10649 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10650
4e7fd91e
PB		 10651 signed_addend = addend;
10652 }
cb1afa5c 10653
dfc5f959
NC		 10654 if (r_type == R_ARM_THM_XPC22)
10655 {
10656 /* Check for Thumb to Thumb call. */
10657 /* FIXME: Should we translate the instruction into a BL
10658 instruction instead ? */
35fc36a8 10659 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10660 _bfd_error_handler
d003868e
AM		 10661 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10662 input_bfd,
10663 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10664 }
10665 else
252b5132 10666 {
dfc5f959
NC		 10667 /* If it is not a call to Thumb, assume call to Arm.
10668 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10669 function call at all, but rather a long jump. Calls through
10670 the PLT do not require stubs. */
34e77a92 10671 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10672 {
bd97cb95 10673 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10674 {
10675 /* Convert BL to BLX. */
10676 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10677 }
155d87d7
CL		 10678 else if (( r_type != R_ARM_THM_CALL)
10679 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10680 {
10681 if (elf32_thumb_to_arm_stub
10682 (info, sym_name, input_bfd, output_bfd, input_section,
10683 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10684 error_message))
10685 return bfd_reloc_ok;
10686 else
10687 return bfd_reloc_dangerous;
10688 }
da5938a2 10689 }
35fc36a8
RS		 10690 else if (branch_type == ST_BRANCH_TO_THUMB
10691 && globals->use_blx
bd97cb95 10692 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10693 {
10694 /* Make sure this is a BL. */
10695 lower_insn |= 0x1800;
10696 }
252b5132 10697 }
f21f3fe0 10698
fe33d2fa 10699 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10700 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10701 {
10702 /* Check if a stub has to be inserted because the destination
8029a119 10703 is too far. */
fe33d2fa
CL		 10704 struct elf32_arm_stub_hash_entry *stub_entry;
10705 struct elf32_arm_link_hash_entry *hash;
10706
10707 hash = (struct elf32_arm_link_hash_entry *) h;
10708
10709 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10710 st_type, &branch_type,
10711 hash, value, sym_sec,
fe33d2fa
CL		 10712 input_bfd, sym_name);
10713
10714 if (stub_type != arm_stub_none)
906e58ca
NC		 10715 {
10716 /* The target is out of reach or we are changing modes, so
10717 redirect the branch to the local stub for this
10718 function. */
10719 stub_entry = elf32_arm_get_stub_entry (input_section,
10720 sym_sec, h,
fe33d2fa
CL		 10721 rel, globals,
10722 stub_type);
906e58ca 10723 if (stub_entry != NULL)
9cd3e4e5
NC		 10724 {
10725 value = (stub_entry->stub_offset
10726 + stub_entry->stub_sec->output_offset
10727 + stub_entry->stub_sec->output_section->vma);
10728
10729 if (plt_offset != (bfd_vma) -1)
10730 *unresolved_reloc_p = FALSE;
10731 }
906e58ca 10732
f4ac8484 10733 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10734 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10735 {
10736 if ((stub_entry
10737 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10738 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10739 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10740 }
906e58ca
NC		 10741 }
10742 }
10743
fe33d2fa 10744 /* Handle calls via the PLT. */
34e77a92 10745 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10746 {
10747 value = (splt->output_section->vma
10748 + splt->output_offset
34e77a92 10749 + plt_offset);
fe33d2fa 10750
eed94f8f
NC		 10751 if (globals->use_blx
10752 && r_type == R_ARM_THM_CALL
10753 && ! using_thumb_only (globals))
fe33d2fa
CL		 10754 {
10755 /* If the Thumb BLX instruction is available, convert
10756 the BL to a BLX instruction to call the ARM-mode
10757 PLT entry. */
10758 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10759 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10760 }
10761 else
10762 {
eed94f8f
NC		 10763 if (! using_thumb_only (globals))
10764 /* Target the Thumb stub before the ARM PLT entry. */
10765 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10766 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10767 }
10768 *unresolved_reloc_p = FALSE;
10769 }
10770
ba96a88f 10771 relocation = value + signed_addend;
f21f3fe0 10772
252b5132 10773 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10774 + input_section->output_offset
10775 + rel->r_offset);
9a5aca8c 10776
252b5132
RH		 10777 check = relocation >> howto->rightshift;
10778
10779 /* If this is a signed value, the rightshift just dropped
10780 leading 1 bits (assuming twos complement). */
10781 if ((bfd_signed_vma) relocation >= 0)
10782 signed_check = check;
10783 else
10784 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10785
e95de063
MS		 10786 /* Calculate the permissable maximum and minimum values for
10787 this relocation according to whether we're relocating for
10788 Thumb-2 or not. */
10789 bitsize = howto->bitsize;
5e866f5a 10790 if (!thumb2_bl)
e95de063 10791 bitsize -= 2;
f6ebfac0 10792 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10793 reloc_signed_min = ~reloc_signed_max;
10794
252b5132 10795 /* Assumes two's complement. */
ba96a88f 10796 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10797 overflow = TRUE;
252b5132 10798
bd97cb95 10799 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10800 /* For a BLX instruction, make sure that the relocation is rounded up
10801 to a word boundary. This follows the semantics of the instruction
10802 which specifies that bit 1 of the target address will come from bit
10803 1 of the base address. */
10804 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10805
e95de063
MS		 10806 /* Put RELOCATION back into the insn. Assumes two's complement.
10807 We use the Thumb-2 encoding, which is safe even if dealing with
10808 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10809 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10810 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10811 | ((relocation >> 12) & 0x3ff)
10812 | (reloc_sign << 10);
906e58ca 10813 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10814 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10815 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10816 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10817
252b5132
RH		 10818 /* Put the relocated value back in the object file: */
10819 bfd_put_16 (input_bfd, upper_insn, hit_data);
10820 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10821
10822 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10823 }
10824 break;
10825
c19d1205
ZW		 10826 case R_ARM_THM_JUMP19:
10827 /* Thumb32 conditional branch instruction. */
10828 {
10829 bfd_vma relocation;
10830 bfd_boolean overflow = FALSE;
10831 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10832 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10833 bfd_signed_vma reloc_signed_max = 0xffffe;
10834 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10835 bfd_signed_vma signed_check;
c5423981
TG		 10836 enum elf32_arm_stub_type stub_type = arm_stub_none;
10837 struct elf32_arm_stub_hash_entry *stub_entry;
10838 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10839
10840 /* Need to refetch the addend, reconstruct the top three bits,
10841 and squish the two 11 bit pieces together. */
10842 if (globals->use_rel)
10843 {
10844 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10845 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10846 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10847 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10848 bfd_vma lower = (lower_insn & 0x07ff);
10849
a00a1f35
MS		 10850 upper |= J1 << 6;
10851 upper |= J2 << 7;
10852 upper |= (!S) << 8;
c19d1205
ZW		 10853 upper -= 0x0100; /* Sign extend. */
10854
10855 addend = (upper << 12) | (lower << 1);
10856 signed_addend = addend;
10857 }
10858
bd97cb95 10859 /* Handle calls via the PLT. */
34e77a92 10860 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10861 {
10862 value = (splt->output_section->vma
10863 + splt->output_offset
34e77a92 10864 + plt_offset);
bd97cb95
DJ		 10865 /* Target the Thumb stub before the ARM PLT entry. */
10866 value -= PLT_THUMB_STUB_SIZE;
10867 *unresolved_reloc_p = FALSE;
10868 }
10869
c5423981
TG		 10870 hash = (struct elf32_arm_link_hash_entry *)h;
10871
10872 stub_type = arm_type_of_stub (info, input_section, rel,
10873 st_type, &branch_type,
10874 hash, value, sym_sec,
10875 input_bfd, sym_name);
10876 if (stub_type != arm_stub_none)
10877 {
10878 stub_entry = elf32_arm_get_stub_entry (input_section,
10879 sym_sec, h,
10880 rel, globals,
10881 stub_type);
10882 if (stub_entry != NULL)
10883 {
10884 value = (stub_entry->stub_offset
10885 + stub_entry->stub_sec->output_offset
10886 + stub_entry->stub_sec->output_section->vma);
10887 }
10888 }
c19d1205 10889
99059e56 10890 relocation = value + signed_addend;
c19d1205
ZW		 10891 relocation -= (input_section->output_section->vma
10892 + input_section->output_offset
10893 + rel->r_offset);
a00a1f35 10894 signed_check = (bfd_signed_vma) relocation;
c19d1205 10895
c19d1205
ZW		 10896 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10897 overflow = TRUE;
10898
10899 /* Put RELOCATION back into the insn. */
10900 {
10901 bfd_vma S = (relocation & 0x00100000) >> 20;
10902 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10903 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10904 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10905 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10906
a00a1f35 10907 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10908 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10909 }
10910
10911 /* Put the relocated value back in the object file: */
10912 bfd_put_16 (input_bfd, upper_insn, hit_data);
10913 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10914
10915 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10916 }
10917
10918 case R_ARM_THM_JUMP11:
10919 case R_ARM_THM_JUMP8:
10920 case R_ARM_THM_JUMP6:
51c5503b
NC		 10921 /* Thumb B (branch) instruction). */
10922 {
6cf9e9fe 10923 bfd_signed_vma relocation;
51c5503b
NC		 10924 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10925 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10926 bfd_signed_vma signed_check;
10927
c19d1205
ZW		 10928 /* CZB cannot jump backward. */
10929 if (r_type == R_ARM_THM_JUMP6)
10930 reloc_signed_min = 0;
10931
4e7fd91e 10932 if (globals->use_rel)
6cf9e9fe 10933 {
4e7fd91e
PB		 10934 /* Need to refetch addend. */
10935 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10936 if (addend & ((howto->src_mask + 1) >> 1))
10937 {
10938 signed_addend = -1;
10939 signed_addend &= ~ howto->src_mask;
10940 signed_addend |= addend;
10941 }
10942 else
10943 signed_addend = addend;
10944 /* The value in the insn has been right shifted. We need to
10945 undo this, so that we can perform the address calculation
10946 in terms of bytes. */
10947 signed_addend <<= howto->rightshift;
6cf9e9fe 10948 }
6cf9e9fe 10949 relocation = value + signed_addend;
51c5503b
NC		 10950
10951 relocation -= (input_section->output_section->vma
10952 + input_section->output_offset
10953 + rel->r_offset);
10954
6cf9e9fe
NC		 10955 relocation >>= howto->rightshift;
10956 signed_check = relocation;
c19d1205
ZW		 10957
10958 if (r_type == R_ARM_THM_JUMP6)
10959 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10960 else
10961 relocation &= howto->dst_mask;
51c5503b 10962 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10963
51c5503b
NC		 10964 bfd_put_16 (input_bfd, relocation, hit_data);
10965
10966 /* Assumes two's complement. */
10967 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10968 return bfd_reloc_overflow;
10969
10970 return bfd_reloc_ok;
10971 }
cedb70c5 10972
8375c36b
PB		 10973 case R_ARM_ALU_PCREL7_0:
10974 case R_ARM_ALU_PCREL15_8:
10975 case R_ARM_ALU_PCREL23_15:
10976 {
10977 bfd_vma insn;
10978 bfd_vma relocation;
10979
10980 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10981 if (globals->use_rel)
10982 {
10983 /* Extract the addend. */
10984 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10985 signed_addend = addend;
10986 }
8375c36b
PB		 10987 relocation = value + signed_addend;
10988
10989 relocation -= (input_section->output_section->vma
10990 + input_section->output_offset
10991 + rel->r_offset);
10992 insn = (insn & ~0xfff)
10993 | ((howto->bitpos << 7) & 0xf00)
10994 | ((relocation >> howto->bitpos) & 0xff);
10995 bfd_put_32 (input_bfd, value, hit_data);
10996 }
10997 return bfd_reloc_ok;
10998
252b5132
RH		 10999 case R_ARM_GNU_VTINHERIT:
11000 case R_ARM_GNU_VTENTRY:
11001 return bfd_reloc_ok;
11002
c19d1205 11003 case R_ARM_GOTOFF32:
252b5132 11004 /* Relocation is relative to the start of the
99059e56 11005 global offset table. */
252b5132
RH		 11006
11007 BFD_ASSERT (sgot != NULL);
11008 if (sgot == NULL)
99059e56 11009 return bfd_reloc_notsupported;
9a5aca8c 11010
cedb70c5 11011 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11012 address by one, so that attempts to call the function pointer will
11013 correctly interpret it as Thumb code. */
35fc36a8 11014 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11015 value += 1;
11016
252b5132 11017 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11018 calculation. We always want the start of .got. If we
11019 define _GLOBAL_OFFSET_TABLE in a different way, as is
11020 permitted by the ABI, we might have to change this
11021 calculation. */
252b5132 11022 value -= sgot->output_section->vma;
f21f3fe0 11023 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11024 contents, rel->r_offset, value,
00a97672 11025 rel->r_addend);
252b5132
RH		 11026
11027 case R_ARM_GOTPC:
a7c10850 11028 /* Use global offset table as symbol value. */
252b5132 11029 BFD_ASSERT (sgot != NULL);
f21f3fe0 11030
252b5132 11031 if (sgot == NULL)
99059e56 11032 return bfd_reloc_notsupported;
252b5132 11033
0945cdfd 11034 *unresolved_reloc_p = FALSE;
252b5132 11035 value = sgot->output_section->vma;
f21f3fe0 11036 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11037 contents, rel->r_offset, value,
00a97672 11038 rel->r_addend);
f21f3fe0 11039
252b5132 11040 case R_ARM_GOT32:
eb043451 11041 case R_ARM_GOT_PREL:
252b5132 11042 /* Relocation is to the entry for this symbol in the
99059e56 11043 global offset table. */
252b5132
RH		 11044 if (sgot == NULL)
11045 return bfd_reloc_notsupported;
f21f3fe0 11046
34e77a92
RS		 11047 if (dynreloc_st_type == STT_GNU_IFUNC
11048 && plt_offset != (bfd_vma) -1
11049 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11050 {
11051 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11052 symbol, and the relocation resolves directly to the runtime
11053 target rather than to the .iplt entry. This means that any
11054 .got entry would be the same value as the .igot.plt entry,
11055 so there's no point creating both. */
11056 sgot = globals->root.igotplt;
11057 value = sgot->output_offset + gotplt_offset;
11058 }
11059 else if (h != NULL)
252b5132
RH		 11060 {
11061 bfd_vma off;
f21f3fe0 11062
252b5132
RH		 11063 off = h->got.offset;
11064 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11065 if ((off & 1) != 0)
252b5132 11066 {
b436d854
RS		 11067 /* We have already processsed one GOT relocation against
11068 this symbol. */
11069 off &= ~1;
11070 if (globals->root.dynamic_sections_created
11071 && !SYMBOL_REFERENCES_LOCAL (info, h))
11072 *unresolved_reloc_p = FALSE;
11073 }
11074 else
11075 {
11076 Elf_Internal_Rela outrel;
11077
6f820c85 11078 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11079 {
11080 /* If the symbol doesn't resolve locally in a static
11081 object, we have an undefined reference. If the
11082 symbol doesn't resolve locally in a dynamic object,
11083 it should be resolved by the dynamic linker. */
11084 if (globals->root.dynamic_sections_created)
11085 {
11086 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11087 *unresolved_reloc_p = FALSE;
11088 }
11089 else
11090 outrel.r_info = 0;
11091 outrel.r_addend = 0;
11092 }
252b5132
RH		 11093 else
11094 {
34e77a92 11095 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11096 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11097 else if (bfd_link_pic (info)
11098 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11099 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11100 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11101 else
11102 outrel.r_info = 0;
34e77a92 11103 outrel.r_addend = dynreloc_value;
b436d854 11104 }
ee29b9fb 11105
b436d854
RS		 11106 /* The GOT entry is initialized to zero by default.
11107 See if we should install a different value. */
11108 if (outrel.r_addend != 0
11109 && (outrel.r_info == 0 || globals->use_rel))
11110 {
11111 bfd_put_32 (output_bfd, outrel.r_addend,
11112 sgot->contents + off);
11113 outrel.r_addend = 0;
252b5132 11114 }
f21f3fe0 11115
b436d854
RS		 11116 if (outrel.r_info != 0)
11117 {
11118 outrel.r_offset = (sgot->output_section->vma
11119 + sgot->output_offset
11120 + off);
11121 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11122 }
11123 h->got.offset |= 1;
11124 }
252b5132
RH		 11125 value = sgot->output_offset + off;
11126 }
11127 else
11128 {
11129 bfd_vma off;
f21f3fe0 11130
5025eb7c
AO		 11131 BFD_ASSERT (local_got_offsets != NULL
11132 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11133
252b5132 11134 off = local_got_offsets[r_symndx];
f21f3fe0 11135
252b5132
RH		 11136 /* The offset must always be a multiple of 4. We use the
11137 least significant bit to record whether we have already
9b485d32 11138 generated the necessary reloc. */
252b5132
RH		 11139 if ((off & 1) != 0)
11140 off &= ~1;
11141 else
11142 {
00a97672 11143 if (globals->use_rel)
34e77a92 11144 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11145
0e1862bb 11146 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11147 {
947216bf 11148 Elf_Internal_Rela outrel;
f21f3fe0 11149
34e77a92 11150 outrel.r_addend = addend + dynreloc_value;
252b5132 11151 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11152 + sgot->output_offset
252b5132 11153 + off);
34e77a92 11154 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11155 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11156 else
11157 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11158 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11159 }
f21f3fe0 11160
252b5132
RH		 11161 local_got_offsets[r_symndx] |= 1;
11162 }
f21f3fe0 11163
252b5132
RH		 11164 value = sgot->output_offset + off;
11165 }
eb043451
PB		 11166 if (r_type != R_ARM_GOT32)
11167 value += sgot->output_section->vma;
9a5aca8c 11168
f21f3fe0 11169 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11170 contents, rel->r_offset, value,
00a97672 11171 rel->r_addend);
f21f3fe0 11172
ba93b8ac
DJ		 11173 case R_ARM_TLS_LDO32:
11174 value = value - dtpoff_base (info);
11175
11176 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11177 contents, rel->r_offset, value,
11178 rel->r_addend);
ba93b8ac
DJ		 11179
11180 case R_ARM_TLS_LDM32:
11181 {
11182 bfd_vma off;
11183
362d30a1 11184 if (sgot == NULL)
ba93b8ac
DJ		 11185 abort ();
11186
11187 off = globals->tls_ldm_got.offset;
11188
11189 if ((off & 1) != 0)
11190 off &= ~1;
11191 else
11192 {
11193 /* If we don't know the module number, create a relocation
11194 for it. */
0e1862bb 11195 if (bfd_link_pic (info))
ba93b8ac
DJ		 11196 {
11197 Elf_Internal_Rela outrel;
ba93b8ac 11198
362d30a1 11199 if (srelgot == NULL)
ba93b8ac
DJ		 11200 abort ();
11201
00a97672 11202 outrel.r_addend = 0;
362d30a1
RS		 11203 outrel.r_offset = (sgot->output_section->vma
11204 + sgot->output_offset + off);
ba93b8ac
DJ		 11205 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11206
00a97672
RS		 11207 if (globals->use_rel)
11208 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11209 sgot->contents + off);
ba93b8ac 11210
47beaa6a 11211 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11212 }
11213 else
362d30a1 11214 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11215
11216 globals->tls_ldm_got.offset |= 1;
11217 }
11218
362d30a1 11219 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11220 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11221
11222 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11223 contents, rel->r_offset, value,
00a97672 11224 rel->r_addend);
ba93b8ac
DJ		 11225 }
11226
0855e32b
NS		 11227 case R_ARM_TLS_CALL:
11228 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11229 case R_ARM_TLS_GD32:
11230 case R_ARM_TLS_IE32:
0855e32b
NS		 11231 case R_ARM_TLS_GOTDESC:
11232 case R_ARM_TLS_DESCSEQ:
11233 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11234 {
0855e32b
NS		 11235 bfd_vma off, offplt;
11236 int indx = 0;
ba93b8ac
DJ		 11237 char tls_type;
11238
0855e32b 11239 BFD_ASSERT (sgot != NULL);
ba93b8ac 11240
ba93b8ac
DJ		 11241 if (h != NULL)
11242 {
11243 bfd_boolean dyn;
11244 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11245 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11246 bfd_link_pic (info),
11247 h)
11248 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11249 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11250 {
11251 *unresolved_reloc_p = FALSE;
11252 indx = h->dynindx;
11253 }
11254 off = h->got.offset;
0855e32b 11255 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11256 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11257 }
11258 else
11259 {
0855e32b 11260 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11261 off = local_got_offsets[r_symndx];
0855e32b 11262 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11263 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11264 }
11265
0855e32b 11266 /* Linker relaxations happens from one of the
b38cadfb 11267 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11268 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11269 tls_type = GOT_TLS_IE;
0855e32b
NS		 11270
11271 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11272
11273 if ((off & 1) != 0)
11274 off &= ~1;
11275 else
11276 {
11277 bfd_boolean need_relocs = FALSE;
11278 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11279 int cur_off = off;
11280
11281 /* The GOT entries have not been initialized yet. Do it
11282 now, and emit any relocations. If both an IE GOT and a
11283 GD GOT are necessary, we emit the GD first. */
11284
0e1862bb 11285 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11286 && (h == NULL
11287 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11288 || h->root.type != bfd_link_hash_undefweak))
11289 {
11290 need_relocs = TRUE;
0855e32b 11291 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11292 }
11293
0855e32b
NS		 11294 if (tls_type & GOT_TLS_GDESC)
11295 {
47beaa6a
RS		 11296 bfd_byte *loc;
11297
0855e32b
NS		 11298 /* We should have relaxed, unless this is an undefined
11299 weak symbol. */
11300 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11301 || bfd_link_pic (info));
0855e32b 11302 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11303 <= globals->root.sgotplt->size);
0855e32b
NS		 11304
11305 outrel.r_addend = 0;
11306 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11307 + globals->root.sgotplt->output_offset
11308 + offplt
11309 + globals->sgotplt_jump_table_size);
b38cadfb 11310
0855e32b
NS		 11311 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11312 sreloc = globals->root.srelplt;
11313 loc = sreloc->contents;
11314 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11315 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11316 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11317
11318 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11319
11320 /* For globals, the first word in the relocation gets
11321 the relocation index and the top bit set, or zero,
11322 if we're binding now. For locals, it gets the
11323 symbol's offset in the tls section. */
99059e56 11324 bfd_put_32 (output_bfd,
0855e32b
NS		 11325 !h ? value - elf_hash_table (info)->tls_sec->vma
11326 : info->flags & DF_BIND_NOW ? 0
11327 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11328 globals->root.sgotplt->contents + offplt
11329 + globals->sgotplt_jump_table_size);
11330
0855e32b 11331 /* Second word in the relocation is always zero. */
99059e56 11332 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11333 globals->root.sgotplt->contents + offplt
11334 + globals->sgotplt_jump_table_size + 4);
0855e32b 11335 }
ba93b8ac
DJ		 11336 if (tls_type & GOT_TLS_GD)
11337 {
11338 if (need_relocs)
11339 {
00a97672 11340 outrel.r_addend = 0;
362d30a1
RS		 11341 outrel.r_offset = (sgot->output_section->vma
11342 + sgot->output_offset
00a97672 11343 + cur_off);
ba93b8ac 11344 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11345
00a97672
RS		 11346 if (globals->use_rel)
11347 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11348 sgot->contents + cur_off);
00a97672 11349
47beaa6a 11350 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11351
11352 if (indx == 0)
11353 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11354 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11355 else
11356 {
00a97672 11357 outrel.r_addend = 0;
ba93b8ac
DJ		 11358 outrel.r_info = ELF32_R_INFO (indx,
11359 R_ARM_TLS_DTPOFF32);
11360 outrel.r_offset += 4;
00a97672
RS		 11361
11362 if (globals->use_rel)
11363 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11364 sgot->contents + cur_off + 4);
00a97672 11365
47beaa6a
RS		 11366 elf32_arm_add_dynreloc (output_bfd, info,
11367 srelgot, &outrel);
ba93b8ac
DJ		 11368 }
11369 }
11370 else
11371 {
11372 /* If we are not emitting relocations for a
11373 general dynamic reference, then we must be in a
11374 static link or an executable link with the
11375 symbol binding locally. Mark it as belonging
11376 to module 1, the executable. */
11377 bfd_put_32 (output_bfd, 1,
362d30a1 11378 sgot->contents + cur_off);
ba93b8ac 11379 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11380 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11381 }
11382
11383 cur_off += 8;
11384 }
11385
11386 if (tls_type & GOT_TLS_IE)
11387 {
11388 if (need_relocs)
11389 {
00a97672
RS		 11390 if (indx == 0)
11391 outrel.r_addend = value - dtpoff_base (info);
11392 else
11393 outrel.r_addend = 0;
362d30a1
RS		 11394 outrel.r_offset = (sgot->output_section->vma
11395 + sgot->output_offset
ba93b8ac
DJ		 11396 + cur_off);
11397 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11398
00a97672
RS		 11399 if (globals->use_rel)
11400 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11401 sgot->contents + cur_off);
ba93b8ac 11402
47beaa6a 11403 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11404 }
11405 else
11406 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11407 sgot->contents + cur_off);
ba93b8ac
DJ		 11408 cur_off += 4;
11409 }
11410
11411 if (h != NULL)
11412 h->got.offset |= 1;
11413 else
11414 local_got_offsets[r_symndx] |= 1;
11415 }
11416
11417 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11418 off += 8;
0855e32b
NS		 11419 else if (tls_type & GOT_TLS_GDESC)
11420 off = offplt;
11421
11422 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11423 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11424 {
11425 bfd_signed_vma offset;
12352d3f
PB		 11426 /* TLS stubs are arm mode. The original symbol is a
11427 data object, so branch_type is bogus. */
11428 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11429 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11430 = arm_type_of_stub (info, input_section, rel,
11431 st_type, &branch_type,
0855e32b
NS		 11432 (struct elf32_arm_link_hash_entry *)h,
11433 globals->tls_trampoline, globals->root.splt,
11434 input_bfd, sym_name);
11435
11436 if (stub_type != arm_stub_none)
11437 {
11438 struct elf32_arm_stub_hash_entry *stub_entry
11439 = elf32_arm_get_stub_entry
11440 (input_section, globals->root.splt, 0, rel,
11441 globals, stub_type);
11442 offset = (stub_entry->stub_offset
11443 + stub_entry->stub_sec->output_offset
11444 + stub_entry->stub_sec->output_section->vma);
11445 }
11446 else
11447 offset = (globals->root.splt->output_section->vma
11448 + globals->root.splt->output_offset
11449 + globals->tls_trampoline);
11450
11451 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11452 {
11453 unsigned long inst;
b38cadfb
NC		 11454
11455 offset -= (input_section->output_section->vma
11456 + input_section->output_offset
11457 + rel->r_offset + 8);
0855e32b
NS		 11458
11459 inst = offset >> 2;
11460 inst &= 0x00ffffff;
11461 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11462 }
11463 else
11464 {
11465 /* Thumb blx encodes the offset in a complicated
11466 fashion. */
11467 unsigned upper_insn, lower_insn;
11468 unsigned neg;
11469
b38cadfb
NC		 11470 offset -= (input_section->output_section->vma
11471 + input_section->output_offset
0855e32b 11472 + rel->r_offset + 4);
b38cadfb 11473
12352d3f
PB		 11474 if (stub_type != arm_stub_none
11475 && arm_stub_is_thumb (stub_type))
11476 {
11477 lower_insn = 0xd000;
11478 }
11479 else
11480 {
11481 lower_insn = 0xc000;
6a631e86 11482 /* Round up the offset to a word boundary. */
12352d3f
PB		 11483 offset = (offset + 2) & ~2;
11484 }
11485
0855e32b
NS		 11486 neg = offset < 0;
11487 upper_insn = (0xf000
11488 | ((offset >> 12) & 0x3ff)
11489 | (neg << 10));
12352d3f 11490 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11491 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11492 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11493 bfd_put_16 (input_bfd, upper_insn, hit_data);
11494 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11495 return bfd_reloc_ok;
11496 }
11497 }
11498 /* These relocations needs special care, as besides the fact
11499 they point somewhere in .gotplt, the addend must be
11500 adjusted accordingly depending on the type of instruction
6a631e86 11501 we refer to. */
0855e32b
NS		 11502 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11503 {
11504 unsigned long data, insn;
11505 unsigned thumb;
b38cadfb 11506
0855e32b
NS		 11507 data = bfd_get_32 (input_bfd, hit_data);
11508 thumb = data & 1;
11509 data &= ~1u;
b38cadfb 11510
0855e32b
NS		 11511 if (thumb)
11512 {
11513 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11514 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11515 insn = (insn << 16)
11516 | bfd_get_16 (input_bfd,
11517 contents + rel->r_offset - data + 2);
11518 if ((insn & 0xf800c000) == 0xf000c000)
11519 /* bl/blx */
11520 value = -6;
11521 else if ((insn & 0xffffff00) == 0x4400)
11522 /* add */
11523 value = -5;
11524 else
11525 {
4eca0228 11526 _bfd_error_handler
695344c0 11527 /* xgettext:c-format */
d42c267e
AM		 11528 (_("%B(%A+%#Lx): unexpected Thumb instruction '%#lx' referenced by TLS_GOTDESC"),
11529 input_bfd, input_section, rel->r_offset, insn);
0855e32b
NS		 11530 return bfd_reloc_notsupported;
11531 }
11532 }
11533 else
11534 {
11535 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11536
11537 switch (insn >> 24)
11538 {
11539 case 0xeb: /* bl */
11540 case 0xfa: /* blx */
11541 value = -4;
11542 break;
11543
11544 case 0xe0: /* add */
11545 value = -8;
11546 break;
b38cadfb 11547
0855e32b 11548 default:
4eca0228 11549 _bfd_error_handler
695344c0 11550 /* xgettext:c-format */
d42c267e
AM		 11551 (_("%B(%A+%#Lx): unexpected ARM instruction '%#lx' referenced by TLS_GOTDESC"),
11552 input_bfd, input_section, rel->r_offset, insn);
0855e32b
NS		 11553 return bfd_reloc_notsupported;
11554 }
11555 }
b38cadfb 11556
0855e32b
NS		 11557 value += ((globals->root.sgotplt->output_section->vma
11558 + globals->root.sgotplt->output_offset + off)
11559 - (input_section->output_section->vma
11560 + input_section->output_offset
11561 + rel->r_offset)
11562 + globals->sgotplt_jump_table_size);
11563 }
11564 else
11565 value = ((globals->root.sgot->output_section->vma
11566 + globals->root.sgot->output_offset + off)
11567 - (input_section->output_section->vma
11568 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11569
11570 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11571 contents, rel->r_offset, value,
00a97672 11572 rel->r_addend);
ba93b8ac
DJ		 11573 }
11574
11575 case R_ARM_TLS_LE32:
3cbc1e5e 11576 if (bfd_link_dll (info))
ba93b8ac 11577 {
4eca0228 11578 _bfd_error_handler
695344c0 11579 /* xgettext:c-format */
d42c267e
AM		 11580 (_("%B(%A+%#Lx): %s relocation not permitted in shared object"),
11581 input_bfd, input_section, rel->r_offset, howto->name);
46691134 11582 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11583 }
11584 else
11585 value = tpoff (info, value);
906e58ca 11586
ba93b8ac 11587 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11588 contents, rel->r_offset, value,
11589 rel->r_addend);
ba93b8ac 11590
319850b4
JB		 11591 case R_ARM_V4BX:
11592 if (globals->fix_v4bx)
845b51d6
PB		 11593 {
11594 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11595
845b51d6
PB		 11596 /* Ensure that we have a BX instruction. */
11597 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11598
845b51d6
PB		 11599 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11600 {
11601 /* Branch to veneer. */
11602 bfd_vma glue_addr;
11603 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11604 glue_addr -= input_section->output_section->vma
11605 + input_section->output_offset
11606 + rel->r_offset + 8;
11607 insn = (insn & 0xf0000000) | 0x0a000000
11608 | ((glue_addr >> 2) & 0x00ffffff);
11609 }
11610 else
11611 {
11612 /* Preserve Rm (lowest four bits) and the condition code
11613 (highest four bits). Other bits encode MOV PC,Rm. */
11614 insn = (insn & 0xf000000f) | 0x01a0f000;
11615 }
319850b4 11616
845b51d6
PB		 11617 bfd_put_32 (input_bfd, insn, hit_data);
11618 }
319850b4
JB		 11619 return bfd_reloc_ok;
11620
b6895b4f
PB		 11621 case R_ARM_MOVW_ABS_NC:
11622 case R_ARM_MOVT_ABS:
11623 case R_ARM_MOVW_PREL_NC:
11624 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11625 /* Until we properly support segment-base-relative addressing then
11626 we assume the segment base to be zero, as for the group relocations.
11627 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11628 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11629 case R_ARM_MOVW_BREL_NC:
11630 case R_ARM_MOVW_BREL:
11631 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11632 {
11633 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11634
11635 if (globals->use_rel)
11636 {
11637 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11638 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11639 }
92f5d02b 11640
b6895b4f 11641 value += signed_addend;
b6895b4f
PB		 11642
11643 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11644 value -= (input_section->output_section->vma
11645 + input_section->output_offset + rel->r_offset);
11646
92f5d02b 11647 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11648 return bfd_reloc_overflow;
92f5d02b 11649
35fc36a8 11650 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11651 value |= 1;
11652
11653 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11654 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11655 value >>= 16;
11656
11657 insn &= 0xfff0f000;
11658 insn |= value & 0xfff;
11659 insn |= (value & 0xf000) << 4;
11660 bfd_put_32 (input_bfd, insn, hit_data);
11661 }
11662 return bfd_reloc_ok;
11663
11664 case R_ARM_THM_MOVW_ABS_NC:
11665 case R_ARM_THM_MOVT_ABS:
11666 case R_ARM_THM_MOVW_PREL_NC:
11667 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11668 /* Until we properly support segment-base-relative addressing then
11669 we assume the segment base to be zero, as for the above relocations.
11670 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11671 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11672 as R_ARM_THM_MOVT_ABS. */
11673 case R_ARM_THM_MOVW_BREL_NC:
11674 case R_ARM_THM_MOVW_BREL:
11675 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11676 {
11677 bfd_vma insn;
906e58ca 11678
b6895b4f
PB		 11679 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11680 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11681
11682 if (globals->use_rel)
11683 {
11684 addend = ((insn >> 4) & 0xf000)
11685 | ((insn >> 15) & 0x0800)
11686 | ((insn >> 4) & 0x0700)
11687 | (insn & 0x00ff);
39623e12 11688 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11689 }
92f5d02b 11690
b6895b4f 11691 value += signed_addend;
b6895b4f
PB		 11692
11693 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11694 value -= (input_section->output_section->vma
11695 + input_section->output_offset + rel->r_offset);
11696
92f5d02b 11697 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11698 return bfd_reloc_overflow;
92f5d02b 11699
35fc36a8 11700 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11701 value |= 1;
11702
11703 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11704 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11705 value >>= 16;
11706
11707 insn &= 0xfbf08f00;
11708 insn |= (value & 0xf000) << 4;
11709 insn |= (value & 0x0800) << 15;
11710 insn |= (value & 0x0700) << 4;
11711 insn |= (value & 0x00ff);
11712
11713 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11714 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11715 }
11716 return bfd_reloc_ok;
11717
4962c51a
MS		 11718 case R_ARM_ALU_PC_G0_NC:
11719 case R_ARM_ALU_PC_G1_NC:
11720 case R_ARM_ALU_PC_G0:
11721 case R_ARM_ALU_PC_G1:
11722 case R_ARM_ALU_PC_G2:
11723 case R_ARM_ALU_SB_G0_NC:
11724 case R_ARM_ALU_SB_G1_NC:
11725 case R_ARM_ALU_SB_G0:
11726 case R_ARM_ALU_SB_G1:
11727 case R_ARM_ALU_SB_G2:
11728 {
11729 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11730 bfd_vma pc = input_section->output_section->vma
4962c51a 11731 + input_section->output_offset + rel->r_offset;
31a91d61 11732 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11733 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11734 bfd_vma residual;
11735 bfd_vma g_n;
4962c51a 11736 bfd_signed_vma signed_value;
99059e56
RM		 11737 int group = 0;
11738
11739 /* Determine which group of bits to select. */
11740 switch (r_type)
11741 {
11742 case R_ARM_ALU_PC_G0_NC:
11743 case R_ARM_ALU_PC_G0:
11744 case R_ARM_ALU_SB_G0_NC:
11745 case R_ARM_ALU_SB_G0:
11746 group = 0;
11747 break;
11748
11749 case R_ARM_ALU_PC_G1_NC:
11750 case R_ARM_ALU_PC_G1:
11751 case R_ARM_ALU_SB_G1_NC:
11752 case R_ARM_ALU_SB_G1:
11753 group = 1;
11754 break;
11755
11756 case R_ARM_ALU_PC_G2:
11757 case R_ARM_ALU_SB_G2:
11758 group = 2;
11759 break;
11760
11761 default:
11762 abort ();
11763 }
11764
11765 /* If REL, extract the addend from the insn. If RELA, it will
11766 have already been fetched for us. */
4962c51a 11767 if (globals->use_rel)
99059e56
RM		 11768 {
11769 int negative;
11770 bfd_vma constant = insn & 0xff;
11771 bfd_vma rotation = (insn & 0xf00) >> 8;
11772
11773 if (rotation == 0)
11774 signed_addend = constant;
11775 else
11776 {
11777 /* Compensate for the fact that in the instruction, the
11778 rotation is stored in multiples of 2 bits. */
11779 rotation *= 2;
11780
11781 /* Rotate "constant" right by "rotation" bits. */
11782 signed_addend = (constant >> rotation) |
11783 (constant << (8 * sizeof (bfd_vma) - rotation));
11784 }
11785
11786 /* Determine if the instruction is an ADD or a SUB.
11787 (For REL, this determines the sign of the addend.) */
11788 negative = identify_add_or_sub (insn);
11789 if (negative == 0)
11790 {
4eca0228 11791 _bfd_error_handler
695344c0 11792 /* xgettext:c-format */
d42c267e
AM		 11793 (_("%B(%A+%#Lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11794 input_bfd, input_section, rel->r_offset);
99059e56
RM		 11795 return bfd_reloc_overflow;
11796 }
11797
11798 signed_addend *= negative;
11799 }
4962c51a
MS		 11800
11801 /* Compute the value (X) to go in the place. */
99059e56
RM		 11802 if (r_type == R_ARM_ALU_PC_G0_NC
11803 || r_type == R_ARM_ALU_PC_G1_NC
11804 || r_type == R_ARM_ALU_PC_G0
11805 || r_type == R_ARM_ALU_PC_G1
11806 || r_type == R_ARM_ALU_PC_G2)
11807 /* PC relative. */
11808 signed_value = value - pc + signed_addend;
11809 else
11810 /* Section base relative. */
11811 signed_value = value - sb + signed_addend;
11812
11813 /* If the target symbol is a Thumb function, then set the
11814 Thumb bit in the address. */
35fc36a8 11815 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11816 signed_value |= 1;
11817
99059e56
RM		 11818 /* Calculate the value of the relevant G_n, in encoded
11819 constant-with-rotation format. */
b6518b38
NC		 11820 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11821 group, &residual);
99059e56
RM		 11822
11823 /* Check for overflow if required. */
11824 if ((r_type == R_ARM_ALU_PC_G0
11825 || r_type == R_ARM_ALU_PC_G1
11826 || r_type == R_ARM_ALU_PC_G2
11827 || r_type == R_ARM_ALU_SB_G0
11828 || r_type == R_ARM_ALU_SB_G1
11829 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11830 {
4eca0228 11831 _bfd_error_handler
695344c0 11832 /* xgettext:c-format */
d42c267e
AM		 11833 (_("%B(%A+%#Lx): Overflow whilst splitting %#Lx for group relocation %s"),
11834 input_bfd, input_section, rel->r_offset,
11835 signed_value < 0 ? -signed_value : signed_value, howto->name);
99059e56
RM		 11836 return bfd_reloc_overflow;
11837 }
11838
11839 /* Mask out the value and the ADD/SUB part of the opcode; take care
11840 not to destroy the S bit. */
11841 insn &= 0xff1ff000;
11842
11843 /* Set the opcode according to whether the value to go in the
11844 place is negative. */
11845 if (signed_value < 0)
11846 insn |= 1 << 22;
11847 else
11848 insn |= 1 << 23;
11849
11850 /* Encode the offset. */
11851 insn |= g_n;
4962c51a
MS		 11852
11853 bfd_put_32 (input_bfd, insn, hit_data);
11854 }
11855 return bfd_reloc_ok;
11856
11857 case R_ARM_LDR_PC_G0:
11858 case R_ARM_LDR_PC_G1:
11859 case R_ARM_LDR_PC_G2:
11860 case R_ARM_LDR_SB_G0:
11861 case R_ARM_LDR_SB_G1:
11862 case R_ARM_LDR_SB_G2:
11863 {
11864 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11865 bfd_vma pc = input_section->output_section->vma
4962c51a 11866 + input_section->output_offset + rel->r_offset;
31a91d61 11867 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11868 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11869 bfd_vma residual;
4962c51a 11870 bfd_signed_vma signed_value;
99059e56
RM		 11871 int group = 0;
11872
11873 /* Determine which groups of bits to calculate. */
11874 switch (r_type)
11875 {
11876 case R_ARM_LDR_PC_G0:
11877 case R_ARM_LDR_SB_G0:
11878 group = 0;
11879 break;
11880
11881 case R_ARM_LDR_PC_G1:
11882 case R_ARM_LDR_SB_G1:
11883 group = 1;
11884 break;
11885
11886 case R_ARM_LDR_PC_G2:
11887 case R_ARM_LDR_SB_G2:
11888 group = 2;
11889 break;
11890
11891 default:
11892 abort ();
11893 }
11894
11895 /* If REL, extract the addend from the insn. If RELA, it will
11896 have already been fetched for us. */
4962c51a 11897 if (globals->use_rel)
99059e56
RM		 11898 {
11899 int negative = (insn & (1 << 23)) ? 1 : -1;
11900 signed_addend = negative * (insn & 0xfff);
11901 }
4962c51a
MS		 11902
11903 /* Compute the value (X) to go in the place. */
99059e56
RM		 11904 if (r_type == R_ARM_LDR_PC_G0
11905 || r_type == R_ARM_LDR_PC_G1
11906 || r_type == R_ARM_LDR_PC_G2)
11907 /* PC relative. */
11908 signed_value = value - pc + signed_addend;
11909 else
11910 /* Section base relative. */
11911 signed_value = value - sb + signed_addend;
11912
11913 /* Calculate the value of the relevant G_{n-1} to obtain
11914 the residual at that stage. */
b6518b38
NC		 11915 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11916 group - 1, &residual);
99059e56
RM		 11917
11918 /* Check for overflow. */
11919 if (residual >= 0x1000)
11920 {
4eca0228 11921 _bfd_error_handler
695344c0 11922 /* xgettext:c-format */
d42c267e
AM		 11923 (_("%B(%A+%#Lx): Overflow whilst splitting %#Lx for group relocation %s"),
11924 input_bfd, input_section, rel->r_offset,
11925 signed_value < 0 ? -signed_value : signed_value, howto->name);
99059e56
RM		 11926 return bfd_reloc_overflow;
11927 }
11928
11929 /* Mask out the value and U bit. */
11930 insn &= 0xff7ff000;
11931
11932 /* Set the U bit if the value to go in the place is non-negative. */
11933 if (signed_value >= 0)
11934 insn |= 1 << 23;
11935
11936 /* Encode the offset. */
11937 insn |= residual;
4962c51a
MS		 11938
11939 bfd_put_32 (input_bfd, insn, hit_data);
11940 }
11941 return bfd_reloc_ok;
11942
11943 case R_ARM_LDRS_PC_G0:
11944 case R_ARM_LDRS_PC_G1:
11945 case R_ARM_LDRS_PC_G2:
11946 case R_ARM_LDRS_SB_G0:
11947 case R_ARM_LDRS_SB_G1:
11948 case R_ARM_LDRS_SB_G2:
11949 {
11950 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11951 bfd_vma pc = input_section->output_section->vma
4962c51a 11952 + input_section->output_offset + rel->r_offset;
31a91d61 11953 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11954 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11955 bfd_vma residual;
4962c51a 11956 bfd_signed_vma signed_value;
99059e56
RM		 11957 int group = 0;
11958
11959 /* Determine which groups of bits to calculate. */
11960 switch (r_type)
11961 {
11962 case R_ARM_LDRS_PC_G0:
11963 case R_ARM_LDRS_SB_G0:
11964 group = 0;
11965 break;
11966
11967 case R_ARM_LDRS_PC_G1:
11968 case R_ARM_LDRS_SB_G1:
11969 group = 1;
11970 break;
11971
11972 case R_ARM_LDRS_PC_G2:
11973 case R_ARM_LDRS_SB_G2:
11974 group = 2;
11975 break;
11976
11977 default:
11978 abort ();
11979 }
11980
11981 /* If REL, extract the addend from the insn. If RELA, it will
11982 have already been fetched for us. */
4962c51a 11983 if (globals->use_rel)
99059e56
RM		 11984 {
11985 int negative = (insn & (1 << 23)) ? 1 : -1;
11986 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11987 }
4962c51a
MS		 11988
11989 /* Compute the value (X) to go in the place. */
99059e56
RM		 11990 if (r_type == R_ARM_LDRS_PC_G0
11991 || r_type == R_ARM_LDRS_PC_G1
11992 || r_type == R_ARM_LDRS_PC_G2)
11993 /* PC relative. */
11994 signed_value = value - pc + signed_addend;
11995 else
11996 /* Section base relative. */
11997 signed_value = value - sb + signed_addend;
11998
11999 /* Calculate the value of the relevant G_{n-1} to obtain
12000 the residual at that stage. */
b6518b38
NC		 12001 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12002 group - 1, &residual);
99059e56
RM		 12003
12004 /* Check for overflow. */
12005 if (residual >= 0x100)
12006 {
4eca0228 12007 _bfd_error_handler
695344c0 12008 /* xgettext:c-format */
d42c267e
AM		 12009 (_("%B(%A+%#Lx): Overflow whilst splitting %#Lx for group relocation %s"),
12010 input_bfd, input_section, rel->r_offset,
12011 signed_value < 0 ? -signed_value : signed_value, howto->name);
99059e56
RM		 12012 return bfd_reloc_overflow;
12013 }
12014
12015 /* Mask out the value and U bit. */
12016 insn &= 0xff7ff0f0;
12017
12018 /* Set the U bit if the value to go in the place is non-negative. */
12019 if (signed_value >= 0)
12020 insn |= 1 << 23;
12021
12022 /* Encode the offset. */
12023 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12024
12025 bfd_put_32 (input_bfd, insn, hit_data);
12026 }
12027 return bfd_reloc_ok;
12028
12029 case R_ARM_LDC_PC_G0:
12030 case R_ARM_LDC_PC_G1:
12031 case R_ARM_LDC_PC_G2:
12032 case R_ARM_LDC_SB_G0:
12033 case R_ARM_LDC_SB_G1:
12034 case R_ARM_LDC_SB_G2:
12035 {
12036 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12037 bfd_vma pc = input_section->output_section->vma
4962c51a 12038 + input_section->output_offset + rel->r_offset;
31a91d61 12039 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12040 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12041 bfd_vma residual;
4962c51a 12042 bfd_signed_vma signed_value;
99059e56
RM		 12043 int group = 0;
12044
12045 /* Determine which groups of bits to calculate. */
12046 switch (r_type)
12047 {
12048 case R_ARM_LDC_PC_G0:
12049 case R_ARM_LDC_SB_G0:
12050 group = 0;
12051 break;
12052
12053 case R_ARM_LDC_PC_G1:
12054 case R_ARM_LDC_SB_G1:
12055 group = 1;
12056 break;
12057
12058 case R_ARM_LDC_PC_G2:
12059 case R_ARM_LDC_SB_G2:
12060 group = 2;
12061 break;
12062
12063 default:
12064 abort ();
12065 }
12066
12067 /* If REL, extract the addend from the insn. If RELA, it will
12068 have already been fetched for us. */
4962c51a 12069 if (globals->use_rel)
99059e56
RM		 12070 {
12071 int negative = (insn & (1 << 23)) ? 1 : -1;
12072 signed_addend = negative * ((insn & 0xff) << 2);
12073 }
4962c51a
MS		 12074
12075 /* Compute the value (X) to go in the place. */
99059e56
RM		 12076 if (r_type == R_ARM_LDC_PC_G0
12077 || r_type == R_ARM_LDC_PC_G1
12078 || r_type == R_ARM_LDC_PC_G2)
12079 /* PC relative. */
12080 signed_value = value - pc + signed_addend;
12081 else
12082 /* Section base relative. */
12083 signed_value = value - sb + signed_addend;
12084
12085 /* Calculate the value of the relevant G_{n-1} to obtain
12086 the residual at that stage. */
b6518b38
NC		 12087 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12088 group - 1, &residual);
99059e56
RM		 12089
12090 /* Check for overflow. (The absolute value to go in the place must be
12091 divisible by four and, after having been divided by four, must
12092 fit in eight bits.) */
12093 if ((residual & 0x3) != 0 || residual >= 0x400)
12094 {
4eca0228 12095 _bfd_error_handler
695344c0 12096 /* xgettext:c-format */
d42c267e
AM		 12097 (_("%B(%A+%#Lx): Overflow whilst splitting %#Lx for group relocation %s"),
12098 input_bfd, input_section, rel->r_offset,
12099 signed_value < 0 ? -signed_value : signed_value, howto->name);
99059e56
RM		 12100 return bfd_reloc_overflow;
12101 }
12102
12103 /* Mask out the value and U bit. */
12104 insn &= 0xff7fff00;
12105
12106 /* Set the U bit if the value to go in the place is non-negative. */
12107 if (signed_value >= 0)
12108 insn |= 1 << 23;
12109
12110 /* Encode the offset. */
12111 insn |= residual >> 2;
4962c51a
MS		 12112
12113 bfd_put_32 (input_bfd, insn, hit_data);
12114 }
12115 return bfd_reloc_ok;
12116
72d98d16
MG		 12117 case R_ARM_THM_ALU_ABS_G0_NC:
12118 case R_ARM_THM_ALU_ABS_G1_NC:
12119 case R_ARM_THM_ALU_ABS_G2_NC:
12120 case R_ARM_THM_ALU_ABS_G3_NC:
12121 {
12122 const int shift_array[4] = {0, 8, 16, 24};
12123 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12124 bfd_vma addr = value;
12125 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12126
12127 /* Compute address. */
12128 if (globals->use_rel)
12129 signed_addend = insn & 0xff;
12130 addr += signed_addend;
12131 if (branch_type == ST_BRANCH_TO_THUMB)
12132 addr |= 1;
12133 /* Clean imm8 insn. */
12134 insn &= 0xff00;
12135 /* And update with correct part of address. */
12136 insn |= (addr >> shift) & 0xff;
12137 /* Update insn. */
12138 bfd_put_16 (input_bfd, insn, hit_data);
12139 }
12140
12141 *unresolved_reloc_p = FALSE;
12142 return bfd_reloc_ok;
12143
252b5132
RH		 12144 default:
12145 return bfd_reloc_notsupported;
12146 }
12147}
12148
98c1d4aa
NC		 12149/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12150static void
57e8b36a
NC		 12151arm_add_to_rel (bfd * abfd,
12152 bfd_byte * address,
12153 reloc_howto_type * howto,
12154 bfd_signed_vma increment)
98c1d4aa 12155{
98c1d4aa
NC		 12156 bfd_signed_vma addend;
12157
bd97cb95
DJ		 12158 if (howto->type == R_ARM_THM_CALL
12159 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12160 {
9a5aca8c
AM		 12161 int upper_insn, lower_insn;
12162 int upper, lower;
98c1d4aa 12163
9a5aca8c
AM		 12164 upper_insn = bfd_get_16 (abfd, address);
12165 lower_insn = bfd_get_16 (abfd, address + 2);
12166 upper = upper_insn & 0x7ff;
12167 lower = lower_insn & 0x7ff;
12168
12169 addend = (upper << 12) | (lower << 1);
ddda4409 12170 addend += increment;
9a5aca8c 12171 addend >>= 1;
98c1d4aa 12172
9a5aca8c
AM		 12173 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12174 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12175
dc810e39
AM		 12176 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12177 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12178 }
12179 else
12180 {
12181 bfd_vma contents;
12182
12183 contents = bfd_get_32 (abfd, address);
12184
12185 /* Get the (signed) value from the instruction. */
12186 addend = contents & howto->src_mask;
12187 if (addend & ((howto->src_mask + 1) >> 1))
12188 {
12189 bfd_signed_vma mask;
12190
12191 mask = -1;
12192 mask &= ~ howto->src_mask;
12193 addend |= mask;
12194 }
12195
12196 /* Add in the increment, (which is a byte value). */
12197 switch (howto->type)
12198 {
12199 default:
12200 addend += increment;
12201 break;
12202
12203 case R_ARM_PC24:
c6596c5e 12204 case R_ARM_PLT32:
5b5bb741
PB		 12205 case R_ARM_CALL:
12206 case R_ARM_JUMP24:
9a5aca8c 12207 addend <<= howto->size;
dc810e39 12208 addend += increment;
9a5aca8c
AM		 12209
12210 /* Should we check for overflow here ? */
12211
12212 /* Drop any undesired bits. */
12213 addend >>= howto->rightshift;
12214 break;
12215 }
12216
12217 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12218
12219 bfd_put_32 (abfd, contents, address);
ddda4409 12220 }
98c1d4aa 12221}
252b5132 12222
ba93b8ac
DJ		 12223#define IS_ARM_TLS_RELOC(R_TYPE) \
12224 ((R_TYPE) == R_ARM_TLS_GD32 \
12225 || (R_TYPE) == R_ARM_TLS_LDO32 \
12226 || (R_TYPE) == R_ARM_TLS_LDM32 \
12227 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12228 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12229 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12230 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12231 || (R_TYPE) == R_ARM_TLS_IE32 \
12232 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12233
12234/* Specific set of relocations for the gnu tls dialect. */
12235#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12236 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12237 || (R_TYPE) == R_ARM_TLS_CALL \
12238 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12239 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12240 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12241
252b5132 12242/* Relocate an ARM ELF section. */
906e58ca 12243
b34976b6 12244static bfd_boolean
57e8b36a
NC		 12245elf32_arm_relocate_section (bfd * output_bfd,
12246 struct bfd_link_info * info,
12247 bfd * input_bfd,
12248 asection * input_section,
12249 bfd_byte * contents,
12250 Elf_Internal_Rela * relocs,
12251 Elf_Internal_Sym * local_syms,
12252 asection ** local_sections)
252b5132 12253{
b34976b6
AM		 12254 Elf_Internal_Shdr *symtab_hdr;
12255 struct elf_link_hash_entry **sym_hashes;
12256 Elf_Internal_Rela *rel;
12257 Elf_Internal_Rela *relend;
12258 const char *name;
b32d3aa2 12259 struct elf32_arm_link_hash_table * globals;
252b5132 12260
4e7fd91e 12261 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12262 if (globals == NULL)
12263 return FALSE;
b491616a 12264
0ffa91dd 12265 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12266 sym_hashes = elf_sym_hashes (input_bfd);
12267
12268 rel = relocs;
12269 relend = relocs + input_section->reloc_count;
12270 for (; rel < relend; rel++)
12271 {
ba96a88f
NC		 12272 int r_type;
12273 reloc_howto_type * howto;
12274 unsigned long r_symndx;
12275 Elf_Internal_Sym * sym;
12276 asection * sec;
252b5132 12277 struct elf_link_hash_entry * h;
ba96a88f
NC		 12278 bfd_vma relocation;
12279 bfd_reloc_status_type r;
12280 arelent bfd_reloc;
ba93b8ac 12281 char sym_type;
0945cdfd 12282 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12283 char *error_message = NULL;
f21f3fe0 12284
252b5132 12285 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12286 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12287 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12288
ba96a88f 12289 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12290 || r_type == R_ARM_GNU_VTINHERIT)
12291 continue;
252b5132 12292
47aeb64c
NC		 12293 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
12294
12295 if (howto == NULL)
12296 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 12297
252b5132
RH		 12298 h = NULL;
12299 sym = NULL;
12300 sec = NULL;
9b485d32 12301
252b5132
RH		 12302 if (r_symndx < symtab_hdr->sh_info)
12303 {
12304 sym = local_syms + r_symndx;
ba93b8ac 12305 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12306 sec = local_sections[r_symndx];
ffcb4889
NS		 12307
12308 /* An object file might have a reference to a local
12309 undefined symbol. This is a daft object file, but we
12310 should at least do something about it. V4BX & NONE
12311 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12312 allowed to use the undefined symbol, so allow those.
12313 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12314 if (r_type != R_ARM_V4BX
12315 && r_type != R_ARM_NONE
77b4f08f 12316 && r_symndx != STN_UNDEF
ffcb4889
NS		 12317 && bfd_is_und_section (sec)
12318 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12319 (*info->callbacks->undefined_symbol)
12320 (info, bfd_elf_string_from_elf_section
12321 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12322 input_bfd, input_section,
12323 rel->r_offset, TRUE);
b38cadfb 12324
4e7fd91e 12325 if (globals->use_rel)
f8df10f4 12326 {
4e7fd91e
PB		 12327 relocation = (sec->output_section->vma
12328 + sec->output_offset
12329 + sym->st_value);
0e1862bb 12330 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12331 && (sec->flags & SEC_MERGE)
12332 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12333 {
4e7fd91e
PB		 12334 asection *msec;
12335 bfd_vma addend, value;
12336
39623e12 12337 switch (r_type)
4e7fd91e 12338 {
39623e12
PB		 12339 case R_ARM_MOVW_ABS_NC:
12340 case R_ARM_MOVT_ABS:
12341 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12342 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12343 addend = (addend ^ 0x8000) - 0x8000;
12344 break;
f8df10f4 12345
39623e12
PB		 12346 case R_ARM_THM_MOVW_ABS_NC:
12347 case R_ARM_THM_MOVT_ABS:
12348 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12349 << 16;
12350 value |= bfd_get_16 (input_bfd,
12351 contents + rel->r_offset + 2);
12352 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12353 | ((value & 0x04000000) >> 15);
12354 addend = (addend ^ 0x8000) - 0x8000;
12355 break;
f8df10f4 12356
39623e12
PB		 12357 default:
12358 if (howto->rightshift
12359 || (howto->src_mask & (howto->src_mask + 1)))
12360 {
4eca0228 12361 _bfd_error_handler
695344c0 12362 /* xgettext:c-format */
d42c267e 12363 (_("%B(%A+%#Lx): %s relocation against SEC_MERGE section"),
39623e12 12364 input_bfd, input_section,
d42c267e 12365 rel->r_offset, howto->name);
39623e12
PB		 12366 return FALSE;
12367 }
12368
12369 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12370
12371 /* Get the (signed) value from the instruction. */
12372 addend = value & howto->src_mask;
12373 if (addend & ((howto->src_mask + 1) >> 1))
12374 {
12375 bfd_signed_vma mask;
12376
12377 mask = -1;
12378 mask &= ~ howto->src_mask;
12379 addend |= mask;
12380 }
12381 break;
4e7fd91e 12382 }
39623e12 12383
4e7fd91e
PB		 12384 msec = sec;
12385 addend =
12386 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12387 - relocation;
12388 addend += msec->output_section->vma + msec->output_offset;
39623e12 12389
cc643b88 12390 /* Cases here must match those in the preceding
39623e12
PB		 12391 switch statement. */
12392 switch (r_type)
12393 {
12394 case R_ARM_MOVW_ABS_NC:
12395 case R_ARM_MOVT_ABS:
12396 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12397 | (addend & 0xfff);
12398 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12399 break;
12400
12401 case R_ARM_THM_MOVW_ABS_NC:
12402 case R_ARM_THM_MOVT_ABS:
12403 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12404 | (addend & 0xff) | ((addend & 0x0800) << 15);
12405 bfd_put_16 (input_bfd, value >> 16,
12406 contents + rel->r_offset);
12407 bfd_put_16 (input_bfd, value,
12408 contents + rel->r_offset + 2);
12409 break;
12410
12411 default:
12412 value = (value & ~ howto->dst_mask)
12413 | (addend & howto->dst_mask);
12414 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12415 break;
12416 }
f8df10f4 12417 }
f8df10f4 12418 }
4e7fd91e
PB		 12419 else
12420 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12421 }
12422 else
12423 {
62d887d4 12424 bfd_boolean warned, ignored;
560e09e9 12425
b2a8e766
AM		 12426 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12427 r_symndx, symtab_hdr, sym_hashes,
12428 h, sec, relocation,
62d887d4 12429 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12430
12431 sym_type = h->type;
252b5132
RH		 12432 }
12433
dbaa2011 12434 if (sec != NULL && discarded_section (sec))
e4067dbb 12435 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12436 rel, 1, relend, howto, 0, contents);
ab96bf03 12437
0e1862bb 12438 if (bfd_link_relocatable (info))
ab96bf03
AM		 12439 {
12440 /* This is a relocatable link. We don't have to change
12441 anything, unless the reloc is against a section symbol,
12442 in which case we have to adjust according to where the
12443 section symbol winds up in the output section. */
12444 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12445 {
12446 if (globals->use_rel)
12447 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12448 howto, (bfd_signed_vma) sec->output_offset);
12449 else
12450 rel->r_addend += sec->output_offset;
12451 }
12452 continue;
12453 }
12454
252b5132
RH		 12455 if (h != NULL)
12456 name = h->root.root.string;
12457 else
12458 {
12459 name = (bfd_elf_string_from_elf_section
12460 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12461 if (name == NULL || *name == '\0')
12462 name = bfd_section_name (input_bfd, sec);
12463 }
f21f3fe0 12464
cf35638d 12465 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12466 && r_type != R_ARM_NONE
12467 && (h == NULL
12468 || h->root.type == bfd_link_hash_defined
12469 || h->root.type == bfd_link_hash_defweak)
12470 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12471 {
4eca0228 12472 _bfd_error_handler
ba93b8ac 12473 ((sym_type == STT_TLS
695344c0 12474 /* xgettext:c-format */
d42c267e 12475 ? _("%B(%A+%#Lx): %s used with TLS symbol %s")
695344c0 12476 /* xgettext:c-format */
d42c267e 12477 : _("%B(%A+%#Lx): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 12478 input_bfd,
12479 input_section,
d42c267e 12480 rel->r_offset,
ba93b8ac
DJ		 12481 howto->name,
12482 name);
12483 }
12484
0855e32b 12485 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12486 done, i.e., the relaxation produced the final output we want,
12487 and we won't let anybody mess with it. Also, we have to do
12488 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12489 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12490 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12491 || (IS_ARM_TLS_GNU_RELOC (r_type)
12492 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12493 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12494 & GOT_TLS_GDESC)))
12495 {
12496 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12497 contents, rel, h == NULL);
12498 /* This may have been marked unresolved because it came from
12499 a shared library. But we've just dealt with that. */
12500 unresolved_reloc = 0;
12501 }
12502 else
12503 r = bfd_reloc_continue;
b38cadfb 12504
39d911fc
TP		 12505 if (r == bfd_reloc_continue)
12506 {
12507 unsigned char branch_type =
12508 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12509 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12510
12511 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12512 input_section, contents, rel,
12513 relocation, info, sec, name,
12514 sym_type, branch_type, h,
12515 &unresolved_reloc,
12516 &error_message);
12517 }
0945cdfd
DJ		 12518
12519 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12520 because such sections are not SEC_ALLOC and thus ld.so will
12521 not process them. */
12522 if (unresolved_reloc
99059e56
RM		 12523 && !((input_section->flags & SEC_DEBUGGING) != 0
12524 && h->def_dynamic)
1d5316ab
AM		 12525 && _bfd_elf_section_offset (output_bfd, info, input_section,
12526 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12527 {
4eca0228 12528 _bfd_error_handler
695344c0 12529 /* xgettext:c-format */
d42c267e 12530 (_("%B(%A+%#Lx): unresolvable %s relocation against symbol `%s'"),
843fe662
L		 12531 input_bfd,
12532 input_section,
d42c267e 12533 rel->r_offset,
843fe662
L		 12534 howto->name,
12535 h->root.root.string);
0945cdfd
DJ		 12536 return FALSE;
12537 }
252b5132
RH		 12538
12539 if (r != bfd_reloc_ok)
12540 {
252b5132
RH		 12541 switch (r)
12542 {
12543 case bfd_reloc_overflow:
cf919dfd
PB		 12544 /* If the overflowing reloc was to an undefined symbol,
12545 we have already printed one error message and there
12546 is no point complaining again. */
1a72702b
AM		 12547 if (!h || h->root.type != bfd_link_hash_undefined)
12548 (*info->callbacks->reloc_overflow)
12549 (info, (h ? &h->root : NULL), name, howto->name,
12550 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12551 break;
12552
12553 case bfd_reloc_undefined:
1a72702b
AM		 12554 (*info->callbacks->undefined_symbol)
12555 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12556 break;
12557
12558 case bfd_reloc_outofrange:
f2a9dd69 12559 error_message = _("out of range");
252b5132
RH		 12560 goto common_error;
12561
12562 case bfd_reloc_notsupported:
f2a9dd69 12563 error_message = _("unsupported relocation");
252b5132
RH		 12564 goto common_error;
12565
12566 case bfd_reloc_dangerous:
f2a9dd69 12567 /* error_message should already be set. */
252b5132
RH		 12568 goto common_error;
12569
12570 default:
f2a9dd69 12571 error_message = _("unknown error");
8029a119 12572 /* Fall through. */
252b5132
RH		 12573
12574 common_error:
f2a9dd69 12575 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12576 (*info->callbacks->reloc_dangerous)
12577 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12578 break;
12579 }
12580 }
12581 }
12582
b34976b6 12583 return TRUE;
252b5132
RH		 12584}
12585
91d6fa6a 12586/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12587 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12588 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12589 maintaining that condition). */
12590
12591static void
12592add_unwind_table_edit (arm_unwind_table_edit **head,
12593 arm_unwind_table_edit **tail,
12594 arm_unwind_edit_type type,
12595 asection *linked_section,
91d6fa6a 12596 unsigned int tindex)
2468f9c9 12597{
21d799b5
NC		 12598 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12599 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12600
2468f9c9
PB		 12601 new_edit->type = type;
12602 new_edit->linked_section = linked_section;
91d6fa6a 12603 new_edit->index = tindex;
b38cadfb 12604
91d6fa6a 12605 if (tindex > 0)
2468f9c9
PB		 12606 {
12607 new_edit->next = NULL;
12608
12609 if (*tail)
12610 (*tail)->next = new_edit;
12611
12612 (*tail) = new_edit;
12613
12614 if (!*head)
12615 (*head) = new_edit;
12616 }
12617 else
12618 {
12619 new_edit->next = *head;
12620
12621 if (!*tail)
12622 *tail = new_edit;
12623
12624 *head = new_edit;
12625 }
12626}
12627
12628static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12629
12630/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12631static void
12632adjust_exidx_size(asection *exidx_sec, int adjust)
12633{
12634 asection *out_sec;
12635
12636 if (!exidx_sec->rawsize)
12637 exidx_sec->rawsize = exidx_sec->size;
12638
12639 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12640 out_sec = exidx_sec->output_section;
12641 /* Adjust size of output section. */
12642 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12643}
12644
12645/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12646static void
12647insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12648{
12649 struct _arm_elf_section_data *exidx_arm_data;
12650
12651 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12652 add_unwind_table_edit (
12653 &exidx_arm_data->u.exidx.unwind_edit_list,
12654 &exidx_arm_data->u.exidx.unwind_edit_tail,
12655 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12656
491d01d3
YU		 12657 exidx_arm_data->additional_reloc_count++;
12658
2468f9c9
PB		 12659 adjust_exidx_size(exidx_sec, 8);
12660}
12661
12662/* Scan .ARM.exidx tables, and create a list describing edits which should be
12663 made to those tables, such that:
b38cadfb 12664
2468f9c9
PB		 12665 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12666 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12667 codes which have been inlined into the index).
2468f9c9 12668
85fdf906
AH		 12669 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12670
2468f9c9 12671 The edits are applied when the tables are written
b38cadfb 12672 (in elf32_arm_write_section). */
2468f9c9
PB		 12673
12674bfd_boolean
12675elf32_arm_fix_exidx_coverage (asection **text_section_order,
12676 unsigned int num_text_sections,
85fdf906
AH		 12677 struct bfd_link_info *info,
12678 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12679{
12680 bfd *inp;
12681 unsigned int last_second_word = 0, i;
12682 asection *last_exidx_sec = NULL;
12683 asection *last_text_sec = NULL;
12684 int last_unwind_type = -1;
12685
12686 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12687 text sections. */
c72f2fb2 12688 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12689 {
12690 asection *sec;
b38cadfb 12691
2468f9c9 12692 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12693 {
2468f9c9
PB		 12694 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12695 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12696
dec9d5df 12697 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12698 continue;
b38cadfb 12699
2468f9c9
PB		 12700 if (elf_sec->linked_to)
12701 {
12702 Elf_Internal_Shdr *linked_hdr
99059e56 12703 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12704 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12705 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12706
12707 if (linked_sec_arm_data == NULL)
99059e56 12708 continue;
2468f9c9
PB		 12709
12710 /* Link this .ARM.exidx section back from the text section it
99059e56 12711 describes. */
2468f9c9
PB		 12712 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12713 }
12714 }
12715 }
12716
12717 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12718 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12719 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12720
12721 for (i = 0; i < num_text_sections; i++)
12722 {
12723 asection *sec = text_section_order[i];
12724 asection *exidx_sec;
12725 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12726 struct _arm_elf_section_data *exidx_arm_data;
12727 bfd_byte *contents = NULL;
12728 int deleted_exidx_bytes = 0;
12729 bfd_vma j;
12730 arm_unwind_table_edit *unwind_edit_head = NULL;
12731 arm_unwind_table_edit *unwind_edit_tail = NULL;
12732 Elf_Internal_Shdr *hdr;
12733 bfd *ibfd;
12734
12735 if (arm_data == NULL)
99059e56 12736 continue;
2468f9c9
PB		 12737
12738 exidx_sec = arm_data->u.text.arm_exidx_sec;
12739 if (exidx_sec == NULL)
12740 {
12741 /* Section has no unwind data. */
12742 if (last_unwind_type == 0 || !last_exidx_sec)
12743 continue;
12744
12745 /* Ignore zero sized sections. */
12746 if (sec->size == 0)
12747 continue;
12748
12749 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12750 last_unwind_type = 0;
12751 continue;
12752 }
12753
22a8f80e
PB		 12754 /* Skip /DISCARD/ sections. */
12755 if (bfd_is_abs_section (exidx_sec->output_section))
12756 continue;
12757
2468f9c9
PB		 12758 hdr = &elf_section_data (exidx_sec)->this_hdr;
12759 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12760 continue;
b38cadfb 12761
2468f9c9
PB		 12762 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12763 if (exidx_arm_data == NULL)
99059e56 12764 continue;
b38cadfb 12765
2468f9c9 12766 ibfd = exidx_sec->owner;
b38cadfb 12767
2468f9c9
PB		 12768 if (hdr->contents != NULL)
12769 contents = hdr->contents;
12770 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12771 /* An error? */
12772 continue;
12773
ac06903d
YU		 12774 if (last_unwind_type > 0)
12775 {
12776 unsigned int first_word = bfd_get_32 (ibfd, contents);
12777 /* Add cantunwind if first unwind item does not match section
12778 start. */
12779 if (first_word != sec->vma)
12780 {
12781 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12782 last_unwind_type = 0;
12783 }
12784 }
12785
2468f9c9
PB		 12786 for (j = 0; j < hdr->sh_size; j += 8)
12787 {
12788 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12789 int unwind_type;
12790 int elide = 0;
12791
12792 /* An EXIDX_CANTUNWIND entry. */
12793 if (second_word == 1)
12794 {
12795 if (last_unwind_type == 0)
12796 elide = 1;
12797 unwind_type = 0;
12798 }
12799 /* Inlined unwinding data. Merge if equal to previous. */
12800 else if ((second_word & 0x80000000) != 0)
12801 {
85fdf906
AH		 12802 if (merge_exidx_entries
12803 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12804 elide = 1;
12805 unwind_type = 1;
12806 last_second_word = second_word;
12807 }
12808 /* Normal table entry. In theory we could merge these too,
12809 but duplicate entries are likely to be much less common. */
12810 else
12811 unwind_type = 2;
12812
491d01d3 12813 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12814 {
12815 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12816 DELETE_EXIDX_ENTRY, NULL, j / 8);
12817
12818 deleted_exidx_bytes += 8;
12819 }
12820
12821 last_unwind_type = unwind_type;
12822 }
12823
12824 /* Free contents if we allocated it ourselves. */
12825 if (contents != hdr->contents)
99059e56 12826 free (contents);
2468f9c9
PB		 12827
12828 /* Record edits to be applied later (in elf32_arm_write_section). */
12829 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12830 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12831
2468f9c9
PB		 12832 if (deleted_exidx_bytes > 0)
12833 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12834
12835 last_exidx_sec = exidx_sec;
12836 last_text_sec = sec;
12837 }
12838
12839 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12840 if (!bfd_link_relocatable (info) && last_exidx_sec
12841 && last_unwind_type != 0)
2468f9c9
PB		 12842 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12843
12844 return TRUE;
12845}
12846
3e6b1042
DJ		 12847static bfd_boolean
12848elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12849 bfd *ibfd, const char *name)
12850{
12851 asection *sec, *osec;
12852
3d4d4302 12853 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12854 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12855 return TRUE;
12856
12857 osec = sec->output_section;
12858 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12859 return TRUE;
12860
12861 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12862 sec->output_offset, sec->size))
12863 return FALSE;
12864
12865 return TRUE;
12866}
12867
12868static bfd_boolean
12869elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12870{
12871 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12872 asection *sec, *osec;
3e6b1042 12873
4dfe6ac6
NC		 12874 if (globals == NULL)
12875 return FALSE;
12876
3e6b1042
DJ		 12877 /* Invoke the regular ELF backend linker to do all the work. */
12878 if (!bfd_elf_final_link (abfd, info))
12879 return FALSE;
12880
fe33d2fa
CL		 12881 /* Process stub sections (eg BE8 encoding, ...). */
12882 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12883 unsigned int i;
cdb21a0a
NS		 12884 for (i=0; i<htab->top_id; i++)
12885 {
12886 sec = htab->stub_group[i].stub_sec;
12887 /* Only process it once, in its link_sec slot. */
12888 if (sec && i == htab->stub_group[i].link_sec->id)
12889 {
12890 osec = sec->output_section;
12891 elf32_arm_write_section (abfd, info, sec, sec->contents);
12892 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12893 sec->output_offset, sec->size))
12894 return FALSE;
12895 }
fe33d2fa 12896 }
fe33d2fa 12897
3e6b1042
DJ		 12898 /* Write out any glue sections now that we have created all the
12899 stubs. */
12900 if (globals->bfd_of_glue_owner != NULL)
12901 {
12902 if (! elf32_arm_output_glue_section (info, abfd,
12903 globals->bfd_of_glue_owner,
12904 ARM2THUMB_GLUE_SECTION_NAME))
12905 return FALSE;
12906
12907 if (! elf32_arm_output_glue_section (info, abfd,
12908 globals->bfd_of_glue_owner,
12909 THUMB2ARM_GLUE_SECTION_NAME))
12910 return FALSE;
12911
12912 if (! elf32_arm_output_glue_section (info, abfd,
12913 globals->bfd_of_glue_owner,
12914 VFP11_ERRATUM_VENEER_SECTION_NAME))
12915 return FALSE;
12916
a504d23a
LA		 12917 if (! elf32_arm_output_glue_section (info, abfd,
12918 globals->bfd_of_glue_owner,
12919 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12920 return FALSE;
12921
3e6b1042
DJ		 12922 if (! elf32_arm_output_glue_section (info, abfd,
12923 globals->bfd_of_glue_owner,
12924 ARM_BX_GLUE_SECTION_NAME))
12925 return FALSE;
12926 }
12927
12928 return TRUE;
12929}
12930
5968a7b8
NC		 12931/* Return a best guess for the machine number based on the attributes. */
12932
12933static unsigned int
12934bfd_arm_get_mach_from_attributes (bfd * abfd)
12935{
12936 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12937
12938 switch (arch)
12939 {
12940 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12941 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12942 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12943
12944 case TAG_CPU_ARCH_V5TE:
12945 {
12946 char * name;
12947
12948 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12949 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12950
12951 if (name)
12952 {
12953 if (strcmp (name, "IWMMXT2") == 0)
12954 return bfd_mach_arm_iWMMXt2;
12955
12956 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12957 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12958
12959 if (strcmp (name, "XSCALE") == 0)
12960 {
12961 int wmmx;
12962
12963 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12964 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12965 switch (wmmx)
12966 {
12967 case 1: return bfd_mach_arm_iWMMXt;
12968 case 2: return bfd_mach_arm_iWMMXt2;
12969 default: return bfd_mach_arm_XScale;
12970 }
12971 }
5968a7b8
NC		 12972 }
12973
12974 return bfd_mach_arm_5TE;
12975 }
12976
12977 default:
12978 return bfd_mach_arm_unknown;
12979 }
12980}
12981
c178919b
NC		 12982/* Set the right machine number. */
12983
12984static bfd_boolean
57e8b36a 12985elf32_arm_object_p (bfd *abfd)
c178919b 12986{
5a6c6817 12987 unsigned int mach;
57e8b36a 12988
5a6c6817 12989 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12990
5968a7b8
NC		 12991 if (mach == bfd_mach_arm_unknown)
12992 {
12993 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12994 mach = bfd_mach_arm_ep9312;
12995 else
12996 mach = bfd_arm_get_mach_from_attributes (abfd);
12997 }
c178919b 12998
5968a7b8 12999 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13000 return TRUE;
13001}
13002
fc830a83 13003/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13004
b34976b6 13005static bfd_boolean
57e8b36a 13006elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13007{
13008 if (elf_flags_init (abfd)
13009 && elf_elfheader (abfd)->e_flags != flags)
13010 {
fc830a83
NC		 13011 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13012 {
fd2ec330 13013 if (flags & EF_ARM_INTERWORK)
4eca0228 13014 _bfd_error_handler
d003868e
AM		 13015 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13016 abfd);
fc830a83 13017 else
d003868e
AM		 13018 _bfd_error_handler
13019 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13020 abfd);
fc830a83 13021 }
252b5132
RH		 13022 }
13023 else
13024 {
13025 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13026 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13027 }
13028
b34976b6 13029 return TRUE;
252b5132
RH		 13030}
13031
fc830a83 13032/* Copy backend specific data from one object module to another. */
9b485d32 13033
b34976b6 13034static bfd_boolean
57e8b36a 13035elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13036{
13037 flagword in_flags;
13038 flagword out_flags;
13039
0ffa91dd 13040 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13041 return TRUE;
252b5132 13042
fc830a83 13043 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13044 out_flags = elf_elfheader (obfd)->e_flags;
13045
fc830a83
NC		 13046 if (elf_flags_init (obfd)
13047 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13048 && in_flags != out_flags)
252b5132 13049 {
252b5132 13050 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13051 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13052 return FALSE;
252b5132
RH		 13053
13054 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13055 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13056 return FALSE;
252b5132
RH		 13057
13058 /* If the src and dest have different interworking flags
99059e56 13059 then turn off the interworking bit. */
fd2ec330 13060 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13061 {
fd2ec330 13062 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13063 _bfd_error_handler
13064 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13065 obfd, ibfd);
252b5132 13066
fd2ec330 13067 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13068 }
1006ba19
PB		 13069
13070 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13071 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13072 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13073 }
13074
13075 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13076 elf_flags_init (obfd) = TRUE;
252b5132 13077
e2349352 13078 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13079}
13080
13081/* Values for Tag_ABI_PCS_R9_use. */
13082enum
13083{
13084 AEABI_R9_V6,
13085 AEABI_R9_SB,
13086 AEABI_R9_TLS,
13087 AEABI_R9_unused
13088};
13089
13090/* Values for Tag_ABI_PCS_RW_data. */
13091enum
13092{
13093 AEABI_PCS_RW_data_absolute,
13094 AEABI_PCS_RW_data_PCrel,
13095 AEABI_PCS_RW_data_SBrel,
13096 AEABI_PCS_RW_data_unused
13097};
13098
13099/* Values for Tag_ABI_enum_size. */
13100enum
13101{
13102 AEABI_enum_unused,
13103 AEABI_enum_short,
13104 AEABI_enum_wide,
13105 AEABI_enum_forced_wide
13106};
13107
104d59d1
JM		 13108/* Determine whether an object attribute tag takes an integer, a
13109 string or both. */
906e58ca 13110
104d59d1
JM		 13111static int
13112elf32_arm_obj_attrs_arg_type (int tag)
13113{
13114 if (tag == Tag_compatibility)
3483fe2e 13115 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13116 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13117 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13118 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13119 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13120 else if (tag < 32)
3483fe2e 13121 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13122 else
3483fe2e 13123 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13124}
13125
5aa6ff7c
AS		 13126/* The ABI defines that Tag_conformance should be emitted first, and that
13127 Tag_nodefaults should be second (if either is defined). This sets those
13128 two positions, and bumps up the position of all the remaining tags to
13129 compensate. */
13130static int
13131elf32_arm_obj_attrs_order (int num)
13132{
3de4a297 13133 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13134 return Tag_conformance;
3de4a297 13135 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13136 return Tag_nodefaults;
13137 if ((num - 2) < Tag_nodefaults)
13138 return num - 2;
13139 if ((num - 1) < Tag_conformance)
13140 return num - 1;
13141 return num;
13142}
13143
e8b36cd1
JM		 13144/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13145static bfd_boolean
13146elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13147{
13148 if ((tag & 127) < 64)
13149 {
13150 _bfd_error_handler
13151 (_("%B: Unknown mandatory EABI object attribute %d"),
13152 abfd, tag);
13153 bfd_set_error (bfd_error_bad_value);
13154 return FALSE;
13155 }
13156 else
13157 {
13158 _bfd_error_handler
13159 (_("Warning: %B: Unknown EABI object attribute %d"),
13160 abfd, tag);
13161 return TRUE;
13162 }
13163}
13164
91e22acd
AS		 13165/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13166 Returns -1 if no architecture could be read. */
13167
13168static int
13169get_secondary_compatible_arch (bfd *abfd)
13170{
13171 obj_attribute *attr =
13172 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13173
13174 /* Note: the tag and its argument below are uleb128 values, though
13175 currently-defined values fit in one byte for each. */
13176 if (attr->s
13177 && attr->s[0] == Tag_CPU_arch
13178 && (attr->s[1] & 128) != 128
13179 && attr->s[2] == 0)
13180 return attr->s[1];
13181
13182 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13183 return -1;
13184}
13185
13186/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13187 The tag is removed if ARCH is -1. */
13188
8e79c3df 13189static void
91e22acd 13190set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13191{
91e22acd
AS		 13192 obj_attribute *attr =
13193 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13194
91e22acd
AS		 13195 if (arch == -1)
13196 {
13197 attr->s = NULL;
13198 return;
8e79c3df 13199 }
91e22acd
AS		 13200
13201 /* Note: the tag and its argument below are uleb128 values, though
13202 currently-defined values fit in one byte for each. */
13203 if (!attr->s)
21d799b5 13204 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13205 attr->s[0] = Tag_CPU_arch;
13206 attr->s[1] = arch;
13207 attr->s[2] = '\0';
8e79c3df
CM		 13208}
13209
91e22acd
AS		 13210/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13211 into account. */
13212
13213static int
13214tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13215 int newtag, int secondary_compat)
8e79c3df 13216{
91e22acd
AS		 13217#define T(X) TAG_CPU_ARCH_##X
13218 int tagl, tagh, result;
13219 const int v6t2[] =
13220 {
13221 T(V6T2), /* PRE_V4. */
13222 T(V6T2), /* V4. */
13223 T(V6T2), /* V4T. */
13224 T(V6T2), /* V5T. */
13225 T(V6T2), /* V5TE. */
13226 T(V6T2), /* V5TEJ. */
13227 T(V6T2), /* V6. */
13228 T(V7), /* V6KZ. */
13229 T(V6T2) /* V6T2. */
13230 };
13231 const int v6k[] =
13232 {
13233 T(V6K), /* PRE_V4. */
13234 T(V6K), /* V4. */
13235 T(V6K), /* V4T. */
13236 T(V6K), /* V5T. */
13237 T(V6K), /* V5TE. */
13238 T(V6K), /* V5TEJ. */
13239 T(V6K), /* V6. */
13240 T(V6KZ), /* V6KZ. */
13241 T(V7), /* V6T2. */
13242 T(V6K) /* V6K. */
13243 };
13244 const int v7[] =
13245 {
13246 T(V7), /* PRE_V4. */
13247 T(V7), /* V4. */
13248 T(V7), /* V4T. */
13249 T(V7), /* V5T. */
13250 T(V7), /* V5TE. */
13251 T(V7), /* V5TEJ. */
13252 T(V7), /* V6. */
13253 T(V7), /* V6KZ. */
13254 T(V7), /* V6T2. */
13255 T(V7), /* V6K. */
13256 T(V7) /* V7. */
13257 };
13258 const int v6_m[] =
13259 {
13260 -1, /* PRE_V4. */
13261 -1, /* V4. */
13262 T(V6K), /* V4T. */
13263 T(V6K), /* V5T. */
13264 T(V6K), /* V5TE. */
13265 T(V6K), /* V5TEJ. */
13266 T(V6K), /* V6. */
13267 T(V6KZ), /* V6KZ. */
13268 T(V7), /* V6T2. */
13269 T(V6K), /* V6K. */
13270 T(V7), /* V7. */
13271 T(V6_M) /* V6_M. */
13272 };
13273 const int v6s_m[] =
13274 {
13275 -1, /* PRE_V4. */
13276 -1, /* V4. */
13277 T(V6K), /* V4T. */
13278 T(V6K), /* V5T. */
13279 T(V6K), /* V5TE. */
13280 T(V6K), /* V5TEJ. */
13281 T(V6K), /* V6. */
13282 T(V6KZ), /* V6KZ. */
13283 T(V7), /* V6T2. */
13284 T(V6K), /* V6K. */
13285 T(V7), /* V7. */
13286 T(V6S_M), /* V6_M. */
13287 T(V6S_M) /* V6S_M. */
13288 };
9e3c6df6
PB		 13289 const int v7e_m[] =
13290 {
13291 -1, /* PRE_V4. */
13292 -1, /* V4. */
13293 T(V7E_M), /* V4T. */
13294 T(V7E_M), /* V5T. */
13295 T(V7E_M), /* V5TE. */
13296 T(V7E_M), /* V5TEJ. */
13297 T(V7E_M), /* V6. */
13298 T(V7E_M), /* V6KZ. */
13299 T(V7E_M), /* V6T2. */
13300 T(V7E_M), /* V6K. */
13301 T(V7E_M), /* V7. */
13302 T(V7E_M), /* V6_M. */
13303 T(V7E_M), /* V6S_M. */
13304 T(V7E_M) /* V7E_M. */
13305 };
bca38921
MGD		 13306 const int v8[] =
13307 {
13308 T(V8), /* PRE_V4. */
13309 T(V8), /* V4. */
13310 T(V8), /* V4T. */
13311 T(V8), /* V5T. */
13312 T(V8), /* V5TE. */
13313 T(V8), /* V5TEJ. */
13314 T(V8), /* V6. */
13315 T(V8), /* V6KZ. */
13316 T(V8), /* V6T2. */
13317 T(V8), /* V6K. */
13318 T(V8), /* V7. */
13319 T(V8), /* V6_M. */
13320 T(V8), /* V6S_M. */
13321 T(V8), /* V7E_M. */
13322 T(V8) /* V8. */
13323 };
bff0500d
TP		 13324 const int v8r[] =
13325 {
13326 T(V8R), /* PRE_V4. */
13327 T(V8R), /* V4. */
13328 T(V8R), /* V4T. */
13329 T(V8R), /* V5T. */
13330 T(V8R), /* V5TE. */
13331 T(V8R), /* V5TEJ. */
13332 T(V8R), /* V6. */
13333 T(V8R), /* V6KZ. */
13334 T(V8R), /* V6T2. */
13335 T(V8R), /* V6K. */
13336 T(V8R), /* V7. */
13337 T(V8R), /* V6_M. */
13338 T(V8R), /* V6S_M. */
13339 T(V8R), /* V7E_M. */
13340 T(V8), /* V8. */
13341 T(V8R), /* V8R. */
13342 };
2fd158eb
TP		 13343 const int v8m_baseline[] =
13344 {
13345 -1, /* PRE_V4. */
13346 -1, /* V4. */
13347 -1, /* V4T. */
13348 -1, /* V5T. */
13349 -1, /* V5TE. */
13350 -1, /* V5TEJ. */
13351 -1, /* V6. */
13352 -1, /* V6KZ. */
13353 -1, /* V6T2. */
13354 -1, /* V6K. */
13355 -1, /* V7. */
13356 T(V8M_BASE), /* V6_M. */
13357 T(V8M_BASE), /* V6S_M. */
13358 -1, /* V7E_M. */
13359 -1, /* V8. */
bff0500d 13360 -1, /* V8R. */
2fd158eb
TP		 13361 T(V8M_BASE) /* V8-M BASELINE. */
13362 };
13363 const int v8m_mainline[] =
13364 {
13365 -1, /* PRE_V4. */
13366 -1, /* V4. */
13367 -1, /* V4T. */
13368 -1, /* V5T. */
13369 -1, /* V5TE. */
13370 -1, /* V5TEJ. */
13371 -1, /* V6. */
13372 -1, /* V6KZ. */
13373 -1, /* V6T2. */
13374 -1, /* V6K. */
13375 T(V8M_MAIN), /* V7. */
13376 T(V8M_MAIN), /* V6_M. */
13377 T(V8M_MAIN), /* V6S_M. */
13378 T(V8M_MAIN), /* V7E_M. */
13379 -1, /* V8. */
bff0500d 13380 -1, /* V8R. */
2fd158eb
TP		 13381 T(V8M_MAIN), /* V8-M BASELINE. */
13382 T(V8M_MAIN) /* V8-M MAINLINE. */
13383 };
91e22acd
AS		 13384 const int v4t_plus_v6_m[] =
13385 {
13386 -1, /* PRE_V4. */
13387 -1, /* V4. */
13388 T(V4T), /* V4T. */
13389 T(V5T), /* V5T. */
13390 T(V5TE), /* V5TE. */
13391 T(V5TEJ), /* V5TEJ. */
13392 T(V6), /* V6. */
13393 T(V6KZ), /* V6KZ. */
13394 T(V6T2), /* V6T2. */
13395 T(V6K), /* V6K. */
13396 T(V7), /* V7. */
13397 T(V6_M), /* V6_M. */
13398 T(V6S_M), /* V6S_M. */
9e3c6df6 13399 T(V7E_M), /* V7E_M. */
bca38921 13400 T(V8), /* V8. */
bff0500d 13401 -1, /* V8R. */
2fd158eb
TP		 13402 T(V8M_BASE), /* V8-M BASELINE. */
13403 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13404 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13405 };
13406 const int *comb[] =
13407 {
13408 v6t2,
13409 v6k,
13410 v7,
13411 v6_m,
13412 v6s_m,
9e3c6df6 13413 v7e_m,
bca38921 13414 v8,
bff0500d 13415 v8r,
2fd158eb
TP		 13416 v8m_baseline,
13417 v8m_mainline,
91e22acd
AS		 13418 /* Pseudo-architecture. */
13419 v4t_plus_v6_m
13420 };
13421
13422 /* Check we've not got a higher architecture than we know about. */
13423
9e3c6df6 13424 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13425 {
3895f852 13426 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13427 return -1;
13428 }
13429
13430 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13431
13432 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13433 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13434 oldtag = T(V4T_PLUS_V6_M);
13435
13436 /* And override the new tag if we have a Tag_also_compatible_with on the
13437 input. */
13438
13439 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13440 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13441 newtag = T(V4T_PLUS_V6_M);
13442
13443 tagl = (oldtag < newtag) ? oldtag : newtag;
13444 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13445
13446 /* Architectures before V6KZ add features monotonically. */
13447 if (tagh <= TAG_CPU_ARCH_V6KZ)
13448 return result;
13449
4ed7ed8d 13450 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13451
13452 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13453 as the canonical version. */
13454 if (result == T(V4T_PLUS_V6_M))
13455 {
13456 result = T(V4T);
13457 *secondary_compat_out = T(V6_M);
13458 }
13459 else
13460 *secondary_compat_out = -1;
13461
13462 if (result == -1)
13463 {
3895f852 13464 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13465 ibfd, oldtag, newtag);
13466 return -1;
13467 }
13468
13469 return result;
13470#undef T
8e79c3df
CM		 13471}
13472
ac56ee8f
MGD		 13473/* Query attributes object to see if integer divide instructions may be
13474 present in an object. */
13475static bfd_boolean
13476elf32_arm_attributes_accept_div (const obj_attribute *attr)
13477{
13478 int arch = attr[Tag_CPU_arch].i;
13479 int profile = attr[Tag_CPU_arch_profile].i;
13480
13481 switch (attr[Tag_DIV_use].i)
13482 {
13483 case 0:
13484 /* Integer divide allowed if instruction contained in archetecture. */
13485 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13486 return TRUE;
13487 else if (arch >= TAG_CPU_ARCH_V7E_M)
13488 return TRUE;
13489 else
13490 return FALSE;
13491
13492 case 1:
13493 /* Integer divide explicitly prohibited. */
13494 return FALSE;
13495
13496 default:
13497 /* Unrecognised case - treat as allowing divide everywhere. */
13498 case 2:
13499 /* Integer divide allowed in ARM state. */
13500 return TRUE;
13501 }
13502}
13503
13504/* Query attributes object to see if integer divide instructions are
13505 forbidden to be in the object. This is not the inverse of
13506 elf32_arm_attributes_accept_div. */
13507static bfd_boolean
13508elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13509{
13510 return attr[Tag_DIV_use].i == 1;
13511}
13512
ee065d83
PB		 13513/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13514 are conflicting attributes. */
906e58ca 13515
ee065d83 13516static bfd_boolean
50e03d47 13517elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13518{
50e03d47 13519 bfd *obfd = info->output_bfd;
104d59d1
JM		 13520 obj_attribute *in_attr;
13521 obj_attribute *out_attr;
ee065d83
PB		 13522 /* Some tags have 0 = don't care, 1 = strong requirement,
13523 2 = weak requirement. */
91e22acd 13524 static const int order_021[3] = {0, 2, 1};
ee065d83 13525 int i;
91e22acd 13526 bfd_boolean result = TRUE;
9274e9de 13527 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13528
3e6b1042
DJ		 13529 /* Skip the linker stubs file. This preserves previous behavior
13530 of accepting unknown attributes in the first input file - but
13531 is that a bug? */
13532 if (ibfd->flags & BFD_LINKER_CREATED)
13533 return TRUE;
13534
9274e9de
TG		 13535 /* Skip any input that hasn't attribute section.
13536 This enables to link object files without attribute section with
13537 any others. */
13538 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13539 return TRUE;
13540
104d59d1 13541 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13542 {
13543 /* This is the first object. Copy the attributes. */
104d59d1 13544 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13545
cd21e546
MGD		 13546 out_attr = elf_known_obj_attributes_proc (obfd);
13547
004ae526
PB		 13548 /* Use the Tag_null value to indicate the attributes have been
13549 initialized. */
cd21e546 13550 out_attr[0].i = 1;
004ae526 13551
cd21e546
MGD		 13552 /* We do not output objects with Tag_MPextension_use_legacy - we move
13553 the attribute's value to Tag_MPextension_use. */
13554 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13555 {
13556 if (out_attr[Tag_MPextension_use].i != 0
13557 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13558 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13559 {
13560 _bfd_error_handler
13561 (_("Error: %B has both the current and legacy "
13562 "Tag_MPextension_use attributes"), ibfd);
13563 result = FALSE;
13564 }
13565
13566 out_attr[Tag_MPextension_use] =
13567 out_attr[Tag_MPextension_use_legacy];
13568 out_attr[Tag_MPextension_use_legacy].type = 0;
13569 out_attr[Tag_MPextension_use_legacy].i = 0;
13570 }
13571
13572 return result;
ee065d83
PB		 13573 }
13574
104d59d1
JM		 13575 in_attr = elf_known_obj_attributes_proc (ibfd);
13576 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13577 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13578 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13579 {
5c294fee
TG		 13580 /* Ignore mismatches if the object doesn't use floating point or is
13581 floating point ABI independent. */
13582 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13583 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13584 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13585 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13586 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13587 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13588 {
13589 _bfd_error_handler
3895f852 13590 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13591 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13592 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13593 result = FALSE;
ee065d83
PB		 13594 }
13595 }
13596
3de4a297 13597 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13598 {
13599 /* Merge this attribute with existing attributes. */
13600 switch (i)
13601 {
13602 case Tag_CPU_raw_name:
13603 case Tag_CPU_name:
6a631e86 13604 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13605 break;
13606
13607 case Tag_ABI_optimization_goals:
13608 case Tag_ABI_FP_optimization_goals:
13609 /* Use the first value seen. */
13610 break;
13611
13612 case Tag_CPU_arch:
91e22acd
AS		 13613 {
13614 int secondary_compat = -1, secondary_compat_out = -1;
13615 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13616 int arch_attr;
13617 static const char *name_table[] =
13618 {
91e22acd
AS		 13619 /* These aren't real CPU names, but we can't guess
13620 that from the architecture version alone. */
13621 "Pre v4",
13622 "ARM v4",
13623 "ARM v4T",
13624 "ARM v5T",
13625 "ARM v5TE",
13626 "ARM v5TEJ",
13627 "ARM v6",
13628 "ARM v6KZ",
13629 "ARM v6T2",
13630 "ARM v6K",
13631 "ARM v7",
13632 "ARM v6-M",
bca38921 13633 "ARM v6S-M",
2fd158eb
TP		 13634 "ARM v8",
13635 "",
13636 "ARM v8-M.baseline",
13637 "ARM v8-M.mainline",
91e22acd
AS		 13638 };
13639
13640 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13641 secondary_compat = get_secondary_compatible_arch (ibfd);
13642 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13643 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13644 &secondary_compat_out,
13645 in_attr[i].i,
13646 secondary_compat);
13647
13648 /* Return with error if failed to merge. */
13649 if (arch_attr == -1)
13650 return FALSE;
13651
13652 out_attr[i].i = arch_attr;
13653
91e22acd
AS		 13654 set_secondary_compatible_arch (obfd, secondary_compat_out);
13655
13656 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13657 if (out_attr[i].i == saved_out_attr)
13658 ; /* Leave the names alone. */
13659 else if (out_attr[i].i == in_attr[i].i)
13660 {
13661 /* The output architecture has been changed to match the
13662 input architecture. Use the input names. */
13663 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13664 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13665 : NULL;
13666 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13667 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13668 : NULL;
13669 }
13670 else
13671 {
13672 out_attr[Tag_CPU_name].s = NULL;
13673 out_attr[Tag_CPU_raw_name].s = NULL;
13674 }
13675
13676 /* If we still don't have a value for Tag_CPU_name,
13677 make one up now. Tag_CPU_raw_name remains blank. */
13678 if (out_attr[Tag_CPU_name].s == NULL
13679 && out_attr[i].i < ARRAY_SIZE (name_table))
13680 out_attr[Tag_CPU_name].s =
13681 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13682 }
13683 break;
13684
ee065d83
PB		 13685 case Tag_ARM_ISA_use:
13686 case Tag_THUMB_ISA_use:
ee065d83 13687 case Tag_WMMX_arch:
91e22acd
AS		 13688 case Tag_Advanced_SIMD_arch:
13689 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13690 case Tag_ABI_FP_rounding:
ee065d83
PB		 13691 case Tag_ABI_FP_exceptions:
13692 case Tag_ABI_FP_user_exceptions:
13693 case Tag_ABI_FP_number_model:
75375b3e 13694 case Tag_FP_HP_extension:
91e22acd
AS		 13695 case Tag_CPU_unaligned_access:
13696 case Tag_T2EE_use:
91e22acd 13697 case Tag_MPextension_use:
ee065d83
PB		 13698 /* Use the largest value specified. */
13699 if (in_attr[i].i > out_attr[i].i)
13700 out_attr[i].i = in_attr[i].i;
13701 break;
13702
75375b3e 13703 case Tag_ABI_align_preserved:
91e22acd
AS		 13704 case Tag_ABI_PCS_RO_data:
13705 /* Use the smallest value specified. */
13706 if (in_attr[i].i < out_attr[i].i)
13707 out_attr[i].i = in_attr[i].i;
13708 break;
13709
75375b3e 13710 case Tag_ABI_align_needed:
91e22acd 13711 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13712 && (in_attr[Tag_ABI_align_preserved].i == 0
13713 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13714 {
91e22acd
AS		 13715 /* This error message should be enabled once all non-conformant
13716 binaries in the toolchain have had the attributes set
13717 properly.
ee065d83 13718 _bfd_error_handler
3895f852 13719 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13720 obfd, ibfd);
13721 result = FALSE; */
ee065d83 13722 }
91e22acd
AS		 13723 /* Fall through. */
13724 case Tag_ABI_FP_denormal:
13725 case Tag_ABI_PCS_GOT_use:
13726 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13727 value if greater than 2 (for future-proofing). */
13728 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13729 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13730 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13731 out_attr[i].i = in_attr[i].i;
13732 break;
91e22acd 13733
75375b3e
MGD		 13734 case Tag_Virtualization_use:
13735 /* The virtualization tag effectively stores two bits of
13736 information: the intended use of TrustZone (in bit 0), and the
13737 intended use of Virtualization (in bit 1). */
13738 if (out_attr[i].i == 0)
13739 out_attr[i].i = in_attr[i].i;
13740 else if (in_attr[i].i != 0
13741 && in_attr[i].i != out_attr[i].i)
13742 {
13743 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13744 out_attr[i].i = 3;
13745 else
13746 {
13747 _bfd_error_handler
13748 (_("error: %B: unable to merge virtualization attributes "
13749 "with %B"),
13750 obfd, ibfd);
13751 result = FALSE;
13752 }
13753 }
13754 break;
91e22acd
AS		 13755
13756 case Tag_CPU_arch_profile:
13757 if (out_attr[i].i != in_attr[i].i)
13758 {
13759 /* 0 will merge with anything.
13760 'A' and 'S' merge to 'A'.
13761 'R' and 'S' merge to 'R'.
99059e56 13762 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13763 if (out_attr[i].i == 0
13764 || (out_attr[i].i == 'S'
13765 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13766 out_attr[i].i = in_attr[i].i;
13767 else if (in_attr[i].i == 0
13768 || (in_attr[i].i == 'S'
13769 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13770 ; /* Do nothing. */
91e22acd
AS		 13771 else
13772 {
13773 _bfd_error_handler
3895f852 13774 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13775 ibfd,
13776 in_attr[i].i ? in_attr[i].i : '0',
13777 out_attr[i].i ? out_attr[i].i : '0');
13778 result = FALSE;
13779 }
13780 }
13781 break;
15afaa63
TP		 13782
13783 case Tag_DSP_extension:
13784 /* No need to change output value if any of:
13785 - pre (<=) ARMv5T input architecture (do not have DSP)
13786 - M input profile not ARMv7E-M and do not have DSP. */
13787 if (in_attr[Tag_CPU_arch].i <= 3
13788 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13789 && in_attr[Tag_CPU_arch].i != 13
13790 && in_attr[i].i == 0))
13791 ; /* Do nothing. */
13792 /* Output value should be 0 if DSP part of architecture, ie.
13793 - post (>=) ARMv5te architecture output
13794 - A, R or S profile output or ARMv7E-M output architecture. */
13795 else if (out_attr[Tag_CPU_arch].i >= 4
13796 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13797 || out_attr[Tag_CPU_arch_profile].i == 'R'
13798 || out_attr[Tag_CPU_arch_profile].i == 'S'
13799 || out_attr[Tag_CPU_arch].i == 13))
13800 out_attr[i].i = 0;
13801 /* Otherwise, DSP instructions are added and not part of output
13802 architecture. */
13803 else
13804 out_attr[i].i = 1;
13805 break;
13806
75375b3e 13807 case Tag_FP_arch:
62f3b8c8 13808 {
4547cb56
NC		 13809 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13810 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13811 when it's 0. It might mean absence of FP hardware if
99654aaf 13812 Tag_FP_arch is zero. */
4547cb56 13813
a715796b 13814#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13815 static const struct
13816 {
13817 int ver;
13818 int regs;
bca38921 13819 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13820 {
13821 {0, 0},
13822 {1, 16},
13823 {2, 16},
13824 {3, 32},
13825 {3, 16},
13826 {4, 32},
bca38921 13827 {4, 16},
a715796b
TG		 13828 {8, 32},
13829 {8, 16}
62f3b8c8
PB		 13830 };
13831 int ver;
13832 int regs;
13833 int newval;
13834
4547cb56
NC		 13835 /* If the output has no requirement about FP hardware,
13836 follow the requirement of the input. */
13837 if (out_attr[i].i == 0)
13838 {
4ec192e6
RE		 13839 /* This assert is still reasonable, we shouldn't
13840 produce the suspicious build attribute
13841 combination (See below for in_attr). */
4547cb56
NC		 13842 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13843 out_attr[i].i = in_attr[i].i;
13844 out_attr[Tag_ABI_HardFP_use].i
13845 = in_attr[Tag_ABI_HardFP_use].i;
13846 break;
13847 }
13848 /* If the input has no requirement about FP hardware, do
13849 nothing. */
13850 else if (in_attr[i].i == 0)
13851 {
4ec192e6
RE		 13852 /* We used to assert that Tag_ABI_HardFP_use was
13853 zero here, but we should never assert when
13854 consuming an object file that has suspicious
13855 build attributes. The single precision variant
13856 of 'no FP architecture' is still 'no FP
13857 architecture', so we just ignore the tag in this
13858 case. */
4547cb56
NC		 13859 break;
13860 }
13861
13862 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13863 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13864
13865 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13866 do nothing. */
13867 if (in_attr[Tag_ABI_HardFP_use].i == 0
13868 && out_attr[Tag_ABI_HardFP_use].i == 0)
13869 ;
13870 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13871 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13872 else if (in_attr[Tag_ABI_HardFP_use].i
13873 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13874 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13875
13876 /* Now we can handle Tag_FP_arch. */
13877
bca38921
MGD		 13878 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13879 pick the biggest. */
13880 if (in_attr[i].i >= VFP_VERSION_COUNT
13881 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13882 {
13883 out_attr[i] = in_attr[i];
13884 break;
13885 }
13886 /* The output uses the superset of input features
13887 (ISA version) and registers. */
13888 ver = vfp_versions[in_attr[i].i].ver;
13889 if (ver < vfp_versions[out_attr[i].i].ver)
13890 ver = vfp_versions[out_attr[i].i].ver;
13891 regs = vfp_versions[in_attr[i].i].regs;
13892 if (regs < vfp_versions[out_attr[i].i].regs)
13893 regs = vfp_versions[out_attr[i].i].regs;
13894 /* This assumes all possible supersets are also a valid
99059e56 13895 options. */
bca38921 13896 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13897 {
13898 if (regs == vfp_versions[newval].regs
13899 && ver == vfp_versions[newval].ver)
13900 break;
13901 }
13902 out_attr[i].i = newval;
13903 }
b1cc4aeb 13904 break;
ee065d83
PB		 13905 case Tag_PCS_config:
13906 if (out_attr[i].i == 0)
13907 out_attr[i].i = in_attr[i].i;
b6009aca 13908 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13909 {
13910 /* It's sometimes ok to mix different configs, so this is only
99059e56 13911 a warning. */
ee065d83
PB		 13912 _bfd_error_handler
13913 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13914 }
13915 break;
13916 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13917 if (in_attr[i].i != out_attr[i].i
13918 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13919 && in_attr[i].i != AEABI_R9_unused)
13920 {
13921 _bfd_error_handler
3895f852 13922 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13923 result = FALSE;
ee065d83
PB		 13924 }
13925 if (out_attr[i].i == AEABI_R9_unused)
13926 out_attr[i].i = in_attr[i].i;
13927 break;
13928 case Tag_ABI_PCS_RW_data:
13929 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13930 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13931 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13932 {
13933 _bfd_error_handler
3895f852 13934 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13935 ibfd);
91e22acd 13936 result = FALSE;
ee065d83
PB		 13937 }
13938 /* Use the smallest value specified. */
13939 if (in_attr[i].i < out_attr[i].i)
13940 out_attr[i].i = in_attr[i].i;
13941 break;
ee065d83 13942 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13943 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13944 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13945 {
13946 _bfd_error_handler
a9dc9481
JM		 13947 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13948 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13949 }
a9dc9481 13950 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13951 out_attr[i].i = in_attr[i].i;
13952 break;
ee065d83
PB		 13953 case Tag_ABI_enum_size:
13954 if (in_attr[i].i != AEABI_enum_unused)
13955 {
13956 if (out_attr[i].i == AEABI_enum_unused
13957 || out_attr[i].i == AEABI_enum_forced_wide)
13958 {
13959 /* The existing object is compatible with anything.
13960 Use whatever requirements the new object has. */
13961 out_attr[i].i = in_attr[i].i;
13962 }
13963 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13964 && out_attr[i].i != in_attr[i].i
0ffa91dd 13965 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13966 {
91e22acd 13967 static const char *aeabi_enum_names[] =
bf21ed78 13968 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13969 const char *in_name =
13970 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13971 ? aeabi_enum_names[in_attr[i].i]
13972 : "<unknown>";
13973 const char *out_name =
13974 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13975 ? aeabi_enum_names[out_attr[i].i]
13976 : "<unknown>";
ee065d83 13977 _bfd_error_handler
bf21ed78 13978 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13979 ibfd, in_name, out_name);
ee065d83
PB		 13980 }
13981 }
13982 break;
13983 case Tag_ABI_VFP_args:
13984 /* Aready done. */
13985 break;
13986 case Tag_ABI_WMMX_args:
13987 if (in_attr[i].i != out_attr[i].i)
13988 {
13989 _bfd_error_handler
3895f852 13990 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13991 ibfd, obfd);
91e22acd 13992 result = FALSE;
ee065d83
PB		 13993 }
13994 break;
7b86a9fa
AS		 13995 case Tag_compatibility:
13996 /* Merged in target-independent code. */
13997 break;
91e22acd 13998 case Tag_ABI_HardFP_use:
4547cb56 13999 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14000 break;
14001 case Tag_ABI_FP_16bit_format:
14002 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14003 {
14004 if (in_attr[i].i != out_attr[i].i)
14005 {
14006 _bfd_error_handler
3895f852 14007 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 14008 ibfd, obfd);
14009 result = FALSE;
14010 }
14011 }
14012 if (in_attr[i].i != 0)
14013 out_attr[i].i = in_attr[i].i;
14014 break;
7b86a9fa 14015
cd21e546 14016 case Tag_DIV_use:
ac56ee8f
MGD		 14017 /* A value of zero on input means that the divide instruction may
14018 be used if available in the base architecture as specified via
14019 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14020 the user did not want divide instructions. A value of 2
14021 explicitly means that divide instructions were allowed in ARM
14022 and Thumb state. */
14023 if (in_attr[i].i == out_attr[i].i)
14024 /* Do nothing. */ ;
14025 else if (elf32_arm_attributes_forbid_div (in_attr)
14026 && !elf32_arm_attributes_accept_div (out_attr))
14027 out_attr[i].i = 1;
14028 else if (elf32_arm_attributes_forbid_div (out_attr)
14029 && elf32_arm_attributes_accept_div (in_attr))
14030 out_attr[i].i = in_attr[i].i;
14031 else if (in_attr[i].i == 2)
14032 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14033 break;
14034
14035 case Tag_MPextension_use_legacy:
14036 /* We don't output objects with Tag_MPextension_use_legacy - we
14037 move the value to Tag_MPextension_use. */
14038 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14039 {
14040 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14041 {
14042 _bfd_error_handler
de194d85 14043 (_("%B has both the current and legacy "
b38cadfb 14044 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14045 ibfd);
14046 result = FALSE;
14047 }
14048 }
14049
14050 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14051 out_attr[Tag_MPextension_use] = in_attr[i];
14052
14053 break;
14054
91e22acd 14055 case Tag_nodefaults:
2d0bb761
AS		 14056 /* This tag is set if it exists, but the value is unused (and is
14057 typically zero). We don't actually need to do anything here -
14058 the merge happens automatically when the type flags are merged
14059 below. */
91e22acd
AS		 14060 break;
14061 case Tag_also_compatible_with:
14062 /* Already done in Tag_CPU_arch. */
14063 break;
14064 case Tag_conformance:
14065 /* Keep the attribute if it matches. Throw it away otherwise.
14066 No attribute means no claim to conform. */
14067 if (!in_attr[i].s || !out_attr[i].s
14068 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14069 out_attr[i].s = NULL;
14070 break;
3cfad14c 14071
91e22acd 14072 default:
e8b36cd1
JM		 14073 result
14074 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14075 }
14076
14077 /* If out_attr was copied from in_attr then it won't have a type yet. */
14078 if (in_attr[i].type && !out_attr[i].type)
14079 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14080 }
14081
104d59d1 14082 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14083 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14084 return FALSE;
ee065d83 14085
104d59d1 14086 /* Check for any attributes not known on ARM. */
e8b36cd1 14087 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14088
91e22acd 14089 return result;
252b5132
RH		 14090}
14091
3a4a14e9
PB		 14092
14093/* Return TRUE if the two EABI versions are incompatible. */
14094
14095static bfd_boolean
14096elf32_arm_versions_compatible (unsigned iver, unsigned over)
14097{
14098 /* v4 and v5 are the same spec before and after it was released,
14099 so allow mixing them. */
14100 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14101 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14102 return TRUE;
14103
14104 return (iver == over);
14105}
14106
252b5132
RH		 14107/* Merge backend specific data from an object file to the output
14108 object file when linking. */
9b485d32 14109
b34976b6 14110static bfd_boolean
50e03d47 14111elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14112
9b485d32
NC		 14113/* Display the flags field. */
14114
b34976b6 14115static bfd_boolean
57e8b36a 14116elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14117{
fc830a83
NC		 14118 FILE * file = (FILE *) ptr;
14119 unsigned long flags;
252b5132
RH		 14120
14121 BFD_ASSERT (abfd != NULL && ptr != NULL);
14122
14123 /* Print normal ELF private data. */
14124 _bfd_elf_print_private_bfd_data (abfd, ptr);
14125
fc830a83 14126 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14127 /* Ignore init flag - it may not be set, despite the flags field
14128 containing valid data. */
252b5132 14129
9b485d32 14130 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14131
fc830a83
NC		 14132 switch (EF_ARM_EABI_VERSION (flags))
14133 {
14134 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14135 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14136 official ARM ELF extended ABI. Hence they are only decoded if
14137 the EABI version is not set. */
fd2ec330 14138 if (flags & EF_ARM_INTERWORK)
9b485d32 14139 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14140
fd2ec330 14141 if (flags & EF_ARM_APCS_26)
6c571f00 14142 fprintf (file, " [APCS-26]");
fc830a83 14143 else
6c571f00 14144 fprintf (file, " [APCS-32]");
9a5aca8c 14145
96a846ea
RE		 14146 if (flags & EF_ARM_VFP_FLOAT)
14147 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14148 else if (flags & EF_ARM_MAVERICK_FLOAT)
14149 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14150 else
14151 fprintf (file, _(" [FPA float format]"));
14152
fd2ec330 14153 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14154 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14155
fd2ec330 14156 if (flags & EF_ARM_PIC)
9b485d32 14157 fprintf (file, _(" [position independent]"));
fc830a83 14158
fd2ec330 14159 if (flags & EF_ARM_NEW_ABI)
9b485d32 14160 fprintf (file, _(" [new ABI]"));
9a5aca8c 14161
fd2ec330 14162 if (flags & EF_ARM_OLD_ABI)
9b485d32 14163 fprintf (file, _(" [old ABI]"));
9a5aca8c 14164
fd2ec330 14165 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14166 fprintf (file, _(" [software FP]"));
9a5aca8c 14167
96a846ea
RE		 14168 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14169 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14170 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14171 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14172 break;
9a5aca8c 14173
fc830a83 14174 case EF_ARM_EABI_VER1:
9b485d32 14175 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14176
fc830a83 14177 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14178 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14179 else
9b485d32 14180 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14181
fc830a83
NC		 14182 flags &= ~ EF_ARM_SYMSARESORTED;
14183 break;
9a5aca8c 14184
fd2ec330
PB		 14185 case EF_ARM_EABI_VER2:
14186 fprintf (file, _(" [Version2 EABI]"));
14187
14188 if (flags & EF_ARM_SYMSARESORTED)
14189 fprintf (file, _(" [sorted symbol table]"));
14190 else
14191 fprintf (file, _(" [unsorted symbol table]"));
14192
14193 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14194 fprintf (file, _(" [dynamic symbols use segment index]"));
14195
14196 if (flags & EF_ARM_MAPSYMSFIRST)
14197 fprintf (file, _(" [mapping symbols precede others]"));
14198
99e4ae17 14199 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14200 | EF_ARM_MAPSYMSFIRST);
14201 break;
14202
d507cf36
PB		 14203 case EF_ARM_EABI_VER3:
14204 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14205 break;
14206
14207 case EF_ARM_EABI_VER4:
14208 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14209 goto eabi;
d507cf36 14210
3a4a14e9
PB		 14211 case EF_ARM_EABI_VER5:
14212 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14213
14214 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14215 fprintf (file, _(" [soft-float ABI]"));
14216
14217 if (flags & EF_ARM_ABI_FLOAT_HARD)
14218 fprintf (file, _(" [hard-float ABI]"));
14219
14220 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14221
3a4a14e9 14222 eabi:
d507cf36
PB		 14223 if (flags & EF_ARM_BE8)
14224 fprintf (file, _(" [BE8]"));
14225
14226 if (flags & EF_ARM_LE8)
14227 fprintf (file, _(" [LE8]"));
14228
14229 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14230 break;
14231
fc830a83 14232 default:
9b485d32 14233 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14234 break;
14235 }
252b5132 14236
fc830a83 14237 flags &= ~ EF_ARM_EABIMASK;
252b5132 14238
fc830a83 14239 if (flags & EF_ARM_RELEXEC)
9b485d32 14240 fprintf (file, _(" [relocatable executable]"));
252b5132 14241
a5721edd 14242 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14243
14244 if (flags)
9b485d32 14245 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14246
252b5132
RH		 14247 fputc ('\n', file);
14248
b34976b6 14249 return TRUE;
252b5132
RH		 14250}
14251
14252static int
57e8b36a 14253elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14254{
2f0ca46a
NC		 14255 switch (ELF_ST_TYPE (elf_sym->st_info))
14256 {
14257 case STT_ARM_TFUNC:
14258 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14259
2f0ca46a
NC		 14260 case STT_ARM_16BIT:
14261 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14262 This allows us to distinguish between data used by Thumb instructions
14263 and non-data (which is probably code) inside Thumb regions of an
14264 executable. */
1a0eb693 14265 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14266 return ELF_ST_TYPE (elf_sym->st_info);
14267 break;
9a5aca8c 14268
ce855c42
NC		 14269 default:
14270 break;
2f0ca46a
NC		 14271 }
14272
14273 return type;
252b5132 14274}
f21f3fe0 14275
252b5132 14276static asection *
07adf181
AM		 14277elf32_arm_gc_mark_hook (asection *sec,
14278 struct bfd_link_info *info,
14279 Elf_Internal_Rela *rel,
14280 struct elf_link_hash_entry *h,
14281 Elf_Internal_Sym *sym)
252b5132
RH		 14282{
14283 if (h != NULL)
07adf181 14284 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14285 {
14286 case R_ARM_GNU_VTINHERIT:
14287 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14288 return NULL;
14289 }
9ad5cbcf 14290
07adf181 14291 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14292}
14293
780a67af
NC		 14294/* Update the got entry reference counts for the section being removed. */
14295
b34976b6 14296static bfd_boolean
ba93b8ac
DJ		 14297elf32_arm_gc_sweep_hook (bfd * abfd,
14298 struct bfd_link_info * info,
14299 asection * sec,
14300 const Elf_Internal_Rela * relocs)
252b5132 14301{
5e681ec4
PB		 14302 Elf_Internal_Shdr *symtab_hdr;
14303 struct elf_link_hash_entry **sym_hashes;
14304 bfd_signed_vma *local_got_refcounts;
14305 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14306 struct elf32_arm_link_hash_table * globals;
14307
0e1862bb 14308 if (bfd_link_relocatable (info))
7dda2462
TG		 14309 return TRUE;
14310
eb043451 14311 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14312 if (globals == NULL)
14313 return FALSE;
5e681ec4
PB		 14314
14315 elf_section_data (sec)->local_dynrel = NULL;
14316
0ffa91dd 14317 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14318 sym_hashes = elf_sym_hashes (abfd);
14319 local_got_refcounts = elf_local_got_refcounts (abfd);
14320
906e58ca 14321 check_use_blx (globals);
bd97cb95 14322
5e681ec4
PB		 14323 relend = relocs + sec->reloc_count;
14324 for (rel = relocs; rel < relend; rel++)
eb043451 14325 {
3eb128b2
AM		 14326 unsigned long r_symndx;
14327 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14328 struct elf32_arm_link_hash_entry *eh;
eb043451 14329 int r_type;
34e77a92 14330 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14331 bfd_boolean may_become_dynamic_p;
14332 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14333 union gotplt_union *root_plt;
14334 struct arm_plt_info *arm_plt;
5e681ec4 14335
3eb128b2
AM		 14336 r_symndx = ELF32_R_SYM (rel->r_info);
14337 if (r_symndx >= symtab_hdr->sh_info)
14338 {
14339 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14340 while (h->root.type == bfd_link_hash_indirect
14341 || h->root.type == bfd_link_hash_warning)
14342 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14343 }
f6e32f6d
RS		 14344 eh = (struct elf32_arm_link_hash_entry *) h;
14345
34e77a92 14346 call_reloc_p = FALSE;
f6e32f6d
RS		 14347 may_become_dynamic_p = FALSE;
14348 may_need_local_target_p = FALSE;
3eb128b2 14349
eb043451 14350 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14351 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14352 switch (r_type)
14353 {
14354 case R_ARM_GOT32:
eb043451 14355 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14356 case R_ARM_TLS_GD32:
14357 case R_ARM_TLS_IE32:
3eb128b2 14358 if (h != NULL)
eb043451 14359 {
eb043451
PB		 14360 if (h->got.refcount > 0)
14361 h->got.refcount -= 1;
14362 }
14363 else if (local_got_refcounts != NULL)
14364 {
14365 if (local_got_refcounts[r_symndx] > 0)
14366 local_got_refcounts[r_symndx] -= 1;
14367 }
14368 break;
14369
ba93b8ac 14370 case R_ARM_TLS_LDM32:
4dfe6ac6 14371 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14372 break;
14373
eb043451
PB		 14374 case R_ARM_PC24:
14375 case R_ARM_PLT32:
5b5bb741
PB		 14376 case R_ARM_CALL:
14377 case R_ARM_JUMP24:
eb043451 14378 case R_ARM_PREL31:
c19d1205 14379 case R_ARM_THM_CALL:
bd97cb95
DJ		 14380 case R_ARM_THM_JUMP24:
14381 case R_ARM_THM_JUMP19:
34e77a92 14382 call_reloc_p = TRUE;
f6e32f6d
RS		 14383 may_need_local_target_p = TRUE;
14384 break;
14385
14386 case R_ARM_ABS12:
14387 if (!globals->vxworks_p)
14388 {
14389 may_need_local_target_p = TRUE;
14390 break;
14391 }
14392 /* Fall through. */
14393 case R_ARM_ABS32:
14394 case R_ARM_ABS32_NOI:
14395 case R_ARM_REL32:
14396 case R_ARM_REL32_NOI:
b6895b4f
PB		 14397 case R_ARM_MOVW_ABS_NC:
14398 case R_ARM_MOVT_ABS:
14399 case R_ARM_MOVW_PREL_NC:
14400 case R_ARM_MOVT_PREL:
14401 case R_ARM_THM_MOVW_ABS_NC:
14402 case R_ARM_THM_MOVT_ABS:
14403 case R_ARM_THM_MOVW_PREL_NC:
14404 case R_ARM_THM_MOVT_PREL:
b7693d02 14405 /* Should the interworking branches be here also? */
0e1862bb 14406 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14407 && (sec->flags & SEC_ALLOC) != 0)
14408 {
14409 if (h == NULL
469a3493 14410 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14411 {
14412 call_reloc_p = TRUE;
14413 may_need_local_target_p = TRUE;
14414 }
14415 else
14416 may_become_dynamic_p = TRUE;
14417 }
f6e32f6d
RS		 14418 else
14419 may_need_local_target_p = TRUE;
14420 break;
b7693d02 14421
f6e32f6d
RS		 14422 default:
14423 break;
14424 }
5e681ec4 14425
34e77a92 14426 if (may_need_local_target_p
4ba2ef8f
TP		 14427 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14428 &arm_plt))
f6e32f6d 14429 {
27586251
HPN		 14430 /* If PLT refcount book-keeping is wrong and too low, we'll
14431 see a zero value (going to -1) for the root PLT reference
14432 count. */
14433 if (root_plt->refcount >= 0)
14434 {
14435 BFD_ASSERT (root_plt->refcount != 0);
14436 root_plt->refcount -= 1;
14437 }
14438 else
14439 /* A value of -1 means the symbol has become local, forced
14440 or seeing a hidden definition. Any other negative value
14441 is an error. */
14442 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14443
14444 if (!call_reloc_p)
14445 arm_plt->noncall_refcount--;
5e681ec4 14446
f6e32f6d 14447 if (r_type == R_ARM_THM_CALL)
34e77a92 14448 arm_plt->maybe_thumb_refcount--;
bd97cb95 14449
f6e32f6d
RS		 14450 if (r_type == R_ARM_THM_JUMP24
14451 || r_type == R_ARM_THM_JUMP19)
34e77a92 14452 arm_plt->thumb_refcount--;
f6e32f6d 14453 }
5e681ec4 14454
34e77a92 14455 if (may_become_dynamic_p)
f6e32f6d
RS		 14456 {
14457 struct elf_dyn_relocs **pp;
14458 struct elf_dyn_relocs *p;
5e681ec4 14459
34e77a92 14460 if (h != NULL)
9c489990 14461 pp = &(eh->dyn_relocs);
34e77a92
RS		 14462 else
14463 {
14464 Elf_Internal_Sym *isym;
14465
14466 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14467 abfd, r_symndx);
14468 if (isym == NULL)
14469 return FALSE;
14470 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14471 if (pp == NULL)
14472 return FALSE;
14473 }
9c489990 14474 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14475 if (p->sec == sec)
14476 {
14477 /* Everything must go for SEC. */
14478 *pp = p->next;
14479 break;
14480 }
eb043451
PB		 14481 }
14482 }
5e681ec4 14483
b34976b6 14484 return TRUE;
252b5132
RH		 14485}
14486
780a67af
NC		 14487/* Look through the relocs for a section during the first phase. */
14488
b34976b6 14489static bfd_boolean
57e8b36a
NC		 14490elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14491 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14492{
b34976b6
AM		 14493 Elf_Internal_Shdr *symtab_hdr;
14494 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14495 const Elf_Internal_Rela *rel;
14496 const Elf_Internal_Rela *rel_end;
14497 bfd *dynobj;
5e681ec4 14498 asection *sreloc;
5e681ec4 14499 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14500 bfd_boolean call_reloc_p;
14501 bfd_boolean may_become_dynamic_p;
14502 bfd_boolean may_need_local_target_p;
ce98a316 14503 unsigned long nsyms;
9a5aca8c 14504
0e1862bb 14505 if (bfd_link_relocatable (info))
b34976b6 14506 return TRUE;
9a5aca8c 14507
0ffa91dd
NC		 14508 BFD_ASSERT (is_arm_elf (abfd));
14509
5e681ec4 14510 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14511 if (htab == NULL)
14512 return FALSE;
14513
5e681ec4 14514 sreloc = NULL;
9a5aca8c 14515
67687978
PB		 14516 /* Create dynamic sections for relocatable executables so that we can
14517 copy relocations. */
14518 if (htab->root.is_relocatable_executable
14519 && ! htab->root.dynamic_sections_created)
14520 {
14521 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14522 return FALSE;
14523 }
14524
cbc704f3
RS		 14525 if (htab->root.dynobj == NULL)
14526 htab->root.dynobj = abfd;
34e77a92
RS		 14527 if (!create_ifunc_sections (info))
14528 return FALSE;
cbc704f3
RS		 14529
14530 dynobj = htab->root.dynobj;
14531
0ffa91dd 14532 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14533 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14534 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14535
252b5132
RH		 14536 rel_end = relocs + sec->reloc_count;
14537 for (rel = relocs; rel < rel_end; rel++)
14538 {
34e77a92 14539 Elf_Internal_Sym *isym;
252b5132 14540 struct elf_link_hash_entry *h;
b7693d02 14541 struct elf32_arm_link_hash_entry *eh;
d42c267e 14542 unsigned int r_symndx;
eb043451 14543 int r_type;
9a5aca8c 14544
252b5132 14545 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14546 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14547 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14548
ce98a316
NC		 14549 if (r_symndx >= nsyms
14550 /* PR 9934: It is possible to have relocations that do not
14551 refer to symbols, thus it is also possible to have an
14552 object file containing relocations but no symbol table. */
cf35638d 14553 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14554 {
4eca0228
AM		 14555 _bfd_error_handler (_("%B: bad symbol index: %d"), abfd,
14556 r_symndx);
ba93b8ac
DJ		 14557 return FALSE;
14558 }
14559
34e77a92
RS		 14560 h = NULL;
14561 isym = NULL;
14562 if (nsyms > 0)
973a3492 14563 {
34e77a92
RS		 14564 if (r_symndx < symtab_hdr->sh_info)
14565 {
14566 /* A local symbol. */
14567 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14568 abfd, r_symndx);
14569 if (isym == NULL)
14570 return FALSE;
14571 }
14572 else
14573 {
14574 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14575 while (h->root.type == bfd_link_hash_indirect
14576 || h->root.type == bfd_link_hash_warning)
14577 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14578
14579 /* PR15323, ref flags aren't set for references in the
14580 same object. */
bc4e12de 14581 h->root.non_ir_ref_regular = 1;
34e77a92 14582 }
973a3492 14583 }
9a5aca8c 14584
b7693d02
DJ		 14585 eh = (struct elf32_arm_link_hash_entry *) h;
14586
f6e32f6d
RS		 14587 call_reloc_p = FALSE;
14588 may_become_dynamic_p = FALSE;
14589 may_need_local_target_p = FALSE;
14590
0855e32b
NS		 14591 /* Could be done earlier, if h were already available. */
14592 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14593 switch (r_type)
99059e56 14594 {
5e681ec4 14595 case R_ARM_GOT32:
eb043451 14596 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14597 case R_ARM_TLS_GD32:
14598 case R_ARM_TLS_IE32:
0855e32b
NS		 14599 case R_ARM_TLS_GOTDESC:
14600 case R_ARM_TLS_DESCSEQ:
14601 case R_ARM_THM_TLS_DESCSEQ:
14602 case R_ARM_TLS_CALL:
14603 case R_ARM_THM_TLS_CALL:
5e681ec4 14604 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14605 {
14606 int tls_type, old_tls_type;
5e681ec4 14607
ba93b8ac
DJ		 14608 switch (r_type)
14609 {
14610 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14611
ba93b8ac 14612 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14613
0855e32b
NS		 14614 case R_ARM_TLS_GOTDESC:
14615 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14616 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14617 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14618
ba93b8ac
DJ		 14619 default: tls_type = GOT_NORMAL; break;
14620 }
252b5132 14621
0e1862bb 14622 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14623 info->flags |= DF_STATIC_TLS;
14624
ba93b8ac
DJ		 14625 if (h != NULL)
14626 {
14627 h->got.refcount++;
14628 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14629 }
14630 else
14631 {
ba93b8ac 14632 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14633 if (!elf32_arm_allocate_local_sym_info (abfd))
14634 return FALSE;
14635 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14636 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14637 }
14638
0855e32b 14639 /* If a variable is accessed with both tls methods, two
99059e56 14640 slots may be created. */
0855e32b
NS		 14641 if (GOT_TLS_GD_ANY_P (old_tls_type)
14642 && GOT_TLS_GD_ANY_P (tls_type))
14643 tls_type |= old_tls_type;
14644
14645 /* We will already have issued an error message if there
14646 is a TLS/non-TLS mismatch, based on the symbol
14647 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14648 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14649 && tls_type != GOT_NORMAL)
14650 tls_type |= old_tls_type;
14651
0855e32b 14652 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14653 method, we're able to relax. Turn off the GDESC flag,
14654 without messing up with any other kind of tls types
6a631e86 14655 that may be involved. */
0855e32b
NS		 14656 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14657 tls_type &= ~GOT_TLS_GDESC;
14658
ba93b8ac
DJ		 14659 if (old_tls_type != tls_type)
14660 {
14661 if (h != NULL)
14662 elf32_arm_hash_entry (h)->tls_type = tls_type;
14663 else
14664 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14665 }
14666 }
8029a119 14667 /* Fall through. */
ba93b8ac
DJ		 14668
14669 case R_ARM_TLS_LDM32:
14670 if (r_type == R_ARM_TLS_LDM32)
14671 htab->tls_ldm_got.refcount++;
8029a119 14672 /* Fall through. */
252b5132 14673
c19d1205 14674 case R_ARM_GOTOFF32:
5e681ec4 14675 case R_ARM_GOTPC:
cbc704f3
RS		 14676 if (htab->root.sgot == NULL
14677 && !create_got_section (htab->root.dynobj, info))
14678 return FALSE;
252b5132
RH		 14679 break;
14680
252b5132 14681 case R_ARM_PC24:
7359ea65 14682 case R_ARM_PLT32:
5b5bb741
PB		 14683 case R_ARM_CALL:
14684 case R_ARM_JUMP24:
eb043451 14685 case R_ARM_PREL31:
c19d1205 14686 case R_ARM_THM_CALL:
bd97cb95
DJ		 14687 case R_ARM_THM_JUMP24:
14688 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14689 call_reloc_p = TRUE;
14690 may_need_local_target_p = TRUE;
14691 break;
14692
14693 case R_ARM_ABS12:
14694 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14695 ldr __GOTT_INDEX__ offsets. */
14696 if (!htab->vxworks_p)
14697 {
14698 may_need_local_target_p = TRUE;
14699 break;
14700 }
aebf9be7 14701 else goto jump_over;
9eaff861 14702
f6e32f6d 14703 /* Fall through. */
39623e12 14704
96c23d59
JM		 14705 case R_ARM_MOVW_ABS_NC:
14706 case R_ARM_MOVT_ABS:
14707 case R_ARM_THM_MOVW_ABS_NC:
14708 case R_ARM_THM_MOVT_ABS:
0e1862bb 14709 if (bfd_link_pic (info))
96c23d59 14710 {
4eca0228 14711 _bfd_error_handler
96c23d59
JM		 14712 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14713 abfd, elf32_arm_howto_table_1[r_type].name,
14714 (h) ? h->root.root.string : "a local symbol");
14715 bfd_set_error (bfd_error_bad_value);
14716 return FALSE;
14717 }
14718
14719 /* Fall through. */
39623e12
PB		 14720 case R_ARM_ABS32:
14721 case R_ARM_ABS32_NOI:
aebf9be7 14722 jump_over:
0e1862bb 14723 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14724 {
14725 h->pointer_equality_needed = 1;
14726 }
14727 /* Fall through. */
39623e12
PB		 14728 case R_ARM_REL32:
14729 case R_ARM_REL32_NOI:
b6895b4f
PB		 14730 case R_ARM_MOVW_PREL_NC:
14731 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14732 case R_ARM_THM_MOVW_PREL_NC:
14733 case R_ARM_THM_MOVT_PREL:
39623e12 14734
b7693d02 14735 /* Should the interworking branches be listed here? */
0e1862bb 14736 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14737 && (sec->flags & SEC_ALLOC) != 0)
14738 {
14739 if (h == NULL
469a3493 14740 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14741 {
14742 /* In shared libraries and relocatable executables,
14743 we treat local relative references as calls;
14744 see the related SYMBOL_CALLS_LOCAL code in
14745 allocate_dynrelocs. */
14746 call_reloc_p = TRUE;
14747 may_need_local_target_p = TRUE;
14748 }
14749 else
14750 /* We are creating a shared library or relocatable
14751 executable, and this is a reloc against a global symbol,
14752 or a non-PC-relative reloc against a local symbol.
14753 We may need to copy the reloc into the output. */
14754 may_become_dynamic_p = TRUE;
14755 }
f6e32f6d
RS		 14756 else
14757 may_need_local_target_p = TRUE;
252b5132
RH		 14758 break;
14759
99059e56
RM		 14760 /* This relocation describes the C++ object vtable hierarchy.
14761 Reconstruct it for later use during GC. */
14762 case R_ARM_GNU_VTINHERIT:
14763 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14764 return FALSE;
14765 break;
14766
14767 /* This relocation describes which C++ vtable entries are actually
14768 used. Record for later use during GC. */
14769 case R_ARM_GNU_VTENTRY:
14770 BFD_ASSERT (h != NULL);
14771 if (h != NULL
14772 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14773 return FALSE;
14774 break;
14775 }
f6e32f6d
RS		 14776
14777 if (h != NULL)
14778 {
14779 if (call_reloc_p)
14780 /* We may need a .plt entry if the function this reloc
14781 refers to is in a different object, regardless of the
14782 symbol's type. We can't tell for sure yet, because
14783 something later might force the symbol local. */
14784 h->needs_plt = 1;
14785 else if (may_need_local_target_p)
14786 /* If this reloc is in a read-only section, we might
14787 need a copy reloc. We can't check reliably at this
14788 stage whether the section is read-only, as input
14789 sections have not yet been mapped to output sections.
14790 Tentatively set the flag for now, and correct in
14791 adjust_dynamic_symbol. */
14792 h->non_got_ref = 1;
14793 }
14794
34e77a92
RS		 14795 if (may_need_local_target_p
14796 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14797 {
34e77a92
RS		 14798 union gotplt_union *root_plt;
14799 struct arm_plt_info *arm_plt;
14800 struct arm_local_iplt_info *local_iplt;
14801
14802 if (h != NULL)
14803 {
14804 root_plt = &h->plt;
14805 arm_plt = &eh->plt;
14806 }
14807 else
14808 {
14809 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14810 if (local_iplt == NULL)
14811 return FALSE;
14812 root_plt = &local_iplt->root;
14813 arm_plt = &local_iplt->arm;
14814 }
14815
f6e32f6d
RS		 14816 /* If the symbol is a function that doesn't bind locally,
14817 this relocation will need a PLT entry. */
a8c887dd
NC		 14818 if (root_plt->refcount != -1)
14819 root_plt->refcount += 1;
34e77a92
RS		 14820
14821 if (!call_reloc_p)
14822 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14823
14824 /* It's too early to use htab->use_blx here, so we have to
14825 record possible blx references separately from
14826 relocs that definitely need a thumb stub. */
14827
14828 if (r_type == R_ARM_THM_CALL)
34e77a92 14829 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14830
14831 if (r_type == R_ARM_THM_JUMP24
14832 || r_type == R_ARM_THM_JUMP19)
34e77a92 14833 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14834 }
14835
14836 if (may_become_dynamic_p)
14837 {
14838 struct elf_dyn_relocs *p, **head;
14839
14840 /* Create a reloc section in dynobj. */
14841 if (sreloc == NULL)
14842 {
14843 sreloc = _bfd_elf_make_dynamic_reloc_section
14844 (sec, dynobj, 2, abfd, ! htab->use_rel);
14845
14846 if (sreloc == NULL)
14847 return FALSE;
14848
14849 /* BPABI objects never have dynamic relocations mapped. */
14850 if (htab->symbian_p)
14851 {
14852 flagword flags;
14853
14854 flags = bfd_get_section_flags (dynobj, sreloc);
14855 flags &= ~(SEC_LOAD | SEC_ALLOC);
14856 bfd_set_section_flags (dynobj, sreloc, flags);
14857 }
14858 }
14859
14860 /* If this is a global symbol, count the number of
14861 relocations we need for this symbol. */
14862 if (h != NULL)
14863 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14864 else
14865 {
34e77a92
RS		 14866 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14867 if (head == NULL)
f6e32f6d 14868 return FALSE;
f6e32f6d
RS		 14869 }
14870
14871 p = *head;
14872 if (p == NULL || p->sec != sec)
14873 {
14874 bfd_size_type amt = sizeof *p;
14875
14876 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14877 if (p == NULL)
14878 return FALSE;
14879 p->next = *head;
14880 *head = p;
14881 p->sec = sec;
14882 p->count = 0;
14883 p->pc_count = 0;
14884 }
14885
469a3493 14886 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14887 p->pc_count += 1;
14888 p->count += 1;
14889 }
252b5132 14890 }
f21f3fe0 14891
b34976b6 14892 return TRUE;
252b5132
RH		 14893}
14894
9eaff861
AO		 14895static void
14896elf32_arm_update_relocs (asection *o,
14897 struct bfd_elf_section_reloc_data *reldata)
14898{
14899 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14900 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14901 const struct elf_backend_data *bed;
14902 _arm_elf_section_data *eado;
14903 struct bfd_link_order *p;
14904 bfd_byte *erela_head, *erela;
14905 Elf_Internal_Rela *irela_head, *irela;
14906 Elf_Internal_Shdr *rel_hdr;
14907 bfd *abfd;
14908 unsigned int count;
14909
14910 eado = get_arm_elf_section_data (o);
14911
14912 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14913 return;
14914
14915 abfd = o->owner;
14916 bed = get_elf_backend_data (abfd);
14917 rel_hdr = reldata->hdr;
14918
14919 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14920 {
14921 swap_in = bed->s->swap_reloc_in;
14922 swap_out = bed->s->swap_reloc_out;
14923 }
14924 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14925 {
14926 swap_in = bed->s->swap_reloca_in;
14927 swap_out = bed->s->swap_reloca_out;
14928 }
14929 else
14930 abort ();
14931
14932 erela_head = rel_hdr->contents;
14933 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14934 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14935
14936 erela = erela_head;
14937 irela = irela_head;
14938 count = 0;
14939
14940 for (p = o->map_head.link_order; p; p = p->next)
14941 {
14942 if (p->type == bfd_section_reloc_link_order
14943 || p->type == bfd_symbol_reloc_link_order)
14944 {
14945 (*swap_in) (abfd, erela, irela);
14946 erela += rel_hdr->sh_entsize;
14947 irela++;
14948 count++;
14949 }
14950 else if (p->type == bfd_indirect_link_order)
14951 {
14952 struct bfd_elf_section_reloc_data *input_reldata;
14953 arm_unwind_table_edit *edit_list, *edit_tail;
14954 _arm_elf_section_data *eadi;
14955 bfd_size_type j;
14956 bfd_vma offset;
14957 asection *i;
14958
14959 i = p->u.indirect.section;
14960
14961 eadi = get_arm_elf_section_data (i);
14962 edit_list = eadi->u.exidx.unwind_edit_list;
14963 edit_tail = eadi->u.exidx.unwind_edit_tail;
14964 offset = o->vma + i->output_offset;
14965
14966 if (eadi->elf.rel.hdr &&
14967 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14968 input_reldata = &eadi->elf.rel;
14969 else if (eadi->elf.rela.hdr &&
14970 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14971 input_reldata = &eadi->elf.rela;
14972 else
14973 abort ();
14974
14975 if (edit_list)
14976 {
14977 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14978 {
14979 arm_unwind_table_edit *edit_node, *edit_next;
14980 bfd_vma bias;
c48182bf 14981 bfd_vma reloc_index;
9eaff861
AO		 14982
14983 (*swap_in) (abfd, erela, irela);
c48182bf 14984 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14985
14986 bias = 0;
14987 edit_node = edit_list;
14988 for (edit_next = edit_list;
c48182bf 14989 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14990 edit_next = edit_node->next)
14991 {
14992 bias++;
14993 edit_node = edit_next;
14994 }
14995
14996 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14997 || edit_node->index != reloc_index)
9eaff861
AO		 14998 {
14999 irela->r_offset -= bias * 8;
15000 irela++;
15001 count++;
15002 }
15003
15004 erela += rel_hdr->sh_entsize;
15005 }
15006
15007 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15008 {
15009 /* New relocation entity. */
15010 asection *text_sec = edit_tail->linked_section;
15011 asection *text_out = text_sec->output_section;
15012 bfd_vma exidx_offset = offset + i->size - 8;
15013
15014 irela->r_addend = 0;
15015 irela->r_offset = exidx_offset;
15016 irela->r_info = ELF32_R_INFO
15017 (text_out->target_index, R_ARM_PREL31);
15018 irela++;
15019 count++;
15020 }
15021 }
15022 else
15023 {
15024 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15025 {
15026 (*swap_in) (abfd, erela, irela);
15027 erela += rel_hdr->sh_entsize;
15028 irela++;
15029 }
15030
15031 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15032 }
15033 }
15034 }
15035
15036 reldata->count = count;
15037 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15038
15039 erela = erela_head;
15040 irela = irela_head;
15041 while (count > 0)
15042 {
15043 (*swap_out) (abfd, irela, erela);
15044 erela += rel_hdr->sh_entsize;
15045 irela++;
15046 count--;
15047 }
15048
15049 free (irela_head);
15050
15051 /* Hashes are no longer valid. */
15052 free (reldata->hashes);
15053 reldata->hashes = NULL;
15054}
15055
6a5bb875 15056/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15057 required if the corresponding code section is marked. Similarly, ARMv8-M
15058 secure entry functions can only be referenced by SG veneers which are
15059 created after the GC process. They need to be marked in case they reside in
15060 their own section (as would be the case if code was compiled with
15061 -ffunction-sections). */
6a5bb875
PB		 15062
15063static bfd_boolean
906e58ca
NC		 15064elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15065 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15066{
15067 bfd *sub;
15068 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15069 asection *cmse_sec;
15070 obj_attribute *out_attr;
15071 Elf_Internal_Shdr *symtab_hdr;
15072 unsigned i, sym_count, ext_start;
15073 const struct elf_backend_data *bed;
15074 struct elf_link_hash_entry **sym_hashes;
15075 struct elf32_arm_link_hash_entry *cmse_hash;
15076 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15077
7f6ab9f8
AM		 15078 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15079
4ba2ef8f
TP		 15080 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15081 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15082 && out_attr[Tag_CPU_arch_profile].i == 'M';
15083
6a5bb875
PB		 15084 /* Marking EH data may cause additional code sections to be marked,
15085 requiring multiple passes. */
15086 again = TRUE;
15087 while (again)
15088 {
15089 again = FALSE;
c72f2fb2 15090 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15091 {
15092 asection *o;
15093
0ffa91dd 15094 if (! is_arm_elf (sub))
6a5bb875
PB		 15095 continue;
15096
15097 elf_shdrp = elf_elfsections (sub);
15098 for (o = sub->sections; o != NULL; o = o->next)
15099 {
15100 Elf_Internal_Shdr *hdr;
0ffa91dd 15101
6a5bb875 15102 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15103 if (hdr->sh_type == SHT_ARM_EXIDX
15104 && hdr->sh_link
15105 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15106 && !o->gc_mark
15107 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15108 {
15109 again = TRUE;
15110 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15111 return FALSE;
15112 }
15113 }
4ba2ef8f
TP		 15114
15115 /* Mark section holding ARMv8-M secure entry functions. We mark all
15116 of them so no need for a second browsing. */
15117 if (is_v8m && first_bfd_browse)
15118 {
15119 sym_hashes = elf_sym_hashes (sub);
15120 bed = get_elf_backend_data (sub);
15121 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15122 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15123 ext_start = symtab_hdr->sh_info;
15124
15125 /* Scan symbols. */
15126 for (i = ext_start; i < sym_count; i++)
15127 {
15128 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15129
15130 /* Assume it is a special symbol. If not, cmse_scan will
15131 warn about it and user can do something about it. */
15132 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15133 {
15134 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15135 if (!cmse_sec->gc_mark
15136 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15137 return FALSE;
15138 }
15139 }
15140 }
6a5bb875 15141 }
4ba2ef8f 15142 first_bfd_browse = FALSE;
6a5bb875
PB		 15143 }
15144
15145 return TRUE;
15146}
15147
3c9458e9
NC		 15148/* Treat mapping symbols as special target symbols. */
15149
15150static bfd_boolean
15151elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15152{
b0796911
PB		 15153 return bfd_is_arm_special_symbol_name (sym->name,
15154 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15155}
15156
0367ecfb
NC		 15157/* This is a copy of elf_find_function() from elf.c except that
15158 ARM mapping symbols are ignored when looking for function names
15159 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15160
0367ecfb
NC		 15161static bfd_boolean
15162arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15163 asymbol ** symbols,
fb167eb2 15164 asection * section,
0367ecfb
NC		 15165 bfd_vma offset,
15166 const char ** filename_ptr,
15167 const char ** functionname_ptr)
15168{
15169 const char * filename = NULL;
15170 asymbol * func = NULL;
15171 bfd_vma low_func = 0;
15172 asymbol ** p;
252b5132
RH		 15173
15174 for (p = symbols; *p != NULL; p++)
15175 {
15176 elf_symbol_type *q;
15177
15178 q = (elf_symbol_type *) *p;
15179
252b5132
RH		 15180 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15181 {
15182 default:
15183 break;
15184 case STT_FILE:
15185 filename = bfd_asymbol_name (&q->symbol);
15186 break;
252b5132
RH		 15187 case STT_FUNC:
15188 case STT_ARM_TFUNC:
9d2da7ca 15189 case STT_NOTYPE:
b0796911 15190 /* Skip mapping symbols. */
0367ecfb 15191 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15192 && bfd_is_arm_special_symbol_name (q->symbol.name,
15193 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15194 continue;
15195 /* Fall through. */
6b40fcba 15196 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15197 && q->symbol.value >= low_func
15198 && q->symbol.value <= offset)
15199 {
15200 func = (asymbol *) q;
15201 low_func = q->symbol.value;
15202 }
15203 break;
15204 }
15205 }
15206
15207 if (func == NULL)
b34976b6 15208 return FALSE;
252b5132 15209
0367ecfb
NC		 15210 if (filename_ptr)
15211 *filename_ptr = filename;
15212 if (functionname_ptr)
15213 *functionname_ptr = bfd_asymbol_name (func);
15214
15215 return TRUE;
906e58ca 15216}
0367ecfb
NC		 15217
15218
15219/* Find the nearest line to a particular section and offset, for error
15220 reporting. This code is a duplicate of the code in elf.c, except
15221 that it uses arm_elf_find_function. */
15222
15223static bfd_boolean
15224elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15225 asymbol ** symbols,
fb167eb2 15226 asection * section,
0367ecfb
NC		 15227 bfd_vma offset,
15228 const char ** filename_ptr,
15229 const char ** functionname_ptr,
fb167eb2
AM		 15230 unsigned int * line_ptr,
15231 unsigned int * discriminator_ptr)
0367ecfb
NC		 15232{
15233 bfd_boolean found = FALSE;
15234
fb167eb2 15235 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15236 filename_ptr, functionname_ptr,
fb167eb2
AM		 15237 line_ptr, discriminator_ptr,
15238 dwarf_debug_sections, 0,
0367ecfb
NC		 15239 & elf_tdata (abfd)->dwarf2_find_line_info))
15240 {
15241 if (!*functionname_ptr)
fb167eb2 15242 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15243 *filename_ptr ? NULL : filename_ptr,
15244 functionname_ptr);
f21f3fe0 15245
0367ecfb
NC		 15246 return TRUE;
15247 }
15248
fb167eb2
AM		 15249 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15250 uses DWARF1. */
15251
0367ecfb
NC		 15252 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15253 & found, filename_ptr,
15254 functionname_ptr, line_ptr,
15255 & elf_tdata (abfd)->line_info))
15256 return FALSE;
15257
15258 if (found && (*functionname_ptr || *line_ptr))
15259 return TRUE;
15260
15261 if (symbols == NULL)
15262 return FALSE;
15263
fb167eb2 15264 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15265 filename_ptr, functionname_ptr))
15266 return FALSE;
15267
15268 *line_ptr = 0;
b34976b6 15269 return TRUE;
252b5132
RH		 15270}
15271
4ab527b0
FF		 15272static bfd_boolean
15273elf32_arm_find_inliner_info (bfd * abfd,
15274 const char ** filename_ptr,
15275 const char ** functionname_ptr,
15276 unsigned int * line_ptr)
15277{
15278 bfd_boolean found;
15279 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15280 functionname_ptr, line_ptr,
15281 & elf_tdata (abfd)->dwarf2_find_line_info);
15282 return found;
15283}
15284
252b5132
RH		 15285/* Adjust a symbol defined by a dynamic object and referenced by a
15286 regular object. The current definition is in some section of the
15287 dynamic object, but we're not including those sections. We have to
15288 change the definition to something the rest of the link can
15289 understand. */
15290
b34976b6 15291static bfd_boolean
57e8b36a
NC		 15292elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15293 struct elf_link_hash_entry * h)
252b5132
RH		 15294{
15295 bfd * dynobj;
5474d94f 15296 asection *s, *srel;
b7693d02 15297 struct elf32_arm_link_hash_entry * eh;
67687978 15298 struct elf32_arm_link_hash_table *globals;
252b5132 15299
67687978 15300 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15301 if (globals == NULL)
15302 return FALSE;
15303
252b5132
RH		 15304 dynobj = elf_hash_table (info)->dynobj;
15305
15306 /* Make sure we know what is going on here. */
15307 BFD_ASSERT (dynobj != NULL
f5385ebf 15308 && (h->needs_plt
34e77a92 15309 || h->type == STT_GNU_IFUNC
f6e332e6 15310 || h->u.weakdef != NULL
f5385ebf
AM		 15311 || (h->def_dynamic
15312 && h->ref_regular
15313 && !h->def_regular)));
252b5132 15314
b7693d02
DJ		 15315 eh = (struct elf32_arm_link_hash_entry *) h;
15316
252b5132
RH		 15317 /* If this is a function, put it in the procedure linkage table. We
15318 will fill in the contents of the procedure linkage table later,
15319 when we know the address of the .got section. */
34e77a92 15320 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15321 {
34e77a92
RS		 15322 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15323 symbol binds locally. */
5e681ec4 15324 if (h->plt.refcount <= 0
34e77a92
RS		 15325 || (h->type != STT_GNU_IFUNC
15326 && (SYMBOL_CALLS_LOCAL (info, h)
15327 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15328 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15329 {
15330 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15331 file, but the symbol was never referred to by a dynamic
15332 object, or if all references were garbage collected. In
15333 such a case, we don't actually need to build a procedure
15334 linkage table, and we can just do a PC24 reloc instead. */
15335 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15336 eh->plt.thumb_refcount = 0;
15337 eh->plt.maybe_thumb_refcount = 0;
15338 eh->plt.noncall_refcount = 0;
f5385ebf 15339 h->needs_plt = 0;
252b5132
RH		 15340 }
15341
b34976b6 15342 return TRUE;
252b5132 15343 }
5e681ec4 15344 else
b7693d02
DJ		 15345 {
15346 /* It's possible that we incorrectly decided a .plt reloc was
15347 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15348 in check_relocs. We can't decide accurately between function
15349 and non-function syms in check-relocs; Objects loaded later in
15350 the link may change h->type. So fix it now. */
15351 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15352 eh->plt.thumb_refcount = 0;
15353 eh->plt.maybe_thumb_refcount = 0;
15354 eh->plt.noncall_refcount = 0;
b7693d02 15355 }
252b5132
RH		 15356
15357 /* If this is a weak symbol, and there is a real definition, the
15358 processor independent code will have arranged for us to see the
15359 real definition first, and we can just use the same value. */
f6e332e6 15360 if (h->u.weakdef != NULL)
252b5132 15361 {
f6e332e6
AM		 15362 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15363 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15364 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15365 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15366 return TRUE;
252b5132
RH		 15367 }
15368
ba93b8ac
DJ		 15369 /* If there are no non-GOT references, we do not need a copy
15370 relocation. */
15371 if (!h->non_got_ref)
15372 return TRUE;
15373
252b5132
RH		 15374 /* This is a reference to a symbol defined by a dynamic object which
15375 is not a function. */
15376
15377 /* If we are creating a shared library, we must presume that the
15378 only references to the symbol are via the global offset table.
15379 For such cases we need not do anything here; the relocations will
67687978
PB		 15380 be handled correctly by relocate_section. Relocatable executables
15381 can reference data in shared objects directly, so we don't need to
15382 do anything here. */
0e1862bb 15383 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15384 return TRUE;
252b5132
RH		 15385
15386 /* We must allocate the symbol in our .dynbss section, which will
15387 become part of the .bss section of the executable. There will be
15388 an entry for this symbol in the .dynsym section. The dynamic
15389 object will contain position independent code, so all references
15390 from the dynamic object to this symbol will go through the global
15391 offset table. The dynamic linker will use the .dynsym entry to
15392 determine the address it must put in the global offset table, so
15393 both the dynamic object and the regular object will refer to the
15394 same memory location for the variable. */
5522f910
NC		 15395 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15396 linker to copy the initial value out of the dynamic object and into
15397 the runtime process image. We need to remember the offset into the
00a97672 15398 .rel(a).bss section we are going to use. */
5474d94f
AM		 15399 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15400 {
15401 s = globals->root.sdynrelro;
15402 srel = globals->root.sreldynrelro;
15403 }
15404 else
15405 {
15406 s = globals->root.sdynbss;
15407 srel = globals->root.srelbss;
15408 }
5522f910
NC		 15409 if (info->nocopyreloc == 0
15410 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15411 && h->size != 0)
252b5132 15412 {
47beaa6a 15413 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15414 h->needs_copy = 1;
252b5132
RH		 15415 }
15416
6cabe1ea 15417 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15418}
15419
5e681ec4
PB		 15420/* Allocate space in .plt, .got and associated reloc sections for
15421 dynamic relocs. */
15422
15423static bfd_boolean
47beaa6a 15424allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15425{
15426 struct bfd_link_info *info;
15427 struct elf32_arm_link_hash_table *htab;
15428 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15429 struct elf_dyn_relocs *p;
5e681ec4
PB		 15430
15431 if (h->root.type == bfd_link_hash_indirect)
15432 return TRUE;
15433
e6a6bb22
AM		 15434 eh = (struct elf32_arm_link_hash_entry *) h;
15435
5e681ec4
PB		 15436 info = (struct bfd_link_info *) inf;
15437 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15438 if (htab == NULL)
15439 return FALSE;
5e681ec4 15440
34e77a92 15441 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15442 && h->plt.refcount > 0)
15443 {
15444 /* Make sure this symbol is output as a dynamic symbol.
15445 Undefined weak syms won't yet be marked as dynamic. */
15446 if (h->dynindx == -1
f5385ebf 15447 && !h->forced_local)
5e681ec4 15448 {
c152c796 15449 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15450 return FALSE;
15451 }
15452
34e77a92
RS		 15453 /* If the call in the PLT entry binds locally, the associated
15454 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15455 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15456 than the .plt section. */
15457 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15458 {
15459 eh->is_iplt = 1;
15460 if (eh->plt.noncall_refcount == 0
15461 && SYMBOL_REFERENCES_LOCAL (info, h))
15462 /* All non-call references can be resolved directly.
15463 This means that they can (and in some cases, must)
15464 resolve directly to the run-time target, rather than
15465 to the PLT. That in turns means that any .got entry
15466 would be equal to the .igot.plt entry, so there's
15467 no point having both. */
15468 h->got.refcount = 0;
15469 }
15470
0e1862bb 15471 if (bfd_link_pic (info)
34e77a92 15472 || eh->is_iplt
7359ea65 15473 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15474 {
34e77a92 15475 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15476
5e681ec4
PB		 15477 /* If this symbol is not defined in a regular file, and we are
15478 not generating a shared library, then set the symbol to this
15479 location in the .plt. This is required to make function
15480 pointers compare as equal between the normal executable and
15481 the shared library. */
0e1862bb 15482 if (! bfd_link_pic (info)
f5385ebf 15483 && !h->def_regular)
5e681ec4 15484 {
34e77a92 15485 h->root.u.def.section = htab->root.splt;
5e681ec4 15486 h->root.u.def.value = h->plt.offset;
5e681ec4 15487
67d74e43
DJ		 15488 /* Make sure the function is not marked as Thumb, in case
15489 it is the target of an ABS32 relocation, which will
15490 point to the PLT entry. */
39d911fc 15491 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15492 }
022f8312 15493
00a97672
RS		 15494 /* VxWorks executables have a second set of relocations for
15495 each PLT entry. They go in a separate relocation section,
15496 which is processed by the kernel loader. */
0e1862bb 15497 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15498 {
15499 /* There is a relocation for the initial PLT entry:
15500 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15501 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15502 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15503
15504 /* There are two extra relocations for each subsequent
15505 PLT entry: an R_ARM_32 relocation for the GOT entry,
15506 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15507 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15508 }
5e681ec4
PB		 15509 }
15510 else
15511 {
15512 h->plt.offset = (bfd_vma) -1;
f5385ebf 15513 h->needs_plt = 0;
5e681ec4
PB		 15514 }
15515 }
15516 else
15517 {
15518 h->plt.offset = (bfd_vma) -1;
f5385ebf 15519 h->needs_plt = 0;
5e681ec4
PB		 15520 }
15521
0855e32b
NS		 15522 eh = (struct elf32_arm_link_hash_entry *) h;
15523 eh->tlsdesc_got = (bfd_vma) -1;
15524
5e681ec4
PB		 15525 if (h->got.refcount > 0)
15526 {
15527 asection *s;
15528 bfd_boolean dyn;
ba93b8ac
DJ		 15529 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15530 int indx;
5e681ec4
PB		 15531
15532 /* Make sure this symbol is output as a dynamic symbol.
15533 Undefined weak syms won't yet be marked as dynamic. */
15534 if (h->dynindx == -1
f5385ebf 15535 && !h->forced_local)
5e681ec4 15536 {
c152c796 15537 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15538 return FALSE;
15539 }
15540
e5a52504
MM		 15541 if (!htab->symbian_p)
15542 {
362d30a1 15543 s = htab->root.sgot;
e5a52504 15544 h->got.offset = s->size;
ba93b8ac
DJ		 15545
15546 if (tls_type == GOT_UNKNOWN)
15547 abort ();
15548
15549 if (tls_type == GOT_NORMAL)
15550 /* Non-TLS symbols need one GOT slot. */
15551 s->size += 4;
15552 else
15553 {
99059e56
RM		 15554 if (tls_type & GOT_TLS_GDESC)
15555 {
0855e32b 15556 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15557 eh->tlsdesc_got
0855e32b
NS		 15558 = (htab->root.sgotplt->size
15559 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15560 htab->root.sgotplt->size += 8;
15561 h->got.offset = (bfd_vma) -2;
34e77a92 15562 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15563 reloc in the middle of .got.plt. */
99059e56
RM		 15564 htab->num_tls_desc++;
15565 }
0855e32b 15566
ba93b8ac 15567 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15568 {
15569 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15570 the symbol is both GD and GDESC, got.offset may
15571 have been overwritten. */
15572 h->got.offset = s->size;
15573 s->size += 8;
15574 }
15575
ba93b8ac
DJ		 15576 if (tls_type & GOT_TLS_IE)
15577 /* R_ARM_TLS_IE32 needs one GOT slot. */
15578 s->size += 4;
15579 }
15580
e5a52504 15581 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15582
15583 indx = 0;
0e1862bb
L		 15584 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15585 bfd_link_pic (info),
15586 h)
15587 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15588 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15589 indx = h->dynindx;
15590
15591 if (tls_type != GOT_NORMAL
0e1862bb 15592 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15593 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15594 || h->root.type != bfd_link_hash_undefweak))
15595 {
15596 if (tls_type & GOT_TLS_IE)
47beaa6a 15597 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15598
15599 if (tls_type & GOT_TLS_GD)
47beaa6a 15600 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15601
b38cadfb 15602 if (tls_type & GOT_TLS_GDESC)
0855e32b 15603 {
47beaa6a 15604 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15605 /* GDESC needs a trampoline to jump to. */
15606 htab->tls_trampoline = -1;
15607 }
15608
15609 /* Only GD needs it. GDESC just emits one relocation per
15610 2 entries. */
b38cadfb 15611 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15612 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15613 }
6f820c85 15614 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15615 {
15616 if (htab->root.dynamic_sections_created)
15617 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15618 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15619 }
34e77a92
RS		 15620 else if (h->type == STT_GNU_IFUNC
15621 && eh->plt.noncall_refcount == 0)
15622 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15623 they all resolve dynamically instead. Reserve room for the
15624 GOT entry's R_ARM_IRELATIVE relocation. */
15625 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15626 else if (bfd_link_pic (info)
15627 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15628 || h->root.type != bfd_link_hash_undefweak))
b436d854 15629 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15630 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15631 }
5e681ec4
PB		 15632 }
15633 else
15634 h->got.offset = (bfd_vma) -1;
15635
a4fd1a8e
PB		 15636 /* Allocate stubs for exported Thumb functions on v4t. */
15637 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15638 && h->def_regular
39d911fc 15639 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15640 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15641 {
15642 struct elf_link_hash_entry * th;
15643 struct bfd_link_hash_entry * bh;
15644 struct elf_link_hash_entry * myh;
15645 char name[1024];
15646 asection *s;
15647 bh = NULL;
15648 /* Create a new symbol to regist the real location of the function. */
15649 s = h->root.u.def.section;
906e58ca 15650 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15651 _bfd_generic_link_add_one_symbol (info, s->owner,
15652 name, BSF_GLOBAL, s,
15653 h->root.u.def.value,
15654 NULL, TRUE, FALSE, &bh);
15655
15656 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15657 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15658 myh->forced_local = 1;
39d911fc 15659 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15660 eh->export_glue = myh;
15661 th = record_arm_to_thumb_glue (info, h);
15662 /* Point the symbol at the stub. */
15663 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15664 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15665 h->root.u.def.section = th->root.u.def.section;
15666 h->root.u.def.value = th->root.u.def.value & ~1;
15667 }
15668
0bdcacaf 15669 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15670 return TRUE;
15671
15672 /* In the shared -Bsymbolic case, discard space allocated for
15673 dynamic pc-relative relocs against symbols which turn out to be
15674 defined in regular objects. For the normal shared case, discard
15675 space for pc-relative relocs that have become local due to symbol
15676 visibility changes. */
15677
0e1862bb 15678 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15679 {
469a3493
RM		 15680 /* Relocs that use pc_count are PC-relative forms, which will appear
15681 on something like ".long foo - ." or "movw REG, foo - .". We want
15682 calls to protected symbols to resolve directly to the function
15683 rather than going via the plt. If people want function pointer
15684 comparisons to work as expected then they should avoid writing
15685 assembly like ".long foo - .". */
ba93b8ac
DJ		 15686 if (SYMBOL_CALLS_LOCAL (info, h))
15687 {
0bdcacaf 15688 struct elf_dyn_relocs **pp;
ba93b8ac 15689
0bdcacaf 15690 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15691 {
15692 p->count -= p->pc_count;
15693 p->pc_count = 0;
15694 if (p->count == 0)
15695 *pp = p->next;
15696 else
15697 pp = &p->next;
15698 }
15699 }
15700
4dfe6ac6 15701 if (htab->vxworks_p)
3348747a 15702 {
0bdcacaf 15703 struct elf_dyn_relocs **pp;
3348747a 15704
0bdcacaf 15705 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15706 {
0bdcacaf 15707 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15708 *pp = p->next;
15709 else
15710 pp = &p->next;
15711 }
15712 }
15713
ba93b8ac 15714 /* Also discard relocs on undefined weak syms with non-default
99059e56 15715 visibility. */
0bdcacaf 15716 if (eh->dyn_relocs != NULL
5e681ec4 15717 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15718 {
15719 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15720 eh->dyn_relocs = NULL;
22d606e9
AM		 15721
15722 /* Make sure undefined weak symbols are output as a dynamic
15723 symbol in PIEs. */
15724 else if (h->dynindx == -1
15725 && !h->forced_local)
15726 {
15727 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15728 return FALSE;
15729 }
15730 }
15731
67687978
PB		 15732 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15733 && h->root.type == bfd_link_hash_new)
15734 {
15735 /* Output absolute symbols so that we can create relocations
15736 against them. For normal symbols we output a relocation
15737 against the section that contains them. */
15738 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15739 return FALSE;
15740 }
15741
5e681ec4
PB		 15742 }
15743 else
15744 {
15745 /* For the non-shared case, discard space for relocs against
15746 symbols which turn out to need copy relocs or are not
15747 dynamic. */
15748
f5385ebf
AM		 15749 if (!h->non_got_ref
15750 && ((h->def_dynamic
15751 && !h->def_regular)
5e681ec4
PB		 15752 || (htab->root.dynamic_sections_created
15753 && (h->root.type == bfd_link_hash_undefweak
15754 || h->root.type == bfd_link_hash_undefined))))
15755 {
15756 /* Make sure this symbol is output as a dynamic symbol.
15757 Undefined weak syms won't yet be marked as dynamic. */
15758 if (h->dynindx == -1
f5385ebf 15759 && !h->forced_local)
5e681ec4 15760 {
c152c796 15761 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15762 return FALSE;
15763 }
15764
15765 /* If that succeeded, we know we'll be keeping all the
15766 relocs. */
15767 if (h->dynindx != -1)
15768 goto keep;
15769 }
15770
0bdcacaf 15771 eh->dyn_relocs = NULL;
5e681ec4
PB		 15772
15773 keep: ;
15774 }
15775
15776 /* Finally, allocate space. */
0bdcacaf 15777 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15778 {
0bdcacaf 15779 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15780 if (h->type == STT_GNU_IFUNC
15781 && eh->plt.noncall_refcount == 0
15782 && SYMBOL_REFERENCES_LOCAL (info, h))
15783 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15784 else
15785 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15786 }
15787
15788 return TRUE;
15789}
15790
08d1f311
DJ		 15791/* Find any dynamic relocs that apply to read-only sections. */
15792
15793static bfd_boolean
8029a119 15794elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15795{
8029a119 15796 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15797 struct elf_dyn_relocs * p;
08d1f311 15798
08d1f311 15799 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15800 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15801 {
0bdcacaf 15802 asection *s = p->sec;
08d1f311
DJ		 15803
15804 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15805 {
15806 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15807
15808 info->flags |= DF_TEXTREL;
15809
15810 /* Not an error, just cut short the traversal. */
15811 return FALSE;
15812 }
15813 }
15814 return TRUE;
15815}
15816
d504ffc8
DJ		 15817void
15818bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15819 int byteswap_code)
15820{
15821 struct elf32_arm_link_hash_table *globals;
15822
15823 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15824 if (globals == NULL)
15825 return;
15826
d504ffc8
DJ		 15827 globals->byteswap_code = byteswap_code;
15828}
15829
252b5132
RH		 15830/* Set the sizes of the dynamic sections. */
15831
b34976b6 15832static bfd_boolean
57e8b36a
NC		 15833elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15834 struct bfd_link_info * info)
252b5132
RH		 15835{
15836 bfd * dynobj;
15837 asection * s;
b34976b6
AM		 15838 bfd_boolean plt;
15839 bfd_boolean relocs;
5e681ec4
PB		 15840 bfd *ibfd;
15841 struct elf32_arm_link_hash_table *htab;
252b5132 15842
5e681ec4 15843 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15844 if (htab == NULL)
15845 return FALSE;
15846
252b5132
RH		 15847 dynobj = elf_hash_table (info)->dynobj;
15848 BFD_ASSERT (dynobj != NULL);
39b41c9c 15849 check_use_blx (htab);
252b5132
RH		 15850
15851 if (elf_hash_table (info)->dynamic_sections_created)
15852 {
15853 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15854 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15855 {
3d4d4302 15856 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15857 BFD_ASSERT (s != NULL);
eea6121a 15858 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15859 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15860 }
15861 }
5e681ec4
PB		 15862
15863 /* Set up .got offsets for local syms, and space for local dynamic
15864 relocs. */
c72f2fb2 15865 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15866 {
5e681ec4
PB		 15867 bfd_signed_vma *local_got;
15868 bfd_signed_vma *end_local_got;
34e77a92 15869 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15870 char *local_tls_type;
0855e32b 15871 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15872 bfd_size_type locsymcount;
15873 Elf_Internal_Shdr *symtab_hdr;
15874 asection *srel;
4dfe6ac6 15875 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15876 unsigned int symndx;
5e681ec4 15877
0ffa91dd 15878 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15879 continue;
15880
15881 for (s = ibfd->sections; s != NULL; s = s->next)
15882 {
0bdcacaf 15883 struct elf_dyn_relocs *p;
5e681ec4 15884
0bdcacaf 15885 for (p = (struct elf_dyn_relocs *)
99059e56 15886 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15887 {
0bdcacaf
RS		 15888 if (!bfd_is_abs_section (p->sec)
15889 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15890 {
15891 /* Input section has been discarded, either because
15892 it is a copy of a linkonce section or due to
15893 linker script /DISCARD/, so we'll be discarding
15894 the relocs too. */
15895 }
3348747a 15896 else if (is_vxworks
0bdcacaf 15897 && strcmp (p->sec->output_section->name,
3348747a
NS		 15898 ".tls_vars") == 0)
15899 {
15900 /* Relocations in vxworks .tls_vars sections are
15901 handled specially by the loader. */
15902 }
5e681ec4
PB		 15903 else if (p->count != 0)
15904 {
0bdcacaf 15905 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15906 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15907 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15908 info->flags |= DF_TEXTREL;
15909 }
15910 }
15911 }
15912
15913 local_got = elf_local_got_refcounts (ibfd);
15914 if (!local_got)
15915 continue;
15916
0ffa91dd 15917 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15918 locsymcount = symtab_hdr->sh_info;
15919 end_local_got = local_got + locsymcount;
34e77a92 15920 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15921 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15922 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15923 symndx = 0;
362d30a1
RS		 15924 s = htab->root.sgot;
15925 srel = htab->root.srelgot;
0855e32b 15926 for (; local_got < end_local_got;
34e77a92
RS		 15927 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15928 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15929 {
0855e32b 15930 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15931 local_iplt = *local_iplt_ptr;
15932 if (local_iplt != NULL)
15933 {
15934 struct elf_dyn_relocs *p;
15935
15936 if (local_iplt->root.refcount > 0)
15937 {
15938 elf32_arm_allocate_plt_entry (info, TRUE,
15939 &local_iplt->root,
15940 &local_iplt->arm);
15941 if (local_iplt->arm.noncall_refcount == 0)
15942 /* All references to the PLT are calls, so all
15943 non-call references can resolve directly to the
15944 run-time target. This means that the .got entry
15945 would be the same as the .igot.plt entry, so there's
15946 no point creating both. */
15947 *local_got = 0;
15948 }
15949 else
15950 {
15951 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15952 local_iplt->root.offset = (bfd_vma) -1;
15953 }
15954
15955 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15956 {
15957 asection *psrel;
15958
15959 psrel = elf_section_data (p->sec)->sreloc;
15960 if (local_iplt->arm.noncall_refcount == 0)
15961 elf32_arm_allocate_irelocs (info, psrel, p->count);
15962 else
15963 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15964 }
15965 }
5e681ec4
PB		 15966 if (*local_got > 0)
15967 {
34e77a92
RS		 15968 Elf_Internal_Sym *isym;
15969
eea6121a 15970 *local_got = s->size;
ba93b8ac
DJ		 15971 if (*local_tls_type & GOT_TLS_GD)
15972 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15973 s->size += 8;
0855e32b
NS		 15974 if (*local_tls_type & GOT_TLS_GDESC)
15975 {
15976 *local_tlsdesc_gotent = htab->root.sgotplt->size
15977 - elf32_arm_compute_jump_table_size (htab);
15978 htab->root.sgotplt->size += 8;
15979 *local_got = (bfd_vma) -2;
34e77a92 15980 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15981 reloc in the middle of .got.plt. */
99059e56 15982 htab->num_tls_desc++;
0855e32b 15983 }
ba93b8ac
DJ		 15984 if (*local_tls_type & GOT_TLS_IE)
15985 s->size += 4;
ba93b8ac 15986
0855e32b
NS		 15987 if (*local_tls_type & GOT_NORMAL)
15988 {
15989 /* If the symbol is both GD and GDESC, *local_got
15990 may have been overwritten. */
15991 *local_got = s->size;
15992 s->size += 4;
15993 }
15994
34e77a92
RS		 15995 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15996 if (isym == NULL)
15997 return FALSE;
15998
15999 /* If all references to an STT_GNU_IFUNC PLT are calls,
16000 then all non-call references, including this GOT entry,
16001 resolve directly to the run-time target. */
16002 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16003 && (local_iplt == NULL
16004 || local_iplt->arm.noncall_refcount == 0))
16005 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 16006 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 16007 {
0e1862bb 16008 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 16009 || *local_tls_type & GOT_TLS_GD)
16010 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 16011
0e1862bb 16012 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16013 {
16014 elf32_arm_allocate_dynrelocs (info,
16015 htab->root.srelplt, 1);
16016 htab->tls_trampoline = -1;
16017 }
0855e32b 16018 }
5e681ec4
PB		 16019 }
16020 else
16021 *local_got = (bfd_vma) -1;
16022 }
252b5132
RH		 16023 }
16024
ba93b8ac
DJ		 16025 if (htab->tls_ldm_got.refcount > 0)
16026 {
16027 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16028 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 16029 htab->tls_ldm_got.offset = htab->root.sgot->size;
16030 htab->root.sgot->size += 8;
0e1862bb 16031 if (bfd_link_pic (info))
47beaa6a 16032 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16033 }
16034 else
16035 htab->tls_ldm_got.offset = -1;
16036
5e681ec4
PB		 16037 /* Allocate global sym .plt and .got entries, and space for global
16038 sym dynamic relocs. */
47beaa6a 16039 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16040
d504ffc8 16041 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16042 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16043 {
0ffa91dd 16044 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16045 continue;
16046
c7b8f16e
JB		 16047 /* Initialise mapping tables for code/data. */
16048 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16049
c7b8f16e 16050 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16051 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16052 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
dae82561 16053 _bfd_error_handler (_("Errors encountered processing file %B"), ibfd);
c7b8f16e 16054 }
d504ffc8 16055
3e6b1042
DJ		 16056 /* Allocate space for the glue sections now that we've sized them. */
16057 bfd_elf32_arm_allocate_interworking_sections (info);
16058
0855e32b
NS		 16059 /* For every jump slot reserved in the sgotplt, reloc_count is
16060 incremented. However, when we reserve space for TLS descriptors,
16061 it's not incremented, so in order to compute the space reserved
16062 for them, it suffices to multiply the reloc count by the jump
16063 slot size. */
16064 if (htab->root.srelplt)
16065 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16066
16067 if (htab->tls_trampoline)
16068 {
16069 if (htab->root.splt->size == 0)
16070 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16071
0855e32b
NS		 16072 htab->tls_trampoline = htab->root.splt->size;
16073 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16074
0855e32b 16075 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16076 PLT and GOT entries they require. */
0855e32b
NS		 16077 if (!(info->flags & DF_BIND_NOW))
16078 {
16079 htab->dt_tlsdesc_got = htab->root.sgot->size;
16080 htab->root.sgot->size += 4;
16081
16082 htab->dt_tlsdesc_plt = htab->root.splt->size;
16083 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16084 }
16085 }
16086
252b5132
RH		 16087 /* The check_relocs and adjust_dynamic_symbol entry points have
16088 determined the sizes of the various dynamic sections. Allocate
16089 memory for them. */
b34976b6
AM		 16090 plt = FALSE;
16091 relocs = FALSE;
252b5132
RH		 16092 for (s = dynobj->sections; s != NULL; s = s->next)
16093 {
16094 const char * name;
252b5132
RH		 16095
16096 if ((s->flags & SEC_LINKER_CREATED) == 0)
16097 continue;
16098
16099 /* It's OK to base decisions on the section name, because none
16100 of the dynobj section names depend upon the input files. */
16101 name = bfd_get_section_name (dynobj, s);
16102
34e77a92 16103 if (s == htab->root.splt)
252b5132 16104 {
c456f082
AM		 16105 /* Remember whether there is a PLT. */
16106 plt = s->size != 0;
252b5132 16107 }
0112cd26 16108 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16109 {
c456f082 16110 if (s->size != 0)
252b5132 16111 {
252b5132 16112 /* Remember whether there are any reloc sections other
00a97672 16113 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16114 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16115 relocs = TRUE;
252b5132
RH		 16116
16117 /* We use the reloc_count field as a counter if we need
16118 to copy relocs into the output file. */
16119 s->reloc_count = 0;
16120 }
16121 }
34e77a92
RS		 16122 else if (s != htab->root.sgot
16123 && s != htab->root.sgotplt
16124 && s != htab->root.iplt
16125 && s != htab->root.igotplt
5474d94f
AM		 16126 && s != htab->root.sdynbss
16127 && s != htab->root.sdynrelro)
252b5132
RH		 16128 {
16129 /* It's not one of our sections, so don't allocate space. */
16130 continue;
16131 }
16132
c456f082 16133 if (s->size == 0)
252b5132 16134 {
c456f082 16135 /* If we don't need this section, strip it from the
00a97672
RS		 16136 output file. This is mostly to handle .rel(a).bss and
16137 .rel(a).plt. We must create both sections in
c456f082
AM		 16138 create_dynamic_sections, because they must be created
16139 before the linker maps input sections to output
16140 sections. The linker does that before
16141 adjust_dynamic_symbol is called, and it is that
16142 function which decides whether anything needs to go
16143 into these sections. */
8423293d 16144 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16145 continue;
16146 }
16147
c456f082
AM		 16148 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16149 continue;
16150
252b5132 16151 /* Allocate memory for the section contents. */
21d799b5 16152 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16153 if (s->contents == NULL)
b34976b6 16154 return FALSE;
252b5132
RH		 16155 }
16156
16157 if (elf_hash_table (info)->dynamic_sections_created)
16158 {
16159 /* Add some entries to the .dynamic section. We fill in the
16160 values later, in elf32_arm_finish_dynamic_sections, but we
16161 must add the entries now so that we get the correct size for
16162 the .dynamic section. The DT_DEBUG entry is filled in by the
16163 dynamic linker and used by the debugger. */
dc810e39 16164#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16165 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16166
0e1862bb 16167 if (bfd_link_executable (info))
252b5132 16168 {
dc810e39 16169 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16170 return FALSE;
252b5132
RH		 16171 }
16172
16173 if (plt)
16174 {
dc810e39
AM		 16175 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16176 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16177 || !add_dynamic_entry (DT_PLTREL,
16178 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16179 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16180 return FALSE;
0855e32b 16181
5025eb7c
AO		 16182 if (htab->dt_tlsdesc_plt
16183 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16184 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16185 return FALSE;
252b5132
RH		 16186 }
16187
16188 if (relocs)
16189 {
00a97672
RS		 16190 if (htab->use_rel)
16191 {
16192 if (!add_dynamic_entry (DT_REL, 0)
16193 || !add_dynamic_entry (DT_RELSZ, 0)
16194 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16195 return FALSE;
16196 }
16197 else
16198 {
16199 if (!add_dynamic_entry (DT_RELA, 0)
16200 || !add_dynamic_entry (DT_RELASZ, 0)
16201 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16202 return FALSE;
16203 }
252b5132
RH		 16204 }
16205
08d1f311
DJ		 16206 /* If any dynamic relocs apply to a read-only section,
16207 then we need a DT_TEXTREL entry. */
16208 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16209 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16210 info);
08d1f311 16211
99e4ae17 16212 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16213 {
dc810e39 16214 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16215 return FALSE;
252b5132 16216 }
7a2b07ff
NS		 16217 if (htab->vxworks_p
16218 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16219 return FALSE;
252b5132 16220 }
8532796c 16221#undef add_dynamic_entry
252b5132 16222
b34976b6 16223 return TRUE;
252b5132
RH		 16224}
16225
0855e32b
NS		 16226/* Size sections even though they're not dynamic. We use it to setup
16227 _TLS_MODULE_BASE_, if needed. */
16228
16229static bfd_boolean
16230elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16231 struct bfd_link_info *info)
0855e32b
NS		 16232{
16233 asection *tls_sec;
16234
0e1862bb 16235 if (bfd_link_relocatable (info))
0855e32b
NS		 16236 return TRUE;
16237
16238 tls_sec = elf_hash_table (info)->tls_sec;
16239
16240 if (tls_sec)
16241 {
16242 struct elf_link_hash_entry *tlsbase;
16243
16244 tlsbase = elf_link_hash_lookup
16245 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16246
16247 if (tlsbase)
99059e56
RM		 16248 {
16249 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16250 const struct elf_backend_data *bed
99059e56 16251 = get_elf_backend_data (output_bfd);
0855e32b 16252
99059e56 16253 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16254 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16255 tls_sec, 0, NULL, FALSE,
16256 bed->collect, &bh)))
16257 return FALSE;
b38cadfb 16258
99059e56
RM		 16259 tlsbase->type = STT_TLS;
16260 tlsbase = (struct elf_link_hash_entry *)bh;
16261 tlsbase->def_regular = 1;
16262 tlsbase->other = STV_HIDDEN;
16263 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16264 }
16265 }
16266 return TRUE;
16267}
16268
252b5132
RH		 16269/* Finish up dynamic symbol handling. We set the contents of various
16270 dynamic sections here. */
16271
b34976b6 16272static bfd_boolean
906e58ca
NC		 16273elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16274 struct bfd_link_info * info,
16275 struct elf_link_hash_entry * h,
16276 Elf_Internal_Sym * sym)
252b5132 16277{
e5a52504 16278 struct elf32_arm_link_hash_table *htab;
b7693d02 16279 struct elf32_arm_link_hash_entry *eh;
252b5132 16280
e5a52504 16281 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16282 if (htab == NULL)
16283 return FALSE;
16284
b7693d02 16285 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16286
16287 if (h->plt.offset != (bfd_vma) -1)
16288 {
34e77a92 16289 if (!eh->is_iplt)
e5a52504 16290 {
34e77a92 16291 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16292 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16293 h->dynindx, 0))
16294 return FALSE;
e5a52504 16295 }
57e8b36a 16296
f5385ebf 16297 if (!h->def_regular)
252b5132
RH		 16298 {
16299 /* Mark the symbol as undefined, rather than as defined in
3a635617 16300 the .plt section. */
252b5132 16301 sym->st_shndx = SHN_UNDEF;
3a635617 16302 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16303 Otherwise, the PLT entry would provide a definition for
16304 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16305 and so the symbol would never be NULL. Leave the value if
16306 there were any relocations where pointer equality matters
16307 (this is a clue for the dynamic linker, to make function
16308 pointer comparisons work between an application and shared
16309 library). */
97323ad1 16310 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16311 sym->st_value = 0;
252b5132 16312 }
34e77a92
RS		 16313 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16314 {
16315 /* At least one non-call relocation references this .iplt entry,
16316 so the .iplt entry is the function's canonical address. */
16317 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16318 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16319 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16320 (output_bfd, htab->root.iplt->output_section));
16321 sym->st_value = (h->plt.offset
16322 + htab->root.iplt->output_section->vma
16323 + htab->root.iplt->output_offset);
16324 }
252b5132
RH		 16325 }
16326
f5385ebf 16327 if (h->needs_copy)
252b5132
RH		 16328 {
16329 asection * s;
947216bf 16330 Elf_Internal_Rela rel;
252b5132
RH		 16331
16332 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16333 BFD_ASSERT (h->dynindx != -1
16334 && (h->root.type == bfd_link_hash_defined
16335 || h->root.type == bfd_link_hash_defweak));
16336
00a97672 16337 rel.r_addend = 0;
252b5132
RH		 16338 rel.r_offset = (h->root.u.def.value
16339 + h->root.u.def.section->output_section->vma
16340 + h->root.u.def.section->output_offset);
16341 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 16342 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 16343 s = htab->root.sreldynrelro;
16344 else
16345 s = htab->root.srelbss;
47beaa6a 16346 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16347 }
16348
00a97672
RS		 16349 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16350 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16351 to the ".got" section. */
9637f6ef 16352 if (h == htab->root.hdynamic
00a97672 16353 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16354 sym->st_shndx = SHN_ABS;
16355
b34976b6 16356 return TRUE;
252b5132
RH		 16357}
16358
0855e32b
NS		 16359static void
16360arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16361 void *contents,
16362 const unsigned long *template, unsigned count)
16363{
16364 unsigned ix;
b38cadfb 16365
0855e32b
NS		 16366 for (ix = 0; ix != count; ix++)
16367 {
16368 unsigned long insn = template[ix];
16369
16370 /* Emit mov pc,rx if bx is not permitted. */
16371 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16372 insn = (insn & 0xf000000f) | 0x01a0f000;
16373 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16374 }
16375}
16376
99059e56
RM		 16377/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16378 other variants, NaCl needs this entry in a static executable's
16379 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16380 zero. For .iplt really only the last bundle is useful, and .iplt
16381 could have a shorter first entry, with each individual PLT entry's
16382 relative branch calculated differently so it targets the last
16383 bundle instead of the instruction before it (labelled .Lplt_tail
16384 above). But it's simpler to keep the size and layout of PLT0
16385 consistent with the dynamic case, at the cost of some dead code at
16386 the start of .iplt and the one dead store to the stack at the start
16387 of .Lplt_tail. */
16388static void
16389arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16390 asection *plt, bfd_vma got_displacement)
16391{
16392 unsigned int i;
16393
16394 put_arm_insn (htab, output_bfd,
16395 elf32_arm_nacl_plt0_entry[0]
16396 | arm_movw_immediate (got_displacement),
16397 plt->contents + 0);
16398 put_arm_insn (htab, output_bfd,
16399 elf32_arm_nacl_plt0_entry[1]
16400 | arm_movt_immediate (got_displacement),
16401 plt->contents + 4);
16402
16403 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16404 put_arm_insn (htab, output_bfd,
16405 elf32_arm_nacl_plt0_entry[i],
16406 plt->contents + (i * 4));
16407}
16408
252b5132
RH		 16409/* Finish up the dynamic sections. */
16410
b34976b6 16411static bfd_boolean
57e8b36a 16412elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16413{
16414 bfd * dynobj;
16415 asection * sgot;
16416 asection * sdyn;
4dfe6ac6
NC		 16417 struct elf32_arm_link_hash_table *htab;
16418
16419 htab = elf32_arm_hash_table (info);
16420 if (htab == NULL)
16421 return FALSE;
252b5132
RH		 16422
16423 dynobj = elf_hash_table (info)->dynobj;
16424
362d30a1 16425 sgot = htab->root.sgotplt;
894891db
NC		 16426 /* A broken linker script might have discarded the dynamic sections.
16427 Catch this here so that we do not seg-fault later on. */
16428 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16429 return FALSE;
3d4d4302 16430 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16431
16432 if (elf_hash_table (info)->dynamic_sections_created)
16433 {
16434 asection *splt;
16435 Elf32_External_Dyn *dyncon, *dynconend;
16436
362d30a1 16437 splt = htab->root.splt;
24a1ba0f 16438 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16439 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16440
16441 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16442 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16443
252b5132
RH		 16444 for (; dyncon < dynconend; dyncon++)
16445 {
16446 Elf_Internal_Dyn dyn;
16447 const char * name;
16448 asection * s;
16449
16450 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16451
16452 switch (dyn.d_tag)
16453 {
229fcec5
MM		 16454 unsigned int type;
16455
252b5132 16456 default:
7a2b07ff
NS		 16457 if (htab->vxworks_p
16458 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16459 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16460 break;
16461
229fcec5
MM		 16462 case DT_HASH:
16463 name = ".hash";
16464 goto get_vma_if_bpabi;
16465 case DT_STRTAB:
16466 name = ".dynstr";
16467 goto get_vma_if_bpabi;
16468 case DT_SYMTAB:
16469 name = ".dynsym";
16470 goto get_vma_if_bpabi;
c0042f5d
MM		 16471 case DT_VERSYM:
16472 name = ".gnu.version";
16473 goto get_vma_if_bpabi;
16474 case DT_VERDEF:
16475 name = ".gnu.version_d";
16476 goto get_vma_if_bpabi;
16477 case DT_VERNEED:
16478 name = ".gnu.version_r";
16479 goto get_vma_if_bpabi;
16480
252b5132 16481 case DT_PLTGOT:
4ade44b7 16482 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16483 goto get_vma;
16484 case DT_JMPREL:
00a97672 16485 name = RELOC_SECTION (htab, ".plt");
252b5132 16486 get_vma:
4ade44b7 16487 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16488 if (s == NULL)
16489 {
4eca0228 16490 _bfd_error_handler
4ade44b7 16491 (_("could not find section %s"), name);
05456594
NC		 16492 bfd_set_error (bfd_error_invalid_operation);
16493 return FALSE;
16494 }
229fcec5 16495 if (!htab->symbian_p)
4ade44b7 16496 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16497 else
16498 /* In the BPABI, tags in the PT_DYNAMIC section point
16499 at the file offset, not the memory address, for the
16500 convenience of the post linker. */
4ade44b7 16501 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16502 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16503 break;
16504
229fcec5
MM		 16505 get_vma_if_bpabi:
16506 if (htab->symbian_p)
16507 goto get_vma;
16508 break;
16509
252b5132 16510 case DT_PLTRELSZ:
362d30a1 16511 s = htab->root.srelplt;
252b5132 16512 BFD_ASSERT (s != NULL);
eea6121a 16513 dyn.d_un.d_val = s->size;
252b5132
RH		 16514 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16515 break;
906e58ca 16516
252b5132 16517 case DT_RELSZ:
00a97672 16518 case DT_RELASZ:
229fcec5
MM		 16519 case DT_REL:
16520 case DT_RELA:
229fcec5
MM		 16521 /* In the BPABI, the DT_REL tag must point at the file
16522 offset, not the VMA, of the first relocation
16523 section. So, we use code similar to that in
16524 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16525 relocation section, since relocation sections are
16526 never allocated under the BPABI. PLT relocs are also
16527 included. */
229fcec5
MM		 16528 if (htab->symbian_p)
16529 {
16530 unsigned int i;
16531 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16532 ? SHT_REL : SHT_RELA);
16533 dyn.d_un.d_val = 0;
16534 for (i = 1; i < elf_numsections (output_bfd); i++)
16535 {
906e58ca 16536 Elf_Internal_Shdr *hdr
229fcec5
MM		 16537 = elf_elfsections (output_bfd)[i];
16538 if (hdr->sh_type == type)
16539 {
906e58ca 16540 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16541 || dyn.d_tag == DT_RELASZ)
16542 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16543 else if ((ufile_ptr) hdr->sh_offset
16544 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16545 dyn.d_un.d_val = hdr->sh_offset;
16546 }
16547 }
16548 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16549 }
252b5132 16550 break;
88f7bcd5 16551
0855e32b 16552 case DT_TLSDESC_PLT:
99059e56 16553 s = htab->root.splt;
0855e32b
NS		 16554 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16555 + htab->dt_tlsdesc_plt);
16556 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16557 break;
16558
16559 case DT_TLSDESC_GOT:
99059e56 16560 s = htab->root.sgot;
0855e32b 16561 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16562 + htab->dt_tlsdesc_got);
0855e32b
NS		 16563 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16564 break;
16565
88f7bcd5
NC		 16566 /* Set the bottom bit of DT_INIT/FINI if the
16567 corresponding function is Thumb. */
16568 case DT_INIT:
16569 name = info->init_function;
16570 goto get_sym;
16571 case DT_FINI:
16572 name = info->fini_function;
16573 get_sym:
16574 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16575 then there is nothing to adjust. */
88f7bcd5
NC		 16576 if (dyn.d_un.d_val != 0)
16577 {
16578 struct elf_link_hash_entry * eh;
16579
16580 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16581 FALSE, FALSE, TRUE);
39d911fc
TP		 16582 if (eh != NULL
16583 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16584 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16585 {
16586 dyn.d_un.d_val |= 1;
b34976b6 16587 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16588 }
16589 }
16590 break;
252b5132
RH		 16591 }
16592 }
16593
24a1ba0f 16594 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16595 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16596 {
00a97672
RS		 16597 const bfd_vma *plt0_entry;
16598 bfd_vma got_address, plt_address, got_displacement;
16599
16600 /* Calculate the addresses of the GOT and PLT. */
16601 got_address = sgot->output_section->vma + sgot->output_offset;
16602 plt_address = splt->output_section->vma + splt->output_offset;
16603
16604 if (htab->vxworks_p)
16605 {
16606 /* The VxWorks GOT is relocated by the dynamic linker.
16607 Therefore, we must emit relocations rather than simply
16608 computing the values now. */
16609 Elf_Internal_Rela rel;
16610
16611 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16612 put_arm_insn (htab, output_bfd, plt0_entry[0],
16613 splt->contents + 0);
16614 put_arm_insn (htab, output_bfd, plt0_entry[1],
16615 splt->contents + 4);
16616 put_arm_insn (htab, output_bfd, plt0_entry[2],
16617 splt->contents + 8);
00a97672
RS		 16618 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16619
8029a119 16620 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16621 rel.r_offset = plt_address + 12;
16622 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16623 rel.r_addend = 0;
16624 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16625 htab->srelplt2->contents);
16626 }
b38cadfb 16627 else if (htab->nacl_p)
99059e56
RM		 16628 arm_nacl_put_plt0 (htab, output_bfd, splt,
16629 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16630 else if (using_thumb_only (htab))
16631 {
16632 got_displacement = got_address - (plt_address + 12);
16633
16634 plt0_entry = elf32_thumb2_plt0_entry;
16635 put_arm_insn (htab, output_bfd, plt0_entry[0],
16636 splt->contents + 0);
16637 put_arm_insn (htab, output_bfd, plt0_entry[1],
16638 splt->contents + 4);
16639 put_arm_insn (htab, output_bfd, plt0_entry[2],
16640 splt->contents + 8);
16641
16642 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16643 }
00a97672
RS		 16644 else
16645 {
16646 got_displacement = got_address - (plt_address + 16);
16647
16648 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16649 put_arm_insn (htab, output_bfd, plt0_entry[0],
16650 splt->contents + 0);
16651 put_arm_insn (htab, output_bfd, plt0_entry[1],
16652 splt->contents + 4);
16653 put_arm_insn (htab, output_bfd, plt0_entry[2],
16654 splt->contents + 8);
16655 put_arm_insn (htab, output_bfd, plt0_entry[3],
16656 splt->contents + 12);
5e681ec4 16657
5e681ec4 16658#ifdef FOUR_WORD_PLT
00a97672
RS		 16659 /* The displacement value goes in the otherwise-unused
16660 last word of the second entry. */
16661 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16662#else
00a97672 16663 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16664#endif
00a97672 16665 }
f7a74f8c 16666 }
252b5132
RH		 16667
16668 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16669 really seem like the right value. */
74541ad4
AM		 16670 if (splt->output_section->owner == output_bfd)
16671 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16672
0855e32b
NS		 16673 if (htab->dt_tlsdesc_plt)
16674 {
16675 bfd_vma got_address
16676 = sgot->output_section->vma + sgot->output_offset;
16677 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16678 + htab->root.sgot->output_offset);
16679 bfd_vma plt_address
16680 = splt->output_section->vma + splt->output_offset;
16681
b38cadfb 16682 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16683 splt->contents + htab->dt_tlsdesc_plt,
16684 dl_tlsdesc_lazy_trampoline, 6);
16685
16686 bfd_put_32 (output_bfd,
16687 gotplt_address + htab->dt_tlsdesc_got
16688 - (plt_address + htab->dt_tlsdesc_plt)
16689 - dl_tlsdesc_lazy_trampoline[6],
16690 splt->contents + htab->dt_tlsdesc_plt + 24);
16691 bfd_put_32 (output_bfd,
16692 got_address - (plt_address + htab->dt_tlsdesc_plt)
16693 - dl_tlsdesc_lazy_trampoline[7],
16694 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16695 }
16696
16697 if (htab->tls_trampoline)
16698 {
b38cadfb 16699 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16700 splt->contents + htab->tls_trampoline,
16701 tls_trampoline, 3);
16702#ifdef FOUR_WORD_PLT
16703 bfd_put_32 (output_bfd, 0x00000000,
16704 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16705#endif
0855e32b
NS		 16706 }
16707
0e1862bb
L		 16708 if (htab->vxworks_p
16709 && !bfd_link_pic (info)
16710 && htab->root.splt->size > 0)
00a97672
RS		 16711 {
16712 /* Correct the .rel(a).plt.unloaded relocations. They will have
16713 incorrect symbol indexes. */
16714 int num_plts;
eed62c48 16715 unsigned char *p;
00a97672 16716
362d30a1 16717 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16718 / htab->plt_entry_size);
16719 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16720
16721 for (; num_plts; num_plts--)
16722 {
16723 Elf_Internal_Rela rel;
16724
16725 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16726 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16727 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16728 p += RELOC_SIZE (htab);
16729
16730 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16731 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16732 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16733 p += RELOC_SIZE (htab);
16734 }
16735 }
252b5132
RH		 16736 }
16737
99059e56
RM		 16738 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16739 /* NaCl uses a special first entry in .iplt too. */
16740 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16741
252b5132 16742 /* Fill in the first three entries in the global offset table. */
229fcec5 16743 if (sgot)
252b5132 16744 {
229fcec5
MM		 16745 if (sgot->size > 0)
16746 {
16747 if (sdyn == NULL)
16748 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16749 else
16750 bfd_put_32 (output_bfd,
16751 sdyn->output_section->vma + sdyn->output_offset,
16752 sgot->contents);
16753 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16754 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16755 }
252b5132 16756
229fcec5
MM		 16757 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16758 }
252b5132 16759
b34976b6 16760 return TRUE;
252b5132
RH		 16761}
16762
ba96a88f 16763static void
57e8b36a 16764elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16765{
9b485d32 16766 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16767 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16768 struct elf_segment_map *m;
ba96a88f
NC		 16769
16770 i_ehdrp = elf_elfheader (abfd);
16771
94a3258f
PB		 16772 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16773 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16774 else
7394f108 16775 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16776 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16777
93204d3a
PB		 16778 if (link_info)
16779 {
16780 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16781 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16782 i_ehdrp->e_flags |= EF_ARM_BE8;
16783 }
3bfcb652
NC		 16784
16785 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16786 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16787 {
16788 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16789 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16790 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16791 else
16792 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16793 }
ac4c9b04
MG		 16794
16795 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16796 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16797 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16798 {
16799 unsigned int j;
16800
16801 if (m->count == 0)
16802 continue;
16803 for (j = 0; j < m->count; j++)
16804 {
f0728ee3 16805 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16806 break;
16807 }
16808 if (j == m->count)
16809 {
16810 m->p_flags = PF_X;
16811 m->p_flags_valid = 1;
16812 }
16813 }
ba96a88f
NC		 16814}
16815
99e4ae17 16816static enum elf_reloc_type_class
7e612e98
AM		 16817elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16818 const asection *rel_sec ATTRIBUTE_UNUSED,
16819 const Elf_Internal_Rela *rela)
99e4ae17 16820{
f51e552e 16821 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16822 {
16823 case R_ARM_RELATIVE:
16824 return reloc_class_relative;
16825 case R_ARM_JUMP_SLOT:
16826 return reloc_class_plt;
16827 case R_ARM_COPY:
16828 return reloc_class_copy;
109575d7
JW		 16829 case R_ARM_IRELATIVE:
16830 return reloc_class_ifunc;
99e4ae17
AJ		 16831 default:
16832 return reloc_class_normal;
16833 }
16834}
16835
e489d0ae 16836static void
57e8b36a 16837elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16838{
5a6c6817 16839 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16840}
16841
40a18ebd
NC		 16842/* Return TRUE if this is an unwinding table entry. */
16843
16844static bfd_boolean
16845is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16846{
0112cd26
NC		 16847 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16848 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16849}
16850
16851
16852/* Set the type and flags for an ARM section. We do this by
16853 the section name, which is a hack, but ought to work. */
16854
16855static bfd_boolean
16856elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16857{
16858 const char * name;
16859
16860 name = bfd_get_section_name (abfd, sec);
16861
16862 if (is_arm_elf_unwind_section_name (abfd, name))
16863 {
16864 hdr->sh_type = SHT_ARM_EXIDX;
16865 hdr->sh_flags |= SHF_LINK_ORDER;
16866 }
ac4c9b04 16867
f0728ee3
AV		 16868 if (sec->flags & SEC_ELF_PURECODE)
16869 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16870
40a18ebd
NC		 16871 return TRUE;
16872}
16873
6dc132d9
L		 16874/* Handle an ARM specific section when reading an object file. This is
16875 called when bfd_section_from_shdr finds a section with an unknown
16876 type. */
40a18ebd
NC		 16877
16878static bfd_boolean
16879elf32_arm_section_from_shdr (bfd *abfd,
16880 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16881 const char *name,
16882 int shindex)
40a18ebd
NC		 16883{
16884 /* There ought to be a place to keep ELF backend specific flags, but
16885 at the moment there isn't one. We just keep track of the
16886 sections by their name, instead. Fortunately, the ABI gives
16887 names for all the ARM specific sections, so we will probably get
16888 away with this. */
16889 switch (hdr->sh_type)
16890 {
16891 case SHT_ARM_EXIDX:
0951f019
RE		 16892 case SHT_ARM_PREEMPTMAP:
16893 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16894 break;
16895
16896 default:
16897 return FALSE;
16898 }
16899
6dc132d9 16900 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16901 return FALSE;
16902
16903 return TRUE;
16904}
e489d0ae 16905
44444f50
NC		 16906static _arm_elf_section_data *
16907get_arm_elf_section_data (asection * sec)
16908{
47b2e99c
JZ		 16909 if (sec && sec->owner && is_arm_elf (sec->owner))
16910 return elf32_arm_section_data (sec);
44444f50
NC		 16911 else
16912 return NULL;
8e3de13a
NC		 16913}
16914
4e617b1e
PB		 16915typedef struct
16916{
57402f1e 16917 void *flaginfo;
4e617b1e 16918 struct bfd_link_info *info;
91a5743d
PB		 16919 asection *sec;
16920 int sec_shndx;
6e0b88f1
AM		 16921 int (*func) (void *, const char *, Elf_Internal_Sym *,
16922 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16923} output_arch_syminfo;
16924
16925enum map_symbol_type
16926{
16927 ARM_MAP_ARM,
16928 ARM_MAP_THUMB,
16929 ARM_MAP_DATA
16930};
16931
16932
7413f23f 16933/* Output a single mapping symbol. */
4e617b1e
PB		 16934
16935static bfd_boolean
7413f23f
DJ		 16936elf32_arm_output_map_sym (output_arch_syminfo *osi,
16937 enum map_symbol_type type,
16938 bfd_vma offset)
4e617b1e
PB		 16939{
16940 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16941 Elf_Internal_Sym sym;
16942
91a5743d
PB		 16943 sym.st_value = osi->sec->output_section->vma
16944 + osi->sec->output_offset
16945 + offset;
4e617b1e
PB		 16946 sym.st_size = 0;
16947 sym.st_other = 0;
16948 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16949 sym.st_shndx = osi->sec_shndx;
35fc36a8 16950 sym.st_target_internal = 0;
fe33d2fa 16951 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16952 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16953}
16954
34e77a92
RS		 16955/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16956 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16957
16958static bfd_boolean
34e77a92
RS		 16959elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16960 bfd_boolean is_iplt_entry_p,
16961 union gotplt_union *root_plt,
16962 struct arm_plt_info *arm_plt)
4e617b1e 16963{
4e617b1e 16964 struct elf32_arm_link_hash_table *htab;
34e77a92 16965 bfd_vma addr, plt_header_size;
4e617b1e 16966
34e77a92 16967 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16968 return TRUE;
16969
4dfe6ac6
NC		 16970 htab = elf32_arm_hash_table (osi->info);
16971 if (htab == NULL)
16972 return FALSE;
16973
34e77a92
RS		 16974 if (is_iplt_entry_p)
16975 {
16976 osi->sec = htab->root.iplt;
16977 plt_header_size = 0;
16978 }
16979 else
16980 {
16981 osi->sec = htab->root.splt;
16982 plt_header_size = htab->plt_header_size;
16983 }
16984 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16985 (osi->info->output_bfd, osi->sec->output_section));
16986
16987 addr = root_plt->offset & -2;
4e617b1e
PB		 16988 if (htab->symbian_p)
16989 {
7413f23f 16990 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16991 return FALSE;
7413f23f 16992 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16993 return FALSE;
16994 }
16995 else if (htab->vxworks_p)
16996 {
7413f23f 16997 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16998 return FALSE;
7413f23f 16999 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17000 return FALSE;
7413f23f 17001 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17002 return FALSE;
7413f23f 17003 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17004 return FALSE;
17005 }
b38cadfb
NC		 17006 else if (htab->nacl_p)
17007 {
17008 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17009 return FALSE;
17010 }
eed94f8f
NC		 17011 else if (using_thumb_only (htab))
17012 {
17013 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17014 return FALSE;
6a631e86 17015 }
4e617b1e
PB		 17016 else
17017 {
34e77a92 17018 bfd_boolean thumb_stub_p;
bd97cb95 17019
34e77a92
RS		 17020 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17021 if (thumb_stub_p)
4e617b1e 17022 {
7413f23f 17023 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17024 return FALSE;
17025 }
17026#ifdef FOUR_WORD_PLT
7413f23f 17027 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17028 return FALSE;
7413f23f 17029 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17030 return FALSE;
17031#else
906e58ca 17032 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17033 so only need to output a mapping symbol for the first PLT entry and
17034 entries with thumb thunks. */
34e77a92 17035 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17036 {
7413f23f 17037 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17038 return FALSE;
17039 }
17040#endif
17041 }
17042
17043 return TRUE;
17044}
17045
34e77a92
RS		 17046/* Output mapping symbols for PLT entries associated with H. */
17047
17048static bfd_boolean
17049elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17050{
17051 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17052 struct elf32_arm_link_hash_entry *eh;
17053
17054 if (h->root.type == bfd_link_hash_indirect)
17055 return TRUE;
17056
17057 if (h->root.type == bfd_link_hash_warning)
17058 /* When warning symbols are created, they **replace** the "real"
17059 entry in the hash table, thus we never get to see the real
17060 symbol in a hash traversal. So look at it now. */
17061 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17062
17063 eh = (struct elf32_arm_link_hash_entry *) h;
17064 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17065 &h->plt, &eh->plt);
17066}
17067
4f4faa4d
TP		 17068/* Bind a veneered symbol to its veneer identified by its hash entry
17069 STUB_ENTRY. The veneered location thus loose its symbol. */
17070
17071static void
17072arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17073{
17074 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17075
17076 BFD_ASSERT (hash);
17077 hash->root.root.u.def.section = stub_entry->stub_sec;
17078 hash->root.root.u.def.value = stub_entry->stub_offset;
17079 hash->root.size = stub_entry->stub_size;
17080}
17081
7413f23f
DJ		 17082/* Output a single local symbol for a generated stub. */
17083
17084static bfd_boolean
17085elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17086 bfd_vma offset, bfd_vma size)
17087{
7413f23f
DJ		 17088 Elf_Internal_Sym sym;
17089
7413f23f
DJ		 17090 sym.st_value = osi->sec->output_section->vma
17091 + osi->sec->output_offset
17092 + offset;
17093 sym.st_size = size;
17094 sym.st_other = 0;
17095 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17096 sym.st_shndx = osi->sec_shndx;
35fc36a8 17097 sym.st_target_internal = 0;
57402f1e 17098 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17099}
4e617b1e 17100
da5938a2 17101static bfd_boolean
8029a119
NC		 17102arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17103 void * in_arg)
da5938a2
NC		 17104{
17105 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17106 asection *stub_sec;
17107 bfd_vma addr;
7413f23f 17108 char *stub_name;
9a008db3 17109 output_arch_syminfo *osi;
d3ce72d0 17110 const insn_sequence *template_sequence;
461a49ca
DJ		 17111 enum stub_insn_type prev_type;
17112 int size;
17113 int i;
17114 enum map_symbol_type sym_type;
da5938a2
NC		 17115
17116 /* Massage our args to the form they really have. */
17117 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17118 osi = (output_arch_syminfo *) in_arg;
da5938a2 17119
da5938a2
NC		 17120 stub_sec = stub_entry->stub_sec;
17121
17122 /* Ensure this stub is attached to the current section being
7413f23f 17123 processed. */
da5938a2
NC		 17124 if (stub_sec != osi->sec)
17125 return TRUE;
17126
7413f23f 17127 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17128 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17129
17130 if (arm_stub_sym_claimed (stub_entry->stub_type))
17131 arm_stub_claim_sym (stub_entry);
17132 else
7413f23f 17133 {
4f4faa4d
TP		 17134 stub_name = stub_entry->output_name;
17135 switch (template_sequence[0].type)
17136 {
17137 case ARM_TYPE:
17138 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17139 stub_entry->stub_size))
17140 return FALSE;
17141 break;
17142 case THUMB16_TYPE:
17143 case THUMB32_TYPE:
17144 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17145 stub_entry->stub_size))
17146 return FALSE;
17147 break;
17148 default:
17149 BFD_FAIL ();
17150 return 0;
17151 }
7413f23f 17152 }
da5938a2 17153
461a49ca
DJ		 17154 prev_type = DATA_TYPE;
17155 size = 0;
17156 for (i = 0; i < stub_entry->stub_template_size; i++)
17157 {
d3ce72d0 17158 switch (template_sequence[i].type)
461a49ca
DJ		 17159 {
17160 case ARM_TYPE:
17161 sym_type = ARM_MAP_ARM;
17162 break;
17163
17164 case THUMB16_TYPE:
48229727 17165 case THUMB32_TYPE:
461a49ca
DJ		 17166 sym_type = ARM_MAP_THUMB;
17167 break;
17168
17169 case DATA_TYPE:
17170 sym_type = ARM_MAP_DATA;
17171 break;
17172
17173 default:
17174 BFD_FAIL ();
4e31c731 17175 return FALSE;
461a49ca
DJ		 17176 }
17177
d3ce72d0 17178 if (template_sequence[i].type != prev_type)
461a49ca 17179 {
d3ce72d0 17180 prev_type = template_sequence[i].type;
461a49ca
DJ		 17181 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17182 return FALSE;
17183 }
17184
d3ce72d0 17185 switch (template_sequence[i].type)
461a49ca
DJ		 17186 {
17187 case ARM_TYPE:
48229727 17188 case THUMB32_TYPE:
461a49ca
DJ		 17189 size += 4;
17190 break;
17191
17192 case THUMB16_TYPE:
17193 size += 2;
17194 break;
17195
17196 case DATA_TYPE:
17197 size += 4;
17198 break;
17199
17200 default:
17201 BFD_FAIL ();
4e31c731 17202 return FALSE;
461a49ca
DJ		 17203 }
17204 }
17205
da5938a2
NC		 17206 return TRUE;
17207}
17208
33811162
DG		 17209/* Output mapping symbols for linker generated sections,
17210 and for those data-only sections that do not have a
17211 $d. */
4e617b1e
PB		 17212
17213static bfd_boolean
17214elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17215 struct bfd_link_info *info,
57402f1e 17216 void *flaginfo,
6e0b88f1
AM		 17217 int (*func) (void *, const char *,
17218 Elf_Internal_Sym *,
17219 asection *,
17220 struct elf_link_hash_entry *))
4e617b1e
PB		 17221{
17222 output_arch_syminfo osi;
17223 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17224 bfd_vma offset;
17225 bfd_size_type size;
33811162 17226 bfd *input_bfd;
4e617b1e
PB		 17227
17228 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17229 if (htab == NULL)
17230 return FALSE;
17231
906e58ca 17232 check_use_blx (htab);
91a5743d 17233
57402f1e 17234 osi.flaginfo = flaginfo;
4e617b1e
PB		 17235 osi.info = info;
17236 osi.func = func;
906e58ca 17237
33811162
DG		 17238 /* Add a $d mapping symbol to data-only sections that
17239 don't have any mapping symbol. This may result in (harmless) redundant
17240 mapping symbols. */
17241 for (input_bfd = info->input_bfds;
17242 input_bfd != NULL;
c72f2fb2 17243 input_bfd = input_bfd->link.next)
33811162
DG		 17244 {
17245 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17246 for (osi.sec = input_bfd->sections;
17247 osi.sec != NULL;
17248 osi.sec = osi.sec->next)
17249 {
17250 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17251 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17252 != 0)
33811162
DG		 17253 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17254 == SEC_HAS_CONTENTS
17255 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17256 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17257 && osi.sec->size > 0
17258 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17259 {
17260 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17261 (output_bfd, osi.sec->output_section);
17262 if (osi.sec_shndx != (int)SHN_BAD)
17263 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17264 }
17265 }
17266 }
17267
91a5743d
PB		 17268 /* ARM->Thumb glue. */
17269 if (htab->arm_glue_size > 0)
17270 {
3d4d4302
AM		 17271 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17272 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17273
17274 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17275 (output_bfd, osi.sec->output_section);
0e1862bb 17276 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17277 || htab->pic_veneer)
17278 size = ARM2THUMB_PIC_GLUE_SIZE;
17279 else if (htab->use_blx)
17280 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17281 else
17282 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17283
91a5743d
PB		 17284 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17285 {
7413f23f
DJ		 17286 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17287 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17288 }
17289 }
17290
17291 /* Thumb->ARM glue. */
17292 if (htab->thumb_glue_size > 0)
17293 {
3d4d4302
AM		 17294 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17295 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17296
17297 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17298 (output_bfd, osi.sec->output_section);
17299 size = THUMB2ARM_GLUE_SIZE;
17300
17301 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17302 {
7413f23f
DJ		 17303 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17304 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17305 }
17306 }
17307
845b51d6
PB		 17308 /* ARMv4 BX veneers. */
17309 if (htab->bx_glue_size > 0)
17310 {
3d4d4302
AM		 17311 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17312 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17313
17314 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17315 (output_bfd, osi.sec->output_section);
17316
7413f23f 17317 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17318 }
17319
8029a119
NC		 17320 /* Long calls stubs. */
17321 if (htab->stub_bfd && htab->stub_bfd->sections)
17322 {
da5938a2 17323 asection* stub_sec;
8029a119 17324
da5938a2
NC		 17325 for (stub_sec = htab->stub_bfd->sections;
17326 stub_sec != NULL;
8029a119
NC		 17327 stub_sec = stub_sec->next)
17328 {
17329 /* Ignore non-stub sections. */
17330 if (!strstr (stub_sec->name, STUB_SUFFIX))
17331 continue;
da5938a2 17332
8029a119 17333 osi.sec = stub_sec;
da5938a2 17334
8029a119
NC		 17335 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17336 (output_bfd, osi.sec->output_section);
da5938a2 17337
8029a119
NC		 17338 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17339 }
17340 }
da5938a2 17341
91a5743d 17342 /* Finally, output mapping symbols for the PLT. */
34e77a92 17343 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17344 {
34e77a92
RS		 17345 osi.sec = htab->root.splt;
17346 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17347 (output_bfd, osi.sec->output_section));
17348
17349 /* Output mapping symbols for the plt header. SymbianOS does not have a
17350 plt header. */
17351 if (htab->vxworks_p)
17352 {
17353 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17354 if (!bfd_link_pic (info))
34e77a92
RS		 17355 {
17356 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17357 return FALSE;
17358 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17359 return FALSE;
17360 }
17361 }
b38cadfb
NC		 17362 else if (htab->nacl_p)
17363 {
17364 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17365 return FALSE;
17366 }
eed94f8f
NC		 17367 else if (using_thumb_only (htab))
17368 {
17369 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17370 return FALSE;
17371 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17372 return FALSE;
17373 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17374 return FALSE;
17375 }
34e77a92 17376 else if (!htab->symbian_p)
4e617b1e 17377 {
7413f23f 17378 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17379 return FALSE;
34e77a92
RS		 17380#ifndef FOUR_WORD_PLT
17381 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17382 return FALSE;
34e77a92 17383#endif
4e617b1e
PB		 17384 }
17385 }
99059e56
RM		 17386 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17387 {
17388 /* NaCl uses a special first entry in .iplt too. */
17389 osi.sec = htab->root.iplt;
17390 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17391 (output_bfd, osi.sec->output_section));
17392 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17393 return FALSE;
17394 }
34e77a92
RS		 17395 if ((htab->root.splt && htab->root.splt->size > 0)
17396 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17397 {
34e77a92
RS		 17398 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17399 for (input_bfd = info->input_bfds;
17400 input_bfd != NULL;
c72f2fb2 17401 input_bfd = input_bfd->link.next)
34e77a92
RS		 17402 {
17403 struct arm_local_iplt_info **local_iplt;
17404 unsigned int i, num_syms;
4e617b1e 17405
34e77a92
RS		 17406 local_iplt = elf32_arm_local_iplt (input_bfd);
17407 if (local_iplt != NULL)
17408 {
17409 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17410 for (i = 0; i < num_syms; i++)
17411 if (local_iplt[i] != NULL
17412 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17413 &local_iplt[i]->root,
17414 &local_iplt[i]->arm))
17415 return FALSE;
17416 }
17417 }
17418 }
0855e32b
NS		 17419 if (htab->dt_tlsdesc_plt != 0)
17420 {
17421 /* Mapping symbols for the lazy tls trampoline. */
17422 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17423 return FALSE;
b38cadfb 17424
0855e32b
NS		 17425 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17426 htab->dt_tlsdesc_plt + 24))
17427 return FALSE;
17428 }
17429 if (htab->tls_trampoline != 0)
17430 {
17431 /* Mapping symbols for the tls trampoline. */
17432 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17433 return FALSE;
17434#ifdef FOUR_WORD_PLT
17435 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17436 htab->tls_trampoline + 12))
17437 return FALSE;
b38cadfb 17438#endif
0855e32b 17439 }
b38cadfb 17440
4e617b1e
PB		 17441 return TRUE;
17442}
17443
54ddd295
TP		 17444/* Filter normal symbols of CMSE entry functions of ABFD to include in
17445 the import library. All SYMCOUNT symbols of ABFD can be examined
17446 from their pointers in SYMS. Pointers of symbols to keep should be
17447 stored continuously at the beginning of that array.
17448
17449 Returns the number of symbols to keep. */
17450
17451static unsigned int
17452elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17453 struct bfd_link_info *info,
17454 asymbol **syms, long symcount)
17455{
17456 size_t maxnamelen;
17457 char *cmse_name;
17458 long src_count, dst_count = 0;
17459 struct elf32_arm_link_hash_table *htab;
17460
17461 htab = elf32_arm_hash_table (info);
17462 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17463 symcount = 0;
17464
17465 maxnamelen = 128;
17466 cmse_name = (char *) bfd_malloc (maxnamelen);
17467 for (src_count = 0; src_count < symcount; src_count++)
17468 {
17469 struct elf32_arm_link_hash_entry *cmse_hash;
17470 asymbol *sym;
17471 flagword flags;
17472 char *name;
17473 size_t namelen;
17474
17475 sym = syms[src_count];
17476 flags = sym->flags;
17477 name = (char *) bfd_asymbol_name (sym);
17478
17479 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17480 continue;
17481 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17482 continue;
17483
17484 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17485 if (namelen > maxnamelen)
17486 {
17487 cmse_name = (char *)
17488 bfd_realloc (cmse_name, namelen);
17489 maxnamelen = namelen;
17490 }
17491 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17492 cmse_hash = (struct elf32_arm_link_hash_entry *)
17493 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17494
17495 if (!cmse_hash
17496 || (cmse_hash->root.root.type != bfd_link_hash_defined
17497 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17498 || cmse_hash->root.type != STT_FUNC)
17499 continue;
17500
17501 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17502 continue;
17503
17504 syms[dst_count++] = sym;
17505 }
17506 free (cmse_name);
17507
17508 syms[dst_count] = NULL;
17509
17510 return dst_count;
17511}
17512
17513/* Filter symbols of ABFD to include in the import library. All
17514 SYMCOUNT symbols of ABFD can be examined from their pointers in
17515 SYMS. Pointers of symbols to keep should be stored continuously at
17516 the beginning of that array.
17517
17518 Returns the number of symbols to keep. */
17519
17520static unsigned int
17521elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17522 struct bfd_link_info *info,
17523 asymbol **syms, long symcount)
17524{
17525 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17526
046734ff
TP		 17527 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
17528 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
17529 library to be a relocatable object file. */
17530 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 17531 if (globals->cmse_implib)
17532 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17533 else
17534 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17535}
17536
e489d0ae
PB		 17537/* Allocate target specific section data. */
17538
17539static bfd_boolean
17540elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17541{
f592407e
AM		 17542 if (!sec->used_by_bfd)
17543 {
17544 _arm_elf_section_data *sdata;
17545 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17546
21d799b5 17547 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17548 if (sdata == NULL)
17549 return FALSE;
17550 sec->used_by_bfd = sdata;
17551 }
e489d0ae
PB		 17552
17553 return _bfd_elf_new_section_hook (abfd, sec);
17554}
17555
17556
17557/* Used to order a list of mapping symbols by address. */
17558
17559static int
17560elf32_arm_compare_mapping (const void * a, const void * b)
17561{
7f6a71ff
JM		 17562 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17563 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17564
17565 if (amap->vma > bmap->vma)
17566 return 1;
17567 else if (amap->vma < bmap->vma)
17568 return -1;
17569 else if (amap->type > bmap->type)
17570 /* Ensure results do not depend on the host qsort for objects with
17571 multiple mapping symbols at the same address by sorting on type
17572 after vma. */
17573 return 1;
17574 else if (amap->type < bmap->type)
17575 return -1;
17576 else
17577 return 0;
e489d0ae
PB		 17578}
17579
2468f9c9
PB		 17580/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17581
17582static unsigned long
17583offset_prel31 (unsigned long addr, bfd_vma offset)
17584{
17585 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17586}
17587
17588/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17589 relocations. */
17590
17591static void
17592copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17593{
17594 unsigned long first_word = bfd_get_32 (output_bfd, from);
17595 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17596
2468f9c9
PB		 17597 /* High bit of first word is supposed to be zero. */
17598 if ((first_word & 0x80000000ul) == 0)
17599 first_word = offset_prel31 (first_word, offset);
b38cadfb 17600
2468f9c9
PB		 17601 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17602 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17603 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17604 second_word = offset_prel31 (second_word, offset);
b38cadfb 17605
2468f9c9
PB		 17606 bfd_put_32 (output_bfd, first_word, to);
17607 bfd_put_32 (output_bfd, second_word, to + 4);
17608}
e489d0ae 17609
48229727
JB		 17610/* Data for make_branch_to_a8_stub(). */
17611
b38cadfb
NC		 17612struct a8_branch_to_stub_data
17613{
48229727
JB		 17614 asection *writing_section;
17615 bfd_byte *contents;
17616};
17617
17618
17619/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17620 places for a particular section. */
17621
17622static bfd_boolean
17623make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17624 void *in_arg)
48229727
JB		 17625{
17626 struct elf32_arm_stub_hash_entry *stub_entry;
17627 struct a8_branch_to_stub_data *data;
17628 bfd_byte *contents;
17629 unsigned long branch_insn;
17630 bfd_vma veneered_insn_loc, veneer_entry_loc;
17631 bfd_signed_vma branch_offset;
17632 bfd *abfd;
8d9d9490 17633 unsigned int loc;
48229727
JB		 17634
17635 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17636 data = (struct a8_branch_to_stub_data *) in_arg;
17637
17638 if (stub_entry->target_section != data->writing_section
4563a860 17639 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17640 return TRUE;
17641
17642 contents = data->contents;
17643
8d9d9490
TP		 17644 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17645 generated when both source and target are in the same section. */
48229727
JB		 17646 veneered_insn_loc = stub_entry->target_section->output_section->vma
17647 + stub_entry->target_section->output_offset
8d9d9490 17648 + stub_entry->source_value;
48229727
JB		 17649
17650 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17651 + stub_entry->stub_sec->output_offset
17652 + stub_entry->stub_offset;
17653
17654 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17655 veneered_insn_loc &= ~3u;
17656
17657 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17658
17659 abfd = stub_entry->target_section->owner;
8d9d9490 17660 loc = stub_entry->source_value;
48229727
JB		 17661
17662 /* We attempt to avoid this condition by setting stubs_always_after_branch
17663 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17664 This check is just to be on the safe side... */
17665 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17666 {
4eca0228
AM		 17667 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub is "
17668 "allocated in unsafe location"), abfd);
48229727
JB		 17669 return FALSE;
17670 }
17671
17672 switch (stub_entry->stub_type)
17673 {
17674 case arm_stub_a8_veneer_b:
17675 case arm_stub_a8_veneer_b_cond:
17676 branch_insn = 0xf0009000;
17677 goto jump24;
17678
17679 case arm_stub_a8_veneer_blx:
17680 branch_insn = 0xf000e800;
17681 goto jump24;
17682
17683 case arm_stub_a8_veneer_bl:
17684 {
17685 unsigned int i1, j1, i2, j2, s;
17686
17687 branch_insn = 0xf000d000;
17688
17689 jump24:
17690 if (branch_offset < -16777216 || branch_offset > 16777214)
17691 {
17692 /* There's not much we can do apart from complain if this
17693 happens. */
4eca0228
AM		 17694 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub out "
17695 "of range (input file too large)"), abfd);
48229727
JB		 17696 return FALSE;
17697 }
17698
17699 /* i1 = not(j1 eor s), so:
17700 not i1 = j1 eor s
17701 j1 = (not i1) eor s. */
17702
17703 branch_insn |= (branch_offset >> 1) & 0x7ff;
17704 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17705 i2 = (branch_offset >> 22) & 1;
17706 i1 = (branch_offset >> 23) & 1;
17707 s = (branch_offset >> 24) & 1;
17708 j1 = (!i1) ^ s;
17709 j2 = (!i2) ^ s;
17710 branch_insn |= j2 << 11;
17711 branch_insn |= j1 << 13;
17712 branch_insn |= s << 26;
17713 }
17714 break;
17715
17716 default:
17717 BFD_FAIL ();
17718 return FALSE;
17719 }
17720
8d9d9490
TP		 17721 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17722 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17723
17724 return TRUE;
17725}
17726
a504d23a
LA		 17727/* Beginning of stm32l4xx work-around. */
17728
17729/* Functions encoding instructions necessary for the emission of the
17730 fix-stm32l4xx-629360.
17731 Encoding is extracted from the
17732 ARM (C) Architecture Reference Manual
17733 ARMv7-A and ARMv7-R edition
17734 ARM DDI 0406C.b (ID072512). */
17735
17736static inline bfd_vma
82188b29 17737create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17738{
17739 /* A8.8.18 B (A8-334)
17740 B target_address (Encoding T4). */
17741 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17742 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17743 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17744
a504d23a
LA		 17745 int s = ((branch_offset & 0x1000000) >> 24);
17746 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17747 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17748
17749 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17750 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17751
17752 bfd_vma patched_inst = 0xf0009000
17753 | s << 26 /* S. */
17754 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17755 | j1 << 13 /* J1. */
17756 | j2 << 11 /* J2. */
17757 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17758
17759 return patched_inst;
17760}
17761
17762static inline bfd_vma
17763create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17764{
17765 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17766 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17767 bfd_vma patched_inst = 0xe8900000
17768 | (/*W=*/wback << 21)
17769 | (base_reg << 16)
17770 | (reg_mask & 0x0000ffff);
17771
17772 return patched_inst;
17773}
17774
17775static inline bfd_vma
17776create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17777{
17778 /* A8.8.60 LDMDB/LDMEA (A8-402)
17779 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17780 bfd_vma patched_inst = 0xe9100000
17781 | (/*W=*/wback << 21)
17782 | (base_reg << 16)
17783 | (reg_mask & 0x0000ffff);
17784
17785 return patched_inst;
17786}
17787
17788static inline bfd_vma
17789create_instruction_mov (int target_reg, int source_reg)
17790{
17791 /* A8.8.103 MOV (register) (A8-486)
17792 MOV Rd, Rm (Encoding T1). */
17793 bfd_vma patched_inst = 0x4600
17794 | (target_reg & 0x7)
17795 | ((target_reg & 0x8) >> 3) << 7
17796 | (source_reg << 3);
17797
17798 return patched_inst;
17799}
17800
17801static inline bfd_vma
17802create_instruction_sub (int target_reg, int source_reg, int value)
17803{
17804 /* A8.8.221 SUB (immediate) (A8-708)
17805 SUB Rd, Rn, #value (Encoding T3). */
17806 bfd_vma patched_inst = 0xf1a00000
17807 | (target_reg << 8)
17808 | (source_reg << 16)
17809 | (/*S=*/0 << 20)
17810 | ((value & 0x800) >> 11) << 26
17811 | ((value & 0x700) >> 8) << 12
17812 | (value & 0x0ff);
17813
17814 return patched_inst;
17815}
17816
17817static inline bfd_vma
9239bbd3 17818create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17819 int first_reg)
17820{
17821 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17822 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17823 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17824 | (/*W=*/wback << 21)
17825 | (base_reg << 16)
9239bbd3
CM		 17826 | (num_words & 0x000000ff)
17827 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17828 | (first_reg & 0x00000001) << 22;
17829
17830 return patched_inst;
17831}
17832
17833static inline bfd_vma
9239bbd3
CM		 17834create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17835 int first_reg)
a504d23a
LA		 17836{
17837 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17838 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17839 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17840 | (base_reg << 16)
9239bbd3
CM		 17841 | (num_words & 0x000000ff)
17842 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17843 | (first_reg & 0x00000001) << 22;
17844
17845 return patched_inst;
17846}
17847
17848static inline bfd_vma
17849create_instruction_udf_w (int value)
17850{
17851 /* A8.8.247 UDF (A8-758)
17852 Undefined (Encoding T2). */
17853 bfd_vma patched_inst = 0xf7f0a000
17854 | (value & 0x00000fff)
17855 | (value & 0x000f0000) << 16;
17856
17857 return patched_inst;
17858}
17859
17860static inline bfd_vma
17861create_instruction_udf (int value)
17862{
17863 /* A8.8.247 UDF (A8-758)
17864 Undefined (Encoding T1). */
17865 bfd_vma patched_inst = 0xde00
17866 | (value & 0xff);
17867
17868 return patched_inst;
17869}
17870
17871/* Functions writing an instruction in memory, returning the next
17872 memory position to write to. */
17873
17874static inline bfd_byte *
17875push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17876 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17877{
17878 put_thumb2_insn (htab, output_bfd, insn, pt);
17879 return pt + 4;
17880}
17881
17882static inline bfd_byte *
17883push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17884 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17885{
17886 put_thumb_insn (htab, output_bfd, insn, pt);
17887 return pt + 2;
17888}
17889
17890/* Function filling up a region in memory with T1 and T2 UDFs taking
17891 care of alignment. */
17892
17893static bfd_byte *
17894stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17895 bfd * output_bfd,
17896 const bfd_byte * const base_stub_contents,
17897 bfd_byte * const from_stub_contents,
17898 const bfd_byte * const end_stub_contents)
17899{
17900 bfd_byte *current_stub_contents = from_stub_contents;
17901
17902 /* Fill the remaining of the stub with deterministic contents : UDF
17903 instructions.
17904 Check if realignment is needed on modulo 4 frontier using T1, to
17905 further use T2. */
17906 if ((current_stub_contents < end_stub_contents)
17907 && !((current_stub_contents - base_stub_contents) % 2)
17908 && ((current_stub_contents - base_stub_contents) % 4))
17909 current_stub_contents =
17910 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17911 create_instruction_udf (0));
17912
17913 for (; current_stub_contents < end_stub_contents;)
17914 current_stub_contents =
17915 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17916 create_instruction_udf_w (0));
17917
17918 return current_stub_contents;
17919}
17920
17921/* Functions writing the stream of instructions equivalent to the
17922 derived sequence for ldmia, ldmdb, vldm respectively. */
17923
17924static void
17925stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17926 bfd * output_bfd,
17927 const insn32 initial_insn,
17928 const bfd_byte *const initial_insn_addr,
17929 bfd_byte *const base_stub_contents)
17930{
17931 int wback = (initial_insn & 0x00200000) >> 21;
17932 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17933 int insn_all_registers = initial_insn & 0x0000ffff;
17934 int insn_low_registers, insn_high_registers;
17935 int usable_register_mask;
b25e998d 17936 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17937 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17938 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17939 bfd_byte *current_stub_contents = base_stub_contents;
17940
17941 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17942
17943 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17944 smaller than 8 registers load sequences that do not cause the
17945 hardware issue. */
17946 if (nb_registers <= 8)
17947 {
17948 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17949 current_stub_contents =
17950 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17951 initial_insn);
17952
17953 /* B initial_insn_addr+4. */
17954 if (!restore_pc)
17955 current_stub_contents =
17956 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17957 create_instruction_branch_absolute
82188b29 17958 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17959
17960 /* Fill the remaining of the stub with deterministic contents. */
17961 current_stub_contents =
17962 stm32l4xx_fill_stub_udf (htab, output_bfd,
17963 base_stub_contents, current_stub_contents,
17964 base_stub_contents +
17965 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17966
17967 return;
17968 }
17969
17970 /* - reg_list[13] == 0. */
17971 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17972
17973 /* - reg_list[14] & reg_list[15] != 1. */
17974 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17975
17976 /* - if (wback==1) reg_list[rn] == 0. */
17977 BFD_ASSERT (!wback || !restore_rn);
17978
17979 /* - nb_registers > 8. */
b25e998d 17980 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17981
17982 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17983
17984 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17985 - One with the 7 lowest registers (register mask 0x007F)
17986 This LDM will finally contain between 2 and 7 registers
17987 - One with the 7 highest registers (register mask 0xDF80)
17988 This ldm will finally contain between 2 and 7 registers. */
17989 insn_low_registers = insn_all_registers & 0x007F;
17990 insn_high_registers = insn_all_registers & 0xDF80;
17991
17992 /* A spare register may be needed during this veneer to temporarily
17993 handle the base register. This register will be restored with the
17994 last LDM operation.
17995 The usable register may be any general purpose register (that
17996 excludes PC, SP, LR : register mask is 0x1FFF). */
17997 usable_register_mask = 0x1FFF;
17998
17999 /* Generate the stub function. */
18000 if (wback)
18001 {
18002 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18003 current_stub_contents =
18004 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18005 create_instruction_ldmia
18006 (rn, /*wback=*/1, insn_low_registers));
18007
18008 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18009 current_stub_contents =
18010 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18011 create_instruction_ldmia
18012 (rn, /*wback=*/1, insn_high_registers));
18013 if (!restore_pc)
18014 {
18015 /* B initial_insn_addr+4. */
18016 current_stub_contents =
18017 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18018 create_instruction_branch_absolute
82188b29 18019 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18020 }
18021 }
18022 else /* if (!wback). */
18023 {
18024 ri = rn;
18025
18026 /* If Rn is not part of the high-register-list, move it there. */
18027 if (!(insn_high_registers & (1 << rn)))
18028 {
18029 /* Choose a Ri in the high-register-list that will be restored. */
18030 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18031
18032 /* MOV Ri, Rn. */
18033 current_stub_contents =
18034 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18035 create_instruction_mov (ri, rn));
18036 }
18037
18038 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18039 current_stub_contents =
18040 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18041 create_instruction_ldmia
18042 (ri, /*wback=*/1, insn_low_registers));
18043
18044 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18045 current_stub_contents =
18046 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18047 create_instruction_ldmia
18048 (ri, /*wback=*/0, insn_high_registers));
18049
18050 if (!restore_pc)
18051 {
18052 /* B initial_insn_addr+4. */
18053 current_stub_contents =
18054 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18055 create_instruction_branch_absolute
82188b29 18056 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18057 }
18058 }
18059
18060 /* Fill the remaining of the stub with deterministic contents. */
18061 current_stub_contents =
18062 stm32l4xx_fill_stub_udf (htab, output_bfd,
18063 base_stub_contents, current_stub_contents,
18064 base_stub_contents +
18065 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18066}
18067
18068static void
18069stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18070 bfd * output_bfd,
18071 const insn32 initial_insn,
18072 const bfd_byte *const initial_insn_addr,
18073 bfd_byte *const base_stub_contents)
18074{
18075 int wback = (initial_insn & 0x00200000) >> 21;
18076 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18077 int insn_all_registers = initial_insn & 0x0000ffff;
18078 int insn_low_registers, insn_high_registers;
18079 int usable_register_mask;
18080 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18081 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18082 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18083 bfd_byte *current_stub_contents = base_stub_contents;
18084
18085 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18086
18087 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18088 smaller than 8 registers load sequences that do not cause the
18089 hardware issue. */
18090 if (nb_registers <= 8)
18091 {
18092 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18093 current_stub_contents =
18094 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18095 initial_insn);
18096
18097 /* B initial_insn_addr+4. */
18098 current_stub_contents =
18099 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18100 create_instruction_branch_absolute
82188b29 18101 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18102
18103 /* Fill the remaining of the stub with deterministic contents. */
18104 current_stub_contents =
18105 stm32l4xx_fill_stub_udf (htab, output_bfd,
18106 base_stub_contents, current_stub_contents,
18107 base_stub_contents +
18108 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18109
18110 return;
18111 }
18112
18113 /* - reg_list[13] == 0. */
18114 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18115
18116 /* - reg_list[14] & reg_list[15] != 1. */
18117 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18118
18119 /* - if (wback==1) reg_list[rn] == 0. */
18120 BFD_ASSERT (!wback || !restore_rn);
18121
18122 /* - nb_registers > 8. */
b25e998d 18123 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18124
18125 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18126
18127 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18128 - One with the 7 lowest registers (register mask 0x007F)
18129 This LDM will finally contain between 2 and 7 registers
18130 - One with the 7 highest registers (register mask 0xDF80)
18131 This ldm will finally contain between 2 and 7 registers. */
18132 insn_low_registers = insn_all_registers & 0x007F;
18133 insn_high_registers = insn_all_registers & 0xDF80;
18134
18135 /* A spare register may be needed during this veneer to temporarily
18136 handle the base register. This register will be restored with
18137 the last LDM operation.
18138 The usable register may be any general purpose register (that excludes
18139 PC, SP, LR : register mask is 0x1FFF). */
18140 usable_register_mask = 0x1FFF;
18141
18142 /* Generate the stub function. */
18143 if (!wback && !restore_pc && !restore_rn)
18144 {
18145 /* Choose a Ri in the low-register-list that will be restored. */
18146 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18147
18148 /* MOV Ri, Rn. */
18149 current_stub_contents =
18150 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18151 create_instruction_mov (ri, rn));
18152
18153 /* LDMDB Ri!, {R-high-register-list}. */
18154 current_stub_contents =
18155 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18156 create_instruction_ldmdb
18157 (ri, /*wback=*/1, insn_high_registers));
18158
18159 /* LDMDB Ri, {R-low-register-list}. */
18160 current_stub_contents =
18161 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18162 create_instruction_ldmdb
18163 (ri, /*wback=*/0, insn_low_registers));
18164
18165 /* B initial_insn_addr+4. */
18166 current_stub_contents =
18167 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18168 create_instruction_branch_absolute
82188b29 18169 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18170 }
18171 else if (wback && !restore_pc && !restore_rn)
18172 {
18173 /* LDMDB Rn!, {R-high-register-list}. */
18174 current_stub_contents =
18175 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18176 create_instruction_ldmdb
18177 (rn, /*wback=*/1, insn_high_registers));
18178
18179 /* LDMDB Rn!, {R-low-register-list}. */
18180 current_stub_contents =
18181 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18182 create_instruction_ldmdb
18183 (rn, /*wback=*/1, insn_low_registers));
18184
18185 /* B initial_insn_addr+4. */
18186 current_stub_contents =
18187 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18188 create_instruction_branch_absolute
82188b29 18189 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18190 }
18191 else if (!wback && restore_pc && !restore_rn)
18192 {
18193 /* Choose a Ri in the high-register-list that will be restored. */
18194 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18195
18196 /* SUB Ri, Rn, #(4*nb_registers). */
18197 current_stub_contents =
18198 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18199 create_instruction_sub (ri, rn, (4 * nb_registers)));
18200
18201 /* LDMIA Ri!, {R-low-register-list}. */
18202 current_stub_contents =
18203 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18204 create_instruction_ldmia
18205 (ri, /*wback=*/1, insn_low_registers));
18206
18207 /* LDMIA Ri, {R-high-register-list}. */
18208 current_stub_contents =
18209 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18210 create_instruction_ldmia
18211 (ri, /*wback=*/0, insn_high_registers));
18212 }
18213 else if (wback && restore_pc && !restore_rn)
18214 {
18215 /* Choose a Ri in the high-register-list that will be restored. */
18216 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18217
18218 /* SUB Rn, Rn, #(4*nb_registers) */
18219 current_stub_contents =
18220 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18221 create_instruction_sub (rn, rn, (4 * nb_registers)));
18222
18223 /* MOV Ri, Rn. */
18224 current_stub_contents =
18225 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18226 create_instruction_mov (ri, rn));
18227
18228 /* LDMIA Ri!, {R-low-register-list}. */
18229 current_stub_contents =
18230 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18231 create_instruction_ldmia
18232 (ri, /*wback=*/1, insn_low_registers));
18233
18234 /* LDMIA Ri, {R-high-register-list}. */
18235 current_stub_contents =
18236 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18237 create_instruction_ldmia
18238 (ri, /*wback=*/0, insn_high_registers));
18239 }
18240 else if (!wback && !restore_pc && restore_rn)
18241 {
18242 ri = rn;
18243 if (!(insn_low_registers & (1 << rn)))
18244 {
18245 /* Choose a Ri in the low-register-list that will be restored. */
18246 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18247
18248 /* MOV Ri, Rn. */
18249 current_stub_contents =
18250 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18251 create_instruction_mov (ri, rn));
18252 }
18253
18254 /* LDMDB Ri!, {R-high-register-list}. */
18255 current_stub_contents =
18256 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18257 create_instruction_ldmdb
18258 (ri, /*wback=*/1, insn_high_registers));
18259
18260 /* LDMDB Ri, {R-low-register-list}. */
18261 current_stub_contents =
18262 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18263 create_instruction_ldmdb
18264 (ri, /*wback=*/0, insn_low_registers));
18265
18266 /* B initial_insn_addr+4. */
18267 current_stub_contents =
18268 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18269 create_instruction_branch_absolute
82188b29 18270 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18271 }
18272 else if (!wback && restore_pc && restore_rn)
18273 {
18274 ri = rn;
18275 if (!(insn_high_registers & (1 << rn)))
18276 {
18277 /* Choose a Ri in the high-register-list that will be restored. */
18278 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18279 }
18280
18281 /* SUB Ri, Rn, #(4*nb_registers). */
18282 current_stub_contents =
18283 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18284 create_instruction_sub (ri, rn, (4 * nb_registers)));
18285
18286 /* LDMIA Ri!, {R-low-register-list}. */
18287 current_stub_contents =
18288 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18289 create_instruction_ldmia
18290 (ri, /*wback=*/1, insn_low_registers));
18291
18292 /* LDMIA Ri, {R-high-register-list}. */
18293 current_stub_contents =
18294 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18295 create_instruction_ldmia
18296 (ri, /*wback=*/0, insn_high_registers));
18297 }
18298 else if (wback && restore_rn)
18299 {
18300 /* The assembler should not have accepted to encode this. */
18301 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18302 "undefined behavior.\n");
18303 }
18304
18305 /* Fill the remaining of the stub with deterministic contents. */
18306 current_stub_contents =
18307 stm32l4xx_fill_stub_udf (htab, output_bfd,
18308 base_stub_contents, current_stub_contents,
18309 base_stub_contents +
18310 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18311
18312}
18313
18314static void
18315stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18316 bfd * output_bfd,
18317 const insn32 initial_insn,
18318 const bfd_byte *const initial_insn_addr,
18319 bfd_byte *const base_stub_contents)
18320{
9239bbd3 18321 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18322 bfd_byte *current_stub_contents = base_stub_contents;
18323
18324 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18325
18326 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18327 smaller than 8 words load sequences that do not cause the
a504d23a 18328 hardware issue. */
9239bbd3 18329 if (num_words <= 8)
a504d23a
LA		 18330 {
18331 /* Untouched instruction. */
18332 current_stub_contents =
18333 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18334 initial_insn);
18335
18336 /* B initial_insn_addr+4. */
18337 current_stub_contents =
18338 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18339 create_instruction_branch_absolute
82188b29 18340 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18341 }
18342 else
18343 {
9eaff861 18344 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18345 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18346 bfd_boolean is_ia_nobang = /* (IA without !). */
18347 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18348 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18349 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18350 bfd_boolean is_db_bang = /* (DB with !). */
18351 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18352 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18353 /* d = UInt (Vd:D);. */
9239bbd3 18354 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18355 | (((unsigned int)initial_insn << 9) >> 31);
18356
9239bbd3
CM		 18357 /* Compute the number of 8-words chunks needed to split. */
18358 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18359 int chunk;
18360
18361 /* The test coverage has been done assuming the following
18362 hypothesis that exactly one of the previous is_ predicates is
18363 true. */
9239bbd3
CM		 18364 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18365 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18366
9239bbd3 18367 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18368 cases, then we emit the adjustments:
18369
18370 vldm rx, {...}
18371 -> vldm rx!, {8_words_or_less} for each needed 8_word
18372 -> sub rx, rx, #size (list)
18373
18374 vldm rx!, {...}
18375 -> vldm rx!, {8_words_or_less} for each needed 8_word
18376 This also handles vpop instruction (when rx is sp)
18377
18378 vldmd rx!, {...}
18379 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18380 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18381 {
9239bbd3
CM		 18382 bfd_vma new_insn = 0;
18383
a504d23a
LA		 18384 if (is_ia_nobang || is_ia_bang)
18385 {
9239bbd3
CM		 18386 new_insn = create_instruction_vldmia
18387 (base_reg,
18388 is_dp,
18389 /*wback= . */1,
18390 chunks - (chunk + 1) ?
18391 8 : num_words - chunk * 8,
18392 first_reg + chunk * 8);
a504d23a
LA		 18393 }
18394 else if (is_db_bang)
18395 {
9239bbd3
CM		 18396 new_insn = create_instruction_vldmdb
18397 (base_reg,
18398 is_dp,
18399 chunks - (chunk + 1) ?
18400 8 : num_words - chunk * 8,
18401 first_reg + chunk * 8);
a504d23a 18402 }
9239bbd3
CM		 18403
18404 if (new_insn)
18405 current_stub_contents =
18406 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18407 new_insn);
a504d23a
LA		 18408 }
18409
18410 /* Only this case requires the base register compensation
18411 subtract. */
18412 if (is_ia_nobang)
18413 {
18414 current_stub_contents =
18415 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18416 create_instruction_sub
9239bbd3 18417 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18418 }
18419
18420 /* B initial_insn_addr+4. */
18421 current_stub_contents =
18422 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18423 create_instruction_branch_absolute
82188b29 18424 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18425 }
18426
18427 /* Fill the remaining of the stub with deterministic contents. */
18428 current_stub_contents =
18429 stm32l4xx_fill_stub_udf (htab, output_bfd,
18430 base_stub_contents, current_stub_contents,
18431 base_stub_contents +
18432 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18433}
18434
18435static void
18436stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18437 bfd * output_bfd,
18438 const insn32 wrong_insn,
18439 const bfd_byte *const wrong_insn_addr,
18440 bfd_byte *const stub_contents)
18441{
18442 if (is_thumb2_ldmia (wrong_insn))
18443 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18444 wrong_insn, wrong_insn_addr,
18445 stub_contents);
18446 else if (is_thumb2_ldmdb (wrong_insn))
18447 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18448 wrong_insn, wrong_insn_addr,
18449 stub_contents);
18450 else if (is_thumb2_vldm (wrong_insn))
18451 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18452 wrong_insn, wrong_insn_addr,
18453 stub_contents);
18454}
18455
18456/* End of stm32l4xx work-around. */
18457
18458
e489d0ae
PB		 18459/* Do code byteswapping. Return FALSE afterwards so that the section is
18460 written out as normal. */
18461
18462static bfd_boolean
c7b8f16e 18463elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18464 struct bfd_link_info *link_info,
18465 asection *sec,
e489d0ae
PB		 18466 bfd_byte *contents)
18467{
48229727 18468 unsigned int mapcount, errcount;
8e3de13a 18469 _arm_elf_section_data *arm_data;
c7b8f16e 18470 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18471 elf32_arm_section_map *map;
c7b8f16e 18472 elf32_vfp11_erratum_list *errnode;
a504d23a 18473 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18474 bfd_vma ptr;
18475 bfd_vma end;
c7b8f16e 18476 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18477 bfd_byte tmp;
48229727 18478 unsigned int i;
57e8b36a 18479
4dfe6ac6
NC		 18480 if (globals == NULL)
18481 return FALSE;
18482
8e3de13a
NC		 18483 /* If this section has not been allocated an _arm_elf_section_data
18484 structure then we cannot record anything. */
18485 arm_data = get_arm_elf_section_data (sec);
18486 if (arm_data == NULL)
18487 return FALSE;
18488
18489 mapcount = arm_data->mapcount;
18490 map = arm_data->map;
c7b8f16e
JB		 18491 errcount = arm_data->erratumcount;
18492
18493 if (errcount != 0)
18494 {
18495 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18496
18497 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18498 errnode = errnode->next)
18499 {
18500 bfd_vma target = errnode->vma - offset;
18501
18502 switch (errnode->type)
18503 {
18504 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18505 {
18506 bfd_vma branch_to_veneer;
18507 /* Original condition code of instruction, plus bit mask for
18508 ARM B instruction. */
18509 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18510 | 0x0a000000;
c7b8f16e
JB		 18511
18512 /* The instruction is before the label. */
91d6fa6a 18513 target -= 4;
c7b8f16e
JB		 18514
18515 /* Above offset included in -4 below. */
18516 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18517 - errnode->vma - 4;
c7b8f16e
JB		 18518
18519 if ((signed) branch_to_veneer < -(1 << 25)
18520 || (signed) branch_to_veneer >= (1 << 25))
4eca0228
AM		 18521 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18522 "range"), output_bfd);
c7b8f16e 18523
99059e56
RM		 18524 insn |= (branch_to_veneer >> 2) & 0xffffff;
18525 contents[endianflip ^ target] = insn & 0xff;
18526 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18527 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18528 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18529 }
18530 break;
c7b8f16e
JB		 18531
18532 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18533 {
18534 bfd_vma branch_from_veneer;
18535 unsigned int insn;
c7b8f16e 18536
99059e56
RM		 18537 /* Take size of veneer into account. */
18538 branch_from_veneer = errnode->u.v.branch->vma
18539 - errnode->vma - 12;
c7b8f16e
JB		 18540
18541 if ((signed) branch_from_veneer < -(1 << 25)
18542 || (signed) branch_from_veneer >= (1 << 25))
4eca0228
AM		 18543 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18544 "range"), output_bfd);
c7b8f16e 18545
99059e56
RM		 18546 /* Original instruction. */
18547 insn = errnode->u.v.branch->u.b.vfp_insn;
18548 contents[endianflip ^ target] = insn & 0xff;
18549 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18550 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18551 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18552
18553 /* Branch back to insn after original insn. */
18554 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18555 contents[endianflip ^ (target + 4)] = insn & 0xff;
18556 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18557 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18558 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18559 }
18560 break;
c7b8f16e 18561
99059e56
RM		 18562 default:
18563 abort ();
18564 }
18565 }
c7b8f16e 18566 }
e489d0ae 18567
a504d23a
LA		 18568 if (arm_data->stm32l4xx_erratumcount != 0)
18569 {
18570 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18571 stm32l4xx_errnode != 0;
18572 stm32l4xx_errnode = stm32l4xx_errnode->next)
18573 {
18574 bfd_vma target = stm32l4xx_errnode->vma - offset;
18575
18576 switch (stm32l4xx_errnode->type)
18577 {
18578 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18579 {
18580 unsigned int insn;
18581 bfd_vma branch_to_veneer =
18582 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18583
18584 if ((signed) branch_to_veneer < -(1 << 24)
18585 || (signed) branch_to_veneer >= (1 << 24))
18586 {
18587 bfd_vma out_of_range =
18588 ((signed) branch_to_veneer < -(1 << 24)) ?
18589 - branch_to_veneer - (1 << 24) :
18590 ((signed) branch_to_veneer >= (1 << 24)) ?
18591 branch_to_veneer - (1 << 24) : 0;
18592
4eca0228 18593 _bfd_error_handler
d42c267e
AM		 18594 (_("%B(%#Lx): error: Cannot create STM32L4XX veneer. "
18595 "Jump out of range by %Ld bytes. "
a504d23a
LA		 18596 "Cannot encode branch instruction. "),
18597 output_bfd,
d42c267e 18598 stm32l4xx_errnode->vma - 4,
a504d23a
LA		 18599 out_of_range);
18600 continue;
18601 }
18602
18603 insn = create_instruction_branch_absolute
82188b29 18604 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18605
18606 /* The instruction is before the label. */
18607 target -= 4;
18608
18609 put_thumb2_insn (globals, output_bfd,
18610 (bfd_vma) insn, contents + target);
18611 }
18612 break;
18613
18614 case STM32L4XX_ERRATUM_VENEER:
18615 {
82188b29
NC		 18616 bfd_byte * veneer;
18617 bfd_byte * veneer_r;
a504d23a
LA		 18618 unsigned int insn;
18619
82188b29
NC		 18620 veneer = contents + target;
18621 veneer_r = veneer
18622 + stm32l4xx_errnode->u.b.veneer->vma
18623 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18624
18625 if ((signed) (veneer_r - veneer -
18626 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18627 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18628 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18629 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18630 || (signed) (veneer_r - veneer) >= (1 << 24))
18631 {
4eca0228
AM		 18632 _bfd_error_handler (_("%B: error: Cannot create STM32L4XX "
18633 "veneer."), output_bfd);
a504d23a
LA		 18634 continue;
18635 }
18636
18637 /* Original instruction. */
18638 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18639
18640 stm32l4xx_create_replacing_stub
18641 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18642 }
18643 break;
18644
18645 default:
18646 abort ();
18647 }
18648 }
18649 }
18650
2468f9c9
PB		 18651 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18652 {
18653 arm_unwind_table_edit *edit_node
99059e56 18654 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18655 /* Now, sec->size is the size of the section we will write. The original
99059e56 18656 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18657 markers) was sec->rawsize. (This isn't the case if we perform no
18658 edits, then rawsize will be zero and we should use size). */
21d799b5 18659 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18660 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18661 unsigned int in_index, out_index;
18662 bfd_vma add_to_offsets = 0;
18663
18664 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18665 {
2468f9c9
PB		 18666 if (edit_node)
18667 {
18668 unsigned int edit_index = edit_node->index;
b38cadfb 18669
2468f9c9 18670 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18671 {
2468f9c9
PB		 18672 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18673 contents + in_index * 8, add_to_offsets);
18674 out_index++;
18675 in_index++;
18676 }
18677 else if (in_index == edit_index
18678 || (in_index * 8 >= input_size
18679 && edit_index == UINT_MAX))
99059e56 18680 {
2468f9c9
PB		 18681 switch (edit_node->type)
18682 {
18683 case DELETE_EXIDX_ENTRY:
18684 in_index++;
18685 add_to_offsets += 8;
18686 break;
b38cadfb 18687
2468f9c9
PB		 18688 case INSERT_EXIDX_CANTUNWIND_AT_END:
18689 {
99059e56 18690 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18691 bfd_vma text_offset = text_sec->output_section->vma
18692 + text_sec->output_offset
18693 + text_sec->size;
18694 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18695 unsigned long prel31_offset;
2468f9c9
PB		 18696
18697 /* Note: this is meant to be equivalent to an
18698 R_ARM_PREL31 relocation. These synthetic
18699 EXIDX_CANTUNWIND markers are not relocated by the
18700 usual BFD method. */
18701 prel31_offset = (text_offset - exidx_offset)
18702 & 0x7ffffffful;
491d01d3
YU		 18703 if (bfd_link_relocatable (link_info))
18704 {
18705 /* Here relocation for new EXIDX_CANTUNWIND is
18706 created, so there is no need to
18707 adjust offset by hand. */
18708 prel31_offset = text_sec->output_offset
18709 + text_sec->size;
491d01d3 18710 }
2468f9c9
PB		 18711
18712 /* First address we can't unwind. */
18713 bfd_put_32 (output_bfd, prel31_offset,
18714 &edited_contents[out_index * 8]);
18715
18716 /* Code for EXIDX_CANTUNWIND. */
18717 bfd_put_32 (output_bfd, 0x1,
18718 &edited_contents[out_index * 8 + 4]);
18719
18720 out_index++;
18721 add_to_offsets -= 8;
18722 }
18723 break;
18724 }
b38cadfb 18725
2468f9c9
PB		 18726 edit_node = edit_node->next;
18727 }
18728 }
18729 else
18730 {
18731 /* No more edits, copy remaining entries verbatim. */
18732 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18733 contents + in_index * 8, add_to_offsets);
18734 out_index++;
18735 in_index++;
18736 }
18737 }
18738
18739 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18740 bfd_set_section_contents (output_bfd, sec->output_section,
18741 edited_contents,
18742 (file_ptr) sec->output_offset, sec->size);
18743
18744 return TRUE;
18745 }
18746
48229727
JB		 18747 /* Fix code to point to Cortex-A8 erratum stubs. */
18748 if (globals->fix_cortex_a8)
18749 {
18750 struct a8_branch_to_stub_data data;
18751
18752 data.writing_section = sec;
18753 data.contents = contents;
18754
a504d23a
LA		 18755 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18756 & data);
48229727
JB		 18757 }
18758
e489d0ae
PB		 18759 if (mapcount == 0)
18760 return FALSE;
18761
c7b8f16e 18762 if (globals->byteswap_code)
e489d0ae 18763 {
c7b8f16e 18764 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18765
c7b8f16e
JB		 18766 ptr = map[0].vma;
18767 for (i = 0; i < mapcount; i++)
99059e56
RM		 18768 {
18769 if (i == mapcount - 1)
c7b8f16e 18770 end = sec->size;
99059e56
RM		 18771 else
18772 end = map[i + 1].vma;
e489d0ae 18773
99059e56 18774 switch (map[i].type)
e489d0ae 18775 {
c7b8f16e
JB		 18776 case 'a':
18777 /* Byte swap code words. */
18778 while (ptr + 3 < end)
99059e56
RM		 18779 {
18780 tmp = contents[ptr];
18781 contents[ptr] = contents[ptr + 3];
18782 contents[ptr + 3] = tmp;
18783 tmp = contents[ptr + 1];
18784 contents[ptr + 1] = contents[ptr + 2];
18785 contents[ptr + 2] = tmp;
18786 ptr += 4;
18787 }
c7b8f16e 18788 break;
e489d0ae 18789
c7b8f16e
JB		 18790 case 't':
18791 /* Byte swap code halfwords. */
18792 while (ptr + 1 < end)
99059e56
RM		 18793 {
18794 tmp = contents[ptr];
18795 contents[ptr] = contents[ptr + 1];
18796 contents[ptr + 1] = tmp;
18797 ptr += 2;
18798 }
c7b8f16e
JB		 18799 break;
18800
18801 case 'd':
18802 /* Leave data alone. */
18803 break;
18804 }
99059e56
RM		 18805 ptr = end;
18806 }
e489d0ae 18807 }
8e3de13a 18808
93204d3a 18809 free (map);
47b2e99c 18810 arm_data->mapcount = -1;
c7b8f16e 18811 arm_data->mapsize = 0;
8e3de13a 18812 arm_data->map = NULL;
8e3de13a 18813
e489d0ae
PB		 18814 return FALSE;
18815}
18816
0beaef2b
PB		 18817/* Mangle thumb function symbols as we read them in. */
18818
8384fb8f 18819static bfd_boolean
0beaef2b
PB		 18820elf32_arm_swap_symbol_in (bfd * abfd,
18821 const void *psrc,
18822 const void *pshn,
18823 Elf_Internal_Sym *dst)
18824{
4ba2ef8f
TP		 18825 Elf_Internal_Shdr *symtab_hdr;
18826 const char *name = NULL;
18827
8384fb8f
AM		 18828 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18829 return FALSE;
39d911fc 18830 dst->st_target_internal = 0;
0beaef2b
PB		 18831
18832 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18833 the address. */
63e1a0fc
PB		 18834 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18835 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18836 {
63e1a0fc
PB		 18837 if (dst->st_value & 1)
18838 {
18839 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18840 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18841 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18842 }
18843 else
39d911fc 18844 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18845 }
18846 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18847 {
18848 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18849 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18850 }
35fc36a8 18851 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18852 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18853 else
39d911fc 18854 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18855
4ba2ef8f
TP		 18856 /* Mark CMSE special symbols. */
18857 symtab_hdr = & elf_symtab_hdr (abfd);
18858 if (symtab_hdr->sh_size)
18859 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18860 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18861 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18862
8384fb8f 18863 return TRUE;
0beaef2b
PB		 18864}
18865
18866
18867/* Mangle thumb function symbols as we write them out. */
18868
18869static void
18870elf32_arm_swap_symbol_out (bfd *abfd,
18871 const Elf_Internal_Sym *src,
18872 void *cdst,
18873 void *shndx)
18874{
18875 Elf_Internal_Sym newsym;
18876
18877 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18878 of the address set, as per the new EABI. We do this unconditionally
18879 because objcopy does not set the elf header flags until after
18880 it writes out the symbol table. */
39d911fc 18881 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18882 {
18883 newsym = *src;
34e77a92
RS		 18884 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18885 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18886 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18887 {
18888 /* Do this only for defined symbols. At link type, the static
18889 linker will simulate the work of dynamic linker of resolving
18890 symbols and will carry over the thumbness of found symbols to
18891 the output symbol table. It's not clear how it happens, but
18892 the thumbness of undefined symbols can well be different at
18893 runtime, and writing '1' for them will be confusing for users
18894 and possibly for dynamic linker itself.
18895 */
18896 newsym.st_value |= 1;
18897 }
906e58ca 18898
0beaef2b
PB		 18899 src = &newsym;
18900 }
18901 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18902}
18903
b294bdf8
MM		 18904/* Add the PT_ARM_EXIDX program header. */
18905
18906static bfd_boolean
906e58ca 18907elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18908 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18909{
18910 struct elf_segment_map *m;
18911 asection *sec;
18912
18913 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18914 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18915 {
18916 /* If there is already a PT_ARM_EXIDX header, then we do not
18917 want to add another one. This situation arises when running
18918 "strip"; the input binary already has the header. */
12bd6957 18919 m = elf_seg_map (abfd);
b294bdf8
MM		 18920 while (m && m->p_type != PT_ARM_EXIDX)
18921 m = m->next;
18922 if (!m)
18923 {
21d799b5 18924 m = (struct elf_segment_map *)
99059e56 18925 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18926 if (m == NULL)
18927 return FALSE;
18928 m->p_type = PT_ARM_EXIDX;
18929 m->count = 1;
18930 m->sections[0] = sec;
18931
12bd6957
AM		 18932 m->next = elf_seg_map (abfd);
18933 elf_seg_map (abfd) = m;
b294bdf8
MM		 18934 }
18935 }
18936
18937 return TRUE;
18938}
18939
18940/* We may add a PT_ARM_EXIDX program header. */
18941
18942static int
a6b96beb
AM		 18943elf32_arm_additional_program_headers (bfd *abfd,
18944 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18945{
18946 asection *sec;
18947
18948 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18949 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18950 return 1;
18951 else
18952 return 0;
18953}
18954
34e77a92
RS		 18955/* Hook called by the linker routine which adds symbols from an object
18956 file. */
18957
18958static bfd_boolean
18959elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18960 Elf_Internal_Sym *sym, const char **namep,
18961 flagword *flagsp, asection **secp, bfd_vma *valp)
18962{
a43942db 18963 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18964 && (abfd->flags & DYNAMIC) == 0
18965 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18966 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18967
c792917c
NC		 18968 if (elf32_arm_hash_table (info) == NULL)
18969 return FALSE;
18970
34e77a92
RS		 18971 if (elf32_arm_hash_table (info)->vxworks_p
18972 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18973 flagsp, secp, valp))
18974 return FALSE;
18975
18976 return TRUE;
18977}
18978
0beaef2b 18979/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18980const struct elf_size_info elf32_arm_size_info =
18981{
0beaef2b
PB		 18982 sizeof (Elf32_External_Ehdr),
18983 sizeof (Elf32_External_Phdr),
18984 sizeof (Elf32_External_Shdr),
18985 sizeof (Elf32_External_Rel),
18986 sizeof (Elf32_External_Rela),
18987 sizeof (Elf32_External_Sym),
18988 sizeof (Elf32_External_Dyn),
18989 sizeof (Elf_External_Note),
18990 4,
18991 1,
18992 32, 2,
18993 ELFCLASS32, EV_CURRENT,
18994 bfd_elf32_write_out_phdrs,
18995 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18996 bfd_elf32_checksum_contents,
0beaef2b
PB		 18997 bfd_elf32_write_relocs,
18998 elf32_arm_swap_symbol_in,
18999 elf32_arm_swap_symbol_out,
19000 bfd_elf32_slurp_reloc_table,
19001 bfd_elf32_slurp_symbol_table,
19002 bfd_elf32_swap_dyn_in,
19003 bfd_elf32_swap_dyn_out,
19004 bfd_elf32_swap_reloc_in,
19005 bfd_elf32_swap_reloc_out,
19006 bfd_elf32_swap_reloca_in,
19007 bfd_elf32_swap_reloca_out
19008};
19009
685e70ae
VK		 19010static bfd_vma
19011read_code32 (const bfd *abfd, const bfd_byte *addr)
19012{
19013 /* V7 BE8 code is always little endian. */
19014 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19015 return bfd_getl32 (addr);
19016
19017 return bfd_get_32 (abfd, addr);
19018}
19019
19020static bfd_vma
19021read_code16 (const bfd *abfd, const bfd_byte *addr)
19022{
19023 /* V7 BE8 code is always little endian. */
19024 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19025 return bfd_getl16 (addr);
19026
19027 return bfd_get_16 (abfd, addr);
19028}
19029
6a631e86
YG		 19030/* Return size of plt0 entry starting at ADDR
19031 or (bfd_vma) -1 if size can not be determined. */
19032
19033static bfd_vma
19034elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19035{
19036 bfd_vma first_word;
19037 bfd_vma plt0_size;
19038
685e70ae 19039 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19040
19041 if (first_word == elf32_arm_plt0_entry[0])
19042 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19043 else if (first_word == elf32_thumb2_plt0_entry[0])
19044 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19045 else
19046 /* We don't yet handle this PLT format. */
19047 return (bfd_vma) -1;
19048
19049 return plt0_size;
19050}
19051
19052/* Return size of plt entry starting at offset OFFSET
19053 of plt section located at address START
19054 or (bfd_vma) -1 if size can not be determined. */
19055
19056static bfd_vma
19057elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19058{
19059 bfd_vma first_insn;
19060 bfd_vma plt_size = 0;
19061 const bfd_byte *addr = start + offset;
19062
19063 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19064 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19065 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19066
19067 /* Respect Thumb stub if necessary. */
685e70ae 19068 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19069 {
19070 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19071 }
19072
19073 /* Strip immediate from first add. */
685e70ae 19074 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19075
19076#ifdef FOUR_WORD_PLT
19077 if (first_insn == elf32_arm_plt_entry[0])
19078 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19079#else
19080 if (first_insn == elf32_arm_plt_entry_long[0])
19081 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19082 else if (first_insn == elf32_arm_plt_entry_short[0])
19083 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19084#endif
19085 else
19086 /* We don't yet handle this PLT format. */
19087 return (bfd_vma) -1;
19088
19089 return plt_size;
19090}
19091
19092/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19093
19094static long
19095elf32_arm_get_synthetic_symtab (bfd *abfd,
19096 long symcount ATTRIBUTE_UNUSED,
19097 asymbol **syms ATTRIBUTE_UNUSED,
19098 long dynsymcount,
19099 asymbol **dynsyms,
19100 asymbol **ret)
19101{
19102 asection *relplt;
19103 asymbol *s;
19104 arelent *p;
19105 long count, i, n;
19106 size_t size;
19107 Elf_Internal_Shdr *hdr;
19108 char *names;
19109 asection *plt;
19110 bfd_vma offset;
19111 bfd_byte *data;
19112
19113 *ret = NULL;
19114
19115 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19116 return 0;
19117
19118 if (dynsymcount <= 0)
19119 return 0;
19120
19121 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19122 if (relplt == NULL)
19123 return 0;
19124
19125 hdr = &elf_section_data (relplt)->this_hdr;
19126 if (hdr->sh_link != elf_dynsymtab (abfd)
19127 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19128 return 0;
19129
19130 plt = bfd_get_section_by_name (abfd, ".plt");
19131 if (plt == NULL)
19132 return 0;
19133
19134 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19135 return -1;
19136
19137 data = plt->contents;
19138 if (data == NULL)
19139 {
19140 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19141 return -1;
19142 bfd_cache_section_contents((asection *) plt, data);
19143 }
19144
19145 count = relplt->size / hdr->sh_entsize;
19146 size = count * sizeof (asymbol);
19147 p = relplt->relocation;
19148 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19149 {
19150 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19151 if (p->addend != 0)
19152 size += sizeof ("+0x") - 1 + 8;
19153 }
19154
19155 s = *ret = (asymbol *) bfd_malloc (size);
19156 if (s == NULL)
19157 return -1;
19158
19159 offset = elf32_arm_plt0_size (abfd, data);
19160 if (offset == (bfd_vma) -1)
19161 return -1;
19162
19163 names = (char *) (s + count);
19164 p = relplt->relocation;
19165 n = 0;
19166 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19167 {
19168 size_t len;
19169
19170 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19171 if (plt_size == (bfd_vma) -1)
19172 break;
19173
19174 *s = **p->sym_ptr_ptr;
19175 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19176 we are defining a symbol, ensure one of them is set. */
19177 if ((s->flags & BSF_LOCAL) == 0)
19178 s->flags |= BSF_GLOBAL;
19179 s->flags |= BSF_SYNTHETIC;
19180 s->section = plt;
19181 s->value = offset;
19182 s->name = names;
19183 s->udata.p = NULL;
19184 len = strlen ((*p->sym_ptr_ptr)->name);
19185 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19186 names += len;
19187 if (p->addend != 0)
19188 {
19189 char buf[30], *a;
19190
19191 memcpy (names, "+0x", sizeof ("+0x") - 1);
19192 names += sizeof ("+0x") - 1;
19193 bfd_sprintf_vma (abfd, buf, p->addend);
19194 for (a = buf; *a == '0'; ++a)
19195 ;
19196 len = strlen (a);
19197 memcpy (names, a, len);
19198 names += len;
19199 }
19200 memcpy (names, "@plt", sizeof ("@plt"));
19201 names += sizeof ("@plt");
19202 ++s, ++n;
19203 offset += plt_size;
19204 }
19205
19206 return n;
19207}
19208
ac4c9b04
MG		 19209static bfd_boolean
19210elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19211{
f0728ee3
AV		 19212 if (hdr->sh_flags & SHF_ARM_PURECODE)
19213 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19214 return TRUE;
19215}
19216
19217static flagword
19218elf32_arm_lookup_section_flags (char *flag_name)
19219{
f0728ee3
AV		 19220 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19221 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19222
19223 return SEC_NO_FLAGS;
19224}
19225
491d01d3
YU		 19226static unsigned int
19227elf32_arm_count_additional_relocs (asection *sec)
19228{
19229 struct _arm_elf_section_data *arm_data;
19230 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19231
6342be70 19232 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19233}
19234
5522f910 19235/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19236 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19237 FALSE otherwise. ISECTION is the best guess matching section from the
19238 input bfd IBFD, but it might be NULL. */
19239
19240static bfd_boolean
19241elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19242 bfd *obfd ATTRIBUTE_UNUSED,
19243 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19244 Elf_Internal_Shdr *osection)
19245{
19246 switch (osection->sh_type)
19247 {
19248 case SHT_ARM_EXIDX:
19249 {
19250 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19251 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19252 unsigned i = 0;
19253
19254 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19255 osection->sh_info = 0;
19256
19257 /* The sh_link field must be set to the text section associated with
19258 this index section. Unfortunately the ARM EHABI does not specify
19259 exactly how to determine this association. Our caller does try
19260 to match up OSECTION with its corresponding input section however
19261 so that is a good first guess. */
19262 if (isection != NULL
19263 && osection->bfd_section != NULL
19264 && isection->bfd_section != NULL
19265 && isection->bfd_section->output_section != NULL
19266 && isection->bfd_section->output_section == osection->bfd_section
19267 && iheaders != NULL
19268 && isection->sh_link > 0
19269 && isection->sh_link < elf_numsections (ibfd)
19270 && iheaders[isection->sh_link]->bfd_section != NULL
19271 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19272 )
19273 {
19274 for (i = elf_numsections (obfd); i-- > 0;)
19275 if (oheaders[i]->bfd_section
19276 == iheaders[isection->sh_link]->bfd_section->output_section)
19277 break;
19278 }
9eaff861 19279
5522f910
NC		 19280 if (i == 0)
19281 {
19282 /* Failing that we have to find a matching section ourselves. If
19283 we had the output section name available we could compare that
19284 with input section names. Unfortunately we don't. So instead
19285 we use a simple heuristic and look for the nearest executable
19286 section before this one. */
19287 for (i = elf_numsections (obfd); i-- > 0;)
19288 if (oheaders[i] == osection)
19289 break;
19290 if (i == 0)
19291 break;
19292
19293 while (i-- > 0)
19294 if (oheaders[i]->sh_type == SHT_PROGBITS
19295 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19296 == (SHF_ALLOC | SHF_EXECINSTR))
19297 break;
19298 }
19299
19300 if (i)
19301 {
19302 osection->sh_link = i;
19303 /* If the text section was part of a group
19304 then the index section should be too. */
19305 if (oheaders[i]->sh_flags & SHF_GROUP)
19306 osection->sh_flags |= SHF_GROUP;
19307 return TRUE;
19308 }
19309 }
19310 break;
19311
19312 case SHT_ARM_PREEMPTMAP:
19313 osection->sh_flags = SHF_ALLOC;
19314 break;
19315
19316 case SHT_ARM_ATTRIBUTES:
19317 case SHT_ARM_DEBUGOVERLAY:
19318 case SHT_ARM_OVERLAYSECTION:
19319 default:
19320 break;
19321 }
19322
19323 return FALSE;
19324}
19325
d691934d
NC		 19326/* Returns TRUE if NAME is an ARM mapping symbol.
19327 Traditionally the symbols $a, $d and $t have been used.
19328 The ARM ELF standard also defines $x (for A64 code). It also allows a
19329 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19330 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19331 not support them here. $t.x indicates the start of ThumbEE instructions. */
19332
19333static bfd_boolean
19334is_arm_mapping_symbol (const char * name)
19335{
19336 return name != NULL /* Paranoia. */
19337 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19338 the mapping symbols could have acquired a prefix.
19339 We do not support this here, since such symbols no
19340 longer conform to the ARM ELF ABI. */
19341 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19342 && (name[2] == 0 || name[2] == '.');
19343 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19344 any characters that follow the period are legal characters for the body
19345 of a symbol's name. For now we just assume that this is the case. */
19346}
19347
fca2a38f
NC		 19348/* Make sure that mapping symbols in object files are not removed via the
19349 "strip --strip-unneeded" tool. These symbols are needed in order to
19350 correctly generate interworking veneers, and for byte swapping code
19351 regions. Once an object file has been linked, it is safe to remove the
19352 symbols as they will no longer be needed. */
19353
19354static void
19355elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19356{
19357 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19358 && sym->section != bfd_abs_section_ptr
d691934d 19359 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19360 sym->flags |= BSF_KEEP;
19361}
19362
5522f910
NC		 19363#undef elf_backend_copy_special_section_fields
19364#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19365
252b5132 19366#define ELF_ARCH bfd_arch_arm
ae95ffa6 19367#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19368#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19369#ifdef __QNXTARGET__
19370#define ELF_MAXPAGESIZE 0x1000
19371#else
7572ca89 19372#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19373#endif
b1342370 19374#define ELF_MINPAGESIZE 0x1000
24718e3b 19375#define ELF_COMMONPAGESIZE 0x1000
252b5132 19376
ba93b8ac
DJ		 19377#define bfd_elf32_mkobject elf32_arm_mkobject
19378
99e4ae17
AJ		 19379#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19380#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19381#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19382#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19383#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19384#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19385#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19386#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19387#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19388#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19389#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19390#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19391#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19392
19393#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19394#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19395#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19396#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19397#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19398#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19399#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19400#define elf_backend_write_section elf32_arm_write_section
252b5132 19401#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19402#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19403#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19404#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19405#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19406#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19407#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19408#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19409#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19410#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19411#define elf_backend_fake_sections elf32_arm_fake_sections
19412#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19413#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19414#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19415#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19416#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19417#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19418#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19419#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19420#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19421#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19422#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19423#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19424
19425#define elf_backend_can_refcount 1
19426#define elf_backend_can_gc_sections 1
19427#define elf_backend_plt_readonly 1
19428#define elf_backend_want_got_plt 1
19429#define elf_backend_want_plt_sym 0
5474d94f 19430#define elf_backend_want_dynrelro 1
906e58ca
NC		 19431#define elf_backend_may_use_rel_p 1
19432#define elf_backend_may_use_rela_p 0
4e7fd91e 19433#define elf_backend_default_use_rela_p 0
64f52338 19434#define elf_backend_dtrel_excludes_plt 1
252b5132 19435
04f7c78d 19436#define elf_backend_got_header_size 12
b68a20d6 19437#define elf_backend_extern_protected_data 1
04f7c78d 19438
906e58ca
NC		 19439#undef elf_backend_obj_attrs_vendor
19440#define elf_backend_obj_attrs_vendor "aeabi"
19441#undef elf_backend_obj_attrs_section
19442#define elf_backend_obj_attrs_section ".ARM.attributes"
19443#undef elf_backend_obj_attrs_arg_type
19444#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19445#undef elf_backend_obj_attrs_section_type
104d59d1 19446#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19447#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19448#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19449
5025eb7c 19450#undef elf_backend_section_flags
ac4c9b04 19451#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19452#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19453#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19454
252b5132 19455#include "elf32-target.h"
7f266840 19456
b38cadfb
NC		 19457/* Native Client targets. */
19458
19459#undef TARGET_LITTLE_SYM
6d00b590 19460#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19461#undef TARGET_LITTLE_NAME
19462#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19463#undef TARGET_BIG_SYM
6d00b590 19464#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19465#undef TARGET_BIG_NAME
19466#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19467
19468/* Like elf32_arm_link_hash_table_create -- but overrides
19469 appropriately for NaCl. */
19470
19471static struct bfd_link_hash_table *
19472elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19473{
19474 struct bfd_link_hash_table *ret;
19475
19476 ret = elf32_arm_link_hash_table_create (abfd);
19477 if (ret)
19478 {
19479 struct elf32_arm_link_hash_table *htab
19480 = (struct elf32_arm_link_hash_table *) ret;
19481
19482 htab->nacl_p = 1;
19483
19484 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19485 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19486 }
19487 return ret;
19488}
19489
19490/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19491 really need to use elf32_arm_modify_segment_map. But we do it
19492 anyway just to reduce gratuitous differences with the stock ARM backend. */
19493
19494static bfd_boolean
19495elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19496{
19497 return (elf32_arm_modify_segment_map (abfd, info)
19498 && nacl_modify_segment_map (abfd, info));
19499}
19500
887badb3
RM		 19501static void
19502elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19503{
19504 elf32_arm_final_write_processing (abfd, linker);
19505 nacl_final_write_processing (abfd, linker);
19506}
19507
6a631e86
YG		 19508static bfd_vma
19509elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19510 const arelent *rel ATTRIBUTE_UNUSED)
19511{
19512 return plt->vma
19513 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19514 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19515}
887badb3 19516
b38cadfb 19517#undef elf32_bed
6a631e86 19518#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19519#undef bfd_elf32_bfd_link_hash_table_create
19520#define bfd_elf32_bfd_link_hash_table_create \
19521 elf32_arm_nacl_link_hash_table_create
19522#undef elf_backend_plt_alignment
6a631e86 19523#define elf_backend_plt_alignment 4
b38cadfb
NC		 19524#undef elf_backend_modify_segment_map
19525#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19526#undef elf_backend_modify_program_headers
19527#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19528#undef elf_backend_final_write_processing
19529#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19530#undef bfd_elf32_get_synthetic_symtab
19531#undef elf_backend_plt_sym_val
19532#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19533#undef elf_backend_copy_special_section_fields
b38cadfb 19534
887badb3
RM		 19535#undef ELF_MINPAGESIZE
19536#undef ELF_COMMONPAGESIZE
19537
b38cadfb
NC		 19538
19539#include "elf32-target.h"
19540
19541/* Reset to defaults. */
19542#undef elf_backend_plt_alignment
19543#undef elf_backend_modify_segment_map
19544#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19545#undef elf_backend_modify_program_headers
887badb3
RM		 19546#undef elf_backend_final_write_processing
19547#define elf_backend_final_write_processing elf32_arm_final_write_processing
19548#undef ELF_MINPAGESIZE
19549#define ELF_MINPAGESIZE 0x1000
19550#undef ELF_COMMONPAGESIZE
19551#define ELF_COMMONPAGESIZE 0x1000
19552
b38cadfb 19553
906e58ca 19554/* VxWorks Targets. */
4e7fd91e 19555
906e58ca 19556#undef TARGET_LITTLE_SYM
6d00b590 19557#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19558#undef TARGET_LITTLE_NAME
4e7fd91e 19559#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19560#undef TARGET_BIG_SYM
6d00b590 19561#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19562#undef TARGET_BIG_NAME
4e7fd91e
PB		 19563#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19564
19565/* Like elf32_arm_link_hash_table_create -- but overrides
19566 appropriately for VxWorks. */
906e58ca 19567
4e7fd91e
PB		 19568static struct bfd_link_hash_table *
19569elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19570{
19571 struct bfd_link_hash_table *ret;
19572
19573 ret = elf32_arm_link_hash_table_create (abfd);
19574 if (ret)
19575 {
19576 struct elf32_arm_link_hash_table *htab
00a97672 19577 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19578 htab->use_rel = 0;
00a97672 19579 htab->vxworks_p = 1;
4e7fd91e
PB		 19580 }
19581 return ret;
906e58ca 19582}
4e7fd91e 19583
00a97672
RS		 19584static void
19585elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19586{
19587 elf32_arm_final_write_processing (abfd, linker);
19588 elf_vxworks_final_write_processing (abfd, linker);
19589}
19590
906e58ca 19591#undef elf32_bed
4e7fd91e
PB		 19592#define elf32_bed elf32_arm_vxworks_bed
19593
906e58ca
NC		 19594#undef bfd_elf32_bfd_link_hash_table_create
19595#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19596#undef elf_backend_final_write_processing
19597#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19598#undef elf_backend_emit_relocs
9eaff861 19599#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19600
906e58ca 19601#undef elf_backend_may_use_rel_p
00a97672 19602#define elf_backend_may_use_rel_p 0
906e58ca 19603#undef elf_backend_may_use_rela_p
00a97672 19604#define elf_backend_may_use_rela_p 1
906e58ca 19605#undef elf_backend_default_use_rela_p
00a97672 19606#define elf_backend_default_use_rela_p 1
906e58ca 19607#undef elf_backend_want_plt_sym
00a97672 19608#define elf_backend_want_plt_sym 1
906e58ca 19609#undef ELF_MAXPAGESIZE
00a97672 19610#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19611
19612#include "elf32-target.h"
19613
19614
21d799b5
NC		 19615/* Merge backend specific data from an object file to the output
19616 object file when linking. */
19617
19618static bfd_boolean
50e03d47 19619elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19620{
50e03d47 19621 bfd *obfd = info->output_bfd;
21d799b5
NC		 19622 flagword out_flags;
19623 flagword in_flags;
19624 bfd_boolean flags_compatible = TRUE;
19625 asection *sec;
19626
cc643b88 19627 /* Check if we have the same endianness. */
50e03d47 19628 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19629 return FALSE;
19630
19631 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19632 return TRUE;
19633
50e03d47 19634 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19635 return FALSE;
19636
19637 /* The input BFD must have had its flags initialised. */
19638 /* The following seems bogus to me -- The flags are initialized in
19639 the assembler but I don't think an elf_flags_init field is
19640 written into the object. */
19641 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19642
19643 in_flags = elf_elfheader (ibfd)->e_flags;
19644 out_flags = elf_elfheader (obfd)->e_flags;
19645
19646 /* In theory there is no reason why we couldn't handle this. However
19647 in practice it isn't even close to working and there is no real
19648 reason to want it. */
19649 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19650 && !(ibfd->flags & DYNAMIC)
19651 && (in_flags & EF_ARM_BE8))
19652 {
19653 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19654 ibfd);
19655 return FALSE;
19656 }
19657
19658 if (!elf_flags_init (obfd))
19659 {
19660 /* If the input is the default architecture and had the default
19661 flags then do not bother setting the flags for the output
19662 architecture, instead allow future merges to do this. If no
19663 future merges ever set these flags then they will retain their
99059e56
RM		 19664 uninitialised values, which surprise surprise, correspond
19665 to the default values. */
21d799b5
NC		 19666 if (bfd_get_arch_info (ibfd)->the_default
19667 && elf_elfheader (ibfd)->e_flags == 0)
19668 return TRUE;
19669
19670 elf_flags_init (obfd) = TRUE;
19671 elf_elfheader (obfd)->e_flags = in_flags;
19672
19673 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19674 && bfd_get_arch_info (obfd)->the_default)
19675 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19676
19677 return TRUE;
19678 }
19679
19680 /* Determine what should happen if the input ARM architecture
19681 does not match the output ARM architecture. */
19682 if (! bfd_arm_merge_machines (ibfd, obfd))
19683 return FALSE;
19684
19685 /* Identical flags must be compatible. */
19686 if (in_flags == out_flags)
19687 return TRUE;
19688
19689 /* Check to see if the input BFD actually contains any sections. If
19690 not, its flags may not have been initialised either, but it
19691 cannot actually cause any incompatiblity. Do not short-circuit
19692 dynamic objects; their section list may be emptied by
19693 elf_link_add_object_symbols.
19694
19695 Also check to see if there are no code sections in the input.
19696 In this case there is no need to check for code specific flags.
19697 XXX - do we need to worry about floating-point format compatability
19698 in data sections ? */
19699 if (!(ibfd->flags & DYNAMIC))
19700 {
19701 bfd_boolean null_input_bfd = TRUE;
19702 bfd_boolean only_data_sections = TRUE;
19703
19704 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19705 {
19706 /* Ignore synthetic glue sections. */
19707 if (strcmp (sec->name, ".glue_7")
19708 && strcmp (sec->name, ".glue_7t"))
19709 {
19710 if ((bfd_get_section_flags (ibfd, sec)
19711 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19712 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19713 only_data_sections = FALSE;
21d799b5
NC		 19714
19715 null_input_bfd = FALSE;
19716 break;
19717 }
19718 }
19719
19720 if (null_input_bfd || only_data_sections)
19721 return TRUE;
19722 }
19723
19724 /* Complain about various flag mismatches. */
19725 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19726 EF_ARM_EABI_VERSION (out_flags)))
19727 {
19728 _bfd_error_handler
19729 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
c08bb8dd
AM		 19730 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
19731 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 19732 return FALSE;
19733 }
19734
19735 /* Not sure what needs to be checked for EABI versions >= 1. */
19736 /* VxWorks libraries do not use these flags. */
19737 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19738 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19739 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19740 {
19741 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19742 {
19743 _bfd_error_handler
19744 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
c08bb8dd
AM		 19745 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
19746 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 19747 flags_compatible = FALSE;
19748 }
19749
19750 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19751 {
19752 if (in_flags & EF_ARM_APCS_FLOAT)
19753 _bfd_error_handler
19754 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19755 ibfd, obfd);
19756 else
19757 _bfd_error_handler
19758 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19759 ibfd, obfd);
19760
19761 flags_compatible = FALSE;
19762 }
19763
19764 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19765 {
19766 if (in_flags & EF_ARM_VFP_FLOAT)
19767 _bfd_error_handler
19768 (_("error: %B uses VFP instructions, whereas %B does not"),
19769 ibfd, obfd);
19770 else
19771 _bfd_error_handler
19772 (_("error: %B uses FPA instructions, whereas %B does not"),
19773 ibfd, obfd);
19774
19775 flags_compatible = FALSE;
19776 }
19777
19778 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19779 {
19780 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19781 _bfd_error_handler
19782 (_("error: %B uses Maverick instructions, whereas %B does not"),
19783 ibfd, obfd);
19784 else
19785 _bfd_error_handler
19786 (_("error: %B does not use Maverick instructions, whereas %B does"),
19787 ibfd, obfd);
19788
19789 flags_compatible = FALSE;
19790 }
19791
19792#ifdef EF_ARM_SOFT_FLOAT
19793 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19794 {
19795 /* We can allow interworking between code that is VFP format
19796 layout, and uses either soft float or integer regs for
19797 passing floating point arguments and results. We already
19798 know that the APCS_FLOAT flags match; similarly for VFP
19799 flags. */
19800 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19801 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19802 {
19803 if (in_flags & EF_ARM_SOFT_FLOAT)
19804 _bfd_error_handler
19805 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19806 ibfd, obfd);
19807 else
19808 _bfd_error_handler
19809 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19810 ibfd, obfd);
19811
19812 flags_compatible = FALSE;
19813 }
19814 }
19815#endif
19816
19817 /* Interworking mismatch is only a warning. */
19818 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19819 {
19820 if (in_flags & EF_ARM_INTERWORK)
19821 {
19822 _bfd_error_handler
19823 (_("Warning: %B supports interworking, whereas %B does not"),
19824 ibfd, obfd);
19825 }
19826 else
19827 {
19828 _bfd_error_handler
19829 (_("Warning: %B does not support interworking, whereas %B does"),
19830 ibfd, obfd);
19831 }
19832 }
19833 }
19834
19835 return flags_compatible;
19836}
19837
19838
906e58ca 19839/* Symbian OS Targets. */
7f266840 19840
906e58ca 19841#undef TARGET_LITTLE_SYM
6d00b590 19842#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19843#undef TARGET_LITTLE_NAME
7f266840 19844#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19845#undef TARGET_BIG_SYM
6d00b590 19846#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19847#undef TARGET_BIG_NAME
7f266840
DJ		 19848#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19849
19850/* Like elf32_arm_link_hash_table_create -- but overrides
19851 appropriately for Symbian OS. */
906e58ca 19852
7f266840
DJ		 19853static struct bfd_link_hash_table *
19854elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19855{
19856 struct bfd_link_hash_table *ret;
19857
19858 ret = elf32_arm_link_hash_table_create (abfd);
19859 if (ret)
19860 {
19861 struct elf32_arm_link_hash_table *htab
19862 = (struct elf32_arm_link_hash_table *)ret;
19863 /* There is no PLT header for Symbian OS. */
19864 htab->plt_header_size = 0;
95720a86
DJ		 19865 /* The PLT entries are each one instruction and one word. */
19866 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19867 htab->symbian_p = 1;
33bfe774
JB		 19868 /* Symbian uses armv5t or above, so use_blx is always true. */
19869 htab->use_blx = 1;
67687978 19870 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19871 }
19872 return ret;
906e58ca 19873}
7f266840 19874
b35d266b 19875static const struct bfd_elf_special_section
551b43fd 19876elf32_arm_symbian_special_sections[] =
7f266840 19877{
5cd3778d
MM		 19878 /* In a BPABI executable, the dynamic linking sections do not go in
19879 the loadable read-only segment. The post-linker may wish to
19880 refer to these sections, but they are not part of the final
19881 program image. */
0112cd26
NC		 19882 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19883 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19884 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19885 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19886 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19887 /* These sections do not need to be writable as the SymbianOS
19888 postlinker will arrange things so that no dynamic relocation is
19889 required. */
0112cd26
NC		 19890 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19891 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19892 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19893 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19894};
19895
c3c76620 19896static void
906e58ca 19897elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19898 struct bfd_link_info *link_info)
c3c76620
MM		 19899{
19900 /* BPABI objects are never loaded directly by an OS kernel; they are
19901 processed by a postlinker first, into an OS-specific format. If
19902 the D_PAGED bit is set on the file, BFD will align segments on
19903 page boundaries, so that an OS can directly map the file. With
19904 BPABI objects, that just results in wasted space. In addition,
19905 because we clear the D_PAGED bit, map_sections_to_segments will
19906 recognize that the program headers should not be mapped into any
19907 loadable segment. */
19908 abfd->flags &= ~D_PAGED;
906e58ca 19909 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19910}
7f266840
DJ		 19911
19912static bfd_boolean
906e58ca 19913elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19914 struct bfd_link_info *info)
7f266840
DJ		 19915{
19916 struct elf_segment_map *m;
19917 asection *dynsec;
19918
7f266840
DJ		 19919 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19920 segment. However, because the .dynamic section is not marked
19921 with SEC_LOAD, the generic ELF code will not create such a
19922 segment. */
19923 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19924 if (dynsec)
19925 {
12bd6957 19926 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19927 if (m->p_type == PT_DYNAMIC)
19928 break;
19929
19930 if (m == NULL)
19931 {
19932 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19933 m->next = elf_seg_map (abfd);
19934 elf_seg_map (abfd) = m;
8ded5a0f 19935 }
7f266840
DJ		 19936 }
19937
b294bdf8
MM		 19938 /* Also call the generic arm routine. */
19939 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19940}
19941
95720a86
DJ		 19942/* Return address for Ith PLT stub in section PLT, for relocation REL
19943 or (bfd_vma) -1 if it should not be included. */
19944
19945static bfd_vma
19946elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19947 const arelent *rel ATTRIBUTE_UNUSED)
19948{
19949 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19950}
19951
8029a119 19952#undef elf32_bed
7f266840
DJ		 19953#define elf32_bed elf32_arm_symbian_bed
19954
19955/* The dynamic sections are not allocated on SymbianOS; the postlinker
19956 will process them and then discard them. */
906e58ca 19957#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19958#define ELF_DYNAMIC_SEC_FLAGS \
19959 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19960
9eaff861 19961#undef elf_backend_emit_relocs
c3c76620 19962
906e58ca
NC		 19963#undef bfd_elf32_bfd_link_hash_table_create
19964#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19965#undef elf_backend_special_sections
19966#define elf_backend_special_sections elf32_arm_symbian_special_sections
19967#undef elf_backend_begin_write_processing
19968#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19969#undef elf_backend_final_write_processing
19970#define elf_backend_final_write_processing elf32_arm_final_write_processing
19971
19972#undef elf_backend_modify_segment_map
7f266840
DJ		 19973#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19974
19975/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19976#undef elf_backend_got_header_size
7f266840
DJ		 19977#define elf_backend_got_header_size 0
19978
19979/* Similarly, there is no .got.plt section. */
906e58ca 19980#undef elf_backend_want_got_plt
7f266840
DJ		 19981#define elf_backend_want_got_plt 0
19982
906e58ca 19983#undef elf_backend_plt_sym_val
95720a86
DJ		 19984#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19985
906e58ca 19986#undef elf_backend_may_use_rel_p
00a97672 19987#define elf_backend_may_use_rel_p 1
906e58ca 19988#undef elf_backend_may_use_rela_p
00a97672 19989#define elf_backend_may_use_rela_p 0
906e58ca 19990#undef elf_backend_default_use_rela_p
00a97672 19991#define elf_backend_default_use_rela_p 0
906e58ca 19992#undef elf_backend_want_plt_sym
00a97672 19993#define elf_backend_want_plt_sym 0
64f52338
AM		 19994#undef elf_backend_dtrel_excludes_plt
19995#define elf_backend_dtrel_excludes_plt 0
906e58ca 19996#undef ELF_MAXPAGESIZE
00a97672 19997#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19998
7f266840 19999#include "elf32-target.h"
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