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[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI
[thirdparty/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
7f266840 31
00a97672
RS		 32/* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34#define RELOC_SECTION(HTAB, NAME) \
35 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
36
37/* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39#define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
43
44/* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46#define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
50
51/* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53#define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
57
f3185997 58#define elf_info_to_howto NULL
07d6d2b8 59#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 60
61#define ARM_ELF_ABI_VERSION 0
62#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
63
79f08007
YZ		 64/* The Adjusted Place, as defined by AAELF. */
65#define Pa(X) ((X) & 0xfffffffc)
66
3e6b1042
DJ		 67static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
68 struct bfd_link_info *link_info,
69 asection *sec,
70 bfd_byte *contents);
71
7f266840
DJ		 72/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
73 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
74 in that slot. */
75
c19d1205 76static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 77{
8029a119 78 /* No relocation. */
7f266840
DJ		 79 HOWTO (R_ARM_NONE, /* type */
80 0, /* rightshift */
6346d5ca 81 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 82 0, /* bitsize */
83 FALSE, /* pc_relative */
84 0, /* bitpos */
85 complain_overflow_dont,/* complain_on_overflow */
86 bfd_elf_generic_reloc, /* special_function */
87 "R_ARM_NONE", /* name */
88 FALSE, /* partial_inplace */
89 0, /* src_mask */
90 0, /* dst_mask */
91 FALSE), /* pcrel_offset */
92
93 HOWTO (R_ARM_PC24, /* type */
94 2, /* rightshift */
95 2, /* size (0 = byte, 1 = short, 2 = long) */
96 24, /* bitsize */
97 TRUE, /* pc_relative */
98 0, /* bitpos */
99 complain_overflow_signed,/* complain_on_overflow */
100 bfd_elf_generic_reloc, /* special_function */
101 "R_ARM_PC24", /* name */
102 FALSE, /* partial_inplace */
103 0x00ffffff, /* src_mask */
104 0x00ffffff, /* dst_mask */
105 TRUE), /* pcrel_offset */
106
107 /* 32 bit absolute */
108 HOWTO (R_ARM_ABS32, /* type */
109 0, /* rightshift */
110 2, /* size (0 = byte, 1 = short, 2 = long) */
111 32, /* bitsize */
112 FALSE, /* pc_relative */
113 0, /* bitpos */
114 complain_overflow_bitfield,/* complain_on_overflow */
115 bfd_elf_generic_reloc, /* special_function */
116 "R_ARM_ABS32", /* name */
117 FALSE, /* partial_inplace */
118 0xffffffff, /* src_mask */
119 0xffffffff, /* dst_mask */
120 FALSE), /* pcrel_offset */
121
122 /* standard 32bit pc-relative reloc */
123 HOWTO (R_ARM_REL32, /* type */
124 0, /* rightshift */
125 2, /* size (0 = byte, 1 = short, 2 = long) */
126 32, /* bitsize */
127 TRUE, /* pc_relative */
128 0, /* bitpos */
129 complain_overflow_bitfield,/* complain_on_overflow */
130 bfd_elf_generic_reloc, /* special_function */
131 "R_ARM_REL32", /* name */
132 FALSE, /* partial_inplace */
133 0xffffffff, /* src_mask */
134 0xffffffff, /* dst_mask */
135 TRUE), /* pcrel_offset */
136
c19d1205 137 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 138 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 139 0, /* rightshift */
140 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 141 32, /* bitsize */
142 TRUE, /* pc_relative */
7f266840 143 0, /* bitpos */
4962c51a 144 complain_overflow_dont,/* complain_on_overflow */
7f266840 145 bfd_elf_generic_reloc, /* special_function */
4962c51a 146 "R_ARM_LDR_PC_G0", /* name */
7f266840 147 FALSE, /* partial_inplace */
4962c51a
MS		 148 0xffffffff, /* src_mask */
149 0xffffffff, /* dst_mask */
150 TRUE), /* pcrel_offset */
7f266840
DJ		 151
152 /* 16 bit absolute */
153 HOWTO (R_ARM_ABS16, /* type */
154 0, /* rightshift */
155 1, /* size (0 = byte, 1 = short, 2 = long) */
156 16, /* bitsize */
157 FALSE, /* pc_relative */
158 0, /* bitpos */
159 complain_overflow_bitfield,/* complain_on_overflow */
160 bfd_elf_generic_reloc, /* special_function */
161 "R_ARM_ABS16", /* name */
162 FALSE, /* partial_inplace */
163 0x0000ffff, /* src_mask */
164 0x0000ffff, /* dst_mask */
165 FALSE), /* pcrel_offset */
166
167 /* 12 bit absolute */
168 HOWTO (R_ARM_ABS12, /* type */
169 0, /* rightshift */
170 2, /* size (0 = byte, 1 = short, 2 = long) */
171 12, /* bitsize */
172 FALSE, /* pc_relative */
173 0, /* bitpos */
174 complain_overflow_bitfield,/* complain_on_overflow */
175 bfd_elf_generic_reloc, /* special_function */
176 "R_ARM_ABS12", /* name */
177 FALSE, /* partial_inplace */
00a97672
RS		 178 0x00000fff, /* src_mask */
179 0x00000fff, /* dst_mask */
7f266840
DJ		 180 FALSE), /* pcrel_offset */
181
182 HOWTO (R_ARM_THM_ABS5, /* type */
183 6, /* rightshift */
184 1, /* size (0 = byte, 1 = short, 2 = long) */
185 5, /* bitsize */
186 FALSE, /* pc_relative */
187 0, /* bitpos */
188 complain_overflow_bitfield,/* complain_on_overflow */
189 bfd_elf_generic_reloc, /* special_function */
190 "R_ARM_THM_ABS5", /* name */
191 FALSE, /* partial_inplace */
192 0x000007e0, /* src_mask */
193 0x000007e0, /* dst_mask */
194 FALSE), /* pcrel_offset */
195
196 /* 8 bit absolute */
197 HOWTO (R_ARM_ABS8, /* type */
198 0, /* rightshift */
199 0, /* size (0 = byte, 1 = short, 2 = long) */
200 8, /* bitsize */
201 FALSE, /* pc_relative */
202 0, /* bitpos */
203 complain_overflow_bitfield,/* complain_on_overflow */
204 bfd_elf_generic_reloc, /* special_function */
205 "R_ARM_ABS8", /* name */
206 FALSE, /* partial_inplace */
207 0x000000ff, /* src_mask */
208 0x000000ff, /* dst_mask */
209 FALSE), /* pcrel_offset */
210
211 HOWTO (R_ARM_SBREL32, /* type */
212 0, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 32, /* bitsize */
215 FALSE, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_dont,/* complain_on_overflow */
218 bfd_elf_generic_reloc, /* special_function */
219 "R_ARM_SBREL32", /* name */
220 FALSE, /* partial_inplace */
221 0xffffffff, /* src_mask */
222 0xffffffff, /* dst_mask */
223 FALSE), /* pcrel_offset */
224
c19d1205 225 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 226 1, /* rightshift */
227 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 228 24, /* bitsize */
7f266840
DJ		 229 TRUE, /* pc_relative */
230 0, /* bitpos */
231 complain_overflow_signed,/* complain_on_overflow */
232 bfd_elf_generic_reloc, /* special_function */
c19d1205 233 "R_ARM_THM_CALL", /* name */
7f266840 234 FALSE, /* partial_inplace */
7f6ab9f8
AM		 235 0x07ff2fff, /* src_mask */
236 0x07ff2fff, /* dst_mask */
7f266840
DJ		 237 TRUE), /* pcrel_offset */
238
07d6d2b8 239 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 240 1, /* rightshift */
241 1, /* size (0 = byte, 1 = short, 2 = long) */
242 8, /* bitsize */
243 TRUE, /* pc_relative */
244 0, /* bitpos */
245 complain_overflow_signed,/* complain_on_overflow */
246 bfd_elf_generic_reloc, /* special_function */
247 "R_ARM_THM_PC8", /* name */
248 FALSE, /* partial_inplace */
249 0x000000ff, /* src_mask */
250 0x000000ff, /* dst_mask */
251 TRUE), /* pcrel_offset */
252
c19d1205 253 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 254 1, /* rightshift */
255 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 256 32, /* bitsize */
257 FALSE, /* pc_relative */
7f266840
DJ		 258 0, /* bitpos */
259 complain_overflow_signed,/* complain_on_overflow */
260 bfd_elf_generic_reloc, /* special_function */
c19d1205 261 "R_ARM_BREL_ADJ", /* name */
7f266840 262 FALSE, /* partial_inplace */
c19d1205
ZW		 263 0xffffffff, /* src_mask */
264 0xffffffff, /* dst_mask */
265 FALSE), /* pcrel_offset */
7f266840 266
0855e32b 267 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 268 0, /* rightshift */
0855e32b
NS		 269 2, /* size (0 = byte, 1 = short, 2 = long) */
270 32, /* bitsize */
7f266840
DJ		 271 FALSE, /* pc_relative */
272 0, /* bitpos */
0855e32b 273 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 274 bfd_elf_generic_reloc, /* special_function */
0855e32b 275 "R_ARM_TLS_DESC", /* name */
7f266840 276 FALSE, /* partial_inplace */
0855e32b
NS		 277 0xffffffff, /* src_mask */
278 0xffffffff, /* dst_mask */
7f266840
DJ		 279 FALSE), /* pcrel_offset */
280
281 HOWTO (R_ARM_THM_SWI8, /* type */
282 0, /* rightshift */
283 0, /* size (0 = byte, 1 = short, 2 = long) */
284 0, /* bitsize */
285 FALSE, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_signed,/* complain_on_overflow */
288 bfd_elf_generic_reloc, /* special_function */
289 "R_ARM_SWI8", /* name */
290 FALSE, /* partial_inplace */
291 0x00000000, /* src_mask */
292 0x00000000, /* dst_mask */
293 FALSE), /* pcrel_offset */
294
295 /* BLX instruction for the ARM. */
296 HOWTO (R_ARM_XPC25, /* type */
297 2, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 299 24, /* bitsize */
7f266840
DJ		 300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_signed,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_ARM_XPC25", /* name */
305 FALSE, /* partial_inplace */
306 0x00ffffff, /* src_mask */
307 0x00ffffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 /* BLX instruction for the Thumb. */
311 HOWTO (R_ARM_THM_XPC22, /* type */
312 2, /* rightshift */
313 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 314 24, /* bitsize */
7f266840
DJ		 315 TRUE, /* pc_relative */
316 0, /* bitpos */
317 complain_overflow_signed,/* complain_on_overflow */
318 bfd_elf_generic_reloc, /* special_function */
319 "R_ARM_THM_XPC22", /* name */
320 FALSE, /* partial_inplace */
7f6ab9f8
AM		 321 0x07ff2fff, /* src_mask */
322 0x07ff2fff, /* dst_mask */
7f266840
DJ		 323 TRUE), /* pcrel_offset */
324
ba93b8ac 325 /* Dynamic TLS relocations. */
7f266840 326
ba93b8ac 327 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
331 FALSE, /* pc_relative */
332 0, /* bitpos */
99059e56
RM		 333 complain_overflow_bitfield,/* complain_on_overflow */
334 bfd_elf_generic_reloc, /* special_function */
335 "R_ARM_TLS_DTPMOD32", /* name */
336 TRUE, /* partial_inplace */
337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
07d6d2b8 339 FALSE), /* pcrel_offset */
7f266840 340
ba93b8ac 341 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
345 FALSE, /* pc_relative */
346 0, /* bitpos */
99059e56
RM		 347 complain_overflow_bitfield,/* complain_on_overflow */
348 bfd_elf_generic_reloc, /* special_function */
349 "R_ARM_TLS_DTPOFF32", /* name */
350 TRUE, /* partial_inplace */
351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
07d6d2b8 353 FALSE), /* pcrel_offset */
7f266840 354
ba93b8ac 355 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 356 0, /* rightshift */
357 2, /* size (0 = byte, 1 = short, 2 = long) */
358 32, /* bitsize */
359 FALSE, /* pc_relative */
360 0, /* bitpos */
99059e56
RM		 361 complain_overflow_bitfield,/* complain_on_overflow */
362 bfd_elf_generic_reloc, /* special_function */
363 "R_ARM_TLS_TPOFF32", /* name */
364 TRUE, /* partial_inplace */
365 0xffffffff, /* src_mask */
366 0xffffffff, /* dst_mask */
07d6d2b8 367 FALSE), /* pcrel_offset */
7f266840
DJ		 368
369 /* Relocs used in ARM Linux */
370
371 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 372 0, /* rightshift */
373 2, /* size (0 = byte, 1 = short, 2 = long) */
374 32, /* bitsize */
375 FALSE, /* pc_relative */
376 0, /* bitpos */
99059e56
RM		 377 complain_overflow_bitfield,/* complain_on_overflow */
378 bfd_elf_generic_reloc, /* special_function */
379 "R_ARM_COPY", /* name */
380 TRUE, /* partial_inplace */
381 0xffffffff, /* src_mask */
382 0xffffffff, /* dst_mask */
07d6d2b8 383 FALSE), /* pcrel_offset */
7f266840
DJ		 384
385 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 386 0, /* rightshift */
387 2, /* size (0 = byte, 1 = short, 2 = long) */
388 32, /* bitsize */
389 FALSE, /* pc_relative */
390 0, /* bitpos */
99059e56
RM		 391 complain_overflow_bitfield,/* complain_on_overflow */
392 bfd_elf_generic_reloc, /* special_function */
393 "R_ARM_GLOB_DAT", /* name */
394 TRUE, /* partial_inplace */
395 0xffffffff, /* src_mask */
396 0xffffffff, /* dst_mask */
07d6d2b8 397 FALSE), /* pcrel_offset */
7f266840
DJ		 398
399 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 400 0, /* rightshift */
401 2, /* size (0 = byte, 1 = short, 2 = long) */
402 32, /* bitsize */
403 FALSE, /* pc_relative */
404 0, /* bitpos */
99059e56
RM		 405 complain_overflow_bitfield,/* complain_on_overflow */
406 bfd_elf_generic_reloc, /* special_function */
407 "R_ARM_JUMP_SLOT", /* name */
408 TRUE, /* partial_inplace */
409 0xffffffff, /* src_mask */
410 0xffffffff, /* dst_mask */
07d6d2b8 411 FALSE), /* pcrel_offset */
7f266840
DJ		 412
413 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 414 0, /* rightshift */
415 2, /* size (0 = byte, 1 = short, 2 = long) */
416 32, /* bitsize */
417 FALSE, /* pc_relative */
418 0, /* bitpos */
99059e56
RM		 419 complain_overflow_bitfield,/* complain_on_overflow */
420 bfd_elf_generic_reloc, /* special_function */
421 "R_ARM_RELATIVE", /* name */
422 TRUE, /* partial_inplace */
423 0xffffffff, /* src_mask */
424 0xffffffff, /* dst_mask */
07d6d2b8 425 FALSE), /* pcrel_offset */
7f266840 426
c19d1205 427 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 428 0, /* rightshift */
429 2, /* size (0 = byte, 1 = short, 2 = long) */
430 32, /* bitsize */
431 FALSE, /* pc_relative */
432 0, /* bitpos */
99059e56
RM		 433 complain_overflow_bitfield,/* complain_on_overflow */
434 bfd_elf_generic_reloc, /* special_function */
435 "R_ARM_GOTOFF32", /* name */
436 TRUE, /* partial_inplace */
437 0xffffffff, /* src_mask */
438 0xffffffff, /* dst_mask */
07d6d2b8 439 FALSE), /* pcrel_offset */
7f266840
DJ		 440
441 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 442 0, /* rightshift */
443 2, /* size (0 = byte, 1 = short, 2 = long) */
444 32, /* bitsize */
99059e56 445 TRUE, /* pc_relative */
07d6d2b8 446 0, /* bitpos */
99059e56
RM		 447 complain_overflow_bitfield,/* complain_on_overflow */
448 bfd_elf_generic_reloc, /* special_function */
449 "R_ARM_GOTPC", /* name */
450 TRUE, /* partial_inplace */
451 0xffffffff, /* src_mask */
452 0xffffffff, /* dst_mask */
453 TRUE), /* pcrel_offset */
7f266840
DJ		 454
455 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 456 0, /* rightshift */
457 2, /* size (0 = byte, 1 = short, 2 = long) */
458 32, /* bitsize */
99059e56 459 FALSE, /* pc_relative */
07d6d2b8 460 0, /* bitpos */
99059e56
RM		 461 complain_overflow_bitfield,/* complain_on_overflow */
462 bfd_elf_generic_reloc, /* special_function */
463 "R_ARM_GOT32", /* name */
464 TRUE, /* partial_inplace */
465 0xffffffff, /* src_mask */
466 0xffffffff, /* dst_mask */
467 FALSE), /* pcrel_offset */
7f266840
DJ		 468
469 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 470 2, /* rightshift */
471 2, /* size (0 = byte, 1 = short, 2 = long) */
472 24, /* bitsize */
99059e56 473 TRUE, /* pc_relative */
07d6d2b8 474 0, /* bitpos */
99059e56
RM		 475 complain_overflow_bitfield,/* complain_on_overflow */
476 bfd_elf_generic_reloc, /* special_function */
477 "R_ARM_PLT32", /* name */
478 FALSE, /* partial_inplace */
479 0x00ffffff, /* src_mask */
480 0x00ffffff, /* dst_mask */
481 TRUE), /* pcrel_offset */
7f266840
DJ		 482
483 HOWTO (R_ARM_CALL, /* type */
484 2, /* rightshift */
485 2, /* size (0 = byte, 1 = short, 2 = long) */
486 24, /* bitsize */
487 TRUE, /* pc_relative */
488 0, /* bitpos */
489 complain_overflow_signed,/* complain_on_overflow */
490 bfd_elf_generic_reloc, /* special_function */
491 "R_ARM_CALL", /* name */
492 FALSE, /* partial_inplace */
493 0x00ffffff, /* src_mask */
494 0x00ffffff, /* dst_mask */
495 TRUE), /* pcrel_offset */
496
497 HOWTO (R_ARM_JUMP24, /* type */
498 2, /* rightshift */
499 2, /* size (0 = byte, 1 = short, 2 = long) */
500 24, /* bitsize */
501 TRUE, /* pc_relative */
502 0, /* bitpos */
503 complain_overflow_signed,/* complain_on_overflow */
504 bfd_elf_generic_reloc, /* special_function */
505 "R_ARM_JUMP24", /* name */
506 FALSE, /* partial_inplace */
507 0x00ffffff, /* src_mask */
508 0x00ffffff, /* dst_mask */
509 TRUE), /* pcrel_offset */
510
c19d1205
ZW		 511 HOWTO (R_ARM_THM_JUMP24, /* type */
512 1, /* rightshift */
513 2, /* size (0 = byte, 1 = short, 2 = long) */
514 24, /* bitsize */
515 TRUE, /* pc_relative */
7f266840 516 0, /* bitpos */
c19d1205 517 complain_overflow_signed,/* complain_on_overflow */
7f266840 518 bfd_elf_generic_reloc, /* special_function */
c19d1205 519 "R_ARM_THM_JUMP24", /* name */
7f266840 520 FALSE, /* partial_inplace */
c19d1205
ZW		 521 0x07ff2fff, /* src_mask */
522 0x07ff2fff, /* dst_mask */
523 TRUE), /* pcrel_offset */
7f266840 524
c19d1205 525 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 526 0, /* rightshift */
c19d1205
ZW		 527 2, /* size (0 = byte, 1 = short, 2 = long) */
528 32, /* bitsize */
7f266840
DJ		 529 FALSE, /* pc_relative */
530 0, /* bitpos */
531 complain_overflow_dont,/* complain_on_overflow */
532 bfd_elf_generic_reloc, /* special_function */
c19d1205 533 "R_ARM_BASE_ABS", /* name */
7f266840 534 FALSE, /* partial_inplace */
c19d1205
ZW		 535 0xffffffff, /* src_mask */
536 0xffffffff, /* dst_mask */
7f266840
DJ		 537 FALSE), /* pcrel_offset */
538
539 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
540 0, /* rightshift */
541 2, /* size (0 = byte, 1 = short, 2 = long) */
542 12, /* bitsize */
543 TRUE, /* pc_relative */
544 0, /* bitpos */
545 complain_overflow_dont,/* complain_on_overflow */
546 bfd_elf_generic_reloc, /* special_function */
547 "R_ARM_ALU_PCREL_7_0", /* name */
548 FALSE, /* partial_inplace */
549 0x00000fff, /* src_mask */
550 0x00000fff, /* dst_mask */
551 TRUE), /* pcrel_offset */
552
553 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
554 0, /* rightshift */
555 2, /* size (0 = byte, 1 = short, 2 = long) */
556 12, /* bitsize */
557 TRUE, /* pc_relative */
558 8, /* bitpos */
559 complain_overflow_dont,/* complain_on_overflow */
560 bfd_elf_generic_reloc, /* special_function */
561 "R_ARM_ALU_PCREL_15_8",/* name */
562 FALSE, /* partial_inplace */
563 0x00000fff, /* src_mask */
564 0x00000fff, /* dst_mask */
565 TRUE), /* pcrel_offset */
566
567 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
568 0, /* rightshift */
569 2, /* size (0 = byte, 1 = short, 2 = long) */
570 12, /* bitsize */
571 TRUE, /* pc_relative */
572 16, /* bitpos */
573 complain_overflow_dont,/* complain_on_overflow */
574 bfd_elf_generic_reloc, /* special_function */
575 "R_ARM_ALU_PCREL_23_15",/* name */
576 FALSE, /* partial_inplace */
577 0x00000fff, /* src_mask */
578 0x00000fff, /* dst_mask */
579 TRUE), /* pcrel_offset */
580
581 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
582 0, /* rightshift */
583 2, /* size (0 = byte, 1 = short, 2 = long) */
584 12, /* bitsize */
585 FALSE, /* pc_relative */
586 0, /* bitpos */
587 complain_overflow_dont,/* complain_on_overflow */
588 bfd_elf_generic_reloc, /* special_function */
589 "R_ARM_LDR_SBREL_11_0",/* name */
590 FALSE, /* partial_inplace */
591 0x00000fff, /* src_mask */
592 0x00000fff, /* dst_mask */
593 FALSE), /* pcrel_offset */
594
595 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
596 0, /* rightshift */
597 2, /* size (0 = byte, 1 = short, 2 = long) */
598 8, /* bitsize */
599 FALSE, /* pc_relative */
600 12, /* bitpos */
601 complain_overflow_dont,/* complain_on_overflow */
602 bfd_elf_generic_reloc, /* special_function */
603 "R_ARM_ALU_SBREL_19_12",/* name */
604 FALSE, /* partial_inplace */
605 0x000ff000, /* src_mask */
606 0x000ff000, /* dst_mask */
607 FALSE), /* pcrel_offset */
608
609 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
610 0, /* rightshift */
611 2, /* size (0 = byte, 1 = short, 2 = long) */
612 8, /* bitsize */
613 FALSE, /* pc_relative */
614 20, /* bitpos */
615 complain_overflow_dont,/* complain_on_overflow */
616 bfd_elf_generic_reloc, /* special_function */
617 "R_ARM_ALU_SBREL_27_20",/* name */
618 FALSE, /* partial_inplace */
619 0x0ff00000, /* src_mask */
620 0x0ff00000, /* dst_mask */
621 FALSE), /* pcrel_offset */
622
623 HOWTO (R_ARM_TARGET1, /* type */
624 0, /* rightshift */
625 2, /* size (0 = byte, 1 = short, 2 = long) */
626 32, /* bitsize */
627 FALSE, /* pc_relative */
628 0, /* bitpos */
629 complain_overflow_dont,/* complain_on_overflow */
630 bfd_elf_generic_reloc, /* special_function */
631 "R_ARM_TARGET1", /* name */
632 FALSE, /* partial_inplace */
633 0xffffffff, /* src_mask */
634 0xffffffff, /* dst_mask */
635 FALSE), /* pcrel_offset */
636
637 HOWTO (R_ARM_ROSEGREL32, /* type */
638 0, /* rightshift */
639 2, /* size (0 = byte, 1 = short, 2 = long) */
640 32, /* bitsize */
641 FALSE, /* pc_relative */
642 0, /* bitpos */
643 complain_overflow_dont,/* complain_on_overflow */
644 bfd_elf_generic_reloc, /* special_function */
645 "R_ARM_ROSEGREL32", /* name */
646 FALSE, /* partial_inplace */
647 0xffffffff, /* src_mask */
648 0xffffffff, /* dst_mask */
649 FALSE), /* pcrel_offset */
650
651 HOWTO (R_ARM_V4BX, /* type */
652 0, /* rightshift */
653 2, /* size (0 = byte, 1 = short, 2 = long) */
654 32, /* bitsize */
655 FALSE, /* pc_relative */
656 0, /* bitpos */
657 complain_overflow_dont,/* complain_on_overflow */
658 bfd_elf_generic_reloc, /* special_function */
659 "R_ARM_V4BX", /* name */
660 FALSE, /* partial_inplace */
661 0xffffffff, /* src_mask */
662 0xffffffff, /* dst_mask */
663 FALSE), /* pcrel_offset */
664
665 HOWTO (R_ARM_TARGET2, /* type */
666 0, /* rightshift */
667 2, /* size (0 = byte, 1 = short, 2 = long) */
668 32, /* bitsize */
669 FALSE, /* pc_relative */
670 0, /* bitpos */
671 complain_overflow_signed,/* complain_on_overflow */
672 bfd_elf_generic_reloc, /* special_function */
673 "R_ARM_TARGET2", /* name */
674 FALSE, /* partial_inplace */
675 0xffffffff, /* src_mask */
676 0xffffffff, /* dst_mask */
677 TRUE), /* pcrel_offset */
678
679 HOWTO (R_ARM_PREL31, /* type */
680 0, /* rightshift */
681 2, /* size (0 = byte, 1 = short, 2 = long) */
682 31, /* bitsize */
683 TRUE, /* pc_relative */
684 0, /* bitpos */
685 complain_overflow_signed,/* complain_on_overflow */
686 bfd_elf_generic_reloc, /* special_function */
687 "R_ARM_PREL31", /* name */
688 FALSE, /* partial_inplace */
689 0x7fffffff, /* src_mask */
690 0x7fffffff, /* dst_mask */
691 TRUE), /* pcrel_offset */
c19d1205
ZW		 692
693 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
694 0, /* rightshift */
695 2, /* size (0 = byte, 1 = short, 2 = long) */
696 16, /* bitsize */
697 FALSE, /* pc_relative */
698 0, /* bitpos */
699 complain_overflow_dont,/* complain_on_overflow */
700 bfd_elf_generic_reloc, /* special_function */
701 "R_ARM_MOVW_ABS_NC", /* name */
702 FALSE, /* partial_inplace */
39623e12
PB		 703 0x000f0fff, /* src_mask */
704 0x000f0fff, /* dst_mask */
c19d1205
ZW		 705 FALSE), /* pcrel_offset */
706
707 HOWTO (R_ARM_MOVT_ABS, /* type */
708 0, /* rightshift */
709 2, /* size (0 = byte, 1 = short, 2 = long) */
710 16, /* bitsize */
711 FALSE, /* pc_relative */
712 0, /* bitpos */
713 complain_overflow_bitfield,/* complain_on_overflow */
714 bfd_elf_generic_reloc, /* special_function */
715 "R_ARM_MOVT_ABS", /* name */
716 FALSE, /* partial_inplace */
39623e12
PB		 717 0x000f0fff, /* src_mask */
718 0x000f0fff, /* dst_mask */
c19d1205
ZW		 719 FALSE), /* pcrel_offset */
720
721 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
722 0, /* rightshift */
723 2, /* size (0 = byte, 1 = short, 2 = long) */
724 16, /* bitsize */
725 TRUE, /* pc_relative */
726 0, /* bitpos */
727 complain_overflow_dont,/* complain_on_overflow */
728 bfd_elf_generic_reloc, /* special_function */
729 "R_ARM_MOVW_PREL_NC", /* name */
730 FALSE, /* partial_inplace */
39623e12
PB		 731 0x000f0fff, /* src_mask */
732 0x000f0fff, /* dst_mask */
c19d1205
ZW		 733 TRUE), /* pcrel_offset */
734
735 HOWTO (R_ARM_MOVT_PREL, /* type */
736 0, /* rightshift */
737 2, /* size (0 = byte, 1 = short, 2 = long) */
738 16, /* bitsize */
739 TRUE, /* pc_relative */
740 0, /* bitpos */
741 complain_overflow_bitfield,/* complain_on_overflow */
742 bfd_elf_generic_reloc, /* special_function */
743 "R_ARM_MOVT_PREL", /* name */
744 FALSE, /* partial_inplace */
39623e12
PB		 745 0x000f0fff, /* src_mask */
746 0x000f0fff, /* dst_mask */
c19d1205
ZW		 747 TRUE), /* pcrel_offset */
748
749 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
750 0, /* rightshift */
751 2, /* size (0 = byte, 1 = short, 2 = long) */
752 16, /* bitsize */
753 FALSE, /* pc_relative */
754 0, /* bitpos */
755 complain_overflow_dont,/* complain_on_overflow */
756 bfd_elf_generic_reloc, /* special_function */
757 "R_ARM_THM_MOVW_ABS_NC",/* name */
758 FALSE, /* partial_inplace */
759 0x040f70ff, /* src_mask */
760 0x040f70ff, /* dst_mask */
761 FALSE), /* pcrel_offset */
762
763 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
764 0, /* rightshift */
765 2, /* size (0 = byte, 1 = short, 2 = long) */
766 16, /* bitsize */
767 FALSE, /* pc_relative */
768 0, /* bitpos */
769 complain_overflow_bitfield,/* complain_on_overflow */
770 bfd_elf_generic_reloc, /* special_function */
771 "R_ARM_THM_MOVT_ABS", /* name */
772 FALSE, /* partial_inplace */
773 0x040f70ff, /* src_mask */
774 0x040f70ff, /* dst_mask */
775 FALSE), /* pcrel_offset */
776
777 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
778 0, /* rightshift */
779 2, /* size (0 = byte, 1 = short, 2 = long) */
780 16, /* bitsize */
781 TRUE, /* pc_relative */
782 0, /* bitpos */
783 complain_overflow_dont,/* complain_on_overflow */
784 bfd_elf_generic_reloc, /* special_function */
785 "R_ARM_THM_MOVW_PREL_NC",/* name */
786 FALSE, /* partial_inplace */
787 0x040f70ff, /* src_mask */
788 0x040f70ff, /* dst_mask */
789 TRUE), /* pcrel_offset */
790
791 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
792 0, /* rightshift */
793 2, /* size (0 = byte, 1 = short, 2 = long) */
794 16, /* bitsize */
795 TRUE, /* pc_relative */
796 0, /* bitpos */
797 complain_overflow_bitfield,/* complain_on_overflow */
798 bfd_elf_generic_reloc, /* special_function */
799 "R_ARM_THM_MOVT_PREL", /* name */
800 FALSE, /* partial_inplace */
801 0x040f70ff, /* src_mask */
802 0x040f70ff, /* dst_mask */
803 TRUE), /* pcrel_offset */
804
805 HOWTO (R_ARM_THM_JUMP19, /* type */
806 1, /* rightshift */
807 2, /* size (0 = byte, 1 = short, 2 = long) */
808 19, /* bitsize */
809 TRUE, /* pc_relative */
810 0, /* bitpos */
811 complain_overflow_signed,/* complain_on_overflow */
812 bfd_elf_generic_reloc, /* special_function */
813 "R_ARM_THM_JUMP19", /* name */
814 FALSE, /* partial_inplace */
815 0x043f2fff, /* src_mask */
816 0x043f2fff, /* dst_mask */
817 TRUE), /* pcrel_offset */
818
819 HOWTO (R_ARM_THM_JUMP6, /* type */
820 1, /* rightshift */
821 1, /* size (0 = byte, 1 = short, 2 = long) */
822 6, /* bitsize */
823 TRUE, /* pc_relative */
824 0, /* bitpos */
825 complain_overflow_unsigned,/* complain_on_overflow */
826 bfd_elf_generic_reloc, /* special_function */
827 "R_ARM_THM_JUMP6", /* name */
828 FALSE, /* partial_inplace */
829 0x02f8, /* src_mask */
830 0x02f8, /* dst_mask */
831 TRUE), /* pcrel_offset */
832
833 /* These are declared as 13-bit signed relocations because we can
834 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
835 versa. */
836 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
837 0, /* rightshift */
838 2, /* size (0 = byte, 1 = short, 2 = long) */
839 13, /* bitsize */
840 TRUE, /* pc_relative */
841 0, /* bitpos */
2cab6cc3 842 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 843 bfd_elf_generic_reloc, /* special_function */
844 "R_ARM_THM_ALU_PREL_11_0",/* name */
845 FALSE, /* partial_inplace */
2cab6cc3
MS		 846 0xffffffff, /* src_mask */
847 0xffffffff, /* dst_mask */
c19d1205
ZW		 848 TRUE), /* pcrel_offset */
849
850 HOWTO (R_ARM_THM_PC12, /* type */
851 0, /* rightshift */
852 2, /* size (0 = byte, 1 = short, 2 = long) */
853 13, /* bitsize */
854 TRUE, /* pc_relative */
855 0, /* bitpos */
2cab6cc3 856 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 857 bfd_elf_generic_reloc, /* special_function */
858 "R_ARM_THM_PC12", /* name */
859 FALSE, /* partial_inplace */
2cab6cc3
MS		 860 0xffffffff, /* src_mask */
861 0xffffffff, /* dst_mask */
c19d1205
ZW		 862 TRUE), /* pcrel_offset */
863
864 HOWTO (R_ARM_ABS32_NOI, /* type */
865 0, /* rightshift */
866 2, /* size (0 = byte, 1 = short, 2 = long) */
867 32, /* bitsize */
868 FALSE, /* pc_relative */
869 0, /* bitpos */
870 complain_overflow_dont,/* complain_on_overflow */
871 bfd_elf_generic_reloc, /* special_function */
872 "R_ARM_ABS32_NOI", /* name */
873 FALSE, /* partial_inplace */
874 0xffffffff, /* src_mask */
875 0xffffffff, /* dst_mask */
876 FALSE), /* pcrel_offset */
877
878 HOWTO (R_ARM_REL32_NOI, /* type */
879 0, /* rightshift */
880 2, /* size (0 = byte, 1 = short, 2 = long) */
881 32, /* bitsize */
882 TRUE, /* pc_relative */
883 0, /* bitpos */
884 complain_overflow_dont,/* complain_on_overflow */
885 bfd_elf_generic_reloc, /* special_function */
886 "R_ARM_REL32_NOI", /* name */
887 FALSE, /* partial_inplace */
888 0xffffffff, /* src_mask */
889 0xffffffff, /* dst_mask */
890 FALSE), /* pcrel_offset */
7f266840 891
4962c51a
MS		 892 /* Group relocations. */
893
894 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
895 0, /* rightshift */
896 2, /* size (0 = byte, 1 = short, 2 = long) */
897 32, /* bitsize */
898 TRUE, /* pc_relative */
899 0, /* bitpos */
900 complain_overflow_dont,/* complain_on_overflow */
901 bfd_elf_generic_reloc, /* special_function */
902 "R_ARM_ALU_PC_G0_NC", /* name */
903 FALSE, /* partial_inplace */
904 0xffffffff, /* src_mask */
905 0xffffffff, /* dst_mask */
906 TRUE), /* pcrel_offset */
907
07d6d2b8 908 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 909 0, /* rightshift */
910 2, /* size (0 = byte, 1 = short, 2 = long) */
911 32, /* bitsize */
912 TRUE, /* pc_relative */
913 0, /* bitpos */
914 complain_overflow_dont,/* complain_on_overflow */
915 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 916 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 917 FALSE, /* partial_inplace */
918 0xffffffff, /* src_mask */
919 0xffffffff, /* dst_mask */
920 TRUE), /* pcrel_offset */
921
922 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
923 0, /* rightshift */
924 2, /* size (0 = byte, 1 = short, 2 = long) */
925 32, /* bitsize */
926 TRUE, /* pc_relative */
927 0, /* bitpos */
928 complain_overflow_dont,/* complain_on_overflow */
929 bfd_elf_generic_reloc, /* special_function */
930 "R_ARM_ALU_PC_G1_NC", /* name */
931 FALSE, /* partial_inplace */
932 0xffffffff, /* src_mask */
933 0xffffffff, /* dst_mask */
934 TRUE), /* pcrel_offset */
935
07d6d2b8 936 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 937 0, /* rightshift */
938 2, /* size (0 = byte, 1 = short, 2 = long) */
939 32, /* bitsize */
940 TRUE, /* pc_relative */
941 0, /* bitpos */
942 complain_overflow_dont,/* complain_on_overflow */
943 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 944 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 945 FALSE, /* partial_inplace */
946 0xffffffff, /* src_mask */
947 0xffffffff, /* dst_mask */
948 TRUE), /* pcrel_offset */
949
07d6d2b8 950 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 951 0, /* rightshift */
952 2, /* size (0 = byte, 1 = short, 2 = long) */
953 32, /* bitsize */
954 TRUE, /* pc_relative */
955 0, /* bitpos */
956 complain_overflow_dont,/* complain_on_overflow */
957 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 958 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 959 FALSE, /* partial_inplace */
960 0xffffffff, /* src_mask */
961 0xffffffff, /* dst_mask */
962 TRUE), /* pcrel_offset */
963
07d6d2b8 964 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 965 0, /* rightshift */
966 2, /* size (0 = byte, 1 = short, 2 = long) */
967 32, /* bitsize */
968 TRUE, /* pc_relative */
969 0, /* bitpos */
970 complain_overflow_dont,/* complain_on_overflow */
971 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 972 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 973 FALSE, /* partial_inplace */
974 0xffffffff, /* src_mask */
975 0xffffffff, /* dst_mask */
976 TRUE), /* pcrel_offset */
977
07d6d2b8 978 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 979 0, /* rightshift */
980 2, /* size (0 = byte, 1 = short, 2 = long) */
981 32, /* bitsize */
982 TRUE, /* pc_relative */
983 0, /* bitpos */
984 complain_overflow_dont,/* complain_on_overflow */
985 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 986 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 987 FALSE, /* partial_inplace */
988 0xffffffff, /* src_mask */
989 0xffffffff, /* dst_mask */
990 TRUE), /* pcrel_offset */
991
07d6d2b8 992 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 993 0, /* rightshift */
994 2, /* size (0 = byte, 1 = short, 2 = long) */
995 32, /* bitsize */
996 TRUE, /* pc_relative */
997 0, /* bitpos */
998 complain_overflow_dont,/* complain_on_overflow */
999 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1000 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1001 FALSE, /* partial_inplace */
1002 0xffffffff, /* src_mask */
1003 0xffffffff, /* dst_mask */
1004 TRUE), /* pcrel_offset */
1005
07d6d2b8 1006 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1007 0, /* rightshift */
1008 2, /* size (0 = byte, 1 = short, 2 = long) */
1009 32, /* bitsize */
1010 TRUE, /* pc_relative */
1011 0, /* bitpos */
1012 complain_overflow_dont,/* complain_on_overflow */
1013 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1014 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1015 FALSE, /* partial_inplace */
1016 0xffffffff, /* src_mask */
1017 0xffffffff, /* dst_mask */
1018 TRUE), /* pcrel_offset */
1019
07d6d2b8 1020 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1021 0, /* rightshift */
1022 2, /* size (0 = byte, 1 = short, 2 = long) */
1023 32, /* bitsize */
1024 TRUE, /* pc_relative */
1025 0, /* bitpos */
1026 complain_overflow_dont,/* complain_on_overflow */
1027 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1028 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1029 FALSE, /* partial_inplace */
1030 0xffffffff, /* src_mask */
1031 0xffffffff, /* dst_mask */
1032 TRUE), /* pcrel_offset */
1033
07d6d2b8 1034 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1035 0, /* rightshift */
1036 2, /* size (0 = byte, 1 = short, 2 = long) */
1037 32, /* bitsize */
1038 TRUE, /* pc_relative */
1039 0, /* bitpos */
1040 complain_overflow_dont,/* complain_on_overflow */
1041 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1042 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1043 FALSE, /* partial_inplace */
1044 0xffffffff, /* src_mask */
1045 0xffffffff, /* dst_mask */
1046 TRUE), /* pcrel_offset */
1047
07d6d2b8 1048 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1049 0, /* rightshift */
1050 2, /* size (0 = byte, 1 = short, 2 = long) */
1051 32, /* bitsize */
1052 TRUE, /* pc_relative */
1053 0, /* bitpos */
1054 complain_overflow_dont,/* complain_on_overflow */
1055 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1056 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1057 FALSE, /* partial_inplace */
1058 0xffffffff, /* src_mask */
1059 0xffffffff, /* dst_mask */
1060 TRUE), /* pcrel_offset */
1061
07d6d2b8 1062 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1063 0, /* rightshift */
1064 2, /* size (0 = byte, 1 = short, 2 = long) */
1065 32, /* bitsize */
1066 TRUE, /* pc_relative */
1067 0, /* bitpos */
1068 complain_overflow_dont,/* complain_on_overflow */
1069 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1070 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1071 FALSE, /* partial_inplace */
1072 0xffffffff, /* src_mask */
1073 0xffffffff, /* dst_mask */
1074 TRUE), /* pcrel_offset */
1075
07d6d2b8 1076 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1077 0, /* rightshift */
1078 2, /* size (0 = byte, 1 = short, 2 = long) */
1079 32, /* bitsize */
1080 TRUE, /* pc_relative */
1081 0, /* bitpos */
1082 complain_overflow_dont,/* complain_on_overflow */
1083 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1084 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1085 FALSE, /* partial_inplace */
1086 0xffffffff, /* src_mask */
1087 0xffffffff, /* dst_mask */
1088 TRUE), /* pcrel_offset */
1089
07d6d2b8 1090 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1091 0, /* rightshift */
1092 2, /* size (0 = byte, 1 = short, 2 = long) */
1093 32, /* bitsize */
1094 TRUE, /* pc_relative */
1095 0, /* bitpos */
1096 complain_overflow_dont,/* complain_on_overflow */
1097 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1098 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1099 FALSE, /* partial_inplace */
1100 0xffffffff, /* src_mask */
1101 0xffffffff, /* dst_mask */
1102 TRUE), /* pcrel_offset */
1103
07d6d2b8 1104 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1105 0, /* rightshift */
1106 2, /* size (0 = byte, 1 = short, 2 = long) */
1107 32, /* bitsize */
1108 TRUE, /* pc_relative */
1109 0, /* bitpos */
1110 complain_overflow_dont,/* complain_on_overflow */
1111 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1112 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1113 FALSE, /* partial_inplace */
1114 0xffffffff, /* src_mask */
1115 0xffffffff, /* dst_mask */
1116 TRUE), /* pcrel_offset */
1117
07d6d2b8 1118 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1119 0, /* rightshift */
1120 2, /* size (0 = byte, 1 = short, 2 = long) */
1121 32, /* bitsize */
1122 TRUE, /* pc_relative */
1123 0, /* bitpos */
1124 complain_overflow_dont,/* complain_on_overflow */
1125 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1126 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1127 FALSE, /* partial_inplace */
1128 0xffffffff, /* src_mask */
1129 0xffffffff, /* dst_mask */
1130 TRUE), /* pcrel_offset */
1131
07d6d2b8 1132 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1133 0, /* rightshift */
1134 2, /* size (0 = byte, 1 = short, 2 = long) */
1135 32, /* bitsize */
1136 TRUE, /* pc_relative */
1137 0, /* bitpos */
1138 complain_overflow_dont,/* complain_on_overflow */
1139 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1140 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1141 FALSE, /* partial_inplace */
1142 0xffffffff, /* src_mask */
1143 0xffffffff, /* dst_mask */
1144 TRUE), /* pcrel_offset */
1145
07d6d2b8 1146 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1147 0, /* rightshift */
1148 2, /* size (0 = byte, 1 = short, 2 = long) */
1149 32, /* bitsize */
1150 TRUE, /* pc_relative */
1151 0, /* bitpos */
1152 complain_overflow_dont,/* complain_on_overflow */
1153 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1154 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1155 FALSE, /* partial_inplace */
1156 0xffffffff, /* src_mask */
1157 0xffffffff, /* dst_mask */
1158 TRUE), /* pcrel_offset */
1159
07d6d2b8 1160 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1161 0, /* rightshift */
1162 2, /* size (0 = byte, 1 = short, 2 = long) */
1163 32, /* bitsize */
1164 TRUE, /* pc_relative */
1165 0, /* bitpos */
1166 complain_overflow_dont,/* complain_on_overflow */
1167 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1168 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1169 FALSE, /* partial_inplace */
1170 0xffffffff, /* src_mask */
1171 0xffffffff, /* dst_mask */
1172 TRUE), /* pcrel_offset */
1173
07d6d2b8 1174 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1175 0, /* rightshift */
1176 2, /* size (0 = byte, 1 = short, 2 = long) */
1177 32, /* bitsize */
1178 TRUE, /* pc_relative */
1179 0, /* bitpos */
1180 complain_overflow_dont,/* complain_on_overflow */
1181 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1182 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1183 FALSE, /* partial_inplace */
1184 0xffffffff, /* src_mask */
1185 0xffffffff, /* dst_mask */
1186 TRUE), /* pcrel_offset */
1187
07d6d2b8 1188 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1189 0, /* rightshift */
1190 2, /* size (0 = byte, 1 = short, 2 = long) */
1191 32, /* bitsize */
1192 TRUE, /* pc_relative */
1193 0, /* bitpos */
1194 complain_overflow_dont,/* complain_on_overflow */
1195 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1196 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1197 FALSE, /* partial_inplace */
1198 0xffffffff, /* src_mask */
1199 0xffffffff, /* dst_mask */
1200 TRUE), /* pcrel_offset */
1201
07d6d2b8 1202 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1203 0, /* rightshift */
1204 2, /* size (0 = byte, 1 = short, 2 = long) */
1205 32, /* bitsize */
1206 TRUE, /* pc_relative */
1207 0, /* bitpos */
1208 complain_overflow_dont,/* complain_on_overflow */
1209 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1210 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1211 FALSE, /* partial_inplace */
1212 0xffffffff, /* src_mask */
1213 0xffffffff, /* dst_mask */
1214 TRUE), /* pcrel_offset */
1215
07d6d2b8 1216 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1217 0, /* rightshift */
1218 2, /* size (0 = byte, 1 = short, 2 = long) */
1219 32, /* bitsize */
1220 TRUE, /* pc_relative */
1221 0, /* bitpos */
1222 complain_overflow_dont,/* complain_on_overflow */
1223 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1224 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1225 FALSE, /* partial_inplace */
1226 0xffffffff, /* src_mask */
1227 0xffffffff, /* dst_mask */
1228 TRUE), /* pcrel_offset */
1229
07d6d2b8 1230 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1231 0, /* rightshift */
1232 2, /* size (0 = byte, 1 = short, 2 = long) */
1233 32, /* bitsize */
1234 TRUE, /* pc_relative */
1235 0, /* bitpos */
1236 complain_overflow_dont,/* complain_on_overflow */
1237 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1238 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1239 FALSE, /* partial_inplace */
1240 0xffffffff, /* src_mask */
1241 0xffffffff, /* dst_mask */
1242 TRUE), /* pcrel_offset */
1243
07d6d2b8 1244 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1245 0, /* rightshift */
1246 2, /* size (0 = byte, 1 = short, 2 = long) */
1247 32, /* bitsize */
1248 TRUE, /* pc_relative */
1249 0, /* bitpos */
1250 complain_overflow_dont,/* complain_on_overflow */
1251 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1252 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1253 FALSE, /* partial_inplace */
1254 0xffffffff, /* src_mask */
1255 0xffffffff, /* dst_mask */
1256 TRUE), /* pcrel_offset */
1257
07d6d2b8 1258 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1259 0, /* rightshift */
1260 2, /* size (0 = byte, 1 = short, 2 = long) */
1261 32, /* bitsize */
1262 TRUE, /* pc_relative */
1263 0, /* bitpos */
1264 complain_overflow_dont,/* complain_on_overflow */
1265 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1266 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1267 FALSE, /* partial_inplace */
1268 0xffffffff, /* src_mask */
1269 0xffffffff, /* dst_mask */
1270 TRUE), /* pcrel_offset */
1271
1272 /* End of group relocations. */
c19d1205 1273
c19d1205
ZW		 1274 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1275 0, /* rightshift */
1276 2, /* size (0 = byte, 1 = short, 2 = long) */
1277 16, /* bitsize */
1278 FALSE, /* pc_relative */
1279 0, /* bitpos */
1280 complain_overflow_dont,/* complain_on_overflow */
1281 bfd_elf_generic_reloc, /* special_function */
1282 "R_ARM_MOVW_BREL_NC", /* name */
1283 FALSE, /* partial_inplace */
1284 0x0000ffff, /* src_mask */
1285 0x0000ffff, /* dst_mask */
1286 FALSE), /* pcrel_offset */
1287
1288 HOWTO (R_ARM_MOVT_BREL, /* type */
1289 0, /* rightshift */
1290 2, /* size (0 = byte, 1 = short, 2 = long) */
1291 16, /* bitsize */
1292 FALSE, /* pc_relative */
1293 0, /* bitpos */
1294 complain_overflow_bitfield,/* complain_on_overflow */
1295 bfd_elf_generic_reloc, /* special_function */
1296 "R_ARM_MOVT_BREL", /* name */
1297 FALSE, /* partial_inplace */
1298 0x0000ffff, /* src_mask */
1299 0x0000ffff, /* dst_mask */
1300 FALSE), /* pcrel_offset */
1301
1302 HOWTO (R_ARM_MOVW_BREL, /* type */
1303 0, /* rightshift */
1304 2, /* size (0 = byte, 1 = short, 2 = long) */
1305 16, /* bitsize */
1306 FALSE, /* pc_relative */
1307 0, /* bitpos */
1308 complain_overflow_dont,/* complain_on_overflow */
1309 bfd_elf_generic_reloc, /* special_function */
1310 "R_ARM_MOVW_BREL", /* name */
1311 FALSE, /* partial_inplace */
1312 0x0000ffff, /* src_mask */
1313 0x0000ffff, /* dst_mask */
1314 FALSE), /* pcrel_offset */
1315
1316 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1317 0, /* rightshift */
1318 2, /* size (0 = byte, 1 = short, 2 = long) */
1319 16, /* bitsize */
1320 FALSE, /* pc_relative */
1321 0, /* bitpos */
1322 complain_overflow_dont,/* complain_on_overflow */
1323 bfd_elf_generic_reloc, /* special_function */
1324 "R_ARM_THM_MOVW_BREL_NC",/* name */
1325 FALSE, /* partial_inplace */
1326 0x040f70ff, /* src_mask */
1327 0x040f70ff, /* dst_mask */
1328 FALSE), /* pcrel_offset */
1329
1330 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1331 0, /* rightshift */
1332 2, /* size (0 = byte, 1 = short, 2 = long) */
1333 16, /* bitsize */
1334 FALSE, /* pc_relative */
1335 0, /* bitpos */
1336 complain_overflow_bitfield,/* complain_on_overflow */
1337 bfd_elf_generic_reloc, /* special_function */
1338 "R_ARM_THM_MOVT_BREL", /* name */
1339 FALSE, /* partial_inplace */
1340 0x040f70ff, /* src_mask */
1341 0x040f70ff, /* dst_mask */
1342 FALSE), /* pcrel_offset */
1343
1344 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1345 0, /* rightshift */
1346 2, /* size (0 = byte, 1 = short, 2 = long) */
1347 16, /* bitsize */
1348 FALSE, /* pc_relative */
1349 0, /* bitpos */
1350 complain_overflow_dont,/* complain_on_overflow */
1351 bfd_elf_generic_reloc, /* special_function */
1352 "R_ARM_THM_MOVW_BREL", /* name */
1353 FALSE, /* partial_inplace */
1354 0x040f70ff, /* src_mask */
1355 0x040f70ff, /* dst_mask */
1356 FALSE), /* pcrel_offset */
1357
0855e32b
NS		 1358 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1359 0, /* rightshift */
1360 2, /* size (0 = byte, 1 = short, 2 = long) */
1361 32, /* bitsize */
1362 FALSE, /* pc_relative */
1363 0, /* bitpos */
1364 complain_overflow_bitfield,/* complain_on_overflow */
1365 NULL, /* special_function */
1366 "R_ARM_TLS_GOTDESC", /* name */
1367 TRUE, /* partial_inplace */
1368 0xffffffff, /* src_mask */
1369 0xffffffff, /* dst_mask */
1370 FALSE), /* pcrel_offset */
1371
1372 HOWTO (R_ARM_TLS_CALL, /* type */
1373 0, /* rightshift */
1374 2, /* size (0 = byte, 1 = short, 2 = long) */
1375 24, /* bitsize */
1376 FALSE, /* pc_relative */
1377 0, /* bitpos */
1378 complain_overflow_dont,/* complain_on_overflow */
1379 bfd_elf_generic_reloc, /* special_function */
1380 "R_ARM_TLS_CALL", /* name */
1381 FALSE, /* partial_inplace */
1382 0x00ffffff, /* src_mask */
1383 0x00ffffff, /* dst_mask */
1384 FALSE), /* pcrel_offset */
1385
1386 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1387 0, /* rightshift */
1388 2, /* size (0 = byte, 1 = short, 2 = long) */
1389 0, /* bitsize */
1390 FALSE, /* pc_relative */
1391 0, /* bitpos */
1392 complain_overflow_bitfield,/* complain_on_overflow */
1393 bfd_elf_generic_reloc, /* special_function */
1394 "R_ARM_TLS_DESCSEQ", /* name */
1395 FALSE, /* partial_inplace */
1396 0x00000000, /* src_mask */
1397 0x00000000, /* dst_mask */
1398 FALSE), /* pcrel_offset */
1399
1400 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1401 0, /* rightshift */
1402 2, /* size (0 = byte, 1 = short, 2 = long) */
1403 24, /* bitsize */
1404 FALSE, /* pc_relative */
1405 0, /* bitpos */
1406 complain_overflow_dont,/* complain_on_overflow */
1407 bfd_elf_generic_reloc, /* special_function */
1408 "R_ARM_THM_TLS_CALL", /* name */
1409 FALSE, /* partial_inplace */
1410 0x07ff07ff, /* src_mask */
1411 0x07ff07ff, /* dst_mask */
1412 FALSE), /* pcrel_offset */
c19d1205
ZW		 1413
1414 HOWTO (R_ARM_PLT32_ABS, /* type */
1415 0, /* rightshift */
1416 2, /* size (0 = byte, 1 = short, 2 = long) */
1417 32, /* bitsize */
1418 FALSE, /* pc_relative */
1419 0, /* bitpos */
1420 complain_overflow_dont,/* complain_on_overflow */
1421 bfd_elf_generic_reloc, /* special_function */
1422 "R_ARM_PLT32_ABS", /* name */
1423 FALSE, /* partial_inplace */
1424 0xffffffff, /* src_mask */
1425 0xffffffff, /* dst_mask */
1426 FALSE), /* pcrel_offset */
1427
1428 HOWTO (R_ARM_GOT_ABS, /* type */
1429 0, /* rightshift */
1430 2, /* size (0 = byte, 1 = short, 2 = long) */
1431 32, /* bitsize */
1432 FALSE, /* pc_relative */
1433 0, /* bitpos */
1434 complain_overflow_dont,/* complain_on_overflow */
1435 bfd_elf_generic_reloc, /* special_function */
1436 "R_ARM_GOT_ABS", /* name */
1437 FALSE, /* partial_inplace */
1438 0xffffffff, /* src_mask */
1439 0xffffffff, /* dst_mask */
1440 FALSE), /* pcrel_offset */
1441
1442 HOWTO (R_ARM_GOT_PREL, /* type */
1443 0, /* rightshift */
1444 2, /* size (0 = byte, 1 = short, 2 = long) */
1445 32, /* bitsize */
1446 TRUE, /* pc_relative */
1447 0, /* bitpos */
1448 complain_overflow_dont, /* complain_on_overflow */
1449 bfd_elf_generic_reloc, /* special_function */
1450 "R_ARM_GOT_PREL", /* name */
1451 FALSE, /* partial_inplace */
1452 0xffffffff, /* src_mask */
1453 0xffffffff, /* dst_mask */
1454 TRUE), /* pcrel_offset */
1455
1456 HOWTO (R_ARM_GOT_BREL12, /* type */
1457 0, /* rightshift */
1458 2, /* size (0 = byte, 1 = short, 2 = long) */
1459 12, /* bitsize */
1460 FALSE, /* pc_relative */
1461 0, /* bitpos */
1462 complain_overflow_bitfield,/* complain_on_overflow */
1463 bfd_elf_generic_reloc, /* special_function */
1464 "R_ARM_GOT_BREL12", /* name */
1465 FALSE, /* partial_inplace */
1466 0x00000fff, /* src_mask */
1467 0x00000fff, /* dst_mask */
1468 FALSE), /* pcrel_offset */
1469
1470 HOWTO (R_ARM_GOTOFF12, /* type */
1471 0, /* rightshift */
1472 2, /* size (0 = byte, 1 = short, 2 = long) */
1473 12, /* bitsize */
1474 FALSE, /* pc_relative */
1475 0, /* bitpos */
1476 complain_overflow_bitfield,/* complain_on_overflow */
1477 bfd_elf_generic_reloc, /* special_function */
1478 "R_ARM_GOTOFF12", /* name */
1479 FALSE, /* partial_inplace */
1480 0x00000fff, /* src_mask */
1481 0x00000fff, /* dst_mask */
1482 FALSE), /* pcrel_offset */
1483
07d6d2b8 1484 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1485
1486 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1487 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1488 0, /* rightshift */
1489 2, /* size (0 = byte, 1 = short, 2 = long) */
1490 0, /* bitsize */
1491 FALSE, /* pc_relative */
1492 0, /* bitpos */
99059e56 1493 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1494 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1495 "R_ARM_GNU_VTENTRY", /* name */
1496 FALSE, /* partial_inplace */
1497 0, /* src_mask */
1498 0, /* dst_mask */
1499 FALSE), /* pcrel_offset */
c19d1205
ZW		 1500
1501 /* GNU extension to record C++ vtable hierarchy */
1502 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1503 0, /* rightshift */
1504 2, /* size (0 = byte, 1 = short, 2 = long) */
1505 0, /* bitsize */
1506 FALSE, /* pc_relative */
1507 0, /* bitpos */
99059e56 1508 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1509 NULL, /* special_function */
99059e56 1510 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1511 FALSE, /* partial_inplace */
1512 0, /* src_mask */
1513 0, /* dst_mask */
1514 FALSE), /* pcrel_offset */
c19d1205
ZW		 1515
1516 HOWTO (R_ARM_THM_JUMP11, /* type */
1517 1, /* rightshift */
1518 1, /* size (0 = byte, 1 = short, 2 = long) */
1519 11, /* bitsize */
1520 TRUE, /* pc_relative */
1521 0, /* bitpos */
1522 complain_overflow_signed, /* complain_on_overflow */
1523 bfd_elf_generic_reloc, /* special_function */
1524 "R_ARM_THM_JUMP11", /* name */
1525 FALSE, /* partial_inplace */
1526 0x000007ff, /* src_mask */
1527 0x000007ff, /* dst_mask */
1528 TRUE), /* pcrel_offset */
1529
1530 HOWTO (R_ARM_THM_JUMP8, /* type */
1531 1, /* rightshift */
1532 1, /* size (0 = byte, 1 = short, 2 = long) */
1533 8, /* bitsize */
1534 TRUE, /* pc_relative */
1535 0, /* bitpos */
1536 complain_overflow_signed, /* complain_on_overflow */
1537 bfd_elf_generic_reloc, /* special_function */
1538 "R_ARM_THM_JUMP8", /* name */
1539 FALSE, /* partial_inplace */
1540 0x000000ff, /* src_mask */
1541 0x000000ff, /* dst_mask */
1542 TRUE), /* pcrel_offset */
ba93b8ac 1543
c19d1205
ZW		 1544 /* TLS relocations */
1545 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1546 0, /* rightshift */
1547 2, /* size (0 = byte, 1 = short, 2 = long) */
1548 32, /* bitsize */
1549 FALSE, /* pc_relative */
1550 0, /* bitpos */
99059e56
RM		 1551 complain_overflow_bitfield,/* complain_on_overflow */
1552 NULL, /* special_function */
1553 "R_ARM_TLS_GD32", /* name */
1554 TRUE, /* partial_inplace */
1555 0xffffffff, /* src_mask */
1556 0xffffffff, /* dst_mask */
07d6d2b8 1557 FALSE), /* pcrel_offset */
ba93b8ac 1558
ba93b8ac 1559 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1560 0, /* rightshift */
1561 2, /* size (0 = byte, 1 = short, 2 = long) */
1562 32, /* bitsize */
1563 FALSE, /* pc_relative */
1564 0, /* bitpos */
99059e56
RM		 1565 complain_overflow_bitfield,/* complain_on_overflow */
1566 bfd_elf_generic_reloc, /* special_function */
1567 "R_ARM_TLS_LDM32", /* name */
1568 TRUE, /* partial_inplace */
1569 0xffffffff, /* src_mask */
1570 0xffffffff, /* dst_mask */
07d6d2b8 1571 FALSE), /* pcrel_offset */
ba93b8ac 1572
c19d1205 1573 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1574 0, /* rightshift */
1575 2, /* size (0 = byte, 1 = short, 2 = long) */
1576 32, /* bitsize */
1577 FALSE, /* pc_relative */
1578 0, /* bitpos */
99059e56
RM		 1579 complain_overflow_bitfield,/* complain_on_overflow */
1580 bfd_elf_generic_reloc, /* special_function */
1581 "R_ARM_TLS_LDO32", /* name */
1582 TRUE, /* partial_inplace */
1583 0xffffffff, /* src_mask */
1584 0xffffffff, /* dst_mask */
07d6d2b8 1585 FALSE), /* pcrel_offset */
ba93b8ac 1586
ba93b8ac 1587 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1588 0, /* rightshift */
1589 2, /* size (0 = byte, 1 = short, 2 = long) */
1590 32, /* bitsize */
1591 FALSE, /* pc_relative */
1592 0, /* bitpos */
99059e56
RM		 1593 complain_overflow_bitfield,/* complain_on_overflow */
1594 NULL, /* special_function */
1595 "R_ARM_TLS_IE32", /* name */
1596 TRUE, /* partial_inplace */
1597 0xffffffff, /* src_mask */
1598 0xffffffff, /* dst_mask */
07d6d2b8 1599 FALSE), /* pcrel_offset */
7f266840 1600
c19d1205 1601 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1602 0, /* rightshift */
1603 2, /* size (0 = byte, 1 = short, 2 = long) */
1604 32, /* bitsize */
1605 FALSE, /* pc_relative */
1606 0, /* bitpos */
99059e56 1607 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1608 NULL, /* special_function */
99059e56
RM		 1609 "R_ARM_TLS_LE32", /* name */
1610 TRUE, /* partial_inplace */
1611 0xffffffff, /* src_mask */
1612 0xffffffff, /* dst_mask */
07d6d2b8 1613 FALSE), /* pcrel_offset */
7f266840 1614
c19d1205
ZW		 1615 HOWTO (R_ARM_TLS_LDO12, /* type */
1616 0, /* rightshift */
1617 2, /* size (0 = byte, 1 = short, 2 = long) */
1618 12, /* bitsize */
1619 FALSE, /* pc_relative */
7f266840 1620 0, /* bitpos */
c19d1205 1621 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1622 bfd_elf_generic_reloc, /* special_function */
c19d1205 1623 "R_ARM_TLS_LDO12", /* name */
7f266840 1624 FALSE, /* partial_inplace */
c19d1205
ZW		 1625 0x00000fff, /* src_mask */
1626 0x00000fff, /* dst_mask */
1627 FALSE), /* pcrel_offset */
7f266840 1628
c19d1205
ZW		 1629 HOWTO (R_ARM_TLS_LE12, /* type */
1630 0, /* rightshift */
1631 2, /* size (0 = byte, 1 = short, 2 = long) */
1632 12, /* bitsize */
1633 FALSE, /* pc_relative */
7f266840 1634 0, /* bitpos */
c19d1205 1635 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1636 bfd_elf_generic_reloc, /* special_function */
c19d1205 1637 "R_ARM_TLS_LE12", /* name */
7f266840 1638 FALSE, /* partial_inplace */
c19d1205
ZW		 1639 0x00000fff, /* src_mask */
1640 0x00000fff, /* dst_mask */
1641 FALSE), /* pcrel_offset */
7f266840 1642
c19d1205 1643 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1644 0, /* rightshift */
1645 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1646 12, /* bitsize */
1647 FALSE, /* pc_relative */
7f266840 1648 0, /* bitpos */
c19d1205 1649 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1650 bfd_elf_generic_reloc, /* special_function */
c19d1205 1651 "R_ARM_TLS_IE12GP", /* name */
7f266840 1652 FALSE, /* partial_inplace */
c19d1205
ZW		 1653 0x00000fff, /* src_mask */
1654 0x00000fff, /* dst_mask */
1655 FALSE), /* pcrel_offset */
0855e32b 1656
34e77a92 1657 /* 112-127 private relocations. */
0855e32b
NS		 1658 EMPTY_HOWTO (112),
1659 EMPTY_HOWTO (113),
1660 EMPTY_HOWTO (114),
1661 EMPTY_HOWTO (115),
1662 EMPTY_HOWTO (116),
1663 EMPTY_HOWTO (117),
1664 EMPTY_HOWTO (118),
1665 EMPTY_HOWTO (119),
1666 EMPTY_HOWTO (120),
1667 EMPTY_HOWTO (121),
1668 EMPTY_HOWTO (122),
1669 EMPTY_HOWTO (123),
1670 EMPTY_HOWTO (124),
1671 EMPTY_HOWTO (125),
1672 EMPTY_HOWTO (126),
1673 EMPTY_HOWTO (127),
34e77a92
RS		 1674
1675 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1676 EMPTY_HOWTO (128),
1677
1678 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1679 0, /* rightshift */
1680 1, /* size (0 = byte, 1 = short, 2 = long) */
1681 0, /* bitsize */
1682 FALSE, /* pc_relative */
1683 0, /* bitpos */
1684 complain_overflow_bitfield,/* complain_on_overflow */
1685 bfd_elf_generic_reloc, /* special_function */
1686 "R_ARM_THM_TLS_DESCSEQ",/* name */
1687 FALSE, /* partial_inplace */
1688 0x00000000, /* src_mask */
1689 0x00000000, /* dst_mask */
1690 FALSE), /* pcrel_offset */
72d98d16
MG		 1691 EMPTY_HOWTO (130),
1692 EMPTY_HOWTO (131),
1693 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1694 0, /* rightshift. */
1695 1, /* size (0 = byte, 1 = short, 2 = long). */
1696 16, /* bitsize. */
1697 FALSE, /* pc_relative. */
1698 0, /* bitpos. */
1699 complain_overflow_bitfield,/* complain_on_overflow. */
1700 bfd_elf_generic_reloc, /* special_function. */
1701 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1702 FALSE, /* partial_inplace. */
1703 0x00000000, /* src_mask. */
1704 0x00000000, /* dst_mask. */
1705 FALSE), /* pcrel_offset. */
1706 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1707 0, /* rightshift. */
1708 1, /* size (0 = byte, 1 = short, 2 = long). */
1709 16, /* bitsize. */
1710 FALSE, /* pc_relative. */
1711 0, /* bitpos. */
1712 complain_overflow_bitfield,/* complain_on_overflow. */
1713 bfd_elf_generic_reloc, /* special_function. */
1714 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1715 FALSE, /* partial_inplace. */
1716 0x00000000, /* src_mask. */
1717 0x00000000, /* dst_mask. */
1718 FALSE), /* pcrel_offset. */
1719 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1720 0, /* rightshift. */
1721 1, /* size (0 = byte, 1 = short, 2 = long). */
1722 16, /* bitsize. */
1723 FALSE, /* pc_relative. */
1724 0, /* bitpos. */
1725 complain_overflow_bitfield,/* complain_on_overflow. */
1726 bfd_elf_generic_reloc, /* special_function. */
1727 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1728 FALSE, /* partial_inplace. */
1729 0x00000000, /* src_mask. */
1730 0x00000000, /* dst_mask. */
1731 FALSE), /* pcrel_offset. */
1732 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1733 0, /* rightshift. */
1734 1, /* size (0 = byte, 1 = short, 2 = long). */
1735 16, /* bitsize. */
1736 FALSE, /* pc_relative. */
1737 0, /* bitpos. */
1738 complain_overflow_bitfield,/* complain_on_overflow. */
1739 bfd_elf_generic_reloc, /* special_function. */
1740 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1741 FALSE, /* partial_inplace. */
1742 0x00000000, /* src_mask. */
1743 0x00000000, /* dst_mask. */
1744 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1745};
1746
34e77a92 1747/* 160 onwards: */
5c5a4843 1748static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1749{
1750 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1751 0, /* rightshift */
1752 2, /* size (0 = byte, 1 = short, 2 = long) */
1753 32, /* bitsize */
1754 FALSE, /* pc_relative */
1755 0, /* bitpos */
99059e56
RM		 1756 complain_overflow_bitfield,/* complain_on_overflow */
1757 bfd_elf_generic_reloc, /* special_function */
1758 "R_ARM_IRELATIVE", /* name */
1759 TRUE, /* partial_inplace */
1760 0xffffffff, /* src_mask */
1761 0xffffffff, /* dst_mask */
188fd7ae
CL		 1762 FALSE), /* pcrel_offset */
1763 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1764 0, /* rightshift */
1765 2, /* size (0 = byte, 1 = short, 2 = long) */
1766 32, /* bitsize */
1767 FALSE, /* pc_relative */
1768 0, /* bitpos */
1769 complain_overflow_bitfield,/* complain_on_overflow */
1770 bfd_elf_generic_reloc, /* special_function */
1771 "R_ARM_GOTFUNCDESC", /* name */
1772 FALSE, /* partial_inplace */
1773 0, /* src_mask */
1774 0xffffffff, /* dst_mask */
1775 FALSE), /* pcrel_offset */
1776 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1777 0, /* rightshift */
1778 2, /* size (0 = byte, 1 = short, 2 = long) */
1779 32, /* bitsize */
1780 FALSE, /* pc_relative */
1781 0, /* bitpos */
1782 complain_overflow_bitfield,/* complain_on_overflow */
1783 bfd_elf_generic_reloc, /* special_function */
1784 "R_ARM_GOTOFFFUNCDESC",/* name */
1785 FALSE, /* partial_inplace */
1786 0, /* src_mask */
1787 0xffffffff, /* dst_mask */
1788 FALSE), /* pcrel_offset */
1789 HOWTO (R_ARM_FUNCDESC, /* type */
1790 0, /* rightshift */
1791 2, /* size (0 = byte, 1 = short, 2 = long) */
1792 32, /* bitsize */
1793 FALSE, /* pc_relative */
1794 0, /* bitpos */
1795 complain_overflow_bitfield,/* complain_on_overflow */
1796 bfd_elf_generic_reloc, /* special_function */
1797 "R_ARM_FUNCDESC", /* name */
1798 FALSE, /* partial_inplace */
1799 0, /* src_mask */
1800 0xffffffff, /* dst_mask */
1801 FALSE), /* pcrel_offset */
1802 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1803 0, /* rightshift */
1804 2, /* size (0 = byte, 1 = short, 2 = long) */
1805 64, /* bitsize */
1806 FALSE, /* pc_relative */
1807 0, /* bitpos */
1808 complain_overflow_bitfield,/* complain_on_overflow */
1809 bfd_elf_generic_reloc, /* special_function */
1810 "R_ARM_FUNCDESC_VALUE",/* name */
1811 FALSE, /* partial_inplace */
1812 0, /* src_mask */
1813 0xffffffff, /* dst_mask */
1814 FALSE), /* pcrel_offset */
5c5a4843
CL		 1815 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1816 0, /* rightshift */
1817 2, /* size (0 = byte, 1 = short, 2 = long) */
1818 32, /* bitsize */
1819 FALSE, /* pc_relative */
1820 0, /* bitpos */
1821 complain_overflow_bitfield,/* complain_on_overflow */
1822 bfd_elf_generic_reloc, /* special_function */
1823 "R_ARM_TLS_GD32_FDPIC",/* name */
1824 FALSE, /* partial_inplace */
1825 0, /* src_mask */
1826 0xffffffff, /* dst_mask */
1827 FALSE), /* pcrel_offset */
1828 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1829 0, /* rightshift */
1830 2, /* size (0 = byte, 1 = short, 2 = long) */
1831 32, /* bitsize */
1832 FALSE, /* pc_relative */
1833 0, /* bitpos */
1834 complain_overflow_bitfield,/* complain_on_overflow */
1835 bfd_elf_generic_reloc, /* special_function */
1836 "R_ARM_TLS_LDM32_FDPIC",/* name */
1837 FALSE, /* partial_inplace */
1838 0, /* src_mask */
1839 0xffffffff, /* dst_mask */
1840 FALSE), /* pcrel_offset */
1841 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1842 0, /* rightshift */
1843 2, /* size (0 = byte, 1 = short, 2 = long) */
1844 32, /* bitsize */
1845 FALSE, /* pc_relative */
1846 0, /* bitpos */
1847 complain_overflow_bitfield,/* complain_on_overflow */
1848 bfd_elf_generic_reloc, /* special_function */
1849 "R_ARM_TLS_IE32_FDPIC",/* name */
1850 FALSE, /* partial_inplace */
1851 0, /* src_mask */
1852 0xffffffff, /* dst_mask */
1853 FALSE), /* pcrel_offset */
34e77a92 1854};
c19d1205 1855
34e77a92
RS		 1856/* 249-255 extended, currently unused, relocations: */
1857static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1858{
1859 HOWTO (R_ARM_RREL32, /* type */
1860 0, /* rightshift */
1861 0, /* size (0 = byte, 1 = short, 2 = long) */
1862 0, /* bitsize */
1863 FALSE, /* pc_relative */
1864 0, /* bitpos */
1865 complain_overflow_dont,/* complain_on_overflow */
1866 bfd_elf_generic_reloc, /* special_function */
1867 "R_ARM_RREL32", /* name */
1868 FALSE, /* partial_inplace */
1869 0, /* src_mask */
1870 0, /* dst_mask */
1871 FALSE), /* pcrel_offset */
1872
1873 HOWTO (R_ARM_RABS32, /* type */
1874 0, /* rightshift */
1875 0, /* size (0 = byte, 1 = short, 2 = long) */
1876 0, /* bitsize */
1877 FALSE, /* pc_relative */
1878 0, /* bitpos */
1879 complain_overflow_dont,/* complain_on_overflow */
1880 bfd_elf_generic_reloc, /* special_function */
1881 "R_ARM_RABS32", /* name */
1882 FALSE, /* partial_inplace */
1883 0, /* src_mask */
1884 0, /* dst_mask */
1885 FALSE), /* pcrel_offset */
1886
1887 HOWTO (R_ARM_RPC24, /* type */
1888 0, /* rightshift */
1889 0, /* size (0 = byte, 1 = short, 2 = long) */
1890 0, /* bitsize */
1891 FALSE, /* pc_relative */
1892 0, /* bitpos */
1893 complain_overflow_dont,/* complain_on_overflow */
1894 bfd_elf_generic_reloc, /* special_function */
1895 "R_ARM_RPC24", /* name */
1896 FALSE, /* partial_inplace */
1897 0, /* src_mask */
1898 0, /* dst_mask */
1899 FALSE), /* pcrel_offset */
1900
1901 HOWTO (R_ARM_RBASE, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RBASE", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE) /* pcrel_offset */
1914};
1915
1916static reloc_howto_type *
1917elf32_arm_howto_from_type (unsigned int r_type)
1918{
906e58ca 1919 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1920 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1921
188fd7ae
CL		 1922 if (r_type >= R_ARM_IRELATIVE
1923 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1924 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1925
c19d1205 1926 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1927 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1928 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1929
c19d1205 1930 return NULL;
7f266840
DJ		 1931}
1932
f3185997
NC		 1933static bfd_boolean
1934elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1935 Elf_Internal_Rela * elf_reloc)
1936{
1937 unsigned int r_type;
1938
1939 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1940 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1941 {
1942 /* xgettext:c-format */
1943 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1944 abfd, r_type);
1945 bfd_set_error (bfd_error_bad_value);
1946 return FALSE;
1947 }
1948 return TRUE;
7f266840
DJ		 1949}
1950
1951struct elf32_arm_reloc_map
1952 {
1953 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1954 unsigned char elf_reloc_val;
7f266840
DJ		 1955 };
1956
1957/* All entries in this list must also be present in elf32_arm_howto_table. */
1958static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1959 {
07d6d2b8 1960 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 1961 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1962 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1963 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 1964 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1965 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1966 {BFD_RELOC_32, R_ARM_ABS32},
1967 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1968 {BFD_RELOC_8, R_ARM_ABS8},
1969 {BFD_RELOC_16, R_ARM_ABS16},
1970 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 1971 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1972 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1973 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1974 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1975 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1976 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1977 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 1978 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1979 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1980 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
1981 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
1982 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
1983 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
1984 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1985 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 1986 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1987 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1988 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1989 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 1990 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 1991 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1992 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1993 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 1994 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 1995 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 1996 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 1997 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1998 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1999 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2000 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2001 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2002 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2003 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2004 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2005 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2006 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2007 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2008 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2009 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2010 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2011 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2012 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2013 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2014 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2015 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2016 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2017 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2018 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2019 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2020 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2021 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2022 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2023 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2024 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2025 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2026 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2027 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2028 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2029 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2030 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2031 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2032 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2033 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2034 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2035 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2036 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2037 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2038 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2039 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2040 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2041 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2042 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2043 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2044 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2045 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2046 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2047 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2048 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2049 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2050 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2051 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2052 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2053 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2054 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2055 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
2056 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 2057 };
2058
2059static reloc_howto_type *
f1c71a59
ZW		 2060elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2061 bfd_reloc_code_real_type code)
7f266840
DJ		 2062{
2063 unsigned int i;
8029a119 2064
906e58ca 2065 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2066 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2067 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2068
c19d1205 2069 return NULL;
7f266840
DJ		 2070}
2071
157090f7
AM		 2072static reloc_howto_type *
2073elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2074 const char *r_name)
2075{
2076 unsigned int i;
2077
906e58ca 2078 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2079 if (elf32_arm_howto_table_1[i].name != NULL
2080 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2081 return &elf32_arm_howto_table_1[i];
2082
906e58ca 2083 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2084 if (elf32_arm_howto_table_2[i].name != NULL
2085 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2086 return &elf32_arm_howto_table_2[i];
2087
34e77a92
RS		 2088 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2089 if (elf32_arm_howto_table_3[i].name != NULL
2090 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2091 return &elf32_arm_howto_table_3[i];
2092
157090f7
AM		 2093 return NULL;
2094}
2095
906e58ca
NC		 2096/* Support for core dump NOTE sections. */
2097
7f266840 2098static bfd_boolean
f1c71a59 2099elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2100{
2101 int offset;
2102 size_t size;
2103
2104 switch (note->descsz)
2105 {
2106 default:
2107 return FALSE;
2108
8029a119 2109 case 148: /* Linux/ARM 32-bit. */
7f266840 2110 /* pr_cursig */
228e534f 2111 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2112
2113 /* pr_pid */
228e534f 2114 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2115
2116 /* pr_reg */
2117 offset = 72;
2118 size = 72;
2119
2120 break;
2121 }
2122
2123 /* Make a ".reg/999" section. */
2124 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2125 size, note->descpos + offset);
2126}
2127
2128static bfd_boolean
f1c71a59 2129elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2130{
2131 switch (note->descsz)
2132 {
2133 default:
2134 return FALSE;
2135
8029a119 2136 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2137 elf_tdata (abfd)->core->pid
4395ee08 2138 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2139 elf_tdata (abfd)->core->program
7f266840 2140 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2141 elf_tdata (abfd)->core->command
7f266840
DJ		 2142 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2143 }
2144
2145 /* Note that for some reason, a spurious space is tacked
2146 onto the end of the args in some (at least one anyway)
2147 implementations, so strip it off if it exists. */
7f266840 2148 {
228e534f 2149 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2150 int n = strlen (command);
2151
2152 if (0 < n && command[n - 1] == ' ')
2153 command[n - 1] = '\0';
2154 }
2155
2156 return TRUE;
2157}
2158
1f20dca5
UW		 2159static char *
2160elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2161 int note_type, ...)
2162{
2163 switch (note_type)
2164 {
2165 default:
2166 return NULL;
2167
2168 case NT_PRPSINFO:
2169 {
602f1657 2170 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2171 va_list ap;
2172
2173 va_start (ap, note_type);
2174 memset (data, 0, sizeof (data));
2175 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2176#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2177 DIAGNOSTIC_PUSH;
be3e27bb 2178 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2179 -Wstringop-truncation:
2180 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2181 */
95da9854
L		 2182 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2183#endif
1f20dca5 2184 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2185#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2186 DIAGNOSTIC_POP;
fe75810f 2187#endif
1f20dca5
UW		 2188 va_end (ap);
2189
2190 return elfcore_write_note (abfd, buf, bufsiz,
2191 "CORE", note_type, data, sizeof (data));
2192 }
2193
2194 case NT_PRSTATUS:
2195 {
2196 char data[148];
2197 va_list ap;
2198 long pid;
2199 int cursig;
2200 const void *greg;
2201
2202 va_start (ap, note_type);
2203 memset (data, 0, sizeof (data));
2204 pid = va_arg (ap, long);
2205 bfd_put_32 (abfd, pid, data + 24);
2206 cursig = va_arg (ap, int);
2207 bfd_put_16 (abfd, cursig, data + 12);
2208 greg = va_arg (ap, const void *);
2209 memcpy (data + 72, greg, 72);
2210 va_end (ap);
2211
2212 return elfcore_write_note (abfd, buf, bufsiz,
2213 "CORE", note_type, data, sizeof (data));
2214 }
2215 }
2216}
2217
07d6d2b8
AM		 2218#define TARGET_LITTLE_SYM arm_elf32_le_vec
2219#define TARGET_LITTLE_NAME "elf32-littlearm"
2220#define TARGET_BIG_SYM arm_elf32_be_vec
2221#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2222
2223#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2224#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2225#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2226
252b5132
RH		 2227typedef unsigned long int insn32;
2228typedef unsigned short int insn16;
2229
3a4a14e9
PB		 2230/* In lieu of proper flags, assume all EABIv4 or later objects are
2231 interworkable. */
57e8b36a 2232#define INTERWORK_FLAG(abfd) \
3a4a14e9 2233 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2234 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2235 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2236
252b5132
RH		 2237/* The linker script knows the section names for placement.
2238 The entry_names are used to do simple name mangling on the stubs.
2239 Given a function name, and its type, the stub can be found. The
9b485d32 2240 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2241#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2242#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2243
2244#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2245#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2246
c7b8f16e
JB		 2247#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2248#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2249
a504d23a
LA		 2250#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2251#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2252
845b51d6
PB		 2253#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2254#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2255
7413f23f
DJ		 2256#define STUB_ENTRY_NAME "__%s_veneer"
2257
4ba2ef8f
TP		 2258#define CMSE_PREFIX "__acle_se_"
2259
252b5132
RH		 2260/* The name of the dynamic interpreter. This is put in the .interp
2261 section. */
2262#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2263
cb10292c
CL		 2264/* FDPIC default stack size. */
2265#define DEFAULT_STACK_SIZE 0x8000
2266
0855e32b 2267static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2268{
2269 0xe08e0000, /* add r0, lr, r0 */
2270 0xe5901004, /* ldr r1, [r0,#4] */
2271 0xe12fff11, /* bx r1 */
2272};
0855e32b
NS		 2273
2274static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2275{
2276 0xe52d2004, /* push {r2} */
2277 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2278 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2279 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2280 0xe081100f, /* 2: add r1, pc */
2281 0xe12fff12, /* bx r2 */
2282 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2283 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2284 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2285};
0855e32b 2286
7801f98f
CL		 2287/* ARM FDPIC PLT entry. */
2288/* The last 5 words contain PLT lazy fragment code and data. */
2289static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2290 {
2291 0xe59fc008, /* ldr r12, .L1 */
2292 0xe08cc009, /* add r12, r12, r9 */
2293 0xe59c9004, /* ldr r9, [r12, #4] */
2294 0xe59cf000, /* ldr pc, [r12] */
2295 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2296 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2297 0xe51fc00c, /* ldr r12, [pc, #-12] */
2298 0xe92d1000, /* push {r12} */
2299 0xe599c004, /* ldr r12, [r9, #4] */
2300 0xe599f000, /* ldr pc, [r9] */
2301 };
2302
59029f57
CL		 2303/* Thumb FDPIC PLT entry. */
2304/* The last 5 words contain PLT lazy fragment code and data. */
2305static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2306 {
2307 0xc00cf8df, /* ldr.w r12, .L1 */
2308 0x0c09eb0c, /* add.w r12, r12, r9 */
2309 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2310 0xf000f8dc, /* ldr.w pc, [r12] */
2311 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2312 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2313 0xc008f85f, /* ldr.w r12, .L2 */
2314 0xcd04f84d, /* push {r12} */
2315 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2316 0xf000f8d9, /* ldr.w pc, [r9] */
2317 };
2318
5e681ec4
PB		 2319#ifdef FOUR_WORD_PLT
2320
252b5132
RH		 2321/* The first entry in a procedure linkage table looks like
2322 this. It is set up so that any shared library function that is
59f2c4e7 2323 called before the relocation has been set up calls the dynamic
9b485d32 2324 linker first. */
e5a52504 2325static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2326{
2327 0xe52de004, /* str lr, [sp, #-4]! */
2328 0xe59fe010, /* ldr lr, [pc, #16] */
2329 0xe08fe00e, /* add lr, pc, lr */
2330 0xe5bef008, /* ldr pc, [lr, #8]! */
2331};
5e681ec4
PB		 2332
2333/* Subsequent entries in a procedure linkage table look like
2334 this. */
e5a52504 2335static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2336{
2337 0xe28fc600, /* add ip, pc, #NN */
2338 0xe28cca00, /* add ip, ip, #NN */
2339 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2340 0x00000000, /* unused */
2341};
5e681ec4 2342
eed94f8f 2343#else /* not FOUR_WORD_PLT */
5e681ec4 2344
5e681ec4
PB		 2345/* The first entry in a procedure linkage table looks like
2346 this. It is set up so that any shared library function that is
2347 called before the relocation has been set up calls the dynamic
2348 linker first. */
e5a52504 2349static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2350{
07d6d2b8
AM		 2351 0xe52de004, /* str lr, [sp, #-4]! */
2352 0xe59fe004, /* ldr lr, [pc, #4] */
2353 0xe08fe00e, /* add lr, pc, lr */
2354 0xe5bef008, /* ldr pc, [lr, #8]! */
2355 0x00000000, /* &GOT[0] - . */
b38cadfb 2356};
252b5132 2357
1db37fe6
YG		 2358/* By default subsequent entries in a procedure linkage table look like
2359 this. Offsets that don't fit into 28 bits will cause link error. */
2360static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2361{
2362 0xe28fc600, /* add ip, pc, #0xNN00000 */
2363 0xe28cca00, /* add ip, ip, #0xNN000 */
2364 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2365};
5e681ec4 2366
1db37fe6
YG		 2367/* When explicitly asked, we'll use this "long" entry format
2368 which can cope with arbitrary displacements. */
2369static const bfd_vma elf32_arm_plt_entry_long [] =
2370{
07d6d2b8
AM		 2371 0xe28fc200, /* add ip, pc, #0xN0000000 */
2372 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2373 0xe28cca00, /* add ip, ip, #0xNN000 */
2374 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2375};
2376
2377static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2378
eed94f8f
NC		 2379#endif /* not FOUR_WORD_PLT */
2380
2381/* The first entry in a procedure linkage table looks like this.
2382 It is set up so that any shared library function that is called before the
2383 relocation has been set up calls the dynamic linker first. */
2384static const bfd_vma elf32_thumb2_plt0_entry [] =
2385{
2386 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2387 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2388 0xf8dfb500, /* push {lr} */
2389 0x44fee008, /* ldr.w lr, [pc, #8] */
2390 /* add lr, pc */
eed94f8f 2391 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2392 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2393};
2394
2395/* Subsequent entries in a procedure linkage table for thumb only target
2396 look like this. */
2397static const bfd_vma elf32_thumb2_plt_entry [] =
2398{
2399 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2400 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2401 0x0c00f240, /* movw ip, #0xNNNN */
2402 0x0c00f2c0, /* movt ip, #0xNNNN */
2403 0xf8dc44fc, /* add ip, pc */
2404 0xbf00f000 /* ldr.w pc, [ip] */
2405 /* nop */
eed94f8f 2406};
252b5132 2407
00a97672
RS		 2408/* The format of the first entry in the procedure linkage table
2409 for a VxWorks executable. */
2410static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2411{
07d6d2b8
AM		 2412 0xe52dc008, /* str ip,[sp,#-8]! */
2413 0xe59fc000, /* ldr ip,[pc] */
2414 0xe59cf008, /* ldr pc,[ip,#8] */
2415 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2416};
00a97672
RS		 2417
2418/* The format of subsequent entries in a VxWorks executable. */
2419static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2420{
07d6d2b8
AM		 2421 0xe59fc000, /* ldr ip,[pc] */
2422 0xe59cf000, /* ldr pc,[ip] */
2423 0x00000000, /* .long @got */
2424 0xe59fc000, /* ldr ip,[pc] */
2425 0xea000000, /* b _PLT */
2426 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2427};
00a97672
RS		 2428
2429/* The format of entries in a VxWorks shared library. */
2430static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2431{
07d6d2b8
AM		 2432 0xe59fc000, /* ldr ip,[pc] */
2433 0xe79cf009, /* ldr pc,[ip,r9] */
2434 0x00000000, /* .long @got */
2435 0xe59fc000, /* ldr ip,[pc] */
2436 0xe599f008, /* ldr pc,[r9,#8] */
2437 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2438};
00a97672 2439
b7693d02
DJ		 2440/* An initial stub used if the PLT entry is referenced from Thumb code. */
2441#define PLT_THUMB_STUB_SIZE 4
2442static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2443{
2444 0x4778, /* bx pc */
2445 0x46c0 /* nop */
2446};
b7693d02 2447
e5a52504
MM		 2448/* The entries in a PLT when using a DLL-based target with multiple
2449 address spaces. */
906e58ca 2450static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2451{
07d6d2b8
AM		 2452 0xe51ff004, /* ldr pc, [pc, #-4] */
2453 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2454};
2455
2456/* The first entry in a procedure linkage table looks like
2457 this. It is set up so that any shared library function that is
2458 called before the relocation has been set up calls the dynamic
2459 linker first. */
2460static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2461{
2462 /* First bundle: */
2463 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2464 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2465 0xe08cc00f, /* add ip, ip, pc */
2466 0xe52dc008, /* str ip, [sp, #-8]! */
2467 /* Second bundle: */
edccdf7c
RM		 2468 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2469 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2470 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2471 0xe12fff1c, /* bx ip */
b38cadfb 2472 /* Third bundle: */
edccdf7c
RM		 2473 0xe320f000, /* nop */
2474 0xe320f000, /* nop */
2475 0xe320f000, /* nop */
b38cadfb
NC		 2476 /* .Lplt_tail: */
2477 0xe50dc004, /* str ip, [sp, #-4] */
2478 /* Fourth bundle: */
edccdf7c
RM		 2479 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2480 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2481 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2482 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2483};
2484#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2485
2486/* Subsequent entries in a procedure linkage table look like this. */
2487static const bfd_vma elf32_arm_nacl_plt_entry [] =
2488{
2489 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2490 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2491 0xe08cc00f, /* add ip, ip, pc */
2492 0xea000000, /* b .Lplt_tail */
2493};
e5a52504 2494
906e58ca
NC		 2495#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2496#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2497#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2498#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2499#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2500#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2501#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2502#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2503
461a49ca 2504enum stub_insn_type
b38cadfb
NC		 2505{
2506 THUMB16_TYPE = 1,
2507 THUMB32_TYPE,
2508 ARM_TYPE,
2509 DATA_TYPE
2510};
461a49ca 2511
48229727
JB		 2512#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2513/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2514 is inserted in arm_build_one_stub(). */
2515#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2516#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2517#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2518#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2519#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2520#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2521#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2522#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2523
2524typedef struct
2525{
07d6d2b8 2526 bfd_vma data;
b38cadfb 2527 enum stub_insn_type type;
07d6d2b8
AM		 2528 unsigned int r_type;
2529 int reloc_addend;
461a49ca
DJ		 2530} insn_sequence;
2531
fea2b4d6
CL		 2532/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2533 to reach the stub if necessary. */
461a49ca 2534static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2535{
07d6d2b8 2536 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2537 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2538};
906e58ca 2539
fea2b4d6
CL		 2540/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2541 available. */
461a49ca 2542static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2543{
07d6d2b8
AM		 2544 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2546 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2547};
906e58ca 2548
d3626fb0 2549/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2550static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2551{
07d6d2b8
AM		 2552 THUMB16_INSN (0xb401), /* push {r0} */
2553 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2554 THUMB16_INSN (0x4684), /* mov ip, r0 */
2555 THUMB16_INSN (0xbc01), /* pop {r0} */
2556 THUMB16_INSN (0x4760), /* bx ip */
2557 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2558 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2559};
906e58ca 2560
80c135e5
TP		 2561/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2562static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2563{
07d6d2b8 2564 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2565 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2566};
2567
d5a67c02
AV		 2568/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2569 M-profile architectures. */
2570static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2571{
2572 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2573 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2574 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2575};
2576
d3626fb0
CL		 2577/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2578 allowed. */
2579static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2580{
07d6d2b8
AM		 2581 THUMB16_INSN (0x4778), /* bx pc */
2582 THUMB16_INSN (0x46c0), /* nop */
2583 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2584 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2585 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2586};
d3626fb0 2587
fea2b4d6
CL		 2588/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2589 available. */
461a49ca 2590static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2591{
07d6d2b8
AM		 2592 THUMB16_INSN (0x4778), /* bx pc */
2593 THUMB16_INSN (0x46c0), /* nop */
2594 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2595 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2596};
906e58ca 2597
fea2b4d6
CL		 2598/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2599 one, when the destination is close enough. */
461a49ca 2600static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2601{
07d6d2b8
AM		 2602 THUMB16_INSN (0x4778), /* bx pc */
2603 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2604 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2605};
c820be07 2606
cf3eccff 2607/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2608 blx to reach the stub if necessary. */
cf3eccff 2609static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2610{
07d6d2b8
AM		 2611 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2612 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2613 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2614};
906e58ca 2615
cf3eccff
DJ		 2616/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2617 blx to reach the stub if necessary. We can not add into pc;
2618 it is not guaranteed to mode switch (different in ARMv6 and
2619 ARMv7). */
2620static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2621{
07d6d2b8
AM		 2622 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2623 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2624 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2625 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2626};
cf3eccff 2627
ebe24dd4
CL		 2628/* V4T ARM -> ARM long branch stub, PIC. */
2629static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2630{
07d6d2b8
AM		 2631 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2632 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2633 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2634 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2635};
ebe24dd4
CL		 2636
2637/* V4T Thumb -> ARM long branch stub, PIC. */
2638static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2639{
07d6d2b8
AM		 2640 THUMB16_INSN (0x4778), /* bx pc */
2641 THUMB16_INSN (0x46c0), /* nop */
2642 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2643 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2644 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2645};
ebe24dd4 2646
d3626fb0
CL		 2647/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2648 architectures. */
ebe24dd4 2649static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2650{
07d6d2b8
AM		 2651 THUMB16_INSN (0xb401), /* push {r0} */
2652 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2653 THUMB16_INSN (0x46fc), /* mov ip, pc */
2654 THUMB16_INSN (0x4484), /* add ip, r0 */
2655 THUMB16_INSN (0xbc01), /* pop {r0} */
2656 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2657 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2658};
ebe24dd4 2659
d3626fb0
CL		 2660/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2661 allowed. */
2662static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2663{
07d6d2b8
AM		 2664 THUMB16_INSN (0x4778), /* bx pc */
2665 THUMB16_INSN (0x46c0), /* nop */
2666 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2667 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2668 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2669 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2670};
d3626fb0 2671
0855e32b
NS		 2672/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2673 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2674static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2677 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2678 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2679};
2680
2681/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2682 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2684{
07d6d2b8
AM		 2685 THUMB16_INSN (0x4778), /* bx pc */
2686 THUMB16_INSN (0x46c0), /* nop */
2687 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2688 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2689 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2690};
2691
7a89b94e
NC		 2692/* NaCl ARM -> ARM long branch stub. */
2693static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2694{
2695 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2696 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2697 ARM_INSN (0xe12fff1c), /* bx ip */
2698 ARM_INSN (0xe320f000), /* nop */
2699 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2700 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2701 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2702 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2703};
2704
2705/* NaCl ARM -> ARM long branch stub, PIC. */
2706static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2707{
2708 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2709 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2710 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2711 ARM_INSN (0xe12fff1c), /* bx ip */
2712 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2713 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2714 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2715 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2716};
2717
4ba2ef8f
TP		 2718/* Stub used for transition to secure state (aka SG veneer). */
2719static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2720{
2721 THUMB32_INSN (0xe97fe97f), /* sg. */
2722 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2723};
2724
7a89b94e 2725
48229727
JB		 2726/* Cortex-A8 erratum-workaround stubs. */
2727
2728/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2729 can't use a conditional branch to reach this stub). */
2730
2731static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2732{
07d6d2b8 2733 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2734 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2735 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2736};
48229727
JB		 2737
2738/* Stub used for b.w and bl.w instructions. */
2739
2740static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2741{
2742 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2743};
48229727
JB		 2744
2745static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2746{
2747 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2748};
48229727
JB		 2749
2750/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2751 instruction (which switches to ARM mode) to point to this stub. Jump to the
2752 real destination using an ARM-mode branch. */
2753
2754static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2755{
2756 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2757};
48229727 2758
9553db3c
NC		 2759/* For each section group there can be a specially created linker section
2760 to hold the stubs for that group. The name of the stub section is based
2761 upon the name of another section within that group with the suffix below
2762 applied.
2763
2764 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2765 create what appeared to be a linker stub section when it actually
2766 contained user code/data. For example, consider this fragment:
b38cadfb 2767
9553db3c
NC		 2768 const char * stubborn_problems[] = { "np" };
2769
2770 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2771 section called:
2772
2773 .data.rel.local.stubborn_problems
2774
2775 This then causes problems in arm32_arm_build_stubs() as it triggers:
2776
2777 // Ignore non-stub sections.
2778 if (!strstr (stub_sec->name, STUB_SUFFIX))
2779 continue;
2780
2781 And so the section would be ignored instead of being processed. Hence
2782 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2783 C identifier. */
2784#define STUB_SUFFIX ".__stub"
906e58ca 2785
738a79f6
CL		 2786/* One entry per long/short branch stub defined above. */
2787#define DEF_STUBS \
2788 DEF_STUB(long_branch_any_any) \
2789 DEF_STUB(long_branch_v4t_arm_thumb) \
2790 DEF_STUB(long_branch_thumb_only) \
2791 DEF_STUB(long_branch_v4t_thumb_thumb) \
2792 DEF_STUB(long_branch_v4t_thumb_arm) \
2793 DEF_STUB(short_branch_v4t_thumb_arm) \
2794 DEF_STUB(long_branch_any_arm_pic) \
2795 DEF_STUB(long_branch_any_thumb_pic) \
2796 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2797 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2798 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2799 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2800 DEF_STUB(long_branch_any_tls_pic) \
2801 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2802 DEF_STUB(long_branch_arm_nacl) \
2803 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2804 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2805 DEF_STUB(a8_veneer_b_cond) \
2806 DEF_STUB(a8_veneer_b) \
2807 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2808 DEF_STUB(a8_veneer_blx) \
2809 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2810 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2811
2812#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2813enum elf32_arm_stub_type
2814{
906e58ca 2815 arm_stub_none,
738a79f6 2816 DEF_STUBS
4f4faa4d 2817 max_stub_type
738a79f6
CL		 2818};
2819#undef DEF_STUB
2820
8d9d9490
TP		 2821/* Note the first a8_veneer type. */
2822const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2823
738a79f6
CL		 2824typedef struct
2825{
d3ce72d0 2826 const insn_sequence* template_sequence;
738a79f6
CL		 2827 int template_size;
2828} stub_def;
2829
2830#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2831static const stub_def stub_definitions[] =
2832{
738a79f6
CL		 2833 {NULL, 0},
2834 DEF_STUBS
906e58ca
NC		 2835};
2836
2837struct elf32_arm_stub_hash_entry
2838{
2839 /* Base hash table entry structure. */
2840 struct bfd_hash_entry root;
2841
2842 /* The stub section. */
2843 asection *stub_sec;
2844
2845 /* Offset within stub_sec of the beginning of this stub. */
2846 bfd_vma stub_offset;
2847
2848 /* Given the symbol's value and its section we can determine its final
2849 value when building the stubs (so the stub knows where to jump). */
2850 bfd_vma target_value;
2851 asection *target_section;
2852
8d9d9490
TP		 2853 /* Same as above but for the source of the branch to the stub. Used for
2854 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2855 such, source section does not need to be recorded since Cortex-A8 erratum
2856 workaround stubs are only generated when both source and target are in the
2857 same section. */
2858 bfd_vma source_value;
48229727
JB		 2859
2860 /* The instruction which caused this stub to be generated (only valid for
2861 Cortex-A8 erratum workaround stubs at present). */
2862 unsigned long orig_insn;
2863
461a49ca 2864 /* The stub type. */
906e58ca 2865 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2866 /* Its encoding size in bytes. */
2867 int stub_size;
2868 /* Its template. */
2869 const insn_sequence *stub_template;
2870 /* The size of the template (number of entries). */
2871 int stub_template_size;
906e58ca
NC		 2872
2873 /* The symbol table entry, if any, that this was derived from. */
2874 struct elf32_arm_link_hash_entry *h;
2875
35fc36a8
RS		 2876 /* Type of branch. */
2877 enum arm_st_branch_type branch_type;
906e58ca
NC		 2878
2879 /* Where this stub is being called from, or, in the case of combined
2880 stub sections, the first input section in the group. */
2881 asection *id_sec;
7413f23f
DJ		 2882
2883 /* The name for the local symbol at the start of this stub. The
2884 stub name in the hash table has to be unique; this does not, so
2885 it can be friendlier. */
2886 char *output_name;
906e58ca
NC		 2887};
2888
e489d0ae
PB		 2889/* Used to build a map of a section. This is required for mixed-endian
2890 code/data. */
2891
2892typedef struct elf32_elf_section_map
2893{
2894 bfd_vma vma;
2895 char type;
2896}
2897elf32_arm_section_map;
2898
c7b8f16e
JB		 2899/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2900
2901typedef enum
2902{
2903 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2904 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2905 VFP11_ERRATUM_ARM_VENEER,
2906 VFP11_ERRATUM_THUMB_VENEER
2907}
2908elf32_vfp11_erratum_type;
2909
2910typedef struct elf32_vfp11_erratum_list
2911{
2912 struct elf32_vfp11_erratum_list *next;
2913 bfd_vma vma;
2914 union
2915 {
2916 struct
2917 {
2918 struct elf32_vfp11_erratum_list *veneer;
2919 unsigned int vfp_insn;
2920 } b;
2921 struct
2922 {
2923 struct elf32_vfp11_erratum_list *branch;
2924 unsigned int id;
2925 } v;
2926 } u;
2927 elf32_vfp11_erratum_type type;
2928}
2929elf32_vfp11_erratum_list;
2930
a504d23a
LA		 2931/* Information about a STM32L4XX erratum veneer, or a branch to such a
2932 veneer. */
2933typedef enum
2934{
2935 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2936 STM32L4XX_ERRATUM_VENEER
2937}
2938elf32_stm32l4xx_erratum_type;
2939
2940typedef struct elf32_stm32l4xx_erratum_list
2941{
2942 struct elf32_stm32l4xx_erratum_list *next;
2943 bfd_vma vma;
2944 union
2945 {
2946 struct
2947 {
2948 struct elf32_stm32l4xx_erratum_list *veneer;
2949 unsigned int insn;
2950 } b;
2951 struct
2952 {
2953 struct elf32_stm32l4xx_erratum_list *branch;
2954 unsigned int id;
2955 } v;
2956 } u;
2957 elf32_stm32l4xx_erratum_type type;
2958}
2959elf32_stm32l4xx_erratum_list;
2960
2468f9c9
PB		 2961typedef enum
2962{
2963 DELETE_EXIDX_ENTRY,
2964 INSERT_EXIDX_CANTUNWIND_AT_END
2965}
2966arm_unwind_edit_type;
2967
2968/* A (sorted) list of edits to apply to an unwind table. */
2969typedef struct arm_unwind_table_edit
2970{
2971 arm_unwind_edit_type type;
2972 /* Note: we sometimes want to insert an unwind entry corresponding to a
2973 section different from the one we're currently writing out, so record the
2974 (text) section this edit relates to here. */
2975 asection *linked_section;
2976 unsigned int index;
2977 struct arm_unwind_table_edit *next;
2978}
2979arm_unwind_table_edit;
2980
8e3de13a 2981typedef struct _arm_elf_section_data
e489d0ae 2982{
2468f9c9 2983 /* Information about mapping symbols. */
e489d0ae 2984 struct bfd_elf_section_data elf;
8e3de13a 2985 unsigned int mapcount;
c7b8f16e 2986 unsigned int mapsize;
e489d0ae 2987 elf32_arm_section_map *map;
2468f9c9 2988 /* Information about CPU errata. */
c7b8f16e
JB		 2989 unsigned int erratumcount;
2990 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2991 unsigned int stm32l4xx_erratumcount;
2992 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2993 unsigned int additional_reloc_count;
2468f9c9
PB		 2994 /* Information about unwind tables. */
2995 union
2996 {
2997 /* Unwind info attached to a text section. */
2998 struct
2999 {
3000 asection *arm_exidx_sec;
3001 } text;
3002
3003 /* Unwind info attached to an .ARM.exidx section. */
3004 struct
3005 {
3006 arm_unwind_table_edit *unwind_edit_list;
3007 arm_unwind_table_edit *unwind_edit_tail;
3008 } exidx;
3009 } u;
8e3de13a
NC		 3010}
3011_arm_elf_section_data;
e489d0ae
PB		 3012
3013#define elf32_arm_section_data(sec) \
8e3de13a 3014 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3015
48229727
JB		 3016/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3017 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3018 so may be created multiple times: we use an array of these entries whilst
3019 relaxing which we can refresh easily, then create stubs for each potentially
3020 erratum-triggering instruction once we've settled on a solution. */
3021
b38cadfb
NC		 3022struct a8_erratum_fix
3023{
48229727
JB		 3024 bfd *input_bfd;
3025 asection *section;
3026 bfd_vma offset;
8d9d9490 3027 bfd_vma target_offset;
48229727
JB		 3028 unsigned long orig_insn;
3029 char *stub_name;
3030 enum elf32_arm_stub_type stub_type;
35fc36a8 3031 enum arm_st_branch_type branch_type;
48229727
JB		 3032};
3033
3034/* A table of relocs applied to branches which might trigger Cortex-A8
3035 erratum. */
3036
b38cadfb
NC		 3037struct a8_erratum_reloc
3038{
48229727
JB		 3039 bfd_vma from;
3040 bfd_vma destination;
92750f34
DJ		 3041 struct elf32_arm_link_hash_entry *hash;
3042 const char *sym_name;
48229727 3043 unsigned int r_type;
35fc36a8 3044 enum arm_st_branch_type branch_type;
48229727
JB		 3045 bfd_boolean non_a8_stub;
3046};
3047
ba93b8ac
DJ		 3048/* The size of the thread control block. */
3049#define TCB_SIZE 8
3050
34e77a92
RS		 3051/* ARM-specific information about a PLT entry, over and above the usual
3052 gotplt_union. */
b38cadfb
NC		 3053struct arm_plt_info
3054{
34e77a92
RS		 3055 /* We reference count Thumb references to a PLT entry separately,
3056 so that we can emit the Thumb trampoline only if needed. */
3057 bfd_signed_vma thumb_refcount;
3058
3059 /* Some references from Thumb code may be eliminated by BL->BLX
3060 conversion, so record them separately. */
3061 bfd_signed_vma maybe_thumb_refcount;
3062
3063 /* How many of the recorded PLT accesses were from non-call relocations.
3064 This information is useful when deciding whether anything takes the
3065 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3066 non-call references to the function should resolve directly to the
3067 real runtime target. */
3068 unsigned int noncall_refcount;
3069
3070 /* Since PLT entries have variable size if the Thumb prologue is
3071 used, we need to record the index into .got.plt instead of
3072 recomputing it from the PLT offset. */
3073 bfd_signed_vma got_offset;
3074};
3075
3076/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3077struct arm_local_iplt_info
3078{
34e77a92
RS		 3079 /* The information that is usually found in the generic ELF part of
3080 the hash table entry. */
3081 union gotplt_union root;
3082
3083 /* The information that is usually found in the ARM-specific part of
3084 the hash table entry. */
3085 struct arm_plt_info arm;
3086
3087 /* A list of all potential dynamic relocations against this symbol. */
3088 struct elf_dyn_relocs *dyn_relocs;
3089};
3090
e8b09b87
CL		 3091/* Structure to handle FDPIC support for local functions. */
3092struct fdpic_local {
3093 unsigned int funcdesc_cnt;
3094 unsigned int gotofffuncdesc_cnt;
3095 int funcdesc_offset;
3096};
3097
0ffa91dd 3098struct elf_arm_obj_tdata
ba93b8ac
DJ		 3099{
3100 struct elf_obj_tdata root;
3101
3102 /* tls_type for each local got entry. */
3103 char *local_got_tls_type;
ee065d83 3104
0855e32b
NS		 3105 /* GOTPLT entries for TLS descriptors. */
3106 bfd_vma *local_tlsdesc_gotent;
3107
34e77a92
RS		 3108 /* Information for local symbols that need entries in .iplt. */
3109 struct arm_local_iplt_info **local_iplt;
3110
bf21ed78
MS		 3111 /* Zero to warn when linking objects with incompatible enum sizes. */
3112 int no_enum_size_warning;
a9dc9481
JM		 3113
3114 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3115 int no_wchar_size_warning;
e8b09b87
CL		 3116
3117 /* Maintains FDPIC counters and funcdesc info. */
3118 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3119};
3120
0ffa91dd
NC		 3121#define elf_arm_tdata(bfd) \
3122 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3123
0ffa91dd
NC		 3124#define elf32_arm_local_got_tls_type(bfd) \
3125 (elf_arm_tdata (bfd)->local_got_tls_type)
3126
0855e32b
NS		 3127#define elf32_arm_local_tlsdesc_gotent(bfd) \
3128 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3129
34e77a92
RS		 3130#define elf32_arm_local_iplt(bfd) \
3131 (elf_arm_tdata (bfd)->local_iplt)
3132
e8b09b87
CL		 3133#define elf32_arm_local_fdpic_cnts(bfd) \
3134 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3135
0ffa91dd
NC		 3136#define is_arm_elf(bfd) \
3137 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3138 && elf_tdata (bfd) != NULL \
4dfe6ac6 3139 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3140
3141static bfd_boolean
3142elf32_arm_mkobject (bfd *abfd)
3143{
0ffa91dd 3144 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3145 ARM_ELF_DATA);
ba93b8ac
DJ		 3146}
3147
ba93b8ac
DJ		 3148#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3149
e8b09b87
CL		 3150/* Structure to handle FDPIC support for extern functions. */
3151struct fdpic_global {
3152 unsigned int gotofffuncdesc_cnt;
3153 unsigned int gotfuncdesc_cnt;
3154 unsigned int funcdesc_cnt;
3155 int funcdesc_offset;
3156 int gotfuncdesc_offset;
3157};
3158
ba96a88f 3159/* Arm ELF linker hash entry. */
252b5132 3160struct elf32_arm_link_hash_entry
b38cadfb
NC		 3161{
3162 struct elf_link_hash_entry root;
252b5132 3163
b38cadfb
NC		 3164 /* Track dynamic relocs copied for this symbol. */
3165 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3166
b38cadfb
NC		 3167 /* ARM-specific PLT information. */
3168 struct arm_plt_info plt;
ba93b8ac
DJ		 3169
3170#define GOT_UNKNOWN 0
3171#define GOT_NORMAL 1
3172#define GOT_TLS_GD 2
3173#define GOT_TLS_IE 4
0855e32b
NS		 3174#define GOT_TLS_GDESC 8
3175#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3176 unsigned int tls_type : 8;
34e77a92 3177
b38cadfb
NC		 3178 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3179 unsigned int is_iplt : 1;
34e77a92 3180
b38cadfb 3181 unsigned int unused : 23;
a4fd1a8e 3182
b38cadfb
NC		 3183 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3184 starting at the end of the jump table. */
3185 bfd_vma tlsdesc_got;
0855e32b 3186
b38cadfb
NC		 3187 /* The symbol marking the real symbol location for exported thumb
3188 symbols with Arm stubs. */
3189 struct elf_link_hash_entry *export_glue;
906e58ca 3190
b38cadfb 3191 /* A pointer to the most recently used stub hash entry against this
8029a119 3192 symbol. */
b38cadfb 3193 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3194
3195 /* Counter for FDPIC relocations against this symbol. */
3196 struct fdpic_global fdpic_cnts;
b38cadfb 3197};
252b5132 3198
252b5132 3199/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3200#define elf32_arm_link_hash_traverse(table, func, info) \
3201 (elf_link_hash_traverse \
3202 (&(table)->root, \
b7693d02 3203 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3204 (info)))
3205
3206/* Get the ARM elf linker hash table from a link_info structure. */
3207#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3208 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3209 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3210
906e58ca
NC		 3211#define arm_stub_hash_lookup(table, string, create, copy) \
3212 ((struct elf32_arm_stub_hash_entry *) \
3213 bfd_hash_lookup ((table), (string), (create), (copy)))
3214
21d799b5
NC		 3215/* Array to keep track of which stub sections have been created, and
3216 information on stub grouping. */
3217struct map_stub
3218{
3219 /* This is the section to which stubs in the group will be
3220 attached. */
3221 asection *link_sec;
3222 /* The stub section. */
3223 asection *stub_sec;
3224};
3225
0855e32b
NS		 3226#define elf32_arm_compute_jump_table_size(htab) \
3227 ((htab)->next_tls_desc_index * 4)
3228
9b485d32 3229/* ARM ELF linker hash table. */
252b5132 3230struct elf32_arm_link_hash_table
906e58ca
NC		 3231{
3232 /* The main hash table. */
3233 struct elf_link_hash_table root;
252b5132 3234
906e58ca
NC		 3235 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3236 bfd_size_type thumb_glue_size;
252b5132 3237
906e58ca
NC		 3238 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3239 bfd_size_type arm_glue_size;
252b5132 3240
906e58ca
NC		 3241 /* The size in bytes of section containing the ARMv4 BX veneers. */
3242 bfd_size_type bx_glue_size;
845b51d6 3243
906e58ca
NC		 3244 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3245 veneer has been populated. */
3246 bfd_vma bx_glue_offset[15];
845b51d6 3247
906e58ca
NC		 3248 /* The size in bytes of the section containing glue for VFP11 erratum
3249 veneers. */
3250 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3251
a504d23a
LA		 3252 /* The size in bytes of the section containing glue for STM32L4XX erratum
3253 veneers. */
3254 bfd_size_type stm32l4xx_erratum_glue_size;
3255
48229727
JB		 3256 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3257 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3258 elf32_arm_write_section(). */
3259 struct a8_erratum_fix *a8_erratum_fixes;
3260 unsigned int num_a8_erratum_fixes;
3261
906e58ca
NC		 3262 /* An arbitrary input BFD chosen to hold the glue sections. */
3263 bfd * bfd_of_glue_owner;
ba96a88f 3264
906e58ca
NC		 3265 /* Nonzero to output a BE8 image. */
3266 int byteswap_code;
e489d0ae 3267
906e58ca
NC		 3268 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3269 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3270 int target1_is_rel;
9c504268 3271
906e58ca
NC		 3272 /* The relocation to use for R_ARM_TARGET2 relocations. */
3273 int target2_reloc;
eb043451 3274
906e58ca
NC		 3275 /* 0 = Ignore R_ARM_V4BX.
3276 1 = Convert BX to MOV PC.
3277 2 = Generate v4 interworing stubs. */
3278 int fix_v4bx;
319850b4 3279
48229727
JB		 3280 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3281 int fix_cortex_a8;
3282
2de70689
MGD		 3283 /* Whether we should fix the ARM1176 BLX immediate issue. */
3284 int fix_arm1176;
3285
906e58ca
NC		 3286 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3287 int use_blx;
33bfe774 3288
906e58ca
NC		 3289 /* What sort of code sequences we should look for which may trigger the
3290 VFP11 denorm erratum. */
3291 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3292
906e58ca
NC		 3293 /* Global counter for the number of fixes we have emitted. */
3294 int num_vfp11_fixes;
c7b8f16e 3295
a504d23a
LA		 3296 /* What sort of code sequences we should look for which may trigger the
3297 STM32L4XX erratum. */
3298 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3299
3300 /* Global counter for the number of fixes we have emitted. */
3301 int num_stm32l4xx_fixes;
3302
906e58ca
NC		 3303 /* Nonzero to force PIC branch veneers. */
3304 int pic_veneer;
27e55c4d 3305
906e58ca
NC		 3306 /* The number of bytes in the initial entry in the PLT. */
3307 bfd_size_type plt_header_size;
e5a52504 3308
906e58ca
NC		 3309 /* The number of bytes in the subsequent PLT etries. */
3310 bfd_size_type plt_entry_size;
e5a52504 3311
906e58ca
NC		 3312 /* True if the target system is VxWorks. */
3313 int vxworks_p;
00a97672 3314
906e58ca
NC		 3315 /* True if the target system is Symbian OS. */
3316 int symbian_p;
e5a52504 3317
b38cadfb
NC		 3318 /* True if the target system is Native Client. */
3319 int nacl_p;
3320
906e58ca 3321 /* True if the target uses REL relocations. */
f3185997 3322 bfd_boolean use_rel;
4e7fd91e 3323
54ddd295
TP		 3324 /* Nonzero if import library must be a secure gateway import library
3325 as per ARMv8-M Security Extensions. */
3326 int cmse_implib;
3327
0955507f
TP		 3328 /* The import library whose symbols' address must remain stable in
3329 the import library generated. */
3330 bfd *in_implib_bfd;
3331
0855e32b
NS		 3332 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3333 bfd_vma next_tls_desc_index;
3334
3335 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3336 bfd_vma num_tls_desc;
3337
906e58ca
NC		 3338 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3339 asection *srelplt2;
00a97672 3340
0855e32b
NS		 3341 /* The offset into splt of the PLT entry for the TLS descriptor
3342 resolver. Special values are 0, if not necessary (or not found
3343 to be necessary yet), and -1 if needed but not determined
3344 yet. */
3345 bfd_vma dt_tlsdesc_plt;
3346
3347 /* The offset into sgot of the GOT entry used by the PLT entry
3348 above. */
b38cadfb 3349 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3350
3351 /* Offset in .plt section of tls_arm_trampoline. */
3352 bfd_vma tls_trampoline;
3353
5c5a4843 3354 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3355 union
3356 {
3357 bfd_signed_vma refcount;
3358 bfd_vma offset;
3359 } tls_ldm_got;
b7693d02 3360
87d72d41
AM		 3361 /* Small local sym cache. */
3362 struct sym_cache sym_cache;
906e58ca
NC		 3363
3364 /* For convenience in allocate_dynrelocs. */
3365 bfd * obfd;
3366
0855e32b
NS		 3367 /* The amount of space used by the reserved portion of the sgotplt
3368 section, plus whatever space is used by the jump slots. */
3369 bfd_vma sgotplt_jump_table_size;
3370
906e58ca
NC		 3371 /* The stub hash table. */
3372 struct bfd_hash_table stub_hash_table;
3373
3374 /* Linker stub bfd. */
3375 bfd *stub_bfd;
3376
3377 /* Linker call-backs. */
6bde4c52
TP		 3378 asection * (*add_stub_section) (const char *, asection *, asection *,
3379 unsigned int);
906e58ca
NC		 3380 void (*layout_sections_again) (void);
3381
3382 /* Array to keep track of which stub sections have been created, and
3383 information on stub grouping. */
21d799b5 3384 struct map_stub *stub_group;
906e58ca 3385
4ba2ef8f
TP		 3386 /* Input stub section holding secure gateway veneers. */
3387 asection *cmse_stub_sec;
3388
0955507f
TP		 3389 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3390 start to be allocated. */
3391 bfd_vma new_cmse_stub_offset;
3392
fe33d2fa 3393 /* Number of elements in stub_group. */
7292b3ac 3394 unsigned int top_id;
fe33d2fa 3395
906e58ca
NC		 3396 /* Assorted information used by elf32_arm_size_stubs. */
3397 unsigned int bfd_count;
7292b3ac 3398 unsigned int top_index;
906e58ca 3399 asection **input_list;
617a5ada
CL		 3400
3401 /* True if the target system uses FDPIC. */
3402 int fdpic_p;
e8b09b87
CL		 3403
3404 /* Fixup section. Used for FDPIC. */
3405 asection *srofixup;
906e58ca 3406};
252b5132 3407
e8b09b87
CL		 3408/* Add an FDPIC read-only fixup. */
3409static void
3410arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3411{
3412 bfd_vma fixup_offset;
3413
3414 fixup_offset = srofixup->reloc_count++ * 4;
3415 BFD_ASSERT (fixup_offset < srofixup->size);
3416 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3417}
3418
a504d23a
LA		 3419static inline int
3420ctz (unsigned int mask)
3421{
3422#if GCC_VERSION >= 3004
3423 return __builtin_ctz (mask);
3424#else
3425 unsigned int i;
3426
3427 for (i = 0; i < 8 * sizeof (mask); i++)
3428 {
3429 if (mask & 0x1)
3430 break;
3431 mask = (mask >> 1);
3432 }
3433 return i;
3434#endif
3435}
3436
3437static inline int
b25e998d 3438elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3439{
3440#if GCC_VERSION >= 3004
3441 return __builtin_popcount (mask);
3442#else
b25e998d
CG		 3443 unsigned int i;
3444 int sum = 0;
a504d23a
LA		 3445
3446 for (i = 0; i < 8 * sizeof (mask); i++)
3447 {
3448 if (mask & 0x1)
3449 sum++;
3450 mask = (mask >> 1);
3451 }
3452 return sum;
3453#endif
3454}
3455
e8b09b87
CL		 3456static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3457 asection *sreloc, Elf_Internal_Rela *rel);
3458
3459static void
3460arm_elf_fill_funcdesc(bfd *output_bfd,
3461 struct bfd_link_info *info,
3462 int *funcdesc_offset,
3463 int dynindx,
3464 int offset,
3465 bfd_vma addr,
3466 bfd_vma dynreloc_value,
3467 bfd_vma seg)
3468{
3469 if ((*funcdesc_offset & 1) == 0)
3470 {
3471 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3472 asection *sgot = globals->root.sgot;
3473
3474 if (bfd_link_pic(info))
3475 {
3476 asection *srelgot = globals->root.srelgot;
3477 Elf_Internal_Rela outrel;
3478
3479 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3480 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3481 outrel.r_addend = 0;
3482
3483 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3484 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3485 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3486 }
3487 else
3488 {
3489 struct elf_link_hash_entry *hgot = globals->root.hgot;
3490 bfd_vma got_value = hgot->root.u.def.value
3491 + hgot->root.u.def.section->output_section->vma
3492 + hgot->root.u.def.section->output_offset;
3493
3494 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3495 sgot->output_section->vma + sgot->output_offset
3496 + offset);
3497 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3498 sgot->output_section->vma + sgot->output_offset
3499 + offset + 4);
3500 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3501 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3502 }
3503 *funcdesc_offset |= 1;
3504 }
3505}
3506
780a67af
NC		 3507/* Create an entry in an ARM ELF linker hash table. */
3508
3509static struct bfd_hash_entry *
57e8b36a 3510elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3511 struct bfd_hash_table * table,
3512 const char * string)
780a67af
NC		 3513{
3514 struct elf32_arm_link_hash_entry * ret =
3515 (struct elf32_arm_link_hash_entry *) entry;
3516
3517 /* Allocate the structure if it has not already been allocated by a
3518 subclass. */
906e58ca 3519 if (ret == NULL)
21d799b5 3520 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3521 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3522 if (ret == NULL)
780a67af
NC		 3523 return (struct bfd_hash_entry *) ret;
3524
3525 /* Call the allocation method of the superclass. */
3526 ret = ((struct elf32_arm_link_hash_entry *)
3527 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3528 table, string));
57e8b36a 3529 if (ret != NULL)
b7693d02 3530 {
0bdcacaf 3531 ret->dyn_relocs = NULL;
ba93b8ac 3532 ret->tls_type = GOT_UNKNOWN;
0855e32b 3533 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3534 ret->plt.thumb_refcount = 0;
3535 ret->plt.maybe_thumb_refcount = 0;
3536 ret->plt.noncall_refcount = 0;
3537 ret->plt.got_offset = -1;
3538 ret->is_iplt = FALSE;
a4fd1a8e 3539 ret->export_glue = NULL;
906e58ca
NC		 3540
3541 ret->stub_cache = NULL;
e8b09b87
CL		 3542
3543 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3544 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3545 ret->fdpic_cnts.funcdesc_cnt = 0;
3546 ret->fdpic_cnts.funcdesc_offset = -1;
3547 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3548 }
780a67af
NC		 3549
3550 return (struct bfd_hash_entry *) ret;
3551}
3552
34e77a92
RS		 3553/* Ensure that we have allocated bookkeeping structures for ABFD's local
3554 symbols. */
3555
3556static bfd_boolean
3557elf32_arm_allocate_local_sym_info (bfd *abfd)
3558{
3559 if (elf_local_got_refcounts (abfd) == NULL)
3560 {
3561 bfd_size_type num_syms;
3562 bfd_size_type size;
3563 char *data;
3564
3565 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3566 size = num_syms * (sizeof (bfd_signed_vma)
3567 + sizeof (struct arm_local_iplt_info *)
3568 + sizeof (bfd_vma)
e8b09b87
CL		 3569 + sizeof (char)
3570 + sizeof (struct fdpic_local));
34e77a92
RS		 3571 data = bfd_zalloc (abfd, size);
3572 if (data == NULL)
3573 return FALSE;
3574
e8b09b87
CL		 3575 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3576 data += num_syms * sizeof (struct fdpic_local);
3577
34e77a92
RS		 3578 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3579 data += num_syms * sizeof (bfd_signed_vma);
3580
3581 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3582 data += num_syms * sizeof (struct arm_local_iplt_info *);
3583
3584 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3585 data += num_syms * sizeof (bfd_vma);
3586
3587 elf32_arm_local_got_tls_type (abfd) = data;
3588 }
3589 return TRUE;
3590}
3591
3592/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3593 to input bfd ABFD. Create the information if it doesn't already exist.
3594 Return null if an allocation fails. */
3595
3596static struct arm_local_iplt_info *
3597elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3598{
3599 struct arm_local_iplt_info **ptr;
3600
3601 if (!elf32_arm_allocate_local_sym_info (abfd))
3602 return NULL;
3603
3604 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3605 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3606 if (*ptr == NULL)
3607 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3608 return *ptr;
3609}
3610
3611/* Try to obtain PLT information for the symbol with index R_SYMNDX
3612 in ABFD's symbol table. If the symbol is global, H points to its
3613 hash table entry, otherwise H is null.
3614
3615 Return true if the symbol does have PLT information. When returning
3616 true, point *ROOT_PLT at the target-independent reference count/offset
3617 union and *ARM_PLT at the ARM-specific information. */
3618
3619static bfd_boolean
4ba2ef8f
TP		 3620elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3621 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3622 unsigned long r_symndx, union gotplt_union **root_plt,
3623 struct arm_plt_info **arm_plt)
3624{
3625 struct arm_local_iplt_info *local_iplt;
3626
4ba2ef8f
TP		 3627 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3628 return FALSE;
3629
34e77a92
RS		 3630 if (h != NULL)
3631 {
3632 *root_plt = &h->root.plt;
3633 *arm_plt = &h->plt;
3634 return TRUE;
3635 }
3636
3637 if (elf32_arm_local_iplt (abfd) == NULL)
3638 return FALSE;
3639
3640 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3641 if (local_iplt == NULL)
3642 return FALSE;
3643
3644 *root_plt = &local_iplt->root;
3645 *arm_plt = &local_iplt->arm;
3646 return TRUE;
3647}
3648
59029f57
CL		 3649static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3650
34e77a92
RS		 3651/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3652 before it. */
3653
3654static bfd_boolean
3655elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3656 struct arm_plt_info *arm_plt)
3657{
3658 struct elf32_arm_link_hash_table *htab;
3659
3660 htab = elf32_arm_hash_table (info);
59029f57
CL		 3661
3662 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3663 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3664}
3665
3666/* Return a pointer to the head of the dynamic reloc list that should
3667 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3668 ABFD's symbol table. Return null if an error occurs. */
3669
3670static struct elf_dyn_relocs **
3671elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3672 Elf_Internal_Sym *isym)
3673{
3674 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3675 {
3676 struct arm_local_iplt_info *local_iplt;
3677
3678 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3679 if (local_iplt == NULL)
3680 return NULL;
3681 return &local_iplt->dyn_relocs;
3682 }
3683 else
3684 {
3685 /* Track dynamic relocs needed for local syms too.
3686 We really need local syms available to do this
3687 easily. Oh well. */
3688 asection *s;
3689 void *vpp;
3690
3691 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3692 if (s == NULL)
3693 abort ();
3694
3695 vpp = &elf_section_data (s)->local_dynrel;
3696 return (struct elf_dyn_relocs **) vpp;
3697 }
3698}
3699
906e58ca
NC		 3700/* Initialize an entry in the stub hash table. */
3701
3702static struct bfd_hash_entry *
3703stub_hash_newfunc (struct bfd_hash_entry *entry,
3704 struct bfd_hash_table *table,
3705 const char *string)
3706{
3707 /* Allocate the structure if it has not already been allocated by a
3708 subclass. */
3709 if (entry == NULL)
3710 {
21d799b5 3711 entry = (struct bfd_hash_entry *)
99059e56 3712 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3713 if (entry == NULL)
3714 return entry;
3715 }
3716
3717 /* Call the allocation method of the superclass. */
3718 entry = bfd_hash_newfunc (entry, table, string);
3719 if (entry != NULL)
3720 {
3721 struct elf32_arm_stub_hash_entry *eh;
3722
3723 /* Initialize the local fields. */
3724 eh = (struct elf32_arm_stub_hash_entry *) entry;
3725 eh->stub_sec = NULL;
0955507f 3726 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3727 eh->source_value = 0;
906e58ca
NC		 3728 eh->target_value = 0;
3729 eh->target_section = NULL;
cedfb179 3730 eh->orig_insn = 0;
906e58ca 3731 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3732 eh->stub_size = 0;
3733 eh->stub_template = NULL;
0955507f 3734 eh->stub_template_size = -1;
906e58ca
NC		 3735 eh->h = NULL;
3736 eh->id_sec = NULL;
d8d2f433 3737 eh->output_name = NULL;
906e58ca
NC		 3738 }
3739
3740 return entry;
3741}
3742
00a97672 3743/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3744 shortcuts to them in our hash table. */
3745
3746static bfd_boolean
57e8b36a 3747create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3748{
3749 struct elf32_arm_link_hash_table *htab;
3750
e5a52504 3751 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3752 if (htab == NULL)
3753 return FALSE;
3754
e5a52504
MM		 3755 /* BPABI objects never have a GOT, or associated sections. */
3756 if (htab->symbian_p)
3757 return TRUE;
3758
5e681ec4
PB		 3759 if (! _bfd_elf_create_got_section (dynobj, info))
3760 return FALSE;
3761
e8b09b87
CL		 3762 /* Also create .rofixup. */
3763 if (htab->fdpic_p)
3764 {
3765 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3766 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3767 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
3768 if (htab->srofixup == NULL || ! bfd_set_section_alignment (dynobj, htab->srofixup, 2))
3769 return FALSE;
3770 }
3771
5e681ec4
PB		 3772 return TRUE;
3773}
3774
34e77a92
RS		 3775/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3776
3777static bfd_boolean
3778create_ifunc_sections (struct bfd_link_info *info)
3779{
3780 struct elf32_arm_link_hash_table *htab;
3781 const struct elf_backend_data *bed;
3782 bfd *dynobj;
3783 asection *s;
3784 flagword flags;
b38cadfb 3785
34e77a92
RS		 3786 htab = elf32_arm_hash_table (info);
3787 dynobj = htab->root.dynobj;
3788 bed = get_elf_backend_data (dynobj);
3789 flags = bed->dynamic_sec_flags;
3790
3791 if (htab->root.iplt == NULL)
3792 {
3d4d4302
AM		 3793 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3794 flags | SEC_READONLY | SEC_CODE);
34e77a92 3795 if (s == NULL
a0f49396 3796 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3797 return FALSE;
3798 htab->root.iplt = s;
3799 }
3800
3801 if (htab->root.irelplt == NULL)
3802 {
3d4d4302
AM		 3803 s = bfd_make_section_anyway_with_flags (dynobj,
3804 RELOC_SECTION (htab, ".iplt"),
3805 flags | SEC_READONLY);
34e77a92 3806 if (s == NULL
a0f49396 3807 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3808 return FALSE;
3809 htab->root.irelplt = s;
3810 }
3811
3812 if (htab->root.igotplt == NULL)
3813 {
3d4d4302 3814 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3815 if (s == NULL
3816 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3817 return FALSE;
3818 htab->root.igotplt = s;
3819 }
3820 return TRUE;
3821}
3822
eed94f8f
NC		 3823/* Determine if we're dealing with a Thumb only architecture. */
3824
3825static bfd_boolean
3826using_thumb_only (struct elf32_arm_link_hash_table *globals)
3827{
2fd158eb
TP		 3828 int arch;
3829 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3830 Tag_CPU_arch_profile);
eed94f8f 3831
2fd158eb
TP		 3832 if (profile)
3833 return profile == 'M';
eed94f8f 3834
2fd158eb 3835 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3836
60a019a0 3837 /* Force return logic to be reviewed for each new architecture. */
031254f2 3838 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3839
2fd158eb
TP		 3840 if (arch == TAG_CPU_ARCH_V6_M
3841 || arch == TAG_CPU_ARCH_V6S_M
3842 || arch == TAG_CPU_ARCH_V7E_M
3843 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3844 || arch == TAG_CPU_ARCH_V8M_MAIN
3845 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3846 return TRUE;
eed94f8f 3847
2fd158eb 3848 return FALSE;
eed94f8f
NC		 3849}
3850
3851/* Determine if we're dealing with a Thumb-2 object. */
3852
3853static bfd_boolean
3854using_thumb2 (struct elf32_arm_link_hash_table *globals)
3855{
60a019a0
TP		 3856 int arch;
3857 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3858 Tag_THUMB_ISA_use);
3859
3860 if (thumb_isa)
3861 return thumb_isa == 2;
3862
3863 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3864
3865 /* Force return logic to be reviewed for each new architecture. */
031254f2 3866 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3867
3868 return (arch == TAG_CPU_ARCH_V6T2
3869 || arch == TAG_CPU_ARCH_V7
3870 || arch == TAG_CPU_ARCH_V7E_M
3871 || arch == TAG_CPU_ARCH_V8
bff0500d 3872 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3873 || arch == TAG_CPU_ARCH_V8M_MAIN
3874 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3875}
3876
5e866f5a
TP		 3877/* Determine whether Thumb-2 BL instruction is available. */
3878
3879static bfd_boolean
3880using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3881{
3882 int arch =
3883 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3884
3885 /* Force return logic to be reviewed for each new architecture. */
031254f2 3886 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3887
3888 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3889 return (arch == TAG_CPU_ARCH_V6T2
3890 || arch >= TAG_CPU_ARCH_V7);
3891}
3892
00a97672
RS		 3893/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3894 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3895 hash table. */
3896
3897static bfd_boolean
57e8b36a 3898elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3899{
3900 struct elf32_arm_link_hash_table *htab;
3901
3902 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3903 if (htab == NULL)
3904 return FALSE;
3905
362d30a1 3906 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3907 return FALSE;
3908
3909 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3910 return FALSE;
3911
00a97672
RS		 3912 if (htab->vxworks_p)
3913 {
3914 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3915 return FALSE;
3916
0e1862bb 3917 if (bfd_link_pic (info))
00a97672
RS		 3918 {
3919 htab->plt_header_size = 0;
3920 htab->plt_entry_size
3921 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3922 }
3923 else
3924 {
3925 htab->plt_header_size
3926 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3927 htab->plt_entry_size
3928 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3929 }
aebf9be7
NC		 3930
3931 if (elf_elfheader (dynobj))
3932 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3933 }
eed94f8f
NC		 3934 else
3935 {
3936 /* PR ld/16017
3937 Test for thumb only architectures. Note - we cannot just call
3938 using_thumb_only() as the attributes in the output bfd have not been
3939 initialised at this point, so instead we use the input bfd. */
3940 bfd * saved_obfd = htab->obfd;
3941
3942 htab->obfd = dynobj;
3943 if (using_thumb_only (htab))
3944 {
3945 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3946 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3947 }
3948 htab->obfd = saved_obfd;
3949 }
5e681ec4 3950
7801f98f
CL		 3951 if (htab->fdpic_p) {
3952 htab->plt_header_size = 0;
3953 if (info->flags & DF_BIND_NOW)
3954 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3955 else
3956 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
3957 }
3958
362d30a1
RS		 3959 if (!htab->root.splt
3960 || !htab->root.srelplt
9d19e4fd
AM		 3961 || !htab->root.sdynbss
3962 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3963 abort ();
3964
3965 return TRUE;
3966}
3967
906e58ca
NC		 3968/* Copy the extra info we tack onto an elf_link_hash_entry. */
3969
3970static void
3971elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3972 struct elf_link_hash_entry *dir,
3973 struct elf_link_hash_entry *ind)
3974{
3975 struct elf32_arm_link_hash_entry *edir, *eind;
3976
3977 edir = (struct elf32_arm_link_hash_entry *) dir;
3978 eind = (struct elf32_arm_link_hash_entry *) ind;
3979
0bdcacaf 3980 if (eind->dyn_relocs != NULL)
906e58ca 3981 {
0bdcacaf 3982 if (edir->dyn_relocs != NULL)
906e58ca 3983 {
0bdcacaf
RS		 3984 struct elf_dyn_relocs **pp;
3985 struct elf_dyn_relocs *p;
906e58ca
NC		 3986
3987 /* Add reloc counts against the indirect sym to the direct sym
3988 list. Merge any entries against the same section. */
0bdcacaf 3989 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3990 {
0bdcacaf 3991 struct elf_dyn_relocs *q;
906e58ca 3992
0bdcacaf
RS		 3993 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3994 if (q->sec == p->sec)
906e58ca
NC		 3995 {
3996 q->pc_count += p->pc_count;
3997 q->count += p->count;
3998 *pp = p->next;
3999 break;
4000 }
4001 if (q == NULL)
4002 pp = &p->next;
4003 }
0bdcacaf 4004 *pp = edir->dyn_relocs;
906e58ca
NC		 4005 }
4006
0bdcacaf
RS		 4007 edir->dyn_relocs = eind->dyn_relocs;
4008 eind->dyn_relocs = NULL;
906e58ca
NC		 4009 }
4010
4011 if (ind->root.type == bfd_link_hash_indirect)
4012 {
4013 /* Copy over PLT info. */
34e77a92
RS		 4014 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4015 eind->plt.thumb_refcount = 0;
4016 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4017 eind->plt.maybe_thumb_refcount = 0;
4018 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4019 eind->plt.noncall_refcount = 0;
4020
e8b09b87
CL		 4021 /* Copy FDPIC counters. */
4022 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4023 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4024 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4025
34e77a92
RS		 4026 /* We should only allocate a function to .iplt once the final
4027 symbol information is known. */
4028 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4029
4030 if (dir->got.refcount <= 0)
4031 {
4032 edir->tls_type = eind->tls_type;
4033 eind->tls_type = GOT_UNKNOWN;
4034 }
4035 }
4036
4037 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4038}
4039
68faa637
AM		 4040/* Destroy an ARM elf linker hash table. */
4041
4042static void
d495ab0d 4043elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4044{
4045 struct elf32_arm_link_hash_table *ret
d495ab0d 4046 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4047
4048 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4049 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4050}
4051
906e58ca
NC		 4052/* Create an ARM elf linker hash table. */
4053
4054static struct bfd_link_hash_table *
4055elf32_arm_link_hash_table_create (bfd *abfd)
4056{
4057 struct elf32_arm_link_hash_table *ret;
4058 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4059
7bf52ea2 4060 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4061 if (ret == NULL)
4062 return NULL;
4063
4064 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4065 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4066 sizeof (struct elf32_arm_link_hash_entry),
4067 ARM_ELF_DATA))
906e58ca
NC		 4068 {
4069 free (ret);
4070 return NULL;
4071 }
4072
906e58ca 4073 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4074 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4075#ifdef FOUR_WORD_PLT
4076 ret->plt_header_size = 16;
4077 ret->plt_entry_size = 16;
4078#else
4079 ret->plt_header_size = 20;
1db37fe6 4080 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4081#endif
f3185997 4082 ret->use_rel = TRUE;
906e58ca 4083 ret->obfd = abfd;
617a5ada 4084 ret->fdpic_p = 0;
906e58ca
NC		 4085
4086 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4087 sizeof (struct elf32_arm_stub_hash_entry)))
4088 {
d495ab0d 4089 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4090 return NULL;
4091 }
d495ab0d 4092 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4093
4094 return &ret->root.root;
4095}
4096
cd1dac3d
DG		 4097/* Determine what kind of NOPs are available. */
4098
4099static bfd_boolean
4100arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4101{
4102 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4103 Tag_CPU_arch);
cd1dac3d 4104
60a019a0 4105 /* Force return logic to be reviewed for each new architecture. */
031254f2 4106 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4107
4108 return (arch == TAG_CPU_ARCH_V6T2
4109 || arch == TAG_CPU_ARCH_V6K
4110 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4111 || arch == TAG_CPU_ARCH_V8
4112 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4113}
4114
f4ac8484
DJ		 4115static bfd_boolean
4116arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4117{
4118 switch (stub_type)
4119 {
fea2b4d6 4120 case arm_stub_long_branch_thumb_only:
80c135e5 4121 case arm_stub_long_branch_thumb2_only:
d5a67c02 4122 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4123 case arm_stub_long_branch_v4t_thumb_arm:
4124 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4125 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4126 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4127 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4128 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4129 return TRUE;
4130 case arm_stub_none:
4131 BFD_FAIL ();
4132 return FALSE;
4133 break;
4134 default:
4135 return FALSE;
4136 }
4137}
4138
906e58ca
NC		 4139/* Determine the type of stub needed, if any, for a call. */
4140
4141static enum elf32_arm_stub_type
4142arm_type_of_stub (struct bfd_link_info *info,
4143 asection *input_sec,
4144 const Elf_Internal_Rela *rel,
34e77a92 4145 unsigned char st_type,
35fc36a8 4146 enum arm_st_branch_type *actual_branch_type,
906e58ca 4147 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4148 bfd_vma destination,
4149 asection *sym_sec,
4150 bfd *input_bfd,
4151 const char *name)
906e58ca
NC		 4152{
4153 bfd_vma location;
4154 bfd_signed_vma branch_offset;
4155 unsigned int r_type;
4156 struct elf32_arm_link_hash_table * globals;
5e866f5a 4157 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4158 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4159 int use_plt = 0;
35fc36a8 4160 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4161 union gotplt_union *root_plt;
4162 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4163 int arch;
4164 int thumb2_movw;
906e58ca 4165
35fc36a8 4166 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4167 return stub_type;
4168
906e58ca 4169 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4170 if (globals == NULL)
4171 return stub_type;
906e58ca
NC		 4172
4173 thumb_only = using_thumb_only (globals);
906e58ca 4174 thumb2 = using_thumb2 (globals);
5e866f5a 4175 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4176
d5a67c02
AV		 4177 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4178
4179 /* True for architectures that implement the thumb2 movw instruction. */
4180 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4181
906e58ca
NC		 4182 /* Determine where the call point is. */
4183 location = (input_sec->output_offset
4184 + input_sec->output_section->vma
4185 + rel->r_offset);
4186
906e58ca
NC		 4187 r_type = ELF32_R_TYPE (rel->r_info);
4188
39f21624
NC		 4189 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4190 are considering a function call relocation. */
c5423981 4191 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4192 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4193 && branch_type == ST_BRANCH_TO_ARM)
4194 branch_type = ST_BRANCH_TO_THUMB;
4195
34e77a92
RS		 4196 /* For TLS call relocs, it is the caller's responsibility to provide
4197 the address of the appropriate trampoline. */
4198 if (r_type != R_ARM_TLS_CALL
4199 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4200 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4201 ELF32_R_SYM (rel->r_info), &root_plt,
4202 &arm_plt)
34e77a92 4203 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4204 {
34e77a92 4205 asection *splt;
fe33d2fa 4206
34e77a92
RS		 4207 if (hash == NULL || hash->is_iplt)
4208 splt = globals->root.iplt;
4209 else
4210 splt = globals->root.splt;
4211 if (splt != NULL)
b38cadfb 4212 {
34e77a92
RS		 4213 use_plt = 1;
4214
4215 /* Note when dealing with PLT entries: the main PLT stub is in
4216 ARM mode, so if the branch is in Thumb mode, another
4217 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4218 PLT stub. If a long branch stub is needed, we'll add a
4219 Thumb->Arm one and branch directly to the ARM PLT entry.
4220 Here, we have to check if a pre-PLT Thumb->ARM stub
4221 is needed and if it will be close enough. */
34e77a92
RS		 4222
4223 destination = (splt->output_section->vma
4224 + splt->output_offset
4225 + root_plt->offset);
4226 st_type = STT_FUNC;
2df2751d
CL		 4227
4228 /* Thumb branch/call to PLT: it can become a branch to ARM
4229 or to Thumb. We must perform the same checks and
4230 corrections as in elf32_arm_final_link_relocate. */
4231 if ((r_type == R_ARM_THM_CALL)
4232 || (r_type == R_ARM_THM_JUMP24))
4233 {
4234 if (globals->use_blx
4235 && r_type == R_ARM_THM_CALL
4236 && !thumb_only)
4237 {
4238 /* If the Thumb BLX instruction is available, convert
4239 the BL to a BLX instruction to call the ARM-mode
4240 PLT entry. */
4241 branch_type = ST_BRANCH_TO_ARM;
4242 }
4243 else
4244 {
4245 if (!thumb_only)
4246 /* Target the Thumb stub before the ARM PLT entry. */
4247 destination -= PLT_THUMB_STUB_SIZE;
4248 branch_type = ST_BRANCH_TO_THUMB;
4249 }
4250 }
4251 else
4252 {
4253 branch_type = ST_BRANCH_TO_ARM;
4254 }
34e77a92 4255 }
5fa9e92f 4256 }
34e77a92
RS		 4257 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4258 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4259
fe33d2fa
CL		 4260 branch_offset = (bfd_signed_vma)(destination - location);
4261
0855e32b 4262 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4263 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4264 {
5fa9e92f
CL		 4265 /* Handle cases where:
4266 - this call goes too far (different Thumb/Thumb2 max
99059e56 4267 distance)
155d87d7 4268 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4269 Thumb->Arm branch (not bl). A stub is needed in this case,
4270 but only if this call is not through a PLT entry. Indeed,
695344c0 4271 PLT stubs handle mode switching already. */
5e866f5a 4272 if ((!thumb2_bl
906e58ca
NC		 4273 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4274 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4275 || (thumb2_bl
906e58ca
NC		 4276 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4277 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4278 || (thumb2
4279 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4280 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4281 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4282 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4283 && (((r_type == R_ARM_THM_CALL
4284 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4285 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4286 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4287 && !use_plt))
906e58ca 4288 {
2df2751d
CL		 4289 /* If we need to insert a Thumb-Thumb long branch stub to a
4290 PLT, use one that branches directly to the ARM PLT
4291 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4292 stub, undo this now. */
695344c0
NC		 4293 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4294 {
4295 branch_type = ST_BRANCH_TO_ARM;
4296 branch_offset += PLT_THUMB_STUB_SIZE;
4297 }
2df2751d 4298
35fc36a8 4299 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4300 {
4301 /* Thumb to thumb. */
4302 if (!thumb_only)
4303 {
d5a67c02 4304 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4305 _bfd_error_handler
871b3ab2 4306 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4307 " section with SHF_ARM_PURECODE section"
4308 " attribute is only supported for M-profile"
90b6238f 4309 " targets that implement the movw instruction"),
10463f39 4310 input_bfd, input_sec);
d5a67c02 4311
0e1862bb 4312 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4313 /* PIC stubs. */
155d87d7 4314 ? ((globals->use_blx
9553db3c 4315 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4316 /* V5T and above. Stub starts with ARM code, so
4317 we must be able to switch mode before
4318 reaching it, which is only possible for 'bl'
4319 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4320 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4321 /* On V4T, use Thumb code only. */
d3626fb0 4322 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4323
4324 /* non-PIC stubs. */
155d87d7 4325 : ((globals->use_blx
9553db3c 4326 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4327 /* V5T and above. */
4328 ? arm_stub_long_branch_any_any
4329 /* V4T. */
d3626fb0 4330 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4331 }
4332 else
4333 {
d5a67c02
AV		 4334 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4335 stub_type = arm_stub_long_branch_thumb2_only_pure;
4336 else
4337 {
4338 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4339 _bfd_error_handler
871b3ab2 4340 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4341 " section with SHF_ARM_PURECODE section"
4342 " attribute is only supported for M-profile"
90b6238f 4343 " targets that implement the movw instruction"),
10463f39 4344 input_bfd, input_sec);
d5a67c02
AV		 4345
4346 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4347 /* PIC stub. */
4348 ? arm_stub_long_branch_thumb_only_pic
4349 /* non-PIC stub. */
4350 : (thumb2 ? arm_stub_long_branch_thumb2_only
4351 : arm_stub_long_branch_thumb_only);
4352 }
906e58ca
NC		 4353 }
4354 }
4355 else
4356 {
d5a67c02 4357 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4358 _bfd_error_handler
871b3ab2 4359 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4360 " section with SHF_ARM_PURECODE section"
4361 " attribute is only supported" " for M-profile"
90b6238f 4362 " targets that implement the movw instruction"),
10463f39 4363 input_bfd, input_sec);
d5a67c02 4364
906e58ca 4365 /* Thumb to arm. */
c820be07
NC		 4366 if (sym_sec != NULL
4367 && sym_sec->owner != NULL
4368 && !INTERWORK_FLAG (sym_sec->owner))
4369 {
4eca0228 4370 _bfd_error_handler
90b6238f
AM		 4371 (_("%pB(%s): warning: interworking not enabled;"
4372 " first occurrence: %pB: %s call to %s"),
4373 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4374 }
4375
0855e32b 4376 stub_type =
0e1862bb 4377 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4378 /* PIC stubs. */
0855e32b 4379 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4380 /* TLS PIC stubs. */
0855e32b
NS		 4381 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4382 : arm_stub_long_branch_v4t_thumb_tls_pic)
4383 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4384 /* V5T PIC and above. */
4385 ? arm_stub_long_branch_any_arm_pic
4386 /* V4T PIC stub. */
4387 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4388
4389 /* non-PIC stubs. */
0855e32b 4390 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4391 /* V5T and above. */
4392 ? arm_stub_long_branch_any_any
4393 /* V4T. */
4394 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4395
4396 /* Handle v4t short branches. */
fea2b4d6 4397 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4398 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4399 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4400 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4401 }
4402 }
4403 }
fe33d2fa
CL		 4404 else if (r_type == R_ARM_CALL
4405 || r_type == R_ARM_JUMP24
0855e32b
NS		 4406 || r_type == R_ARM_PLT32
4407 || r_type == R_ARM_TLS_CALL)
906e58ca 4408 {
d5a67c02 4409 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4410 _bfd_error_handler
871b3ab2 4411 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4412 " section with SHF_ARM_PURECODE section"
4413 " attribute is only supported for M-profile"
90b6238f 4414 " targets that implement the movw instruction"),
10463f39 4415 input_bfd, input_sec);
35fc36a8 4416 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4417 {
4418 /* Arm to thumb. */
c820be07
NC		 4419
4420 if (sym_sec != NULL
4421 && sym_sec->owner != NULL
4422 && !INTERWORK_FLAG (sym_sec->owner))
4423 {
4eca0228 4424 _bfd_error_handler
90b6238f
AM		 4425 (_("%pB(%s): warning: interworking not enabled;"
4426 " first occurrence: %pB: %s call to %s"),
4427 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4428 }
4429
4430 /* We have an extra 2-bytes reach because of
4431 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4432 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4433 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4434 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4435 || (r_type == R_ARM_JUMP24)
4436 || (r_type == R_ARM_PLT32))
906e58ca 4437 {
0e1862bb 4438 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4439 /* PIC stubs. */
ebe24dd4
CL		 4440 ? ((globals->use_blx)
4441 /* V5T and above. */
4442 ? arm_stub_long_branch_any_thumb_pic
4443 /* V4T stub. */
4444 : arm_stub_long_branch_v4t_arm_thumb_pic)
4445
c2b4a39d
CL		 4446 /* non-PIC stubs. */
4447 : ((globals->use_blx)
4448 /* V5T and above. */
4449 ? arm_stub_long_branch_any_any
4450 /* V4T. */
4451 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4452 }
4453 }
4454 else
4455 {
4456 /* Arm to arm. */
4457 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4458 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4459 {
0855e32b 4460 stub_type =
0e1862bb 4461 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4462 /* PIC stubs. */
0855e32b 4463 ? (r_type == R_ARM_TLS_CALL
6a631e86 4464 /* TLS PIC Stub. */
0855e32b 4465 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4466 : (globals->nacl_p
4467 ? arm_stub_long_branch_arm_nacl_pic
4468 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4469 /* non-PIC stubs. */
7a89b94e
NC		 4470 : (globals->nacl_p
4471 ? arm_stub_long_branch_arm_nacl
4472 : arm_stub_long_branch_any_any);
906e58ca
NC		 4473 }
4474 }
4475 }
4476
fe33d2fa
CL		 4477 /* If a stub is needed, record the actual destination type. */
4478 if (stub_type != arm_stub_none)
35fc36a8 4479 *actual_branch_type = branch_type;
fe33d2fa 4480
906e58ca
NC		 4481 return stub_type;
4482}
4483
4484/* Build a name for an entry in the stub hash table. */
4485
4486static char *
4487elf32_arm_stub_name (const asection *input_section,
4488 const asection *sym_sec,
4489 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4490 const Elf_Internal_Rela *rel,
4491 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4492{
4493 char *stub_name;
4494 bfd_size_type len;
4495
4496 if (hash)
4497 {
fe33d2fa 4498 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4499 stub_name = (char *) bfd_malloc (len);
906e58ca 4500 if (stub_name != NULL)
fe33d2fa 4501 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4502 input_section->id & 0xffffffff,
4503 hash->root.root.root.string,
fe33d2fa
CL		 4504 (int) rel->r_addend & 0xffffffff,
4505 (int) stub_type);
906e58ca
NC		 4506 }
4507 else
4508 {
fe33d2fa 4509 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4510 stub_name = (char *) bfd_malloc (len);
906e58ca 4511 if (stub_name != NULL)
fe33d2fa 4512 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4513 input_section->id & 0xffffffff,
4514 sym_sec->id & 0xffffffff,
0855e32b
NS		 4515 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4516 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4517 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4518 (int) rel->r_addend & 0xffffffff,
4519 (int) stub_type);
906e58ca
NC		 4520 }
4521
4522 return stub_name;
4523}
4524
4525/* Look up an entry in the stub hash. Stub entries are cached because
4526 creating the stub name takes a bit of time. */
4527
4528static struct elf32_arm_stub_hash_entry *
4529elf32_arm_get_stub_entry (const asection *input_section,
4530 const asection *sym_sec,
4531 struct elf_link_hash_entry *hash,
4532 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4533 struct elf32_arm_link_hash_table *htab,
4534 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4535{
4536 struct elf32_arm_stub_hash_entry *stub_entry;
4537 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4538 const asection *id_sec;
4539
4540 if ((input_section->flags & SEC_CODE) == 0)
4541 return NULL;
4542
4543 /* If this input section is part of a group of sections sharing one
4544 stub section, then use the id of the first section in the group.
4545 Stub names need to include a section id, as there may well be
4546 more than one stub used to reach say, printf, and we need to
4547 distinguish between them. */
c2abbbeb 4548 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4549 id_sec = htab->stub_group[input_section->id].link_sec;
4550
4551 if (h != NULL && h->stub_cache != NULL
4552 && h->stub_cache->h == h
fe33d2fa
CL		 4553 && h->stub_cache->id_sec == id_sec
4554 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4555 {
4556 stub_entry = h->stub_cache;
4557 }
4558 else
4559 {
4560 char *stub_name;
4561
fe33d2fa 4562 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4563 if (stub_name == NULL)
4564 return NULL;
4565
4566 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4567 stub_name, FALSE, FALSE);
4568 if (h != NULL)
4569 h->stub_cache = stub_entry;
4570
4571 free (stub_name);
4572 }
4573
4574 return stub_entry;
4575}
4576
daa4adae
TP		 4577/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4578 section. */
4579
4580static bfd_boolean
4581arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4582{
4583 if (stub_type >= max_stub_type)
4584 abort (); /* Should be unreachable. */
4585
4ba2ef8f
TP		 4586 switch (stub_type)
4587 {
4588 case arm_stub_cmse_branch_thumb_only:
4589 return TRUE;
4590
4591 default:
4592 return FALSE;
4593 }
4594
4595 abort (); /* Should be unreachable. */
daa4adae
TP		 4596}
4597
4598/* Required alignment (as a power of 2) for the dedicated section holding
4599 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4600 with input sections. */
4601
4602static int
4603arm_dedicated_stub_output_section_required_alignment
4604 (enum elf32_arm_stub_type stub_type)
4605{
4606 if (stub_type >= max_stub_type)
4607 abort (); /* Should be unreachable. */
4608
4ba2ef8f
TP		 4609 switch (stub_type)
4610 {
4611 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4612 boundary. */
4613 case arm_stub_cmse_branch_thumb_only:
4614 return 5;
4615
4616 default:
4617 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4618 return 0;
4619 }
4620
4621 abort (); /* Should be unreachable. */
daa4adae
TP		 4622}
4623
4624/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4625 NULL if veneers of this type are interspersed with input sections. */
4626
4627static const char *
4628arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4629{
4630 if (stub_type >= max_stub_type)
4631 abort (); /* Should be unreachable. */
4632
4ba2ef8f
TP		 4633 switch (stub_type)
4634 {
4635 case arm_stub_cmse_branch_thumb_only:
4636 return ".gnu.sgstubs";
4637
4638 default:
4639 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4640 return NULL;
4641 }
4642
4643 abort (); /* Should be unreachable. */
daa4adae
TP		 4644}
4645
4646/* If veneers of type STUB_TYPE should go in a dedicated output section,
4647 returns the address of the hash table field in HTAB holding a pointer to the
4648 corresponding input section. Otherwise, returns NULL. */
4649
4650static asection **
4ba2ef8f
TP		 4651arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4652 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4653{
4654 if (stub_type >= max_stub_type)
4655 abort (); /* Should be unreachable. */
4656
4ba2ef8f
TP		 4657 switch (stub_type)
4658 {
4659 case arm_stub_cmse_branch_thumb_only:
4660 return &htab->cmse_stub_sec;
4661
4662 default:
4663 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4664 return NULL;
4665 }
4666
4667 abort (); /* Should be unreachable. */
daa4adae
TP		 4668}
4669
4670/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4671 is the section that branch into veneer and can be NULL if stub should go in
4672 a dedicated output section. Returns a pointer to the stub section, and the
4673 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4674 LINK_SEC_P may be NULL. */
906e58ca 4675
48229727
JB		 4676static asection *
4677elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4678 struct elf32_arm_link_hash_table *htab,
4679 enum elf32_arm_stub_type stub_type)
906e58ca 4680{
daa4adae
TP		 4681 asection *link_sec, *out_sec, **stub_sec_p;
4682 const char *stub_sec_prefix;
4683 bfd_boolean dedicated_output_section =
4684 arm_dedicated_stub_output_section_required (stub_type);
4685 int align;
906e58ca 4686
daa4adae 4687 if (dedicated_output_section)
906e58ca 4688 {
daa4adae
TP		 4689 bfd *output_bfd = htab->obfd;
4690 const char *out_sec_name =
4691 arm_dedicated_stub_output_section_name (stub_type);
4692 link_sec = NULL;
4693 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4694 stub_sec_prefix = out_sec_name;
4695 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4696 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4697 if (out_sec == NULL)
906e58ca 4698 {
90b6238f 4699 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4700 "section %s"), out_sec_name);
daa4adae 4701 return NULL;
906e58ca 4702 }
daa4adae
TP		 4703 }
4704 else
4705 {
c2abbbeb 4706 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4707 link_sec = htab->stub_group[section->id].link_sec;
4708 BFD_ASSERT (link_sec != NULL);
4709 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4710 if (*stub_sec_p == NULL)
4711 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4712 stub_sec_prefix = link_sec->name;
4713 out_sec = link_sec->output_section;
4714 align = htab->nacl_p ? 4 : 3;
906e58ca 4715 }
b38cadfb 4716
daa4adae
TP		 4717 if (*stub_sec_p == NULL)
4718 {
4719 size_t namelen;
4720 bfd_size_type len;
4721 char *s_name;
4722
4723 namelen = strlen (stub_sec_prefix);
4724 len = namelen + sizeof (STUB_SUFFIX);
4725 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4726 if (s_name == NULL)
4727 return NULL;
4728
4729 memcpy (s_name, stub_sec_prefix, namelen);
4730 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4731 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4732 align);
4733 if (*stub_sec_p == NULL)
4734 return NULL;
4735
4736 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4737 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4738 | SEC_KEEP;
4739 }
4740
4741 if (!dedicated_output_section)
4742 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4743
48229727
JB		 4744 if (link_sec_p)
4745 *link_sec_p = link_sec;
b38cadfb 4746
daa4adae 4747 return *stub_sec_p;
48229727
JB		 4748}
4749
4750/* Add a new stub entry to the stub hash. Not all fields of the new
4751 stub entry are initialised. */
4752
4753static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4754elf32_arm_add_stub (const char *stub_name, asection *section,
4755 struct elf32_arm_link_hash_table *htab,
4756 enum elf32_arm_stub_type stub_type)
48229727
JB		 4757{
4758 asection *link_sec;
4759 asection *stub_sec;
4760 struct elf32_arm_stub_hash_entry *stub_entry;
4761
daa4adae
TP		 4762 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4763 stub_type);
48229727
JB		 4764 if (stub_sec == NULL)
4765 return NULL;
906e58ca
NC		 4766
4767 /* Enter this entry into the linker stub hash table. */
4768 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4769 TRUE, FALSE);
4770 if (stub_entry == NULL)
4771 {
6bde4c52
TP		 4772 if (section == NULL)
4773 section = stub_sec;
871b3ab2 4774 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4775 section->owner, stub_name);
906e58ca
NC		 4776 return NULL;
4777 }
4778
4779 stub_entry->stub_sec = stub_sec;
0955507f 4780 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4781 stub_entry->id_sec = link_sec;
4782
906e58ca
NC		 4783 return stub_entry;
4784}
4785
4786/* Store an Arm insn into an output section not processed by
4787 elf32_arm_write_section. */
4788
4789static void
8029a119
NC		 4790put_arm_insn (struct elf32_arm_link_hash_table * htab,
4791 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4792{
4793 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4794 bfd_putl32 (val, ptr);
4795 else
4796 bfd_putb32 (val, ptr);
4797}
4798
4799/* Store a 16-bit Thumb insn into an output section not processed by
4800 elf32_arm_write_section. */
4801
4802static void
8029a119
NC		 4803put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4804 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4805{
4806 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4807 bfd_putl16 (val, ptr);
4808 else
4809 bfd_putb16 (val, ptr);
4810}
4811
a504d23a
LA		 4812/* Store a Thumb2 insn into an output section not processed by
4813 elf32_arm_write_section. */
4814
4815static void
4816put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4817 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4818{
4819 /* T2 instructions are 16-bit streamed. */
4820 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4821 {
4822 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4823 bfd_putl16 ((val & 0xffff), ptr + 2);
4824 }
4825 else
4826 {
4827 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4828 bfd_putb16 ((val & 0xffff), ptr + 2);
4829 }
4830}
4831
0855e32b
NS		 4832/* If it's possible to change R_TYPE to a more efficient access
4833 model, return the new reloc type. */
4834
4835static unsigned
b38cadfb 4836elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4837 struct elf_link_hash_entry *h)
4838{
4839 int is_local = (h == NULL);
4840
0e1862bb
L		 4841 if (bfd_link_pic (info)
4842 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4843 return r_type;
4844
b38cadfb 4845 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4846 switch (r_type)
4847 {
4848 case R_ARM_TLS_GOTDESC:
4849 case R_ARM_TLS_CALL:
4850 case R_ARM_THM_TLS_CALL:
4851 case R_ARM_TLS_DESCSEQ:
4852 case R_ARM_THM_TLS_DESCSEQ:
4853 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4854 }
4855
4856 return r_type;
4857}
4858
48229727
JB		 4859static bfd_reloc_status_type elf32_arm_final_link_relocate
4860 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4861 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4862 const char *, unsigned char, enum arm_st_branch_type,
4863 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4864
4563a860
JB		 4865static unsigned int
4866arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4867{
4868 switch (stub_type)
4869 {
4870 case arm_stub_a8_veneer_b_cond:
4871 case arm_stub_a8_veneer_b:
4872 case arm_stub_a8_veneer_bl:
4873 return 2;
4874
4875 case arm_stub_long_branch_any_any:
4876 case arm_stub_long_branch_v4t_arm_thumb:
4877 case arm_stub_long_branch_thumb_only:
80c135e5 4878 case arm_stub_long_branch_thumb2_only:
d5a67c02 4879 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4880 case arm_stub_long_branch_v4t_thumb_thumb:
4881 case arm_stub_long_branch_v4t_thumb_arm:
4882 case arm_stub_short_branch_v4t_thumb_arm:
4883 case arm_stub_long_branch_any_arm_pic:
4884 case arm_stub_long_branch_any_thumb_pic:
4885 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4886 case arm_stub_long_branch_v4t_arm_thumb_pic:
4887 case arm_stub_long_branch_v4t_thumb_arm_pic:
4888 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4889 case arm_stub_long_branch_any_tls_pic:
4890 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4891 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4892 case arm_stub_a8_veneer_blx:
4893 return 4;
b38cadfb 4894
7a89b94e
NC		 4895 case arm_stub_long_branch_arm_nacl:
4896 case arm_stub_long_branch_arm_nacl_pic:
4897 return 16;
4898
4563a860
JB		 4899 default:
4900 abort (); /* Should be unreachable. */
4901 }
4902}
4903
4f4faa4d
TP		 4904/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4905 veneering (TRUE) or have their own symbol (FALSE). */
4906
4907static bfd_boolean
4908arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4909{
4910 if (stub_type >= max_stub_type)
4911 abort (); /* Should be unreachable. */
4912
4ba2ef8f
TP		 4913 switch (stub_type)
4914 {
4915 case arm_stub_cmse_branch_thumb_only:
4916 return TRUE;
4917
4918 default:
4919 return FALSE;
4920 }
4921
4922 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4923}
4924
d7c5bd02
TP		 4925/* Returns the padding needed for the dedicated section used stubs of type
4926 STUB_TYPE. */
4927
4928static int
4929arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4930{
4931 if (stub_type >= max_stub_type)
4932 abort (); /* Should be unreachable. */
4933
4ba2ef8f
TP		 4934 switch (stub_type)
4935 {
4936 case arm_stub_cmse_branch_thumb_only:
4937 return 32;
4938
4939 default:
4940 return 0;
4941 }
4942
4943 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4944}
4945
0955507f
TP		 4946/* If veneers of type STUB_TYPE should go in a dedicated output section,
4947 returns the address of the hash table field in HTAB holding the offset at
4948 which new veneers should be layed out in the stub section. */
4949
4950static bfd_vma*
4951arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4952 enum elf32_arm_stub_type stub_type)
4953{
4954 switch (stub_type)
4955 {
4956 case arm_stub_cmse_branch_thumb_only:
4957 return &htab->new_cmse_stub_offset;
4958
4959 default:
4960 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4961 return NULL;
4962 }
4963}
4964
906e58ca
NC		 4965static bfd_boolean
4966arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4967 void * in_arg)
4968{
7a89b94e 4969#define MAXRELOCS 3
0955507f 4970 bfd_boolean removed_sg_veneer;
906e58ca 4971 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4972 struct elf32_arm_link_hash_table *globals;
906e58ca 4973 struct bfd_link_info *info;
906e58ca
NC		 4974 asection *stub_sec;
4975 bfd *stub_bfd;
906e58ca
NC		 4976 bfd_byte *loc;
4977 bfd_vma sym_value;
4978 int template_size;
4979 int size;
d3ce72d0 4980 const insn_sequence *template_sequence;
906e58ca 4981 int i;
48229727
JB		 4982 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4983 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4984 int nrelocs = 0;
0955507f 4985 int just_allocated = 0;
906e58ca
NC		 4986
4987 /* Massage our args to the form they really have. */
4988 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4989 info = (struct bfd_link_info *) in_arg;
4990
4991 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4992 if (globals == NULL)
4993 return FALSE;
906e58ca 4994
906e58ca
NC		 4995 stub_sec = stub_entry->stub_sec;
4996
4dfe6ac6 4997 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4998 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4999 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5000 return TRUE;
fe33d2fa 5001
0955507f
TP		 5002 /* Assign a slot at the end of section if none assigned yet. */
5003 if (stub_entry->stub_offset == (bfd_vma) -1)
5004 {
5005 stub_entry->stub_offset = stub_sec->size;
5006 just_allocated = 1;
5007 }
906e58ca
NC		 5008 loc = stub_sec->contents + stub_entry->stub_offset;
5009
5010 stub_bfd = stub_sec->owner;
5011
906e58ca
NC		 5012 /* This is the address of the stub destination. */
5013 sym_value = (stub_entry->target_value
5014 + stub_entry->target_section->output_offset
5015 + stub_entry->target_section->output_section->vma);
5016
d3ce72d0 5017 template_sequence = stub_entry->stub_template;
461a49ca 5018 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5019
5020 size = 0;
461a49ca 5021 for (i = 0; i < template_size; i++)
906e58ca 5022 {
d3ce72d0 5023 switch (template_sequence[i].type)
461a49ca
DJ		 5024 {
5025 case THUMB16_TYPE:
48229727 5026 {
d3ce72d0
NC		 5027 bfd_vma data = (bfd_vma) template_sequence[i].data;
5028 if (template_sequence[i].reloc_addend != 0)
48229727 5029 {
99059e56
RM		 5030 /* We've borrowed the reloc_addend field to mean we should
5031 insert a condition code into this (Thumb-1 branch)
5032 instruction. See THUMB16_BCOND_INSN. */
5033 BFD_ASSERT ((data & 0xff00) == 0xd000);
5034 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5035 }
fe33d2fa 5036 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5037 size += 2;
5038 }
461a49ca 5039 break;
906e58ca 5040
48229727 5041 case THUMB32_TYPE:
fe33d2fa
CL		 5042 bfd_put_16 (stub_bfd,
5043 (template_sequence[i].data >> 16) & 0xffff,
5044 loc + size);
5045 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5046 loc + size + 2);
99059e56
RM		 5047 if (template_sequence[i].r_type != R_ARM_NONE)
5048 {
5049 stub_reloc_idx[nrelocs] = i;
5050 stub_reloc_offset[nrelocs++] = size;
5051 }
5052 size += 4;
5053 break;
48229727 5054
461a49ca 5055 case ARM_TYPE:
fe33d2fa
CL		 5056 bfd_put_32 (stub_bfd, template_sequence[i].data,
5057 loc + size);
461a49ca
DJ		 5058 /* Handle cases where the target is encoded within the
5059 instruction. */
d3ce72d0 5060 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5061 {
48229727
JB		 5062 stub_reloc_idx[nrelocs] = i;
5063 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5064 }
5065 size += 4;
5066 break;
5067
5068 case DATA_TYPE:
d3ce72d0 5069 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5070 stub_reloc_idx[nrelocs] = i;
5071 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5072 size += 4;
5073 break;
5074
5075 default:
5076 BFD_FAIL ();
5077 return FALSE;
5078 }
906e58ca 5079 }
461a49ca 5080
0955507f
TP		 5081 if (just_allocated)
5082 stub_sec->size += size;
906e58ca 5083
461a49ca
DJ		 5084 /* Stub size has already been computed in arm_size_one_stub. Check
5085 consistency. */
5086 BFD_ASSERT (size == stub_entry->stub_size);
5087
906e58ca 5088 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5089 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5090 sym_value |= 1;
5091
0955507f
TP		 5092 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5093 to relocate in each stub. */
5094 removed_sg_veneer =
5095 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5096 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5097
48229727 5098 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5099 {
5100 Elf_Internal_Rela rel;
5101 bfd_boolean unresolved_reloc;
5102 char *error_message;
5103 bfd_vma points_to =
5104 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5105
5106 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5107 rel.r_info = ELF32_R_INFO (0,
5108 template_sequence[stub_reloc_idx[i]].r_type);
5109 rel.r_addend = 0;
5110
5111 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5112 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5113 template should refer back to the instruction after the original
5114 branch. We use target_section as Cortex-A8 erratum workaround stubs
5115 are only generated when both source and target are in the same
5116 section. */
5117 points_to = stub_entry->target_section->output_section->vma
5118 + stub_entry->target_section->output_offset
5119 + stub_entry->source_value;
5120
5121 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5122 (template_sequence[stub_reloc_idx[i]].r_type),
5123 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5124 points_to, info, stub_entry->target_section, "", STT_FUNC,
5125 stub_entry->branch_type,
5126 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5127 &error_message);
5128 }
906e58ca
NC		 5129
5130 return TRUE;
48229727 5131#undef MAXRELOCS
906e58ca
NC		 5132}
5133
48229727
JB		 5134/* Calculate the template, template size and instruction size for a stub.
5135 Return value is the instruction size. */
906e58ca 5136
48229727
JB		 5137static unsigned int
5138find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5139 const insn_sequence **stub_template,
5140 int *stub_template_size)
906e58ca 5141{
d3ce72d0 5142 const insn_sequence *template_sequence = NULL;
48229727
JB		 5143 int template_size = 0, i;
5144 unsigned int size;
906e58ca 5145
d3ce72d0 5146 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5147 if (stub_template)
5148 *stub_template = template_sequence;
5149
48229727 5150 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5151 if (stub_template_size)
5152 *stub_template_size = template_size;
906e58ca
NC		 5153
5154 size = 0;
461a49ca
DJ		 5155 for (i = 0; i < template_size; i++)
5156 {
d3ce72d0 5157 switch (template_sequence[i].type)
461a49ca
DJ		 5158 {
5159 case THUMB16_TYPE:
5160 size += 2;
5161 break;
5162
5163 case ARM_TYPE:
48229727 5164 case THUMB32_TYPE:
461a49ca
DJ		 5165 case DATA_TYPE:
5166 size += 4;
5167 break;
5168
5169 default:
5170 BFD_FAIL ();
2a229407 5171 return 0;
461a49ca
DJ		 5172 }
5173 }
5174
48229727
JB		 5175 return size;
5176}
5177
5178/* As above, but don't actually build the stub. Just bump offset so
5179 we know stub section sizes. */
5180
5181static bfd_boolean
5182arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5183 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5184{
5185 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5186 const insn_sequence *template_sequence;
48229727
JB		 5187 int template_size, size;
5188
5189 /* Massage our args to the form they really have. */
5190 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5191
5192 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5193 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5194
d3ce72d0 5195 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5196 &template_size);
5197
0955507f
TP		 5198 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5199 if (stub_entry->stub_template_size)
5200 {
5201 stub_entry->stub_size = size;
5202 stub_entry->stub_template = template_sequence;
5203 stub_entry->stub_template_size = template_size;
5204 }
5205
5206 /* Already accounted for. */
5207 if (stub_entry->stub_offset != (bfd_vma) -1)
5208 return TRUE;
461a49ca 5209
906e58ca
NC		 5210 size = (size + 7) & ~7;
5211 stub_entry->stub_sec->size += size;
461a49ca 5212
906e58ca
NC		 5213 return TRUE;
5214}
5215
5216/* External entry points for sizing and building linker stubs. */
5217
5218/* Set up various things so that we can make a list of input sections
5219 for each output section included in the link. Returns -1 on error,
5220 0 when no stubs will be needed, and 1 on success. */
5221
5222int
5223elf32_arm_setup_section_lists (bfd *output_bfd,
5224 struct bfd_link_info *info)
5225{
5226 bfd *input_bfd;
5227 unsigned int bfd_count;
7292b3ac 5228 unsigned int top_id, top_index;
906e58ca
NC		 5229 asection *section;
5230 asection **input_list, **list;
5231 bfd_size_type amt;
5232 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5233
4dfe6ac6
NC		 5234 if (htab == NULL)
5235 return 0;
906e58ca
NC		 5236 if (! is_elf_hash_table (htab))
5237 return 0;
5238
5239 /* Count the number of input BFDs and find the top input section id. */
5240 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5241 input_bfd != NULL;
c72f2fb2 5242 input_bfd = input_bfd->link.next)
906e58ca
NC		 5243 {
5244 bfd_count += 1;
5245 for (section = input_bfd->sections;
5246 section != NULL;
5247 section = section->next)
5248 {
5249 if (top_id < section->id)
5250 top_id = section->id;
5251 }
5252 }
5253 htab->bfd_count = bfd_count;
5254
5255 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5256 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5257 if (htab->stub_group == NULL)
5258 return -1;
fe33d2fa 5259 htab->top_id = top_id;
906e58ca
NC		 5260
5261 /* We can't use output_bfd->section_count here to find the top output
5262 section index as some sections may have been removed, and
5263 _bfd_strip_section_from_output doesn't renumber the indices. */
5264 for (section = output_bfd->sections, top_index = 0;
5265 section != NULL;
5266 section = section->next)
5267 {
5268 if (top_index < section->index)
5269 top_index = section->index;
5270 }
5271
5272 htab->top_index = top_index;
5273 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5274 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5275 htab->input_list = input_list;
5276 if (input_list == NULL)
5277 return -1;
5278
5279 /* For sections we aren't interested in, mark their entries with a
5280 value we can check later. */
5281 list = input_list + top_index;
5282 do
5283 *list = bfd_abs_section_ptr;
5284 while (list-- != input_list);
5285
5286 for (section = output_bfd->sections;
5287 section != NULL;
5288 section = section->next)
5289 {
5290 if ((section->flags & SEC_CODE) != 0)
5291 input_list[section->index] = NULL;
5292 }
5293
5294 return 1;
5295}
5296
5297/* The linker repeatedly calls this function for each input section,
5298 in the order that input sections are linked into output sections.
5299 Build lists of input sections to determine groupings between which
5300 we may insert linker stubs. */
5301
5302void
5303elf32_arm_next_input_section (struct bfd_link_info *info,
5304 asection *isec)
5305{
5306 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5307
4dfe6ac6
NC		 5308 if (htab == NULL)
5309 return;
5310
906e58ca
NC		 5311 if (isec->output_section->index <= htab->top_index)
5312 {
5313 asection **list = htab->input_list + isec->output_section->index;
5314
a7470592 5315 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5316 {
5317 /* Steal the link_sec pointer for our list. */
5318#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5319 /* This happens to make the list in reverse order,
07d72278 5320 which we reverse later. */
906e58ca
NC		 5321 PREV_SEC (isec) = *list;
5322 *list = isec;
5323 }
5324 }
5325}
5326
5327/* See whether we can group stub sections together. Grouping stub
5328 sections may result in fewer stubs. More importantly, we need to
07d72278 5329 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5330 .fini output sections respectively, because glibc splits the
5331 _init and _fini functions into multiple parts. Putting a stub in
5332 the middle of a function is not a good idea. */
5333
5334static void
5335group_sections (struct elf32_arm_link_hash_table *htab,
5336 bfd_size_type stub_group_size,
07d72278 5337 bfd_boolean stubs_always_after_branch)
906e58ca 5338{
07d72278 5339 asection **list = htab->input_list;
906e58ca
NC		 5340
5341 do
5342 {
5343 asection *tail = *list;
07d72278 5344 asection *head;
906e58ca
NC		 5345
5346 if (tail == bfd_abs_section_ptr)
5347 continue;
5348
07d72278
DJ		 5349 /* Reverse the list: we must avoid placing stubs at the
5350 beginning of the section because the beginning of the text
5351 section may be required for an interrupt vector in bare metal
5352 code. */
5353#define NEXT_SEC PREV_SEC
e780aef2
CL		 5354 head = NULL;
5355 while (tail != NULL)
99059e56
RM		 5356 {
5357 /* Pop from tail. */
5358 asection *item = tail;
5359 tail = PREV_SEC (item);
e780aef2 5360
99059e56
RM		 5361 /* Push on head. */
5362 NEXT_SEC (item) = head;
5363 head = item;
5364 }
07d72278
DJ		 5365
5366 while (head != NULL)
906e58ca
NC		 5367 {
5368 asection *curr;
07d72278 5369 asection *next;
e780aef2
CL		 5370 bfd_vma stub_group_start = head->output_offset;
5371 bfd_vma end_of_next;
906e58ca 5372
07d72278 5373 curr = head;
e780aef2 5374 while (NEXT_SEC (curr) != NULL)
8cd931b7 5375 {
e780aef2
CL		 5376 next = NEXT_SEC (curr);
5377 end_of_next = next->output_offset + next->size;
5378 if (end_of_next - stub_group_start >= stub_group_size)
5379 /* End of NEXT is too far from start, so stop. */
8cd931b7 5380 break;
e780aef2
CL		 5381 /* Add NEXT to the group. */
5382 curr = next;
8cd931b7 5383 }
906e58ca 5384
07d72278 5385 /* OK, the size from the start to the start of CURR is less
906e58ca 5386 than stub_group_size and thus can be handled by one stub
07d72278 5387 section. (Or the head section is itself larger than
906e58ca
NC		 5388 stub_group_size, in which case we may be toast.)
5389 We should really be keeping track of the total size of
5390 stubs added here, as stubs contribute to the final output
7fb9f789 5391 section size. */
906e58ca
NC		 5392 do
5393 {
07d72278 5394 next = NEXT_SEC (head);
906e58ca 5395 /* Set up this stub group. */
07d72278 5396 htab->stub_group[head->id].link_sec = curr;
906e58ca 5397 }
07d72278 5398 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5399
5400 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5401 bytes after the stub section can be handled by it too. */
5402 if (!stubs_always_after_branch)
906e58ca 5403 {
e780aef2
CL		 5404 stub_group_start = curr->output_offset + curr->size;
5405
8cd931b7 5406 while (next != NULL)
906e58ca 5407 {
e780aef2
CL		 5408 end_of_next = next->output_offset + next->size;
5409 if (end_of_next - stub_group_start >= stub_group_size)
5410 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5411 break;
e780aef2 5412 /* Add NEXT to the stub group. */
07d72278
DJ		 5413 head = next;
5414 next = NEXT_SEC (head);
5415 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5416 }
5417 }
07d72278 5418 head = next;
906e58ca
NC		 5419 }
5420 }
07d72278 5421 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5422
5423 free (htab->input_list);
5424#undef PREV_SEC
07d72278 5425#undef NEXT_SEC
906e58ca
NC		 5426}
5427
48229727
JB		 5428/* Comparison function for sorting/searching relocations relating to Cortex-A8
5429 erratum fix. */
5430
5431static int
5432a8_reloc_compare (const void *a, const void *b)
5433{
21d799b5
NC		 5434 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5435 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5436
5437 if (ra->from < rb->from)
5438 return -1;
5439 else if (ra->from > rb->from)
5440 return 1;
5441 else
5442 return 0;
5443}
5444
5445static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5446 const char *, char **);
5447
5448/* Helper function to scan code for sequences which might trigger the Cortex-A8
5449 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5450 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5451 otherwise. */
5452
81694485
NC		 5453static bfd_boolean
5454cortex_a8_erratum_scan (bfd *input_bfd,
5455 struct bfd_link_info *info,
48229727
JB		 5456 struct a8_erratum_fix **a8_fixes_p,
5457 unsigned int *num_a8_fixes_p,
5458 unsigned int *a8_fix_table_size_p,
5459 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5460 unsigned int num_a8_relocs,
5461 unsigned prev_num_a8_fixes,
5462 bfd_boolean *stub_changed_p)
48229727
JB		 5463{
5464 asection *section;
5465 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5466 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5467 unsigned int num_a8_fixes = *num_a8_fixes_p;
5468 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5469
4dfe6ac6
NC		 5470 if (htab == NULL)
5471 return FALSE;
5472
48229727
JB		 5473 for (section = input_bfd->sections;
5474 section != NULL;
5475 section = section->next)
5476 {
5477 bfd_byte *contents = NULL;
5478 struct _arm_elf_section_data *sec_data;
5479 unsigned int span;
5480 bfd_vma base_vma;
5481
5482 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5483 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5484 || (section->flags & SEC_EXCLUDE) != 0
5485 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5486 || (section->output_section == bfd_abs_section_ptr))
5487 continue;
48229727
JB		 5488
5489 base_vma = section->output_section->vma + section->output_offset;
5490
5491 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5492 contents = elf_section_data (section)->this_hdr.contents;
48229727 5493 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5494 return TRUE;
48229727
JB		 5495
5496 sec_data = elf32_arm_section_data (section);
5497
5498 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5499 {
5500 unsigned int span_start = sec_data->map[span].vma;
5501 unsigned int span_end = (span == sec_data->mapcount - 1)
5502 ? section->size : sec_data->map[span + 1].vma;
5503 unsigned int i;
5504 char span_type = sec_data->map[span].type;
5505 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5506
5507 if (span_type != 't')
5508 continue;
5509
5510 /* Span is entirely within a single 4KB region: skip scanning. */
5511 if (((base_vma + span_start) & ~0xfff)
48229727 5512 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5513 continue;
5514
5515 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5516
5517 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5518 * The branch target is in the same 4KB region as the
5519 first half of the branch.
5520 * The instruction before the branch is a 32-bit
5521 length non-branch instruction. */
5522 for (i = span_start; i < span_end;)
5523 {
5524 unsigned int insn = bfd_getl16 (&contents[i]);
5525 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5526 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5527
99059e56
RM		 5528 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5529 insn_32bit = TRUE;
48229727
JB		 5530
5531 if (insn_32bit)
99059e56
RM		 5532 {
5533 /* Load the rest of the insn (in manual-friendly order). */
5534 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5535
5536 /* Encoding T4: B<c>.W. */
5537 is_b = (insn & 0xf800d000) == 0xf0009000;
5538 /* Encoding T1: BL<c>.W. */
5539 is_bl = (insn & 0xf800d000) == 0xf000d000;
5540 /* Encoding T2: BLX<c>.W. */
5541 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5542 /* Encoding T3: B<c>.W (not permitted in IT block). */
5543 is_bcc = (insn & 0xf800d000) == 0xf0008000
5544 && (insn & 0x07f00000) != 0x03800000;
5545 }
5546
5547 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5548
99059e56 5549 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5550 && insn_32bit
5551 && is_32bit_branch
5552 && last_was_32bit
5553 && ! last_was_branch)
99059e56
RM		 5554 {
5555 bfd_signed_vma offset = 0;
5556 bfd_boolean force_target_arm = FALSE;
48229727 5557 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5558 bfd_vma target;
5559 enum elf32_arm_stub_type stub_type = arm_stub_none;
5560 struct a8_erratum_reloc key, *found;
5561 bfd_boolean use_plt = FALSE;
48229727 5562
99059e56
RM		 5563 key.from = base_vma + i;
5564 found = (struct a8_erratum_reloc *)
5565 bsearch (&key, a8_relocs, num_a8_relocs,
5566 sizeof (struct a8_erratum_reloc),
5567 &a8_reloc_compare);
48229727
JB		 5568
5569 if (found)
5570 {
5571 char *error_message = NULL;
5572 struct elf_link_hash_entry *entry;
5573
5574 /* We don't care about the error returned from this
99059e56 5575 function, only if there is glue or not. */
48229727
JB		 5576 entry = find_thumb_glue (info, found->sym_name,
5577 &error_message);
5578
5579 if (entry)
5580 found->non_a8_stub = TRUE;
5581
92750f34 5582 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5583 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5584 && found->hash->root.plt.offset != (bfd_vma) -1)
5585 use_plt = TRUE;
5586
5587 if (found->r_type == R_ARM_THM_CALL)
5588 {
35fc36a8
RS		 5589 if (found->branch_type == ST_BRANCH_TO_ARM
5590 || use_plt)
92750f34
DJ		 5591 force_target_arm = TRUE;
5592 else
5593 force_target_thumb = TRUE;
5594 }
48229727
JB		 5595 }
5596
99059e56 5597 /* Check if we have an offending branch instruction. */
48229727
JB		 5598
5599 if (found && found->non_a8_stub)
5600 /* We've already made a stub for this instruction, e.g.
5601 it's a long branch or a Thumb->ARM stub. Assume that
5602 stub will suffice to work around the A8 erratum (see
5603 setting of always_after_branch above). */
5604 ;
99059e56
RM		 5605 else if (is_bcc)
5606 {
5607 offset = (insn & 0x7ff) << 1;
5608 offset |= (insn & 0x3f0000) >> 4;
5609 offset |= (insn & 0x2000) ? 0x40000 : 0;
5610 offset |= (insn & 0x800) ? 0x80000 : 0;
5611 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5612 if (offset & 0x100000)
5613 offset |= ~ ((bfd_signed_vma) 0xfffff);
5614 stub_type = arm_stub_a8_veneer_b_cond;
5615 }
5616 else if (is_b || is_bl || is_blx)
5617 {
5618 int s = (insn & 0x4000000) != 0;
5619 int j1 = (insn & 0x2000) != 0;
5620 int j2 = (insn & 0x800) != 0;
5621 int i1 = !(j1 ^ s);
5622 int i2 = !(j2 ^ s);
5623
5624 offset = (insn & 0x7ff) << 1;
5625 offset |= (insn & 0x3ff0000) >> 4;
5626 offset |= i2 << 22;
5627 offset |= i1 << 23;
5628 offset |= s << 24;
5629 if (offset & 0x1000000)
5630 offset |= ~ ((bfd_signed_vma) 0xffffff);
5631
5632 if (is_blx)
5633 offset &= ~ ((bfd_signed_vma) 3);
5634
5635 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5636 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5637 }
5638
5639 if (stub_type != arm_stub_none)
5640 {
5641 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5642
5643 /* The original instruction is a BL, but the target is
99059e56 5644 an ARM instruction. If we were not making a stub,
48229727
JB		 5645 the BL would have been converted to a BLX. Use the
5646 BLX stub instead in that case. */
5647 if (htab->use_blx && force_target_arm
5648 && stub_type == arm_stub_a8_veneer_bl)
5649 {
5650 stub_type = arm_stub_a8_veneer_blx;
5651 is_blx = TRUE;
5652 is_bl = FALSE;
5653 }
5654 /* Conversely, if the original instruction was
5655 BLX but the target is Thumb mode, use the BL
5656 stub. */
5657 else if (force_target_thumb
5658 && stub_type == arm_stub_a8_veneer_blx)
5659 {
5660 stub_type = arm_stub_a8_veneer_bl;
5661 is_blx = FALSE;
5662 is_bl = TRUE;
5663 }
5664
99059e56
RM		 5665 if (is_blx)
5666 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5667
99059e56
RM		 5668 /* If we found a relocation, use the proper destination,
5669 not the offset in the (unrelocated) instruction.
48229727
JB		 5670 Note this is always done if we switched the stub type
5671 above. */
99059e56
RM		 5672 if (found)
5673 offset =
81694485 5674 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5675
99059e56
RM		 5676 /* If the stub will use a Thumb-mode branch to a
5677 PLT target, redirect it to the preceding Thumb
5678 entry point. */
5679 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5680 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5681
99059e56 5682 target = pc_for_insn + offset;
48229727 5683
99059e56
RM		 5684 /* The BLX stub is ARM-mode code. Adjust the offset to
5685 take the different PC value (+8 instead of +4) into
48229727 5686 account. */
99059e56
RM		 5687 if (stub_type == arm_stub_a8_veneer_blx)
5688 offset += 4;
5689
5690 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5691 {
5692 char *stub_name = NULL;
5693
5694 if (num_a8_fixes == a8_fix_table_size)
5695 {
5696 a8_fix_table_size *= 2;
5697 a8_fixes = (struct a8_erratum_fix *)
5698 bfd_realloc (a8_fixes,
5699 sizeof (struct a8_erratum_fix)
5700 * a8_fix_table_size);
5701 }
48229727 5702
eb7c4339
NS		 5703 if (num_a8_fixes < prev_num_a8_fixes)
5704 {
5705 /* If we're doing a subsequent scan,
5706 check if we've found the same fix as
5707 before, and try and reuse the stub
5708 name. */
5709 stub_name = a8_fixes[num_a8_fixes].stub_name;
5710 if ((a8_fixes[num_a8_fixes].section != section)
5711 || (a8_fixes[num_a8_fixes].offset != i))
5712 {
5713 free (stub_name);
5714 stub_name = NULL;
5715 *stub_changed_p = TRUE;
5716 }
5717 }
5718
5719 if (!stub_name)
5720 {
21d799b5 5721 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5722 if (stub_name != NULL)
5723 sprintf (stub_name, "%x:%x", section->id, i);
5724 }
48229727 5725
99059e56
RM		 5726 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5727 a8_fixes[num_a8_fixes].section = section;
5728 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5729 a8_fixes[num_a8_fixes].target_offset =
5730 target - base_vma;
99059e56
RM		 5731 a8_fixes[num_a8_fixes].orig_insn = insn;
5732 a8_fixes[num_a8_fixes].stub_name = stub_name;
5733 a8_fixes[num_a8_fixes].stub_type = stub_type;
5734 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5735 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5736
99059e56
RM		 5737 num_a8_fixes++;
5738 }
5739 }
5740 }
48229727 5741
99059e56
RM		 5742 i += insn_32bit ? 4 : 2;
5743 last_was_32bit = insn_32bit;
48229727 5744 last_was_branch = is_32bit_branch;
99059e56
RM		 5745 }
5746 }
48229727
JB		 5747
5748 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5749 free (contents);
48229727 5750 }
fe33d2fa 5751
48229727
JB		 5752 *a8_fixes_p = a8_fixes;
5753 *num_a8_fixes_p = num_a8_fixes;
5754 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5755
81694485 5756 return FALSE;
48229727
JB		 5757}
5758
b715f643
TP		 5759/* Create or update a stub entry depending on whether the stub can already be
5760 found in HTAB. The stub is identified by:
5761 - its type STUB_TYPE
5762 - its source branch (note that several can share the same stub) whose
5763 section and relocation (if any) are given by SECTION and IRELA
5764 respectively
5765 - its target symbol whose input section, hash, name, value and branch type
5766 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5767 respectively
5768
5769 If found, the value of the stub's target symbol is updated from SYM_VALUE
5770 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5771 TRUE and the stub entry is initialized.
5772
0955507f
TP		 5773 Returns the stub that was created or updated, or NULL if an error
5774 occurred. */
b715f643 5775
0955507f 5776static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5777elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5778 enum elf32_arm_stub_type stub_type, asection *section,
5779 Elf_Internal_Rela *irela, asection *sym_sec,
5780 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5781 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5782 bfd_boolean *new_stub)
5783{
5784 const asection *id_sec;
5785 char *stub_name;
5786 struct elf32_arm_stub_hash_entry *stub_entry;
5787 unsigned int r_type;
4f4faa4d 5788 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5789
5790 BFD_ASSERT (stub_type != arm_stub_none);
5791 *new_stub = FALSE;
5792
4f4faa4d
TP		 5793 if (sym_claimed)
5794 stub_name = sym_name;
5795 else
5796 {
5797 BFD_ASSERT (irela);
5798 BFD_ASSERT (section);
c2abbbeb 5799 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5800
4f4faa4d
TP		 5801 /* Support for grouping stub sections. */
5802 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5803
4f4faa4d
TP		 5804 /* Get the name of this stub. */
5805 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5806 stub_type);
5807 if (!stub_name)
0955507f 5808 return NULL;
4f4faa4d 5809 }
b715f643
TP		 5810
5811 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5812 FALSE);
5813 /* The proper stub has already been created, just update its value. */
5814 if (stub_entry != NULL)
5815 {
4f4faa4d
TP		 5816 if (!sym_claimed)
5817 free (stub_name);
b715f643 5818 stub_entry->target_value = sym_value;
0955507f 5819 return stub_entry;
b715f643
TP		 5820 }
5821
daa4adae 5822 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5823 if (stub_entry == NULL)
5824 {
4f4faa4d
TP		 5825 if (!sym_claimed)
5826 free (stub_name);
0955507f 5827 return NULL;
b715f643
TP		 5828 }
5829
5830 stub_entry->target_value = sym_value;
5831 stub_entry->target_section = sym_sec;
5832 stub_entry->stub_type = stub_type;
5833 stub_entry->h = hash;
5834 stub_entry->branch_type = branch_type;
5835
4f4faa4d
TP		 5836 if (sym_claimed)
5837 stub_entry->output_name = sym_name;
5838 else
b715f643 5839 {
4f4faa4d
TP		 5840 if (sym_name == NULL)
5841 sym_name = "unnamed";
5842 stub_entry->output_name = (char *)
5843 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5844 + strlen (sym_name));
5845 if (stub_entry->output_name == NULL)
5846 {
5847 free (stub_name);
0955507f 5848 return NULL;
4f4faa4d 5849 }
b715f643 5850
4f4faa4d
TP		 5851 /* For historical reasons, use the existing names for ARM-to-Thumb and
5852 Thumb-to-ARM stubs. */
5853 r_type = ELF32_R_TYPE (irela->r_info);
5854 if ((r_type == (unsigned int) R_ARM_THM_CALL
5855 || r_type == (unsigned int) R_ARM_THM_JUMP24
5856 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5857 && branch_type == ST_BRANCH_TO_ARM)
5858 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5859 else if ((r_type == (unsigned int) R_ARM_CALL
5860 || r_type == (unsigned int) R_ARM_JUMP24)
5861 && branch_type == ST_BRANCH_TO_THUMB)
5862 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5863 else
5864 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5865 }
b715f643
TP		 5866
5867 *new_stub = TRUE;
0955507f 5868 return stub_entry;
b715f643
TP		 5869}
5870
4ba2ef8f
TP		 5871/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5872 gateway veneer to transition from non secure to secure state and create them
5873 accordingly.
5874
5875 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5876 defines the conditions that govern Secure Gateway veneer creation for a
5877 given symbol <SYM> as follows:
5878 - it has function type
5879 - it has non local binding
5880 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5881 same type, binding and value as <SYM> (called normal symbol).
5882 An entry function can handle secure state transition itself in which case
5883 its special symbol would have a different value from the normal symbol.
5884
5885 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5886 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5887 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5888 created.
4ba2ef8f 5889
0955507f 5890 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5891
5892static bfd_boolean
5893cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5894 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5895 int *cmse_stub_created)
4ba2ef8f
TP		 5896{
5897 const struct elf_backend_data *bed;
5898 Elf_Internal_Shdr *symtab_hdr;
5899 unsigned i, j, sym_count, ext_start;
5900 Elf_Internal_Sym *cmse_sym, *local_syms;
5901 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5902 enum arm_st_branch_type branch_type;
5903 char *sym_name, *lsym_name;
5904 bfd_vma sym_value;
5905 asection *section;
0955507f
TP		 5906 struct elf32_arm_stub_hash_entry *stub_entry;
5907 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5908
5909 bed = get_elf_backend_data (input_bfd);
5910 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5911 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5912 ext_start = symtab_hdr->sh_info;
5913 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5914 && out_attr[Tag_CPU_arch_profile].i == 'M');
5915
5916 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5917 if (local_syms == NULL)
5918 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5919 symtab_hdr->sh_info, 0, NULL, NULL,
5920 NULL);
5921 if (symtab_hdr->sh_info && local_syms == NULL)
5922 return FALSE;
5923
5924 /* Scan symbols. */
5925 for (i = 0; i < sym_count; i++)
5926 {
5927 cmse_invalid = FALSE;
5928
5929 if (i < ext_start)
5930 {
5931 cmse_sym = &local_syms[i];
5932 /* Not a special symbol. */
5933 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5934 continue;
5935 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5936 symtab_hdr->sh_link,
5937 cmse_sym->st_name);
5938 /* Special symbol with local binding. */
5939 cmse_invalid = TRUE;
5940 }
5941 else
5942 {
5943 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5944 sym_name = (char *) cmse_hash->root.root.root.string;
5945
5946 /* Not a special symbol. */
5947 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5948 continue;
5949
5950 /* Special symbol has incorrect binding or type. */
5951 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5952 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5953 || cmse_hash->root.type != STT_FUNC)
5954 cmse_invalid = TRUE;
5955 }
5956
5957 if (!is_v8m)
5958 {
90b6238f
AM		 5959 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5960 "ARMv8-M architecture or later"),
4eca0228 5961 input_bfd, sym_name);
4ba2ef8f
TP		 5962 is_v8m = TRUE; /* Avoid multiple warning. */
5963 ret = FALSE;
5964 }
5965
5966 if (cmse_invalid)
5967 {
90b6238f
AM		 5968 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5969 " a global or weak function symbol"),
4eca0228 5970 input_bfd, sym_name);
4ba2ef8f
TP		 5971 ret = FALSE;
5972 if (i < ext_start)
5973 continue;
5974 }
5975
5976 sym_name += strlen (CMSE_PREFIX);
5977 hash = (struct elf32_arm_link_hash_entry *)
5978 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5979
5980 /* No associated normal symbol or it is neither global nor weak. */
5981 if (!hash
5982 || (hash->root.root.type != bfd_link_hash_defined
5983 && hash->root.root.type != bfd_link_hash_defweak)
5984 || hash->root.type != STT_FUNC)
5985 {
5986 /* Initialize here to avoid warning about use of possibly
5987 uninitialized variable. */
5988 j = 0;
5989
5990 if (!hash)
5991 {
5992 /* Searching for a normal symbol with local binding. */
5993 for (; j < ext_start; j++)
5994 {
5995 lsym_name =
5996 bfd_elf_string_from_elf_section (input_bfd,
5997 symtab_hdr->sh_link,
5998 local_syms[j].st_name);
5999 if (!strcmp (sym_name, lsym_name))
6000 break;
6001 }
6002 }
6003
6004 if (hash || j < ext_start)
6005 {
4eca0228 6006 _bfd_error_handler
90b6238f
AM		 6007 (_("%pB: invalid standard symbol `%s'; it must be "
6008 "a global or weak function symbol"),
6009 input_bfd, sym_name);
4ba2ef8f
TP		 6010 }
6011 else
4eca0228 6012 _bfd_error_handler
90b6238f 6013 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6014 ret = FALSE;
6015 if (!hash)
6016 continue;
6017 }
6018
6019 sym_value = hash->root.root.u.def.value;
6020 section = hash->root.root.u.def.section;
6021
6022 if (cmse_hash->root.root.u.def.section != section)
6023 {
4eca0228 6024 _bfd_error_handler
90b6238f 6025 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6026 input_bfd, sym_name);
6027 ret = FALSE;
6028 }
6029 if (cmse_hash->root.root.u.def.value != sym_value)
6030 continue; /* Ignore: could be an entry function starting with SG. */
6031
6032 /* If this section is a link-once section that will be discarded, then
6033 don't create any stubs. */
6034 if (section->output_section == NULL)
6035 {
4eca0228 6036 _bfd_error_handler
90b6238f 6037 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6038 continue;
6039 }
6040
6041 if (hash->root.size == 0)
6042 {
4eca0228 6043 _bfd_error_handler
90b6238f 6044 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6045 ret = FALSE;
6046 }
6047
6048 if (!ret)
6049 continue;
6050 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6051 stub_entry
4ba2ef8f
TP		 6052 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6053 NULL, NULL, section, hash, sym_name,
6054 sym_value, branch_type, &new_stub);
6055
0955507f 6056 if (stub_entry == NULL)
4ba2ef8f
TP		 6057 ret = FALSE;
6058 else
6059 {
6060 BFD_ASSERT (new_stub);
0955507f 6061 (*cmse_stub_created)++;
4ba2ef8f
TP		 6062 }
6063 }
6064
6065 if (!symtab_hdr->contents)
6066 free (local_syms);
6067 return ret;
6068}
6069
0955507f
TP		 6070/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6071 code entry function, ie can be called from non secure code without using a
6072 veneer. */
6073
6074static bfd_boolean
6075cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6076{
42484486 6077 bfd_byte contents[4];
0955507f
TP		 6078 uint32_t first_insn;
6079 asection *section;
6080 file_ptr offset;
6081 bfd *abfd;
6082
6083 /* Defined symbol of function type. */
6084 if (hash->root.root.type != bfd_link_hash_defined
6085 && hash->root.root.type != bfd_link_hash_defweak)
6086 return FALSE;
6087 if (hash->root.type != STT_FUNC)
6088 return FALSE;
6089
6090 /* Read first instruction. */
6091 section = hash->root.root.u.def.section;
6092 abfd = section->owner;
6093 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6094 if (!bfd_get_section_contents (abfd, section, contents, offset,
6095 sizeof (contents)))
0955507f
TP		 6096 return FALSE;
6097
42484486
TP		 6098 first_insn = bfd_get_32 (abfd, contents);
6099
6100 /* Starts by SG instruction. */
0955507f
TP		 6101 return first_insn == 0xe97fe97f;
6102}
6103
6104/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6105 secure gateway veneers (ie. the veneers was not in the input import library)
6106 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6107
6108static bfd_boolean
6109arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6110{
6111 struct elf32_arm_stub_hash_entry *stub_entry;
6112 struct bfd_link_info *info;
6113
6114 /* Massage our args to the form they really have. */
6115 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6116 info = (struct bfd_link_info *) gen_info;
6117
6118 if (info->out_implib_bfd)
6119 return TRUE;
6120
6121 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6122 return TRUE;
6123
6124 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6125 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6126
6127 return TRUE;
6128}
6129
6130/* Set offset of each secure gateway veneers so that its address remain
6131 identical to the one in the input import library referred by
6132 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6133 (present in input import library but absent from the executable being
6134 linked) or if new veneers appeared and there is no output import library
6135 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6136 number of secure gateway veneers found in the input import library.
6137
6138 The function returns whether an error occurred. If no error occurred,
6139 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6140 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6141 veneer observed set for new veneers to be layed out after. */
6142
6143static bfd_boolean
6144set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6145 struct elf32_arm_link_hash_table *htab,
6146 int *cmse_stub_created)
6147{
6148 long symsize;
6149 char *sym_name;
6150 flagword flags;
6151 long i, symcount;
6152 bfd *in_implib_bfd;
6153 asection *stub_out_sec;
6154 bfd_boolean ret = TRUE;
6155 Elf_Internal_Sym *intsym;
6156 const char *out_sec_name;
6157 bfd_size_type cmse_stub_size;
6158 asymbol **sympp = NULL, *sym;
6159 struct elf32_arm_link_hash_entry *hash;
6160 const insn_sequence *cmse_stub_template;
6161 struct elf32_arm_stub_hash_entry *stub_entry;
6162 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6163 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6164 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6165
6166 /* No input secure gateway import library. */
6167 if (!htab->in_implib_bfd)
6168 return TRUE;
6169
6170 in_implib_bfd = htab->in_implib_bfd;
6171 if (!htab->cmse_implib)
6172 {
871b3ab2 6173 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6174 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6175 return FALSE;
6176 }
6177
6178 /* Get symbol table size. */
6179 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6180 if (symsize < 0)
6181 return FALSE;
6182
6183 /* Read in the input secure gateway import library's symbol table. */
6184 sympp = (asymbol **) xmalloc (symsize);
6185 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6186 if (symcount < 0)
6187 {
6188 ret = FALSE;
6189 goto free_sym_buf;
6190 }
6191
6192 htab->new_cmse_stub_offset = 0;
6193 cmse_stub_size =
6194 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6195 &cmse_stub_template,
6196 &cmse_stub_template_size);
6197 out_sec_name =
6198 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6199 stub_out_sec =
6200 bfd_get_section_by_name (htab->obfd, out_sec_name);
6201 if (stub_out_sec != NULL)
6202 cmse_stub_sec_vma = stub_out_sec->vma;
6203
6204 /* Set addresses of veneers mentionned in input secure gateway import
6205 library's symbol table. */
6206 for (i = 0; i < symcount; i++)
6207 {
6208 sym = sympp[i];
6209 flags = sym->flags;
6210 sym_name = (char *) bfd_asymbol_name (sym);
6211 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6212
6213 if (sym->section != bfd_abs_section_ptr
6214 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6215 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6216 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6217 != ST_BRANCH_TO_THUMB))
6218 {
90b6238f
AM		 6219 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6220 "symbol should be absolute, global and "
6221 "refer to Thumb functions"),
4eca0228 6222 in_implib_bfd, sym_name);
0955507f
TP		 6223 ret = FALSE;
6224 continue;
6225 }
6226
6227 veneer_value = bfd_asymbol_value (sym);
6228 stub_offset = veneer_value - cmse_stub_sec_vma;
6229 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6230 FALSE, FALSE);
6231 hash = (struct elf32_arm_link_hash_entry *)
6232 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6233
6234 /* Stub entry should have been created by cmse_scan or the symbol be of
6235 a secure function callable from non secure code. */
6236 if (!stub_entry && !hash)
6237 {
6238 bfd_boolean new_stub;
6239
4eca0228 6240 _bfd_error_handler
90b6238f 6241 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6242 hash = (struct elf32_arm_link_hash_entry *)
6243 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6244 stub_entry
6245 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6246 NULL, NULL, bfd_abs_section_ptr, hash,
6247 sym_name, veneer_value,
6248 ST_BRANCH_TO_THUMB, &new_stub);
6249 if (stub_entry == NULL)
6250 ret = FALSE;
6251 else
6252 {
6253 BFD_ASSERT (new_stub);
6254 new_cmse_stubs_created++;
6255 (*cmse_stub_created)++;
6256 }
6257 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6258 stub_entry->stub_offset = stub_offset;
6259 }
6260 /* Symbol found is not callable from non secure code. */
6261 else if (!stub_entry)
6262 {
6263 if (!cmse_entry_fct_p (hash))
6264 {
90b6238f 6265 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6266 sym_name);
0955507f
TP		 6267 ret = FALSE;
6268 }
6269 continue;
6270 }
6271 else
6272 {
6273 /* Only stubs for SG veneers should have been created. */
6274 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6275
6276 /* Check visibility hasn't changed. */
6277 if (!!(flags & BSF_GLOBAL)
6278 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6279 _bfd_error_handler
90b6238f 6280 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6281 sym_name);
6282
6283 stub_entry->stub_offset = stub_offset;
6284 }
6285
6286 /* Size should match that of a SG veneer. */
6287 if (intsym->st_size != cmse_stub_size)
6288 {
90b6238f 6289 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6290 in_implib_bfd, sym_name);
0955507f
TP		 6291 ret = FALSE;
6292 }
6293
6294 /* Previous veneer address is before current SG veneer section. */
6295 if (veneer_value < cmse_stub_sec_vma)
6296 {
6297 /* Avoid offset underflow. */
6298 if (stub_entry)
6299 stub_entry->stub_offset = 0;
6300 stub_offset = 0;
6301 ret = FALSE;
6302 }
6303
6304 /* Complain if stub offset not a multiple of stub size. */
6305 if (stub_offset % cmse_stub_size)
6306 {
4eca0228 6307 _bfd_error_handler
90b6238f
AM		 6308 (_("offset of veneer for entry function `%s' not a multiple of "
6309 "its size"), sym_name);
0955507f
TP		 6310 ret = FALSE;
6311 }
6312
6313 if (!ret)
6314 continue;
6315
6316 new_cmse_stubs_created--;
6317 if (veneer_value < cmse_stub_array_start)
6318 cmse_stub_array_start = veneer_value;
6319 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6320 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6321 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6322 }
6323
6324 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6325 {
6326 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6327 _bfd_error_handler
0955507f
TP		 6328 (_("new entry function(s) introduced but no output import library "
6329 "specified:"));
6330 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6331 }
6332
6333 if (cmse_stub_array_start != cmse_stub_sec_vma)
6334 {
4eca0228 6335 _bfd_error_handler
90b6238f 6336 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6337 out_sec_name);
6338 ret = FALSE;
6339 }
6340
6341free_sym_buf:
6342 free (sympp);
6343 return ret;
6344}
6345
906e58ca
NC		 6346/* Determine and set the size of the stub section for a final link.
6347
6348 The basic idea here is to examine all the relocations looking for
6349 PC-relative calls to a target that is unreachable with a "bl"
6350 instruction. */
6351
6352bfd_boolean
6353elf32_arm_size_stubs (bfd *output_bfd,
6354 bfd *stub_bfd,
6355 struct bfd_link_info *info,
6356 bfd_signed_vma group_size,
7a89b94e 6357 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6358 asection *,
7a89b94e 6359 unsigned int),
906e58ca
NC		 6360 void (*layout_sections_again) (void))
6361{
0955507f 6362 bfd_boolean ret = TRUE;
4ba2ef8f 6363 obj_attribute *out_attr;
0955507f 6364 int cmse_stub_created = 0;
906e58ca 6365 bfd_size_type stub_group_size;
4ba2ef8f 6366 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6367 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6368 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6369 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6370 struct a8_erratum_reloc *a8_relocs = NULL;
6371 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6372
4dfe6ac6
NC		 6373 if (htab == NULL)
6374 return FALSE;
6375
48229727
JB		 6376 if (htab->fix_cortex_a8)
6377 {
21d799b5 6378 a8_fixes = (struct a8_erratum_fix *)
99059e56 6379 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6380 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6381 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6382 }
906e58ca
NC		 6383
6384 /* Propagate mach to stub bfd, because it may not have been
6385 finalized when we created stub_bfd. */
6386 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6387 bfd_get_mach (output_bfd));
6388
6389 /* Stash our params away. */
6390 htab->stub_bfd = stub_bfd;
6391 htab->add_stub_section = add_stub_section;
6392 htab->layout_sections_again = layout_sections_again;
07d72278 6393 stubs_always_after_branch = group_size < 0;
48229727 6394
4ba2ef8f
TP		 6395 out_attr = elf_known_obj_attributes_proc (output_bfd);
6396 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6397
48229727
JB		 6398 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6399 as the first half of a 32-bit branch straddling two 4K pages. This is a
6400 crude way of enforcing that. */
6401 if (htab->fix_cortex_a8)
6402 stubs_always_after_branch = 1;
6403
906e58ca
NC		 6404 if (group_size < 0)
6405 stub_group_size = -group_size;
6406 else
6407 stub_group_size = group_size;
6408
6409 if (stub_group_size == 1)
6410 {
6411 /* Default values. */
6412 /* Thumb branch range is +-4MB has to be used as the default
6413 maximum size (a given section can contain both ARM and Thumb
6414 code, so the worst case has to be taken into account).
6415
6416 This value is 24K less than that, which allows for 2025
6417 12-byte stubs. If we exceed that, then we will fail to link.
6418 The user will have to relink with an explicit group size
6419 option. */
6420 stub_group_size = 4170000;
6421 }
6422
07d72278 6423 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6424
3ae046cc
NS		 6425 /* If we're applying the cortex A8 fix, we need to determine the
6426 program header size now, because we cannot change it later --
6427 that could alter section placements. Notice the A8 erratum fix
6428 ends up requiring the section addresses to remain unchanged
6429 modulo the page size. That's something we cannot represent
6430 inside BFD, and we don't want to force the section alignment to
6431 be the page size. */
6432 if (htab->fix_cortex_a8)
6433 (*htab->layout_sections_again) ();
6434
906e58ca
NC		 6435 while (1)
6436 {
6437 bfd *input_bfd;
6438 unsigned int bfd_indx;
6439 asection *stub_sec;
d7c5bd02 6440 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6441 bfd_boolean stub_changed = FALSE;
6442 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6443
48229727 6444 num_a8_fixes = 0;
906e58ca
NC		 6445 for (input_bfd = info->input_bfds, bfd_indx = 0;
6446 input_bfd != NULL;
c72f2fb2 6447 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6448 {
6449 Elf_Internal_Shdr *symtab_hdr;
6450 asection *section;
6451 Elf_Internal_Sym *local_syms = NULL;
6452
8c246a60
AM		 6453 if (!is_arm_elf (input_bfd)
6454 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0)
99059e56 6455 continue;
adbcc655 6456
48229727
JB		 6457 num_a8_relocs = 0;
6458
906e58ca
NC		 6459 /* We'll need the symbol table in a second. */
6460 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6461 if (symtab_hdr->sh_info == 0)
6462 continue;
6463
4ba2ef8f
TP		 6464 /* Limit scan of symbols to object file whose profile is
6465 Microcontroller to not hinder performance in the general case. */
6466 if (m_profile && first_veneer_scan)
6467 {
6468 struct elf_link_hash_entry **sym_hashes;
6469
6470 sym_hashes = elf_sym_hashes (input_bfd);
6471 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6472 &cmse_stub_created))
4ba2ef8f 6473 goto error_ret_free_local;
0955507f
TP		 6474
6475 if (cmse_stub_created != 0)
6476 stub_changed = TRUE;
4ba2ef8f
TP		 6477 }
6478
906e58ca
NC		 6479 /* Walk over each section attached to the input bfd. */
6480 for (section = input_bfd->sections;
6481 section != NULL;
6482 section = section->next)
6483 {
6484 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6485
6486 /* If there aren't any relocs, then there's nothing more
6487 to do. */
6488 if ((section->flags & SEC_RELOC) == 0
6489 || section->reloc_count == 0
6490 || (section->flags & SEC_CODE) == 0)
6491 continue;
6492
6493 /* If this section is a link-once section that will be
6494 discarded, then don't create any stubs. */
6495 if (section->output_section == NULL
6496 || section->output_section->owner != output_bfd)
6497 continue;
6498
6499 /* Get the relocs. */
6500 internal_relocs
6501 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6502 NULL, info->keep_memory);
6503 if (internal_relocs == NULL)
6504 goto error_ret_free_local;
6505
6506 /* Now examine each relocation. */
6507 irela = internal_relocs;
6508 irelaend = irela + section->reloc_count;
6509 for (; irela < irelaend; irela++)
6510 {
6511 unsigned int r_type, r_indx;
906e58ca
NC		 6512 asection *sym_sec;
6513 bfd_vma sym_value;
6514 bfd_vma destination;
6515 struct elf32_arm_link_hash_entry *hash;
7413f23f 6516 const char *sym_name;
34e77a92 6517 unsigned char st_type;
35fc36a8 6518 enum arm_st_branch_type branch_type;
48229727 6519 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6520
6521 r_type = ELF32_R_TYPE (irela->r_info);
6522 r_indx = ELF32_R_SYM (irela->r_info);
6523
6524 if (r_type >= (unsigned int) R_ARM_max)
6525 {
6526 bfd_set_error (bfd_error_bad_value);
6527 error_ret_free_internal:
6528 if (elf_section_data (section)->relocs == NULL)
6529 free (internal_relocs);
15dd01b1
TP		 6530 /* Fall through. */
6531 error_ret_free_local:
6532 if (local_syms != NULL
6533 && (symtab_hdr->contents
6534 != (unsigned char *) local_syms))
6535 free (local_syms);
6536 return FALSE;
906e58ca 6537 }
b38cadfb 6538
0855e32b
NS		 6539 hash = NULL;
6540 if (r_indx >= symtab_hdr->sh_info)
6541 hash = elf32_arm_hash_entry
6542 (elf_sym_hashes (input_bfd)
6543 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6544
0855e32b
NS		 6545 /* Only look for stubs on branch instructions, or
6546 non-relaxed TLSCALL */
906e58ca 6547 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6548 && (r_type != (unsigned int) R_ARM_THM_CALL)
6549 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6550 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6551 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6552 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6553 && (r_type != (unsigned int) R_ARM_PLT32)
6554 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6555 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6556 && r_type == elf32_arm_tls_transition
6557 (info, r_type, &hash->root)
6558 && ((hash ? hash->tls_type
6559 : (elf32_arm_local_got_tls_type
6560 (input_bfd)[r_indx]))
6561 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6562 continue;
6563
6564 /* Now determine the call target, its name, value,
6565 section. */
6566 sym_sec = NULL;
6567 sym_value = 0;
6568 destination = 0;
7413f23f 6569 sym_name = NULL;
b38cadfb 6570
0855e32b
NS		 6571 if (r_type == (unsigned int) R_ARM_TLS_CALL
6572 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6573 {
6574 /* A non-relaxed TLS call. The target is the
6575 plt-resident trampoline and nothing to do
6576 with the symbol. */
6577 BFD_ASSERT (htab->tls_trampoline > 0);
6578 sym_sec = htab->root.splt;
6579 sym_value = htab->tls_trampoline;
6580 hash = 0;
34e77a92 6581 st_type = STT_FUNC;
35fc36a8 6582 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6583 }
6584 else if (!hash)
906e58ca
NC		 6585 {
6586 /* It's a local symbol. */
6587 Elf_Internal_Sym *sym;
906e58ca
NC		 6588
6589 if (local_syms == NULL)
6590 {
6591 local_syms
6592 = (Elf_Internal_Sym *) symtab_hdr->contents;
6593 if (local_syms == NULL)
6594 local_syms
6595 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6596 symtab_hdr->sh_info, 0,
6597 NULL, NULL, NULL);
6598 if (local_syms == NULL)
6599 goto error_ret_free_internal;
6600 }
6601
6602 sym = local_syms + r_indx;
f6d250ce
TS		 6603 if (sym->st_shndx == SHN_UNDEF)
6604 sym_sec = bfd_und_section_ptr;
6605 else if (sym->st_shndx == SHN_ABS)
6606 sym_sec = bfd_abs_section_ptr;
6607 else if (sym->st_shndx == SHN_COMMON)
6608 sym_sec = bfd_com_section_ptr;
6609 else
6610 sym_sec =
6611 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6612
ffcb4889
NS		 6613 if (!sym_sec)
6614 /* This is an undefined symbol. It can never
6a631e86 6615 be resolved. */
ffcb4889 6616 continue;
fe33d2fa 6617
906e58ca
NC		 6618 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6619 sym_value = sym->st_value;
6620 destination = (sym_value + irela->r_addend
6621 + sym_sec->output_offset
6622 + sym_sec->output_section->vma);
34e77a92 6623 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6624 branch_type =
6625 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6626 sym_name
6627 = bfd_elf_string_from_elf_section (input_bfd,
6628 symtab_hdr->sh_link,
6629 sym->st_name);
906e58ca
NC		 6630 }
6631 else
6632 {
6633 /* It's an external symbol. */
906e58ca
NC		 6634 while (hash->root.root.type == bfd_link_hash_indirect
6635 || hash->root.root.type == bfd_link_hash_warning)
6636 hash = ((struct elf32_arm_link_hash_entry *)
6637 hash->root.root.u.i.link);
6638
6639 if (hash->root.root.type == bfd_link_hash_defined
6640 || hash->root.root.type == bfd_link_hash_defweak)
6641 {
6642 sym_sec = hash->root.root.u.def.section;
6643 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6644
6645 struct elf32_arm_link_hash_table *globals =
6646 elf32_arm_hash_table (info);
6647
6648 /* For a destination in a shared library,
6649 use the PLT stub as target address to
6650 decide whether a branch stub is
6651 needed. */
4dfe6ac6 6652 if (globals != NULL
362d30a1 6653 && globals->root.splt != NULL
4dfe6ac6 6654 && hash != NULL
022f8312
CL		 6655 && hash->root.plt.offset != (bfd_vma) -1)
6656 {
362d30a1 6657 sym_sec = globals->root.splt;
022f8312
CL		 6658 sym_value = hash->root.plt.offset;
6659 if (sym_sec->output_section != NULL)
6660 destination = (sym_value
6661 + sym_sec->output_offset
6662 + sym_sec->output_section->vma);
6663 }
6664 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6665 destination = (sym_value + irela->r_addend
6666 + sym_sec->output_offset
6667 + sym_sec->output_section->vma);
6668 }
69c5861e
CL		 6669 else if ((hash->root.root.type == bfd_link_hash_undefined)
6670 || (hash->root.root.type == bfd_link_hash_undefweak))
6671 {
6672 /* For a shared library, use the PLT stub as
6673 target address to decide whether a long
6674 branch stub is needed.
6675 For absolute code, they cannot be handled. */
6676 struct elf32_arm_link_hash_table *globals =
6677 elf32_arm_hash_table (info);
6678
4dfe6ac6 6679 if (globals != NULL
362d30a1 6680 && globals->root.splt != NULL
4dfe6ac6 6681 && hash != NULL
69c5861e
CL		 6682 && hash->root.plt.offset != (bfd_vma) -1)
6683 {
362d30a1 6684 sym_sec = globals->root.splt;
69c5861e
CL		 6685 sym_value = hash->root.plt.offset;
6686 if (sym_sec->output_section != NULL)
6687 destination = (sym_value
6688 + sym_sec->output_offset
6689 + sym_sec->output_section->vma);
6690 }
6691 else
6692 continue;
6693 }
906e58ca
NC		 6694 else
6695 {
6696 bfd_set_error (bfd_error_bad_value);
6697 goto error_ret_free_internal;
6698 }
34e77a92 6699 st_type = hash->root.type;
39d911fc
TP		 6700 branch_type =
6701 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6702 sym_name = hash->root.root.root.string;
906e58ca
NC		 6703 }
6704
48229727 6705 do
7413f23f 6706 {
b715f643 6707 bfd_boolean new_stub;
0955507f 6708 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6709
48229727
JB		 6710 /* Determine what (if any) linker stub is needed. */
6711 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6712 st_type, &branch_type,
6713 hash, destination, sym_sec,
48229727
JB		 6714 input_bfd, sym_name);
6715 if (stub_type == arm_stub_none)
6716 break;
6717
48229727
JB		 6718 /* We've either created a stub for this reloc already,
6719 or we are about to. */
0955507f 6720 stub_entry =
b715f643
TP		 6721 elf32_arm_create_stub (htab, stub_type, section, irela,
6722 sym_sec, hash,
6723 (char *) sym_name, sym_value,
6724 branch_type, &new_stub);
7413f23f 6725
0955507f 6726 created_stub = stub_entry != NULL;
b715f643
TP		 6727 if (!created_stub)
6728 goto error_ret_free_internal;
6729 else if (!new_stub)
6730 break;
99059e56 6731 else
b715f643 6732 stub_changed = TRUE;
99059e56
RM		 6733 }
6734 while (0);
6735
6736 /* Look for relocations which might trigger Cortex-A8
6737 erratum. */
6738 if (htab->fix_cortex_a8
6739 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6740 || r_type == (unsigned int) R_ARM_THM_JUMP19
6741 || r_type == (unsigned int) R_ARM_THM_CALL
6742 || r_type == (unsigned int) R_ARM_THM_XPC22))
6743 {
6744 bfd_vma from = section->output_section->vma
6745 + section->output_offset
6746 + irela->r_offset;
6747
6748 if ((from & 0xfff) == 0xffe)
6749 {
6750 /* Found a candidate. Note we haven't checked the
6751 destination is within 4K here: if we do so (and
6752 don't create an entry in a8_relocs) we can't tell
6753 that a branch should have been relocated when
6754 scanning later. */
6755 if (num_a8_relocs == a8_reloc_table_size)
6756 {
6757 a8_reloc_table_size *= 2;
6758 a8_relocs = (struct a8_erratum_reloc *)
6759 bfd_realloc (a8_relocs,
6760 sizeof (struct a8_erratum_reloc)
6761 * a8_reloc_table_size);
6762 }
6763
6764 a8_relocs[num_a8_relocs].from = from;
6765 a8_relocs[num_a8_relocs].destination = destination;
6766 a8_relocs[num_a8_relocs].r_type = r_type;
6767 a8_relocs[num_a8_relocs].branch_type = branch_type;
6768 a8_relocs[num_a8_relocs].sym_name = sym_name;
6769 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6770 a8_relocs[num_a8_relocs].hash = hash;
6771
6772 num_a8_relocs++;
6773 }
6774 }
906e58ca
NC		 6775 }
6776
99059e56
RM		 6777 /* We're done with the internal relocs, free them. */
6778 if (elf_section_data (section)->relocs == NULL)
6779 free (internal_relocs);
6780 }
48229727 6781
99059e56 6782 if (htab->fix_cortex_a8)
48229727 6783 {
99059e56
RM		 6784 /* Sort relocs which might apply to Cortex-A8 erratum. */
6785 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6786 sizeof (struct a8_erratum_reloc),
99059e56 6787 &a8_reloc_compare);
48229727 6788
99059e56
RM		 6789 /* Scan for branches which might trigger Cortex-A8 erratum. */
6790 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6791 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6792 a8_relocs, num_a8_relocs,
6793 prev_num_a8_fixes, &stub_changed)
6794 != 0)
48229727 6795 goto error_ret_free_local;
5e681ec4 6796 }
7f991970
AM		 6797
6798 if (local_syms != NULL
6799 && symtab_hdr->contents != (unsigned char *) local_syms)
6800 {
6801 if (!info->keep_memory)
6802 free (local_syms);
6803 else
6804 symtab_hdr->contents = (unsigned char *) local_syms;
6805 }
5e681ec4
PB		 6806 }
6807
0955507f
TP		 6808 if (first_veneer_scan
6809 && !set_cmse_veneer_addr_from_implib (info, htab,
6810 &cmse_stub_created))
6811 ret = FALSE;
6812
eb7c4339 6813 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6814 stub_changed = TRUE;
48229727 6815
906e58ca
NC		 6816 if (!stub_changed)
6817 break;
5e681ec4 6818
906e58ca
NC		 6819 /* OK, we've added some stubs. Find out the new size of the
6820 stub sections. */
6821 for (stub_sec = htab->stub_bfd->sections;
6822 stub_sec != NULL;
6823 stub_sec = stub_sec->next)
3e6b1042
DJ		 6824 {
6825 /* Ignore non-stub sections. */
6826 if (!strstr (stub_sec->name, STUB_SUFFIX))
6827 continue;
6828
6829 stub_sec->size = 0;
6830 }
b34b2d70 6831
0955507f
TP		 6832 /* Add new SG veneers after those already in the input import
6833 library. */
6834 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6835 stub_type++)
6836 {
6837 bfd_vma *start_offset_p;
6838 asection **stub_sec_p;
6839
6840 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6841 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6842 if (start_offset_p == NULL)
6843 continue;
6844
6845 BFD_ASSERT (stub_sec_p != NULL);
6846 if (*stub_sec_p != NULL)
6847 (*stub_sec_p)->size = *start_offset_p;
6848 }
6849
d7c5bd02 6850 /* Compute stub section size, considering padding. */
906e58ca 6851 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6852 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6853 stub_type++)
6854 {
6855 int size, padding;
6856 asection **stub_sec_p;
6857
6858 padding = arm_dedicated_stub_section_padding (stub_type);
6859 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6860 /* Skip if no stub input section or no stub section padding
6861 required. */
6862 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6863 continue;
6864 /* Stub section padding required but no dedicated section. */
6865 BFD_ASSERT (stub_sec_p);
6866
6867 size = (*stub_sec_p)->size;
6868 size = (size + padding - 1) & ~(padding - 1);
6869 (*stub_sec_p)->size = size;
6870 }
906e58ca 6871
48229727
JB		 6872 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6873 if (htab->fix_cortex_a8)
99059e56
RM		 6874 for (i = 0; i < num_a8_fixes; i++)
6875 {
48229727 6876 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6877 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6878
6879 if (stub_sec == NULL)
7f991970 6880 return FALSE;
48229727 6881
99059e56
RM		 6882 stub_sec->size
6883 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6884 NULL);
6885 }
48229727
JB		 6886
6887
906e58ca
NC		 6888 /* Ask the linker to do its stuff. */
6889 (*htab->layout_sections_again) ();
4ba2ef8f 6890 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6891 }
6892
48229727
JB		 6893 /* Add stubs for Cortex-A8 erratum fixes now. */
6894 if (htab->fix_cortex_a8)
6895 {
6896 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6897 {
6898 struct elf32_arm_stub_hash_entry *stub_entry;
6899 char *stub_name = a8_fixes[i].stub_name;
6900 asection *section = a8_fixes[i].section;
6901 unsigned int section_id = a8_fixes[i].section->id;
6902 asection *link_sec = htab->stub_group[section_id].link_sec;
6903 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6904 const insn_sequence *template_sequence;
6905 int template_size, size = 0;
6906
6907 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6908 TRUE, FALSE);
6909 if (stub_entry == NULL)
6910 {
871b3ab2 6911 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6912 section->owner, stub_name);
99059e56
RM		 6913 return FALSE;
6914 }
6915
6916 stub_entry->stub_sec = stub_sec;
0955507f 6917 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6918 stub_entry->id_sec = link_sec;
6919 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6920 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6921 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6922 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6923 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6924 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6925
99059e56
RM		 6926 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6927 &template_sequence,
6928 &template_size);
48229727 6929
99059e56
RM		 6930 stub_entry->stub_size = size;
6931 stub_entry->stub_template = template_sequence;
6932 stub_entry->stub_template_size = template_size;
6933 }
48229727
JB		 6934
6935 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6936 elf32_arm_write_section(). */
48229727
JB		 6937 htab->a8_erratum_fixes = a8_fixes;
6938 htab->num_a8_erratum_fixes = num_a8_fixes;
6939 }
6940 else
6941 {
6942 htab->a8_erratum_fixes = NULL;
6943 htab->num_a8_erratum_fixes = 0;
6944 }
0955507f 6945 return ret;
5e681ec4
PB		 6946}
6947
906e58ca
NC		 6948/* Build all the stubs associated with the current output file. The
6949 stubs are kept in a hash table attached to the main linker hash
6950 table. We also set up the .plt entries for statically linked PIC
6951 functions here. This function is called via arm_elf_finish in the
6952 linker. */
252b5132 6953
906e58ca
NC		 6954bfd_boolean
6955elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6956{
906e58ca
NC		 6957 asection *stub_sec;
6958 struct bfd_hash_table *table;
0955507f 6959 enum elf32_arm_stub_type stub_type;
906e58ca 6960 struct elf32_arm_link_hash_table *htab;
252b5132 6961
906e58ca 6962 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6963 if (htab == NULL)
6964 return FALSE;
252b5132 6965
906e58ca
NC		 6966 for (stub_sec = htab->stub_bfd->sections;
6967 stub_sec != NULL;
6968 stub_sec = stub_sec->next)
252b5132 6969 {
906e58ca
NC		 6970 bfd_size_type size;
6971
8029a119 6972 /* Ignore non-stub sections. */
906e58ca
NC		 6973 if (!strstr (stub_sec->name, STUB_SUFFIX))
6974 continue;
6975
d7c5bd02 6976 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6977 must at least be done for stub section requiring padding and for SG
6978 veneers to ensure that a non secure code branching to a removed SG
6979 veneer causes an error. */
906e58ca 6980 size = stub_sec->size;
21d799b5 6981 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6982 if (stub_sec->contents == NULL && size != 0)
6983 return FALSE;
0955507f 6984
906e58ca 6985 stub_sec->size = 0;
252b5132
RH		 6986 }
6987
0955507f
TP		 6988 /* Add new SG veneers after those already in the input import library. */
6989 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6990 {
6991 bfd_vma *start_offset_p;
6992 asection **stub_sec_p;
6993
6994 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6995 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6996 if (start_offset_p == NULL)
6997 continue;
6998
6999 BFD_ASSERT (stub_sec_p != NULL);
7000 if (*stub_sec_p != NULL)
7001 (*stub_sec_p)->size = *start_offset_p;
7002 }
7003
906e58ca
NC		 7004 /* Build the stubs as directed by the stub hash table. */
7005 table = &htab->stub_hash_table;
7006 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7007 if (htab->fix_cortex_a8)
7008 {
7009 /* Place the cortex a8 stubs last. */
7010 htab->fix_cortex_a8 = -1;
7011 bfd_hash_traverse (table, arm_build_one_stub, info);
7012 }
252b5132 7013
906e58ca 7014 return TRUE;
252b5132
RH		 7015}
7016
9b485d32
NC		 7017/* Locate the Thumb encoded calling stub for NAME. */
7018
252b5132 7019static struct elf_link_hash_entry *
57e8b36a
NC		 7020find_thumb_glue (struct bfd_link_info *link_info,
7021 const char *name,
f2a9dd69 7022 char **error_message)
252b5132
RH		 7023{
7024 char *tmp_name;
7025 struct elf_link_hash_entry *hash;
7026 struct elf32_arm_link_hash_table *hash_table;
7027
7028 /* We need a pointer to the armelf specific hash table. */
7029 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7030 if (hash_table == NULL)
7031 return NULL;
252b5132 7032
21d799b5 7033 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7034 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7035
7036 BFD_ASSERT (tmp_name);
7037
7038 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7039
7040 hash = elf_link_hash_lookup
b34976b6 7041 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7042
b1657152 7043 if (hash == NULL
90b6238f
AM		 7044 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7045 "Thumb", tmp_name, name) == -1)
b1657152 7046 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7047
7048 free (tmp_name);
7049
7050 return hash;
7051}
7052
9b485d32
NC		 7053/* Locate the ARM encoded calling stub for NAME. */
7054
252b5132 7055static struct elf_link_hash_entry *
57e8b36a
NC		 7056find_arm_glue (struct bfd_link_info *link_info,
7057 const char *name,
f2a9dd69 7058 char **error_message)
252b5132
RH		 7059{
7060 char *tmp_name;
7061 struct elf_link_hash_entry *myh;
7062 struct elf32_arm_link_hash_table *hash_table;
7063
7064 /* We need a pointer to the elfarm specific hash table. */
7065 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7066 if (hash_table == NULL)
7067 return NULL;
252b5132 7068
21d799b5 7069 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7070 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7071
7072 BFD_ASSERT (tmp_name);
7073
7074 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7075
7076 myh = elf_link_hash_lookup
b34976b6 7077 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7078
b1657152 7079 if (myh == NULL
90b6238f
AM		 7080 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7081 "ARM", tmp_name, name) == -1)
b1657152 7082 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7083
7084 free (tmp_name);
7085
7086 return myh;
7087}
7088
8f6277f5 7089/* ARM->Thumb glue (static images):
252b5132
RH		 7090
7091 .arm
7092 __func_from_arm:
7093 ldr r12, __func_addr
7094 bx r12
7095 __func_addr:
906e58ca 7096 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7097
26079076
PB		 7098 (v5t static images)
7099 .arm
7100 __func_from_arm:
7101 ldr pc, __func_addr
7102 __func_addr:
906e58ca 7103 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7104
8f6277f5
PB		 7105 (relocatable images)
7106 .arm
7107 __func_from_arm:
7108 ldr r12, __func_offset
7109 add r12, r12, pc
7110 bx r12
7111 __func_offset:
8029a119 7112 .word func - . */
8f6277f5
PB		 7113
7114#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7115static const insn32 a2t1_ldr_insn = 0xe59fc000;
7116static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7117static const insn32 a2t3_func_addr_insn = 0x00000001;
7118
26079076
PB		 7119#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7120static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7121static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7122
8f6277f5
PB		 7123#define ARM2THUMB_PIC_GLUE_SIZE 16
7124static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7125static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7126static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7127
07d6d2b8 7128/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7129
07d6d2b8
AM		 7130 .thumb .thumb
7131 .align 2 .align 2
7132 __func_from_thumb: __func_from_thumb:
7133 bx pc push {r6, lr}
7134 nop ldr r6, __func_addr
7135 .arm mov lr, pc
7136 b func bx r6
99059e56
RM		 7137 .arm
7138 ;; back_to_thumb
7139 ldmia r13! {r6, lr}
7140 bx lr
7141 __func_addr:
07d6d2b8 7142 .word func */
252b5132
RH		 7143
7144#define THUMB2ARM_GLUE_SIZE 8
7145static const insn16 t2a1_bx_pc_insn = 0x4778;
7146static const insn16 t2a2_noop_insn = 0x46c0;
7147static const insn32 t2a3_b_insn = 0xea000000;
7148
c7b8f16e 7149#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7150#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7151#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7152
845b51d6
PB		 7153#define ARM_BX_VENEER_SIZE 12
7154static const insn32 armbx1_tst_insn = 0xe3100001;
7155static const insn32 armbx2_moveq_insn = 0x01a0f000;
7156static const insn32 armbx3_bx_insn = 0xe12fff10;
7157
7e392df6 7158#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7159static void
7160arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7161{
7162 asection * s;
8029a119 7163 bfd_byte * contents;
252b5132 7164
8029a119 7165 if (size == 0)
3e6b1042
DJ		 7166 {
7167 /* Do not include empty glue sections in the output. */
7168 if (abfd != NULL)
7169 {
3d4d4302 7170 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7171 if (s != NULL)
7172 s->flags |= SEC_EXCLUDE;
7173 }
7174 return;
7175 }
252b5132 7176
8029a119 7177 BFD_ASSERT (abfd != NULL);
252b5132 7178
3d4d4302 7179 s = bfd_get_linker_section (abfd, name);
8029a119 7180 BFD_ASSERT (s != NULL);
252b5132 7181
21d799b5 7182 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 7183
8029a119
NC		 7184 BFD_ASSERT (s->size == size);
7185 s->contents = contents;
7186}
906e58ca 7187
8029a119
NC		 7188bfd_boolean
7189bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7190{
7191 struct elf32_arm_link_hash_table * globals;
906e58ca 7192
8029a119
NC		 7193 globals = elf32_arm_hash_table (info);
7194 BFD_ASSERT (globals != NULL);
906e58ca 7195
8029a119
NC		 7196 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7197 globals->arm_glue_size,
7198 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7199
8029a119
NC		 7200 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7201 globals->thumb_glue_size,
7202 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7203
8029a119
NC		 7204 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7205 globals->vfp11_erratum_glue_size,
7206 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7207
a504d23a
LA		 7208 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7209 globals->stm32l4xx_erratum_glue_size,
7210 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7211
8029a119
NC		 7212 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7213 globals->bx_glue_size,
845b51d6
PB		 7214 ARM_BX_GLUE_SECTION_NAME);
7215
b34976b6 7216 return TRUE;
252b5132
RH		 7217}
7218
a4fd1a8e 7219/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7220 returns the symbol identifying the stub. */
7221
a4fd1a8e 7222static struct elf_link_hash_entry *
57e8b36a
NC		 7223record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7224 struct elf_link_hash_entry * h)
252b5132
RH		 7225{
7226 const char * name = h->root.root.string;
63b0f745 7227 asection * s;
252b5132
RH		 7228 char * tmp_name;
7229 struct elf_link_hash_entry * myh;
14a793b2 7230 struct bfd_link_hash_entry * bh;
252b5132 7231 struct elf32_arm_link_hash_table * globals;
dc810e39 7232 bfd_vma val;
2f475487 7233 bfd_size_type size;
252b5132
RH		 7234
7235 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7236 BFD_ASSERT (globals != NULL);
7237 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7238
3d4d4302 7239 s = bfd_get_linker_section
252b5132
RH		 7240 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7241
252b5132
RH		 7242 BFD_ASSERT (s != NULL);
7243
21d799b5 7244 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7245 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7246
7247 BFD_ASSERT (tmp_name);
7248
7249 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7250
7251 myh = elf_link_hash_lookup
b34976b6 7252 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7253
7254 if (myh != NULL)
7255 {
9b485d32 7256 /* We've already seen this guy. */
252b5132 7257 free (tmp_name);
a4fd1a8e 7258 return myh;
252b5132
RH		 7259 }
7260
57e8b36a
NC		 7261 /* The only trick here is using hash_table->arm_glue_size as the value.
7262 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7263 putting it. The +1 on the value marks that the stub has not been
7264 output yet - not that it is a Thumb function. */
14a793b2 7265 bh = NULL;
dc810e39
AM		 7266 val = globals->arm_glue_size + 1;
7267 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7268 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7269 NULL, TRUE, FALSE, &bh);
252b5132 7270
b7693d02
DJ		 7271 myh = (struct elf_link_hash_entry *) bh;
7272 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7273 myh->forced_local = 1;
7274
252b5132
RH		 7275 free (tmp_name);
7276
0e1862bb
L		 7277 if (bfd_link_pic (link_info)
7278 || globals->root.is_relocatable_executable
27e55c4d 7279 || globals->pic_veneer)
2f475487 7280 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7281 else if (globals->use_blx)
7282 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7283 else
2f475487
AM		 7284 size = ARM2THUMB_STATIC_GLUE_SIZE;
7285
7286 s->size += size;
7287 globals->arm_glue_size += size;
252b5132 7288
a4fd1a8e 7289 return myh;
252b5132
RH		 7290}
7291
845b51d6
PB		 7292/* Allocate space for ARMv4 BX veneers. */
7293
7294static void
7295record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7296{
7297 asection * s;
7298 struct elf32_arm_link_hash_table *globals;
7299 char *tmp_name;
7300 struct elf_link_hash_entry *myh;
7301 struct bfd_link_hash_entry *bh;
7302 bfd_vma val;
7303
7304 /* BX PC does not need a veneer. */
7305 if (reg == 15)
7306 return;
7307
7308 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7309 BFD_ASSERT (globals != NULL);
7310 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7311
7312 /* Check if this veneer has already been allocated. */
7313 if (globals->bx_glue_offset[reg])
7314 return;
7315
3d4d4302 7316 s = bfd_get_linker_section
845b51d6
PB		 7317 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7318
7319 BFD_ASSERT (s != NULL);
7320
7321 /* Add symbol for veneer. */
21d799b5
NC		 7322 tmp_name = (char *)
7323 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7324
845b51d6 7325 BFD_ASSERT (tmp_name);
906e58ca 7326
845b51d6 7327 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7328
845b51d6
PB		 7329 myh = elf_link_hash_lookup
7330 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7331
845b51d6 7332 BFD_ASSERT (myh == NULL);
906e58ca 7333
845b51d6
PB		 7334 bh = NULL;
7335 val = globals->bx_glue_size;
7336 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7337 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7338 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7339
7340 myh = (struct elf_link_hash_entry *) bh;
7341 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7342 myh->forced_local = 1;
7343
7344 s->size += ARM_BX_VENEER_SIZE;
7345 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7346 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7347}
7348
7349
c7b8f16e
JB		 7350/* Add an entry to the code/data map for section SEC. */
7351
7352static void
7353elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7354{
7355 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7356 unsigned int newidx;
906e58ca 7357
c7b8f16e
JB		 7358 if (sec_data->map == NULL)
7359 {
21d799b5 7360 sec_data->map = (elf32_arm_section_map *)
99059e56 7361 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7362 sec_data->mapcount = 0;
7363 sec_data->mapsize = 1;
7364 }
906e58ca 7365
c7b8f16e 7366 newidx = sec_data->mapcount++;
906e58ca 7367
c7b8f16e
JB		 7368 if (sec_data->mapcount > sec_data->mapsize)
7369 {
7370 sec_data->mapsize *= 2;
21d799b5 7371 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7372 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7373 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7374 }
7375
7376 if (sec_data->map)
7377 {
7378 sec_data->map[newidx].vma = vma;
7379 sec_data->map[newidx].type = type;
c7b8f16e 7380 }
c7b8f16e
JB		 7381}
7382
7383
7384/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7385 veneers are handled for now. */
7386
7387static bfd_vma
7388record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7389 elf32_vfp11_erratum_list *branch,
7390 bfd *branch_bfd,
7391 asection *branch_sec,
7392 unsigned int offset)
c7b8f16e
JB		 7393{
7394 asection *s;
7395 struct elf32_arm_link_hash_table *hash_table;
7396 char *tmp_name;
7397 struct elf_link_hash_entry *myh;
7398 struct bfd_link_hash_entry *bh;
7399 bfd_vma val;
7400 struct _arm_elf_section_data *sec_data;
c7b8f16e 7401 elf32_vfp11_erratum_list *newerr;
906e58ca 7402
c7b8f16e 7403 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7404 BFD_ASSERT (hash_table != NULL);
7405 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7406
3d4d4302 7407 s = bfd_get_linker_section
c7b8f16e 7408 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7409
c7b8f16e 7410 sec_data = elf32_arm_section_data (s);
906e58ca 7411
c7b8f16e 7412 BFD_ASSERT (s != NULL);
906e58ca 7413
21d799b5 7414 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7415 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7416
c7b8f16e 7417 BFD_ASSERT (tmp_name);
906e58ca 7418
c7b8f16e
JB		 7419 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7420 hash_table->num_vfp11_fixes);
906e58ca 7421
c7b8f16e
JB		 7422 myh = elf_link_hash_lookup
7423 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7424
c7b8f16e 7425 BFD_ASSERT (myh == NULL);
906e58ca 7426
c7b8f16e
JB		 7427 bh = NULL;
7428 val = hash_table->vfp11_erratum_glue_size;
7429 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7430 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7431 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7432
7433 myh = (struct elf_link_hash_entry *) bh;
7434 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7435 myh->forced_local = 1;
7436
7437 /* Link veneer back to calling location. */
c7e2358a 7438 sec_data->erratumcount += 1;
21d799b5
NC		 7439 newerr = (elf32_vfp11_erratum_list *)
7440 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7441
c7b8f16e
JB		 7442 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7443 newerr->vma = -1;
7444 newerr->u.v.branch = branch;
7445 newerr->u.v.id = hash_table->num_vfp11_fixes;
7446 branch->u.b.veneer = newerr;
7447
7448 newerr->next = sec_data->erratumlist;
7449 sec_data->erratumlist = newerr;
7450
7451 /* A symbol for the return from the veneer. */
7452 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7453 hash_table->num_vfp11_fixes);
7454
7455 myh = elf_link_hash_lookup
7456 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7457
c7b8f16e
JB		 7458 if (myh != NULL)
7459 abort ();
7460
7461 bh = NULL;
7462 val = offset + 4;
7463 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7464 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7465
c7b8f16e
JB		 7466 myh = (struct elf_link_hash_entry *) bh;
7467 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7468 myh->forced_local = 1;
7469
7470 free (tmp_name);
906e58ca 7471
c7b8f16e
JB		 7472 /* Generate a mapping symbol for the veneer section, and explicitly add an
7473 entry for that symbol to the code/data map for the section. */
7474 if (hash_table->vfp11_erratum_glue_size == 0)
7475 {
7476 bh = NULL;
7477 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7478 ever requires this erratum fix. */
c7b8f16e
JB		 7479 _bfd_generic_link_add_one_symbol (link_info,
7480 hash_table->bfd_of_glue_owner, "$a",
7481 BSF_LOCAL, s, 0, NULL,
99059e56 7482 TRUE, FALSE, &bh);
c7b8f16e
JB		 7483
7484 myh = (struct elf_link_hash_entry *) bh;
7485 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7486 myh->forced_local = 1;
906e58ca 7487
c7b8f16e 7488 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7489 BFDs. We must make a note of this generated mapping symbol
7490 ourselves so that code byteswapping works properly in
7491 elf32_arm_write_section. */
c7b8f16e
JB		 7492 elf32_arm_section_map_add (s, 'a', 0);
7493 }
906e58ca 7494
c7b8f16e
JB		 7495 s->size += VFP11_ERRATUM_VENEER_SIZE;
7496 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7497 hash_table->num_vfp11_fixes++;
906e58ca 7498
c7b8f16e
JB		 7499 /* The offset of the veneer. */
7500 return val;
7501}
7502
a504d23a
LA		 7503/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7504 veneers need to be handled because used only in Cortex-M. */
7505
7506static bfd_vma
7507record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7508 elf32_stm32l4xx_erratum_list *branch,
7509 bfd *branch_bfd,
7510 asection *branch_sec,
7511 unsigned int offset,
7512 bfd_size_type veneer_size)
7513{
7514 asection *s;
7515 struct elf32_arm_link_hash_table *hash_table;
7516 char *tmp_name;
7517 struct elf_link_hash_entry *myh;
7518 struct bfd_link_hash_entry *bh;
7519 bfd_vma val;
7520 struct _arm_elf_section_data *sec_data;
7521 elf32_stm32l4xx_erratum_list *newerr;
7522
7523 hash_table = elf32_arm_hash_table (link_info);
7524 BFD_ASSERT (hash_table != NULL);
7525 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7526
7527 s = bfd_get_linker_section
7528 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7529
7530 BFD_ASSERT (s != NULL);
7531
7532 sec_data = elf32_arm_section_data (s);
7533
7534 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7535 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7536
7537 BFD_ASSERT (tmp_name);
7538
7539 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7540 hash_table->num_stm32l4xx_fixes);
7541
7542 myh = elf_link_hash_lookup
7543 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7544
7545 BFD_ASSERT (myh == NULL);
7546
7547 bh = NULL;
7548 val = hash_table->stm32l4xx_erratum_glue_size;
7549 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7550 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7551 NULL, TRUE, FALSE, &bh);
7552
7553 myh = (struct elf_link_hash_entry *) bh;
7554 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7555 myh->forced_local = 1;
7556
7557 /* Link veneer back to calling location. */
7558 sec_data->stm32l4xx_erratumcount += 1;
7559 newerr = (elf32_stm32l4xx_erratum_list *)
7560 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7561
7562 newerr->type = STM32L4XX_ERRATUM_VENEER;
7563 newerr->vma = -1;
7564 newerr->u.v.branch = branch;
7565 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7566 branch->u.b.veneer = newerr;
7567
7568 newerr->next = sec_data->stm32l4xx_erratumlist;
7569 sec_data->stm32l4xx_erratumlist = newerr;
7570
7571 /* A symbol for the return from the veneer. */
7572 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7573 hash_table->num_stm32l4xx_fixes);
7574
7575 myh = elf_link_hash_lookup
7576 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7577
7578 if (myh != NULL)
7579 abort ();
7580
7581 bh = NULL;
7582 val = offset + 4;
7583 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7584 branch_sec, val, NULL, TRUE, FALSE, &bh);
7585
7586 myh = (struct elf_link_hash_entry *) bh;
7587 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7588 myh->forced_local = 1;
7589
7590 free (tmp_name);
7591
7592 /* Generate a mapping symbol for the veneer section, and explicitly add an
7593 entry for that symbol to the code/data map for the section. */
7594 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7595 {
7596 bh = NULL;
7597 /* Creates a THUMB symbol since there is no other choice. */
7598 _bfd_generic_link_add_one_symbol (link_info,
7599 hash_table->bfd_of_glue_owner, "$t",
7600 BSF_LOCAL, s, 0, NULL,
7601 TRUE, FALSE, &bh);
7602
7603 myh = (struct elf_link_hash_entry *) bh;
7604 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7605 myh->forced_local = 1;
7606
7607 /* The elf32_arm_init_maps function only cares about symbols from input
7608 BFDs. We must make a note of this generated mapping symbol
7609 ourselves so that code byteswapping works properly in
7610 elf32_arm_write_section. */
7611 elf32_arm_section_map_add (s, 't', 0);
7612 }
7613
7614 s->size += veneer_size;
7615 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7616 hash_table->num_stm32l4xx_fixes++;
7617
7618 /* The offset of the veneer. */
7619 return val;
7620}
7621
8029a119 7622#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7623 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7624 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7625
7626/* Create a fake section for use by the ARM backend of the linker. */
7627
7628static bfd_boolean
7629arm_make_glue_section (bfd * abfd, const char * name)
7630{
7631 asection * sec;
7632
3d4d4302 7633 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7634 if (sec != NULL)
7635 /* Already made. */
7636 return TRUE;
7637
3d4d4302 7638 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7639
7640 if (sec == NULL
7641 || !bfd_set_section_alignment (abfd, sec, 2))
7642 return FALSE;
7643
7644 /* Set the gc mark to prevent the section from being removed by garbage
7645 collection, despite the fact that no relocs refer to this section. */
7646 sec->gc_mark = 1;
7647
7648 return TRUE;
7649}
7650
1db37fe6
YG		 7651/* Set size of .plt entries. This function is called from the
7652 linker scripts in ld/emultempl/{armelf}.em. */
7653
7654void
7655bfd_elf32_arm_use_long_plt (void)
7656{
7657 elf32_arm_use_long_plt_entry = TRUE;
7658}
7659
8afb0e02
NC		 7660/* Add the glue sections to ABFD. This function is called from the
7661 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7662
b34976b6 7663bfd_boolean
57e8b36a
NC		 7664bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7665 struct bfd_link_info *info)
252b5132 7666{
a504d23a
LA		 7667 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7668 bfd_boolean dostm32l4xx = globals
7669 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7670 bfd_boolean addglue;
7671
8afb0e02
NC		 7672 /* If we are only performing a partial
7673 link do not bother adding the glue. */
0e1862bb 7674 if (bfd_link_relocatable (info))
b34976b6 7675 return TRUE;
252b5132 7676
a504d23a 7677 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7678 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7679 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7680 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7681
7682 if (!dostm32l4xx)
7683 return addglue;
7684
7685 return addglue
7686 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7687}
7688
daa4adae
TP		 7689/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7690 ensures they are not marked for deletion by
7691 strip_excluded_output_sections () when veneers are going to be created
7692 later. Not doing so would trigger assert on empty section size in
7693 lang_size_sections_1 (). */
7694
7695void
7696bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7697{
7698 enum elf32_arm_stub_type stub_type;
7699
7700 /* If we are only performing a partial
7701 link do not bother adding the glue. */
7702 if (bfd_link_relocatable (info))
7703 return;
7704
7705 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7706 {
7707 asection *out_sec;
7708 const char *out_sec_name;
7709
7710 if (!arm_dedicated_stub_output_section_required (stub_type))
7711 continue;
7712
7713 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7714 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7715 if (out_sec != NULL)
7716 out_sec->flags |= SEC_KEEP;
7717 }
7718}
7719
8afb0e02
NC		 7720/* Select a BFD to be used to hold the sections used by the glue code.
7721 This function is called from the linker scripts in ld/emultempl/
8029a119 7722 {armelf/pe}.em. */
8afb0e02 7723
b34976b6 7724bfd_boolean
57e8b36a 7725bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7726{
7727 struct elf32_arm_link_hash_table *globals;
7728
7729 /* If we are only performing a partial link
7730 do not bother getting a bfd to hold the glue. */
0e1862bb 7731 if (bfd_link_relocatable (info))
b34976b6 7732 return TRUE;
8afb0e02 7733
b7693d02
DJ		 7734 /* Make sure we don't attach the glue sections to a dynamic object. */
7735 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7736
8afb0e02 7737 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7738 BFD_ASSERT (globals != NULL);
7739
7740 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7741 return TRUE;
8afb0e02 7742
252b5132
RH		 7743 /* Save the bfd for later use. */
7744 globals->bfd_of_glue_owner = abfd;
cedb70c5 7745
b34976b6 7746 return TRUE;
252b5132
RH		 7747}
7748
906e58ca
NC		 7749static void
7750check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7751{
2de70689
MGD		 7752 int cpu_arch;
7753
b38cadfb 7754 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7755 Tag_CPU_arch);
7756
7757 if (globals->fix_arm1176)
7758 {
7759 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7760 globals->use_blx = 1;
7761 }
7762 else
7763 {
7764 if (cpu_arch > TAG_CPU_ARCH_V4T)
7765 globals->use_blx = 1;
7766 }
39b41c9c
PB		 7767}
7768
b34976b6 7769bfd_boolean
57e8b36a 7770bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7771 struct bfd_link_info *link_info)
252b5132
RH		 7772{
7773 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7774 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7775 Elf_Internal_Rela *irel, *irelend;
7776 bfd_byte *contents = NULL;
252b5132
RH		 7777
7778 asection *sec;
7779 struct elf32_arm_link_hash_table *globals;
7780
7781 /* If we are only performing a partial link do not bother
7782 to construct any glue. */
0e1862bb 7783 if (bfd_link_relocatable (link_info))
b34976b6 7784 return TRUE;
252b5132 7785
39ce1a6a
NC		 7786 /* Here we have a bfd that is to be included on the link. We have a
7787 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7788 globals = elf32_arm_hash_table (link_info);
252b5132 7789 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7790
7791 check_use_blx (globals);
252b5132 7792
d504ffc8 7793 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7794 {
90b6238f 7795 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7796 abfd);
e489d0ae
PB		 7797 return FALSE;
7798 }
f21f3fe0 7799
39ce1a6a
NC		 7800 /* PR 5398: If we have not decided to include any loadable sections in
7801 the output then we will not have a glue owner bfd. This is OK, it
7802 just means that there is nothing else for us to do here. */
7803 if (globals->bfd_of_glue_owner == NULL)
7804 return TRUE;
7805
252b5132
RH		 7806 /* Rummage around all the relocs and map the glue vectors. */
7807 sec = abfd->sections;
7808
7809 if (sec == NULL)
b34976b6 7810 return TRUE;
252b5132
RH		 7811
7812 for (; sec != NULL; sec = sec->next)
7813 {
7814 if (sec->reloc_count == 0)
7815 continue;
7816
2f475487
AM		 7817 if ((sec->flags & SEC_EXCLUDE) != 0)
7818 continue;
7819
0ffa91dd 7820 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7821
9b485d32 7822 /* Load the relocs. */
6cdc0ccc 7823 internal_relocs
906e58ca 7824 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7825
6cdc0ccc
AM		 7826 if (internal_relocs == NULL)
7827 goto error_return;
252b5132 7828
6cdc0ccc
AM		 7829 irelend = internal_relocs + sec->reloc_count;
7830 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7831 {
7832 long r_type;
7833 unsigned long r_index;
252b5132
RH		 7834
7835 struct elf_link_hash_entry *h;
7836
7837 r_type = ELF32_R_TYPE (irel->r_info);
7838 r_index = ELF32_R_SYM (irel->r_info);
7839
9b485d32 7840 /* These are the only relocation types we care about. */
ba96a88f 7841 if ( r_type != R_ARM_PC24
845b51d6 7842 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7843 continue;
7844
7845 /* Get the section contents if we haven't done so already. */
7846 if (contents == NULL)
7847 {
7848 /* Get cached copy if it exists. */
7849 if (elf_section_data (sec)->this_hdr.contents != NULL)
7850 contents = elf_section_data (sec)->this_hdr.contents;
7851 else
7852 {
7853 /* Go get them off disk. */
57e8b36a 7854 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7855 goto error_return;
7856 }
7857 }
7858
845b51d6
PB		 7859 if (r_type == R_ARM_V4BX)
7860 {
7861 int reg;
7862
7863 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7864 record_arm_bx_glue (link_info, reg);
7865 continue;
7866 }
7867
a7c10850 7868 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7869 h = NULL;
7870
9b485d32 7871 /* We don't care about local symbols. */
252b5132
RH		 7872 if (r_index < symtab_hdr->sh_info)
7873 continue;
7874
9b485d32 7875 /* This is an external symbol. */
252b5132
RH		 7876 r_index -= symtab_hdr->sh_info;
7877 h = (struct elf_link_hash_entry *)
7878 elf_sym_hashes (abfd)[r_index];
7879
7880 /* If the relocation is against a static symbol it must be within
7881 the current section and so cannot be a cross ARM/Thumb relocation. */
7882 if (h == NULL)
7883 continue;
7884
d504ffc8
DJ		 7885 /* If the call will go through a PLT entry then we do not need
7886 glue. */
362d30a1 7887 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7888 continue;
7889
252b5132
RH		 7890 switch (r_type)
7891 {
7892 case R_ARM_PC24:
7893 /* This one is a call from arm code. We need to look up
99059e56
RM		 7894 the target of the call. If it is a thumb target, we
7895 insert glue. */
39d911fc
TP		 7896 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7897 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7898 record_arm_to_thumb_glue (link_info, h);
7899 break;
7900
252b5132 7901 default:
c6596c5e 7902 abort ();
252b5132
RH		 7903 }
7904 }
6cdc0ccc
AM		 7905
7906 if (contents != NULL
7907 && elf_section_data (sec)->this_hdr.contents != contents)
7908 free (contents);
7909 contents = NULL;
7910
7911 if (internal_relocs != NULL
7912 && elf_section_data (sec)->relocs != internal_relocs)
7913 free (internal_relocs);
7914 internal_relocs = NULL;
252b5132
RH		 7915 }
7916
b34976b6 7917 return TRUE;
9a5aca8c 7918
252b5132 7919error_return:
6cdc0ccc
AM		 7920 if (contents != NULL
7921 && elf_section_data (sec)->this_hdr.contents != contents)
7922 free (contents);
7923 if (internal_relocs != NULL
7924 && elf_section_data (sec)->relocs != internal_relocs)
7925 free (internal_relocs);
9a5aca8c 7926
b34976b6 7927 return FALSE;
252b5132 7928}
7e392df6 7929#endif
252b5132 7930
eb043451 7931
c7b8f16e
JB		 7932/* Initialise maps of ARM/Thumb/data for input BFDs. */
7933
7934void
7935bfd_elf32_arm_init_maps (bfd *abfd)
7936{
7937 Elf_Internal_Sym *isymbuf;
7938 Elf_Internal_Shdr *hdr;
7939 unsigned int i, localsyms;
7940
af1f4419
NC		 7941 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7942 if (! is_arm_elf (abfd))
7943 return;
7944
c7b8f16e
JB		 7945 if ((abfd->flags & DYNAMIC) != 0)
7946 return;
7947
0ffa91dd 7948 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7949 localsyms = hdr->sh_info;
7950
7951 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7952 should contain the number of local symbols, which should come before any
7953 global symbols. Mapping symbols are always local. */
7954 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7955 NULL);
7956
7957 /* No internal symbols read? Skip this BFD. */
7958 if (isymbuf == NULL)
7959 return;
7960
7961 for (i = 0; i < localsyms; i++)
7962 {
7963 Elf_Internal_Sym *isym = &isymbuf[i];
7964 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7965 const char *name;
906e58ca 7966
c7b8f16e 7967 if (sec != NULL
99059e56
RM		 7968 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7969 {
7970 name = bfd_elf_string_from_elf_section (abfd,
7971 hdr->sh_link, isym->st_name);
906e58ca 7972
99059e56 7973 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7974 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7975 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7976 }
c7b8f16e
JB		 7977 }
7978}
7979
7980
48229727
JB		 7981/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7982 say what they wanted. */
7983
7984void
7985bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7986{
7987 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7988 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7989
4dfe6ac6
NC		 7990 if (globals == NULL)
7991 return;
7992
48229727
JB		 7993 if (globals->fix_cortex_a8 == -1)
7994 {
7995 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7996 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7997 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7998 || out_attr[Tag_CPU_arch_profile].i == 0))
7999 globals->fix_cortex_a8 = 1;
8000 else
8001 globals->fix_cortex_a8 = 0;
8002 }
8003}
8004
8005
c7b8f16e
JB		 8006void
8007bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8008{
8009 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8010 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8011
4dfe6ac6
NC		 8012 if (globals == NULL)
8013 return;
c7b8f16e
JB		 8014 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8015 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8016 {
8017 switch (globals->vfp11_fix)
99059e56
RM		 8018 {
8019 case BFD_ARM_VFP11_FIX_DEFAULT:
8020 case BFD_ARM_VFP11_FIX_NONE:
8021 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8022 break;
8023
8024 default:
8025 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8026 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8027 "workaround is not necessary for target architecture"), obfd);
8028 }
c7b8f16e
JB		 8029 }
8030 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8031 /* For earlier architectures, we might need the workaround, but do not
8032 enable it by default. If users is running with broken hardware, they
8033 must enable the erratum fix explicitly. */
8034 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8035}
8036
a504d23a
LA		 8037void
8038bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8039{
8040 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8041 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8042
8043 if (globals == NULL)
8044 return;
8045
8046 /* We assume only Cortex-M4 may require the fix. */
8047 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8048 || out_attr[Tag_CPU_arch_profile].i != 'M')
8049 {
8050 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8051 /* Give a warning, but do as the user requests anyway. */
4eca0228 8052 _bfd_error_handler
871b3ab2 8053 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8054 "workaround is not necessary for target architecture"), obfd);
8055 }
8056}
c7b8f16e 8057
906e58ca
NC		 8058enum bfd_arm_vfp11_pipe
8059{
c7b8f16e
JB		 8060 VFP11_FMAC,
8061 VFP11_LS,
8062 VFP11_DS,
8063 VFP11_BAD
8064};
8065
8066/* Return a VFP register number. This is encoded as RX:X for single-precision
8067 registers, or X:RX for double-precision registers, where RX is the group of
8068 four bits in the instruction encoding and X is the single extension bit.
8069 RX and X fields are specified using their lowest (starting) bit. The return
8070 value is:
8071
8072 0...31: single-precision registers s0...s31
8073 32...63: double-precision registers d0...d31.
906e58ca 8074
c7b8f16e
JB		 8075 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8076 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8077
c7b8f16e
JB		 8078static unsigned int
8079bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8080 unsigned int x)
c7b8f16e
JB		 8081{
8082 if (is_double)
8083 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8084 else
8085 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8086}
8087
8088/* Set bits in *WMASK according to a register number REG as encoded by
8089 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8090
8091static void
8092bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8093{
8094 if (reg < 32)
8095 *wmask |= 1 << reg;
8096 else if (reg < 48)
8097 *wmask |= 3 << ((reg - 32) * 2);
8098}
8099
8100/* Return TRUE if WMASK overwrites anything in REGS. */
8101
8102static bfd_boolean
8103bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8104{
8105 int i;
906e58ca 8106
c7b8f16e
JB		 8107 for (i = 0; i < numregs; i++)
8108 {
8109 unsigned int reg = regs[i];
8110
8111 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8112 return TRUE;
906e58ca 8113
c7b8f16e
JB		 8114 reg -= 32;
8115
8116 if (reg >= 16)
99059e56 8117 continue;
906e58ca 8118
c7b8f16e 8119 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8120 return TRUE;
c7b8f16e 8121 }
906e58ca 8122
c7b8f16e
JB		 8123 return FALSE;
8124}
8125
8126/* In this function, we're interested in two things: finding input registers
8127 for VFP data-processing instructions, and finding the set of registers which
8128 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8129 hold the written set, so FLDM etc. are easy to deal with (we're only
8130 interested in 32 SP registers or 16 dp registers, due to the VFP version
8131 implemented by the chip in question). DP registers are marked by setting
8132 both SP registers in the write mask). */
8133
8134static enum bfd_arm_vfp11_pipe
8135bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8136 int *numregs)
c7b8f16e 8137{
91d6fa6a 8138 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8139 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8140
8141 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8142 {
8143 unsigned int pqrs;
8144 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8145 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8146
8147 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8148 | ((insn & 0x00300000) >> 19)
8149 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8150
8151 switch (pqrs)
99059e56
RM		 8152 {
8153 case 0: /* fmac[sd]. */
8154 case 1: /* fnmac[sd]. */
8155 case 2: /* fmsc[sd]. */
8156 case 3: /* fnmsc[sd]. */
8157 vpipe = VFP11_FMAC;
8158 bfd_arm_vfp11_write_mask (destmask, fd);
8159 regs[0] = fd;
8160 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8161 regs[2] = fm;
8162 *numregs = 3;
8163 break;
8164
8165 case 4: /* fmul[sd]. */
8166 case 5: /* fnmul[sd]. */
8167 case 6: /* fadd[sd]. */
8168 case 7: /* fsub[sd]. */
8169 vpipe = VFP11_FMAC;
8170 goto vfp_binop;
8171
8172 case 8: /* fdiv[sd]. */
8173 vpipe = VFP11_DS;
8174 vfp_binop:
8175 bfd_arm_vfp11_write_mask (destmask, fd);
8176 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8177 regs[1] = fm;
8178 *numregs = 2;
8179 break;
8180
8181 case 15: /* extended opcode. */
8182 {
8183 unsigned int extn = ((insn >> 15) & 0x1e)
8184 | ((insn >> 7) & 1);
8185
8186 switch (extn)
8187 {
8188 case 0: /* fcpy[sd]. */
8189 case 1: /* fabs[sd]. */
8190 case 2: /* fneg[sd]. */
8191 case 8: /* fcmp[sd]. */
8192 case 9: /* fcmpe[sd]. */
8193 case 10: /* fcmpz[sd]. */
8194 case 11: /* fcmpez[sd]. */
8195 case 16: /* fuito[sd]. */
8196 case 17: /* fsito[sd]. */
8197 case 24: /* ftoui[sd]. */
8198 case 25: /* ftouiz[sd]. */
8199 case 26: /* ftosi[sd]. */
8200 case 27: /* ftosiz[sd]. */
8201 /* These instructions will not bounce due to underflow. */
8202 *numregs = 0;
8203 vpipe = VFP11_FMAC;
8204 break;
8205
8206 case 3: /* fsqrt[sd]. */
8207 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8208 registers to cause the erratum in previous instructions. */
8209 bfd_arm_vfp11_write_mask (destmask, fd);
8210 vpipe = VFP11_DS;
8211 break;
8212
8213 case 15: /* fcvt{ds,sd}. */
8214 {
8215 int rnum = 0;
8216
8217 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8218
8219 /* Only FCVTSD can underflow. */
99059e56
RM		 8220 if ((insn & 0x100) != 0)
8221 regs[rnum++] = fm;
c7b8f16e 8222
99059e56 8223 *numregs = rnum;
c7b8f16e 8224
99059e56
RM		 8225 vpipe = VFP11_FMAC;
8226 }
8227 break;
c7b8f16e 8228
99059e56
RM		 8229 default:
8230 return VFP11_BAD;
8231 }
8232 }
8233 break;
c7b8f16e 8234
99059e56
RM		 8235 default:
8236 return VFP11_BAD;
8237 }
c7b8f16e
JB		 8238 }
8239 /* Two-register transfer. */
8240 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8241 {
8242 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8243
c7b8f16e
JB		 8244 if ((insn & 0x100000) == 0)
8245 {
99059e56
RM		 8246 if (is_double)
8247 bfd_arm_vfp11_write_mask (destmask, fm);
8248 else
8249 {
8250 bfd_arm_vfp11_write_mask (destmask, fm);
8251 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8252 }
c7b8f16e
JB		 8253 }
8254
91d6fa6a 8255 vpipe = VFP11_LS;
c7b8f16e
JB		 8256 }
8257 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8258 {
8259 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8260 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8261
c7b8f16e 8262 switch (puw)
99059e56
RM		 8263 {
8264 case 0: /* Two-reg transfer. We should catch these above. */
8265 abort ();
906e58ca 8266
99059e56
RM		 8267 case 2: /* fldm[sdx]. */
8268 case 3:
8269 case 5:
8270 {
8271 unsigned int i, offset = insn & 0xff;
c7b8f16e 8272
99059e56
RM		 8273 if (is_double)
8274 offset >>= 1;
c7b8f16e 8275
99059e56
RM		 8276 for (i = fd; i < fd + offset; i++)
8277 bfd_arm_vfp11_write_mask (destmask, i);
8278 }
8279 break;
906e58ca 8280
99059e56
RM		 8281 case 4: /* fld[sd]. */
8282 case 6:
8283 bfd_arm_vfp11_write_mask (destmask, fd);
8284 break;
906e58ca 8285
99059e56
RM		 8286 default:
8287 return VFP11_BAD;
8288 }
c7b8f16e 8289
91d6fa6a 8290 vpipe = VFP11_LS;
c7b8f16e
JB		 8291 }
8292 /* Single-register transfer. Note L==0. */
8293 else if ((insn & 0x0f100e10) == 0x0e000a10)
8294 {
8295 unsigned int opcode = (insn >> 21) & 7;
8296 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8297
8298 switch (opcode)
99059e56
RM		 8299 {
8300 case 0: /* fmsr/fmdlr. */
8301 case 1: /* fmdhr. */
8302 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8303 destination register. I don't know if this is exactly right,
8304 but it is the conservative choice. */
8305 bfd_arm_vfp11_write_mask (destmask, fn);
8306 break;
8307
8308 case 7: /* fmxr. */
8309 break;
8310 }
c7b8f16e 8311
91d6fa6a 8312 vpipe = VFP11_LS;
c7b8f16e
JB		 8313 }
8314
91d6fa6a 8315 return vpipe;
c7b8f16e
JB		 8316}
8317
8318
8319static int elf32_arm_compare_mapping (const void * a, const void * b);
8320
8321
8322/* Look for potentially-troublesome code sequences which might trigger the
8323 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8324 (available from ARM) for details of the erratum. A short version is
8325 described in ld.texinfo. */
8326
8327bfd_boolean
8328bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8329{
8330 asection *sec;
8331 bfd_byte *contents = NULL;
8332 int state = 0;
8333 int regs[3], numregs = 0;
8334 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8335 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8336
4dfe6ac6
NC		 8337 if (globals == NULL)
8338 return FALSE;
8339
c7b8f16e
JB		 8340 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8341 The states transition as follows:
906e58ca 8342
c7b8f16e 8343 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8344 A VFP FMAC-pipeline instruction has been seen. Fill
8345 regs[0]..regs[numregs-1] with its input operands. Remember this
8346 instruction in 'first_fmac'.
c7b8f16e
JB		 8347
8348 1 -> 2
99059e56
RM		 8349 Any instruction, except for a VFP instruction which overwrites
8350 regs[*].
906e58ca 8351
c7b8f16e
JB		 8352 1 -> 3 [ -> 0 ] or
8353 2 -> 3 [ -> 0 ]
99059e56
RM		 8354 A VFP instruction has been seen which overwrites any of regs[*].
8355 We must make a veneer! Reset state to 0 before examining next
8356 instruction.
906e58ca 8357
c7b8f16e 8358 2 -> 0
99059e56
RM		 8359 If we fail to match anything in state 2, reset to state 0 and reset
8360 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8361
8362 If the VFP11 vector mode is in use, there must be at least two unrelated
8363 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8364 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8365
8366 /* If we are only performing a partial link do not bother
8367 to construct any glue. */
0e1862bb 8368 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8369 return TRUE;
8370
0ffa91dd
NC		 8371 /* Skip if this bfd does not correspond to an ELF image. */
8372 if (! is_arm_elf (abfd))
8373 return TRUE;
906e58ca 8374
c7b8f16e
JB		 8375 /* We should have chosen a fix type by the time we get here. */
8376 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8377
8378 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8379 return TRUE;
2e6030b9 8380
33a7ffc2
JM		 8381 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8382 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8383 return TRUE;
8384
c7b8f16e
JB		 8385 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8386 {
8387 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8388 struct _arm_elf_section_data *sec_data;
8389
8390 /* If we don't have executable progbits, we're not interested in this
99059e56 8391 section. Also skip if section is to be excluded. */
c7b8f16e 8392 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8393 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8394 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8395 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8396 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8397 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8398 continue;
c7b8f16e
JB		 8399
8400 sec_data = elf32_arm_section_data (sec);
906e58ca 8401
c7b8f16e 8402 if (sec_data->mapcount == 0)
99059e56 8403 continue;
906e58ca 8404
c7b8f16e
JB		 8405 if (elf_section_data (sec)->this_hdr.contents != NULL)
8406 contents = elf_section_data (sec)->this_hdr.contents;
8407 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8408 goto error_return;
8409
8410 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8411 elf32_arm_compare_mapping);
8412
8413 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8414 {
8415 unsigned int span_start = sec_data->map[span].vma;
8416 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8417 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8418 char span_type = sec_data->map[span].type;
8419
8420 /* FIXME: Only ARM mode is supported at present. We may need to
8421 support Thumb-2 mode also at some point. */
8422 if (span_type != 'a')
8423 continue;
8424
8425 for (i = span_start; i < span_end;)
8426 {
8427 unsigned int next_i = i + 4;
8428 unsigned int insn = bfd_big_endian (abfd)
8429 ? (contents[i] << 24)
8430 | (contents[i + 1] << 16)
8431 | (contents[i + 2] << 8)
8432 | contents[i + 3]
8433 : (contents[i + 3] << 24)
8434 | (contents[i + 2] << 16)
8435 | (contents[i + 1] << 8)
8436 | contents[i];
8437 unsigned int writemask = 0;
8438 enum bfd_arm_vfp11_pipe vpipe;
8439
8440 switch (state)
8441 {
8442 case 0:
8443 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8444 &numregs);
8445 /* I'm assuming the VFP11 erratum can trigger with denorm
8446 operands on either the FMAC or the DS pipeline. This might
8447 lead to slightly overenthusiastic veneer insertion. */
8448 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8449 {
8450 state = use_vector ? 1 : 2;
8451 first_fmac = i;
8452 veneer_of_insn = insn;
8453 }
8454 break;
8455
8456 case 1:
8457 {
8458 int other_regs[3], other_numregs;
8459 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8460 other_regs,
99059e56
RM		 8461 &other_numregs);
8462 if (vpipe != VFP11_BAD
8463 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8464 numregs))
99059e56
RM		 8465 state = 3;
8466 else
8467 state = 2;
8468 }
8469 break;
8470
8471 case 2:
8472 {
8473 int other_regs[3], other_numregs;
8474 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8475 other_regs,
99059e56
RM		 8476 &other_numregs);
8477 if (vpipe != VFP11_BAD
8478 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8479 numregs))
99059e56
RM		 8480 state = 3;
8481 else
8482 {
8483 state = 0;
8484 next_i = first_fmac + 4;
8485 }
8486 }
8487 break;
8488
8489 case 3:
8490 abort (); /* Should be unreachable. */
8491 }
8492
8493 if (state == 3)
8494 {
8495 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8496 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8497
8498 elf32_arm_section_data (sec)->erratumcount += 1;
8499
8500 newerr->u.b.vfp_insn = veneer_of_insn;
8501
8502 switch (span_type)
8503 {
8504 case 'a':
8505 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8506 break;
8507
8508 default:
8509 abort ();
8510 }
8511
8512 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8513 first_fmac);
8514
99059e56 8515 newerr->vma = -1;
c7b8f16e 8516
99059e56
RM		 8517 newerr->next = sec_data->erratumlist;
8518 sec_data->erratumlist = newerr;
c7b8f16e 8519
99059e56
RM		 8520 state = 0;
8521 }
c7b8f16e 8522
99059e56
RM		 8523 i = next_i;
8524 }
8525 }
906e58ca 8526
c7b8f16e 8527 if (contents != NULL
99059e56
RM		 8528 && elf_section_data (sec)->this_hdr.contents != contents)
8529 free (contents);
c7b8f16e
JB		 8530 contents = NULL;
8531 }
8532
8533 return TRUE;
8534
8535error_return:
8536 if (contents != NULL
8537 && elf_section_data (sec)->this_hdr.contents != contents)
8538 free (contents);
906e58ca 8539
c7b8f16e
JB		 8540 return FALSE;
8541}
8542
8543/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8544 after sections have been laid out, using specially-named symbols. */
8545
8546void
8547bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8548 struct bfd_link_info *link_info)
8549{
8550 asection *sec;
8551 struct elf32_arm_link_hash_table *globals;
8552 char *tmp_name;
906e58ca 8553
0e1862bb 8554 if (bfd_link_relocatable (link_info))
c7b8f16e 8555 return;
2e6030b9
MS		 8556
8557 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8558 if (! is_arm_elf (abfd))
2e6030b9
MS		 8559 return;
8560
c7b8f16e 8561 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8562 if (globals == NULL)
8563 return;
906e58ca 8564
21d799b5 8565 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8566 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8567
8568 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8569 {
8570 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8571 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8572
c7b8f16e 8573 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8574 {
8575 struct elf_link_hash_entry *myh;
8576 bfd_vma vma;
8577
8578 switch (errnode->type)
8579 {
8580 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8581 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8582 /* Find veneer symbol. */
8583 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8584 errnode->u.b.veneer->u.v.id);
8585
99059e56
RM		 8586 myh = elf_link_hash_lookup
8587 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8588
a504d23a 8589 if (myh == NULL)
90b6238f
AM		 8590 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8591 abfd, "VFP11", tmp_name);
a504d23a
LA		 8592
8593 vma = myh->root.u.def.section->output_section->vma
8594 + myh->root.u.def.section->output_offset
8595 + myh->root.u.def.value;
8596
8597 errnode->u.b.veneer->vma = vma;
8598 break;
8599
8600 case VFP11_ERRATUM_ARM_VENEER:
8601 case VFP11_ERRATUM_THUMB_VENEER:
8602 /* Find return location. */
8603 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8604 errnode->u.v.id);
8605
8606 myh = elf_link_hash_lookup
8607 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8608
8609 if (myh == NULL)
90b6238f
AM		 8610 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8611 abfd, "VFP11", tmp_name);
a504d23a
LA		 8612
8613 vma = myh->root.u.def.section->output_section->vma
8614 + myh->root.u.def.section->output_offset
8615 + myh->root.u.def.value;
8616
8617 errnode->u.v.branch->vma = vma;
8618 break;
8619
8620 default:
8621 abort ();
8622 }
8623 }
8624 }
8625
8626 free (tmp_name);
8627}
8628
8629/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8630 return locations after sections have been laid out, using
8631 specially-named symbols. */
8632
8633void
8634bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8635 struct bfd_link_info *link_info)
8636{
8637 asection *sec;
8638 struct elf32_arm_link_hash_table *globals;
8639 char *tmp_name;
8640
8641 if (bfd_link_relocatable (link_info))
8642 return;
8643
8644 /* Skip if this bfd does not correspond to an ELF image. */
8645 if (! is_arm_elf (abfd))
8646 return;
8647
8648 globals = elf32_arm_hash_table (link_info);
8649 if (globals == NULL)
8650 return;
8651
8652 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8653 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8654
8655 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8656 {
8657 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8658 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8659
8660 for (; errnode != NULL; errnode = errnode->next)
8661 {
8662 struct elf_link_hash_entry *myh;
8663 bfd_vma vma;
8664
8665 switch (errnode->type)
8666 {
8667 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8668 /* Find veneer symbol. */
8669 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8670 errnode->u.b.veneer->u.v.id);
8671
8672 myh = elf_link_hash_lookup
8673 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8674
8675 if (myh == NULL)
90b6238f
AM		 8676 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8677 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8678
8679 vma = myh->root.u.def.section->output_section->vma
8680 + myh->root.u.def.section->output_offset
8681 + myh->root.u.def.value;
8682
8683 errnode->u.b.veneer->vma = vma;
8684 break;
8685
8686 case STM32L4XX_ERRATUM_VENEER:
8687 /* Find return location. */
8688 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8689 errnode->u.v.id);
8690
8691 myh = elf_link_hash_lookup
8692 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8693
8694 if (myh == NULL)
90b6238f
AM		 8695 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8696 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8697
8698 vma = myh->root.u.def.section->output_section->vma
8699 + myh->root.u.def.section->output_offset
8700 + myh->root.u.def.value;
8701
8702 errnode->u.v.branch->vma = vma;
8703 break;
8704
8705 default:
8706 abort ();
8707 }
8708 }
8709 }
8710
8711 free (tmp_name);
8712}
8713
8714static inline bfd_boolean
8715is_thumb2_ldmia (const insn32 insn)
8716{
8717 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8718 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8719 return (insn & 0xffd02000) == 0xe8900000;
8720}
8721
8722static inline bfd_boolean
8723is_thumb2_ldmdb (const insn32 insn)
8724{
8725 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8726 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8727 return (insn & 0xffd02000) == 0xe9100000;
8728}
8729
8730static inline bfd_boolean
8731is_thumb2_vldm (const insn32 insn)
8732{
8733 /* A6.5 Extension register load or store instruction
8734 A7.7.229
9239bbd3
CM		 8735 We look for SP 32-bit and DP 64-bit registers.
8736 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8737 <list> is consecutive 64-bit registers
8738 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8739 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8740 <list> is consecutive 32-bit registers
8741 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8742 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8743 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8744 return
9239bbd3
CM		 8745 (((insn & 0xfe100f00) == 0xec100b00) ||
8746 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8747 && /* (IA without !). */
8748 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8749 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8750 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8751 /* (DB with !). */
8752 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8753}
8754
8755/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8756 VLDM opcode and:
8757 - computes the number and the mode of memory accesses
8758 - decides if the replacement should be done:
8759 . replaces only if > 8-word accesses
8760 . or (testing purposes only) replaces all accesses. */
8761
8762static bfd_boolean
8763stm32l4xx_need_create_replacing_stub (const insn32 insn,
8764 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8765{
9239bbd3 8766 int nb_words = 0;
a504d23a
LA		 8767
8768 /* The field encoding the register list is the same for both LDMIA
8769 and LDMDB encodings. */
8770 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8771 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8772 else if (is_thumb2_vldm (insn))
9239bbd3 8773 nb_words = (insn & 0xff);
a504d23a
LA		 8774
8775 /* DEFAULT mode accounts for the real bug condition situation,
8776 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8777 return
9239bbd3 8778 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8779 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8780}
8781
8782/* Look for potentially-troublesome code sequences which might trigger
8783 the STM STM32L4XX erratum. */
8784
8785bfd_boolean
8786bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8787 struct bfd_link_info *link_info)
8788{
8789 asection *sec;
8790 bfd_byte *contents = NULL;
8791 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8792
8793 if (globals == NULL)
8794 return FALSE;
8795
8796 /* If we are only performing a partial link do not bother
8797 to construct any glue. */
8798 if (bfd_link_relocatable (link_info))
8799 return TRUE;
8800
8801 /* Skip if this bfd does not correspond to an ELF image. */
8802 if (! is_arm_elf (abfd))
8803 return TRUE;
8804
8805 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8806 return TRUE;
8807
8808 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8809 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8810 return TRUE;
8811
8812 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8813 {
8814 unsigned int i, span;
8815 struct _arm_elf_section_data *sec_data;
8816
8817 /* If we don't have executable progbits, we're not interested in this
8818 section. Also skip if section is to be excluded. */
8819 if (elf_section_type (sec) != SHT_PROGBITS
8820 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8821 || (sec->flags & SEC_EXCLUDE) != 0
8822 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8823 || sec->output_section == bfd_abs_section_ptr
8824 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8825 continue;
8826
8827 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8828
a504d23a
LA		 8829 if (sec_data->mapcount == 0)
8830 continue;
c7b8f16e 8831
a504d23a
LA		 8832 if (elf_section_data (sec)->this_hdr.contents != NULL)
8833 contents = elf_section_data (sec)->this_hdr.contents;
8834 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8835 goto error_return;
c7b8f16e 8836
a504d23a
LA		 8837 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8838 elf32_arm_compare_mapping);
c7b8f16e 8839
a504d23a
LA		 8840 for (span = 0; span < sec_data->mapcount; span++)
8841 {
8842 unsigned int span_start = sec_data->map[span].vma;
8843 unsigned int span_end = (span == sec_data->mapcount - 1)
8844 ? sec->size : sec_data->map[span + 1].vma;
8845 char span_type = sec_data->map[span].type;
8846 int itblock_current_pos = 0;
c7b8f16e 8847
a504d23a
LA		 8848 /* Only Thumb2 mode need be supported with this CM4 specific
8849 code, we should not encounter any arm mode eg span_type
8850 != 'a'. */
8851 if (span_type != 't')
8852 continue;
c7b8f16e 8853
a504d23a
LA		 8854 for (i = span_start; i < span_end;)
8855 {
8856 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8857 bfd_boolean insn_32bit = FALSE;
8858 bfd_boolean is_ldm = FALSE;
8859 bfd_boolean is_vldm = FALSE;
8860 bfd_boolean is_not_last_in_it_block = FALSE;
8861
8862 /* The first 16-bits of all 32-bit thumb2 instructions start
8863 with opcode[15..13]=0b111 and the encoded op1 can be anything
8864 except opcode[12..11]!=0b00.
8865 See 32-bit Thumb instruction encoding. */
8866 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8867 insn_32bit = TRUE;
c7b8f16e 8868
a504d23a
LA		 8869 /* Compute the predicate that tells if the instruction
8870 is concerned by the IT block
8871 - Creates an error if there is a ldm that is not
8872 last in the IT block thus cannot be replaced
8873 - Otherwise we can create a branch at the end of the
8874 IT block, it will be controlled naturally by IT
8875 with the proper pseudo-predicate
8876 - So the only interesting predicate is the one that
8877 tells that we are not on the last item of an IT
8878 block. */
8879 if (itblock_current_pos != 0)
8880 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8881
a504d23a
LA		 8882 if (insn_32bit)
8883 {
8884 /* Load the rest of the insn (in manual-friendly order). */
8885 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8886 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8887 is_vldm = is_thumb2_vldm (insn);
8888
8889 /* Veneers are created for (v)ldm depending on
8890 option flags and memory accesses conditions; but
8891 if the instruction is not the last instruction of
8892 an IT block, we cannot create a jump there, so we
8893 bail out. */
5025eb7c
AO		 8894 if ((is_ldm || is_vldm)
8895 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8896 (insn, globals->stm32l4xx_fix))
8897 {
8898 if (is_not_last_in_it_block)
8899 {
4eca0228 8900 _bfd_error_handler
695344c0 8901 /* xgettext:c-format */
871b3ab2 8902 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8903 " in non-last IT block instruction:"
8904 " STM32L4XX veneer cannot be generated; "
8905 "use gcc option -mrestrict-it to generate"
8906 " only one instruction per IT block"),
d42c267e 8907 abfd, sec, i);
a504d23a
LA		 8908 }
8909 else
8910 {
8911 elf32_stm32l4xx_erratum_list *newerr =
8912 (elf32_stm32l4xx_erratum_list *)
8913 bfd_zmalloc
8914 (sizeof (elf32_stm32l4xx_erratum_list));
8915
8916 elf32_arm_section_data (sec)
8917 ->stm32l4xx_erratumcount += 1;
8918 newerr->u.b.insn = insn;
8919 /* We create only thumb branches. */
8920 newerr->type =
8921 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8922 record_stm32l4xx_erratum_veneer
8923 (link_info, newerr, abfd, sec,
8924 i,
8925 is_ldm ?
8926 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8927 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8928 newerr->vma = -1;
8929 newerr->next = sec_data->stm32l4xx_erratumlist;
8930 sec_data->stm32l4xx_erratumlist = newerr;
8931 }
8932 }
8933 }
8934 else
8935 {
8936 /* A7.7.37 IT p208
8937 IT blocks are only encoded in T1
8938 Encoding T1: IT{x{y{z}}} <firstcond>
8939 1 0 1 1 - 1 1 1 1 - firstcond - mask
8940 if mask = '0000' then see 'related encodings'
8941 We don't deal with UNPREDICTABLE, just ignore these.
8942 There can be no nested IT blocks so an IT block
8943 is naturally a new one for which it is worth
8944 computing its size. */
5025eb7c
AO		 8945 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8946 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8947 /* If we have a new IT block we compute its size. */
8948 if (is_newitblock)
8949 {
8950 /* Compute the number of instructions controlled
8951 by the IT block, it will be used to decide
8952 whether we are inside an IT block or not. */
8953 unsigned int mask = insn & 0x000f;
8954 itblock_current_pos = 4 - ctz (mask);
8955 }
8956 }
8957
8958 i += insn_32bit ? 4 : 2;
99059e56
RM		 8959 }
8960 }
a504d23a
LA		 8961
8962 if (contents != NULL
8963 && elf_section_data (sec)->this_hdr.contents != contents)
8964 free (contents);
8965 contents = NULL;
c7b8f16e 8966 }
906e58ca 8967
a504d23a
LA		 8968 return TRUE;
8969
8970error_return:
8971 if (contents != NULL
8972 && elf_section_data (sec)->this_hdr.contents != contents)
8973 free (contents);
c7b8f16e 8974
a504d23a
LA		 8975 return FALSE;
8976}
c7b8f16e 8977
eb043451
PB		 8978/* Set target relocation values needed during linking. */
8979
8980void
68c39892 8981bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8982 struct bfd_link_info *link_info,
68c39892 8983 struct elf32_arm_params *params)
eb043451
PB		 8984{
8985 struct elf32_arm_link_hash_table *globals;
8986
8987 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8988 if (globals == NULL)
8989 return;
eb043451 8990
68c39892 8991 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 8992 if (globals->fdpic_p)
8993 globals->target2_reloc = R_ARM_GOT32;
8994 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 8995 globals->target2_reloc = R_ARM_REL32;
68c39892 8996 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8997 globals->target2_reloc = R_ARM_ABS32;
68c39892 8998 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8999 globals->target2_reloc = R_ARM_GOT_PREL;
9000 else
9001 {
90b6238f 9002 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9003 params->target2_type);
eb043451 9004 }
68c39892
TP		 9005 globals->fix_v4bx = params->fix_v4bx;
9006 globals->use_blx |= params->use_blx;
9007 globals->vfp11_fix = params->vfp11_denorm_fix;
9008 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9009 if (globals->fdpic_p)
9010 globals->pic_veneer = 1;
9011 else
9012 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9013 globals->fix_cortex_a8 = params->fix_cortex_a8;
9014 globals->fix_arm1176 = params->fix_arm1176;
9015 globals->cmse_implib = params->cmse_implib;
9016 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9017
0ffa91dd 9018 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9019 elf_arm_tdata (output_bfd)->no_enum_size_warning
9020 = params->no_enum_size_warning;
9021 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9022 = params->no_wchar_size_warning;
eb043451 9023}
eb043451 9024
12a0a0fd 9025/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9026
12a0a0fd
PB		 9027static void
9028insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9029{
9030 bfd_vma upper;
9031 bfd_vma lower;
9032 int reloc_sign;
9033
9034 BFD_ASSERT ((offset & 1) == 0);
9035
9036 upper = bfd_get_16 (abfd, insn);
9037 lower = bfd_get_16 (abfd, insn + 2);
9038 reloc_sign = (offset < 0) ? 1 : 0;
9039 upper = (upper & ~(bfd_vma) 0x7ff)
9040 | ((offset >> 12) & 0x3ff)
9041 | (reloc_sign << 10);
906e58ca 9042 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9043 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9044 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9045 | ((offset >> 1) & 0x7ff);
9046 bfd_put_16 (abfd, upper, insn);
9047 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9048}
9049
9b485d32
NC		 9050/* Thumb code calling an ARM function. */
9051
252b5132 9052static int
57e8b36a 9053elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9054 const char * name,
9055 bfd * input_bfd,
9056 bfd * output_bfd,
9057 asection * input_section,
9058 bfd_byte * hit_data,
9059 asection * sym_sec,
9060 bfd_vma offset,
9061 bfd_signed_vma addend,
9062 bfd_vma val,
f2a9dd69 9063 char **error_message)
252b5132 9064{
bcbdc74c 9065 asection * s = 0;
dc810e39 9066 bfd_vma my_offset;
252b5132 9067 long int ret_offset;
bcbdc74c
NC		 9068 struct elf_link_hash_entry * myh;
9069 struct elf32_arm_link_hash_table * globals;
252b5132 9070
f2a9dd69 9071 myh = find_thumb_glue (info, name, error_message);
252b5132 9072 if (myh == NULL)
b34976b6 9073 return FALSE;
252b5132
RH		 9074
9075 globals = elf32_arm_hash_table (info);
252b5132
RH		 9076 BFD_ASSERT (globals != NULL);
9077 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9078
9079 my_offset = myh->root.u.def.value;
9080
3d4d4302
AM		 9081 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9082 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9083
9084 BFD_ASSERT (s != NULL);
9085 BFD_ASSERT (s->contents != NULL);
9086 BFD_ASSERT (s->output_section != NULL);
9087
9088 if ((my_offset & 0x01) == 0x01)
9089 {
9090 if (sym_sec != NULL
9091 && sym_sec->owner != NULL
9092 && !INTERWORK_FLAG (sym_sec->owner))
9093 {
4eca0228 9094 _bfd_error_handler
90b6238f
AM		 9095 (_("%pB(%s): warning: interworking not enabled;"
9096 " first occurrence: %pB: %s call to %s"),
9097 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9098
b34976b6 9099 return FALSE;
252b5132
RH		 9100 }
9101
9102 --my_offset;
9103 myh->root.u.def.value = my_offset;
9104
52ab56c2
PB		 9105 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9106 s->contents + my_offset);
252b5132 9107
52ab56c2
PB		 9108 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9109 s->contents + my_offset + 2);
252b5132
RH		 9110
9111 ret_offset =
9b485d32
NC		 9112 /* Address of destination of the stub. */
9113 ((bfd_signed_vma) val)
252b5132 9114 - ((bfd_signed_vma)
57e8b36a
NC		 9115 /* Offset from the start of the current section
9116 to the start of the stubs. */
9b485d32
NC		 9117 (s->output_offset
9118 /* Offset of the start of this stub from the start of the stubs. */
9119 + my_offset
9120 /* Address of the start of the current section. */
9121 + s->output_section->vma)
9122 /* The branch instruction is 4 bytes into the stub. */
9123 + 4
9124 /* ARM branches work from the pc of the instruction + 8. */
9125 + 8);
252b5132 9126
52ab56c2
PB		 9127 put_arm_insn (globals, output_bfd,
9128 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9129 s->contents + my_offset + 4);
252b5132
RH		 9130 }
9131
9132 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9133
427bfd90
NC		 9134 /* Now go back and fix up the original BL insn to point to here. */
9135 ret_offset =
9136 /* Address of where the stub is located. */
9137 (s->output_section->vma + s->output_offset + my_offset)
9138 /* Address of where the BL is located. */
57e8b36a
NC		 9139 - (input_section->output_section->vma + input_section->output_offset
9140 + offset)
427bfd90
NC		 9141 /* Addend in the relocation. */
9142 - addend
9143 /* Biassing for PC-relative addressing. */
9144 - 8;
252b5132 9145
12a0a0fd 9146 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9147
b34976b6 9148 return TRUE;
252b5132
RH		 9149}
9150
a4fd1a8e 9151/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9152
a4fd1a8e
PB		 9153static struct elf_link_hash_entry *
9154elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9155 const char * name,
9156 bfd * input_bfd,
9157 bfd * output_bfd,
9158 asection * sym_sec,
9159 bfd_vma val,
9160 asection * s,
9161 char ** error_message)
252b5132 9162{
dc810e39 9163 bfd_vma my_offset;
252b5132 9164 long int ret_offset;
bcbdc74c
NC		 9165 struct elf_link_hash_entry * myh;
9166 struct elf32_arm_link_hash_table * globals;
252b5132 9167
f2a9dd69 9168 myh = find_arm_glue (info, name, error_message);
252b5132 9169 if (myh == NULL)
a4fd1a8e 9170 return NULL;
252b5132
RH		 9171
9172 globals = elf32_arm_hash_table (info);
252b5132
RH		 9173 BFD_ASSERT (globals != NULL);
9174 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9175
9176 my_offset = myh->root.u.def.value;
252b5132
RH		 9177
9178 if ((my_offset & 0x01) == 0x01)
9179 {
9180 if (sym_sec != NULL
9181 && sym_sec->owner != NULL
9182 && !INTERWORK_FLAG (sym_sec->owner))
9183 {
4eca0228 9184 _bfd_error_handler
90b6238f
AM		 9185 (_("%pB(%s): warning: interworking not enabled;"
9186 " first occurrence: %pB: %s call to %s"),
9187 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9188 }
9b485d32 9189
252b5132
RH		 9190 --my_offset;
9191 myh->root.u.def.value = my_offset;
9192
0e1862bb
L		 9193 if (bfd_link_pic (info)
9194 || globals->root.is_relocatable_executable
27e55c4d 9195 || globals->pic_veneer)
8f6277f5
PB		 9196 {
9197 /* For relocatable objects we can't use absolute addresses,
9198 so construct the address from a relative offset. */
9199 /* TODO: If the offset is small it's probably worth
9200 constructing the address with adds. */
52ab56c2
PB		 9201 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9202 s->contents + my_offset);
9203 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9204 s->contents + my_offset + 4);
9205 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9206 s->contents + my_offset + 8);
8f6277f5
PB		 9207 /* Adjust the offset by 4 for the position of the add,
9208 and 8 for the pipeline offset. */
9209 ret_offset = (val - (s->output_offset
9210 + s->output_section->vma
9211 + my_offset + 12))
9212 | 1;
9213 bfd_put_32 (output_bfd, ret_offset,
9214 s->contents + my_offset + 12);
9215 }
26079076
PB		 9216 else if (globals->use_blx)
9217 {
9218 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9219 s->contents + my_offset);
9220
9221 /* It's a thumb address. Add the low order bit. */
9222 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9223 s->contents + my_offset + 4);
9224 }
8f6277f5
PB		 9225 else
9226 {
52ab56c2
PB		 9227 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9228 s->contents + my_offset);
252b5132 9229
52ab56c2
PB		 9230 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9231 s->contents + my_offset + 4);
252b5132 9232
8f6277f5
PB		 9233 /* It's a thumb address. Add the low order bit. */
9234 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9235 s->contents + my_offset + 8);
8029a119
NC		 9236
9237 my_offset += 12;
8f6277f5 9238 }
252b5132
RH		 9239 }
9240
9241 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9242
a4fd1a8e
PB		 9243 return myh;
9244}
9245
9246/* Arm code calling a Thumb function. */
9247
9248static int
9249elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9250 const char * name,
9251 bfd * input_bfd,
9252 bfd * output_bfd,
9253 asection * input_section,
9254 bfd_byte * hit_data,
9255 asection * sym_sec,
9256 bfd_vma offset,
9257 bfd_signed_vma addend,
9258 bfd_vma val,
f2a9dd69 9259 char **error_message)
a4fd1a8e
PB		 9260{
9261 unsigned long int tmp;
9262 bfd_vma my_offset;
9263 asection * s;
9264 long int ret_offset;
9265 struct elf_link_hash_entry * myh;
9266 struct elf32_arm_link_hash_table * globals;
9267
9268 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9269 BFD_ASSERT (globals != NULL);
9270 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9271
3d4d4302
AM		 9272 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9273 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9274 BFD_ASSERT (s != NULL);
9275 BFD_ASSERT (s->contents != NULL);
9276 BFD_ASSERT (s->output_section != NULL);
9277
9278 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9279 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9280 if (!myh)
9281 return FALSE;
9282
9283 my_offset = myh->root.u.def.value;
252b5132
RH		 9284 tmp = bfd_get_32 (input_bfd, hit_data);
9285 tmp = tmp & 0xFF000000;
9286
9b485d32 9287 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9288 ret_offset = (s->output_offset
9289 + my_offset
9290 + s->output_section->vma
9291 - (input_section->output_offset
9292 + input_section->output_section->vma
9293 + offset + addend)
9294 - 8);
9a5aca8c 9295
252b5132
RH		 9296 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9297
dc810e39 9298 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9299
b34976b6 9300 return TRUE;
252b5132
RH		 9301}
9302
a4fd1a8e
PB		 9303/* Populate Arm stub for an exported Thumb function. */
9304
9305static bfd_boolean
9306elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9307{
9308 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9309 asection * s;
9310 struct elf_link_hash_entry * myh;
9311 struct elf32_arm_link_hash_entry *eh;
9312 struct elf32_arm_link_hash_table * globals;
9313 asection *sec;
9314 bfd_vma val;
f2a9dd69 9315 char *error_message;
a4fd1a8e 9316
906e58ca 9317 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9318 /* Allocate stubs for exported Thumb functions on v4t. */
9319 if (eh->export_glue == NULL)
9320 return TRUE;
9321
9322 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9323 BFD_ASSERT (globals != NULL);
9324 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9325
3d4d4302
AM		 9326 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9327 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9328 BFD_ASSERT (s != NULL);
9329 BFD_ASSERT (s->contents != NULL);
9330 BFD_ASSERT (s->output_section != NULL);
9331
9332 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9333
9334 BFD_ASSERT (sec->output_section != NULL);
9335
a4fd1a8e
PB		 9336 val = eh->export_glue->root.u.def.value + sec->output_offset
9337 + sec->output_section->vma;
8029a119 9338
a4fd1a8e
PB		 9339 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9340 h->root.u.def.section->owner,
f2a9dd69
DJ		 9341 globals->obfd, sec, val, s,
9342 &error_message);
a4fd1a8e
PB		 9343 BFD_ASSERT (myh);
9344 return TRUE;
9345}
9346
845b51d6
PB		 9347/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9348
9349static bfd_vma
9350elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9351{
9352 bfd_byte *p;
9353 bfd_vma glue_addr;
9354 asection *s;
9355 struct elf32_arm_link_hash_table *globals;
9356
9357 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9358 BFD_ASSERT (globals != NULL);
9359 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9360
3d4d4302
AM		 9361 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9362 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9363 BFD_ASSERT (s != NULL);
9364 BFD_ASSERT (s->contents != NULL);
9365 BFD_ASSERT (s->output_section != NULL);
9366
9367 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9368
9369 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9370
9371 if ((globals->bx_glue_offset[reg] & 1) == 0)
9372 {
9373 p = s->contents + glue_addr;
9374 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9375 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9376 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9377 globals->bx_glue_offset[reg] |= 1;
9378 }
9379
9380 return glue_addr + s->output_section->vma + s->output_offset;
9381}
9382
a4fd1a8e
PB		 9383/* Generate Arm stubs for exported Thumb symbols. */
9384static void
906e58ca 9385elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9386 struct bfd_link_info *link_info)
9387{
9388 struct elf32_arm_link_hash_table * globals;
9389
8029a119
NC		 9390 if (link_info == NULL)
9391 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9392 return;
9393
9394 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9395 if (globals == NULL)
9396 return;
9397
84c08195
PB		 9398 /* If blx is available then exported Thumb symbols are OK and there is
9399 nothing to do. */
a4fd1a8e
PB		 9400 if (globals->use_blx)
9401 return;
9402
9403 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9404 link_info);
9405}
9406
47beaa6a
RS		 9407/* Reserve space for COUNT dynamic relocations in relocation selection
9408 SRELOC. */
9409
9410static void
9411elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9412 bfd_size_type count)
9413{
9414 struct elf32_arm_link_hash_table *htab;
9415
9416 htab = elf32_arm_hash_table (info);
9417 BFD_ASSERT (htab->root.dynamic_sections_created);
9418 if (sreloc == NULL)
9419 abort ();
9420 sreloc->size += RELOC_SIZE (htab) * count;
9421}
9422
34e77a92
RS		 9423/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9424 dynamic, the relocations should go in SRELOC, otherwise they should
9425 go in the special .rel.iplt section. */
9426
9427static void
9428elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9429 bfd_size_type count)
9430{
9431 struct elf32_arm_link_hash_table *htab;
9432
9433 htab = elf32_arm_hash_table (info);
9434 if (!htab->root.dynamic_sections_created)
9435 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9436 else
9437 {
9438 BFD_ASSERT (sreloc != NULL);
9439 sreloc->size += RELOC_SIZE (htab) * count;
9440 }
9441}
9442
47beaa6a
RS		 9443/* Add relocation REL to the end of relocation section SRELOC. */
9444
9445static void
9446elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9447 asection *sreloc, Elf_Internal_Rela *rel)
9448{
9449 bfd_byte *loc;
9450 struct elf32_arm_link_hash_table *htab;
9451
9452 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9453 if (!htab->root.dynamic_sections_created
9454 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9455 sreloc = htab->root.irelplt;
47beaa6a
RS		 9456 if (sreloc == NULL)
9457 abort ();
9458 loc = sreloc->contents;
9459 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9460 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9461 abort ();
9462 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9463}
9464
34e77a92
RS		 9465/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9466 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9467 to .plt. */
9468
9469static void
9470elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9471 bfd_boolean is_iplt_entry,
9472 union gotplt_union *root_plt,
9473 struct arm_plt_info *arm_plt)
9474{
9475 struct elf32_arm_link_hash_table *htab;
9476 asection *splt;
9477 asection *sgotplt;
9478
9479 htab = elf32_arm_hash_table (info);
9480
9481 if (is_iplt_entry)
9482 {
9483 splt = htab->root.iplt;
9484 sgotplt = htab->root.igotplt;
9485
99059e56
RM		 9486 /* NaCl uses a special first entry in .iplt too. */
9487 if (htab->nacl_p && splt->size == 0)
9488 splt->size += htab->plt_header_size;
9489
34e77a92
RS		 9490 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9491 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9492 }
9493 else
9494 {
9495 splt = htab->root.splt;
9496 sgotplt = htab->root.sgotplt;
9497
7801f98f
CL		 9498 if (htab->fdpic_p)
9499 {
9500 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9501 /* For lazy binding, relocations will be put into .rel.plt, in
9502 .rel.got otherwise. */
9503 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9504 if (info->flags & DF_BIND_NOW)
9505 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9506 else
9507 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9508 }
9509 else
9510 {
9511 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9512 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9513 }
34e77a92
RS		 9514
9515 /* If this is the first .plt entry, make room for the special
9516 first entry. */
9517 if (splt->size == 0)
9518 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9519
9520 htab->next_tls_desc_index++;
34e77a92
RS		 9521 }
9522
9523 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9524 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9525 splt->size += PLT_THUMB_STUB_SIZE;
9526 root_plt->offset = splt->size;
9527 splt->size += htab->plt_entry_size;
9528
9529 if (!htab->symbian_p)
9530 {
9531 /* We also need to make an entry in the .got.plt section, which
9532 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9533 if (is_iplt_entry)
9534 arm_plt->got_offset = sgotplt->size;
9535 else
9536 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9537 if (htab->fdpic_p)
9538 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9539 sgotplt->size += 8;
7801f98f
CL		 9540 else
9541 sgotplt->size += 4;
34e77a92
RS		 9542 }
9543}
9544
b38cadfb
NC		 9545static bfd_vma
9546arm_movw_immediate (bfd_vma value)
9547{
9548 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9549}
9550
9551static bfd_vma
9552arm_movt_immediate (bfd_vma value)
9553{
9554 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9555}
9556
34e77a92
RS		 9557/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9558 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9559 Otherwise, DYNINDX is the index of the symbol in the dynamic
9560 symbol table and SYM_VALUE is undefined.
9561
9562 ROOT_PLT points to the offset of the PLT entry from the start of its
9563 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9564 bookkeeping information.
34e77a92 9565
57460bcf
NC		 9566 Returns FALSE if there was a problem. */
9567
9568static bfd_boolean
34e77a92
RS		 9569elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9570 union gotplt_union *root_plt,
9571 struct arm_plt_info *arm_plt,
9572 int dynindx, bfd_vma sym_value)
9573{
9574 struct elf32_arm_link_hash_table *htab;
9575 asection *sgot;
9576 asection *splt;
9577 asection *srel;
9578 bfd_byte *loc;
9579 bfd_vma plt_index;
9580 Elf_Internal_Rela rel;
9581 bfd_vma plt_header_size;
9582 bfd_vma got_header_size;
9583
9584 htab = elf32_arm_hash_table (info);
9585
9586 /* Pick the appropriate sections and sizes. */
9587 if (dynindx == -1)
9588 {
9589 splt = htab->root.iplt;
9590 sgot = htab->root.igotplt;
9591 srel = htab->root.irelplt;
9592
9593 /* There are no reserved entries in .igot.plt, and no special
9594 first entry in .iplt. */
9595 got_header_size = 0;
9596 plt_header_size = 0;
9597 }
9598 else
9599 {
9600 splt = htab->root.splt;
9601 sgot = htab->root.sgotplt;
9602 srel = htab->root.srelplt;
9603
9604 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9605 plt_header_size = htab->plt_header_size;
9606 }
9607 BFD_ASSERT (splt != NULL && srel != NULL);
9608
9609 /* Fill in the entry in the procedure linkage table. */
9610 if (htab->symbian_p)
9611 {
9612 BFD_ASSERT (dynindx >= 0);
9613 put_arm_insn (htab, output_bfd,
9614 elf32_arm_symbian_plt_entry[0],
9615 splt->contents + root_plt->offset);
9616 bfd_put_32 (output_bfd,
9617 elf32_arm_symbian_plt_entry[1],
9618 splt->contents + root_plt->offset + 4);
9619
9620 /* Fill in the entry in the .rel.plt section. */
9621 rel.r_offset = (splt->output_section->vma
9622 + splt->output_offset
9623 + root_plt->offset + 4);
9624 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9625
9626 /* Get the index in the procedure linkage table which
9627 corresponds to this symbol. This is the index of this symbol
9628 in all the symbols for which we are making plt entries. The
9629 first entry in the procedure linkage table is reserved. */
9630 plt_index = ((root_plt->offset - plt_header_size)
9631 / htab->plt_entry_size);
9632 }
9633 else
9634 {
9635 bfd_vma got_offset, got_address, plt_address;
9636 bfd_vma got_displacement, initial_got_entry;
9637 bfd_byte * ptr;
9638
9639 BFD_ASSERT (sgot != NULL);
9640
9641 /* Get the offset into the .(i)got.plt table of the entry that
9642 corresponds to this function. */
9643 got_offset = (arm_plt->got_offset & -2);
9644
9645 /* Get the index in the procedure linkage table which
9646 corresponds to this symbol. This is the index of this symbol
9647 in all the symbols for which we are making plt entries.
9648 After the reserved .got.plt entries, all symbols appear in
9649 the same order as in .plt. */
7801f98f 9650 if (htab->fdpic_p)
4b24dd1a
AM		 9651 /* Function descriptor takes 8 bytes. */
9652 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9653 else
4b24dd1a 9654 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9655
9656 /* Calculate the address of the GOT entry. */
9657 got_address = (sgot->output_section->vma
9658 + sgot->output_offset
9659 + got_offset);
9660
9661 /* ...and the address of the PLT entry. */
9662 plt_address = (splt->output_section->vma
9663 + splt->output_offset
9664 + root_plt->offset);
9665
9666 ptr = splt->contents + root_plt->offset;
0e1862bb 9667 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9668 {
9669 unsigned int i;
9670 bfd_vma val;
9671
9672 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9673 {
9674 val = elf32_arm_vxworks_shared_plt_entry[i];
9675 if (i == 2)
9676 val |= got_address - sgot->output_section->vma;
9677 if (i == 5)
9678 val |= plt_index * RELOC_SIZE (htab);
9679 if (i == 2 || i == 5)
9680 bfd_put_32 (output_bfd, val, ptr);
9681 else
9682 put_arm_insn (htab, output_bfd, val, ptr);
9683 }
9684 }
9685 else if (htab->vxworks_p)
9686 {
9687 unsigned int i;
9688 bfd_vma val;
9689
9690 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9691 {
9692 val = elf32_arm_vxworks_exec_plt_entry[i];
9693 if (i == 2)
9694 val |= got_address;
9695 if (i == 4)
9696 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9697 if (i == 5)
9698 val |= plt_index * RELOC_SIZE (htab);
9699 if (i == 2 || i == 5)
9700 bfd_put_32 (output_bfd, val, ptr);
9701 else
9702 put_arm_insn (htab, output_bfd, val, ptr);
9703 }
9704
9705 loc = (htab->srelplt2->contents
9706 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9707
9708 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9709 referencing the GOT for this PLT entry. */
9710 rel.r_offset = plt_address + 8;
9711 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9712 rel.r_addend = got_offset;
9713 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9714 loc += RELOC_SIZE (htab);
9715
9716 /* Create the R_ARM_ABS32 relocation referencing the
9717 beginning of the PLT for this GOT entry. */
9718 rel.r_offset = got_address;
9719 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9720 rel.r_addend = 0;
9721 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9722 }
b38cadfb
NC		 9723 else if (htab->nacl_p)
9724 {
9725 /* Calculate the displacement between the PLT slot and the
9726 common tail that's part of the special initial PLT slot. */
6034aab8 9727 int32_t tail_displacement
b38cadfb
NC		 9728 = ((splt->output_section->vma + splt->output_offset
9729 + ARM_NACL_PLT_TAIL_OFFSET)
9730 - (plt_address + htab->plt_entry_size + 4));
9731 BFD_ASSERT ((tail_displacement & 3) == 0);
9732 tail_displacement >>= 2;
9733
9734 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9735 || (-tail_displacement & 0xff000000) == 0);
9736
9737 /* Calculate the displacement between the PLT slot and the entry
9738 in the GOT. The offset accounts for the value produced by
9739 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9740 got_displacement = (got_address
99059e56 9741 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9742
9743 /* NaCl does not support interworking at all. */
9744 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9745
9746 put_arm_insn (htab, output_bfd,
9747 elf32_arm_nacl_plt_entry[0]
9748 | arm_movw_immediate (got_displacement),
9749 ptr + 0);
9750 put_arm_insn (htab, output_bfd,
9751 elf32_arm_nacl_plt_entry[1]
9752 | arm_movt_immediate (got_displacement),
9753 ptr + 4);
9754 put_arm_insn (htab, output_bfd,
9755 elf32_arm_nacl_plt_entry[2],
9756 ptr + 8);
9757 put_arm_insn (htab, output_bfd,
9758 elf32_arm_nacl_plt_entry[3]
9759 | (tail_displacement & 0x00ffffff),
9760 ptr + 12);
9761 }
7801f98f
CL		 9762 else if (htab->fdpic_p)
9763 {
59029f57
CL		 9764 const bfd_vma *plt_entry = using_thumb_only(htab)
9765 ? elf32_arm_fdpic_thumb_plt_entry
9766 : elf32_arm_fdpic_plt_entry;
9767
7801f98f
CL		 9768 /* Fill-up Thumb stub if needed. */
9769 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9770 {
9771 put_thumb_insn (htab, output_bfd,
9772 elf32_arm_plt_thumb_stub[0], ptr - 4);
9773 put_thumb_insn (htab, output_bfd,
9774 elf32_arm_plt_thumb_stub[1], ptr - 2);
9775 }
59029f57
CL		 9776 /* As we are using 32 bit instructions even for the Thumb
9777 version, we have to use 'put_arm_insn' instead of
9778 'put_thumb_insn'. */
9779 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9780 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9781 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9782 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9783 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9784
9785 if (!(info->flags & DF_BIND_NOW))
9786 {
9787 /* funcdesc_value_reloc_offset. */
9788 bfd_put_32 (output_bfd,
9789 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9790 ptr + 20);
59029f57
CL		 9791 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9792 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9793 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9794 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9795 }
9796 }
57460bcf
NC		 9797 else if (using_thumb_only (htab))
9798 {
eed94f8f 9799 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9800 if (!using_thumb2 (htab))
eed94f8f
NC		 9801 {
9802 /* FIXME: We ought to be able to generate thumb-1 PLT
9803 instructions... */
90b6238f 9804 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9805 output_bfd);
9806 return FALSE;
9807 }
57460bcf 9808
eed94f8f
NC		 9809 /* Calculate the displacement between the PLT slot and the entry in
9810 the GOT. The 12-byte offset accounts for the value produced by
9811 adding to pc in the 3rd instruction of the PLT stub. */
9812 got_displacement = got_address - (plt_address + 12);
9813
9814 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9815 instead of 'put_thumb_insn'. */
9816 put_arm_insn (htab, output_bfd,
9817 elf32_thumb2_plt_entry[0]
9818 | ((got_displacement & 0x000000ff) << 16)
9819 | ((got_displacement & 0x00000700) << 20)
9820 | ((got_displacement & 0x00000800) >> 1)
9821 | ((got_displacement & 0x0000f000) >> 12),
9822 ptr + 0);
9823 put_arm_insn (htab, output_bfd,
9824 elf32_thumb2_plt_entry[1]
9825 | ((got_displacement & 0x00ff0000) )
9826 | ((got_displacement & 0x07000000) << 4)
9827 | ((got_displacement & 0x08000000) >> 17)
9828 | ((got_displacement & 0xf0000000) >> 28),
9829 ptr + 4);
9830 put_arm_insn (htab, output_bfd,
9831 elf32_thumb2_plt_entry[2],
9832 ptr + 8);
9833 put_arm_insn (htab, output_bfd,
9834 elf32_thumb2_plt_entry[3],
9835 ptr + 12);
57460bcf 9836 }
34e77a92
RS		 9837 else
9838 {
9839 /* Calculate the displacement between the PLT slot and the
9840 entry in the GOT. The eight-byte offset accounts for the
9841 value produced by adding to pc in the first instruction
9842 of the PLT stub. */
9843 got_displacement = got_address - (plt_address + 8);
9844
34e77a92
RS		 9845 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9846 {
9847 put_thumb_insn (htab, output_bfd,
9848 elf32_arm_plt_thumb_stub[0], ptr - 4);
9849 put_thumb_insn (htab, output_bfd,
9850 elf32_arm_plt_thumb_stub[1], ptr - 2);
9851 }
9852
1db37fe6
YG		 9853 if (!elf32_arm_use_long_plt_entry)
9854 {
9855 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9856
9857 put_arm_insn (htab, output_bfd,
9858 elf32_arm_plt_entry_short[0]
9859 | ((got_displacement & 0x0ff00000) >> 20),
9860 ptr + 0);
9861 put_arm_insn (htab, output_bfd,
9862 elf32_arm_plt_entry_short[1]
9863 | ((got_displacement & 0x000ff000) >> 12),
9864 ptr+ 4);
9865 put_arm_insn (htab, output_bfd,
9866 elf32_arm_plt_entry_short[2]
9867 | (got_displacement & 0x00000fff),
9868 ptr + 8);
34e77a92 9869#ifdef FOUR_WORD_PLT
1db37fe6 9870 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9871#endif
1db37fe6
YG		 9872 }
9873 else
9874 {
9875 put_arm_insn (htab, output_bfd,
9876 elf32_arm_plt_entry_long[0]
9877 | ((got_displacement & 0xf0000000) >> 28),
9878 ptr + 0);
9879 put_arm_insn (htab, output_bfd,
9880 elf32_arm_plt_entry_long[1]
9881 | ((got_displacement & 0x0ff00000) >> 20),
9882 ptr + 4);
9883 put_arm_insn (htab, output_bfd,
9884 elf32_arm_plt_entry_long[2]
9885 | ((got_displacement & 0x000ff000) >> 12),
9886 ptr+ 8);
9887 put_arm_insn (htab, output_bfd,
9888 elf32_arm_plt_entry_long[3]
9889 | (got_displacement & 0x00000fff),
9890 ptr + 12);
9891 }
34e77a92
RS		 9892 }
9893
9894 /* Fill in the entry in the .rel(a).(i)plt section. */
9895 rel.r_offset = got_address;
9896 rel.r_addend = 0;
9897 if (dynindx == -1)
9898 {
9899 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9900 The dynamic linker or static executable then calls SYM_VALUE
9901 to determine the correct run-time value of the .igot.plt entry. */
9902 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9903 initial_got_entry = sym_value;
9904 }
9905 else
9906 {
7801f98f
CL		 9907 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9908 used by PLT entry. */
9909 if (htab->fdpic_p)
9910 {
9911 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9912 initial_got_entry = 0;
9913 }
9914 else
9915 {
9916 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9917 initial_got_entry = (splt->output_section->vma
9918 + splt->output_offset);
9919 }
34e77a92
RS		 9920 }
9921
9922 /* Fill in the entry in the global offset table. */
9923 bfd_put_32 (output_bfd, initial_got_entry,
9924 sgot->contents + got_offset);
7801f98f
CL		 9925
9926 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9927 {
9928 /* Setup initial funcdesc value. */
9929 /* FIXME: we don't support lazy binding because there is a
9930 race condition between both words getting written and
9931 some other thread attempting to read them. The ARM
9932 architecture does not have an atomic 64 bit load/store
9933 instruction that could be used to prevent it; it is
9934 recommended that threaded FDPIC applications run with the
9935 LD_BIND_NOW environment variable set. */
9936 bfd_put_32(output_bfd, plt_address + 0x18,
9937 sgot->contents + got_offset);
9938 bfd_put_32(output_bfd, -1 /*TODO*/,
9939 sgot->contents + got_offset + 4);
9940 }
34e77a92
RS		 9941 }
9942
aba8c3de
WN		 9943 if (dynindx == -1)
9944 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9945 else
9946 {
7801f98f
CL		 9947 if (htab->fdpic_p)
9948 {
9949 /* For FDPIC we put PLT relocationss into .rel.got when not
9950 lazy binding otherwise we put them in .rel.plt. For now,
9951 we don't support lazy binding so put it in .rel.got. */
9952 if (info->flags & DF_BIND_NOW)
9953 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9954 else
9955 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9956 }
9957 else
9958 {
9959 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9960 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9961 }
aba8c3de 9962 }
57460bcf
NC		 9963
9964 return TRUE;
34e77a92
RS		 9965}
9966
eb043451
PB		 9967/* Some relocations map to different relocations depending on the
9968 target. Return the real relocation. */
8029a119 9969
eb043451
PB		 9970static int
9971arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9972 int r_type)
9973{
9974 switch (r_type)
9975 {
9976 case R_ARM_TARGET1:
9977 if (globals->target1_is_rel)
9978 return R_ARM_REL32;
9979 else
9980 return R_ARM_ABS32;
9981
9982 case R_ARM_TARGET2:
9983 return globals->target2_reloc;
9984
9985 default:
9986 return r_type;
9987 }
9988}
eb043451 9989
ba93b8ac
DJ		 9990/* Return the base VMA address which should be subtracted from real addresses
9991 when resolving @dtpoff relocation.
9992 This is PT_TLS segment p_vaddr. */
9993
9994static bfd_vma
9995dtpoff_base (struct bfd_link_info *info)
9996{
9997 /* If tls_sec is NULL, we should have signalled an error already. */
9998 if (elf_hash_table (info)->tls_sec == NULL)
9999 return 0;
10000 return elf_hash_table (info)->tls_sec->vma;
10001}
10002
10003/* Return the relocation value for @tpoff relocation
10004 if STT_TLS virtual address is ADDRESS. */
10005
10006static bfd_vma
10007tpoff (struct bfd_link_info *info, bfd_vma address)
10008{
10009 struct elf_link_hash_table *htab = elf_hash_table (info);
10010 bfd_vma base;
10011
10012 /* If tls_sec is NULL, we should have signalled an error already. */
10013 if (htab->tls_sec == NULL)
10014 return 0;
10015 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10016 return address - htab->tls_sec->vma + base;
10017}
10018
00a97672
RS		 10019/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10020 VALUE is the relocation value. */
10021
10022static bfd_reloc_status_type
10023elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10024{
10025 if (value > 0xfff)
10026 return bfd_reloc_overflow;
10027
10028 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10029 bfd_put_32 (abfd, value, data);
10030 return bfd_reloc_ok;
10031}
10032
0855e32b
NS		 10033/* Handle TLS relaxations. Relaxing is possible for symbols that use
10034 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10035 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10036
10037 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10038 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10039 case of error.
10040
10041 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10042 the pre-relaxed code. It would be nice if the relocs were updated
10043 to match the optimization. */
0855e32b 10044
b38cadfb 10045static bfd_reloc_status_type
0855e32b 10046elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10047 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10048 Elf_Internal_Rela *rel, unsigned long is_local)
10049{
10050 unsigned long insn;
b38cadfb 10051
0855e32b
NS		 10052 switch (ELF32_R_TYPE (rel->r_info))
10053 {
10054 default:
10055 return bfd_reloc_notsupported;
b38cadfb 10056
0855e32b
NS		 10057 case R_ARM_TLS_GOTDESC:
10058 if (is_local)
10059 insn = 0;
10060 else
10061 {
10062 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10063 if (insn & 1)
10064 insn -= 5; /* THUMB */
10065 else
10066 insn -= 8; /* ARM */
10067 }
10068 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10069 return bfd_reloc_continue;
10070
10071 case R_ARM_THM_TLS_DESCSEQ:
10072 /* Thumb insn. */
10073 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10074 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10075 {
10076 if (is_local)
10077 /* nop */
10078 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10079 }
10080 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10081 {
10082 if (is_local)
10083 /* nop */
10084 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10085 else
10086 /* ldr rx,[ry] */
10087 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10088 }
10089 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10090 {
10091 if (is_local)
10092 /* nop */
10093 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10094 else
10095 /* mov r0, rx */
10096 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10097 contents + rel->r_offset);
10098 }
10099 else
10100 {
10101 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10102 /* It's a 32 bit instruction, fetch the rest of it for
10103 error generation. */
10104 insn = (insn << 16)
10105 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10106 _bfd_error_handler
695344c0 10107 /* xgettext:c-format */
2dcf00ce 10108 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10109 "unexpected %s instruction '%#lx' in TLS trampoline"),
10110 input_bfd, input_sec, (uint64_t) rel->r_offset,
10111 "Thumb", insn);
0855e32b
NS		 10112 return bfd_reloc_notsupported;
10113 }
10114 break;
b38cadfb 10115
0855e32b
NS		 10116 case R_ARM_TLS_DESCSEQ:
10117 /* arm insn. */
10118 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10119 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10120 {
10121 if (is_local)
10122 /* mov rx, ry */
10123 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10124 contents + rel->r_offset);
10125 }
10126 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10127 {
10128 if (is_local)
10129 /* nop */
10130 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10131 else
10132 /* ldr rx,[ry] */
10133 bfd_put_32 (input_bfd, insn & 0xfffff000,
10134 contents + rel->r_offset);
10135 }
10136 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10137 {
10138 if (is_local)
10139 /* nop */
10140 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10141 else
10142 /* mov r0, rx */
10143 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10144 contents + rel->r_offset);
10145 }
10146 else
10147 {
4eca0228 10148 _bfd_error_handler
695344c0 10149 /* xgettext:c-format */
2dcf00ce 10150 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10151 "unexpected %s instruction '%#lx' in TLS trampoline"),
10152 input_bfd, input_sec, (uint64_t) rel->r_offset,
10153 "ARM", insn);
0855e32b
NS		 10154 return bfd_reloc_notsupported;
10155 }
10156 break;
10157
10158 case R_ARM_TLS_CALL:
10159 /* GD->IE relaxation, turn the instruction into 'nop' or
10160 'ldr r0, [pc,r0]' */
10161 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10162 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10163 break;
b38cadfb 10164
0855e32b 10165 case R_ARM_THM_TLS_CALL:
6a631e86 10166 /* GD->IE relaxation. */
0855e32b
NS		 10167 if (!is_local)
10168 /* add r0,pc; ldr r0, [r0] */
10169 insn = 0x44786800;
60a019a0 10170 else if (using_thumb2 (globals))
0855e32b
NS		 10171 /* nop.w */
10172 insn = 0xf3af8000;
10173 else
10174 /* nop; nop */
10175 insn = 0xbf00bf00;
b38cadfb 10176
0855e32b
NS		 10177 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10178 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10179 break;
10180 }
10181 return bfd_reloc_ok;
10182}
10183
4962c51a
MS		 10184/* For a given value of n, calculate the value of G_n as required to
10185 deal with group relocations. We return it in the form of an
10186 encoded constant-and-rotation, together with the final residual. If n is
10187 specified as less than zero, then final_residual is filled with the
10188 input value and no further action is performed. */
10189
10190static bfd_vma
10191calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10192{
10193 int current_n;
10194 bfd_vma g_n;
10195 bfd_vma encoded_g_n = 0;
10196 bfd_vma residual = value; /* Also known as Y_n. */
10197
10198 for (current_n = 0; current_n <= n; current_n++)
10199 {
10200 int shift;
10201
10202 /* Calculate which part of the value to mask. */
10203 if (residual == 0)
99059e56 10204 shift = 0;
4962c51a 10205 else
99059e56
RM		 10206 {
10207 int msb;
10208
10209 /* Determine the most significant bit in the residual and
10210 align the resulting value to a 2-bit boundary. */
10211 for (msb = 30; msb >= 0; msb -= 2)
10212 if (residual & (3 << msb))
10213 break;
10214
10215 /* The desired shift is now (msb - 6), or zero, whichever
10216 is the greater. */
10217 shift = msb - 6;
10218 if (shift < 0)
10219 shift = 0;
10220 }
4962c51a
MS		 10221
10222 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10223 g_n = residual & (0xff << shift);
10224 encoded_g_n = (g_n >> shift)
99059e56 10225 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10226
10227 /* Calculate the residual for the next time around. */
10228 residual &= ~g_n;
10229 }
10230
10231 *final_residual = residual;
10232
10233 return encoded_g_n;
10234}
10235
10236/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10237 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10238
4962c51a 10239static int
906e58ca 10240identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10241{
10242 int opcode = insn & 0x1e00000;
10243
10244 if (opcode == 1 << 23) /* ADD */
10245 return 1;
10246
10247 if (opcode == 1 << 22) /* SUB */
10248 return -1;
10249
10250 return 0;
10251}
10252
252b5132 10253/* Perform a relocation as part of a final link. */
9b485d32 10254
252b5132 10255static bfd_reloc_status_type
07d6d2b8
AM		 10256elf32_arm_final_link_relocate (reloc_howto_type * howto,
10257 bfd * input_bfd,
10258 bfd * output_bfd,
10259 asection * input_section,
10260 bfd_byte * contents,
10261 Elf_Internal_Rela * rel,
10262 bfd_vma value,
10263 struct bfd_link_info * info,
10264 asection * sym_sec,
10265 const char * sym_name,
10266 unsigned char st_type,
10267 enum arm_st_branch_type branch_type,
0945cdfd 10268 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10269 bfd_boolean * unresolved_reloc_p,
10270 char ** error_message)
10271{
10272 unsigned long r_type = howto->type;
10273 unsigned long r_symndx;
10274 bfd_byte * hit_data = contents + rel->r_offset;
10275 bfd_vma * local_got_offsets;
10276 bfd_vma * local_tlsdesc_gotents;
10277 asection * sgot;
10278 asection * splt;
10279 asection * sreloc = NULL;
10280 asection * srelgot;
10281 bfd_vma addend;
10282 bfd_signed_vma signed_addend;
10283 unsigned char dynreloc_st_type;
10284 bfd_vma dynreloc_value;
ba96a88f 10285 struct elf32_arm_link_hash_table * globals;
34e77a92 10286 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10287 union gotplt_union *root_plt;
10288 struct arm_plt_info *arm_plt;
10289 bfd_vma plt_offset;
10290 bfd_vma gotplt_offset;
10291 bfd_boolean has_iplt_entry;
10292 bfd_boolean resolved_to_zero;
f21f3fe0 10293
9c504268 10294 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10295 if (globals == NULL)
10296 return bfd_reloc_notsupported;
9c504268 10297
0ffa91dd 10298 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10299 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10300
10301 /* Some relocation types map to different relocations depending on the
9c504268 10302 target. We pick the right one here. */
eb043451 10303 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10304
10305 /* It is possible to have linker relaxations on some TLS access
10306 models. Update our information here. */
10307 r_type = elf32_arm_tls_transition (info, r_type, h);
10308
eb043451
PB		 10309 if (r_type != howto->type)
10310 howto = elf32_arm_howto_from_type (r_type);
9c504268 10311
34e77a92 10312 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10313 sgot = globals->root.sgot;
252b5132 10314 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10315 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10316
34e77a92
RS		 10317 if (globals->root.dynamic_sections_created)
10318 srelgot = globals->root.srelgot;
10319 else
10320 srelgot = NULL;
10321
252b5132
RH		 10322 r_symndx = ELF32_R_SYM (rel->r_info);
10323
4e7fd91e 10324 if (globals->use_rel)
ba96a88f 10325 {
4e7fd91e
PB		 10326 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10327
10328 if (addend & ((howto->src_mask + 1) >> 1))
10329 {
10330 signed_addend = -1;
10331 signed_addend &= ~ howto->src_mask;
10332 signed_addend |= addend;
10333 }
10334 else
10335 signed_addend = addend;
ba96a88f
NC		 10336 }
10337 else
4e7fd91e 10338 addend = signed_addend = rel->r_addend;
f21f3fe0 10339
39f21624
NC		 10340 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10341 are resolving a function call relocation. */
10342 if (using_thumb_only (globals)
10343 && (r_type == R_ARM_THM_CALL
10344 || r_type == R_ARM_THM_JUMP24)
10345 && branch_type == ST_BRANCH_TO_ARM)
10346 branch_type = ST_BRANCH_TO_THUMB;
10347
34e77a92
RS		 10348 /* Record the symbol information that should be used in dynamic
10349 relocations. */
10350 dynreloc_st_type = st_type;
10351 dynreloc_value = value;
10352 if (branch_type == ST_BRANCH_TO_THUMB)
10353 dynreloc_value |= 1;
10354
10355 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10356 VALUE appropriately for relocations that we resolve at link time. */
10357 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10358 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10359 &arm_plt)
34e77a92
RS		 10360 && root_plt->offset != (bfd_vma) -1)
10361 {
10362 plt_offset = root_plt->offset;
10363 gotplt_offset = arm_plt->got_offset;
10364
10365 if (h == NULL || eh->is_iplt)
10366 {
10367 has_iplt_entry = TRUE;
10368 splt = globals->root.iplt;
10369
10370 /* Populate .iplt entries here, because not all of them will
10371 be seen by finish_dynamic_symbol. The lower bit is set if
10372 we have already populated the entry. */
10373 if (plt_offset & 1)
10374 plt_offset--;
10375 else
10376 {
57460bcf
NC		 10377 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10378 -1, dynreloc_value))
10379 root_plt->offset |= 1;
10380 else
10381 return bfd_reloc_notsupported;
34e77a92
RS		 10382 }
10383
10384 /* Static relocations always resolve to the .iplt entry. */
10385 st_type = STT_FUNC;
10386 value = (splt->output_section->vma
10387 + splt->output_offset
10388 + plt_offset);
10389 branch_type = ST_BRANCH_TO_ARM;
10390
10391 /* If there are non-call relocations that resolve to the .iplt
10392 entry, then all dynamic ones must too. */
10393 if (arm_plt->noncall_refcount != 0)
10394 {
10395 dynreloc_st_type = st_type;
10396 dynreloc_value = value;
10397 }
10398 }
10399 else
10400 /* We populate the .plt entry in finish_dynamic_symbol. */
10401 splt = globals->root.splt;
10402 }
10403 else
10404 {
10405 splt = NULL;
10406 plt_offset = (bfd_vma) -1;
10407 gotplt_offset = (bfd_vma) -1;
10408 }
10409
95b03e4a
L		 10410 resolved_to_zero = (h != NULL
10411 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10412
252b5132
RH		 10413 switch (r_type)
10414 {
10415 case R_ARM_NONE:
28a094c2
DJ		 10416 /* We don't need to find a value for this symbol. It's just a
10417 marker. */
10418 *unresolved_reloc_p = FALSE;
252b5132
RH		 10419 return bfd_reloc_ok;
10420
00a97672
RS		 10421 case R_ARM_ABS12:
10422 if (!globals->vxworks_p)
10423 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10424 /* Fall through. */
00a97672 10425
252b5132
RH		 10426 case R_ARM_PC24:
10427 case R_ARM_ABS32:
bb224fc3 10428 case R_ARM_ABS32_NOI:
252b5132 10429 case R_ARM_REL32:
bb224fc3 10430 case R_ARM_REL32_NOI:
5b5bb741
PB		 10431 case R_ARM_CALL:
10432 case R_ARM_JUMP24:
dfc5f959 10433 case R_ARM_XPC25:
eb043451 10434 case R_ARM_PREL31:
7359ea65 10435 case R_ARM_PLT32:
7359ea65
DJ		 10436 /* Handle relocations which should use the PLT entry. ABS32/REL32
10437 will use the symbol's value, which may point to a PLT entry, but we
10438 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10439 branches in this object should go to it, except if the PLT is too
10440 far away, in which case a long branch stub should be inserted. */
bb224fc3 10441 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10442 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10443 && r_type != R_ARM_CALL
10444 && r_type != R_ARM_JUMP24
10445 && r_type != R_ARM_PLT32)
34e77a92 10446 && plt_offset != (bfd_vma) -1)
7359ea65 10447 {
34e77a92
RS		 10448 /* If we've created a .plt section, and assigned a PLT entry
10449 to this function, it must either be a STT_GNU_IFUNC reference
10450 or not be known to bind locally. In other cases, we should
10451 have cleared the PLT entry by now. */
10452 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10453
10454 value = (splt->output_section->vma
10455 + splt->output_offset
34e77a92 10456 + plt_offset);
0945cdfd 10457 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10458 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10459 contents, rel->r_offset, value,
00a97672 10460 rel->r_addend);
7359ea65
DJ		 10461 }
10462
67687978
PB		 10463 /* When generating a shared object or relocatable executable, these
10464 relocations are copied into the output file to be resolved at
10465 run time. */
0e1862bb 10466 if ((bfd_link_pic (info)
e8b09b87
CL		 10467 || globals->root.is_relocatable_executable
10468 || globals->fdpic_p)
7359ea65 10469 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10470 && !(globals->vxworks_p
3348747a
NS		 10471 && strcmp (input_section->output_section->name,
10472 ".tls_vars") == 0)
bb224fc3 10473 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10474 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10475 && !(input_bfd == globals->stub_bfd
10476 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10477 && (h == NULL
95b03e4a
L		 10478 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10479 && !resolved_to_zero)
7359ea65
DJ		 10480 || h->root.type != bfd_link_hash_undefweak)
10481 && r_type != R_ARM_PC24
5b5bb741
PB		 10482 && r_type != R_ARM_CALL
10483 && r_type != R_ARM_JUMP24
ee06dc07 10484 && r_type != R_ARM_PREL31
7359ea65 10485 && r_type != R_ARM_PLT32)
252b5132 10486 {
947216bf 10487 Elf_Internal_Rela outrel;
b34976b6 10488 bfd_boolean skip, relocate;
e8b09b87 10489 int isrofixup = 0;
f21f3fe0 10490
52db4ec2
JW		 10491 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10492 && !h->def_regular)
10493 {
10494 char *v = _("shared object");
10495
0e1862bb 10496 if (bfd_link_executable (info))
52db4ec2
JW		 10497 v = _("PIE executable");
10498
4eca0228 10499 _bfd_error_handler
871b3ab2 10500 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10501 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10502 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10503 return bfd_reloc_notsupported;
10504 }
10505
0945cdfd
DJ		 10506 *unresolved_reloc_p = FALSE;
10507
34e77a92 10508 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10509 {
83bac4b0
NC		 10510 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10511 ! globals->use_rel);
f21f3fe0 10512
83bac4b0 10513 if (sreloc == NULL)
252b5132 10514 return bfd_reloc_notsupported;
252b5132 10515 }
f21f3fe0 10516
b34976b6
AM		 10517 skip = FALSE;
10518 relocate = FALSE;
f21f3fe0 10519
00a97672 10520 outrel.r_addend = addend;
c629eae0
JJ		 10521 outrel.r_offset =
10522 _bfd_elf_section_offset (output_bfd, info, input_section,
10523 rel->r_offset);
10524 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10525 skip = TRUE;
0bb2d96a 10526 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10527 skip = TRUE, relocate = TRUE;
252b5132
RH		 10528 outrel.r_offset += (input_section->output_section->vma
10529 + input_section->output_offset);
f21f3fe0 10530
252b5132 10531 if (skip)
0bb2d96a 10532 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10533 else if (h != NULL
10534 && h->dynindx != -1
0e1862bb 10535 && (!bfd_link_pic (info)
1dcb9720
JW		 10536 || !(bfd_link_pie (info)
10537 || SYMBOLIC_BIND (info, h))
f5385ebf 10538 || !h->def_regular))
5e681ec4 10539 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10540 else
10541 {
a16385dc
MM		 10542 int symbol;
10543
5e681ec4 10544 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10545 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10546 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10547 if (globals->symbian_p)
6366ff1e 10548 {
74541ad4
AM		 10549 asection *osec;
10550
6366ff1e
MM		 10551 /* On Symbian OS, the data segment and text segement
10552 can be relocated independently. Therefore, we
10553 must indicate the segment to which this
10554 relocation is relative. The BPABI allows us to
10555 use any symbol in the right segment; we just use
10556 the section symbol as it is convenient. (We
10557 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10558 will not appear in the dynamic symbol table.)
10559
10560 Note that the dynamic linker ignores the section
10561 symbol value, so we don't subtract osec->vma
10562 from the emitted reloc addend. */
10dbd1f3 10563 if (sym_sec)
74541ad4 10564 osec = sym_sec->output_section;
10dbd1f3 10565 else
74541ad4
AM		 10566 osec = input_section->output_section;
10567 symbol = elf_section_data (osec)->dynindx;
10568 if (symbol == 0)
10569 {
10570 struct elf_link_hash_table *htab = elf_hash_table (info);
10571
10572 if ((osec->flags & SEC_READONLY) == 0
10573 && htab->data_index_section != NULL)
10574 osec = htab->data_index_section;
10575 else
10576 osec = htab->text_index_section;
10577 symbol = elf_section_data (osec)->dynindx;
10578 }
6366ff1e
MM		 10579 BFD_ASSERT (symbol != 0);
10580 }
a16385dc
MM		 10581 else
10582 /* On SVR4-ish systems, the dynamic loader cannot
10583 relocate the text and data segments independently,
10584 so the symbol does not matter. */
10585 symbol = 0;
34e77a92
RS		 10586 if (dynreloc_st_type == STT_GNU_IFUNC)
10587 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10588 to the .iplt entry. Instead, every non-call reference
10589 must use an R_ARM_IRELATIVE relocation to obtain the
10590 correct run-time address. */
10591 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10592 else if (globals->fdpic_p && !bfd_link_pic(info))
10593 isrofixup = 1;
34e77a92
RS		 10594 else
10595 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10596 if (globals->use_rel)
10597 relocate = TRUE;
10598 else
34e77a92 10599 outrel.r_addend += dynreloc_value;
252b5132 10600 }
f21f3fe0 10601
e8b09b87
CL		 10602 if (isrofixup)
10603 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10604 else
10605 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10606
f21f3fe0 10607 /* If this reloc is against an external symbol, we do not want to
252b5132 10608 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10609 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10610 if (! relocate)
10611 return bfd_reloc_ok;
9a5aca8c 10612
f21f3fe0 10613 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10614 contents, rel->r_offset,
10615 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10616 }
10617 else switch (r_type)
10618 {
00a97672
RS		 10619 case R_ARM_ABS12:
10620 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10621
dfc5f959 10622 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10623 case R_ARM_CALL:
10624 case R_ARM_JUMP24:
8029a119 10625 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10626 case R_ARM_PLT32:
906e58ca 10627 {
906e58ca
NC		 10628 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10629
dfc5f959 10630 if (r_type == R_ARM_XPC25)
252b5132 10631 {
dfc5f959
NC		 10632 /* Check for Arm calling Arm function. */
10633 /* FIXME: Should we translate the instruction into a BL
10634 instruction instead ? */
35fc36a8 10635 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10636 _bfd_error_handler
90b6238f
AM		 10637 (_("\%pB: warning: %s BLX instruction targets"
10638 " %s function '%s'"),
10639 input_bfd, "ARM",
10640 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10641 }
155d87d7 10642 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10643 {
10644 /* Check for Arm calling Thumb function. */
35fc36a8 10645 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10646 {
f2a9dd69
DJ		 10647 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10648 output_bfd, input_section,
10649 hit_data, sym_sec, rel->r_offset,
10650 signed_addend, value,
10651 error_message))
10652 return bfd_reloc_ok;
10653 else
10654 return bfd_reloc_dangerous;
dfc5f959 10655 }
252b5132 10656 }
ba96a88f 10657
906e58ca 10658 /* Check if a stub has to be inserted because the
8029a119 10659 destination is too far or we are changing mode. */
155d87d7
CL		 10660 if ( r_type == R_ARM_CALL
10661 || r_type == R_ARM_JUMP24
10662 || r_type == R_ARM_PLT32)
906e58ca 10663 {
fe33d2fa
CL		 10664 enum elf32_arm_stub_type stub_type = arm_stub_none;
10665 struct elf32_arm_link_hash_entry *hash;
10666
10667 hash = (struct elf32_arm_link_hash_entry *) h;
10668 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10669 st_type, &branch_type,
10670 hash, value, sym_sec,
fe33d2fa 10671 input_bfd, sym_name);
5fa9e92f 10672
fe33d2fa 10673 if (stub_type != arm_stub_none)
906e58ca
NC		 10674 {
10675 /* The target is out of reach, so redirect the
10676 branch to the local stub for this function. */
906e58ca
NC		 10677 stub_entry = elf32_arm_get_stub_entry (input_section,
10678 sym_sec, h,
fe33d2fa
CL		 10679 rel, globals,
10680 stub_type);
9cd3e4e5
NC		 10681 {
10682 if (stub_entry != NULL)
10683 value = (stub_entry->stub_offset
10684 + stub_entry->stub_sec->output_offset
10685 + stub_entry->stub_sec->output_section->vma);
10686
10687 if (plt_offset != (bfd_vma) -1)
10688 *unresolved_reloc_p = FALSE;
10689 }
906e58ca 10690 }
fe33d2fa
CL		 10691 else
10692 {
10693 /* If the call goes through a PLT entry, make sure to
10694 check distance to the right destination address. */
34e77a92 10695 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10696 {
10697 value = (splt->output_section->vma
10698 + splt->output_offset
34e77a92 10699 + plt_offset);
fe33d2fa
CL		 10700 *unresolved_reloc_p = FALSE;
10701 /* The PLT entry is in ARM mode, regardless of the
10702 target function. */
35fc36a8 10703 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10704 }
10705 }
906e58ca
NC		 10706 }
10707
dea514f5
PB		 10708 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10709 where:
10710 S is the address of the symbol in the relocation.
10711 P is address of the instruction being relocated.
10712 A is the addend (extracted from the instruction) in bytes.
10713
10714 S is held in 'value'.
10715 P is the base address of the section containing the
10716 instruction plus the offset of the reloc into that
10717 section, ie:
10718 (input_section->output_section->vma +
10719 input_section->output_offset +
10720 rel->r_offset).
10721 A is the addend, converted into bytes, ie:
10722 (signed_addend * 4)
10723
10724 Note: None of these operations have knowledge of the pipeline
10725 size of the processor, thus it is up to the assembler to
10726 encode this information into the addend. */
10727 value -= (input_section->output_section->vma
10728 + input_section->output_offset);
10729 value -= rel->r_offset;
4e7fd91e
PB		 10730 if (globals->use_rel)
10731 value += (signed_addend << howto->size);
10732 else
10733 /* RELA addends do not have to be adjusted by howto->size. */
10734 value += signed_addend;
23080146 10735
dcb5e6e6
NC		 10736 signed_addend = value;
10737 signed_addend >>= howto->rightshift;
9a5aca8c 10738
5ab79981 10739 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10740 the next instruction unless a PLT entry will be created.
77b4f08f 10741 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10742 The jump to the next instruction is optimized as a NOP depending
10743 on the architecture. */
ffcb4889 10744 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10745 && plt_offset == (bfd_vma) -1)
77b4f08f 10746 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10747 {
cd1dac3d
DG		 10748 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10749
10750 if (arch_has_arm_nop (globals))
10751 value |= 0x0320f000;
10752 else
10753 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10754 }
10755 else
59f2c4e7 10756 {
9b485d32 10757 /* Perform a signed range check. */
dcb5e6e6 10758 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10759 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10760 return bfd_reloc_overflow;
9a5aca8c 10761
5ab79981 10762 addend = (value & 2);
39b41c9c 10763
5ab79981
PB		 10764 value = (signed_addend & howto->dst_mask)
10765 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10766
5ab79981
PB		 10767 if (r_type == R_ARM_CALL)
10768 {
155d87d7 10769 /* Set the H bit in the BLX instruction. */
35fc36a8 10770 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10771 {
10772 if (addend)
10773 value |= (1 << 24);
10774 else
10775 value &= ~(bfd_vma)(1 << 24);
10776 }
10777
5ab79981 10778 /* Select the correct instruction (BL or BLX). */
906e58ca 10779 /* Only if we are not handling a BL to a stub. In this
8029a119 10780 case, mode switching is performed by the stub. */
35fc36a8 10781 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10782 value |= (1 << 28);
63e1a0fc 10783 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10784 {
10785 value &= ~(bfd_vma)(1 << 28);
10786 value |= (1 << 24);
10787 }
39b41c9c
PB		 10788 }
10789 }
906e58ca 10790 }
252b5132 10791 break;
f21f3fe0 10792
252b5132
RH		 10793 case R_ARM_ABS32:
10794 value += addend;
35fc36a8 10795 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10796 value |= 1;
10797 break;
f21f3fe0 10798
bb224fc3
MS		 10799 case R_ARM_ABS32_NOI:
10800 value += addend;
10801 break;
10802
252b5132 10803 case R_ARM_REL32:
a8bc6c78 10804 value += addend;
35fc36a8 10805 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10806 value |= 1;
252b5132 10807 value -= (input_section->output_section->vma
62efb346 10808 + input_section->output_offset + rel->r_offset);
252b5132 10809 break;
eb043451 10810
bb224fc3
MS		 10811 case R_ARM_REL32_NOI:
10812 value += addend;
10813 value -= (input_section->output_section->vma
10814 + input_section->output_offset + rel->r_offset);
10815 break;
10816
eb043451
PB		 10817 case R_ARM_PREL31:
10818 value -= (input_section->output_section->vma
10819 + input_section->output_offset + rel->r_offset);
10820 value += signed_addend;
10821 if (! h || h->root.type != bfd_link_hash_undefweak)
10822 {
8029a119 10823 /* Check for overflow. */
eb043451
PB		 10824 if ((value ^ (value >> 1)) & (1 << 30))
10825 return bfd_reloc_overflow;
10826 }
10827 value &= 0x7fffffff;
10828 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10829 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10830 value |= 1;
10831 break;
252b5132 10832 }
f21f3fe0 10833
252b5132
RH		 10834 bfd_put_32 (input_bfd, value, hit_data);
10835 return bfd_reloc_ok;
10836
10837 case R_ARM_ABS8:
fd0fd00c
MJ		 10838 /* PR 16202: Refectch the addend using the correct size. */
10839 if (globals->use_rel)
10840 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10841 value += addend;
4e67d4ca
DG		 10842
10843 /* There is no way to tell whether the user intended to use a signed or
10844 unsigned addend. When checking for overflow we accept either,
10845 as specified by the AAELF. */
10846 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10847 return bfd_reloc_overflow;
10848
10849 bfd_put_8 (input_bfd, value, hit_data);
10850 return bfd_reloc_ok;
10851
10852 case R_ARM_ABS16:
fd0fd00c
MJ		 10853 /* PR 16202: Refectch the addend using the correct size. */
10854 if (globals->use_rel)
10855 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10856 value += addend;
10857
4e67d4ca
DG		 10858 /* See comment for R_ARM_ABS8. */
10859 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10860 return bfd_reloc_overflow;
10861
10862 bfd_put_16 (input_bfd, value, hit_data);
10863 return bfd_reloc_ok;
10864
252b5132 10865 case R_ARM_THM_ABS5:
9b485d32 10866 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10867 if (globals->use_rel)
10868 {
10869 /* Need to refetch addend. */
10870 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10871 /* ??? Need to determine shift amount from operand size. */
10872 addend >>= howto->rightshift;
10873 }
252b5132
RH		 10874 value += addend;
10875
10876 /* ??? Isn't value unsigned? */
10877 if ((long) value > 0x1f || (long) value < -0x10)
10878 return bfd_reloc_overflow;
10879
10880 /* ??? Value needs to be properly shifted into place first. */
10881 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10882 bfd_put_16 (input_bfd, value, hit_data);
10883 return bfd_reloc_ok;
10884
2cab6cc3
MS		 10885 case R_ARM_THM_ALU_PREL_11_0:
10886 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10887 {
10888 bfd_vma insn;
10889 bfd_signed_vma relocation;
10890
10891 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10892 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10893
99059e56
RM		 10894 if (globals->use_rel)
10895 {
10896 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10897 | ((insn & (1 << 26)) >> 15);
10898 if (insn & 0xf00000)
10899 signed_addend = -signed_addend;
10900 }
2cab6cc3
MS		 10901
10902 relocation = value + signed_addend;
79f08007 10903 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10904 + input_section->output_offset
10905 + rel->r_offset);
2cab6cc3 10906
8c65b54f
CS		 10907 /* PR 21523: Use an absolute value. The user of this reloc will
10908 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10909 value = llabs (relocation);
2cab6cc3 10910
99059e56
RM		 10911 if (value >= 0x1000)
10912 return bfd_reloc_overflow;
2cab6cc3 10913
e645cf40
AG		 10914 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10915 if (branch_type == ST_BRANCH_TO_THUMB)
10916 value |= 1;
10917
2cab6cc3 10918 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10919 | ((value & 0x700) << 4)
10920 | ((value & 0x800) << 15);
10921 if (relocation < 0)
10922 insn |= 0xa00000;
2cab6cc3
MS		 10923
10924 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10925 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10926
99059e56 10927 return bfd_reloc_ok;
2cab6cc3
MS		 10928 }
10929
e1ec24c6
NC		 10930 case R_ARM_THM_PC8:
10931 /* PR 10073: This reloc is not generated by the GNU toolchain,
10932 but it is supported for compatibility with third party libraries
10933 generated by other compilers, specifically the ARM/IAR. */
10934 {
10935 bfd_vma insn;
10936 bfd_signed_vma relocation;
10937
10938 insn = bfd_get_16 (input_bfd, hit_data);
10939
99059e56 10940 if (globals->use_rel)
79f08007 10941 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10942
10943 relocation = value + addend;
79f08007 10944 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10945 + input_section->output_offset
10946 + rel->r_offset);
e1ec24c6 10947
b6518b38 10948 value = relocation;
e1ec24c6
NC		 10949
10950 /* We do not check for overflow of this reloc. Although strictly
10951 speaking this is incorrect, it appears to be necessary in order
10952 to work with IAR generated relocs. Since GCC and GAS do not
10953 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10954 a problem for them. */
10955 value &= 0x3fc;
10956
10957 insn = (insn & 0xff00) | (value >> 2);
10958
10959 bfd_put_16 (input_bfd, insn, hit_data);
10960
99059e56 10961 return bfd_reloc_ok;
e1ec24c6
NC		 10962 }
10963
2cab6cc3
MS		 10964 case R_ARM_THM_PC12:
10965 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10966 {
10967 bfd_vma insn;
10968 bfd_signed_vma relocation;
10969
10970 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10971 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10972
99059e56
RM		 10973 if (globals->use_rel)
10974 {
10975 signed_addend = insn & 0xfff;
10976 if (!(insn & (1 << 23)))
10977 signed_addend = -signed_addend;
10978 }
2cab6cc3
MS		 10979
10980 relocation = value + signed_addend;
79f08007 10981 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10982 + input_section->output_offset
10983 + rel->r_offset);
2cab6cc3 10984
b6518b38 10985 value = relocation;
2cab6cc3 10986
99059e56
RM		 10987 if (value >= 0x1000)
10988 return bfd_reloc_overflow;
2cab6cc3
MS		 10989
10990 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10991 if (relocation >= 0)
10992 insn |= (1 << 23);
2cab6cc3
MS		 10993
10994 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10995 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10996
99059e56 10997 return bfd_reloc_ok;
2cab6cc3
MS		 10998 }
10999
dfc5f959 11000 case R_ARM_THM_XPC22:
c19d1205 11001 case R_ARM_THM_CALL:
bd97cb95 11002 case R_ARM_THM_JUMP24:
dfc5f959 11003 /* Thumb BL (branch long instruction). */
252b5132 11004 {
b34976b6 11005 bfd_vma relocation;
99059e56 11006 bfd_vma reloc_sign;
b34976b6
AM		 11007 bfd_boolean overflow = FALSE;
11008 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11009 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11010 bfd_signed_vma reloc_signed_max;
11011 bfd_signed_vma reloc_signed_min;
b34976b6 11012 bfd_vma check;
252b5132 11013 bfd_signed_vma signed_check;
e95de063 11014 int bitsize;
cd1dac3d 11015 const int thumb2 = using_thumb2 (globals);
5e866f5a 11016 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11017
5ab79981 11018 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11019 the next instruction unless a PLT entry will be created.
11020 The jump to the next instruction is optimized as a NOP.W for
11021 Thumb-2 enabled architectures. */
19540007 11022 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11023 && plt_offset == (bfd_vma) -1)
5ab79981 11024 {
60a019a0 11025 if (thumb2)
cd1dac3d
DG		 11026 {
11027 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11028 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11029 }
11030 else
11031 {
11032 bfd_put_16 (input_bfd, 0xe000, hit_data);
11033 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11034 }
5ab79981
PB		 11035 return bfd_reloc_ok;
11036 }
11037
e95de063 11038 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11039 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11040 if (globals->use_rel)
11041 {
99059e56
RM		 11042 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11043 bfd_vma upper = upper_insn & 0x3ff;
11044 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11045 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11046 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11047 bfd_vma i1 = j1 ^ s ? 0 : 1;
11048 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11049
99059e56
RM		 11050 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11051 /* Sign extend. */
11052 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11053
4e7fd91e
PB		 11054 signed_addend = addend;
11055 }
cb1afa5c 11056
dfc5f959
NC		 11057 if (r_type == R_ARM_THM_XPC22)
11058 {
11059 /* Check for Thumb to Thumb call. */
11060 /* FIXME: Should we translate the instruction into a BL
11061 instruction instead ? */
35fc36a8 11062 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11063 _bfd_error_handler
90b6238f
AM		 11064 (_("%pB: warning: %s BLX instruction targets"
11065 " %s function '%s'"),
11066 input_bfd, "Thumb",
11067 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11068 }
11069 else
252b5132 11070 {
dfc5f959
NC		 11071 /* If it is not a call to Thumb, assume call to Arm.
11072 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11073 function call at all, but rather a long jump. Calls through
11074 the PLT do not require stubs. */
34e77a92 11075 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11076 {
bd97cb95 11077 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11078 {
11079 /* Convert BL to BLX. */
11080 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11081 }
155d87d7
CL		 11082 else if (( r_type != R_ARM_THM_CALL)
11083 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11084 {
11085 if (elf32_thumb_to_arm_stub
11086 (info, sym_name, input_bfd, output_bfd, input_section,
11087 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11088 error_message))
11089 return bfd_reloc_ok;
11090 else
11091 return bfd_reloc_dangerous;
11092 }
da5938a2 11093 }
35fc36a8
RS		 11094 else if (branch_type == ST_BRANCH_TO_THUMB
11095 && globals->use_blx
bd97cb95 11096 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11097 {
11098 /* Make sure this is a BL. */
11099 lower_insn |= 0x1800;
11100 }
252b5132 11101 }
f21f3fe0 11102
fe33d2fa 11103 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11104 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11105 {
11106 /* Check if a stub has to be inserted because the destination
8029a119 11107 is too far. */
fe33d2fa
CL		 11108 struct elf32_arm_stub_hash_entry *stub_entry;
11109 struct elf32_arm_link_hash_entry *hash;
11110
11111 hash = (struct elf32_arm_link_hash_entry *) h;
11112
11113 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11114 st_type, &branch_type,
11115 hash, value, sym_sec,
fe33d2fa
CL		 11116 input_bfd, sym_name);
11117
11118 if (stub_type != arm_stub_none)
906e58ca
NC		 11119 {
11120 /* The target is out of reach or we are changing modes, so
11121 redirect the branch to the local stub for this
11122 function. */
11123 stub_entry = elf32_arm_get_stub_entry (input_section,
11124 sym_sec, h,
fe33d2fa
CL		 11125 rel, globals,
11126 stub_type);
906e58ca 11127 if (stub_entry != NULL)
9cd3e4e5
NC		 11128 {
11129 value = (stub_entry->stub_offset
11130 + stub_entry->stub_sec->output_offset
11131 + stub_entry->stub_sec->output_section->vma);
11132
11133 if (plt_offset != (bfd_vma) -1)
11134 *unresolved_reloc_p = FALSE;
11135 }
906e58ca 11136
f4ac8484 11137 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11138 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11139 {
11140 if ((stub_entry
11141 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11142 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11143 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11144 }
906e58ca
NC		 11145 }
11146 }
11147
fe33d2fa 11148 /* Handle calls via the PLT. */
34e77a92 11149 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11150 {
11151 value = (splt->output_section->vma
11152 + splt->output_offset
34e77a92 11153 + plt_offset);
fe33d2fa 11154
eed94f8f
NC		 11155 if (globals->use_blx
11156 && r_type == R_ARM_THM_CALL
11157 && ! using_thumb_only (globals))
fe33d2fa
CL		 11158 {
11159 /* If the Thumb BLX instruction is available, convert
11160 the BL to a BLX instruction to call the ARM-mode
11161 PLT entry. */
11162 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11163 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11164 }
11165 else
11166 {
eed94f8f
NC		 11167 if (! using_thumb_only (globals))
11168 /* Target the Thumb stub before the ARM PLT entry. */
11169 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11170 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11171 }
11172 *unresolved_reloc_p = FALSE;
11173 }
11174
ba96a88f 11175 relocation = value + signed_addend;
f21f3fe0 11176
252b5132 11177 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11178 + input_section->output_offset
11179 + rel->r_offset);
9a5aca8c 11180
252b5132
RH		 11181 check = relocation >> howto->rightshift;
11182
11183 /* If this is a signed value, the rightshift just dropped
11184 leading 1 bits (assuming twos complement). */
11185 if ((bfd_signed_vma) relocation >= 0)
11186 signed_check = check;
11187 else
11188 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11189
e95de063
MS		 11190 /* Calculate the permissable maximum and minimum values for
11191 this relocation according to whether we're relocating for
11192 Thumb-2 or not. */
11193 bitsize = howto->bitsize;
5e866f5a 11194 if (!thumb2_bl)
e95de063 11195 bitsize -= 2;
f6ebfac0 11196 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11197 reloc_signed_min = ~reloc_signed_max;
11198
252b5132 11199 /* Assumes two's complement. */
ba96a88f 11200 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11201 overflow = TRUE;
252b5132 11202
bd97cb95 11203 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11204 /* For a BLX instruction, make sure that the relocation is rounded up
11205 to a word boundary. This follows the semantics of the instruction
11206 which specifies that bit 1 of the target address will come from bit
11207 1 of the base address. */
11208 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11209
e95de063
MS		 11210 /* Put RELOCATION back into the insn. Assumes two's complement.
11211 We use the Thumb-2 encoding, which is safe even if dealing with
11212 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11213 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11214 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11215 | ((relocation >> 12) & 0x3ff)
11216 | (reloc_sign << 10);
906e58ca 11217 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11218 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11219 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11220 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11221
252b5132
RH		 11222 /* Put the relocated value back in the object file: */
11223 bfd_put_16 (input_bfd, upper_insn, hit_data);
11224 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11225
11226 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11227 }
11228 break;
11229
c19d1205
ZW		 11230 case R_ARM_THM_JUMP19:
11231 /* Thumb32 conditional branch instruction. */
11232 {
11233 bfd_vma relocation;
11234 bfd_boolean overflow = FALSE;
11235 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11236 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11237 bfd_signed_vma reloc_signed_max = 0xffffe;
11238 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11239 bfd_signed_vma signed_check;
07d6d2b8 11240 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11241 struct elf32_arm_stub_hash_entry *stub_entry;
11242 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11243
11244 /* Need to refetch the addend, reconstruct the top three bits,
11245 and squish the two 11 bit pieces together. */
11246 if (globals->use_rel)
11247 {
11248 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11249 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11250 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11251 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11252 bfd_vma lower = (lower_insn & 0x07ff);
11253
a00a1f35
MS		 11254 upper |= J1 << 6;
11255 upper |= J2 << 7;
11256 upper |= (!S) << 8;
c19d1205
ZW		 11257 upper -= 0x0100; /* Sign extend. */
11258
11259 addend = (upper << 12) | (lower << 1);
11260 signed_addend = addend;
11261 }
11262
bd97cb95 11263 /* Handle calls via the PLT. */
34e77a92 11264 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11265 {
11266 value = (splt->output_section->vma
11267 + splt->output_offset
34e77a92 11268 + plt_offset);
bd97cb95
DJ		 11269 /* Target the Thumb stub before the ARM PLT entry. */
11270 value -= PLT_THUMB_STUB_SIZE;
11271 *unresolved_reloc_p = FALSE;
11272 }
11273
c5423981
TG		 11274 hash = (struct elf32_arm_link_hash_entry *)h;
11275
11276 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11277 st_type, &branch_type,
11278 hash, value, sym_sec,
11279 input_bfd, sym_name);
c5423981
TG		 11280 if (stub_type != arm_stub_none)
11281 {
11282 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11283 sym_sec, h,
11284 rel, globals,
11285 stub_type);
c5423981
TG		 11286 if (stub_entry != NULL)
11287 {
07d6d2b8
AM		 11288 value = (stub_entry->stub_offset
11289 + stub_entry->stub_sec->output_offset
11290 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11291 }
11292 }
c19d1205 11293
99059e56 11294 relocation = value + signed_addend;
c19d1205
ZW		 11295 relocation -= (input_section->output_section->vma
11296 + input_section->output_offset
11297 + rel->r_offset);
a00a1f35 11298 signed_check = (bfd_signed_vma) relocation;
c19d1205 11299
c19d1205
ZW		 11300 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11301 overflow = TRUE;
11302
11303 /* Put RELOCATION back into the insn. */
11304 {
11305 bfd_vma S = (relocation & 0x00100000) >> 20;
11306 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11307 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11308 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11309 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11310
a00a1f35 11311 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11312 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11313 }
11314
11315 /* Put the relocated value back in the object file: */
11316 bfd_put_16 (input_bfd, upper_insn, hit_data);
11317 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11318
11319 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11320 }
11321
11322 case R_ARM_THM_JUMP11:
11323 case R_ARM_THM_JUMP8:
11324 case R_ARM_THM_JUMP6:
51c5503b
NC		 11325 /* Thumb B (branch) instruction). */
11326 {
6cf9e9fe 11327 bfd_signed_vma relocation;
51c5503b
NC		 11328 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11329 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11330 bfd_signed_vma signed_check;
11331
c19d1205
ZW		 11332 /* CZB cannot jump backward. */
11333 if (r_type == R_ARM_THM_JUMP6)
11334 reloc_signed_min = 0;
11335
4e7fd91e 11336 if (globals->use_rel)
6cf9e9fe 11337 {
4e7fd91e
PB		 11338 /* Need to refetch addend. */
11339 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11340 if (addend & ((howto->src_mask + 1) >> 1))
11341 {
11342 signed_addend = -1;
11343 signed_addend &= ~ howto->src_mask;
11344 signed_addend |= addend;
11345 }
11346 else
11347 signed_addend = addend;
11348 /* The value in the insn has been right shifted. We need to
11349 undo this, so that we can perform the address calculation
11350 in terms of bytes. */
11351 signed_addend <<= howto->rightshift;
6cf9e9fe 11352 }
6cf9e9fe 11353 relocation = value + signed_addend;
51c5503b
NC		 11354
11355 relocation -= (input_section->output_section->vma
11356 + input_section->output_offset
11357 + rel->r_offset);
11358
6cf9e9fe
NC		 11359 relocation >>= howto->rightshift;
11360 signed_check = relocation;
c19d1205
ZW		 11361
11362 if (r_type == R_ARM_THM_JUMP6)
11363 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11364 else
11365 relocation &= howto->dst_mask;
51c5503b 11366 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11367
51c5503b
NC		 11368 bfd_put_16 (input_bfd, relocation, hit_data);
11369
11370 /* Assumes two's complement. */
11371 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11372 return bfd_reloc_overflow;
11373
11374 return bfd_reloc_ok;
11375 }
cedb70c5 11376
8375c36b
PB		 11377 case R_ARM_ALU_PCREL7_0:
11378 case R_ARM_ALU_PCREL15_8:
11379 case R_ARM_ALU_PCREL23_15:
11380 {
11381 bfd_vma insn;
11382 bfd_vma relocation;
11383
11384 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11385 if (globals->use_rel)
11386 {
11387 /* Extract the addend. */
11388 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11389 signed_addend = addend;
11390 }
8375c36b
PB		 11391 relocation = value + signed_addend;
11392
11393 relocation -= (input_section->output_section->vma
11394 + input_section->output_offset
11395 + rel->r_offset);
11396 insn = (insn & ~0xfff)
11397 | ((howto->bitpos << 7) & 0xf00)
11398 | ((relocation >> howto->bitpos) & 0xff);
11399 bfd_put_32 (input_bfd, value, hit_data);
11400 }
11401 return bfd_reloc_ok;
11402
252b5132
RH		 11403 case R_ARM_GNU_VTINHERIT:
11404 case R_ARM_GNU_VTENTRY:
11405 return bfd_reloc_ok;
11406
c19d1205 11407 case R_ARM_GOTOFF32:
252b5132 11408 /* Relocation is relative to the start of the
99059e56 11409 global offset table. */
252b5132
RH		 11410
11411 BFD_ASSERT (sgot != NULL);
11412 if (sgot == NULL)
99059e56 11413 return bfd_reloc_notsupported;
9a5aca8c 11414
cedb70c5 11415 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11416 address by one, so that attempts to call the function pointer will
11417 correctly interpret it as Thumb code. */
35fc36a8 11418 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11419 value += 1;
11420
252b5132 11421 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11422 calculation. We always want the start of .got. If we
11423 define _GLOBAL_OFFSET_TABLE in a different way, as is
11424 permitted by the ABI, we might have to change this
11425 calculation. */
252b5132 11426 value -= sgot->output_section->vma;
f21f3fe0 11427 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11428 contents, rel->r_offset, value,
00a97672 11429 rel->r_addend);
252b5132
RH		 11430
11431 case R_ARM_GOTPC:
a7c10850 11432 /* Use global offset table as symbol value. */
252b5132 11433 BFD_ASSERT (sgot != NULL);
f21f3fe0 11434
252b5132 11435 if (sgot == NULL)
99059e56 11436 return bfd_reloc_notsupported;
252b5132 11437
0945cdfd 11438 *unresolved_reloc_p = FALSE;
252b5132 11439 value = sgot->output_section->vma;
f21f3fe0 11440 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11441 contents, rel->r_offset, value,
00a97672 11442 rel->r_addend);
f21f3fe0 11443
252b5132 11444 case R_ARM_GOT32:
eb043451 11445 case R_ARM_GOT_PREL:
252b5132 11446 /* Relocation is to the entry for this symbol in the
99059e56 11447 global offset table. */
252b5132
RH		 11448 if (sgot == NULL)
11449 return bfd_reloc_notsupported;
f21f3fe0 11450
34e77a92
RS		 11451 if (dynreloc_st_type == STT_GNU_IFUNC
11452 && plt_offset != (bfd_vma) -1
11453 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11454 {
11455 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11456 symbol, and the relocation resolves directly to the runtime
11457 target rather than to the .iplt entry. This means that any
11458 .got entry would be the same value as the .igot.plt entry,
11459 so there's no point creating both. */
11460 sgot = globals->root.igotplt;
11461 value = sgot->output_offset + gotplt_offset;
11462 }
11463 else if (h != NULL)
252b5132
RH		 11464 {
11465 bfd_vma off;
f21f3fe0 11466
252b5132
RH		 11467 off = h->got.offset;
11468 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11469 if ((off & 1) != 0)
252b5132 11470 {
b436d854
RS		 11471 /* We have already processsed one GOT relocation against
11472 this symbol. */
11473 off &= ~1;
11474 if (globals->root.dynamic_sections_created
11475 && !SYMBOL_REFERENCES_LOCAL (info, h))
11476 *unresolved_reloc_p = FALSE;
11477 }
11478 else
11479 {
11480 Elf_Internal_Rela outrel;
e8b09b87 11481 int isrofixup = 0;
b436d854 11482
e8b09b87
CL		 11483 if (((h->dynindx != -1) || globals->fdpic_p)
11484 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11485 {
11486 /* If the symbol doesn't resolve locally in a static
11487 object, we have an undefined reference. If the
11488 symbol doesn't resolve locally in a dynamic object,
11489 it should be resolved by the dynamic linker. */
11490 if (globals->root.dynamic_sections_created)
11491 {
11492 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11493 *unresolved_reloc_p = FALSE;
11494 }
11495 else
11496 outrel.r_info = 0;
11497 outrel.r_addend = 0;
11498 }
252b5132
RH		 11499 else
11500 {
34e77a92 11501 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11502 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11503 else if (bfd_link_pic (info)
11504 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11505 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11506 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11507 else
2376f038
EB		 11508 {
11509 outrel.r_info = 0;
11510 if (globals->fdpic_p)
11511 isrofixup = 1;
11512 }
34e77a92 11513 outrel.r_addend = dynreloc_value;
b436d854 11514 }
ee29b9fb 11515
b436d854
RS		 11516 /* The GOT entry is initialized to zero by default.
11517 See if we should install a different value. */
11518 if (outrel.r_addend != 0
2376f038 11519 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11520 {
11521 bfd_put_32 (output_bfd, outrel.r_addend,
11522 sgot->contents + off);
11523 outrel.r_addend = 0;
252b5132 11524 }
f21f3fe0 11525
2376f038
EB		 11526 if (isrofixup)
11527 arm_elf_add_rofixup (output_bfd,
11528 elf32_arm_hash_table(info)->srofixup,
11529 sgot->output_section->vma
11530 + sgot->output_offset + off);
11531
11532 else if (outrel.r_info != 0)
b436d854
RS		 11533 {
11534 outrel.r_offset = (sgot->output_section->vma
11535 + sgot->output_offset
11536 + off);
11537 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11538 }
2376f038 11539
b436d854
RS		 11540 h->got.offset |= 1;
11541 }
252b5132
RH		 11542 value = sgot->output_offset + off;
11543 }
11544 else
11545 {
11546 bfd_vma off;
f21f3fe0 11547
5025eb7c
AO		 11548 BFD_ASSERT (local_got_offsets != NULL
11549 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11550
252b5132 11551 off = local_got_offsets[r_symndx];
f21f3fe0 11552
252b5132
RH		 11553 /* The offset must always be a multiple of 4. We use the
11554 least significant bit to record whether we have already
9b485d32 11555 generated the necessary reloc. */
252b5132
RH		 11556 if ((off & 1) != 0)
11557 off &= ~1;
11558 else
11559 {
2376f038
EB		 11560 Elf_Internal_Rela outrel;
11561 int isrofixup = 0;
f21f3fe0 11562
2376f038
EB		 11563 if (dynreloc_st_type == STT_GNU_IFUNC)
11564 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11565 else if (bfd_link_pic (info))
11566 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11567 else
252b5132 11568 {
2376f038
EB		 11569 outrel.r_info = 0;
11570 if (globals->fdpic_p)
11571 isrofixup = 1;
11572 }
11573
11574 /* The GOT entry is initialized to zero by default.
11575 See if we should install a different value. */
11576 if (globals->use_rel || outrel.r_info == 0)
11577 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11578
11579 if (isrofixup)
11580 arm_elf_add_rofixup (output_bfd,
11581 globals->srofixup,
11582 sgot->output_section->vma
11583 + sgot->output_offset + off);
f21f3fe0 11584
2376f038
EB		 11585 else if (outrel.r_info != 0)
11586 {
34e77a92 11587 outrel.r_addend = addend + dynreloc_value;
252b5132 11588 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11589 + sgot->output_offset
252b5132 11590 + off);
47beaa6a 11591 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11592 }
f21f3fe0 11593
252b5132
RH		 11594 local_got_offsets[r_symndx] |= 1;
11595 }
f21f3fe0 11596
252b5132
RH		 11597 value = sgot->output_offset + off;
11598 }
eb043451
PB		 11599 if (r_type != R_ARM_GOT32)
11600 value += sgot->output_section->vma;
9a5aca8c 11601
f21f3fe0 11602 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11603 contents, rel->r_offset, value,
00a97672 11604 rel->r_addend);
f21f3fe0 11605
ba93b8ac
DJ		 11606 case R_ARM_TLS_LDO32:
11607 value = value - dtpoff_base (info);
11608
11609 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11610 contents, rel->r_offset, value,
11611 rel->r_addend);
ba93b8ac
DJ		 11612
11613 case R_ARM_TLS_LDM32:
5c5a4843 11614 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11615 {
11616 bfd_vma off;
11617
362d30a1 11618 if (sgot == NULL)
ba93b8ac
DJ		 11619 abort ();
11620
11621 off = globals->tls_ldm_got.offset;
11622
11623 if ((off & 1) != 0)
11624 off &= ~1;
11625 else
11626 {
11627 /* If we don't know the module number, create a relocation
11628 for it. */
0e1862bb 11629 if (bfd_link_pic (info))
ba93b8ac
DJ		 11630 {
11631 Elf_Internal_Rela outrel;
ba93b8ac 11632
362d30a1 11633 if (srelgot == NULL)
ba93b8ac
DJ		 11634 abort ();
11635
00a97672 11636 outrel.r_addend = 0;
362d30a1
RS		 11637 outrel.r_offset = (sgot->output_section->vma
11638 + sgot->output_offset + off);
ba93b8ac
DJ		 11639 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11640
00a97672
RS		 11641 if (globals->use_rel)
11642 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11643 sgot->contents + off);
ba93b8ac 11644
47beaa6a 11645 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11646 }
11647 else
362d30a1 11648 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11649
11650 globals->tls_ldm_got.offset |= 1;
11651 }
11652
5c5a4843 11653 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11654 {
11655 bfd_put_32(output_bfd,
11656 globals->root.sgot->output_offset + off,
11657 contents + rel->r_offset);
11658
11659 return bfd_reloc_ok;
11660 }
11661 else
11662 {
11663 value = sgot->output_section->vma + sgot->output_offset + off
11664 - (input_section->output_section->vma
11665 + input_section->output_offset + rel->r_offset);
ba93b8ac 11666
e8b09b87
CL		 11667 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11668 contents, rel->r_offset, value,
11669 rel->r_addend);
11670 }
ba93b8ac
DJ		 11671 }
11672
0855e32b
NS		 11673 case R_ARM_TLS_CALL:
11674 case R_ARM_THM_TLS_CALL:
ba93b8ac 11675 case R_ARM_TLS_GD32:
5c5a4843 11676 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11677 case R_ARM_TLS_IE32:
5c5a4843 11678 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11679 case R_ARM_TLS_GOTDESC:
11680 case R_ARM_TLS_DESCSEQ:
11681 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11682 {
0855e32b
NS		 11683 bfd_vma off, offplt;
11684 int indx = 0;
ba93b8ac
DJ		 11685 char tls_type;
11686
0855e32b 11687 BFD_ASSERT (sgot != NULL);
ba93b8ac 11688
ba93b8ac
DJ		 11689 if (h != NULL)
11690 {
11691 bfd_boolean dyn;
11692 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11693 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11694 bfd_link_pic (info),
11695 h)
11696 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11697 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11698 {
11699 *unresolved_reloc_p = FALSE;
11700 indx = h->dynindx;
11701 }
11702 off = h->got.offset;
0855e32b 11703 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11704 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11705 }
11706 else
11707 {
0855e32b 11708 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11709 off = local_got_offsets[r_symndx];
0855e32b 11710 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11711 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11712 }
11713
0855e32b 11714 /* Linker relaxations happens from one of the
b38cadfb 11715 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11716 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11717 tls_type = GOT_TLS_IE;
0855e32b
NS		 11718
11719 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11720
11721 if ((off & 1) != 0)
11722 off &= ~1;
11723 else
11724 {
11725 bfd_boolean need_relocs = FALSE;
11726 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11727 int cur_off = off;
11728
11729 /* The GOT entries have not been initialized yet. Do it
11730 now, and emit any relocations. If both an IE GOT and a
11731 GD GOT are necessary, we emit the GD first. */
11732
0e1862bb 11733 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11734 && (h == NULL
95b03e4a
L		 11735 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11736 && !resolved_to_zero)
ba93b8ac
DJ		 11737 || h->root.type != bfd_link_hash_undefweak))
11738 {
11739 need_relocs = TRUE;
0855e32b 11740 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11741 }
11742
0855e32b
NS		 11743 if (tls_type & GOT_TLS_GDESC)
11744 {
47beaa6a
RS		 11745 bfd_byte *loc;
11746
0855e32b
NS		 11747 /* We should have relaxed, unless this is an undefined
11748 weak symbol. */
11749 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11750 || bfd_link_pic (info));
0855e32b 11751 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11752 <= globals->root.sgotplt->size);
0855e32b
NS		 11753
11754 outrel.r_addend = 0;
11755 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11756 + globals->root.sgotplt->output_offset
11757 + offplt
11758 + globals->sgotplt_jump_table_size);
b38cadfb 11759
0855e32b
NS		 11760 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11761 sreloc = globals->root.srelplt;
11762 loc = sreloc->contents;
11763 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11764 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11765 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11766
11767 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11768
11769 /* For globals, the first word in the relocation gets
11770 the relocation index and the top bit set, or zero,
11771 if we're binding now. For locals, it gets the
11772 symbol's offset in the tls section. */
99059e56 11773 bfd_put_32 (output_bfd,
0855e32b
NS		 11774 !h ? value - elf_hash_table (info)->tls_sec->vma
11775 : info->flags & DF_BIND_NOW ? 0
11776 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11777 globals->root.sgotplt->contents + offplt
11778 + globals->sgotplt_jump_table_size);
11779
0855e32b 11780 /* Second word in the relocation is always zero. */
99059e56 11781 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11782 globals->root.sgotplt->contents + offplt
11783 + globals->sgotplt_jump_table_size + 4);
0855e32b 11784 }
ba93b8ac
DJ		 11785 if (tls_type & GOT_TLS_GD)
11786 {
11787 if (need_relocs)
11788 {
00a97672 11789 outrel.r_addend = 0;
362d30a1
RS		 11790 outrel.r_offset = (sgot->output_section->vma
11791 + sgot->output_offset
00a97672 11792 + cur_off);
ba93b8ac 11793 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11794
00a97672
RS		 11795 if (globals->use_rel)
11796 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11797 sgot->contents + cur_off);
00a97672 11798
47beaa6a 11799 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11800
11801 if (indx == 0)
11802 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11803 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11804 else
11805 {
00a97672 11806 outrel.r_addend = 0;
ba93b8ac
DJ		 11807 outrel.r_info = ELF32_R_INFO (indx,
11808 R_ARM_TLS_DTPOFF32);
11809 outrel.r_offset += 4;
00a97672
RS		 11810
11811 if (globals->use_rel)
11812 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11813 sgot->contents + cur_off + 4);
00a97672 11814
47beaa6a
RS		 11815 elf32_arm_add_dynreloc (output_bfd, info,
11816 srelgot, &outrel);
ba93b8ac
DJ		 11817 }
11818 }
11819 else
11820 {
11821 /* If we are not emitting relocations for a
11822 general dynamic reference, then we must be in a
11823 static link or an executable link with the
11824 symbol binding locally. Mark it as belonging
11825 to module 1, the executable. */
11826 bfd_put_32 (output_bfd, 1,
362d30a1 11827 sgot->contents + cur_off);
ba93b8ac 11828 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11829 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11830 }
11831
11832 cur_off += 8;
11833 }
11834
11835 if (tls_type & GOT_TLS_IE)
11836 {
11837 if (need_relocs)
11838 {
00a97672
RS		 11839 if (indx == 0)
11840 outrel.r_addend = value - dtpoff_base (info);
11841 else
11842 outrel.r_addend = 0;
362d30a1
RS		 11843 outrel.r_offset = (sgot->output_section->vma
11844 + sgot->output_offset
ba93b8ac
DJ		 11845 + cur_off);
11846 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11847
00a97672
RS		 11848 if (globals->use_rel)
11849 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11850 sgot->contents + cur_off);
ba93b8ac 11851
47beaa6a 11852 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11853 }
11854 else
11855 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11856 sgot->contents + cur_off);
ba93b8ac
DJ		 11857 cur_off += 4;
11858 }
11859
11860 if (h != NULL)
11861 h->got.offset |= 1;
11862 else
11863 local_got_offsets[r_symndx] |= 1;
11864 }
11865
5c5a4843 11866 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11867 off += 8;
0855e32b
NS		 11868 else if (tls_type & GOT_TLS_GDESC)
11869 off = offplt;
11870
11871 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11872 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11873 {
11874 bfd_signed_vma offset;
12352d3f
PB		 11875 /* TLS stubs are arm mode. The original symbol is a
11876 data object, so branch_type is bogus. */
11877 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11878 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11879 = arm_type_of_stub (info, input_section, rel,
11880 st_type, &branch_type,
0855e32b
NS		 11881 (struct elf32_arm_link_hash_entry *)h,
11882 globals->tls_trampoline, globals->root.splt,
11883 input_bfd, sym_name);
11884
11885 if (stub_type != arm_stub_none)
11886 {
11887 struct elf32_arm_stub_hash_entry *stub_entry
11888 = elf32_arm_get_stub_entry
11889 (input_section, globals->root.splt, 0, rel,
11890 globals, stub_type);
11891 offset = (stub_entry->stub_offset
11892 + stub_entry->stub_sec->output_offset
11893 + stub_entry->stub_sec->output_section->vma);
11894 }
11895 else
11896 offset = (globals->root.splt->output_section->vma
11897 + globals->root.splt->output_offset
11898 + globals->tls_trampoline);
11899
11900 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11901 {
11902 unsigned long inst;
b38cadfb
NC		 11903
11904 offset -= (input_section->output_section->vma
11905 + input_section->output_offset
11906 + rel->r_offset + 8);
0855e32b
NS		 11907
11908 inst = offset >> 2;
11909 inst &= 0x00ffffff;
11910 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11911 }
11912 else
11913 {
11914 /* Thumb blx encodes the offset in a complicated
11915 fashion. */
11916 unsigned upper_insn, lower_insn;
11917 unsigned neg;
11918
b38cadfb
NC		 11919 offset -= (input_section->output_section->vma
11920 + input_section->output_offset
0855e32b 11921 + rel->r_offset + 4);
b38cadfb 11922
12352d3f
PB		 11923 if (stub_type != arm_stub_none
11924 && arm_stub_is_thumb (stub_type))
11925 {
11926 lower_insn = 0xd000;
11927 }
11928 else
11929 {
11930 lower_insn = 0xc000;
6a631e86 11931 /* Round up the offset to a word boundary. */
12352d3f
PB		 11932 offset = (offset + 2) & ~2;
11933 }
11934
0855e32b
NS		 11935 neg = offset < 0;
11936 upper_insn = (0xf000
11937 | ((offset >> 12) & 0x3ff)
11938 | (neg << 10));
12352d3f 11939 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11940 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11941 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11942 bfd_put_16 (input_bfd, upper_insn, hit_data);
11943 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11944 return bfd_reloc_ok;
11945 }
11946 }
11947 /* These relocations needs special care, as besides the fact
11948 they point somewhere in .gotplt, the addend must be
11949 adjusted accordingly depending on the type of instruction
6a631e86 11950 we refer to. */
0855e32b
NS		 11951 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11952 {
11953 unsigned long data, insn;
11954 unsigned thumb;
b38cadfb 11955
0855e32b
NS		 11956 data = bfd_get_32 (input_bfd, hit_data);
11957 thumb = data & 1;
11958 data &= ~1u;
b38cadfb 11959
0855e32b
NS		 11960 if (thumb)
11961 {
11962 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11963 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11964 insn = (insn << 16)
11965 | bfd_get_16 (input_bfd,
11966 contents + rel->r_offset - data + 2);
11967 if ((insn & 0xf800c000) == 0xf000c000)
11968 /* bl/blx */
11969 value = -6;
11970 else if ((insn & 0xffffff00) == 0x4400)
11971 /* add */
11972 value = -5;
11973 else
11974 {
4eca0228 11975 _bfd_error_handler
695344c0 11976 /* xgettext:c-format */
2dcf00ce 11977 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11978 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11979 "referenced by TLS_GOTDESC"),
11980 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11981 "Thumb", insn);
0855e32b
NS		 11982 return bfd_reloc_notsupported;
11983 }
11984 }
11985 else
11986 {
11987 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11988
11989 switch (insn >> 24)
11990 {
11991 case 0xeb: /* bl */
11992 case 0xfa: /* blx */
11993 value = -4;
11994 break;
11995
11996 case 0xe0: /* add */
11997 value = -8;
11998 break;
b38cadfb 11999
0855e32b 12000 default:
4eca0228 12001 _bfd_error_handler
695344c0 12002 /* xgettext:c-format */
2dcf00ce 12003 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12004 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12005 "referenced by TLS_GOTDESC"),
12006 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12007 "ARM", insn);
0855e32b
NS		 12008 return bfd_reloc_notsupported;
12009 }
12010 }
b38cadfb 12011
0855e32b
NS		 12012 value += ((globals->root.sgotplt->output_section->vma
12013 + globals->root.sgotplt->output_offset + off)
12014 - (input_section->output_section->vma
12015 + input_section->output_offset
12016 + rel->r_offset)
12017 + globals->sgotplt_jump_table_size);
12018 }
12019 else
12020 value = ((globals->root.sgot->output_section->vma
12021 + globals->root.sgot->output_offset + off)
12022 - (input_section->output_section->vma
12023 + input_section->output_offset + rel->r_offset));
ba93b8ac 12024
5c5a4843
CL		 12025 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12026 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12027 {
12028 /* For FDPIC relocations, resolve to the offset of the GOT
12029 entry from the start of GOT. */
12030 bfd_put_32(output_bfd,
12031 globals->root.sgot->output_offset + off,
12032 contents + rel->r_offset);
12033
12034 return bfd_reloc_ok;
12035 }
12036 else
12037 {
12038 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12039 contents, rel->r_offset, value,
12040 rel->r_addend);
12041 }
ba93b8ac
DJ		 12042 }
12043
12044 case R_ARM_TLS_LE32:
3cbc1e5e 12045 if (bfd_link_dll (info))
ba93b8ac 12046 {
4eca0228 12047 _bfd_error_handler
695344c0 12048 /* xgettext:c-format */
2dcf00ce
AM		 12049 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12050 "in shared object"),
12051 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12052 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12053 }
12054 else
12055 value = tpoff (info, value);
906e58ca 12056
ba93b8ac 12057 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12058 contents, rel->r_offset, value,
12059 rel->r_addend);
ba93b8ac 12060
319850b4
JB		 12061 case R_ARM_V4BX:
12062 if (globals->fix_v4bx)
845b51d6
PB		 12063 {
12064 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12065
845b51d6
PB		 12066 /* Ensure that we have a BX instruction. */
12067 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12068
845b51d6
PB		 12069 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12070 {
12071 /* Branch to veneer. */
12072 bfd_vma glue_addr;
12073 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12074 glue_addr -= input_section->output_section->vma
12075 + input_section->output_offset
12076 + rel->r_offset + 8;
12077 insn = (insn & 0xf0000000) | 0x0a000000
12078 | ((glue_addr >> 2) & 0x00ffffff);
12079 }
12080 else
12081 {
12082 /* Preserve Rm (lowest four bits) and the condition code
12083 (highest four bits). Other bits encode MOV PC,Rm. */
12084 insn = (insn & 0xf000000f) | 0x01a0f000;
12085 }
319850b4 12086
845b51d6
PB		 12087 bfd_put_32 (input_bfd, insn, hit_data);
12088 }
319850b4
JB		 12089 return bfd_reloc_ok;
12090
b6895b4f
PB		 12091 case R_ARM_MOVW_ABS_NC:
12092 case R_ARM_MOVT_ABS:
12093 case R_ARM_MOVW_PREL_NC:
12094 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12095 /* Until we properly support segment-base-relative addressing then
12096 we assume the segment base to be zero, as for the group relocations.
12097 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12098 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12099 case R_ARM_MOVW_BREL_NC:
12100 case R_ARM_MOVW_BREL:
12101 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12102 {
12103 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12104
12105 if (globals->use_rel)
12106 {
12107 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12108 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12109 }
92f5d02b 12110
b6895b4f 12111 value += signed_addend;
b6895b4f
PB		 12112
12113 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12114 value -= (input_section->output_section->vma
12115 + input_section->output_offset + rel->r_offset);
12116
92f5d02b 12117 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12118 return bfd_reloc_overflow;
92f5d02b 12119
35fc36a8 12120 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12121 value |= 1;
12122
12123 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12124 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12125 value >>= 16;
12126
12127 insn &= 0xfff0f000;
12128 insn |= value & 0xfff;
12129 insn |= (value & 0xf000) << 4;
12130 bfd_put_32 (input_bfd, insn, hit_data);
12131 }
12132 return bfd_reloc_ok;
12133
12134 case R_ARM_THM_MOVW_ABS_NC:
12135 case R_ARM_THM_MOVT_ABS:
12136 case R_ARM_THM_MOVW_PREL_NC:
12137 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12138 /* Until we properly support segment-base-relative addressing then
12139 we assume the segment base to be zero, as for the above relocations.
12140 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12141 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12142 as R_ARM_THM_MOVT_ABS. */
12143 case R_ARM_THM_MOVW_BREL_NC:
12144 case R_ARM_THM_MOVW_BREL:
12145 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12146 {
12147 bfd_vma insn;
906e58ca 12148
b6895b4f
PB		 12149 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12150 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12151
12152 if (globals->use_rel)
12153 {
12154 addend = ((insn >> 4) & 0xf000)
12155 | ((insn >> 15) & 0x0800)
12156 | ((insn >> 4) & 0x0700)
07d6d2b8 12157 | (insn & 0x00ff);
39623e12 12158 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12159 }
92f5d02b 12160
b6895b4f 12161 value += signed_addend;
b6895b4f
PB		 12162
12163 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12164 value -= (input_section->output_section->vma
12165 + input_section->output_offset + rel->r_offset);
12166
92f5d02b 12167 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12168 return bfd_reloc_overflow;
92f5d02b 12169
35fc36a8 12170 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12171 value |= 1;
12172
12173 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12174 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12175 value >>= 16;
12176
12177 insn &= 0xfbf08f00;
12178 insn |= (value & 0xf000) << 4;
12179 insn |= (value & 0x0800) << 15;
12180 insn |= (value & 0x0700) << 4;
12181 insn |= (value & 0x00ff);
12182
12183 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12184 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12185 }
12186 return bfd_reloc_ok;
12187
4962c51a
MS		 12188 case R_ARM_ALU_PC_G0_NC:
12189 case R_ARM_ALU_PC_G1_NC:
12190 case R_ARM_ALU_PC_G0:
12191 case R_ARM_ALU_PC_G1:
12192 case R_ARM_ALU_PC_G2:
12193 case R_ARM_ALU_SB_G0_NC:
12194 case R_ARM_ALU_SB_G1_NC:
12195 case R_ARM_ALU_SB_G0:
12196 case R_ARM_ALU_SB_G1:
12197 case R_ARM_ALU_SB_G2:
12198 {
12199 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12200 bfd_vma pc = input_section->output_section->vma
4962c51a 12201 + input_section->output_offset + rel->r_offset;
31a91d61 12202 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12203 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12204 bfd_vma residual;
12205 bfd_vma g_n;
4962c51a 12206 bfd_signed_vma signed_value;
99059e56
RM		 12207 int group = 0;
12208
12209 /* Determine which group of bits to select. */
12210 switch (r_type)
12211 {
12212 case R_ARM_ALU_PC_G0_NC:
12213 case R_ARM_ALU_PC_G0:
12214 case R_ARM_ALU_SB_G0_NC:
12215 case R_ARM_ALU_SB_G0:
12216 group = 0;
12217 break;
12218
12219 case R_ARM_ALU_PC_G1_NC:
12220 case R_ARM_ALU_PC_G1:
12221 case R_ARM_ALU_SB_G1_NC:
12222 case R_ARM_ALU_SB_G1:
12223 group = 1;
12224 break;
12225
12226 case R_ARM_ALU_PC_G2:
12227 case R_ARM_ALU_SB_G2:
12228 group = 2;
12229 break;
12230
12231 default:
12232 abort ();
12233 }
12234
12235 /* If REL, extract the addend from the insn. If RELA, it will
12236 have already been fetched for us. */
4962c51a 12237 if (globals->use_rel)
99059e56
RM		 12238 {
12239 int negative;
12240 bfd_vma constant = insn & 0xff;
12241 bfd_vma rotation = (insn & 0xf00) >> 8;
12242
12243 if (rotation == 0)
12244 signed_addend = constant;
12245 else
12246 {
12247 /* Compensate for the fact that in the instruction, the
12248 rotation is stored in multiples of 2 bits. */
12249 rotation *= 2;
12250
12251 /* Rotate "constant" right by "rotation" bits. */
12252 signed_addend = (constant >> rotation) |
12253 (constant << (8 * sizeof (bfd_vma) - rotation));
12254 }
12255
12256 /* Determine if the instruction is an ADD or a SUB.
12257 (For REL, this determines the sign of the addend.) */
12258 negative = identify_add_or_sub (insn);
12259 if (negative == 0)
12260 {
4eca0228 12261 _bfd_error_handler
695344c0 12262 /* xgettext:c-format */
90b6238f 12263 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12264 "are allowed for ALU group relocations"),
12265 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12266 return bfd_reloc_overflow;
12267 }
12268
12269 signed_addend *= negative;
12270 }
4962c51a
MS		 12271
12272 /* Compute the value (X) to go in the place. */
99059e56
RM		 12273 if (r_type == R_ARM_ALU_PC_G0_NC
12274 || r_type == R_ARM_ALU_PC_G1_NC
12275 || r_type == R_ARM_ALU_PC_G0
12276 || r_type == R_ARM_ALU_PC_G1
12277 || r_type == R_ARM_ALU_PC_G2)
12278 /* PC relative. */
12279 signed_value = value - pc + signed_addend;
12280 else
12281 /* Section base relative. */
12282 signed_value = value - sb + signed_addend;
12283
12284 /* If the target symbol is a Thumb function, then set the
12285 Thumb bit in the address. */
35fc36a8 12286 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12287 signed_value |= 1;
12288
99059e56
RM		 12289 /* Calculate the value of the relevant G_n, in encoded
12290 constant-with-rotation format. */
b6518b38
NC		 12291 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12292 group, &residual);
99059e56
RM		 12293
12294 /* Check for overflow if required. */
12295 if ((r_type == R_ARM_ALU_PC_G0
12296 || r_type == R_ARM_ALU_PC_G1
12297 || r_type == R_ARM_ALU_PC_G2
12298 || r_type == R_ARM_ALU_SB_G0
12299 || r_type == R_ARM_ALU_SB_G1
12300 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12301 {
4eca0228 12302 _bfd_error_handler
695344c0 12303 /* xgettext:c-format */
90b6238f 12304 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12305 "splitting %#" PRIx64 " for group relocation %s"),
12306 input_bfd, input_section, (uint64_t) rel->r_offset,
12307 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12308 howto->name);
99059e56
RM		 12309 return bfd_reloc_overflow;
12310 }
12311
12312 /* Mask out the value and the ADD/SUB part of the opcode; take care
12313 not to destroy the S bit. */
12314 insn &= 0xff1ff000;
12315
12316 /* Set the opcode according to whether the value to go in the
12317 place is negative. */
12318 if (signed_value < 0)
12319 insn |= 1 << 22;
12320 else
12321 insn |= 1 << 23;
12322
12323 /* Encode the offset. */
12324 insn |= g_n;
4962c51a
MS		 12325
12326 bfd_put_32 (input_bfd, insn, hit_data);
12327 }
12328 return bfd_reloc_ok;
12329
12330 case R_ARM_LDR_PC_G0:
12331 case R_ARM_LDR_PC_G1:
12332 case R_ARM_LDR_PC_G2:
12333 case R_ARM_LDR_SB_G0:
12334 case R_ARM_LDR_SB_G1:
12335 case R_ARM_LDR_SB_G2:
12336 {
12337 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12338 bfd_vma pc = input_section->output_section->vma
4962c51a 12339 + input_section->output_offset + rel->r_offset;
31a91d61 12340 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12341 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12342 bfd_vma residual;
4962c51a 12343 bfd_signed_vma signed_value;
99059e56
RM		 12344 int group = 0;
12345
12346 /* Determine which groups of bits to calculate. */
12347 switch (r_type)
12348 {
12349 case R_ARM_LDR_PC_G0:
12350 case R_ARM_LDR_SB_G0:
12351 group = 0;
12352 break;
12353
12354 case R_ARM_LDR_PC_G1:
12355 case R_ARM_LDR_SB_G1:
12356 group = 1;
12357 break;
12358
12359 case R_ARM_LDR_PC_G2:
12360 case R_ARM_LDR_SB_G2:
12361 group = 2;
12362 break;
12363
12364 default:
12365 abort ();
12366 }
12367
12368 /* If REL, extract the addend from the insn. If RELA, it will
12369 have already been fetched for us. */
4962c51a 12370 if (globals->use_rel)
99059e56
RM		 12371 {
12372 int negative = (insn & (1 << 23)) ? 1 : -1;
12373 signed_addend = negative * (insn & 0xfff);
12374 }
4962c51a
MS		 12375
12376 /* Compute the value (X) to go in the place. */
99059e56
RM		 12377 if (r_type == R_ARM_LDR_PC_G0
12378 || r_type == R_ARM_LDR_PC_G1
12379 || r_type == R_ARM_LDR_PC_G2)
12380 /* PC relative. */
12381 signed_value = value - pc + signed_addend;
12382 else
12383 /* Section base relative. */
12384 signed_value = value - sb + signed_addend;
12385
12386 /* Calculate the value of the relevant G_{n-1} to obtain
12387 the residual at that stage. */
b6518b38
NC		 12388 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12389 group - 1, &residual);
99059e56
RM		 12390
12391 /* Check for overflow. */
12392 if (residual >= 0x1000)
12393 {
4eca0228 12394 _bfd_error_handler
695344c0 12395 /* xgettext:c-format */
90b6238f 12396 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12397 "splitting %#" PRIx64 " for group relocation %s"),
12398 input_bfd, input_section, (uint64_t) rel->r_offset,
12399 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12400 howto->name);
99059e56
RM		 12401 return bfd_reloc_overflow;
12402 }
12403
12404 /* Mask out the value and U bit. */
12405 insn &= 0xff7ff000;
12406
12407 /* Set the U bit if the value to go in the place is non-negative. */
12408 if (signed_value >= 0)
12409 insn |= 1 << 23;
12410
12411 /* Encode the offset. */
12412 insn |= residual;
4962c51a
MS		 12413
12414 bfd_put_32 (input_bfd, insn, hit_data);
12415 }
12416 return bfd_reloc_ok;
12417
12418 case R_ARM_LDRS_PC_G0:
12419 case R_ARM_LDRS_PC_G1:
12420 case R_ARM_LDRS_PC_G2:
12421 case R_ARM_LDRS_SB_G0:
12422 case R_ARM_LDRS_SB_G1:
12423 case R_ARM_LDRS_SB_G2:
12424 {
12425 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12426 bfd_vma pc = input_section->output_section->vma
4962c51a 12427 + input_section->output_offset + rel->r_offset;
31a91d61 12428 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12429 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12430 bfd_vma residual;
4962c51a 12431 bfd_signed_vma signed_value;
99059e56
RM		 12432 int group = 0;
12433
12434 /* Determine which groups of bits to calculate. */
12435 switch (r_type)
12436 {
12437 case R_ARM_LDRS_PC_G0:
12438 case R_ARM_LDRS_SB_G0:
12439 group = 0;
12440 break;
12441
12442 case R_ARM_LDRS_PC_G1:
12443 case R_ARM_LDRS_SB_G1:
12444 group = 1;
12445 break;
12446
12447 case R_ARM_LDRS_PC_G2:
12448 case R_ARM_LDRS_SB_G2:
12449 group = 2;
12450 break;
12451
12452 default:
12453 abort ();
12454 }
12455
12456 /* If REL, extract the addend from the insn. If RELA, it will
12457 have already been fetched for us. */
4962c51a 12458 if (globals->use_rel)
99059e56
RM		 12459 {
12460 int negative = (insn & (1 << 23)) ? 1 : -1;
12461 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12462 }
4962c51a
MS		 12463
12464 /* Compute the value (X) to go in the place. */
99059e56
RM		 12465 if (r_type == R_ARM_LDRS_PC_G0
12466 || r_type == R_ARM_LDRS_PC_G1
12467 || r_type == R_ARM_LDRS_PC_G2)
12468 /* PC relative. */
12469 signed_value = value - pc + signed_addend;
12470 else
12471 /* Section base relative. */
12472 signed_value = value - sb + signed_addend;
12473
12474 /* Calculate the value of the relevant G_{n-1} to obtain
12475 the residual at that stage. */
b6518b38
NC		 12476 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12477 group - 1, &residual);
99059e56
RM		 12478
12479 /* Check for overflow. */
12480 if (residual >= 0x100)
12481 {
4eca0228 12482 _bfd_error_handler
695344c0 12483 /* xgettext:c-format */
90b6238f 12484 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12485 "splitting %#" PRIx64 " for group relocation %s"),
12486 input_bfd, input_section, (uint64_t) rel->r_offset,
12487 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12488 howto->name);
99059e56
RM		 12489 return bfd_reloc_overflow;
12490 }
12491
12492 /* Mask out the value and U bit. */
12493 insn &= 0xff7ff0f0;
12494
12495 /* Set the U bit if the value to go in the place is non-negative. */
12496 if (signed_value >= 0)
12497 insn |= 1 << 23;
12498
12499 /* Encode the offset. */
12500 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12501
12502 bfd_put_32 (input_bfd, insn, hit_data);
12503 }
12504 return bfd_reloc_ok;
12505
12506 case R_ARM_LDC_PC_G0:
12507 case R_ARM_LDC_PC_G1:
12508 case R_ARM_LDC_PC_G2:
12509 case R_ARM_LDC_SB_G0:
12510 case R_ARM_LDC_SB_G1:
12511 case R_ARM_LDC_SB_G2:
12512 {
12513 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12514 bfd_vma pc = input_section->output_section->vma
4962c51a 12515 + input_section->output_offset + rel->r_offset;
31a91d61 12516 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12517 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12518 bfd_vma residual;
4962c51a 12519 bfd_signed_vma signed_value;
99059e56
RM		 12520 int group = 0;
12521
12522 /* Determine which groups of bits to calculate. */
12523 switch (r_type)
12524 {
12525 case R_ARM_LDC_PC_G0:
12526 case R_ARM_LDC_SB_G0:
12527 group = 0;
12528 break;
12529
12530 case R_ARM_LDC_PC_G1:
12531 case R_ARM_LDC_SB_G1:
12532 group = 1;
12533 break;
12534
12535 case R_ARM_LDC_PC_G2:
12536 case R_ARM_LDC_SB_G2:
12537 group = 2;
12538 break;
12539
12540 default:
12541 abort ();
12542 }
12543
12544 /* If REL, extract the addend from the insn. If RELA, it will
12545 have already been fetched for us. */
4962c51a 12546 if (globals->use_rel)
99059e56
RM		 12547 {
12548 int negative = (insn & (1 << 23)) ? 1 : -1;
12549 signed_addend = negative * ((insn & 0xff) << 2);
12550 }
4962c51a
MS		 12551
12552 /* Compute the value (X) to go in the place. */
99059e56
RM		 12553 if (r_type == R_ARM_LDC_PC_G0
12554 || r_type == R_ARM_LDC_PC_G1
12555 || r_type == R_ARM_LDC_PC_G2)
12556 /* PC relative. */
12557 signed_value = value - pc + signed_addend;
12558 else
12559 /* Section base relative. */
12560 signed_value = value - sb + signed_addend;
12561
12562 /* Calculate the value of the relevant G_{n-1} to obtain
12563 the residual at that stage. */
b6518b38
NC		 12564 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12565 group - 1, &residual);
99059e56
RM		 12566
12567 /* Check for overflow. (The absolute value to go in the place must be
12568 divisible by four and, after having been divided by four, must
12569 fit in eight bits.) */
12570 if ((residual & 0x3) != 0 || residual >= 0x400)
12571 {
4eca0228 12572 _bfd_error_handler
695344c0 12573 /* xgettext:c-format */
90b6238f 12574 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12575 "splitting %#" PRIx64 " for group relocation %s"),
12576 input_bfd, input_section, (uint64_t) rel->r_offset,
12577 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12578 howto->name);
99059e56
RM		 12579 return bfd_reloc_overflow;
12580 }
12581
12582 /* Mask out the value and U bit. */
12583 insn &= 0xff7fff00;
12584
12585 /* Set the U bit if the value to go in the place is non-negative. */
12586 if (signed_value >= 0)
12587 insn |= 1 << 23;
12588
12589 /* Encode the offset. */
12590 insn |= residual >> 2;
4962c51a
MS		 12591
12592 bfd_put_32 (input_bfd, insn, hit_data);
12593 }
12594 return bfd_reloc_ok;
12595
72d98d16
MG		 12596 case R_ARM_THM_ALU_ABS_G0_NC:
12597 case R_ARM_THM_ALU_ABS_G1_NC:
12598 case R_ARM_THM_ALU_ABS_G2_NC:
12599 case R_ARM_THM_ALU_ABS_G3_NC:
12600 {
12601 const int shift_array[4] = {0, 8, 16, 24};
12602 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12603 bfd_vma addr = value;
12604 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12605
12606 /* Compute address. */
12607 if (globals->use_rel)
12608 signed_addend = insn & 0xff;
12609 addr += signed_addend;
12610 if (branch_type == ST_BRANCH_TO_THUMB)
12611 addr |= 1;
12612 /* Clean imm8 insn. */
12613 insn &= 0xff00;
12614 /* And update with correct part of address. */
12615 insn |= (addr >> shift) & 0xff;
12616 /* Update insn. */
12617 bfd_put_16 (input_bfd, insn, hit_data);
12618 }
12619
12620 *unresolved_reloc_p = FALSE;
12621 return bfd_reloc_ok;
12622
e8b09b87
CL		 12623 case R_ARM_GOTOFFFUNCDESC:
12624 {
4b24dd1a 12625 if (h == NULL)
e8b09b87
CL		 12626 {
12627 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12628 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12629 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12630 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12631 bfd_vma seg = -1;
12632
12633 if (bfd_link_pic(info) && dynindx == 0)
12634 abort();
12635
12636 /* Resolve relocation. */
12637 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12638 , contents + rel->r_offset);
12639 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12640 not done yet. */
12641 arm_elf_fill_funcdesc(output_bfd, info,
12642 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12643 dynindx, offset, addr, dynreloc_value, seg);
12644 }
12645 else
12646 {
12647 int dynindx;
12648 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12649 bfd_vma addr;
12650 bfd_vma seg = -1;
12651
12652 /* For static binaries, sym_sec can be null. */
12653 if (sym_sec)
12654 {
12655 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12656 addr = dynreloc_value - sym_sec->output_section->vma;
12657 }
12658 else
12659 {
12660 dynindx = 0;
12661 addr = 0;
12662 }
12663
12664 if (bfd_link_pic(info) && dynindx == 0)
12665 abort();
12666
12667 /* This case cannot occur since funcdesc is allocated by
12668 the dynamic loader so we cannot resolve the relocation. */
12669 if (h->dynindx != -1)
12670 abort();
12671
12672 /* Resolve relocation. */
12673 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12674 contents + rel->r_offset);
12675 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12676 arm_elf_fill_funcdesc(output_bfd, info,
12677 &eh->fdpic_cnts.funcdesc_offset,
12678 dynindx, offset, addr, dynreloc_value, seg);
12679 }
12680 }
12681 *unresolved_reloc_p = FALSE;
12682 return bfd_reloc_ok;
12683
12684 case R_ARM_GOTFUNCDESC:
12685 {
4b24dd1a 12686 if (h != NULL)
e8b09b87
CL		 12687 {
12688 Elf_Internal_Rela outrel;
12689
12690 /* Resolve relocation. */
12691 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12692 + sgot->output_offset),
12693 contents + rel->r_offset);
12694 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12695 if(h->dynindx == -1)
12696 {
12697 int dynindx;
12698 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12699 bfd_vma addr;
12700 bfd_vma seg = -1;
12701
12702 /* For static binaries sym_sec can be null. */
12703 if (sym_sec)
12704 {
12705 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12706 addr = dynreloc_value - sym_sec->output_section->vma;
12707 }
12708 else
12709 {
12710 dynindx = 0;
12711 addr = 0;
12712 }
12713
12714 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12715 arm_elf_fill_funcdesc(output_bfd, info,
12716 &eh->fdpic_cnts.funcdesc_offset,
12717 dynindx, offset, addr, dynreloc_value, seg);
12718 }
12719
12720 /* Add a dynamic relocation on GOT entry if not already done. */
12721 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12722 {
12723 if (h->dynindx == -1)
12724 {
12725 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12726 if (h->root.type == bfd_link_hash_undefweak)
12727 bfd_put_32(output_bfd, 0, sgot->contents
12728 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12729 else
12730 bfd_put_32(output_bfd, sgot->output_section->vma
12731 + sgot->output_offset
12732 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12733 sgot->contents
12734 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12735 }
12736 else
12737 {
12738 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12739 }
12740 outrel.r_offset = sgot->output_section->vma
12741 + sgot->output_offset
12742 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12743 outrel.r_addend = 0;
12744 if (h->dynindx == -1 && !bfd_link_pic(info))
12745 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12746 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12747 else
4b24dd1a
AM		 12748 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12749 outrel.r_offset);
e8b09b87
CL		 12750 else
12751 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12752 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12753 }
12754 }
12755 else
12756 {
12757 /* Such relocation on static function should not have been
12758 emitted by the compiler. */
12759 abort();
12760 }
12761 }
12762 *unresolved_reloc_p = FALSE;
12763 return bfd_reloc_ok;
12764
12765 case R_ARM_FUNCDESC:
12766 {
4b24dd1a 12767 if (h == NULL)
e8b09b87
CL		 12768 {
12769 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12770 Elf_Internal_Rela outrel;
12771 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12772 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12773 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12774 bfd_vma seg = -1;
12775
12776 if (bfd_link_pic(info) && dynindx == 0)
12777 abort();
12778
12779 /* Replace static FUNCDESC relocation with a
12780 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12781 executable. */
12782 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12783 outrel.r_offset = input_section->output_section->vma
12784 + input_section->output_offset + rel->r_offset;
12785 outrel.r_addend = 0;
12786 if (bfd_link_pic(info))
12787 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12788 else
12789 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12790
12791 bfd_put_32 (input_bfd, sgot->output_section->vma
12792 + sgot->output_offset + offset, hit_data);
12793
12794 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12795 arm_elf_fill_funcdesc(output_bfd, info,
12796 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12797 dynindx, offset, addr, dynreloc_value, seg);
12798 }
12799 else
12800 {
12801 if (h->dynindx == -1)
12802 {
12803 int dynindx;
12804 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12805 bfd_vma addr;
12806 bfd_vma seg = -1;
12807 Elf_Internal_Rela outrel;
12808
12809 /* For static binaries sym_sec can be null. */
12810 if (sym_sec)
12811 {
12812 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12813 addr = dynreloc_value - sym_sec->output_section->vma;
12814 }
12815 else
12816 {
12817 dynindx = 0;
12818 addr = 0;
12819 }
12820
12821 if (bfd_link_pic(info) && dynindx == 0)
12822 abort();
12823
12824 /* Replace static FUNCDESC relocation with a
12825 R_ARM_RELATIVE dynamic relocation. */
12826 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12827 outrel.r_offset = input_section->output_section->vma
12828 + input_section->output_offset + rel->r_offset;
12829 outrel.r_addend = 0;
12830 if (bfd_link_pic(info))
12831 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12832 else
12833 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12834
12835 bfd_put_32 (input_bfd, sgot->output_section->vma
12836 + sgot->output_offset + offset, hit_data);
12837
12838 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12839 arm_elf_fill_funcdesc(output_bfd, info,
12840 &eh->fdpic_cnts.funcdesc_offset,
12841 dynindx, offset, addr, dynreloc_value, seg);
12842 }
12843 else
12844 {
12845 Elf_Internal_Rela outrel;
12846
12847 /* Add a dynamic relocation. */
12848 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12849 outrel.r_offset = input_section->output_section->vma
12850 + input_section->output_offset + rel->r_offset;
12851 outrel.r_addend = 0;
12852 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12853 }
12854 }
12855 }
12856 *unresolved_reloc_p = FALSE;
12857 return bfd_reloc_ok;
12858
252b5132
RH		 12859 default:
12860 return bfd_reloc_notsupported;
12861 }
12862}
12863
98c1d4aa
NC		 12864/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12865static void
07d6d2b8
AM		 12866arm_add_to_rel (bfd * abfd,
12867 bfd_byte * address,
57e8b36a 12868 reloc_howto_type * howto,
07d6d2b8 12869 bfd_signed_vma increment)
98c1d4aa 12870{
98c1d4aa
NC		 12871 bfd_signed_vma addend;
12872
bd97cb95
DJ		 12873 if (howto->type == R_ARM_THM_CALL
12874 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12875 {
9a5aca8c
AM		 12876 int upper_insn, lower_insn;
12877 int upper, lower;
98c1d4aa 12878
9a5aca8c
AM		 12879 upper_insn = bfd_get_16 (abfd, address);
12880 lower_insn = bfd_get_16 (abfd, address + 2);
12881 upper = upper_insn & 0x7ff;
12882 lower = lower_insn & 0x7ff;
12883
12884 addend = (upper << 12) | (lower << 1);
ddda4409 12885 addend += increment;
9a5aca8c 12886 addend >>= 1;
98c1d4aa 12887
9a5aca8c
AM		 12888 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12889 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12890
dc810e39
AM		 12891 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12892 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12893 }
12894 else
12895 {
07d6d2b8 12896 bfd_vma contents;
9a5aca8c
AM		 12897
12898 contents = bfd_get_32 (abfd, address);
12899
12900 /* Get the (signed) value from the instruction. */
12901 addend = contents & howto->src_mask;
12902 if (addend & ((howto->src_mask + 1) >> 1))
12903 {
12904 bfd_signed_vma mask;
12905
12906 mask = -1;
12907 mask &= ~ howto->src_mask;
12908 addend |= mask;
12909 }
12910
12911 /* Add in the increment, (which is a byte value). */
12912 switch (howto->type)
12913 {
12914 default:
12915 addend += increment;
12916 break;
12917
12918 case R_ARM_PC24:
c6596c5e 12919 case R_ARM_PLT32:
5b5bb741
PB		 12920 case R_ARM_CALL:
12921 case R_ARM_JUMP24:
9a5aca8c 12922 addend <<= howto->size;
dc810e39 12923 addend += increment;
9a5aca8c
AM		 12924
12925 /* Should we check for overflow here ? */
12926
12927 /* Drop any undesired bits. */
12928 addend >>= howto->rightshift;
12929 break;
12930 }
12931
12932 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12933
12934 bfd_put_32 (abfd, contents, address);
ddda4409 12935 }
98c1d4aa 12936}
252b5132 12937
ba93b8ac
DJ		 12938#define IS_ARM_TLS_RELOC(R_TYPE) \
12939 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 12940 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 12941 || (R_TYPE) == R_ARM_TLS_LDO32 \
12942 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 12943 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 12944 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12945 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12946 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12947 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 12948 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 12949 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 12950 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12951
12952/* Specific set of relocations for the gnu tls dialect. */
12953#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12954 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12955 || (R_TYPE) == R_ARM_TLS_CALL \
12956 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12957 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12958 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12959
252b5132 12960/* Relocate an ARM ELF section. */
906e58ca 12961
b34976b6 12962static bfd_boolean
07d6d2b8 12963elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 12964 struct bfd_link_info * info,
07d6d2b8
AM		 12965 bfd * input_bfd,
12966 asection * input_section,
12967 bfd_byte * contents,
12968 Elf_Internal_Rela * relocs,
12969 Elf_Internal_Sym * local_syms,
12970 asection ** local_sections)
252b5132 12971{
b34976b6
AM		 12972 Elf_Internal_Shdr *symtab_hdr;
12973 struct elf_link_hash_entry **sym_hashes;
12974 Elf_Internal_Rela *rel;
12975 Elf_Internal_Rela *relend;
12976 const char *name;
b32d3aa2 12977 struct elf32_arm_link_hash_table * globals;
252b5132 12978
4e7fd91e 12979 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12980 if (globals == NULL)
12981 return FALSE;
b491616a 12982
0ffa91dd 12983 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12984 sym_hashes = elf_sym_hashes (input_bfd);
12985
12986 rel = relocs;
12987 relend = relocs + input_section->reloc_count;
12988 for (; rel < relend; rel++)
12989 {
07d6d2b8
AM		 12990 int r_type;
12991 reloc_howto_type * howto;
12992 unsigned long r_symndx;
12993 Elf_Internal_Sym * sym;
12994 asection * sec;
252b5132 12995 struct elf_link_hash_entry * h;
07d6d2b8
AM		 12996 bfd_vma relocation;
12997 bfd_reloc_status_type r;
12998 arelent bfd_reloc;
12999 char sym_type;
13000 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13001 char *error_message = NULL;
f21f3fe0 13002
252b5132 13003 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13004 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13005 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13006
ba96a88f 13007 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13008 || r_type == R_ARM_GNU_VTINHERIT)
13009 continue;
252b5132 13010
47aeb64c
NC		 13011 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13012
13013 if (howto == NULL)
13014 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13015
252b5132
RH		 13016 h = NULL;
13017 sym = NULL;
13018 sec = NULL;
9b485d32 13019
252b5132
RH		 13020 if (r_symndx < symtab_hdr->sh_info)
13021 {
13022 sym = local_syms + r_symndx;
ba93b8ac 13023 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13024 sec = local_sections[r_symndx];
ffcb4889
NS		 13025
13026 /* An object file might have a reference to a local
13027 undefined symbol. This is a daft object file, but we
13028 should at least do something about it. V4BX & NONE
13029 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13030 allowed to use the undefined symbol, so allow those.
13031 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13032 if (r_type != R_ARM_V4BX
13033 && r_type != R_ARM_NONE
77b4f08f 13034 && r_symndx != STN_UNDEF
ffcb4889
NS		 13035 && bfd_is_und_section (sec)
13036 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13037 (*info->callbacks->undefined_symbol)
13038 (info, bfd_elf_string_from_elf_section
13039 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13040 input_bfd, input_section,
13041 rel->r_offset, TRUE);
b38cadfb 13042
4e7fd91e 13043 if (globals->use_rel)
f8df10f4 13044 {
4e7fd91e
PB		 13045 relocation = (sec->output_section->vma
13046 + sec->output_offset
13047 + sym->st_value);
0e1862bb 13048 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13049 && (sec->flags & SEC_MERGE)
13050 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13051 {
4e7fd91e
PB		 13052 asection *msec;
13053 bfd_vma addend, value;
13054
39623e12 13055 switch (r_type)
4e7fd91e 13056 {
39623e12
PB		 13057 case R_ARM_MOVW_ABS_NC:
13058 case R_ARM_MOVT_ABS:
13059 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13060 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13061 addend = (addend ^ 0x8000) - 0x8000;
13062 break;
f8df10f4 13063
39623e12
PB		 13064 case R_ARM_THM_MOVW_ABS_NC:
13065 case R_ARM_THM_MOVT_ABS:
13066 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13067 << 16;
13068 value |= bfd_get_16 (input_bfd,
13069 contents + rel->r_offset + 2);
13070 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13071 | ((value & 0x04000000) >> 15);
13072 addend = (addend ^ 0x8000) - 0x8000;
13073 break;
f8df10f4 13074
39623e12
PB		 13075 default:
13076 if (howto->rightshift
13077 || (howto->src_mask & (howto->src_mask + 1)))
13078 {
4eca0228 13079 _bfd_error_handler
695344c0 13080 /* xgettext:c-format */
2dcf00ce
AM		 13081 (_("%pB(%pA+%#" PRIx64 "): "
13082 "%s relocation against SEC_MERGE section"),
39623e12 13083 input_bfd, input_section,
2dcf00ce 13084 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13085 return FALSE;
13086 }
13087
13088 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13089
13090 /* Get the (signed) value from the instruction. */
13091 addend = value & howto->src_mask;
13092 if (addend & ((howto->src_mask + 1) >> 1))
13093 {
13094 bfd_signed_vma mask;
13095
13096 mask = -1;
13097 mask &= ~ howto->src_mask;
13098 addend |= mask;
13099 }
13100 break;
4e7fd91e 13101 }
39623e12 13102
4e7fd91e
PB		 13103 msec = sec;
13104 addend =
13105 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13106 - relocation;
13107 addend += msec->output_section->vma + msec->output_offset;
39623e12 13108
cc643b88 13109 /* Cases here must match those in the preceding
39623e12
PB		 13110 switch statement. */
13111 switch (r_type)
13112 {
13113 case R_ARM_MOVW_ABS_NC:
13114 case R_ARM_MOVT_ABS:
13115 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13116 | (addend & 0xfff);
13117 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13118 break;
13119
13120 case R_ARM_THM_MOVW_ABS_NC:
13121 case R_ARM_THM_MOVT_ABS:
13122 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13123 | (addend & 0xff) | ((addend & 0x0800) << 15);
13124 bfd_put_16 (input_bfd, value >> 16,
13125 contents + rel->r_offset);
13126 bfd_put_16 (input_bfd, value,
13127 contents + rel->r_offset + 2);
13128 break;
13129
13130 default:
13131 value = (value & ~ howto->dst_mask)
13132 | (addend & howto->dst_mask);
13133 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13134 break;
13135 }
f8df10f4 13136 }
f8df10f4 13137 }
4e7fd91e
PB		 13138 else
13139 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13140 }
13141 else
13142 {
62d887d4 13143 bfd_boolean warned, ignored;
560e09e9 13144
b2a8e766
AM		 13145 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13146 r_symndx, symtab_hdr, sym_hashes,
13147 h, sec, relocation,
62d887d4 13148 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13149
13150 sym_type = h->type;
252b5132
RH		 13151 }
13152
dbaa2011 13153 if (sec != NULL && discarded_section (sec))
e4067dbb 13154 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13155 rel, 1, relend, howto, 0, contents);
ab96bf03 13156
0e1862bb 13157 if (bfd_link_relocatable (info))
ab96bf03
AM		 13158 {
13159 /* This is a relocatable link. We don't have to change
13160 anything, unless the reloc is against a section symbol,
13161 in which case we have to adjust according to where the
13162 section symbol winds up in the output section. */
13163 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13164 {
13165 if (globals->use_rel)
13166 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13167 howto, (bfd_signed_vma) sec->output_offset);
13168 else
13169 rel->r_addend += sec->output_offset;
13170 }
13171 continue;
13172 }
13173
252b5132
RH		 13174 if (h != NULL)
13175 name = h->root.root.string;
13176 else
13177 {
13178 name = (bfd_elf_string_from_elf_section
13179 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13180 if (name == NULL || *name == '\0')
13181 name = bfd_section_name (input_bfd, sec);
13182 }
f21f3fe0 13183
cf35638d 13184 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13185 && r_type != R_ARM_NONE
13186 && (h == NULL
13187 || h->root.type == bfd_link_hash_defined
13188 || h->root.type == bfd_link_hash_defweak)
13189 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13190 {
4eca0228 13191 _bfd_error_handler
ba93b8ac 13192 ((sym_type == STT_TLS
695344c0 13193 /* xgettext:c-format */
2dcf00ce 13194 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13195 /* xgettext:c-format */
2dcf00ce 13196 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13197 input_bfd,
13198 input_section,
2dcf00ce 13199 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13200 howto->name,
13201 name);
13202 }
13203
0855e32b 13204 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13205 done, i.e., the relaxation produced the final output we want,
13206 and we won't let anybody mess with it. Also, we have to do
13207 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13208 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13209 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13210 || (IS_ARM_TLS_GNU_RELOC (r_type)
13211 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13212 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13213 & GOT_TLS_GDESC)))
13214 {
13215 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13216 contents, rel, h == NULL);
13217 /* This may have been marked unresolved because it came from
13218 a shared library. But we've just dealt with that. */
13219 unresolved_reloc = 0;
13220 }
13221 else
13222 r = bfd_reloc_continue;
b38cadfb 13223
39d911fc
TP		 13224 if (r == bfd_reloc_continue)
13225 {
13226 unsigned char branch_type =
13227 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13228 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13229
13230 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13231 input_section, contents, rel,
13232 relocation, info, sec, name,
13233 sym_type, branch_type, h,
13234 &unresolved_reloc,
13235 &error_message);
13236 }
0945cdfd
DJ		 13237
13238 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13239 because such sections are not SEC_ALLOC and thus ld.so will
13240 not process them. */
13241 if (unresolved_reloc
99059e56
RM		 13242 && !((input_section->flags & SEC_DEBUGGING) != 0
13243 && h->def_dynamic)
1d5316ab
AM		 13244 && _bfd_elf_section_offset (output_bfd, info, input_section,
13245 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13246 {
4eca0228 13247 _bfd_error_handler
695344c0 13248 /* xgettext:c-format */
2dcf00ce
AM		 13249 (_("%pB(%pA+%#" PRIx64 "): "
13250 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13251 input_bfd,
13252 input_section,
2dcf00ce 13253 (uint64_t) rel->r_offset,
843fe662
L		 13254 howto->name,
13255 h->root.root.string);
0945cdfd
DJ		 13256 return FALSE;
13257 }
252b5132
RH		 13258
13259 if (r != bfd_reloc_ok)
13260 {
252b5132
RH		 13261 switch (r)
13262 {
13263 case bfd_reloc_overflow:
cf919dfd
PB		 13264 /* If the overflowing reloc was to an undefined symbol,
13265 we have already printed one error message and there
13266 is no point complaining again. */
1a72702b
AM		 13267 if (!h || h->root.type != bfd_link_hash_undefined)
13268 (*info->callbacks->reloc_overflow)
13269 (info, (h ? &h->root : NULL), name, howto->name,
13270 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13271 break;
13272
13273 case bfd_reloc_undefined:
1a72702b
AM		 13274 (*info->callbacks->undefined_symbol)
13275 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13276 break;
13277
13278 case bfd_reloc_outofrange:
f2a9dd69 13279 error_message = _("out of range");
252b5132
RH		 13280 goto common_error;
13281
13282 case bfd_reloc_notsupported:
f2a9dd69 13283 error_message = _("unsupported relocation");
252b5132
RH		 13284 goto common_error;
13285
13286 case bfd_reloc_dangerous:
f2a9dd69 13287 /* error_message should already be set. */
252b5132
RH		 13288 goto common_error;
13289
13290 default:
f2a9dd69 13291 error_message = _("unknown error");
8029a119 13292 /* Fall through. */
252b5132
RH		 13293
13294 common_error:
f2a9dd69 13295 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13296 (*info->callbacks->reloc_dangerous)
13297 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13298 break;
13299 }
13300 }
13301 }
13302
b34976b6 13303 return TRUE;
252b5132
RH		 13304}
13305
91d6fa6a 13306/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13307 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13308 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13309 maintaining that condition). */
13310
13311static void
13312add_unwind_table_edit (arm_unwind_table_edit **head,
13313 arm_unwind_table_edit **tail,
13314 arm_unwind_edit_type type,
13315 asection *linked_section,
91d6fa6a 13316 unsigned int tindex)
2468f9c9 13317{
21d799b5
NC		 13318 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13319 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13320
2468f9c9
PB		 13321 new_edit->type = type;
13322 new_edit->linked_section = linked_section;
91d6fa6a 13323 new_edit->index = tindex;
b38cadfb 13324
91d6fa6a 13325 if (tindex > 0)
2468f9c9
PB		 13326 {
13327 new_edit->next = NULL;
13328
13329 if (*tail)
13330 (*tail)->next = new_edit;
13331
13332 (*tail) = new_edit;
13333
13334 if (!*head)
13335 (*head) = new_edit;
13336 }
13337 else
13338 {
13339 new_edit->next = *head;
13340
13341 if (!*tail)
13342 *tail = new_edit;
13343
13344 *head = new_edit;
13345 }
13346}
13347
13348static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13349
13350/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13351static void
13352adjust_exidx_size(asection *exidx_sec, int adjust)
13353{
13354 asection *out_sec;
13355
13356 if (!exidx_sec->rawsize)
13357 exidx_sec->rawsize = exidx_sec->size;
13358
13359 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
13360 out_sec = exidx_sec->output_section;
13361 /* Adjust size of output section. */
13362 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
13363}
13364
13365/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13366static void
13367insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13368{
13369 struct _arm_elf_section_data *exidx_arm_data;
13370
13371 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13372 add_unwind_table_edit (
13373 &exidx_arm_data->u.exidx.unwind_edit_list,
13374 &exidx_arm_data->u.exidx.unwind_edit_tail,
13375 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13376
491d01d3
YU		 13377 exidx_arm_data->additional_reloc_count++;
13378
2468f9c9
PB		 13379 adjust_exidx_size(exidx_sec, 8);
13380}
13381
13382/* Scan .ARM.exidx tables, and create a list describing edits which should be
13383 made to those tables, such that:
b38cadfb 13384
2468f9c9
PB		 13385 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13386 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13387 codes which have been inlined into the index).
2468f9c9 13388
85fdf906
AH		 13389 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13390
2468f9c9 13391 The edits are applied when the tables are written
b38cadfb 13392 (in elf32_arm_write_section). */
2468f9c9
PB		 13393
13394bfd_boolean
13395elf32_arm_fix_exidx_coverage (asection **text_section_order,
13396 unsigned int num_text_sections,
85fdf906
AH		 13397 struct bfd_link_info *info,
13398 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13399{
13400 bfd *inp;
13401 unsigned int last_second_word = 0, i;
13402 asection *last_exidx_sec = NULL;
13403 asection *last_text_sec = NULL;
13404 int last_unwind_type = -1;
13405
13406 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13407 text sections. */
c72f2fb2 13408 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13409 {
13410 asection *sec;
b38cadfb 13411
2468f9c9 13412 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13413 {
2468f9c9
PB		 13414 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13415 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13416
dec9d5df 13417 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13418 continue;
b38cadfb 13419
2468f9c9
PB		 13420 if (elf_sec->linked_to)
13421 {
13422 Elf_Internal_Shdr *linked_hdr
99059e56 13423 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13424 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13425 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13426
13427 if (linked_sec_arm_data == NULL)
99059e56 13428 continue;
2468f9c9
PB		 13429
13430 /* Link this .ARM.exidx section back from the text section it
99059e56 13431 describes. */
2468f9c9
PB		 13432 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13433 }
13434 }
13435 }
13436
13437 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13438 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13439 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13440
13441 for (i = 0; i < num_text_sections; i++)
13442 {
13443 asection *sec = text_section_order[i];
13444 asection *exidx_sec;
13445 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13446 struct _arm_elf_section_data *exidx_arm_data;
13447 bfd_byte *contents = NULL;
13448 int deleted_exidx_bytes = 0;
13449 bfd_vma j;
13450 arm_unwind_table_edit *unwind_edit_head = NULL;
13451 arm_unwind_table_edit *unwind_edit_tail = NULL;
13452 Elf_Internal_Shdr *hdr;
13453 bfd *ibfd;
13454
13455 if (arm_data == NULL)
99059e56 13456 continue;
2468f9c9
PB		 13457
13458 exidx_sec = arm_data->u.text.arm_exidx_sec;
13459 if (exidx_sec == NULL)
13460 {
13461 /* Section has no unwind data. */
13462 if (last_unwind_type == 0 || !last_exidx_sec)
13463 continue;
13464
13465 /* Ignore zero sized sections. */
13466 if (sec->size == 0)
13467 continue;
13468
13469 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13470 last_unwind_type = 0;
13471 continue;
13472 }
13473
22a8f80e
PB		 13474 /* Skip /DISCARD/ sections. */
13475 if (bfd_is_abs_section (exidx_sec->output_section))
13476 continue;
13477
2468f9c9
PB		 13478 hdr = &elf_section_data (exidx_sec)->this_hdr;
13479 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13480 continue;
b38cadfb 13481
2468f9c9
PB		 13482 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13483 if (exidx_arm_data == NULL)
99059e56 13484 continue;
b38cadfb 13485
2468f9c9 13486 ibfd = exidx_sec->owner;
b38cadfb 13487
2468f9c9
PB		 13488 if (hdr->contents != NULL)
13489 contents = hdr->contents;
13490 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13491 /* An error? */
13492 continue;
13493
ac06903d
YU		 13494 if (last_unwind_type > 0)
13495 {
13496 unsigned int first_word = bfd_get_32 (ibfd, contents);
13497 /* Add cantunwind if first unwind item does not match section
13498 start. */
13499 if (first_word != sec->vma)
13500 {
13501 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13502 last_unwind_type = 0;
13503 }
13504 }
13505
2468f9c9
PB		 13506 for (j = 0; j < hdr->sh_size; j += 8)
13507 {
13508 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13509 int unwind_type;
13510 int elide = 0;
13511
13512 /* An EXIDX_CANTUNWIND entry. */
13513 if (second_word == 1)
13514 {
13515 if (last_unwind_type == 0)
13516 elide = 1;
13517 unwind_type = 0;
13518 }
13519 /* Inlined unwinding data. Merge if equal to previous. */
13520 else if ((second_word & 0x80000000) != 0)
13521 {
85fdf906
AH		 13522 if (merge_exidx_entries
13523 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13524 elide = 1;
13525 unwind_type = 1;
13526 last_second_word = second_word;
13527 }
13528 /* Normal table entry. In theory we could merge these too,
13529 but duplicate entries are likely to be much less common. */
13530 else
13531 unwind_type = 2;
13532
491d01d3 13533 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13534 {
13535 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13536 DELETE_EXIDX_ENTRY, NULL, j / 8);
13537
13538 deleted_exidx_bytes += 8;
13539 }
13540
13541 last_unwind_type = unwind_type;
13542 }
13543
13544 /* Free contents if we allocated it ourselves. */
13545 if (contents != hdr->contents)
99059e56 13546 free (contents);
2468f9c9
PB		 13547
13548 /* Record edits to be applied later (in elf32_arm_write_section). */
13549 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13550 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13551
2468f9c9
PB		 13552 if (deleted_exidx_bytes > 0)
13553 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13554
13555 last_exidx_sec = exidx_sec;
13556 last_text_sec = sec;
13557 }
13558
13559 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13560 if (!bfd_link_relocatable (info) && last_exidx_sec
13561 && last_unwind_type != 0)
2468f9c9
PB		 13562 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13563
13564 return TRUE;
13565}
13566
3e6b1042
DJ		 13567static bfd_boolean
13568elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13569 bfd *ibfd, const char *name)
13570{
13571 asection *sec, *osec;
13572
3d4d4302 13573 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13574 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13575 return TRUE;
13576
13577 osec = sec->output_section;
13578 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13579 return TRUE;
13580
13581 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13582 sec->output_offset, sec->size))
13583 return FALSE;
13584
13585 return TRUE;
13586}
13587
13588static bfd_boolean
13589elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13590{
13591 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13592 asection *sec, *osec;
3e6b1042 13593
4dfe6ac6
NC		 13594 if (globals == NULL)
13595 return FALSE;
13596
3e6b1042
DJ		 13597 /* Invoke the regular ELF backend linker to do all the work. */
13598 if (!bfd_elf_final_link (abfd, info))
13599 return FALSE;
13600
fe33d2fa
CL		 13601 /* Process stub sections (eg BE8 encoding, ...). */
13602 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13603 unsigned int i;
cdb21a0a
NS		 13604 for (i=0; i<htab->top_id; i++)
13605 {
13606 sec = htab->stub_group[i].stub_sec;
13607 /* Only process it once, in its link_sec slot. */
13608 if (sec && i == htab->stub_group[i].link_sec->id)
13609 {
13610 osec = sec->output_section;
13611 elf32_arm_write_section (abfd, info, sec, sec->contents);
13612 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13613 sec->output_offset, sec->size))
13614 return FALSE;
13615 }
fe33d2fa 13616 }
fe33d2fa 13617
3e6b1042
DJ		 13618 /* Write out any glue sections now that we have created all the
13619 stubs. */
13620 if (globals->bfd_of_glue_owner != NULL)
13621 {
13622 if (! elf32_arm_output_glue_section (info, abfd,
13623 globals->bfd_of_glue_owner,
13624 ARM2THUMB_GLUE_SECTION_NAME))
13625 return FALSE;
13626
13627 if (! elf32_arm_output_glue_section (info, abfd,
13628 globals->bfd_of_glue_owner,
13629 THUMB2ARM_GLUE_SECTION_NAME))
13630 return FALSE;
13631
13632 if (! elf32_arm_output_glue_section (info, abfd,
13633 globals->bfd_of_glue_owner,
13634 VFP11_ERRATUM_VENEER_SECTION_NAME))
13635 return FALSE;
13636
a504d23a
LA		 13637 if (! elf32_arm_output_glue_section (info, abfd,
13638 globals->bfd_of_glue_owner,
13639 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13640 return FALSE;
13641
3e6b1042
DJ		 13642 if (! elf32_arm_output_glue_section (info, abfd,
13643 globals->bfd_of_glue_owner,
13644 ARM_BX_GLUE_SECTION_NAME))
13645 return FALSE;
13646 }
13647
13648 return TRUE;
13649}
13650
5968a7b8
NC		 13651/* Return a best guess for the machine number based on the attributes. */
13652
13653static unsigned int
13654bfd_arm_get_mach_from_attributes (bfd * abfd)
13655{
13656 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13657
13658 switch (arch)
13659 {
c0c468d5 13660 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13661 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13662 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13663 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13664
13665 case TAG_CPU_ARCH_V5TE:
13666 {
13667 char * name;
13668
13669 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13670 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13671
13672 if (name)
13673 {
13674 if (strcmp (name, "IWMMXT2") == 0)
13675 return bfd_mach_arm_iWMMXt2;
13676
13677 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13678 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13679
13680 if (strcmp (name, "XSCALE") == 0)
13681 {
13682 int wmmx;
13683
13684 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13685 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13686 switch (wmmx)
13687 {
13688 case 1: return bfd_mach_arm_iWMMXt;
13689 case 2: return bfd_mach_arm_iWMMXt2;
13690 default: return bfd_mach_arm_XScale;
13691 }
13692 }
5968a7b8
NC		 13693 }
13694
13695 return bfd_mach_arm_5TE;
13696 }
13697
c0c468d5
TP		 13698 case TAG_CPU_ARCH_V5TEJ:
13699 return bfd_mach_arm_5TEJ;
13700 case TAG_CPU_ARCH_V6:
13701 return bfd_mach_arm_6;
13702 case TAG_CPU_ARCH_V6KZ:
13703 return bfd_mach_arm_6KZ;
13704 case TAG_CPU_ARCH_V6T2:
13705 return bfd_mach_arm_6T2;
13706 case TAG_CPU_ARCH_V6K:
13707 return bfd_mach_arm_6K;
13708 case TAG_CPU_ARCH_V7:
13709 return bfd_mach_arm_7;
13710 case TAG_CPU_ARCH_V6_M:
13711 return bfd_mach_arm_6M;
13712 case TAG_CPU_ARCH_V6S_M:
13713 return bfd_mach_arm_6SM;
13714 case TAG_CPU_ARCH_V7E_M:
13715 return bfd_mach_arm_7EM;
13716 case TAG_CPU_ARCH_V8:
13717 return bfd_mach_arm_8;
13718 case TAG_CPU_ARCH_V8R:
13719 return bfd_mach_arm_8R;
13720 case TAG_CPU_ARCH_V8M_BASE:
13721 return bfd_mach_arm_8M_BASE;
13722 case TAG_CPU_ARCH_V8M_MAIN:
13723 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13724 case TAG_CPU_ARCH_V8_1M_MAIN:
13725 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13726
5968a7b8 13727 default:
c0c468d5
TP		 13728 /* Force entry to be added for any new known Tag_CPU_arch value. */
13729 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13730
13731 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13732 return bfd_mach_arm_unknown;
13733 }
13734}
13735
c178919b
NC		 13736/* Set the right machine number. */
13737
13738static bfd_boolean
57e8b36a 13739elf32_arm_object_p (bfd *abfd)
c178919b 13740{
5a6c6817 13741 unsigned int mach;
57e8b36a 13742
5a6c6817 13743 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13744
5968a7b8
NC		 13745 if (mach == bfd_mach_arm_unknown)
13746 {
13747 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13748 mach = bfd_mach_arm_ep9312;
13749 else
13750 mach = bfd_arm_get_mach_from_attributes (abfd);
13751 }
c178919b 13752
5968a7b8 13753 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13754 return TRUE;
13755}
13756
fc830a83 13757/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13758
b34976b6 13759static bfd_boolean
57e8b36a 13760elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13761{
13762 if (elf_flags_init (abfd)
13763 && elf_elfheader (abfd)->e_flags != flags)
13764 {
fc830a83
NC		 13765 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13766 {
fd2ec330 13767 if (flags & EF_ARM_INTERWORK)
4eca0228 13768 _bfd_error_handler
90b6238f 13769 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13770 abfd);
fc830a83 13771 else
d003868e 13772 _bfd_error_handler
90b6238f 13773 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13774 abfd);
fc830a83 13775 }
252b5132
RH		 13776 }
13777 else
13778 {
13779 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13780 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13781 }
13782
b34976b6 13783 return TRUE;
252b5132
RH		 13784}
13785
fc830a83 13786/* Copy backend specific data from one object module to another. */
9b485d32 13787
b34976b6 13788static bfd_boolean
57e8b36a 13789elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13790{
13791 flagword in_flags;
13792 flagword out_flags;
13793
0ffa91dd 13794 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13795 return TRUE;
252b5132 13796
fc830a83 13797 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13798 out_flags = elf_elfheader (obfd)->e_flags;
13799
fc830a83
NC		 13800 if (elf_flags_init (obfd)
13801 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13802 && in_flags != out_flags)
252b5132 13803 {
252b5132 13804 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13805 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13806 return FALSE;
252b5132
RH		 13807
13808 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13809 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13810 return FALSE;
252b5132
RH		 13811
13812 /* If the src and dest have different interworking flags
99059e56 13813 then turn off the interworking bit. */
fd2ec330 13814 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13815 {
fd2ec330 13816 if (out_flags & EF_ARM_INTERWORK)
d003868e 13817 _bfd_error_handler
90b6238f 13818 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13819 obfd, ibfd);
252b5132 13820
fd2ec330 13821 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13822 }
1006ba19
PB		 13823
13824 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13825 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13826 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13827 }
13828
13829 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13830 elf_flags_init (obfd) = TRUE;
252b5132 13831
e2349352 13832 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13833}
13834
13835/* Values for Tag_ABI_PCS_R9_use. */
13836enum
13837{
13838 AEABI_R9_V6,
13839 AEABI_R9_SB,
13840 AEABI_R9_TLS,
13841 AEABI_R9_unused
13842};
13843
13844/* Values for Tag_ABI_PCS_RW_data. */
13845enum
13846{
13847 AEABI_PCS_RW_data_absolute,
13848 AEABI_PCS_RW_data_PCrel,
13849 AEABI_PCS_RW_data_SBrel,
13850 AEABI_PCS_RW_data_unused
13851};
13852
13853/* Values for Tag_ABI_enum_size. */
13854enum
13855{
13856 AEABI_enum_unused,
13857 AEABI_enum_short,
13858 AEABI_enum_wide,
13859 AEABI_enum_forced_wide
13860};
13861
104d59d1
JM		 13862/* Determine whether an object attribute tag takes an integer, a
13863 string or both. */
906e58ca 13864
104d59d1
JM		 13865static int
13866elf32_arm_obj_attrs_arg_type (int tag)
13867{
13868 if (tag == Tag_compatibility)
3483fe2e 13869 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13870 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13871 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13872 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13873 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13874 else if (tag < 32)
3483fe2e 13875 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13876 else
3483fe2e 13877 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13878}
13879
5aa6ff7c
AS		 13880/* The ABI defines that Tag_conformance should be emitted first, and that
13881 Tag_nodefaults should be second (if either is defined). This sets those
13882 two positions, and bumps up the position of all the remaining tags to
13883 compensate. */
13884static int
13885elf32_arm_obj_attrs_order (int num)
13886{
3de4a297 13887 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13888 return Tag_conformance;
3de4a297 13889 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13890 return Tag_nodefaults;
13891 if ((num - 2) < Tag_nodefaults)
13892 return num - 2;
13893 if ((num - 1) < Tag_conformance)
13894 return num - 1;
13895 return num;
13896}
13897
e8b36cd1
JM		 13898/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13899static bfd_boolean
13900elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13901{
13902 if ((tag & 127) < 64)
13903 {
13904 _bfd_error_handler
90b6238f 13905 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 13906 abfd, tag);
13907 bfd_set_error (bfd_error_bad_value);
13908 return FALSE;
13909 }
13910 else
13911 {
13912 _bfd_error_handler
90b6238f 13913 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 13914 abfd, tag);
13915 return TRUE;
13916 }
13917}
13918
91e22acd
AS		 13919/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13920 Returns -1 if no architecture could be read. */
13921
13922static int
13923get_secondary_compatible_arch (bfd *abfd)
13924{
13925 obj_attribute *attr =
13926 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13927
13928 /* Note: the tag and its argument below are uleb128 values, though
13929 currently-defined values fit in one byte for each. */
13930 if (attr->s
13931 && attr->s[0] == Tag_CPU_arch
13932 && (attr->s[1] & 128) != 128
13933 && attr->s[2] == 0)
13934 return attr->s[1];
13935
13936 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13937 return -1;
13938}
13939
13940/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13941 The tag is removed if ARCH is -1. */
13942
8e79c3df 13943static void
91e22acd 13944set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13945{
91e22acd
AS		 13946 obj_attribute *attr =
13947 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13948
91e22acd
AS		 13949 if (arch == -1)
13950 {
13951 attr->s = NULL;
13952 return;
8e79c3df 13953 }
91e22acd
AS		 13954
13955 /* Note: the tag and its argument below are uleb128 values, though
13956 currently-defined values fit in one byte for each. */
13957 if (!attr->s)
21d799b5 13958 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13959 attr->s[0] = Tag_CPU_arch;
13960 attr->s[1] = arch;
13961 attr->s[2] = '\0';
8e79c3df
CM		 13962}
13963
91e22acd
AS		 13964/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13965 into account. */
13966
13967static int
13968tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13969 int newtag, int secondary_compat)
8e79c3df 13970{
91e22acd
AS		 13971#define T(X) TAG_CPU_ARCH_##X
13972 int tagl, tagh, result;
13973 const int v6t2[] =
13974 {
13975 T(V6T2), /* PRE_V4. */
13976 T(V6T2), /* V4. */
13977 T(V6T2), /* V4T. */
13978 T(V6T2), /* V5T. */
13979 T(V6T2), /* V5TE. */
13980 T(V6T2), /* V5TEJ. */
13981 T(V6T2), /* V6. */
13982 T(V7), /* V6KZ. */
13983 T(V6T2) /* V6T2. */
13984 };
13985 const int v6k[] =
13986 {
13987 T(V6K), /* PRE_V4. */
13988 T(V6K), /* V4. */
13989 T(V6K), /* V4T. */
13990 T(V6K), /* V5T. */
13991 T(V6K), /* V5TE. */
13992 T(V6K), /* V5TEJ. */
13993 T(V6K), /* V6. */
13994 T(V6KZ), /* V6KZ. */
13995 T(V7), /* V6T2. */
13996 T(V6K) /* V6K. */
13997 };
13998 const int v7[] =
13999 {
14000 T(V7), /* PRE_V4. */
14001 T(V7), /* V4. */
14002 T(V7), /* V4T. */
14003 T(V7), /* V5T. */
14004 T(V7), /* V5TE. */
14005 T(V7), /* V5TEJ. */
14006 T(V7), /* V6. */
14007 T(V7), /* V6KZ. */
14008 T(V7), /* V6T2. */
14009 T(V7), /* V6K. */
14010 T(V7) /* V7. */
14011 };
14012 const int v6_m[] =
14013 {
07d6d2b8
AM		 14014 -1, /* PRE_V4. */
14015 -1, /* V4. */
91e22acd
AS		 14016 T(V6K), /* V4T. */
14017 T(V6K), /* V5T. */
14018 T(V6K), /* V5TE. */
14019 T(V6K), /* V5TEJ. */
14020 T(V6K), /* V6. */
14021 T(V6KZ), /* V6KZ. */
14022 T(V7), /* V6T2. */
14023 T(V6K), /* V6K. */
14024 T(V7), /* V7. */
14025 T(V6_M) /* V6_M. */
14026 };
14027 const int v6s_m[] =
14028 {
07d6d2b8
AM		 14029 -1, /* PRE_V4. */
14030 -1, /* V4. */
91e22acd
AS		 14031 T(V6K), /* V4T. */
14032 T(V6K), /* V5T. */
14033 T(V6K), /* V5TE. */
14034 T(V6K), /* V5TEJ. */
14035 T(V6K), /* V6. */
14036 T(V6KZ), /* V6KZ. */
14037 T(V7), /* V6T2. */
14038 T(V6K), /* V6K. */
14039 T(V7), /* V7. */
14040 T(V6S_M), /* V6_M. */
14041 T(V6S_M) /* V6S_M. */
14042 };
9e3c6df6
PB		 14043 const int v7e_m[] =
14044 {
07d6d2b8
AM		 14045 -1, /* PRE_V4. */
14046 -1, /* V4. */
9e3c6df6
PB		 14047 T(V7E_M), /* V4T. */
14048 T(V7E_M), /* V5T. */
14049 T(V7E_M), /* V5TE. */
14050 T(V7E_M), /* V5TEJ. */
14051 T(V7E_M), /* V6. */
14052 T(V7E_M), /* V6KZ. */
14053 T(V7E_M), /* V6T2. */
14054 T(V7E_M), /* V6K. */
14055 T(V7E_M), /* V7. */
14056 T(V7E_M), /* V6_M. */
14057 T(V7E_M), /* V6S_M. */
14058 T(V7E_M) /* V7E_M. */
14059 };
bca38921
MGD		 14060 const int v8[] =
14061 {
14062 T(V8), /* PRE_V4. */
14063 T(V8), /* V4. */
14064 T(V8), /* V4T. */
14065 T(V8), /* V5T. */
14066 T(V8), /* V5TE. */
14067 T(V8), /* V5TEJ. */
14068 T(V8), /* V6. */
14069 T(V8), /* V6KZ. */
14070 T(V8), /* V6T2. */
14071 T(V8), /* V6K. */
14072 T(V8), /* V7. */
14073 T(V8), /* V6_M. */
14074 T(V8), /* V6S_M. */
14075 T(V8), /* V7E_M. */
14076 T(V8) /* V8. */
14077 };
bff0500d
TP		 14078 const int v8r[] =
14079 {
14080 T(V8R), /* PRE_V4. */
14081 T(V8R), /* V4. */
14082 T(V8R), /* V4T. */
14083 T(V8R), /* V5T. */
14084 T(V8R), /* V5TE. */
14085 T(V8R), /* V5TEJ. */
14086 T(V8R), /* V6. */
14087 T(V8R), /* V6KZ. */
14088 T(V8R), /* V6T2. */
14089 T(V8R), /* V6K. */
14090 T(V8R), /* V7. */
14091 T(V8R), /* V6_M. */
14092 T(V8R), /* V6S_M. */
14093 T(V8R), /* V7E_M. */
14094 T(V8), /* V8. */
14095 T(V8R), /* V8R. */
14096 };
2fd158eb
TP		 14097 const int v8m_baseline[] =
14098 {
14099 -1, /* PRE_V4. */
14100 -1, /* V4. */
14101 -1, /* V4T. */
14102 -1, /* V5T. */
14103 -1, /* V5TE. */
14104 -1, /* V5TEJ. */
14105 -1, /* V6. */
14106 -1, /* V6KZ. */
14107 -1, /* V6T2. */
14108 -1, /* V6K. */
14109 -1, /* V7. */
14110 T(V8M_BASE), /* V6_M. */
14111 T(V8M_BASE), /* V6S_M. */
14112 -1, /* V7E_M. */
14113 -1, /* V8. */
bff0500d 14114 -1, /* V8R. */
2fd158eb
TP		 14115 T(V8M_BASE) /* V8-M BASELINE. */
14116 };
14117 const int v8m_mainline[] =
14118 {
14119 -1, /* PRE_V4. */
14120 -1, /* V4. */
14121 -1, /* V4T. */
14122 -1, /* V5T. */
14123 -1, /* V5TE. */
14124 -1, /* V5TEJ. */
14125 -1, /* V6. */
14126 -1, /* V6KZ. */
14127 -1, /* V6T2. */
14128 -1, /* V6K. */
14129 T(V8M_MAIN), /* V7. */
14130 T(V8M_MAIN), /* V6_M. */
14131 T(V8M_MAIN), /* V6S_M. */
14132 T(V8M_MAIN), /* V7E_M. */
14133 -1, /* V8. */
bff0500d 14134 -1, /* V8R. */
2fd158eb
TP		 14135 T(V8M_MAIN), /* V8-M BASELINE. */
14136 T(V8M_MAIN) /* V8-M MAINLINE. */
14137 };
031254f2
AV		 14138 const int v8_1m_mainline[] =
14139 {
14140 -1, /* PRE_V4. */
14141 -1, /* V4. */
14142 -1, /* V4T. */
14143 -1, /* V5T. */
14144 -1, /* V5TE. */
14145 -1, /* V5TEJ. */
14146 -1, /* V6. */
14147 -1, /* V6KZ. */
14148 -1, /* V6T2. */
14149 -1, /* V6K. */
14150 T(V8_1M_MAIN), /* V7. */
14151 T(V8_1M_MAIN), /* V6_M. */
14152 T(V8_1M_MAIN), /* V6S_M. */
14153 T(V8_1M_MAIN), /* V7E_M. */
14154 -1, /* V8. */
14155 -1, /* V8R. */
14156 T(V8_1M_MAIN), /* V8-M BASELINE. */
14157 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14158 -1, /* Unused (18). */
14159 -1, /* Unused (19). */
14160 -1, /* Unused (20). */
14161 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14162 };
91e22acd
AS		 14163 const int v4t_plus_v6_m[] =
14164 {
14165 -1, /* PRE_V4. */
14166 -1, /* V4. */
14167 T(V4T), /* V4T. */
14168 T(V5T), /* V5T. */
14169 T(V5TE), /* V5TE. */
14170 T(V5TEJ), /* V5TEJ. */
14171 T(V6), /* V6. */
14172 T(V6KZ), /* V6KZ. */
14173 T(V6T2), /* V6T2. */
14174 T(V6K), /* V6K. */
14175 T(V7), /* V7. */
14176 T(V6_M), /* V6_M. */
14177 T(V6S_M), /* V6S_M. */
9e3c6df6 14178 T(V7E_M), /* V7E_M. */
bca38921 14179 T(V8), /* V8. */
bff0500d 14180 -1, /* V8R. */
2fd158eb
TP		 14181 T(V8M_BASE), /* V8-M BASELINE. */
14182 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14183 -1, /* Unused (18). */
14184 -1, /* Unused (19). */
14185 -1, /* Unused (20). */
14186 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14187 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14188 };
14189 const int *comb[] =
14190 {
14191 v6t2,
14192 v6k,
14193 v7,
14194 v6_m,
14195 v6s_m,
9e3c6df6 14196 v7e_m,
bca38921 14197 v8,
bff0500d 14198 v8r,
2fd158eb
TP		 14199 v8m_baseline,
14200 v8m_mainline,
031254f2
AV		 14201 NULL,
14202 NULL,
14203 NULL,
14204 v8_1m_mainline,
91e22acd
AS		 14205 /* Pseudo-architecture. */
14206 v4t_plus_v6_m
14207 };
14208
14209 /* Check we've not got a higher architecture than we know about. */
14210
9e3c6df6 14211 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14212 {
90b6238f 14213 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14214 return -1;
14215 }
14216
14217 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14218
14219 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14220 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14221 oldtag = T(V4T_PLUS_V6_M);
14222
14223 /* And override the new tag if we have a Tag_also_compatible_with on the
14224 input. */
14225
14226 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14227 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14228 newtag = T(V4T_PLUS_V6_M);
14229
14230 tagl = (oldtag < newtag) ? oldtag : newtag;
14231 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14232
14233 /* Architectures before V6KZ add features monotonically. */
14234 if (tagh <= TAG_CPU_ARCH_V6KZ)
14235 return result;
14236
4ed7ed8d 14237 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14238
14239 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14240 as the canonical version. */
14241 if (result == T(V4T_PLUS_V6_M))
14242 {
14243 result = T(V4T);
14244 *secondary_compat_out = T(V6_M);
14245 }
14246 else
14247 *secondary_compat_out = -1;
14248
14249 if (result == -1)
14250 {
90b6238f 14251 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14252 ibfd, oldtag, newtag);
14253 return -1;
14254 }
14255
14256 return result;
14257#undef T
8e79c3df
CM		 14258}
14259
ac56ee8f
MGD		 14260/* Query attributes object to see if integer divide instructions may be
14261 present in an object. */
14262static bfd_boolean
14263elf32_arm_attributes_accept_div (const obj_attribute *attr)
14264{
14265 int arch = attr[Tag_CPU_arch].i;
14266 int profile = attr[Tag_CPU_arch_profile].i;
14267
14268 switch (attr[Tag_DIV_use].i)
14269 {
14270 case 0:
14271 /* Integer divide allowed if instruction contained in archetecture. */
14272 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14273 return TRUE;
14274 else if (arch >= TAG_CPU_ARCH_V7E_M)
14275 return TRUE;
14276 else
14277 return FALSE;
14278
14279 case 1:
14280 /* Integer divide explicitly prohibited. */
14281 return FALSE;
14282
14283 default:
14284 /* Unrecognised case - treat as allowing divide everywhere. */
14285 case 2:
14286 /* Integer divide allowed in ARM state. */
14287 return TRUE;
14288 }
14289}
14290
14291/* Query attributes object to see if integer divide instructions are
14292 forbidden to be in the object. This is not the inverse of
14293 elf32_arm_attributes_accept_div. */
14294static bfd_boolean
14295elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14296{
14297 return attr[Tag_DIV_use].i == 1;
14298}
14299
ee065d83
PB		 14300/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14301 are conflicting attributes. */
906e58ca 14302
ee065d83 14303static bfd_boolean
50e03d47 14304elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14305{
50e03d47 14306 bfd *obfd = info->output_bfd;
104d59d1
JM		 14307 obj_attribute *in_attr;
14308 obj_attribute *out_attr;
ee065d83
PB		 14309 /* Some tags have 0 = don't care, 1 = strong requirement,
14310 2 = weak requirement. */
91e22acd 14311 static const int order_021[3] = {0, 2, 1};
ee065d83 14312 int i;
91e22acd 14313 bfd_boolean result = TRUE;
9274e9de 14314 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14315
3e6b1042
DJ		 14316 /* Skip the linker stubs file. This preserves previous behavior
14317 of accepting unknown attributes in the first input file - but
14318 is that a bug? */
14319 if (ibfd->flags & BFD_LINKER_CREATED)
14320 return TRUE;
14321
9274e9de
TG		 14322 /* Skip any input that hasn't attribute section.
14323 This enables to link object files without attribute section with
14324 any others. */
14325 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14326 return TRUE;
14327
104d59d1 14328 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14329 {
14330 /* This is the first object. Copy the attributes. */
104d59d1 14331 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14332
cd21e546
MGD		 14333 out_attr = elf_known_obj_attributes_proc (obfd);
14334
004ae526
PB		 14335 /* Use the Tag_null value to indicate the attributes have been
14336 initialized. */
cd21e546 14337 out_attr[0].i = 1;
004ae526 14338
cd21e546
MGD		 14339 /* We do not output objects with Tag_MPextension_use_legacy - we move
14340 the attribute's value to Tag_MPextension_use. */
14341 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14342 {
14343 if (out_attr[Tag_MPextension_use].i != 0
14344 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14345 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14346 {
14347 _bfd_error_handler
871b3ab2 14348 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14349 "Tag_MPextension_use attributes"), ibfd);
14350 result = FALSE;
14351 }
14352
14353 out_attr[Tag_MPextension_use] =
14354 out_attr[Tag_MPextension_use_legacy];
14355 out_attr[Tag_MPextension_use_legacy].type = 0;
14356 out_attr[Tag_MPextension_use_legacy].i = 0;
14357 }
14358
14359 return result;
ee065d83
PB		 14360 }
14361
104d59d1
JM		 14362 in_attr = elf_known_obj_attributes_proc (ibfd);
14363 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14364 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14365 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14366 {
5c294fee
TG		 14367 /* Ignore mismatches if the object doesn't use floating point or is
14368 floating point ABI independent. */
14369 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14370 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14371 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14372 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14373 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14374 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14375 {
14376 _bfd_error_handler
871b3ab2 14377 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14378 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14379 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14380 result = FALSE;
ee065d83
PB		 14381 }
14382 }
14383
3de4a297 14384 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14385 {
14386 /* Merge this attribute with existing attributes. */
14387 switch (i)
14388 {
14389 case Tag_CPU_raw_name:
14390 case Tag_CPU_name:
6a631e86 14391 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14392 break;
14393
14394 case Tag_ABI_optimization_goals:
14395 case Tag_ABI_FP_optimization_goals:
14396 /* Use the first value seen. */
14397 break;
14398
14399 case Tag_CPU_arch:
91e22acd
AS		 14400 {
14401 int secondary_compat = -1, secondary_compat_out = -1;
14402 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14403 int arch_attr;
14404 static const char *name_table[] =
14405 {
91e22acd
AS		 14406 /* These aren't real CPU names, but we can't guess
14407 that from the architecture version alone. */
14408 "Pre v4",
14409 "ARM v4",
14410 "ARM v4T",
14411 "ARM v5T",
14412 "ARM v5TE",
14413 "ARM v5TEJ",
14414 "ARM v6",
14415 "ARM v6KZ",
14416 "ARM v6T2",
14417 "ARM v6K",
14418 "ARM v7",
14419 "ARM v6-M",
bca38921 14420 "ARM v6S-M",
2fd158eb
TP		 14421 "ARM v8",
14422 "",
14423 "ARM v8-M.baseline",
14424 "ARM v8-M.mainline",
91e22acd
AS		 14425 };
14426
14427 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14428 secondary_compat = get_secondary_compatible_arch (ibfd);
14429 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14430 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14431 &secondary_compat_out,
14432 in_attr[i].i,
14433 secondary_compat);
14434
14435 /* Return with error if failed to merge. */
14436 if (arch_attr == -1)
14437 return FALSE;
14438
14439 out_attr[i].i = arch_attr;
14440
91e22acd
AS		 14441 set_secondary_compatible_arch (obfd, secondary_compat_out);
14442
14443 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14444 if (out_attr[i].i == saved_out_attr)
14445 ; /* Leave the names alone. */
14446 else if (out_attr[i].i == in_attr[i].i)
14447 {
14448 /* The output architecture has been changed to match the
14449 input architecture. Use the input names. */
14450 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14451 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14452 : NULL;
14453 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14454 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14455 : NULL;
14456 }
14457 else
14458 {
14459 out_attr[Tag_CPU_name].s = NULL;
14460 out_attr[Tag_CPU_raw_name].s = NULL;
14461 }
14462
14463 /* If we still don't have a value for Tag_CPU_name,
14464 make one up now. Tag_CPU_raw_name remains blank. */
14465 if (out_attr[Tag_CPU_name].s == NULL
14466 && out_attr[i].i < ARRAY_SIZE (name_table))
14467 out_attr[Tag_CPU_name].s =
14468 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14469 }
14470 break;
14471
ee065d83
PB		 14472 case Tag_ARM_ISA_use:
14473 case Tag_THUMB_ISA_use:
ee065d83 14474 case Tag_WMMX_arch:
91e22acd
AS		 14475 case Tag_Advanced_SIMD_arch:
14476 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14477 case Tag_ABI_FP_rounding:
ee065d83
PB		 14478 case Tag_ABI_FP_exceptions:
14479 case Tag_ABI_FP_user_exceptions:
14480 case Tag_ABI_FP_number_model:
75375b3e 14481 case Tag_FP_HP_extension:
91e22acd
AS		 14482 case Tag_CPU_unaligned_access:
14483 case Tag_T2EE_use:
91e22acd 14484 case Tag_MPextension_use:
ee065d83
PB		 14485 /* Use the largest value specified. */
14486 if (in_attr[i].i > out_attr[i].i)
14487 out_attr[i].i = in_attr[i].i;
14488 break;
14489
75375b3e 14490 case Tag_ABI_align_preserved:
91e22acd
AS		 14491 case Tag_ABI_PCS_RO_data:
14492 /* Use the smallest value specified. */
14493 if (in_attr[i].i < out_attr[i].i)
14494 out_attr[i].i = in_attr[i].i;
14495 break;
14496
75375b3e 14497 case Tag_ABI_align_needed:
91e22acd 14498 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14499 && (in_attr[Tag_ABI_align_preserved].i == 0
14500 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14501 {
91e22acd
AS		 14502 /* This error message should be enabled once all non-conformant
14503 binaries in the toolchain have had the attributes set
14504 properly.
ee065d83 14505 _bfd_error_handler
871b3ab2 14506 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14507 obfd, ibfd);
14508 result = FALSE; */
ee065d83 14509 }
91e22acd
AS		 14510 /* Fall through. */
14511 case Tag_ABI_FP_denormal:
14512 case Tag_ABI_PCS_GOT_use:
14513 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14514 value if greater than 2 (for future-proofing). */
14515 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14516 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14517 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14518 out_attr[i].i = in_attr[i].i;
14519 break;
91e22acd 14520
75375b3e
MGD		 14521 case Tag_Virtualization_use:
14522 /* The virtualization tag effectively stores two bits of
14523 information: the intended use of TrustZone (in bit 0), and the
14524 intended use of Virtualization (in bit 1). */
14525 if (out_attr[i].i == 0)
14526 out_attr[i].i = in_attr[i].i;
14527 else if (in_attr[i].i != 0
14528 && in_attr[i].i != out_attr[i].i)
14529 {
14530 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14531 out_attr[i].i = 3;
14532 else
14533 {
14534 _bfd_error_handler
871b3ab2
AM		 14535 (_("error: %pB: unable to merge virtualization attributes "
14536 "with %pB"),
75375b3e
MGD		 14537 obfd, ibfd);
14538 result = FALSE;
14539 }
14540 }
14541 break;
91e22acd
AS		 14542
14543 case Tag_CPU_arch_profile:
14544 if (out_attr[i].i != in_attr[i].i)
14545 {
14546 /* 0 will merge with anything.
14547 'A' and 'S' merge to 'A'.
14548 'R' and 'S' merge to 'R'.
99059e56 14549 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14550 if (out_attr[i].i == 0
14551 || (out_attr[i].i == 'S'
14552 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14553 out_attr[i].i = in_attr[i].i;
14554 else if (in_attr[i].i == 0
14555 || (in_attr[i].i == 'S'
14556 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14557 ; /* Do nothing. */
91e22acd
AS		 14558 else
14559 {
14560 _bfd_error_handler
90b6238f 14561 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14562 ibfd,
14563 in_attr[i].i ? in_attr[i].i : '0',
14564 out_attr[i].i ? out_attr[i].i : '0');
14565 result = FALSE;
14566 }
14567 }
14568 break;
15afaa63
TP		 14569
14570 case Tag_DSP_extension:
14571 /* No need to change output value if any of:
14572 - pre (<=) ARMv5T input architecture (do not have DSP)
14573 - M input profile not ARMv7E-M and do not have DSP. */
14574 if (in_attr[Tag_CPU_arch].i <= 3
14575 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14576 && in_attr[Tag_CPU_arch].i != 13
14577 && in_attr[i].i == 0))
14578 ; /* Do nothing. */
14579 /* Output value should be 0 if DSP part of architecture, ie.
14580 - post (>=) ARMv5te architecture output
14581 - A, R or S profile output or ARMv7E-M output architecture. */
14582 else if (out_attr[Tag_CPU_arch].i >= 4
14583 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14584 || out_attr[Tag_CPU_arch_profile].i == 'R'
14585 || out_attr[Tag_CPU_arch_profile].i == 'S'
14586 || out_attr[Tag_CPU_arch].i == 13))
14587 out_attr[i].i = 0;
14588 /* Otherwise, DSP instructions are added and not part of output
14589 architecture. */
14590 else
14591 out_attr[i].i = 1;
14592 break;
14593
75375b3e 14594 case Tag_FP_arch:
62f3b8c8 14595 {
4547cb56
NC		 14596 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14597 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14598 when it's 0. It might mean absence of FP hardware if
99654aaf 14599 Tag_FP_arch is zero. */
4547cb56 14600
a715796b 14601#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14602 static const struct
14603 {
14604 int ver;
14605 int regs;
bca38921 14606 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14607 {
14608 {0, 0},
14609 {1, 16},
14610 {2, 16},
14611 {3, 32},
14612 {3, 16},
14613 {4, 32},
bca38921 14614 {4, 16},
a715796b
TG		 14615 {8, 32},
14616 {8, 16}
62f3b8c8
PB		 14617 };
14618 int ver;
14619 int regs;
14620 int newval;
14621
4547cb56
NC		 14622 /* If the output has no requirement about FP hardware,
14623 follow the requirement of the input. */
14624 if (out_attr[i].i == 0)
14625 {
4ec192e6
RE		 14626 /* This assert is still reasonable, we shouldn't
14627 produce the suspicious build attribute
14628 combination (See below for in_attr). */
4547cb56
NC		 14629 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14630 out_attr[i].i = in_attr[i].i;
14631 out_attr[Tag_ABI_HardFP_use].i
14632 = in_attr[Tag_ABI_HardFP_use].i;
14633 break;
14634 }
14635 /* If the input has no requirement about FP hardware, do
14636 nothing. */
14637 else if (in_attr[i].i == 0)
14638 {
4ec192e6
RE		 14639 /* We used to assert that Tag_ABI_HardFP_use was
14640 zero here, but we should never assert when
14641 consuming an object file that has suspicious
14642 build attributes. The single precision variant
14643 of 'no FP architecture' is still 'no FP
14644 architecture', so we just ignore the tag in this
14645 case. */
4547cb56
NC		 14646 break;
14647 }
14648
14649 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14650 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14651
14652 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14653 do nothing. */
14654 if (in_attr[Tag_ABI_HardFP_use].i == 0
14655 && out_attr[Tag_ABI_HardFP_use].i == 0)
14656 ;
14657 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14658 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14659 else if (in_attr[Tag_ABI_HardFP_use].i
14660 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14661 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14662
14663 /* Now we can handle Tag_FP_arch. */
14664
bca38921
MGD		 14665 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14666 pick the biggest. */
14667 if (in_attr[i].i >= VFP_VERSION_COUNT
14668 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14669 {
14670 out_attr[i] = in_attr[i];
14671 break;
14672 }
14673 /* The output uses the superset of input features
14674 (ISA version) and registers. */
14675 ver = vfp_versions[in_attr[i].i].ver;
14676 if (ver < vfp_versions[out_attr[i].i].ver)
14677 ver = vfp_versions[out_attr[i].i].ver;
14678 regs = vfp_versions[in_attr[i].i].regs;
14679 if (regs < vfp_versions[out_attr[i].i].regs)
14680 regs = vfp_versions[out_attr[i].i].regs;
14681 /* This assumes all possible supersets are also a valid
99059e56 14682 options. */
bca38921 14683 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14684 {
14685 if (regs == vfp_versions[newval].regs
14686 && ver == vfp_versions[newval].ver)
14687 break;
14688 }
14689 out_attr[i].i = newval;
14690 }
b1cc4aeb 14691 break;
ee065d83
PB		 14692 case Tag_PCS_config:
14693 if (out_attr[i].i == 0)
14694 out_attr[i].i = in_attr[i].i;
b6009aca 14695 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14696 {
14697 /* It's sometimes ok to mix different configs, so this is only
99059e56 14698 a warning. */
ee065d83 14699 _bfd_error_handler
90b6238f 14700 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14701 }
14702 break;
14703 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14704 if (in_attr[i].i != out_attr[i].i
14705 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14706 && in_attr[i].i != AEABI_R9_unused)
14707 {
14708 _bfd_error_handler
90b6238f 14709 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14710 result = FALSE;
ee065d83
PB		 14711 }
14712 if (out_attr[i].i == AEABI_R9_unused)
14713 out_attr[i].i = in_attr[i].i;
14714 break;
14715 case Tag_ABI_PCS_RW_data:
14716 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14717 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14718 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14719 {
14720 _bfd_error_handler
871b3ab2 14721 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14722 ibfd);
91e22acd 14723 result = FALSE;
ee065d83
PB		 14724 }
14725 /* Use the smallest value specified. */
14726 if (in_attr[i].i < out_attr[i].i)
14727 out_attr[i].i = in_attr[i].i;
14728 break;
ee065d83 14729 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14730 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14731 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14732 {
14733 _bfd_error_handler
871b3ab2 14734 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14735 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14736 }
a9dc9481 14737 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14738 out_attr[i].i = in_attr[i].i;
14739 break;
ee065d83
PB		 14740 case Tag_ABI_enum_size:
14741 if (in_attr[i].i != AEABI_enum_unused)
14742 {
14743 if (out_attr[i].i == AEABI_enum_unused
14744 || out_attr[i].i == AEABI_enum_forced_wide)
14745 {
14746 /* The existing object is compatible with anything.
14747 Use whatever requirements the new object has. */
14748 out_attr[i].i = in_attr[i].i;
14749 }
14750 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14751 && out_attr[i].i != in_attr[i].i
0ffa91dd 14752 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14753 {
91e22acd 14754 static const char *aeabi_enum_names[] =
bf21ed78 14755 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14756 const char *in_name =
14757 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14758 ? aeabi_enum_names[in_attr[i].i]
14759 : "<unknown>";
14760 const char *out_name =
14761 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14762 ? aeabi_enum_names[out_attr[i].i]
14763 : "<unknown>";
ee065d83 14764 _bfd_error_handler
871b3ab2 14765 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14766 ibfd, in_name, out_name);
ee065d83
PB		 14767 }
14768 }
14769 break;
14770 case Tag_ABI_VFP_args:
14771 /* Aready done. */
14772 break;
14773 case Tag_ABI_WMMX_args:
14774 if (in_attr[i].i != out_attr[i].i)
14775 {
14776 _bfd_error_handler
871b3ab2 14777 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14778 ibfd, obfd);
91e22acd 14779 result = FALSE;
ee065d83
PB		 14780 }
14781 break;
7b86a9fa
AS		 14782 case Tag_compatibility:
14783 /* Merged in target-independent code. */
14784 break;
91e22acd 14785 case Tag_ABI_HardFP_use:
4547cb56 14786 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14787 break;
14788 case Tag_ABI_FP_16bit_format:
14789 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14790 {
14791 if (in_attr[i].i != out_attr[i].i)
14792 {
14793 _bfd_error_handler
871b3ab2 14794 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14795 ibfd, obfd);
14796 result = FALSE;
14797 }
14798 }
14799 if (in_attr[i].i != 0)
14800 out_attr[i].i = in_attr[i].i;
14801 break;
7b86a9fa 14802
cd21e546 14803 case Tag_DIV_use:
ac56ee8f
MGD		 14804 /* A value of zero on input means that the divide instruction may
14805 be used if available in the base architecture as specified via
14806 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14807 the user did not want divide instructions. A value of 2
14808 explicitly means that divide instructions were allowed in ARM
14809 and Thumb state. */
14810 if (in_attr[i].i == out_attr[i].i)
14811 /* Do nothing. */ ;
14812 else if (elf32_arm_attributes_forbid_div (in_attr)
14813 && !elf32_arm_attributes_accept_div (out_attr))
14814 out_attr[i].i = 1;
14815 else if (elf32_arm_attributes_forbid_div (out_attr)
14816 && elf32_arm_attributes_accept_div (in_attr))
14817 out_attr[i].i = in_attr[i].i;
14818 else if (in_attr[i].i == 2)
14819 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14820 break;
14821
14822 case Tag_MPextension_use_legacy:
14823 /* We don't output objects with Tag_MPextension_use_legacy - we
14824 move the value to Tag_MPextension_use. */
14825 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14826 {
14827 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14828 {
14829 _bfd_error_handler
871b3ab2 14830 (_("%pB has both the current and legacy "
b38cadfb 14831 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14832 ibfd);
14833 result = FALSE;
14834 }
14835 }
14836
14837 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14838 out_attr[Tag_MPextension_use] = in_attr[i];
14839
14840 break;
14841
91e22acd 14842 case Tag_nodefaults:
2d0bb761
AS		 14843 /* This tag is set if it exists, but the value is unused (and is
14844 typically zero). We don't actually need to do anything here -
14845 the merge happens automatically when the type flags are merged
14846 below. */
91e22acd
AS		 14847 break;
14848 case Tag_also_compatible_with:
14849 /* Already done in Tag_CPU_arch. */
14850 break;
14851 case Tag_conformance:
14852 /* Keep the attribute if it matches. Throw it away otherwise.
14853 No attribute means no claim to conform. */
14854 if (!in_attr[i].s || !out_attr[i].s
14855 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14856 out_attr[i].s = NULL;
14857 break;
3cfad14c 14858
91e22acd 14859 default:
e8b36cd1
JM		 14860 result
14861 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14862 }
14863
14864 /* If out_attr was copied from in_attr then it won't have a type yet. */
14865 if (in_attr[i].type && !out_attr[i].type)
14866 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14867 }
14868
104d59d1 14869 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14870 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14871 return FALSE;
ee065d83 14872
104d59d1 14873 /* Check for any attributes not known on ARM. */
e8b36cd1 14874 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14875
91e22acd 14876 return result;
252b5132
RH		 14877}
14878
3a4a14e9
PB		 14879
14880/* Return TRUE if the two EABI versions are incompatible. */
14881
14882static bfd_boolean
14883elf32_arm_versions_compatible (unsigned iver, unsigned over)
14884{
14885 /* v4 and v5 are the same spec before and after it was released,
14886 so allow mixing them. */
14887 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14888 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14889 return TRUE;
14890
14891 return (iver == over);
14892}
14893
252b5132
RH		 14894/* Merge backend specific data from an object file to the output
14895 object file when linking. */
9b485d32 14896
b34976b6 14897static bfd_boolean
50e03d47 14898elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14899
9b485d32
NC		 14900/* Display the flags field. */
14901
b34976b6 14902static bfd_boolean
57e8b36a 14903elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14904{
fc830a83
NC		 14905 FILE * file = (FILE *) ptr;
14906 unsigned long flags;
252b5132
RH		 14907
14908 BFD_ASSERT (abfd != NULL && ptr != NULL);
14909
14910 /* Print normal ELF private data. */
14911 _bfd_elf_print_private_bfd_data (abfd, ptr);
14912
fc830a83 14913 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14914 /* Ignore init flag - it may not be set, despite the flags field
14915 containing valid data. */
252b5132 14916
9b485d32 14917 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14918
fc830a83
NC		 14919 switch (EF_ARM_EABI_VERSION (flags))
14920 {
14921 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14922 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14923 official ARM ELF extended ABI. Hence they are only decoded if
14924 the EABI version is not set. */
fd2ec330 14925 if (flags & EF_ARM_INTERWORK)
9b485d32 14926 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14927
fd2ec330 14928 if (flags & EF_ARM_APCS_26)
6c571f00 14929 fprintf (file, " [APCS-26]");
fc830a83 14930 else
6c571f00 14931 fprintf (file, " [APCS-32]");
9a5aca8c 14932
96a846ea
RE		 14933 if (flags & EF_ARM_VFP_FLOAT)
14934 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14935 else if (flags & EF_ARM_MAVERICK_FLOAT)
14936 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14937 else
14938 fprintf (file, _(" [FPA float format]"));
14939
fd2ec330 14940 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14941 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14942
fd2ec330 14943 if (flags & EF_ARM_PIC)
9b485d32 14944 fprintf (file, _(" [position independent]"));
fc830a83 14945
fd2ec330 14946 if (flags & EF_ARM_NEW_ABI)
9b485d32 14947 fprintf (file, _(" [new ABI]"));
9a5aca8c 14948
fd2ec330 14949 if (flags & EF_ARM_OLD_ABI)
9b485d32 14950 fprintf (file, _(" [old ABI]"));
9a5aca8c 14951
fd2ec330 14952 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14953 fprintf (file, _(" [software FP]"));
9a5aca8c 14954
96a846ea
RE		 14955 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14956 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14957 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14958 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14959 break;
9a5aca8c 14960
fc830a83 14961 case EF_ARM_EABI_VER1:
9b485d32 14962 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14963
fc830a83 14964 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14965 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14966 else
9b485d32 14967 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14968
fc830a83
NC		 14969 flags &= ~ EF_ARM_SYMSARESORTED;
14970 break;
9a5aca8c 14971
fd2ec330
PB		 14972 case EF_ARM_EABI_VER2:
14973 fprintf (file, _(" [Version2 EABI]"));
14974
14975 if (flags & EF_ARM_SYMSARESORTED)
14976 fprintf (file, _(" [sorted symbol table]"));
14977 else
14978 fprintf (file, _(" [unsorted symbol table]"));
14979
14980 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14981 fprintf (file, _(" [dynamic symbols use segment index]"));
14982
14983 if (flags & EF_ARM_MAPSYMSFIRST)
14984 fprintf (file, _(" [mapping symbols precede others]"));
14985
99e4ae17 14986 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14987 | EF_ARM_MAPSYMSFIRST);
14988 break;
14989
d507cf36
PB		 14990 case EF_ARM_EABI_VER3:
14991 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14992 break;
14993
14994 case EF_ARM_EABI_VER4:
14995 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14996 goto eabi;
d507cf36 14997
3a4a14e9
PB		 14998 case EF_ARM_EABI_VER5:
14999 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15000
15001 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15002 fprintf (file, _(" [soft-float ABI]"));
15003
15004 if (flags & EF_ARM_ABI_FLOAT_HARD)
15005 fprintf (file, _(" [hard-float ABI]"));
15006
15007 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15008
3a4a14e9 15009 eabi:
d507cf36
PB		 15010 if (flags & EF_ARM_BE8)
15011 fprintf (file, _(" [BE8]"));
15012
15013 if (flags & EF_ARM_LE8)
15014 fprintf (file, _(" [LE8]"));
15015
15016 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15017 break;
15018
fc830a83 15019 default:
9b485d32 15020 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15021 break;
15022 }
252b5132 15023
fc830a83 15024 flags &= ~ EF_ARM_EABIMASK;
252b5132 15025
fc830a83 15026 if (flags & EF_ARM_RELEXEC)
9b485d32 15027 fprintf (file, _(" [relocatable executable]"));
252b5132 15028
18a20338
CL		 15029 if (flags & EF_ARM_PIC)
15030 fprintf (file, _(" [position independent]"));
15031
15032 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15033 fprintf (file, _(" [FDPIC ABI supplement]"));
15034
15035 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15036
15037 if (flags)
9b485d32 15038 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15039
252b5132
RH		 15040 fputc ('\n', file);
15041
b34976b6 15042 return TRUE;
252b5132
RH		 15043}
15044
15045static int
57e8b36a 15046elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15047{
2f0ca46a
NC		 15048 switch (ELF_ST_TYPE (elf_sym->st_info))
15049 {
15050 case STT_ARM_TFUNC:
15051 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15052
2f0ca46a
NC		 15053 case STT_ARM_16BIT:
15054 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15055 This allows us to distinguish between data used by Thumb instructions
15056 and non-data (which is probably code) inside Thumb regions of an
15057 executable. */
1a0eb693 15058 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15059 return ELF_ST_TYPE (elf_sym->st_info);
15060 break;
9a5aca8c 15061
ce855c42
NC		 15062 default:
15063 break;
2f0ca46a
NC		 15064 }
15065
15066 return type;
252b5132 15067}
f21f3fe0 15068
252b5132 15069static asection *
07adf181
AM		 15070elf32_arm_gc_mark_hook (asection *sec,
15071 struct bfd_link_info *info,
15072 Elf_Internal_Rela *rel,
15073 struct elf_link_hash_entry *h,
15074 Elf_Internal_Sym *sym)
252b5132
RH		 15075{
15076 if (h != NULL)
07adf181 15077 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15078 {
15079 case R_ARM_GNU_VTINHERIT:
15080 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15081 return NULL;
15082 }
9ad5cbcf 15083
07adf181 15084 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15085}
15086
780a67af
NC		 15087/* Look through the relocs for a section during the first phase. */
15088
b34976b6 15089static bfd_boolean
57e8b36a
NC		 15090elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15091 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15092{
b34976b6
AM		 15093 Elf_Internal_Shdr *symtab_hdr;
15094 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15095 const Elf_Internal_Rela *rel;
15096 const Elf_Internal_Rela *rel_end;
15097 bfd *dynobj;
5e681ec4 15098 asection *sreloc;
5e681ec4 15099 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15100 bfd_boolean call_reloc_p;
15101 bfd_boolean may_become_dynamic_p;
15102 bfd_boolean may_need_local_target_p;
ce98a316 15103 unsigned long nsyms;
9a5aca8c 15104
0e1862bb 15105 if (bfd_link_relocatable (info))
b34976b6 15106 return TRUE;
9a5aca8c 15107
0ffa91dd
NC		 15108 BFD_ASSERT (is_arm_elf (abfd));
15109
5e681ec4 15110 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15111 if (htab == NULL)
15112 return FALSE;
15113
5e681ec4 15114 sreloc = NULL;
9a5aca8c 15115
67687978
PB		 15116 /* Create dynamic sections for relocatable executables so that we can
15117 copy relocations. */
15118 if (htab->root.is_relocatable_executable
15119 && ! htab->root.dynamic_sections_created)
15120 {
15121 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15122 return FALSE;
15123 }
15124
cbc704f3
RS		 15125 if (htab->root.dynobj == NULL)
15126 htab->root.dynobj = abfd;
34e77a92
RS		 15127 if (!create_ifunc_sections (info))
15128 return FALSE;
cbc704f3
RS		 15129
15130 dynobj = htab->root.dynobj;
15131
0ffa91dd 15132 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15133 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15134 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15135
252b5132
RH		 15136 rel_end = relocs + sec->reloc_count;
15137 for (rel = relocs; rel < rel_end; rel++)
15138 {
34e77a92 15139 Elf_Internal_Sym *isym;
252b5132 15140 struct elf_link_hash_entry *h;
b7693d02 15141 struct elf32_arm_link_hash_entry *eh;
d42c267e 15142 unsigned int r_symndx;
eb043451 15143 int r_type;
9a5aca8c 15144
252b5132 15145 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15146 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15147 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15148
ce98a316
NC		 15149 if (r_symndx >= nsyms
15150 /* PR 9934: It is possible to have relocations that do not
15151 refer to symbols, thus it is also possible to have an
15152 object file containing relocations but no symbol table. */
cf35638d 15153 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15154 {
871b3ab2 15155 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15156 r_symndx);
ba93b8ac
DJ		 15157 return FALSE;
15158 }
15159
34e77a92
RS		 15160 h = NULL;
15161 isym = NULL;
15162 if (nsyms > 0)
973a3492 15163 {
34e77a92
RS		 15164 if (r_symndx < symtab_hdr->sh_info)
15165 {
15166 /* A local symbol. */
15167 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15168 abfd, r_symndx);
15169 if (isym == NULL)
15170 return FALSE;
15171 }
15172 else
15173 {
15174 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15175 while (h->root.type == bfd_link_hash_indirect
15176 || h->root.type == bfd_link_hash_warning)
15177 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15178 }
973a3492 15179 }
9a5aca8c 15180
b7693d02
DJ		 15181 eh = (struct elf32_arm_link_hash_entry *) h;
15182
f6e32f6d
RS		 15183 call_reloc_p = FALSE;
15184 may_become_dynamic_p = FALSE;
15185 may_need_local_target_p = FALSE;
15186
0855e32b
NS		 15187 /* Could be done earlier, if h were already available. */
15188 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15189 switch (r_type)
99059e56 15190 {
e8b09b87
CL		 15191 case R_ARM_GOTOFFFUNCDESC:
15192 {
15193 if (h == NULL)
15194 {
15195 if (!elf32_arm_allocate_local_sym_info (abfd))
15196 return FALSE;
15197 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15198 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15199 }
15200 else
15201 {
15202 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15203 }
15204 }
15205 break;
15206
15207 case R_ARM_GOTFUNCDESC:
15208 {
15209 if (h == NULL)
15210 {
15211 /* Such a relocation is not supposed to be generated
15212 by gcc on a static function. */
15213 /* Anyway if needed it could be handled. */
15214 abort();
15215 }
15216 else
15217 {
15218 eh->fdpic_cnts.gotfuncdesc_cnt++;
15219 }
15220 }
15221 break;
15222
15223 case R_ARM_FUNCDESC:
15224 {
15225 if (h == NULL)
15226 {
15227 if (!elf32_arm_allocate_local_sym_info (abfd))
15228 return FALSE;
15229 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15230 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15231 }
15232 else
15233 {
15234 eh->fdpic_cnts.funcdesc_cnt++;
15235 }
15236 }
15237 break;
15238
5e681ec4 15239 case R_ARM_GOT32:
eb043451 15240 case R_ARM_GOT_PREL:
ba93b8ac 15241 case R_ARM_TLS_GD32:
5c5a4843 15242 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15243 case R_ARM_TLS_IE32:
5c5a4843 15244 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15245 case R_ARM_TLS_GOTDESC:
15246 case R_ARM_TLS_DESCSEQ:
15247 case R_ARM_THM_TLS_DESCSEQ:
15248 case R_ARM_TLS_CALL:
15249 case R_ARM_THM_TLS_CALL:
5e681ec4 15250 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15251 {
15252 int tls_type, old_tls_type;
5e681ec4 15253
ba93b8ac
DJ		 15254 switch (r_type)
15255 {
15256 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15257 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15258
ba93b8ac 15259 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15260 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15261
0855e32b
NS		 15262 case R_ARM_TLS_GOTDESC:
15263 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15264 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15265 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15266
ba93b8ac
DJ		 15267 default: tls_type = GOT_NORMAL; break;
15268 }
252b5132 15269
0e1862bb 15270 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15271 info->flags |= DF_STATIC_TLS;
15272
ba93b8ac
DJ		 15273 if (h != NULL)
15274 {
15275 h->got.refcount++;
15276 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15277 }
15278 else
15279 {
ba93b8ac 15280 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15281 if (!elf32_arm_allocate_local_sym_info (abfd))
15282 return FALSE;
15283 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15284 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15285 }
15286
0855e32b 15287 /* If a variable is accessed with both tls methods, two
99059e56 15288 slots may be created. */
0855e32b
NS		 15289 if (GOT_TLS_GD_ANY_P (old_tls_type)
15290 && GOT_TLS_GD_ANY_P (tls_type))
15291 tls_type |= old_tls_type;
15292
15293 /* We will already have issued an error message if there
15294 is a TLS/non-TLS mismatch, based on the symbol
15295 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15296 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15297 && tls_type != GOT_NORMAL)
15298 tls_type |= old_tls_type;
15299
0855e32b 15300 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15301 method, we're able to relax. Turn off the GDESC flag,
15302 without messing up with any other kind of tls types
6a631e86 15303 that may be involved. */
0855e32b
NS		 15304 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15305 tls_type &= ~GOT_TLS_GDESC;
15306
ba93b8ac
DJ		 15307 if (old_tls_type != tls_type)
15308 {
15309 if (h != NULL)
15310 elf32_arm_hash_entry (h)->tls_type = tls_type;
15311 else
15312 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15313 }
15314 }
8029a119 15315 /* Fall through. */
ba93b8ac
DJ		 15316
15317 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15318 case R_ARM_TLS_LDM32_FDPIC:
15319 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15320 htab->tls_ldm_got.refcount++;
8029a119 15321 /* Fall through. */
252b5132 15322
c19d1205 15323 case R_ARM_GOTOFF32:
5e681ec4 15324 case R_ARM_GOTPC:
cbc704f3
RS		 15325 if (htab->root.sgot == NULL
15326 && !create_got_section (htab->root.dynobj, info))
15327 return FALSE;
252b5132
RH		 15328 break;
15329
252b5132 15330 case R_ARM_PC24:
7359ea65 15331 case R_ARM_PLT32:
5b5bb741
PB		 15332 case R_ARM_CALL:
15333 case R_ARM_JUMP24:
eb043451 15334 case R_ARM_PREL31:
c19d1205 15335 case R_ARM_THM_CALL:
bd97cb95
DJ		 15336 case R_ARM_THM_JUMP24:
15337 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15338 call_reloc_p = TRUE;
15339 may_need_local_target_p = TRUE;
15340 break;
15341
15342 case R_ARM_ABS12:
15343 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15344 ldr __GOTT_INDEX__ offsets. */
15345 if (!htab->vxworks_p)
15346 {
15347 may_need_local_target_p = TRUE;
15348 break;
15349 }
aebf9be7 15350 else goto jump_over;
9eaff861 15351
f6e32f6d 15352 /* Fall through. */
39623e12 15353
96c23d59
JM		 15354 case R_ARM_MOVW_ABS_NC:
15355 case R_ARM_MOVT_ABS:
15356 case R_ARM_THM_MOVW_ABS_NC:
15357 case R_ARM_THM_MOVT_ABS:
0e1862bb 15358 if (bfd_link_pic (info))
96c23d59 15359 {
4eca0228 15360 _bfd_error_handler
871b3ab2 15361 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15362 abfd, elf32_arm_howto_table_1[r_type].name,
15363 (h) ? h->root.root.string : "a local symbol");
15364 bfd_set_error (bfd_error_bad_value);
15365 return FALSE;
15366 }
15367
15368 /* Fall through. */
39623e12
PB		 15369 case R_ARM_ABS32:
15370 case R_ARM_ABS32_NOI:
aebf9be7 15371 jump_over:
0e1862bb 15372 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15373 {
15374 h->pointer_equality_needed = 1;
15375 }
15376 /* Fall through. */
39623e12
PB		 15377 case R_ARM_REL32:
15378 case R_ARM_REL32_NOI:
b6895b4f
PB		 15379 case R_ARM_MOVW_PREL_NC:
15380 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15381 case R_ARM_THM_MOVW_PREL_NC:
15382 case R_ARM_THM_MOVT_PREL:
39623e12 15383
b7693d02 15384 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15385 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15386 || htab->fdpic_p)
34e77a92
RS		 15387 && (sec->flags & SEC_ALLOC) != 0)
15388 {
15389 if (h == NULL
469a3493 15390 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15391 {
15392 /* In shared libraries and relocatable executables,
15393 we treat local relative references as calls;
15394 see the related SYMBOL_CALLS_LOCAL code in
15395 allocate_dynrelocs. */
15396 call_reloc_p = TRUE;
15397 may_need_local_target_p = TRUE;
15398 }
15399 else
15400 /* We are creating a shared library or relocatable
15401 executable, and this is a reloc against a global symbol,
15402 or a non-PC-relative reloc against a local symbol.
15403 We may need to copy the reloc into the output. */
15404 may_become_dynamic_p = TRUE;
15405 }
f6e32f6d
RS		 15406 else
15407 may_need_local_target_p = TRUE;
252b5132
RH		 15408 break;
15409
99059e56
RM		 15410 /* This relocation describes the C++ object vtable hierarchy.
15411 Reconstruct it for later use during GC. */
15412 case R_ARM_GNU_VTINHERIT:
15413 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15414 return FALSE;
15415 break;
15416
15417 /* This relocation describes which C++ vtable entries are actually
15418 used. Record for later use during GC. */
15419 case R_ARM_GNU_VTENTRY:
a0ea3a14 15420 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15421 return FALSE;
15422 break;
15423 }
f6e32f6d
RS		 15424
15425 if (h != NULL)
15426 {
15427 if (call_reloc_p)
15428 /* We may need a .plt entry if the function this reloc
15429 refers to is in a different object, regardless of the
15430 symbol's type. We can't tell for sure yet, because
15431 something later might force the symbol local. */
15432 h->needs_plt = 1;
15433 else if (may_need_local_target_p)
15434 /* If this reloc is in a read-only section, we might
15435 need a copy reloc. We can't check reliably at this
15436 stage whether the section is read-only, as input
15437 sections have not yet been mapped to output sections.
15438 Tentatively set the flag for now, and correct in
15439 adjust_dynamic_symbol. */
15440 h->non_got_ref = 1;
15441 }
15442
34e77a92
RS		 15443 if (may_need_local_target_p
15444 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15445 {
34e77a92
RS		 15446 union gotplt_union *root_plt;
15447 struct arm_plt_info *arm_plt;
15448 struct arm_local_iplt_info *local_iplt;
15449
15450 if (h != NULL)
15451 {
15452 root_plt = &h->plt;
15453 arm_plt = &eh->plt;
15454 }
15455 else
15456 {
15457 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15458 if (local_iplt == NULL)
15459 return FALSE;
15460 root_plt = &local_iplt->root;
15461 arm_plt = &local_iplt->arm;
15462 }
15463
f6e32f6d
RS		 15464 /* If the symbol is a function that doesn't bind locally,
15465 this relocation will need a PLT entry. */
a8c887dd
NC		 15466 if (root_plt->refcount != -1)
15467 root_plt->refcount += 1;
34e77a92
RS		 15468
15469 if (!call_reloc_p)
15470 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15471
15472 /* It's too early to use htab->use_blx here, so we have to
15473 record possible blx references separately from
15474 relocs that definitely need a thumb stub. */
15475
15476 if (r_type == R_ARM_THM_CALL)
34e77a92 15477 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15478
15479 if (r_type == R_ARM_THM_JUMP24
15480 || r_type == R_ARM_THM_JUMP19)
34e77a92 15481 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15482 }
15483
15484 if (may_become_dynamic_p)
15485 {
15486 struct elf_dyn_relocs *p, **head;
15487
15488 /* Create a reloc section in dynobj. */
15489 if (sreloc == NULL)
15490 {
15491 sreloc = _bfd_elf_make_dynamic_reloc_section
15492 (sec, dynobj, 2, abfd, ! htab->use_rel);
15493
15494 if (sreloc == NULL)
15495 return FALSE;
15496
15497 /* BPABI objects never have dynamic relocations mapped. */
15498 if (htab->symbian_p)
15499 {
15500 flagword flags;
15501
15502 flags = bfd_get_section_flags (dynobj, sreloc);
15503 flags &= ~(SEC_LOAD | SEC_ALLOC);
15504 bfd_set_section_flags (dynobj, sreloc, flags);
15505 }
15506 }
15507
15508 /* If this is a global symbol, count the number of
15509 relocations we need for this symbol. */
15510 if (h != NULL)
15511 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15512 else
15513 {
34e77a92
RS		 15514 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15515 if (head == NULL)
f6e32f6d 15516 return FALSE;
f6e32f6d
RS		 15517 }
15518
15519 p = *head;
15520 if (p == NULL || p->sec != sec)
15521 {
15522 bfd_size_type amt = sizeof *p;
15523
15524 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15525 if (p == NULL)
15526 return FALSE;
15527 p->next = *head;
15528 *head = p;
15529 p->sec = sec;
15530 p->count = 0;
15531 p->pc_count = 0;
15532 }
15533
469a3493 15534 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15535 p->pc_count += 1;
15536 p->count += 1;
e8b09b87
CL		 15537 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15538 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15539 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15540 that will become rofixup. */
15541 /* This is due to the fact that we suppose all will become rofixup. */
15542 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15543 _bfd_error_handler
15544 (_("FDPIC does not yet support %s relocation"
15545 " to become dynamic for executable"),
15546 elf32_arm_howto_table_1[r_type].name);
15547 abort();
15548 }
f6e32f6d 15549 }
252b5132 15550 }
f21f3fe0 15551
b34976b6 15552 return TRUE;
252b5132
RH		 15553}
15554
9eaff861
AO		 15555static void
15556elf32_arm_update_relocs (asection *o,
15557 struct bfd_elf_section_reloc_data *reldata)
15558{
15559 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15560 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15561 const struct elf_backend_data *bed;
15562 _arm_elf_section_data *eado;
15563 struct bfd_link_order *p;
15564 bfd_byte *erela_head, *erela;
15565 Elf_Internal_Rela *irela_head, *irela;
15566 Elf_Internal_Shdr *rel_hdr;
15567 bfd *abfd;
15568 unsigned int count;
15569
15570 eado = get_arm_elf_section_data (o);
15571
15572 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15573 return;
15574
15575 abfd = o->owner;
15576 bed = get_elf_backend_data (abfd);
15577 rel_hdr = reldata->hdr;
15578
15579 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15580 {
15581 swap_in = bed->s->swap_reloc_in;
15582 swap_out = bed->s->swap_reloc_out;
15583 }
15584 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15585 {
15586 swap_in = bed->s->swap_reloca_in;
15587 swap_out = bed->s->swap_reloca_out;
15588 }
15589 else
15590 abort ();
15591
15592 erela_head = rel_hdr->contents;
15593 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15594 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15595
15596 erela = erela_head;
15597 irela = irela_head;
15598 count = 0;
15599
15600 for (p = o->map_head.link_order; p; p = p->next)
15601 {
15602 if (p->type == bfd_section_reloc_link_order
15603 || p->type == bfd_symbol_reloc_link_order)
15604 {
15605 (*swap_in) (abfd, erela, irela);
15606 erela += rel_hdr->sh_entsize;
15607 irela++;
15608 count++;
15609 }
15610 else if (p->type == bfd_indirect_link_order)
15611 {
15612 struct bfd_elf_section_reloc_data *input_reldata;
15613 arm_unwind_table_edit *edit_list, *edit_tail;
15614 _arm_elf_section_data *eadi;
15615 bfd_size_type j;
15616 bfd_vma offset;
15617 asection *i;
15618
15619 i = p->u.indirect.section;
15620
15621 eadi = get_arm_elf_section_data (i);
15622 edit_list = eadi->u.exidx.unwind_edit_list;
15623 edit_tail = eadi->u.exidx.unwind_edit_tail;
15624 offset = o->vma + i->output_offset;
15625
15626 if (eadi->elf.rel.hdr &&
15627 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15628 input_reldata = &eadi->elf.rel;
15629 else if (eadi->elf.rela.hdr &&
15630 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15631 input_reldata = &eadi->elf.rela;
15632 else
15633 abort ();
15634
15635 if (edit_list)
15636 {
15637 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15638 {
15639 arm_unwind_table_edit *edit_node, *edit_next;
15640 bfd_vma bias;
c48182bf 15641 bfd_vma reloc_index;
9eaff861
AO		 15642
15643 (*swap_in) (abfd, erela, irela);
c48182bf 15644 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15645
15646 bias = 0;
15647 edit_node = edit_list;
15648 for (edit_next = edit_list;
c48182bf 15649 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15650 edit_next = edit_node->next)
15651 {
15652 bias++;
15653 edit_node = edit_next;
15654 }
15655
15656 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15657 || edit_node->index != reloc_index)
9eaff861
AO		 15658 {
15659 irela->r_offset -= bias * 8;
15660 irela++;
15661 count++;
15662 }
15663
15664 erela += rel_hdr->sh_entsize;
15665 }
15666
15667 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15668 {
15669 /* New relocation entity. */
15670 asection *text_sec = edit_tail->linked_section;
15671 asection *text_out = text_sec->output_section;
15672 bfd_vma exidx_offset = offset + i->size - 8;
15673
15674 irela->r_addend = 0;
15675 irela->r_offset = exidx_offset;
15676 irela->r_info = ELF32_R_INFO
15677 (text_out->target_index, R_ARM_PREL31);
15678 irela++;
15679 count++;
15680 }
15681 }
15682 else
15683 {
15684 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15685 {
15686 (*swap_in) (abfd, erela, irela);
15687 erela += rel_hdr->sh_entsize;
15688 irela++;
15689 }
15690
15691 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15692 }
15693 }
15694 }
15695
15696 reldata->count = count;
15697 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15698
15699 erela = erela_head;
15700 irela = irela_head;
15701 while (count > 0)
15702 {
15703 (*swap_out) (abfd, irela, erela);
15704 erela += rel_hdr->sh_entsize;
15705 irela++;
15706 count--;
15707 }
15708
15709 free (irela_head);
15710
15711 /* Hashes are no longer valid. */
15712 free (reldata->hashes);
15713 reldata->hashes = NULL;
15714}
15715
6a5bb875 15716/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15717 required if the corresponding code section is marked. Similarly, ARMv8-M
15718 secure entry functions can only be referenced by SG veneers which are
15719 created after the GC process. They need to be marked in case they reside in
15720 their own section (as would be the case if code was compiled with
15721 -ffunction-sections). */
6a5bb875
PB		 15722
15723static bfd_boolean
906e58ca
NC		 15724elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15725 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15726{
15727 bfd *sub;
15728 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15729 asection *cmse_sec;
15730 obj_attribute *out_attr;
15731 Elf_Internal_Shdr *symtab_hdr;
15732 unsigned i, sym_count, ext_start;
15733 const struct elf_backend_data *bed;
15734 struct elf_link_hash_entry **sym_hashes;
15735 struct elf32_arm_link_hash_entry *cmse_hash;
15736 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15737
7f6ab9f8
AM		 15738 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15739
4ba2ef8f
TP		 15740 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15741 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15742 && out_attr[Tag_CPU_arch_profile].i == 'M';
15743
6a5bb875
PB		 15744 /* Marking EH data may cause additional code sections to be marked,
15745 requiring multiple passes. */
15746 again = TRUE;
15747 while (again)
15748 {
15749 again = FALSE;
c72f2fb2 15750 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15751 {
15752 asection *o;
15753
0ffa91dd 15754 if (! is_arm_elf (sub))
6a5bb875
PB		 15755 continue;
15756
15757 elf_shdrp = elf_elfsections (sub);
15758 for (o = sub->sections; o != NULL; o = o->next)
15759 {
15760 Elf_Internal_Shdr *hdr;
0ffa91dd 15761
6a5bb875 15762 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15763 if (hdr->sh_type == SHT_ARM_EXIDX
15764 && hdr->sh_link
15765 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15766 && !o->gc_mark
15767 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15768 {
15769 again = TRUE;
15770 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15771 return FALSE;
15772 }
15773 }
4ba2ef8f
TP		 15774
15775 /* Mark section holding ARMv8-M secure entry functions. We mark all
15776 of them so no need for a second browsing. */
15777 if (is_v8m && first_bfd_browse)
15778 {
15779 sym_hashes = elf_sym_hashes (sub);
15780 bed = get_elf_backend_data (sub);
15781 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15782 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15783 ext_start = symtab_hdr->sh_info;
15784
15785 /* Scan symbols. */
15786 for (i = ext_start; i < sym_count; i++)
15787 {
15788 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15789
15790 /* Assume it is a special symbol. If not, cmse_scan will
15791 warn about it and user can do something about it. */
15792 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15793 {
15794 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15795 if (!cmse_sec->gc_mark
15796 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15797 return FALSE;
15798 }
15799 }
15800 }
6a5bb875 15801 }
4ba2ef8f 15802 first_bfd_browse = FALSE;
6a5bb875
PB		 15803 }
15804
15805 return TRUE;
15806}
15807
3c9458e9
NC		 15808/* Treat mapping symbols as special target symbols. */
15809
15810static bfd_boolean
15811elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15812{
b0796911
PB		 15813 return bfd_is_arm_special_symbol_name (sym->name,
15814 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15815}
15816
0367ecfb
NC		 15817/* This is a copy of elf_find_function() from elf.c except that
15818 ARM mapping symbols are ignored when looking for function names
15819 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15820
0367ecfb 15821static bfd_boolean
07d6d2b8 15822arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15823 asymbol ** symbols,
fb167eb2 15824 asection * section,
07d6d2b8 15825 bfd_vma offset,
0367ecfb
NC		 15826 const char ** filename_ptr,
15827 const char ** functionname_ptr)
15828{
15829 const char * filename = NULL;
15830 asymbol * func = NULL;
15831 bfd_vma low_func = 0;
15832 asymbol ** p;
252b5132
RH		 15833
15834 for (p = symbols; *p != NULL; p++)
15835 {
15836 elf_symbol_type *q;
15837
15838 q = (elf_symbol_type *) *p;
15839
252b5132
RH		 15840 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15841 {
15842 default:
15843 break;
15844 case STT_FILE:
15845 filename = bfd_asymbol_name (&q->symbol);
15846 break;
252b5132
RH		 15847 case STT_FUNC:
15848 case STT_ARM_TFUNC:
9d2da7ca 15849 case STT_NOTYPE:
b0796911 15850 /* Skip mapping symbols. */
0367ecfb 15851 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15852 && bfd_is_arm_special_symbol_name (q->symbol.name,
15853 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15854 continue;
15855 /* Fall through. */
6b40fcba 15856 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15857 && q->symbol.value >= low_func
15858 && q->symbol.value <= offset)
15859 {
15860 func = (asymbol *) q;
15861 low_func = q->symbol.value;
15862 }
15863 break;
15864 }
15865 }
15866
15867 if (func == NULL)
b34976b6 15868 return FALSE;
252b5132 15869
0367ecfb
NC		 15870 if (filename_ptr)
15871 *filename_ptr = filename;
15872 if (functionname_ptr)
15873 *functionname_ptr = bfd_asymbol_name (func);
15874
15875 return TRUE;
906e58ca 15876}
0367ecfb
NC		 15877
15878
15879/* Find the nearest line to a particular section and offset, for error
15880 reporting. This code is a duplicate of the code in elf.c, except
15881 that it uses arm_elf_find_function. */
15882
15883static bfd_boolean
07d6d2b8
AM		 15884elf32_arm_find_nearest_line (bfd * abfd,
15885 asymbol ** symbols,
15886 asection * section,
15887 bfd_vma offset,
0367ecfb
NC		 15888 const char ** filename_ptr,
15889 const char ** functionname_ptr,
fb167eb2
AM		 15890 unsigned int * line_ptr,
15891 unsigned int * discriminator_ptr)
0367ecfb
NC		 15892{
15893 bfd_boolean found = FALSE;
15894
fb167eb2 15895 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15896 filename_ptr, functionname_ptr,
fb167eb2
AM		 15897 line_ptr, discriminator_ptr,
15898 dwarf_debug_sections, 0,
0367ecfb
NC		 15899 & elf_tdata (abfd)->dwarf2_find_line_info))
15900 {
15901 if (!*functionname_ptr)
fb167eb2 15902 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15903 *filename_ptr ? NULL : filename_ptr,
15904 functionname_ptr);
f21f3fe0 15905
0367ecfb
NC		 15906 return TRUE;
15907 }
15908
fb167eb2
AM		 15909 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15910 uses DWARF1. */
15911
0367ecfb
NC		 15912 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15913 & found, filename_ptr,
15914 functionname_ptr, line_ptr,
15915 & elf_tdata (abfd)->line_info))
15916 return FALSE;
15917
15918 if (found && (*functionname_ptr || *line_ptr))
15919 return TRUE;
15920
15921 if (symbols == NULL)
15922 return FALSE;
15923
fb167eb2 15924 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15925 filename_ptr, functionname_ptr))
15926 return FALSE;
15927
15928 *line_ptr = 0;
b34976b6 15929 return TRUE;
252b5132
RH		 15930}
15931
4ab527b0 15932static bfd_boolean
07d6d2b8 15933elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 15934 const char ** filename_ptr,
15935 const char ** functionname_ptr,
15936 unsigned int * line_ptr)
15937{
15938 bfd_boolean found;
15939 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15940 functionname_ptr, line_ptr,
15941 & elf_tdata (abfd)->dwarf2_find_line_info);
15942 return found;
15943}
15944
63c1f59d
AM		 15945/* Find dynamic relocs for H that apply to read-only sections. */
15946
15947static asection *
15948readonly_dynrelocs (struct elf_link_hash_entry *h)
15949{
15950 struct elf_dyn_relocs *p;
15951
15952 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
15953 {
15954 asection *s = p->sec->output_section;
15955
15956 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15957 return p->sec;
15958 }
15959 return NULL;
15960}
15961
252b5132
RH		 15962/* Adjust a symbol defined by a dynamic object and referenced by a
15963 regular object. The current definition is in some section of the
15964 dynamic object, but we're not including those sections. We have to
15965 change the definition to something the rest of the link can
15966 understand. */
15967
b34976b6 15968static bfd_boolean
57e8b36a
NC		 15969elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15970 struct elf_link_hash_entry * h)
252b5132
RH		 15971{
15972 bfd * dynobj;
5474d94f 15973 asection *s, *srel;
b7693d02 15974 struct elf32_arm_link_hash_entry * eh;
67687978 15975 struct elf32_arm_link_hash_table *globals;
252b5132 15976
67687978 15977 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15978 if (globals == NULL)
15979 return FALSE;
15980
252b5132
RH		 15981 dynobj = elf_hash_table (info)->dynobj;
15982
15983 /* Make sure we know what is going on here. */
15984 BFD_ASSERT (dynobj != NULL
f5385ebf 15985 && (h->needs_plt
34e77a92 15986 || h->type == STT_GNU_IFUNC
60d67dc8 15987 || h->is_weakalias
f5385ebf
AM		 15988 || (h->def_dynamic
15989 && h->ref_regular
15990 && !h->def_regular)));
252b5132 15991
b7693d02
DJ		 15992 eh = (struct elf32_arm_link_hash_entry *) h;
15993
252b5132
RH		 15994 /* If this is a function, put it in the procedure linkage table. We
15995 will fill in the contents of the procedure linkage table later,
15996 when we know the address of the .got section. */
34e77a92 15997 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15998 {
34e77a92
RS		 15999 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16000 symbol binds locally. */
5e681ec4 16001 if (h->plt.refcount <= 0
34e77a92
RS		 16002 || (h->type != STT_GNU_IFUNC
16003 && (SYMBOL_CALLS_LOCAL (info, h)
16004 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16005 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16006 {
16007 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16008 file, but the symbol was never referred to by a dynamic
16009 object, or if all references were garbage collected. In
16010 such a case, we don't actually need to build a procedure
16011 linkage table, and we can just do a PC24 reloc instead. */
16012 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16013 eh->plt.thumb_refcount = 0;
16014 eh->plt.maybe_thumb_refcount = 0;
16015 eh->plt.noncall_refcount = 0;
f5385ebf 16016 h->needs_plt = 0;
252b5132
RH		 16017 }
16018
b34976b6 16019 return TRUE;
252b5132 16020 }
5e681ec4 16021 else
b7693d02
DJ		 16022 {
16023 /* It's possible that we incorrectly decided a .plt reloc was
16024 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16025 in check_relocs. We can't decide accurately between function
16026 and non-function syms in check-relocs; Objects loaded later in
16027 the link may change h->type. So fix it now. */
16028 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16029 eh->plt.thumb_refcount = 0;
16030 eh->plt.maybe_thumb_refcount = 0;
16031 eh->plt.noncall_refcount = 0;
b7693d02 16032 }
252b5132
RH		 16033
16034 /* If this is a weak symbol, and there is a real definition, the
16035 processor independent code will have arranged for us to see the
16036 real definition first, and we can just use the same value. */
60d67dc8 16037 if (h->is_weakalias)
252b5132 16038 {
60d67dc8
AM		 16039 struct elf_link_hash_entry *def = weakdef (h);
16040 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16041 h->root.u.def.section = def->root.u.def.section;
16042 h->root.u.def.value = def->root.u.def.value;
b34976b6 16043 return TRUE;
252b5132
RH		 16044 }
16045
ba93b8ac
DJ		 16046 /* If there are no non-GOT references, we do not need a copy
16047 relocation. */
16048 if (!h->non_got_ref)
16049 return TRUE;
16050
252b5132
RH		 16051 /* This is a reference to a symbol defined by a dynamic object which
16052 is not a function. */
16053
16054 /* If we are creating a shared library, we must presume that the
16055 only references to the symbol are via the global offset table.
16056 For such cases we need not do anything here; the relocations will
67687978
PB		 16057 be handled correctly by relocate_section. Relocatable executables
16058 can reference data in shared objects directly, so we don't need to
16059 do anything here. */
0e1862bb 16060 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16061 return TRUE;
252b5132
RH		 16062
16063 /* We must allocate the symbol in our .dynbss section, which will
16064 become part of the .bss section of the executable. There will be
16065 an entry for this symbol in the .dynsym section. The dynamic
16066 object will contain position independent code, so all references
16067 from the dynamic object to this symbol will go through the global
16068 offset table. The dynamic linker will use the .dynsym entry to
16069 determine the address it must put in the global offset table, so
16070 both the dynamic object and the regular object will refer to the
16071 same memory location for the variable. */
5522f910
NC		 16072 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16073 linker to copy the initial value out of the dynamic object and into
16074 the runtime process image. We need to remember the offset into the
00a97672 16075 .rel(a).bss section we are going to use. */
5474d94f
AM		 16076 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16077 {
16078 s = globals->root.sdynrelro;
16079 srel = globals->root.sreldynrelro;
16080 }
16081 else
16082 {
16083 s = globals->root.sdynbss;
16084 srel = globals->root.srelbss;
16085 }
5522f910
NC		 16086 if (info->nocopyreloc == 0
16087 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16088 && h->size != 0)
252b5132 16089 {
47beaa6a 16090 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16091 h->needs_copy = 1;
252b5132
RH		 16092 }
16093
6cabe1ea 16094 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16095}
16096
5e681ec4
PB		 16097/* Allocate space in .plt, .got and associated reloc sections for
16098 dynamic relocs. */
16099
16100static bfd_boolean
47beaa6a 16101allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16102{
16103 struct bfd_link_info *info;
16104 struct elf32_arm_link_hash_table *htab;
16105 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16106 struct elf_dyn_relocs *p;
5e681ec4
PB		 16107
16108 if (h->root.type == bfd_link_hash_indirect)
16109 return TRUE;
16110
e6a6bb22
AM		 16111 eh = (struct elf32_arm_link_hash_entry *) h;
16112
5e681ec4
PB		 16113 info = (struct bfd_link_info *) inf;
16114 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16115 if (htab == NULL)
16116 return FALSE;
5e681ec4 16117
34e77a92 16118 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16119 && h->plt.refcount > 0)
16120 {
16121 /* Make sure this symbol is output as a dynamic symbol.
16122 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16123 if (h->dynindx == -1 && !h->forced_local
16124 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16125 {
c152c796 16126 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16127 return FALSE;
16128 }
16129
34e77a92
RS		 16130 /* If the call in the PLT entry binds locally, the associated
16131 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16132 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16133 than the .plt section. */
16134 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16135 {
16136 eh->is_iplt = 1;
16137 if (eh->plt.noncall_refcount == 0
16138 && SYMBOL_REFERENCES_LOCAL (info, h))
16139 /* All non-call references can be resolved directly.
16140 This means that they can (and in some cases, must)
16141 resolve directly to the run-time target, rather than
16142 to the PLT. That in turns means that any .got entry
16143 would be equal to the .igot.plt entry, so there's
16144 no point having both. */
16145 h->got.refcount = 0;
16146 }
16147
0e1862bb 16148 if (bfd_link_pic (info)
34e77a92 16149 || eh->is_iplt
7359ea65 16150 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16151 {
34e77a92 16152 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16153
5e681ec4
PB		 16154 /* If this symbol is not defined in a regular file, and we are
16155 not generating a shared library, then set the symbol to this
16156 location in the .plt. This is required to make function
16157 pointers compare as equal between the normal executable and
16158 the shared library. */
0e1862bb 16159 if (! bfd_link_pic (info)
f5385ebf 16160 && !h->def_regular)
5e681ec4 16161 {
34e77a92 16162 h->root.u.def.section = htab->root.splt;
5e681ec4 16163 h->root.u.def.value = h->plt.offset;
5e681ec4 16164
67d74e43
DJ		 16165 /* Make sure the function is not marked as Thumb, in case
16166 it is the target of an ABS32 relocation, which will
16167 point to the PLT entry. */
39d911fc 16168 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16169 }
022f8312 16170
00a97672
RS		 16171 /* VxWorks executables have a second set of relocations for
16172 each PLT entry. They go in a separate relocation section,
16173 which is processed by the kernel loader. */
0e1862bb 16174 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16175 {
16176 /* There is a relocation for the initial PLT entry:
16177 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16178 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16179 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16180
16181 /* There are two extra relocations for each subsequent
16182 PLT entry: an R_ARM_32 relocation for the GOT entry,
16183 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16184 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16185 }
5e681ec4
PB		 16186 }
16187 else
16188 {
16189 h->plt.offset = (bfd_vma) -1;
f5385ebf 16190 h->needs_plt = 0;
5e681ec4
PB		 16191 }
16192 }
16193 else
16194 {
16195 h->plt.offset = (bfd_vma) -1;
f5385ebf 16196 h->needs_plt = 0;
5e681ec4
PB		 16197 }
16198
0855e32b
NS		 16199 eh = (struct elf32_arm_link_hash_entry *) h;
16200 eh->tlsdesc_got = (bfd_vma) -1;
16201
5e681ec4
PB		 16202 if (h->got.refcount > 0)
16203 {
16204 asection *s;
16205 bfd_boolean dyn;
ba93b8ac
DJ		 16206 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16207 int indx;
5e681ec4
PB		 16208
16209 /* Make sure this symbol is output as a dynamic symbol.
16210 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16211 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16212 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16213 {
c152c796 16214 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16215 return FALSE;
16216 }
16217
e5a52504
MM		 16218 if (!htab->symbian_p)
16219 {
362d30a1 16220 s = htab->root.sgot;
e5a52504 16221 h->got.offset = s->size;
ba93b8ac
DJ		 16222
16223 if (tls_type == GOT_UNKNOWN)
16224 abort ();
16225
16226 if (tls_type == GOT_NORMAL)
16227 /* Non-TLS symbols need one GOT slot. */
16228 s->size += 4;
16229 else
16230 {
99059e56
RM		 16231 if (tls_type & GOT_TLS_GDESC)
16232 {
0855e32b 16233 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16234 eh->tlsdesc_got
0855e32b
NS		 16235 = (htab->root.sgotplt->size
16236 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16237 htab->root.sgotplt->size += 8;
16238 h->got.offset = (bfd_vma) -2;
34e77a92 16239 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16240 reloc in the middle of .got.plt. */
99059e56
RM		 16241 htab->num_tls_desc++;
16242 }
0855e32b 16243
ba93b8ac 16244 if (tls_type & GOT_TLS_GD)
0855e32b 16245 {
5c5a4843
CL		 16246 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16247 consecutive GOT slots. If the symbol is both GD
16248 and GDESC, got.offset may have been
16249 overwritten. */
0855e32b
NS		 16250 h->got.offset = s->size;
16251 s->size += 8;
16252 }
16253
ba93b8ac 16254 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16255 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16256 slot. */
ba93b8ac
DJ		 16257 s->size += 4;
16258 }
16259
e5a52504 16260 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16261
16262 indx = 0;
0e1862bb
L		 16263 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16264 bfd_link_pic (info),
16265 h)
16266 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16267 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16268 indx = h->dynindx;
16269
16270 if (tls_type != GOT_NORMAL
0e1862bb 16271 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 16272 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16273 || h->root.type != bfd_link_hash_undefweak))
16274 {
16275 if (tls_type & GOT_TLS_IE)
47beaa6a 16276 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16277
16278 if (tls_type & GOT_TLS_GD)
47beaa6a 16279 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16280
b38cadfb 16281 if (tls_type & GOT_TLS_GDESC)
0855e32b 16282 {
47beaa6a 16283 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16284 /* GDESC needs a trampoline to jump to. */
16285 htab->tls_trampoline = -1;
16286 }
16287
16288 /* Only GD needs it. GDESC just emits one relocation per
16289 2 entries. */
b38cadfb 16290 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16291 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16292 }
e8b09b87
CL		 16293 else if (((indx != -1) || htab->fdpic_p)
16294 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16295 {
16296 if (htab->root.dynamic_sections_created)
16297 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16298 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16299 }
34e77a92
RS		 16300 else if (h->type == STT_GNU_IFUNC
16301 && eh->plt.noncall_refcount == 0)
16302 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16303 they all resolve dynamically instead. Reserve room for the
16304 GOT entry's R_ARM_IRELATIVE relocation. */
16305 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16306 else if (bfd_link_pic (info)
16307 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16308 || h->root.type != bfd_link_hash_undefweak))
b436d854 16309 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16310 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16311 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16312 /* Reserve room for rofixup for FDPIC executable. */
16313 /* TLS relocs do not need space since they are completely
16314 resolved. */
16315 htab->srofixup->size += 4;
e5a52504 16316 }
5e681ec4
PB		 16317 }
16318 else
16319 h->got.offset = (bfd_vma) -1;
16320
e8b09b87
CL		 16321 /* FDPIC support. */
16322 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16323 {
16324 /* Symbol musn't be exported. */
16325 if (h->dynindx != -1)
16326 abort();
16327
16328 /* We only allocate one function descriptor with its associated relocation. */
16329 if (eh->fdpic_cnts.funcdesc_offset == -1)
16330 {
16331 asection *s = htab->root.sgot;
16332
16333 eh->fdpic_cnts.funcdesc_offset = s->size;
16334 s->size += 8;
16335 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16336 if (bfd_link_pic(info))
16337 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16338 else
16339 htab->srofixup->size += 8;
16340 }
16341 }
16342
16343 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16344 {
16345 asection *s = htab->root.sgot;
16346
16347 if (htab->root.dynamic_sections_created && h->dynindx == -1
16348 && !h->forced_local)
16349 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16350 return FALSE;
16351
16352 if (h->dynindx == -1)
16353 {
16354 /* We only allocate one function descriptor with its associated relocation. q */
16355 if (eh->fdpic_cnts.funcdesc_offset == -1)
16356 {
16357
16358 eh->fdpic_cnts.funcdesc_offset = s->size;
16359 s->size += 8;
16360 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16361 if (bfd_link_pic(info))
16362 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16363 else
16364 htab->srofixup->size += 8;
16365 }
16366 }
16367
16368 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16369 R_ARM_RELATIVE/rofixup relocation on it. */
16370 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16371 s->size += 4;
16372 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16373 htab->srofixup->size += 4;
e8b09b87 16374 else
4b24dd1a 16375 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16376 }
16377
16378 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16379 {
16380 if (htab->root.dynamic_sections_created && h->dynindx == -1
16381 && !h->forced_local)
16382 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16383 return FALSE;
16384
16385 if (h->dynindx == -1)
16386 {
16387 /* We only allocate one function descriptor with its associated relocation. */
16388 if (eh->fdpic_cnts.funcdesc_offset == -1)
16389 {
16390 asection *s = htab->root.sgot;
16391
16392 eh->fdpic_cnts.funcdesc_offset = s->size;
16393 s->size += 8;
16394 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16395 if (bfd_link_pic(info))
16396 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16397 else
16398 htab->srofixup->size += 8;
16399 }
16400 }
16401 if (h->dynindx == -1 && !bfd_link_pic(info))
16402 {
16403 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16404 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16405 }
16406 else
16407 {
16408 /* Will need one dynamic reloc per reference. will be either
16409 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16410 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16411 eh->fdpic_cnts.funcdesc_cnt);
16412 }
16413 }
16414
a4fd1a8e
PB		 16415 /* Allocate stubs for exported Thumb functions on v4t. */
16416 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16417 && h->def_regular
39d911fc 16418 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16419 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16420 {
16421 struct elf_link_hash_entry * th;
16422 struct bfd_link_hash_entry * bh;
16423 struct elf_link_hash_entry * myh;
16424 char name[1024];
16425 asection *s;
16426 bh = NULL;
16427 /* Create a new symbol to regist the real location of the function. */
16428 s = h->root.u.def.section;
906e58ca 16429 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16430 _bfd_generic_link_add_one_symbol (info, s->owner,
16431 name, BSF_GLOBAL, s,
16432 h->root.u.def.value,
16433 NULL, TRUE, FALSE, &bh);
16434
16435 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16436 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16437 myh->forced_local = 1;
39d911fc 16438 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16439 eh->export_glue = myh;
16440 th = record_arm_to_thumb_glue (info, h);
16441 /* Point the symbol at the stub. */
16442 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16443 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16444 h->root.u.def.section = th->root.u.def.section;
16445 h->root.u.def.value = th->root.u.def.value & ~1;
16446 }
16447
0bdcacaf 16448 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16449 return TRUE;
16450
16451 /* In the shared -Bsymbolic case, discard space allocated for
16452 dynamic pc-relative relocs against symbols which turn out to be
16453 defined in regular objects. For the normal shared case, discard
16454 space for pc-relative relocs that have become local due to symbol
16455 visibility changes. */
16456
e8b09b87 16457 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16458 {
469a3493
RM		 16459 /* Relocs that use pc_count are PC-relative forms, which will appear
16460 on something like ".long foo - ." or "movw REG, foo - .". We want
16461 calls to protected symbols to resolve directly to the function
16462 rather than going via the plt. If people want function pointer
16463 comparisons to work as expected then they should avoid writing
16464 assembly like ".long foo - .". */
ba93b8ac
DJ		 16465 if (SYMBOL_CALLS_LOCAL (info, h))
16466 {
0bdcacaf 16467 struct elf_dyn_relocs **pp;
ba93b8ac 16468
0bdcacaf 16469 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16470 {
16471 p->count -= p->pc_count;
16472 p->pc_count = 0;
16473 if (p->count == 0)
16474 *pp = p->next;
16475 else
16476 pp = &p->next;
16477 }
16478 }
16479
4dfe6ac6 16480 if (htab->vxworks_p)
3348747a 16481 {
0bdcacaf 16482 struct elf_dyn_relocs **pp;
3348747a 16483
0bdcacaf 16484 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16485 {
0bdcacaf 16486 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16487 *pp = p->next;
16488 else
16489 pp = &p->next;
16490 }
16491 }
16492
ba93b8ac 16493 /* Also discard relocs on undefined weak syms with non-default
99059e56 16494 visibility. */
0bdcacaf 16495 if (eh->dyn_relocs != NULL
5e681ec4 16496 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16497 {
95b03e4a
L		 16498 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16499 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16500 eh->dyn_relocs = NULL;
22d606e9
AM		 16501
16502 /* Make sure undefined weak symbols are output as a dynamic
16503 symbol in PIEs. */
e8b09b87 16504 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16505 && !h->forced_local)
16506 {
16507 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16508 return FALSE;
16509 }
16510 }
16511
67687978
PB		 16512 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16513 && h->root.type == bfd_link_hash_new)
16514 {
16515 /* Output absolute symbols so that we can create relocations
16516 against them. For normal symbols we output a relocation
16517 against the section that contains them. */
16518 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16519 return FALSE;
16520 }
16521
5e681ec4
PB		 16522 }
16523 else
16524 {
16525 /* For the non-shared case, discard space for relocs against
16526 symbols which turn out to need copy relocs or are not
16527 dynamic. */
16528
f5385ebf
AM		 16529 if (!h->non_got_ref
16530 && ((h->def_dynamic
16531 && !h->def_regular)
5e681ec4
PB		 16532 || (htab->root.dynamic_sections_created
16533 && (h->root.type == bfd_link_hash_undefweak
16534 || h->root.type == bfd_link_hash_undefined))))
16535 {
16536 /* Make sure this symbol is output as a dynamic symbol.
16537 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16538 if (h->dynindx == -1 && !h->forced_local
16539 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16540 {
c152c796 16541 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16542 return FALSE;
16543 }
16544
16545 /* If that succeeded, we know we'll be keeping all the
16546 relocs. */
16547 if (h->dynindx != -1)
16548 goto keep;
16549 }
16550
0bdcacaf 16551 eh->dyn_relocs = NULL;
5e681ec4
PB		 16552
16553 keep: ;
16554 }
16555
16556 /* Finally, allocate space. */
0bdcacaf 16557 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16558 {
0bdcacaf 16559 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16560
34e77a92
RS		 16561 if (h->type == STT_GNU_IFUNC
16562 && eh->plt.noncall_refcount == 0
16563 && SYMBOL_REFERENCES_LOCAL (info, h))
16564 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16565 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16566 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16567 else if (htab->fdpic_p && !bfd_link_pic(info))
16568 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16569 else
16570 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16571 }
16572
16573 return TRUE;
16574}
16575
63c1f59d
AM		 16576/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16577 read-only sections. */
08d1f311
DJ		 16578
16579static bfd_boolean
63c1f59d 16580maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16581{
63c1f59d 16582 asection *sec;
08d1f311 16583
63c1f59d
AM		 16584 if (h->root.type == bfd_link_hash_indirect)
16585 return TRUE;
08d1f311 16586
63c1f59d
AM		 16587 sec = readonly_dynrelocs (h);
16588 if (sec != NULL)
16589 {
16590 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16591
63c1f59d
AM		 16592 info->flags |= DF_TEXTREL;
16593 info->callbacks->minfo
c1c8c1ef 16594 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16595 sec->owner, h->root.root.string, sec);
08d1f311 16596
63c1f59d
AM		 16597 /* Not an error, just cut short the traversal. */
16598 return FALSE;
08d1f311 16599 }
cb10292c 16600
08d1f311
DJ		 16601 return TRUE;
16602}
16603
d504ffc8
DJ		 16604void
16605bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16606 int byteswap_code)
16607{
16608 struct elf32_arm_link_hash_table *globals;
16609
16610 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16611 if (globals == NULL)
16612 return;
16613
d504ffc8
DJ		 16614 globals->byteswap_code = byteswap_code;
16615}
16616
252b5132
RH		 16617/* Set the sizes of the dynamic sections. */
16618
b34976b6 16619static bfd_boolean
57e8b36a
NC		 16620elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16621 struct bfd_link_info * info)
252b5132
RH		 16622{
16623 bfd * dynobj;
16624 asection * s;
b34976b6
AM		 16625 bfd_boolean plt;
16626 bfd_boolean relocs;
5e681ec4
PB		 16627 bfd *ibfd;
16628 struct elf32_arm_link_hash_table *htab;
252b5132 16629
5e681ec4 16630 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16631 if (htab == NULL)
16632 return FALSE;
16633
252b5132
RH		 16634 dynobj = elf_hash_table (info)->dynobj;
16635 BFD_ASSERT (dynobj != NULL);
39b41c9c 16636 check_use_blx (htab);
252b5132
RH		 16637
16638 if (elf_hash_table (info)->dynamic_sections_created)
16639 {
16640 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16641 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16642 {
3d4d4302 16643 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16644 BFD_ASSERT (s != NULL);
eea6121a 16645 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16646 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16647 }
16648 }
5e681ec4
PB		 16649
16650 /* Set up .got offsets for local syms, and space for local dynamic
16651 relocs. */
c72f2fb2 16652 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16653 {
5e681ec4
PB		 16654 bfd_signed_vma *local_got;
16655 bfd_signed_vma *end_local_got;
34e77a92 16656 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16657 char *local_tls_type;
0855e32b 16658 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16659 bfd_size_type locsymcount;
16660 Elf_Internal_Shdr *symtab_hdr;
16661 asection *srel;
4dfe6ac6 16662 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16663 unsigned int symndx;
e8b09b87 16664 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16665
0ffa91dd 16666 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16667 continue;
16668
16669 for (s = ibfd->sections; s != NULL; s = s->next)
16670 {
0bdcacaf 16671 struct elf_dyn_relocs *p;
5e681ec4 16672
0bdcacaf 16673 for (p = (struct elf_dyn_relocs *)
99059e56 16674 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16675 {
0bdcacaf
RS		 16676 if (!bfd_is_abs_section (p->sec)
16677 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16678 {
16679 /* Input section has been discarded, either because
16680 it is a copy of a linkonce section or due to
16681 linker script /DISCARD/, so we'll be discarding
16682 the relocs too. */
16683 }
3348747a 16684 else if (is_vxworks
0bdcacaf 16685 && strcmp (p->sec->output_section->name,
3348747a
NS		 16686 ".tls_vars") == 0)
16687 {
16688 /* Relocations in vxworks .tls_vars sections are
16689 handled specially by the loader. */
16690 }
5e681ec4
PB		 16691 else if (p->count != 0)
16692 {
0bdcacaf 16693 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16694 if (htab->fdpic_p && !bfd_link_pic(info))
16695 htab->srofixup->size += 4 * p->count;
16696 else
16697 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16698 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16699 info->flags |= DF_TEXTREL;
16700 }
16701 }
16702 }
16703
16704 local_got = elf_local_got_refcounts (ibfd);
16705 if (!local_got)
16706 continue;
16707
0ffa91dd 16708 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16709 locsymcount = symtab_hdr->sh_info;
16710 end_local_got = local_got + locsymcount;
34e77a92 16711 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16712 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16713 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16714 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16715 symndx = 0;
362d30a1
RS		 16716 s = htab->root.sgot;
16717 srel = htab->root.srelgot;
0855e32b 16718 for (; local_got < end_local_got;
34e77a92 16719 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16720 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16721 {
0855e32b 16722 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16723 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16724
16725 /* FDPIC support. */
16726 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16727 {
16728 if (local_fdpic_cnts->funcdesc_offset == -1)
16729 {
16730 local_fdpic_cnts->funcdesc_offset = s->size;
16731 s->size += 8;
16732
16733 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16734 if (bfd_link_pic(info))
16735 elf32_arm_allocate_dynrelocs (info, srel, 1);
16736 else
16737 htab->srofixup->size += 8;
16738 }
16739 }
16740
16741 if (local_fdpic_cnts->funcdesc_cnt > 0)
16742 {
16743 if (local_fdpic_cnts->funcdesc_offset == -1)
16744 {
16745 local_fdpic_cnts->funcdesc_offset = s->size;
16746 s->size += 8;
16747
16748 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16749 if (bfd_link_pic(info))
16750 elf32_arm_allocate_dynrelocs (info, srel, 1);
16751 else
16752 htab->srofixup->size += 8;
16753 }
16754
16755 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16756 if (bfd_link_pic(info))
16757 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16758 else
16759 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16760 }
16761
34e77a92
RS		 16762 if (local_iplt != NULL)
16763 {
16764 struct elf_dyn_relocs *p;
16765
16766 if (local_iplt->root.refcount > 0)
16767 {
16768 elf32_arm_allocate_plt_entry (info, TRUE,
16769 &local_iplt->root,
16770 &local_iplt->arm);
16771 if (local_iplt->arm.noncall_refcount == 0)
16772 /* All references to the PLT are calls, so all
16773 non-call references can resolve directly to the
16774 run-time target. This means that the .got entry
16775 would be the same as the .igot.plt entry, so there's
16776 no point creating both. */
16777 *local_got = 0;
16778 }
16779 else
16780 {
16781 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16782 local_iplt->root.offset = (bfd_vma) -1;
16783 }
16784
16785 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16786 {
16787 asection *psrel;
16788
16789 psrel = elf_section_data (p->sec)->sreloc;
16790 if (local_iplt->arm.noncall_refcount == 0)
16791 elf32_arm_allocate_irelocs (info, psrel, p->count);
16792 else
16793 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16794 }
16795 }
5e681ec4
PB		 16796 if (*local_got > 0)
16797 {
34e77a92
RS		 16798 Elf_Internal_Sym *isym;
16799
eea6121a 16800 *local_got = s->size;
ba93b8ac
DJ		 16801 if (*local_tls_type & GOT_TLS_GD)
16802 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16803 s->size += 8;
0855e32b
NS		 16804 if (*local_tls_type & GOT_TLS_GDESC)
16805 {
16806 *local_tlsdesc_gotent = htab->root.sgotplt->size
16807 - elf32_arm_compute_jump_table_size (htab);
16808 htab->root.sgotplt->size += 8;
16809 *local_got = (bfd_vma) -2;
34e77a92 16810 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16811 reloc in the middle of .got.plt. */
99059e56 16812 htab->num_tls_desc++;
0855e32b 16813 }
ba93b8ac
DJ		 16814 if (*local_tls_type & GOT_TLS_IE)
16815 s->size += 4;
ba93b8ac 16816
0855e32b
NS		 16817 if (*local_tls_type & GOT_NORMAL)
16818 {
16819 /* If the symbol is both GD and GDESC, *local_got
16820 may have been overwritten. */
16821 *local_got = s->size;
16822 s->size += 4;
16823 }
16824
34e77a92
RS		 16825 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16826 if (isym == NULL)
16827 return FALSE;
16828
16829 /* If all references to an STT_GNU_IFUNC PLT are calls,
16830 then all non-call references, including this GOT entry,
16831 resolve directly to the run-time target. */
16832 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16833 && (local_iplt == NULL
16834 || local_iplt->arm.noncall_refcount == 0))
16835 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16836 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16837 {
e8b09b87 16838 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16839 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16840 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16841 htab->srofixup->size += 4;
99059e56 16842
e8b09b87
CL		 16843 if ((bfd_link_pic (info) || htab->fdpic_p)
16844 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16845 {
16846 elf32_arm_allocate_dynrelocs (info,
16847 htab->root.srelplt, 1);
16848 htab->tls_trampoline = -1;
16849 }
0855e32b 16850 }
5e681ec4
PB		 16851 }
16852 else
16853 *local_got = (bfd_vma) -1;
16854 }
252b5132
RH		 16855 }
16856
ba93b8ac
DJ		 16857 if (htab->tls_ldm_got.refcount > 0)
16858 {
16859 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 16860 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 16861 htab->tls_ldm_got.offset = htab->root.sgot->size;
16862 htab->root.sgot->size += 8;
0e1862bb 16863 if (bfd_link_pic (info))
47beaa6a 16864 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16865 }
16866 else
16867 htab->tls_ldm_got.offset = -1;
16868
e8b09b87
CL		 16869 /* At the very end of the .rofixup section is a pointer to the GOT,
16870 reserve space for it. */
16871 if (htab->fdpic_p && htab->srofixup != NULL)
16872 htab->srofixup->size += 4;
16873
5e681ec4
PB		 16874 /* Allocate global sym .plt and .got entries, and space for global
16875 sym dynamic relocs. */
47beaa6a 16876 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16877
d504ffc8 16878 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16879 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16880 {
0ffa91dd 16881 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16882 continue;
16883
c7b8f16e
JB		 16884 /* Initialise mapping tables for code/data. */
16885 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16886
c7b8f16e 16887 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16888 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16889 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 16890 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 16891 }
d504ffc8 16892
3e6b1042
DJ		 16893 /* Allocate space for the glue sections now that we've sized them. */
16894 bfd_elf32_arm_allocate_interworking_sections (info);
16895
0855e32b
NS		 16896 /* For every jump slot reserved in the sgotplt, reloc_count is
16897 incremented. However, when we reserve space for TLS descriptors,
16898 it's not incremented, so in order to compute the space reserved
16899 for them, it suffices to multiply the reloc count by the jump
16900 slot size. */
16901 if (htab->root.srelplt)
16902 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16903
16904 if (htab->tls_trampoline)
16905 {
16906 if (htab->root.splt->size == 0)
16907 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16908
0855e32b
NS		 16909 htab->tls_trampoline = htab->root.splt->size;
16910 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16911
0855e32b 16912 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16913 PLT and GOT entries they require. */
0855e32b
NS		 16914 if (!(info->flags & DF_BIND_NOW))
16915 {
16916 htab->dt_tlsdesc_got = htab->root.sgot->size;
16917 htab->root.sgot->size += 4;
16918
16919 htab->dt_tlsdesc_plt = htab->root.splt->size;
16920 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16921 }
16922 }
16923
252b5132
RH		 16924 /* The check_relocs and adjust_dynamic_symbol entry points have
16925 determined the sizes of the various dynamic sections. Allocate
16926 memory for them. */
b34976b6
AM		 16927 plt = FALSE;
16928 relocs = FALSE;
252b5132
RH		 16929 for (s = dynobj->sections; s != NULL; s = s->next)
16930 {
16931 const char * name;
252b5132
RH		 16932
16933 if ((s->flags & SEC_LINKER_CREATED) == 0)
16934 continue;
16935
16936 /* It's OK to base decisions on the section name, because none
16937 of the dynobj section names depend upon the input files. */
16938 name = bfd_get_section_name (dynobj, s);
16939
34e77a92 16940 if (s == htab->root.splt)
252b5132 16941 {
c456f082
AM		 16942 /* Remember whether there is a PLT. */
16943 plt = s->size != 0;
252b5132 16944 }
0112cd26 16945 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16946 {
c456f082 16947 if (s->size != 0)
252b5132 16948 {
252b5132 16949 /* Remember whether there are any reloc sections other
00a97672 16950 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16951 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16952 relocs = TRUE;
252b5132
RH		 16953
16954 /* We use the reloc_count field as a counter if we need
16955 to copy relocs into the output file. */
16956 s->reloc_count = 0;
16957 }
16958 }
34e77a92
RS		 16959 else if (s != htab->root.sgot
16960 && s != htab->root.sgotplt
16961 && s != htab->root.iplt
16962 && s != htab->root.igotplt
5474d94f 16963 && s != htab->root.sdynbss
e8b09b87
CL		 16964 && s != htab->root.sdynrelro
16965 && s != htab->srofixup)
252b5132
RH		 16966 {
16967 /* It's not one of our sections, so don't allocate space. */
16968 continue;
16969 }
16970
c456f082 16971 if (s->size == 0)
252b5132 16972 {
c456f082 16973 /* If we don't need this section, strip it from the
00a97672
RS		 16974 output file. This is mostly to handle .rel(a).bss and
16975 .rel(a).plt. We must create both sections in
c456f082
AM		 16976 create_dynamic_sections, because they must be created
16977 before the linker maps input sections to output
16978 sections. The linker does that before
16979 adjust_dynamic_symbol is called, and it is that
16980 function which decides whether anything needs to go
16981 into these sections. */
8423293d 16982 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16983 continue;
16984 }
16985
c456f082
AM		 16986 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16987 continue;
16988
252b5132 16989 /* Allocate memory for the section contents. */
21d799b5 16990 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16991 if (s->contents == NULL)
b34976b6 16992 return FALSE;
252b5132
RH		 16993 }
16994
16995 if (elf_hash_table (info)->dynamic_sections_created)
16996 {
16997 /* Add some entries to the .dynamic section. We fill in the
16998 values later, in elf32_arm_finish_dynamic_sections, but we
16999 must add the entries now so that we get the correct size for
17000 the .dynamic section. The DT_DEBUG entry is filled in by the
17001 dynamic linker and used by the debugger. */
dc810e39 17002#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17003 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17004
0e1862bb 17005 if (bfd_link_executable (info))
252b5132 17006 {
dc810e39 17007 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17008 return FALSE;
252b5132
RH		 17009 }
17010
17011 if (plt)
17012 {
dc810e39
AM		 17013 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17014 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17015 || !add_dynamic_entry (DT_PLTREL,
17016 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17017 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17018 return FALSE;
0855e32b 17019
5025eb7c
AO		 17020 if (htab->dt_tlsdesc_plt
17021 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17022 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17023 return FALSE;
252b5132
RH		 17024 }
17025
17026 if (relocs)
17027 {
00a97672
RS		 17028 if (htab->use_rel)
17029 {
17030 if (!add_dynamic_entry (DT_REL, 0)
17031 || !add_dynamic_entry (DT_RELSZ, 0)
17032 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17033 return FALSE;
17034 }
17035 else
17036 {
17037 if (!add_dynamic_entry (DT_RELA, 0)
17038 || !add_dynamic_entry (DT_RELASZ, 0)
17039 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17040 return FALSE;
17041 }
252b5132
RH		 17042 }
17043
08d1f311
DJ		 17044 /* If any dynamic relocs apply to a read-only section,
17045 then we need a DT_TEXTREL entry. */
17046 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17047 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17048
99e4ae17 17049 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17050 {
dc810e39 17051 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17052 return FALSE;
252b5132 17053 }
7a2b07ff
NS		 17054 if (htab->vxworks_p
17055 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17056 return FALSE;
252b5132 17057 }
8532796c 17058#undef add_dynamic_entry
252b5132 17059
b34976b6 17060 return TRUE;
252b5132
RH		 17061}
17062
0855e32b
NS		 17063/* Size sections even though they're not dynamic. We use it to setup
17064 _TLS_MODULE_BASE_, if needed. */
17065
17066static bfd_boolean
17067elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17068 struct bfd_link_info *info)
0855e32b
NS		 17069{
17070 asection *tls_sec;
cb10292c
CL		 17071 struct elf32_arm_link_hash_table *htab;
17072
17073 htab = elf32_arm_hash_table (info);
0855e32b 17074
0e1862bb 17075 if (bfd_link_relocatable (info))
0855e32b
NS		 17076 return TRUE;
17077
17078 tls_sec = elf_hash_table (info)->tls_sec;
17079
17080 if (tls_sec)
17081 {
17082 struct elf_link_hash_entry *tlsbase;
17083
17084 tlsbase = elf_link_hash_lookup
17085 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17086
17087 if (tlsbase)
99059e56
RM		 17088 {
17089 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17090 const struct elf_backend_data *bed
99059e56 17091 = get_elf_backend_data (output_bfd);
0855e32b 17092
99059e56 17093 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17094 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17095 tls_sec, 0, NULL, FALSE,
17096 bed->collect, &bh)))
17097 return FALSE;
b38cadfb 17098
99059e56
RM		 17099 tlsbase->type = STT_TLS;
17100 tlsbase = (struct elf_link_hash_entry *)bh;
17101 tlsbase->def_regular = 1;
17102 tlsbase->other = STV_HIDDEN;
17103 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17104 }
17105 }
cb10292c
CL		 17106
17107 if (htab->fdpic_p && !bfd_link_relocatable (info)
17108 && !bfd_elf_stack_segment_size (output_bfd, info,
17109 "__stacksize", DEFAULT_STACK_SIZE))
17110 return FALSE;
17111
0855e32b
NS		 17112 return TRUE;
17113}
17114
252b5132
RH		 17115/* Finish up dynamic symbol handling. We set the contents of various
17116 dynamic sections here. */
17117
b34976b6 17118static bfd_boolean
906e58ca
NC		 17119elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17120 struct bfd_link_info * info,
17121 struct elf_link_hash_entry * h,
17122 Elf_Internal_Sym * sym)
252b5132 17123{
e5a52504 17124 struct elf32_arm_link_hash_table *htab;
b7693d02 17125 struct elf32_arm_link_hash_entry *eh;
252b5132 17126
e5a52504 17127 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17128 if (htab == NULL)
17129 return FALSE;
17130
b7693d02 17131 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17132
17133 if (h->plt.offset != (bfd_vma) -1)
17134 {
34e77a92 17135 if (!eh->is_iplt)
e5a52504 17136 {
34e77a92 17137 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17138 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17139 h->dynindx, 0))
17140 return FALSE;
e5a52504 17141 }
57e8b36a 17142
f5385ebf 17143 if (!h->def_regular)
252b5132
RH		 17144 {
17145 /* Mark the symbol as undefined, rather than as defined in
3a635617 17146 the .plt section. */
252b5132 17147 sym->st_shndx = SHN_UNDEF;
3a635617 17148 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17149 Otherwise, the PLT entry would provide a definition for
17150 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17151 and so the symbol would never be NULL. Leave the value if
17152 there were any relocations where pointer equality matters
17153 (this is a clue for the dynamic linker, to make function
17154 pointer comparisons work between an application and shared
17155 library). */
97323ad1 17156 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17157 sym->st_value = 0;
252b5132 17158 }
34e77a92
RS		 17159 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17160 {
17161 /* At least one non-call relocation references this .iplt entry,
17162 so the .iplt entry is the function's canonical address. */
17163 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17164 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17165 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17166 (output_bfd, htab->root.iplt->output_section));
17167 sym->st_value = (h->plt.offset
17168 + htab->root.iplt->output_section->vma
17169 + htab->root.iplt->output_offset);
17170 }
252b5132
RH		 17171 }
17172
f5385ebf 17173 if (h->needs_copy)
252b5132
RH		 17174 {
17175 asection * s;
947216bf 17176 Elf_Internal_Rela rel;
252b5132
RH		 17177
17178 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17179 BFD_ASSERT (h->dynindx != -1
17180 && (h->root.type == bfd_link_hash_defined
17181 || h->root.type == bfd_link_hash_defweak));
17182
00a97672 17183 rel.r_addend = 0;
252b5132
RH		 17184 rel.r_offset = (h->root.u.def.value
17185 + h->root.u.def.section->output_section->vma
17186 + h->root.u.def.section->output_offset);
17187 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17188 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17189 s = htab->root.sreldynrelro;
17190 else
17191 s = htab->root.srelbss;
47beaa6a 17192 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17193 }
17194
00a97672 17195 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17196 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17197 it is relative to the ".got" section. */
9637f6ef 17198 if (h == htab->root.hdynamic
fac7bd64 17199 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17200 sym->st_shndx = SHN_ABS;
17201
b34976b6 17202 return TRUE;
252b5132
RH		 17203}
17204
0855e32b
NS		 17205static void
17206arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17207 void *contents,
17208 const unsigned long *template, unsigned count)
17209{
17210 unsigned ix;
b38cadfb 17211
0855e32b
NS		 17212 for (ix = 0; ix != count; ix++)
17213 {
17214 unsigned long insn = template[ix];
17215
17216 /* Emit mov pc,rx if bx is not permitted. */
17217 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17218 insn = (insn & 0xf000000f) | 0x01a0f000;
17219 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17220 }
17221}
17222
99059e56
RM		 17223/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17224 other variants, NaCl needs this entry in a static executable's
17225 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17226 zero. For .iplt really only the last bundle is useful, and .iplt
17227 could have a shorter first entry, with each individual PLT entry's
17228 relative branch calculated differently so it targets the last
17229 bundle instead of the instruction before it (labelled .Lplt_tail
17230 above). But it's simpler to keep the size and layout of PLT0
17231 consistent with the dynamic case, at the cost of some dead code at
17232 the start of .iplt and the one dead store to the stack at the start
17233 of .Lplt_tail. */
17234static void
17235arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17236 asection *plt, bfd_vma got_displacement)
17237{
17238 unsigned int i;
17239
17240 put_arm_insn (htab, output_bfd,
17241 elf32_arm_nacl_plt0_entry[0]
17242 | arm_movw_immediate (got_displacement),
17243 plt->contents + 0);
17244 put_arm_insn (htab, output_bfd,
17245 elf32_arm_nacl_plt0_entry[1]
17246 | arm_movt_immediate (got_displacement),
17247 plt->contents + 4);
17248
17249 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17250 put_arm_insn (htab, output_bfd,
17251 elf32_arm_nacl_plt0_entry[i],
17252 plt->contents + (i * 4));
17253}
17254
252b5132
RH		 17255/* Finish up the dynamic sections. */
17256
b34976b6 17257static bfd_boolean
57e8b36a 17258elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17259{
17260 bfd * dynobj;
17261 asection * sgot;
17262 asection * sdyn;
4dfe6ac6
NC		 17263 struct elf32_arm_link_hash_table *htab;
17264
17265 htab = elf32_arm_hash_table (info);
17266 if (htab == NULL)
17267 return FALSE;
252b5132
RH		 17268
17269 dynobj = elf_hash_table (info)->dynobj;
17270
362d30a1 17271 sgot = htab->root.sgotplt;
894891db
NC		 17272 /* A broken linker script might have discarded the dynamic sections.
17273 Catch this here so that we do not seg-fault later on. */
17274 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17275 return FALSE;
3d4d4302 17276 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17277
17278 if (elf_hash_table (info)->dynamic_sections_created)
17279 {
17280 asection *splt;
17281 Elf32_External_Dyn *dyncon, *dynconend;
17282
362d30a1 17283 splt = htab->root.splt;
24a1ba0f 17284 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17285 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17286
17287 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17288 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17289
252b5132
RH		 17290 for (; dyncon < dynconend; dyncon++)
17291 {
17292 Elf_Internal_Dyn dyn;
17293 const char * name;
17294 asection * s;
17295
17296 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17297
17298 switch (dyn.d_tag)
17299 {
229fcec5
MM		 17300 unsigned int type;
17301
252b5132 17302 default:
7a2b07ff
NS		 17303 if (htab->vxworks_p
17304 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17305 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17306 break;
17307
229fcec5
MM		 17308 case DT_HASH:
17309 name = ".hash";
17310 goto get_vma_if_bpabi;
17311 case DT_STRTAB:
17312 name = ".dynstr";
17313 goto get_vma_if_bpabi;
17314 case DT_SYMTAB:
17315 name = ".dynsym";
17316 goto get_vma_if_bpabi;
c0042f5d
MM		 17317 case DT_VERSYM:
17318 name = ".gnu.version";
17319 goto get_vma_if_bpabi;
17320 case DT_VERDEF:
17321 name = ".gnu.version_d";
17322 goto get_vma_if_bpabi;
17323 case DT_VERNEED:
17324 name = ".gnu.version_r";
17325 goto get_vma_if_bpabi;
17326
252b5132 17327 case DT_PLTGOT:
4ade44b7 17328 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17329 goto get_vma;
17330 case DT_JMPREL:
00a97672 17331 name = RELOC_SECTION (htab, ".plt");
252b5132 17332 get_vma:
4ade44b7 17333 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17334 if (s == NULL)
17335 {
4eca0228 17336 _bfd_error_handler
4ade44b7 17337 (_("could not find section %s"), name);
05456594
NC		 17338 bfd_set_error (bfd_error_invalid_operation);
17339 return FALSE;
17340 }
229fcec5 17341 if (!htab->symbian_p)
4ade44b7 17342 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17343 else
17344 /* In the BPABI, tags in the PT_DYNAMIC section point
17345 at the file offset, not the memory address, for the
17346 convenience of the post linker. */
4ade44b7 17347 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17348 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17349 break;
17350
229fcec5
MM		 17351 get_vma_if_bpabi:
17352 if (htab->symbian_p)
17353 goto get_vma;
17354 break;
17355
252b5132 17356 case DT_PLTRELSZ:
362d30a1 17357 s = htab->root.srelplt;
252b5132 17358 BFD_ASSERT (s != NULL);
eea6121a 17359 dyn.d_un.d_val = s->size;
252b5132
RH		 17360 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17361 break;
906e58ca 17362
252b5132 17363 case DT_RELSZ:
00a97672 17364 case DT_RELASZ:
229fcec5
MM		 17365 case DT_REL:
17366 case DT_RELA:
229fcec5
MM		 17367 /* In the BPABI, the DT_REL tag must point at the file
17368 offset, not the VMA, of the first relocation
17369 section. So, we use code similar to that in
17370 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17371 relocation section, since relocation sections are
17372 never allocated under the BPABI. PLT relocs are also
17373 included. */
229fcec5
MM		 17374 if (htab->symbian_p)
17375 {
17376 unsigned int i;
17377 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17378 ? SHT_REL : SHT_RELA);
17379 dyn.d_un.d_val = 0;
17380 for (i = 1; i < elf_numsections (output_bfd); i++)
17381 {
906e58ca 17382 Elf_Internal_Shdr *hdr
229fcec5
MM		 17383 = elf_elfsections (output_bfd)[i];
17384 if (hdr->sh_type == type)
17385 {
906e58ca 17386 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17387 || dyn.d_tag == DT_RELASZ)
17388 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17389 else if ((ufile_ptr) hdr->sh_offset
17390 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17391 dyn.d_un.d_val = hdr->sh_offset;
17392 }
17393 }
17394 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17395 }
252b5132 17396 break;
88f7bcd5 17397
0855e32b 17398 case DT_TLSDESC_PLT:
99059e56 17399 s = htab->root.splt;
0855e32b
NS		 17400 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17401 + htab->dt_tlsdesc_plt);
17402 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17403 break;
17404
17405 case DT_TLSDESC_GOT:
99059e56 17406 s = htab->root.sgot;
0855e32b 17407 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17408 + htab->dt_tlsdesc_got);
0855e32b
NS		 17409 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17410 break;
17411
88f7bcd5
NC		 17412 /* Set the bottom bit of DT_INIT/FINI if the
17413 corresponding function is Thumb. */
17414 case DT_INIT:
17415 name = info->init_function;
17416 goto get_sym;
17417 case DT_FINI:
17418 name = info->fini_function;
17419 get_sym:
17420 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17421 then there is nothing to adjust. */
88f7bcd5
NC		 17422 if (dyn.d_un.d_val != 0)
17423 {
17424 struct elf_link_hash_entry * eh;
17425
17426 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17427 FALSE, FALSE, TRUE);
39d911fc
TP		 17428 if (eh != NULL
17429 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17430 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17431 {
17432 dyn.d_un.d_val |= 1;
b34976b6 17433 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17434 }
17435 }
17436 break;
252b5132
RH		 17437 }
17438 }
17439
24a1ba0f 17440 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17441 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17442 {
00a97672
RS		 17443 const bfd_vma *plt0_entry;
17444 bfd_vma got_address, plt_address, got_displacement;
17445
17446 /* Calculate the addresses of the GOT and PLT. */
17447 got_address = sgot->output_section->vma + sgot->output_offset;
17448 plt_address = splt->output_section->vma + splt->output_offset;
17449
17450 if (htab->vxworks_p)
17451 {
17452 /* The VxWorks GOT is relocated by the dynamic linker.
17453 Therefore, we must emit relocations rather than simply
17454 computing the values now. */
17455 Elf_Internal_Rela rel;
17456
17457 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17458 put_arm_insn (htab, output_bfd, plt0_entry[0],
17459 splt->contents + 0);
17460 put_arm_insn (htab, output_bfd, plt0_entry[1],
17461 splt->contents + 4);
17462 put_arm_insn (htab, output_bfd, plt0_entry[2],
17463 splt->contents + 8);
00a97672
RS		 17464 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17465
8029a119 17466 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17467 rel.r_offset = plt_address + 12;
17468 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17469 rel.r_addend = 0;
17470 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17471 htab->srelplt2->contents);
17472 }
b38cadfb 17473 else if (htab->nacl_p)
99059e56
RM		 17474 arm_nacl_put_plt0 (htab, output_bfd, splt,
17475 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17476 else if (using_thumb_only (htab))
17477 {
17478 got_displacement = got_address - (plt_address + 12);
17479
17480 plt0_entry = elf32_thumb2_plt0_entry;
17481 put_arm_insn (htab, output_bfd, plt0_entry[0],
17482 splt->contents + 0);
17483 put_arm_insn (htab, output_bfd, plt0_entry[1],
17484 splt->contents + 4);
17485 put_arm_insn (htab, output_bfd, plt0_entry[2],
17486 splt->contents + 8);
17487
17488 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17489 }
00a97672
RS		 17490 else
17491 {
17492 got_displacement = got_address - (plt_address + 16);
17493
17494 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17495 put_arm_insn (htab, output_bfd, plt0_entry[0],
17496 splt->contents + 0);
17497 put_arm_insn (htab, output_bfd, plt0_entry[1],
17498 splt->contents + 4);
17499 put_arm_insn (htab, output_bfd, plt0_entry[2],
17500 splt->contents + 8);
17501 put_arm_insn (htab, output_bfd, plt0_entry[3],
17502 splt->contents + 12);
5e681ec4 17503
5e681ec4 17504#ifdef FOUR_WORD_PLT
00a97672
RS		 17505 /* The displacement value goes in the otherwise-unused
17506 last word of the second entry. */
17507 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17508#else
00a97672 17509 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17510#endif
00a97672 17511 }
f7a74f8c 17512 }
252b5132
RH		 17513
17514 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17515 really seem like the right value. */
74541ad4
AM		 17516 if (splt->output_section->owner == output_bfd)
17517 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17518
0855e32b
NS		 17519 if (htab->dt_tlsdesc_plt)
17520 {
17521 bfd_vma got_address
17522 = sgot->output_section->vma + sgot->output_offset;
17523 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17524 + htab->root.sgot->output_offset);
17525 bfd_vma plt_address
17526 = splt->output_section->vma + splt->output_offset;
17527
b38cadfb 17528 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17529 splt->contents + htab->dt_tlsdesc_plt,
17530 dl_tlsdesc_lazy_trampoline, 6);
17531
17532 bfd_put_32 (output_bfd,
17533 gotplt_address + htab->dt_tlsdesc_got
17534 - (plt_address + htab->dt_tlsdesc_plt)
17535 - dl_tlsdesc_lazy_trampoline[6],
17536 splt->contents + htab->dt_tlsdesc_plt + 24);
17537 bfd_put_32 (output_bfd,
17538 got_address - (plt_address + htab->dt_tlsdesc_plt)
17539 - dl_tlsdesc_lazy_trampoline[7],
17540 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17541 }
17542
17543 if (htab->tls_trampoline)
17544 {
b38cadfb 17545 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17546 splt->contents + htab->tls_trampoline,
17547 tls_trampoline, 3);
17548#ifdef FOUR_WORD_PLT
17549 bfd_put_32 (output_bfd, 0x00000000,
17550 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17551#endif
0855e32b
NS		 17552 }
17553
0e1862bb
L		 17554 if (htab->vxworks_p
17555 && !bfd_link_pic (info)
17556 && htab->root.splt->size > 0)
00a97672
RS		 17557 {
17558 /* Correct the .rel(a).plt.unloaded relocations. They will have
17559 incorrect symbol indexes. */
17560 int num_plts;
eed62c48 17561 unsigned char *p;
00a97672 17562
362d30a1 17563 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17564 / htab->plt_entry_size);
17565 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17566
17567 for (; num_plts; num_plts--)
17568 {
17569 Elf_Internal_Rela rel;
17570
17571 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17572 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17573 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17574 p += RELOC_SIZE (htab);
17575
17576 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17577 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17578 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17579 p += RELOC_SIZE (htab);
17580 }
17581 }
252b5132
RH		 17582 }
17583
99059e56
RM		 17584 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17585 /* NaCl uses a special first entry in .iplt too. */
17586 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17587
252b5132 17588 /* Fill in the first three entries in the global offset table. */
229fcec5 17589 if (sgot)
252b5132 17590 {
229fcec5
MM		 17591 if (sgot->size > 0)
17592 {
17593 if (sdyn == NULL)
17594 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17595 else
17596 bfd_put_32 (output_bfd,
17597 sdyn->output_section->vma + sdyn->output_offset,
17598 sgot->contents);
17599 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17600 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17601 }
252b5132 17602
229fcec5
MM		 17603 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17604 }
252b5132 17605
e8b09b87
CL		 17606 /* At the very end of the .rofixup section is a pointer to the GOT. */
17607 if (htab->fdpic_p && htab->srofixup != NULL)
17608 {
17609 struct elf_link_hash_entry *hgot = htab->root.hgot;
17610
17611 bfd_vma got_value = hgot->root.u.def.value
17612 + hgot->root.u.def.section->output_section->vma
17613 + hgot->root.u.def.section->output_offset;
17614
17615 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17616
17617 /* Make sure we allocated and generated the same number of fixups. */
17618 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17619 }
17620
b34976b6 17621 return TRUE;
252b5132
RH		 17622}
17623
ba96a88f 17624static void
57e8b36a 17625elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17626{
9b485d32 17627 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17628 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17629 struct elf_segment_map *m;
ba96a88f
NC		 17630
17631 i_ehdrp = elf_elfheader (abfd);
17632
94a3258f
PB		 17633 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17634 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17635 else
7394f108 17636 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17637 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17638
93204d3a
PB		 17639 if (link_info)
17640 {
17641 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17642 if (globals != NULL && globals->byteswap_code)
93204d3a 17643 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17644
17645 if (globals->fdpic_p)
17646 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17647 }
3bfcb652
NC		 17648
17649 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17650 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17651 {
17652 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17653 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17654 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17655 else
17656 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17657 }
ac4c9b04
MG		 17658
17659 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17660 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17661 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17662 {
17663 unsigned int j;
17664
17665 if (m->count == 0)
17666 continue;
17667 for (j = 0; j < m->count; j++)
17668 {
f0728ee3 17669 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17670 break;
17671 }
17672 if (j == m->count)
17673 {
17674 m->p_flags = PF_X;
17675 m->p_flags_valid = 1;
17676 }
17677 }
ba96a88f
NC		 17678}
17679
99e4ae17 17680static enum elf_reloc_type_class
7e612e98
AM		 17681elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17682 const asection *rel_sec ATTRIBUTE_UNUSED,
17683 const Elf_Internal_Rela *rela)
99e4ae17 17684{
f51e552e 17685 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17686 {
17687 case R_ARM_RELATIVE:
17688 return reloc_class_relative;
17689 case R_ARM_JUMP_SLOT:
17690 return reloc_class_plt;
17691 case R_ARM_COPY:
17692 return reloc_class_copy;
109575d7
JW		 17693 case R_ARM_IRELATIVE:
17694 return reloc_class_ifunc;
99e4ae17
AJ		 17695 default:
17696 return reloc_class_normal;
17697 }
17698}
17699
e489d0ae 17700static void
57e8b36a 17701elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 17702{
5a6c6817 17703 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17704}
17705
40a18ebd
NC		 17706/* Return TRUE if this is an unwinding table entry. */
17707
17708static bfd_boolean
17709is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17710{
0112cd26
NC		 17711 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17712 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17713}
17714
17715
17716/* Set the type and flags for an ARM section. We do this by
17717 the section name, which is a hack, but ought to work. */
17718
17719static bfd_boolean
17720elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17721{
17722 const char * name;
17723
17724 name = bfd_get_section_name (abfd, sec);
17725
17726 if (is_arm_elf_unwind_section_name (abfd, name))
17727 {
17728 hdr->sh_type = SHT_ARM_EXIDX;
17729 hdr->sh_flags |= SHF_LINK_ORDER;
17730 }
ac4c9b04 17731
f0728ee3
AV		 17732 if (sec->flags & SEC_ELF_PURECODE)
17733 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17734
40a18ebd
NC		 17735 return TRUE;
17736}
17737
6dc132d9
L		 17738/* Handle an ARM specific section when reading an object file. This is
17739 called when bfd_section_from_shdr finds a section with an unknown
17740 type. */
40a18ebd
NC		 17741
17742static bfd_boolean
17743elf32_arm_section_from_shdr (bfd *abfd,
17744 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17745 const char *name,
17746 int shindex)
40a18ebd
NC		 17747{
17748 /* There ought to be a place to keep ELF backend specific flags, but
17749 at the moment there isn't one. We just keep track of the
17750 sections by their name, instead. Fortunately, the ABI gives
17751 names for all the ARM specific sections, so we will probably get
17752 away with this. */
17753 switch (hdr->sh_type)
17754 {
17755 case SHT_ARM_EXIDX:
0951f019
RE		 17756 case SHT_ARM_PREEMPTMAP:
17757 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17758 break;
17759
17760 default:
17761 return FALSE;
17762 }
17763
6dc132d9 17764 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17765 return FALSE;
17766
17767 return TRUE;
17768}
e489d0ae 17769
44444f50
NC		 17770static _arm_elf_section_data *
17771get_arm_elf_section_data (asection * sec)
17772{
47b2e99c
JZ		 17773 if (sec && sec->owner && is_arm_elf (sec->owner))
17774 return elf32_arm_section_data (sec);
44444f50
NC		 17775 else
17776 return NULL;
8e3de13a
NC		 17777}
17778
4e617b1e
PB		 17779typedef struct
17780{
57402f1e 17781 void *flaginfo;
4e617b1e 17782 struct bfd_link_info *info;
91a5743d
PB		 17783 asection *sec;
17784 int sec_shndx;
6e0b88f1
AM		 17785 int (*func) (void *, const char *, Elf_Internal_Sym *,
17786 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17787} output_arch_syminfo;
17788
17789enum map_symbol_type
17790{
17791 ARM_MAP_ARM,
17792 ARM_MAP_THUMB,
17793 ARM_MAP_DATA
17794};
17795
17796
7413f23f 17797/* Output a single mapping symbol. */
4e617b1e
PB		 17798
17799static bfd_boolean
7413f23f
DJ		 17800elf32_arm_output_map_sym (output_arch_syminfo *osi,
17801 enum map_symbol_type type,
17802 bfd_vma offset)
4e617b1e
PB		 17803{
17804 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17805 Elf_Internal_Sym sym;
17806
91a5743d
PB		 17807 sym.st_value = osi->sec->output_section->vma
17808 + osi->sec->output_offset
17809 + offset;
4e617b1e
PB		 17810 sym.st_size = 0;
17811 sym.st_other = 0;
17812 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17813 sym.st_shndx = osi->sec_shndx;
35fc36a8 17814 sym.st_target_internal = 0;
fe33d2fa 17815 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17816 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17817}
17818
34e77a92
RS		 17819/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17820 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17821
17822static bfd_boolean
34e77a92
RS		 17823elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17824 bfd_boolean is_iplt_entry_p,
17825 union gotplt_union *root_plt,
17826 struct arm_plt_info *arm_plt)
4e617b1e 17827{
4e617b1e 17828 struct elf32_arm_link_hash_table *htab;
34e77a92 17829 bfd_vma addr, plt_header_size;
4e617b1e 17830
34e77a92 17831 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17832 return TRUE;
17833
4dfe6ac6
NC		 17834 htab = elf32_arm_hash_table (osi->info);
17835 if (htab == NULL)
17836 return FALSE;
17837
34e77a92
RS		 17838 if (is_iplt_entry_p)
17839 {
17840 osi->sec = htab->root.iplt;
17841 plt_header_size = 0;
17842 }
17843 else
17844 {
17845 osi->sec = htab->root.splt;
17846 plt_header_size = htab->plt_header_size;
17847 }
17848 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17849 (osi->info->output_bfd, osi->sec->output_section));
17850
17851 addr = root_plt->offset & -2;
4e617b1e
PB		 17852 if (htab->symbian_p)
17853 {
7413f23f 17854 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17855 return FALSE;
7413f23f 17856 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 17857 return FALSE;
17858 }
17859 else if (htab->vxworks_p)
17860 {
7413f23f 17861 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17862 return FALSE;
7413f23f 17863 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17864 return FALSE;
7413f23f 17865 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17866 return FALSE;
7413f23f 17867 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17868 return FALSE;
17869 }
b38cadfb
NC		 17870 else if (htab->nacl_p)
17871 {
17872 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17873 return FALSE;
17874 }
7801f98f
CL		 17875 else if (htab->fdpic_p)
17876 {
59029f57
CL		 17877 enum map_symbol_type type = using_thumb_only(htab)
17878 ? ARM_MAP_THUMB
17879 : ARM_MAP_ARM;
17880
7801f98f 17881 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 17882 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17883 return FALSE;
59029f57 17884 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 17885 return FALSE;
7801f98f 17886 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 17887 return FALSE;
7801f98f 17888 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 17889 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
17890 return FALSE;
7801f98f 17891 }
eed94f8f
NC		 17892 else if (using_thumb_only (htab))
17893 {
17894 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17895 return FALSE;
6a631e86 17896 }
4e617b1e
PB		 17897 else
17898 {
34e77a92 17899 bfd_boolean thumb_stub_p;
bd97cb95 17900
34e77a92
RS		 17901 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17902 if (thumb_stub_p)
4e617b1e 17903 {
7413f23f 17904 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17905 return FALSE;
17906 }
17907#ifdef FOUR_WORD_PLT
7413f23f 17908 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17909 return FALSE;
7413f23f 17910 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17911 return FALSE;
17912#else
906e58ca 17913 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17914 so only need to output a mapping symbol for the first PLT entry and
17915 entries with thumb thunks. */
34e77a92 17916 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17917 {
7413f23f 17918 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17919 return FALSE;
17920 }
17921#endif
17922 }
17923
17924 return TRUE;
17925}
17926
34e77a92
RS		 17927/* Output mapping symbols for PLT entries associated with H. */
17928
17929static bfd_boolean
17930elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17931{
17932 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17933 struct elf32_arm_link_hash_entry *eh;
17934
17935 if (h->root.type == bfd_link_hash_indirect)
17936 return TRUE;
17937
17938 if (h->root.type == bfd_link_hash_warning)
17939 /* When warning symbols are created, they **replace** the "real"
17940 entry in the hash table, thus we never get to see the real
17941 symbol in a hash traversal. So look at it now. */
17942 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17943
17944 eh = (struct elf32_arm_link_hash_entry *) h;
17945 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17946 &h->plt, &eh->plt);
17947}
17948
4f4faa4d
TP		 17949/* Bind a veneered symbol to its veneer identified by its hash entry
17950 STUB_ENTRY. The veneered location thus loose its symbol. */
17951
17952static void
17953arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17954{
17955 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17956
17957 BFD_ASSERT (hash);
17958 hash->root.root.u.def.section = stub_entry->stub_sec;
17959 hash->root.root.u.def.value = stub_entry->stub_offset;
17960 hash->root.size = stub_entry->stub_size;
17961}
17962
7413f23f
DJ		 17963/* Output a single local symbol for a generated stub. */
17964
17965static bfd_boolean
17966elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17967 bfd_vma offset, bfd_vma size)
17968{
7413f23f
DJ		 17969 Elf_Internal_Sym sym;
17970
7413f23f
DJ		 17971 sym.st_value = osi->sec->output_section->vma
17972 + osi->sec->output_offset
17973 + offset;
17974 sym.st_size = size;
17975 sym.st_other = 0;
17976 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17977 sym.st_shndx = osi->sec_shndx;
35fc36a8 17978 sym.st_target_internal = 0;
57402f1e 17979 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17980}
4e617b1e 17981
da5938a2 17982static bfd_boolean
8029a119
NC		 17983arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17984 void * in_arg)
da5938a2
NC		 17985{
17986 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17987 asection *stub_sec;
17988 bfd_vma addr;
7413f23f 17989 char *stub_name;
9a008db3 17990 output_arch_syminfo *osi;
d3ce72d0 17991 const insn_sequence *template_sequence;
461a49ca
DJ		 17992 enum stub_insn_type prev_type;
17993 int size;
17994 int i;
17995 enum map_symbol_type sym_type;
da5938a2
NC		 17996
17997 /* Massage our args to the form they really have. */
17998 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17999 osi = (output_arch_syminfo *) in_arg;
da5938a2 18000
da5938a2
NC		 18001 stub_sec = stub_entry->stub_sec;
18002
18003 /* Ensure this stub is attached to the current section being
7413f23f 18004 processed. */
da5938a2
NC		 18005 if (stub_sec != osi->sec)
18006 return TRUE;
18007
7413f23f 18008 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18009 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18010
18011 if (arm_stub_sym_claimed (stub_entry->stub_type))
18012 arm_stub_claim_sym (stub_entry);
18013 else
7413f23f 18014 {
4f4faa4d
TP		 18015 stub_name = stub_entry->output_name;
18016 switch (template_sequence[0].type)
18017 {
18018 case ARM_TYPE:
18019 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18020 stub_entry->stub_size))
18021 return FALSE;
18022 break;
18023 case THUMB16_TYPE:
18024 case THUMB32_TYPE:
18025 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18026 stub_entry->stub_size))
18027 return FALSE;
18028 break;
18029 default:
18030 BFD_FAIL ();
18031 return 0;
18032 }
7413f23f 18033 }
da5938a2 18034
461a49ca
DJ		 18035 prev_type = DATA_TYPE;
18036 size = 0;
18037 for (i = 0; i < stub_entry->stub_template_size; i++)
18038 {
d3ce72d0 18039 switch (template_sequence[i].type)
461a49ca
DJ		 18040 {
18041 case ARM_TYPE:
18042 sym_type = ARM_MAP_ARM;
18043 break;
18044
18045 case THUMB16_TYPE:
48229727 18046 case THUMB32_TYPE:
461a49ca
DJ		 18047 sym_type = ARM_MAP_THUMB;
18048 break;
18049
18050 case DATA_TYPE:
18051 sym_type = ARM_MAP_DATA;
18052 break;
18053
18054 default:
18055 BFD_FAIL ();
4e31c731 18056 return FALSE;
461a49ca
DJ		 18057 }
18058
d3ce72d0 18059 if (template_sequence[i].type != prev_type)
461a49ca 18060 {
d3ce72d0 18061 prev_type = template_sequence[i].type;
461a49ca
DJ		 18062 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18063 return FALSE;
18064 }
18065
d3ce72d0 18066 switch (template_sequence[i].type)
461a49ca
DJ		 18067 {
18068 case ARM_TYPE:
48229727 18069 case THUMB32_TYPE:
461a49ca
DJ		 18070 size += 4;
18071 break;
18072
18073 case THUMB16_TYPE:
18074 size += 2;
18075 break;
18076
18077 case DATA_TYPE:
18078 size += 4;
18079 break;
18080
18081 default:
18082 BFD_FAIL ();
4e31c731 18083 return FALSE;
461a49ca
DJ		 18084 }
18085 }
18086
da5938a2
NC		 18087 return TRUE;
18088}
18089
33811162
DG		 18090/* Output mapping symbols for linker generated sections,
18091 and for those data-only sections that do not have a
18092 $d. */
4e617b1e
PB		 18093
18094static bfd_boolean
18095elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18096 struct bfd_link_info *info,
57402f1e 18097 void *flaginfo,
6e0b88f1
AM		 18098 int (*func) (void *, const char *,
18099 Elf_Internal_Sym *,
18100 asection *,
18101 struct elf_link_hash_entry *))
4e617b1e
PB		 18102{
18103 output_arch_syminfo osi;
18104 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18105 bfd_vma offset;
18106 bfd_size_type size;
33811162 18107 bfd *input_bfd;
4e617b1e
PB		 18108
18109 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18110 if (htab == NULL)
18111 return FALSE;
18112
906e58ca 18113 check_use_blx (htab);
91a5743d 18114
57402f1e 18115 osi.flaginfo = flaginfo;
4e617b1e
PB		 18116 osi.info = info;
18117 osi.func = func;
906e58ca 18118
33811162
DG		 18119 /* Add a $d mapping symbol to data-only sections that
18120 don't have any mapping symbol. This may result in (harmless) redundant
18121 mapping symbols. */
18122 for (input_bfd = info->input_bfds;
18123 input_bfd != NULL;
c72f2fb2 18124 input_bfd = input_bfd->link.next)
33811162
DG		 18125 {
18126 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18127 for (osi.sec = input_bfd->sections;
18128 osi.sec != NULL;
18129 osi.sec = osi.sec->next)
18130 {
18131 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18132 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18133 != 0)
33811162
DG		 18134 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18135 == SEC_HAS_CONTENTS
18136 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18137 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18138 && osi.sec->size > 0
18139 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18140 {
18141 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18142 (output_bfd, osi.sec->output_section);
18143 if (osi.sec_shndx != (int)SHN_BAD)
18144 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18145 }
18146 }
18147 }
18148
91a5743d
PB		 18149 /* ARM->Thumb glue. */
18150 if (htab->arm_glue_size > 0)
18151 {
3d4d4302
AM		 18152 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18153 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18154
18155 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18156 (output_bfd, osi.sec->output_section);
0e1862bb 18157 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18158 || htab->pic_veneer)
18159 size = ARM2THUMB_PIC_GLUE_SIZE;
18160 else if (htab->use_blx)
18161 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18162 else
18163 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18164
91a5743d
PB		 18165 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18166 {
7413f23f
DJ		 18167 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18168 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18169 }
18170 }
18171
18172 /* Thumb->ARM glue. */
18173 if (htab->thumb_glue_size > 0)
18174 {
3d4d4302
AM		 18175 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18176 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18177
18178 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18179 (output_bfd, osi.sec->output_section);
18180 size = THUMB2ARM_GLUE_SIZE;
18181
18182 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18183 {
7413f23f
DJ		 18184 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18185 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18186 }
18187 }
18188
845b51d6
PB		 18189 /* ARMv4 BX veneers. */
18190 if (htab->bx_glue_size > 0)
18191 {
3d4d4302
AM		 18192 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18193 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18194
18195 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18196 (output_bfd, osi.sec->output_section);
18197
7413f23f 18198 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18199 }
18200
8029a119
NC		 18201 /* Long calls stubs. */
18202 if (htab->stub_bfd && htab->stub_bfd->sections)
18203 {
da5938a2 18204 asection* stub_sec;
8029a119 18205
da5938a2
NC		 18206 for (stub_sec = htab->stub_bfd->sections;
18207 stub_sec != NULL;
8029a119
NC		 18208 stub_sec = stub_sec->next)
18209 {
18210 /* Ignore non-stub sections. */
18211 if (!strstr (stub_sec->name, STUB_SUFFIX))
18212 continue;
da5938a2 18213
8029a119 18214 osi.sec = stub_sec;
da5938a2 18215
8029a119
NC		 18216 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18217 (output_bfd, osi.sec->output_section);
da5938a2 18218
8029a119
NC		 18219 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18220 }
18221 }
da5938a2 18222
91a5743d 18223 /* Finally, output mapping symbols for the PLT. */
34e77a92 18224 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18225 {
34e77a92
RS		 18226 osi.sec = htab->root.splt;
18227 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18228 (output_bfd, osi.sec->output_section));
18229
18230 /* Output mapping symbols for the plt header. SymbianOS does not have a
18231 plt header. */
18232 if (htab->vxworks_p)
18233 {
18234 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18235 if (!bfd_link_pic (info))
34e77a92
RS		 18236 {
18237 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18238 return FALSE;
18239 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18240 return FALSE;
18241 }
18242 }
b38cadfb
NC		 18243 else if (htab->nacl_p)
18244 {
18245 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18246 return FALSE;
18247 }
59029f57 18248 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18249 {
18250 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18251 return FALSE;
18252 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18253 return FALSE;
18254 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18255 return FALSE;
18256 }
e8b09b87 18257 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18258 {
7413f23f 18259 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18260 return FALSE;
34e77a92
RS		 18261#ifndef FOUR_WORD_PLT
18262 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18263 return FALSE;
34e77a92 18264#endif
4e617b1e
PB		 18265 }
18266 }
99059e56
RM		 18267 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18268 {
18269 /* NaCl uses a special first entry in .iplt too. */
18270 osi.sec = htab->root.iplt;
18271 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18272 (output_bfd, osi.sec->output_section));
18273 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18274 return FALSE;
18275 }
34e77a92
RS		 18276 if ((htab->root.splt && htab->root.splt->size > 0)
18277 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18278 {
34e77a92
RS		 18279 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18280 for (input_bfd = info->input_bfds;
18281 input_bfd != NULL;
c72f2fb2 18282 input_bfd = input_bfd->link.next)
34e77a92
RS		 18283 {
18284 struct arm_local_iplt_info **local_iplt;
18285 unsigned int i, num_syms;
4e617b1e 18286
34e77a92
RS		 18287 local_iplt = elf32_arm_local_iplt (input_bfd);
18288 if (local_iplt != NULL)
18289 {
18290 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18291 for (i = 0; i < num_syms; i++)
18292 if (local_iplt[i] != NULL
18293 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18294 &local_iplt[i]->root,
18295 &local_iplt[i]->arm))
18296 return FALSE;
18297 }
18298 }
18299 }
0855e32b
NS		 18300 if (htab->dt_tlsdesc_plt != 0)
18301 {
18302 /* Mapping symbols for the lazy tls trampoline. */
18303 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18304 return FALSE;
b38cadfb 18305
0855e32b
NS		 18306 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18307 htab->dt_tlsdesc_plt + 24))
18308 return FALSE;
18309 }
18310 if (htab->tls_trampoline != 0)
18311 {
18312 /* Mapping symbols for the tls trampoline. */
18313 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18314 return FALSE;
18315#ifdef FOUR_WORD_PLT
18316 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18317 htab->tls_trampoline + 12))
18318 return FALSE;
b38cadfb 18319#endif
0855e32b 18320 }
b38cadfb 18321
4e617b1e
PB		 18322 return TRUE;
18323}
18324
54ddd295
TP		 18325/* Filter normal symbols of CMSE entry functions of ABFD to include in
18326 the import library. All SYMCOUNT symbols of ABFD can be examined
18327 from their pointers in SYMS. Pointers of symbols to keep should be
18328 stored continuously at the beginning of that array.
18329
18330 Returns the number of symbols to keep. */
18331
18332static unsigned int
18333elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18334 struct bfd_link_info *info,
18335 asymbol **syms, long symcount)
18336{
18337 size_t maxnamelen;
18338 char *cmse_name;
18339 long src_count, dst_count = 0;
18340 struct elf32_arm_link_hash_table *htab;
18341
18342 htab = elf32_arm_hash_table (info);
18343 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18344 symcount = 0;
18345
18346 maxnamelen = 128;
18347 cmse_name = (char *) bfd_malloc (maxnamelen);
18348 for (src_count = 0; src_count < symcount; src_count++)
18349 {
18350 struct elf32_arm_link_hash_entry *cmse_hash;
18351 asymbol *sym;
18352 flagword flags;
18353 char *name;
18354 size_t namelen;
18355
18356 sym = syms[src_count];
18357 flags = sym->flags;
18358 name = (char *) bfd_asymbol_name (sym);
18359
18360 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18361 continue;
18362 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18363 continue;
18364
18365 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18366 if (namelen > maxnamelen)
18367 {
18368 cmse_name = (char *)
18369 bfd_realloc (cmse_name, namelen);
18370 maxnamelen = namelen;
18371 }
18372 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18373 cmse_hash = (struct elf32_arm_link_hash_entry *)
18374 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18375
18376 if (!cmse_hash
18377 || (cmse_hash->root.root.type != bfd_link_hash_defined
18378 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18379 || cmse_hash->root.type != STT_FUNC)
18380 continue;
18381
18382 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
18383 continue;
18384
18385 syms[dst_count++] = sym;
18386 }
18387 free (cmse_name);
18388
18389 syms[dst_count] = NULL;
18390
18391 return dst_count;
18392}
18393
18394/* Filter symbols of ABFD to include in the import library. All
18395 SYMCOUNT symbols of ABFD can be examined from their pointers in
18396 SYMS. Pointers of symbols to keep should be stored continuously at
18397 the beginning of that array.
18398
18399 Returns the number of symbols to keep. */
18400
18401static unsigned int
18402elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18403 struct bfd_link_info *info,
18404 asymbol **syms, long symcount)
18405{
18406 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18407
046734ff
TP		 18408 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18409 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18410 library to be a relocatable object file. */
18411 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18412 if (globals->cmse_implib)
18413 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18414 else
18415 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18416}
18417
e489d0ae
PB		 18418/* Allocate target specific section data. */
18419
18420static bfd_boolean
18421elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18422{
f592407e
AM		 18423 if (!sec->used_by_bfd)
18424 {
18425 _arm_elf_section_data *sdata;
18426 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18427
21d799b5 18428 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18429 if (sdata == NULL)
18430 return FALSE;
18431 sec->used_by_bfd = sdata;
18432 }
e489d0ae
PB		 18433
18434 return _bfd_elf_new_section_hook (abfd, sec);
18435}
18436
18437
18438/* Used to order a list of mapping symbols by address. */
18439
18440static int
18441elf32_arm_compare_mapping (const void * a, const void * b)
18442{
7f6a71ff
JM		 18443 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18444 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18445
18446 if (amap->vma > bmap->vma)
18447 return 1;
18448 else if (amap->vma < bmap->vma)
18449 return -1;
18450 else if (amap->type > bmap->type)
18451 /* Ensure results do not depend on the host qsort for objects with
18452 multiple mapping symbols at the same address by sorting on type
18453 after vma. */
18454 return 1;
18455 else if (amap->type < bmap->type)
18456 return -1;
18457 else
18458 return 0;
e489d0ae
PB		 18459}
18460
2468f9c9
PB		 18461/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18462
18463static unsigned long
18464offset_prel31 (unsigned long addr, bfd_vma offset)
18465{
18466 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18467}
18468
18469/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18470 relocations. */
18471
18472static void
18473copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18474{
18475 unsigned long first_word = bfd_get_32 (output_bfd, from);
18476 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18477
2468f9c9
PB		 18478 /* High bit of first word is supposed to be zero. */
18479 if ((first_word & 0x80000000ul) == 0)
18480 first_word = offset_prel31 (first_word, offset);
b38cadfb 18481
2468f9c9
PB		 18482 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18483 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18484 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18485 second_word = offset_prel31 (second_word, offset);
b38cadfb 18486
2468f9c9
PB		 18487 bfd_put_32 (output_bfd, first_word, to);
18488 bfd_put_32 (output_bfd, second_word, to + 4);
18489}
e489d0ae 18490
48229727
JB		 18491/* Data for make_branch_to_a8_stub(). */
18492
b38cadfb
NC		 18493struct a8_branch_to_stub_data
18494{
48229727
JB		 18495 asection *writing_section;
18496 bfd_byte *contents;
18497};
18498
18499
18500/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18501 places for a particular section. */
18502
18503static bfd_boolean
18504make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18505 void *in_arg)
48229727
JB		 18506{
18507 struct elf32_arm_stub_hash_entry *stub_entry;
18508 struct a8_branch_to_stub_data *data;
18509 bfd_byte *contents;
18510 unsigned long branch_insn;
18511 bfd_vma veneered_insn_loc, veneer_entry_loc;
18512 bfd_signed_vma branch_offset;
18513 bfd *abfd;
8d9d9490 18514 unsigned int loc;
48229727
JB		 18515
18516 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18517 data = (struct a8_branch_to_stub_data *) in_arg;
18518
18519 if (stub_entry->target_section != data->writing_section
4563a860 18520 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18521 return TRUE;
18522
18523 contents = data->contents;
18524
8d9d9490
TP		 18525 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18526 generated when both source and target are in the same section. */
48229727
JB		 18527 veneered_insn_loc = stub_entry->target_section->output_section->vma
18528 + stub_entry->target_section->output_offset
8d9d9490 18529 + stub_entry->source_value;
48229727
JB		 18530
18531 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18532 + stub_entry->stub_sec->output_offset
18533 + stub_entry->stub_offset;
18534
18535 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18536 veneered_insn_loc &= ~3u;
18537
18538 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18539
18540 abfd = stub_entry->target_section->owner;
8d9d9490 18541 loc = stub_entry->source_value;
48229727
JB		 18542
18543 /* We attempt to avoid this condition by setting stubs_always_after_branch
18544 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18545 This check is just to be on the safe side... */
18546 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18547 {
871b3ab2 18548 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18549 "allocated in unsafe location"), abfd);
48229727
JB		 18550 return FALSE;
18551 }
18552
18553 switch (stub_entry->stub_type)
18554 {
18555 case arm_stub_a8_veneer_b:
18556 case arm_stub_a8_veneer_b_cond:
18557 branch_insn = 0xf0009000;
18558 goto jump24;
18559
18560 case arm_stub_a8_veneer_blx:
18561 branch_insn = 0xf000e800;
18562 goto jump24;
18563
18564 case arm_stub_a8_veneer_bl:
18565 {
18566 unsigned int i1, j1, i2, j2, s;
18567
18568 branch_insn = 0xf000d000;
18569
18570 jump24:
18571 if (branch_offset < -16777216 || branch_offset > 16777214)
18572 {
18573 /* There's not much we can do apart from complain if this
18574 happens. */
871b3ab2 18575 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18576 "of range (input file too large)"), abfd);
48229727
JB		 18577 return FALSE;
18578 }
18579
18580 /* i1 = not(j1 eor s), so:
18581 not i1 = j1 eor s
18582 j1 = (not i1) eor s. */
18583
18584 branch_insn |= (branch_offset >> 1) & 0x7ff;
18585 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18586 i2 = (branch_offset >> 22) & 1;
18587 i1 = (branch_offset >> 23) & 1;
18588 s = (branch_offset >> 24) & 1;
18589 j1 = (!i1) ^ s;
18590 j2 = (!i2) ^ s;
18591 branch_insn |= j2 << 11;
18592 branch_insn |= j1 << 13;
18593 branch_insn |= s << 26;
18594 }
18595 break;
18596
18597 default:
18598 BFD_FAIL ();
18599 return FALSE;
18600 }
18601
8d9d9490
TP		 18602 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18603 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18604
18605 return TRUE;
18606}
18607
a504d23a
LA		 18608/* Beginning of stm32l4xx work-around. */
18609
18610/* Functions encoding instructions necessary for the emission of the
18611 fix-stm32l4xx-629360.
18612 Encoding is extracted from the
18613 ARM (C) Architecture Reference Manual
18614 ARMv7-A and ARMv7-R edition
18615 ARM DDI 0406C.b (ID072512). */
18616
18617static inline bfd_vma
82188b29 18618create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18619{
18620 /* A8.8.18 B (A8-334)
18621 B target_address (Encoding T4). */
18622 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18623 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18624 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18625
a504d23a
LA		 18626 int s = ((branch_offset & 0x1000000) >> 24);
18627 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18628 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18629
18630 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18631 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18632
18633 bfd_vma patched_inst = 0xf0009000
18634 | s << 26 /* S. */
18635 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18636 | j1 << 13 /* J1. */
18637 | j2 << 11 /* J2. */
18638 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18639
18640 return patched_inst;
18641}
18642
18643static inline bfd_vma
18644create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18645{
18646 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18647 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18648 bfd_vma patched_inst = 0xe8900000
18649 | (/*W=*/wback << 21)
18650 | (base_reg << 16)
18651 | (reg_mask & 0x0000ffff);
18652
18653 return patched_inst;
18654}
18655
18656static inline bfd_vma
18657create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18658{
18659 /* A8.8.60 LDMDB/LDMEA (A8-402)
18660 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18661 bfd_vma patched_inst = 0xe9100000
18662 | (/*W=*/wback << 21)
18663 | (base_reg << 16)
18664 | (reg_mask & 0x0000ffff);
18665
18666 return patched_inst;
18667}
18668
18669static inline bfd_vma
18670create_instruction_mov (int target_reg, int source_reg)
18671{
18672 /* A8.8.103 MOV (register) (A8-486)
18673 MOV Rd, Rm (Encoding T1). */
18674 bfd_vma patched_inst = 0x4600
18675 | (target_reg & 0x7)
18676 | ((target_reg & 0x8) >> 3) << 7
18677 | (source_reg << 3);
18678
18679 return patched_inst;
18680}
18681
18682static inline bfd_vma
18683create_instruction_sub (int target_reg, int source_reg, int value)
18684{
18685 /* A8.8.221 SUB (immediate) (A8-708)
18686 SUB Rd, Rn, #value (Encoding T3). */
18687 bfd_vma patched_inst = 0xf1a00000
18688 | (target_reg << 8)
18689 | (source_reg << 16)
18690 | (/*S=*/0 << 20)
18691 | ((value & 0x800) >> 11) << 26
18692 | ((value & 0x700) >> 8) << 12
18693 | (value & 0x0ff);
18694
18695 return patched_inst;
18696}
18697
18698static inline bfd_vma
9239bbd3 18699create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18700 int first_reg)
18701{
18702 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18703 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18704 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18705 | (/*W=*/wback << 21)
18706 | (base_reg << 16)
9239bbd3
CM		 18707 | (num_words & 0x000000ff)
18708 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18709 | (first_reg & 0x00000001) << 22;
18710
18711 return patched_inst;
18712}
18713
18714static inline bfd_vma
9239bbd3
CM		 18715create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18716 int first_reg)
a504d23a
LA		 18717{
18718 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18719 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18720 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18721 | (base_reg << 16)
9239bbd3
CM		 18722 | (num_words & 0x000000ff)
18723 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18724 | (first_reg & 0x00000001) << 22;
18725
18726 return patched_inst;
18727}
18728
18729static inline bfd_vma
18730create_instruction_udf_w (int value)
18731{
18732 /* A8.8.247 UDF (A8-758)
18733 Undefined (Encoding T2). */
18734 bfd_vma patched_inst = 0xf7f0a000
18735 | (value & 0x00000fff)
18736 | (value & 0x000f0000) << 16;
18737
18738 return patched_inst;
18739}
18740
18741static inline bfd_vma
18742create_instruction_udf (int value)
18743{
18744 /* A8.8.247 UDF (A8-758)
18745 Undefined (Encoding T1). */
18746 bfd_vma patched_inst = 0xde00
18747 | (value & 0xff);
18748
18749 return patched_inst;
18750}
18751
18752/* Functions writing an instruction in memory, returning the next
18753 memory position to write to. */
18754
18755static inline bfd_byte *
18756push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18757 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18758{
18759 put_thumb2_insn (htab, output_bfd, insn, pt);
18760 return pt + 4;
18761}
18762
18763static inline bfd_byte *
18764push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18765 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18766{
18767 put_thumb_insn (htab, output_bfd, insn, pt);
18768 return pt + 2;
18769}
18770
18771/* Function filling up a region in memory with T1 and T2 UDFs taking
18772 care of alignment. */
18773
18774static bfd_byte *
18775stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18776 bfd * output_bfd,
18777 const bfd_byte * const base_stub_contents,
18778 bfd_byte * const from_stub_contents,
18779 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18780{
18781 bfd_byte *current_stub_contents = from_stub_contents;
18782
18783 /* Fill the remaining of the stub with deterministic contents : UDF
18784 instructions.
18785 Check if realignment is needed on modulo 4 frontier using T1, to
18786 further use T2. */
18787 if ((current_stub_contents < end_stub_contents)
18788 && !((current_stub_contents - base_stub_contents) % 2)
18789 && ((current_stub_contents - base_stub_contents) % 4))
18790 current_stub_contents =
18791 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18792 create_instruction_udf (0));
18793
18794 for (; current_stub_contents < end_stub_contents;)
18795 current_stub_contents =
18796 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18797 create_instruction_udf_w (0));
18798
18799 return current_stub_contents;
18800}
18801
18802/* Functions writing the stream of instructions equivalent to the
18803 derived sequence for ldmia, ldmdb, vldm respectively. */
18804
18805static void
18806stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18807 bfd * output_bfd,
18808 const insn32 initial_insn,
18809 const bfd_byte *const initial_insn_addr,
18810 bfd_byte *const base_stub_contents)
18811{
18812 int wback = (initial_insn & 0x00200000) >> 21;
18813 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18814 int insn_all_registers = initial_insn & 0x0000ffff;
18815 int insn_low_registers, insn_high_registers;
18816 int usable_register_mask;
b25e998d 18817 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18818 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18819 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18820 bfd_byte *current_stub_contents = base_stub_contents;
18821
18822 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18823
18824 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18825 smaller than 8 registers load sequences that do not cause the
18826 hardware issue. */
18827 if (nb_registers <= 8)
18828 {
18829 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18830 current_stub_contents =
18831 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18832 initial_insn);
18833
18834 /* B initial_insn_addr+4. */
18835 if (!restore_pc)
18836 current_stub_contents =
18837 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18838 create_instruction_branch_absolute
82188b29 18839 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18840
18841 /* Fill the remaining of the stub with deterministic contents. */
18842 current_stub_contents =
18843 stm32l4xx_fill_stub_udf (htab, output_bfd,
18844 base_stub_contents, current_stub_contents,
18845 base_stub_contents +
18846 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18847
18848 return;
18849 }
18850
18851 /* - reg_list[13] == 0. */
18852 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18853
18854 /* - reg_list[14] & reg_list[15] != 1. */
18855 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18856
18857 /* - if (wback==1) reg_list[rn] == 0. */
18858 BFD_ASSERT (!wback || !restore_rn);
18859
18860 /* - nb_registers > 8. */
b25e998d 18861 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18862
18863 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18864
18865 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18866 - One with the 7 lowest registers (register mask 0x007F)
18867 This LDM will finally contain between 2 and 7 registers
18868 - One with the 7 highest registers (register mask 0xDF80)
18869 This ldm will finally contain between 2 and 7 registers. */
18870 insn_low_registers = insn_all_registers & 0x007F;
18871 insn_high_registers = insn_all_registers & 0xDF80;
18872
18873 /* A spare register may be needed during this veneer to temporarily
18874 handle the base register. This register will be restored with the
18875 last LDM operation.
18876 The usable register may be any general purpose register (that
18877 excludes PC, SP, LR : register mask is 0x1FFF). */
18878 usable_register_mask = 0x1FFF;
18879
18880 /* Generate the stub function. */
18881 if (wback)
18882 {
18883 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18884 current_stub_contents =
18885 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18886 create_instruction_ldmia
18887 (rn, /*wback=*/1, insn_low_registers));
18888
18889 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18890 current_stub_contents =
18891 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18892 create_instruction_ldmia
18893 (rn, /*wback=*/1, insn_high_registers));
18894 if (!restore_pc)
18895 {
18896 /* B initial_insn_addr+4. */
18897 current_stub_contents =
18898 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18899 create_instruction_branch_absolute
82188b29 18900 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18901 }
18902 }
18903 else /* if (!wback). */
18904 {
18905 ri = rn;
18906
18907 /* If Rn is not part of the high-register-list, move it there. */
18908 if (!(insn_high_registers & (1 << rn)))
18909 {
18910 /* Choose a Ri in the high-register-list that will be restored. */
18911 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18912
18913 /* MOV Ri, Rn. */
18914 current_stub_contents =
18915 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18916 create_instruction_mov (ri, rn));
18917 }
18918
18919 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18920 current_stub_contents =
18921 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18922 create_instruction_ldmia
18923 (ri, /*wback=*/1, insn_low_registers));
18924
18925 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18926 current_stub_contents =
18927 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18928 create_instruction_ldmia
18929 (ri, /*wback=*/0, insn_high_registers));
18930
18931 if (!restore_pc)
18932 {
18933 /* B initial_insn_addr+4. */
18934 current_stub_contents =
18935 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18936 create_instruction_branch_absolute
82188b29 18937 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18938 }
18939 }
18940
18941 /* Fill the remaining of the stub with deterministic contents. */
18942 current_stub_contents =
18943 stm32l4xx_fill_stub_udf (htab, output_bfd,
18944 base_stub_contents, current_stub_contents,
18945 base_stub_contents +
18946 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18947}
18948
18949static void
18950stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18951 bfd * output_bfd,
18952 const insn32 initial_insn,
18953 const bfd_byte *const initial_insn_addr,
18954 bfd_byte *const base_stub_contents)
18955{
18956 int wback = (initial_insn & 0x00200000) >> 21;
18957 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18958 int insn_all_registers = initial_insn & 0x0000ffff;
18959 int insn_low_registers, insn_high_registers;
18960 int usable_register_mask;
18961 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18962 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18963 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18964 bfd_byte *current_stub_contents = base_stub_contents;
18965
18966 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18967
18968 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18969 smaller than 8 registers load sequences that do not cause the
18970 hardware issue. */
18971 if (nb_registers <= 8)
18972 {
18973 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18974 current_stub_contents =
18975 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18976 initial_insn);
18977
18978 /* B initial_insn_addr+4. */
18979 current_stub_contents =
18980 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18981 create_instruction_branch_absolute
82188b29 18982 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18983
18984 /* Fill the remaining of the stub with deterministic contents. */
18985 current_stub_contents =
18986 stm32l4xx_fill_stub_udf (htab, output_bfd,
18987 base_stub_contents, current_stub_contents,
18988 base_stub_contents +
18989 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18990
18991 return;
18992 }
18993
18994 /* - reg_list[13] == 0. */
18995 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18996
18997 /* - reg_list[14] & reg_list[15] != 1. */
18998 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18999
19000 /* - if (wback==1) reg_list[rn] == 0. */
19001 BFD_ASSERT (!wback || !restore_rn);
19002
19003 /* - nb_registers > 8. */
b25e998d 19004 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19005
19006 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19007
19008 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19009 - One with the 7 lowest registers (register mask 0x007F)
19010 This LDM will finally contain between 2 and 7 registers
19011 - One with the 7 highest registers (register mask 0xDF80)
19012 This ldm will finally contain between 2 and 7 registers. */
19013 insn_low_registers = insn_all_registers & 0x007F;
19014 insn_high_registers = insn_all_registers & 0xDF80;
19015
19016 /* A spare register may be needed during this veneer to temporarily
19017 handle the base register. This register will be restored with
19018 the last LDM operation.
19019 The usable register may be any general purpose register (that excludes
19020 PC, SP, LR : register mask is 0x1FFF). */
19021 usable_register_mask = 0x1FFF;
19022
19023 /* Generate the stub function. */
19024 if (!wback && !restore_pc && !restore_rn)
19025 {
19026 /* Choose a Ri in the low-register-list that will be restored. */
19027 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19028
19029 /* MOV Ri, Rn. */
19030 current_stub_contents =
19031 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19032 create_instruction_mov (ri, rn));
19033
19034 /* LDMDB Ri!, {R-high-register-list}. */
19035 current_stub_contents =
19036 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19037 create_instruction_ldmdb
19038 (ri, /*wback=*/1, insn_high_registers));
19039
19040 /* LDMDB Ri, {R-low-register-list}. */
19041 current_stub_contents =
19042 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19043 create_instruction_ldmdb
19044 (ri, /*wback=*/0, insn_low_registers));
19045
19046 /* B initial_insn_addr+4. */
19047 current_stub_contents =
19048 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19049 create_instruction_branch_absolute
82188b29 19050 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19051 }
19052 else if (wback && !restore_pc && !restore_rn)
19053 {
19054 /* LDMDB Rn!, {R-high-register-list}. */
19055 current_stub_contents =
19056 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19057 create_instruction_ldmdb
19058 (rn, /*wback=*/1, insn_high_registers));
19059
19060 /* LDMDB Rn!, {R-low-register-list}. */
19061 current_stub_contents =
19062 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19063 create_instruction_ldmdb
19064 (rn, /*wback=*/1, insn_low_registers));
19065
19066 /* B initial_insn_addr+4. */
19067 current_stub_contents =
19068 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19069 create_instruction_branch_absolute
82188b29 19070 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19071 }
19072 else if (!wback && restore_pc && !restore_rn)
19073 {
19074 /* Choose a Ri in the high-register-list that will be restored. */
19075 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19076
19077 /* SUB Ri, Rn, #(4*nb_registers). */
19078 current_stub_contents =
19079 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19080 create_instruction_sub (ri, rn, (4 * nb_registers)));
19081
19082 /* LDMIA Ri!, {R-low-register-list}. */
19083 current_stub_contents =
19084 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19085 create_instruction_ldmia
19086 (ri, /*wback=*/1, insn_low_registers));
19087
19088 /* LDMIA Ri, {R-high-register-list}. */
19089 current_stub_contents =
19090 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19091 create_instruction_ldmia
19092 (ri, /*wback=*/0, insn_high_registers));
19093 }
19094 else if (wback && restore_pc && !restore_rn)
19095 {
19096 /* Choose a Ri in the high-register-list that will be restored. */
19097 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19098
19099 /* SUB Rn, Rn, #(4*nb_registers) */
19100 current_stub_contents =
19101 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19102 create_instruction_sub (rn, rn, (4 * nb_registers)));
19103
19104 /* MOV Ri, Rn. */
19105 current_stub_contents =
19106 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19107 create_instruction_mov (ri, rn));
19108
19109 /* LDMIA Ri!, {R-low-register-list}. */
19110 current_stub_contents =
19111 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19112 create_instruction_ldmia
19113 (ri, /*wback=*/1, insn_low_registers));
19114
19115 /* LDMIA Ri, {R-high-register-list}. */
19116 current_stub_contents =
19117 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19118 create_instruction_ldmia
19119 (ri, /*wback=*/0, insn_high_registers));
19120 }
19121 else if (!wback && !restore_pc && restore_rn)
19122 {
19123 ri = rn;
19124 if (!(insn_low_registers & (1 << rn)))
19125 {
19126 /* Choose a Ri in the low-register-list that will be restored. */
19127 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19128
19129 /* MOV Ri, Rn. */
19130 current_stub_contents =
19131 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19132 create_instruction_mov (ri, rn));
19133 }
19134
19135 /* LDMDB Ri!, {R-high-register-list}. */
19136 current_stub_contents =
19137 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19138 create_instruction_ldmdb
19139 (ri, /*wback=*/1, insn_high_registers));
19140
19141 /* LDMDB Ri, {R-low-register-list}. */
19142 current_stub_contents =
19143 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19144 create_instruction_ldmdb
19145 (ri, /*wback=*/0, insn_low_registers));
19146
19147 /* B initial_insn_addr+4. */
19148 current_stub_contents =
19149 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19150 create_instruction_branch_absolute
82188b29 19151 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19152 }
19153 else if (!wback && restore_pc && restore_rn)
19154 {
19155 ri = rn;
19156 if (!(insn_high_registers & (1 << rn)))
19157 {
19158 /* Choose a Ri in the high-register-list that will be restored. */
19159 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19160 }
19161
19162 /* SUB Ri, Rn, #(4*nb_registers). */
19163 current_stub_contents =
19164 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19165 create_instruction_sub (ri, rn, (4 * nb_registers)));
19166
19167 /* LDMIA Ri!, {R-low-register-list}. */
19168 current_stub_contents =
19169 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19170 create_instruction_ldmia
19171 (ri, /*wback=*/1, insn_low_registers));
19172
19173 /* LDMIA Ri, {R-high-register-list}. */
19174 current_stub_contents =
19175 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19176 create_instruction_ldmia
19177 (ri, /*wback=*/0, insn_high_registers));
19178 }
19179 else if (wback && restore_rn)
19180 {
19181 /* The assembler should not have accepted to encode this. */
19182 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19183 "undefined behavior.\n");
19184 }
19185
19186 /* Fill the remaining of the stub with deterministic contents. */
19187 current_stub_contents =
19188 stm32l4xx_fill_stub_udf (htab, output_bfd,
19189 base_stub_contents, current_stub_contents,
19190 base_stub_contents +
19191 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19192
19193}
19194
19195static void
19196stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19197 bfd * output_bfd,
19198 const insn32 initial_insn,
19199 const bfd_byte *const initial_insn_addr,
19200 bfd_byte *const base_stub_contents)
19201{
9239bbd3 19202 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19203 bfd_byte *current_stub_contents = base_stub_contents;
19204
19205 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19206
19207 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19208 smaller than 8 words load sequences that do not cause the
a504d23a 19209 hardware issue. */
9239bbd3 19210 if (num_words <= 8)
a504d23a
LA		 19211 {
19212 /* Untouched instruction. */
19213 current_stub_contents =
19214 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19215 initial_insn);
19216
19217 /* B initial_insn_addr+4. */
19218 current_stub_contents =
19219 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19220 create_instruction_branch_absolute
82188b29 19221 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19222 }
19223 else
19224 {
9eaff861 19225 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19226 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19227 bfd_boolean is_ia_nobang = /* (IA without !). */
19228 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19229 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19230 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19231 bfd_boolean is_db_bang = /* (DB with !). */
19232 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19233 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19234 /* d = UInt (Vd:D);. */
9239bbd3 19235 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19236 | (((unsigned int)initial_insn << 9) >> 31);
19237
9239bbd3
CM		 19238 /* Compute the number of 8-words chunks needed to split. */
19239 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19240 int chunk;
19241
19242 /* The test coverage has been done assuming the following
19243 hypothesis that exactly one of the previous is_ predicates is
19244 true. */
9239bbd3
CM		 19245 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19246 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19247
9239bbd3 19248 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19249 cases, then we emit the adjustments:
19250
19251 vldm rx, {...}
19252 -> vldm rx!, {8_words_or_less} for each needed 8_word
19253 -> sub rx, rx, #size (list)
19254
19255 vldm rx!, {...}
19256 -> vldm rx!, {8_words_or_less} for each needed 8_word
19257 This also handles vpop instruction (when rx is sp)
19258
19259 vldmd rx!, {...}
19260 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19261 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19262 {
9239bbd3
CM		 19263 bfd_vma new_insn = 0;
19264
a504d23a
LA		 19265 if (is_ia_nobang || is_ia_bang)
19266 {
9239bbd3
CM		 19267 new_insn = create_instruction_vldmia
19268 (base_reg,
19269 is_dp,
19270 /*wback= . */1,
19271 chunks - (chunk + 1) ?
19272 8 : num_words - chunk * 8,
19273 first_reg + chunk * 8);
a504d23a
LA		 19274 }
19275 else if (is_db_bang)
19276 {
9239bbd3
CM		 19277 new_insn = create_instruction_vldmdb
19278 (base_reg,
19279 is_dp,
19280 chunks - (chunk + 1) ?
19281 8 : num_words - chunk * 8,
19282 first_reg + chunk * 8);
a504d23a 19283 }
9239bbd3
CM		 19284
19285 if (new_insn)
19286 current_stub_contents =
19287 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19288 new_insn);
a504d23a
LA		 19289 }
19290
19291 /* Only this case requires the base register compensation
19292 subtract. */
19293 if (is_ia_nobang)
19294 {
19295 current_stub_contents =
19296 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19297 create_instruction_sub
9239bbd3 19298 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19299 }
19300
19301 /* B initial_insn_addr+4. */
19302 current_stub_contents =
19303 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19304 create_instruction_branch_absolute
82188b29 19305 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19306 }
19307
19308 /* Fill the remaining of the stub with deterministic contents. */
19309 current_stub_contents =
19310 stm32l4xx_fill_stub_udf (htab, output_bfd,
19311 base_stub_contents, current_stub_contents,
19312 base_stub_contents +
19313 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19314}
19315
19316static void
19317stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19318 bfd * output_bfd,
19319 const insn32 wrong_insn,
19320 const bfd_byte *const wrong_insn_addr,
19321 bfd_byte *const stub_contents)
19322{
19323 if (is_thumb2_ldmia (wrong_insn))
19324 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19325 wrong_insn, wrong_insn_addr,
19326 stub_contents);
19327 else if (is_thumb2_ldmdb (wrong_insn))
19328 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19329 wrong_insn, wrong_insn_addr,
19330 stub_contents);
19331 else if (is_thumb2_vldm (wrong_insn))
19332 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19333 wrong_insn, wrong_insn_addr,
19334 stub_contents);
19335}
19336
19337/* End of stm32l4xx work-around. */
19338
19339
e489d0ae
PB		 19340/* Do code byteswapping. Return FALSE afterwards so that the section is
19341 written out as normal. */
19342
19343static bfd_boolean
c7b8f16e 19344elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19345 struct bfd_link_info *link_info,
19346 asection *sec,
e489d0ae
PB		 19347 bfd_byte *contents)
19348{
48229727 19349 unsigned int mapcount, errcount;
8e3de13a 19350 _arm_elf_section_data *arm_data;
c7b8f16e 19351 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19352 elf32_arm_section_map *map;
c7b8f16e 19353 elf32_vfp11_erratum_list *errnode;
a504d23a 19354 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19355 bfd_vma ptr;
19356 bfd_vma end;
c7b8f16e 19357 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19358 bfd_byte tmp;
48229727 19359 unsigned int i;
57e8b36a 19360
4dfe6ac6
NC		 19361 if (globals == NULL)
19362 return FALSE;
19363
8e3de13a
NC		 19364 /* If this section has not been allocated an _arm_elf_section_data
19365 structure then we cannot record anything. */
19366 arm_data = get_arm_elf_section_data (sec);
19367 if (arm_data == NULL)
19368 return FALSE;
19369
19370 mapcount = arm_data->mapcount;
19371 map = arm_data->map;
c7b8f16e
JB		 19372 errcount = arm_data->erratumcount;
19373
19374 if (errcount != 0)
19375 {
19376 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19377
19378 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19379 errnode = errnode->next)
19380 {
19381 bfd_vma target = errnode->vma - offset;
19382
19383 switch (errnode->type)
19384 {
19385 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19386 {
19387 bfd_vma branch_to_veneer;
19388 /* Original condition code of instruction, plus bit mask for
19389 ARM B instruction. */
19390 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19391 | 0x0a000000;
c7b8f16e
JB		 19392
19393 /* The instruction is before the label. */
91d6fa6a 19394 target -= 4;
c7b8f16e
JB		 19395
19396 /* Above offset included in -4 below. */
19397 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19398 - errnode->vma - 4;
c7b8f16e
JB		 19399
19400 if ((signed) branch_to_veneer < -(1 << 25)
19401 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19402 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19403 "range"), output_bfd);
c7b8f16e 19404
99059e56
RM		 19405 insn |= (branch_to_veneer >> 2) & 0xffffff;
19406 contents[endianflip ^ target] = insn & 0xff;
19407 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19408 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19409 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19410 }
19411 break;
c7b8f16e
JB		 19412
19413 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19414 {
19415 bfd_vma branch_from_veneer;
19416 unsigned int insn;
c7b8f16e 19417
99059e56
RM		 19418 /* Take size of veneer into account. */
19419 branch_from_veneer = errnode->u.v.branch->vma
19420 - errnode->vma - 12;
c7b8f16e
JB		 19421
19422 if ((signed) branch_from_veneer < -(1 << 25)
19423 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19424 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19425 "range"), output_bfd);
c7b8f16e 19426
99059e56
RM		 19427 /* Original instruction. */
19428 insn = errnode->u.v.branch->u.b.vfp_insn;
19429 contents[endianflip ^ target] = insn & 0xff;
19430 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19431 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19432 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19433
19434 /* Branch back to insn after original insn. */
19435 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19436 contents[endianflip ^ (target + 4)] = insn & 0xff;
19437 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19438 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19439 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19440 }
19441 break;
c7b8f16e 19442
99059e56
RM		 19443 default:
19444 abort ();
19445 }
19446 }
c7b8f16e 19447 }
e489d0ae 19448
a504d23a
LA		 19449 if (arm_data->stm32l4xx_erratumcount != 0)
19450 {
19451 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19452 stm32l4xx_errnode != 0;
19453 stm32l4xx_errnode = stm32l4xx_errnode->next)
19454 {
19455 bfd_vma target = stm32l4xx_errnode->vma - offset;
19456
19457 switch (stm32l4xx_errnode->type)
19458 {
19459 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19460 {
19461 unsigned int insn;
19462 bfd_vma branch_to_veneer =
19463 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19464
19465 if ((signed) branch_to_veneer < -(1 << 24)
19466 || (signed) branch_to_veneer >= (1 << 24))
19467 {
19468 bfd_vma out_of_range =
19469 ((signed) branch_to_veneer < -(1 << 24)) ?
19470 - branch_to_veneer - (1 << 24) :
19471 ((signed) branch_to_veneer >= (1 << 24)) ?
19472 branch_to_veneer - (1 << 24) : 0;
19473
4eca0228 19474 _bfd_error_handler
2dcf00ce 19475 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19476 "cannot create STM32L4XX veneer; "
19477 "jump out of range by %" PRId64 " bytes; "
19478 "cannot encode branch instruction"),
a504d23a 19479 output_bfd,
2dcf00ce
AM		 19480 (uint64_t) (stm32l4xx_errnode->vma - 4),
19481 (int64_t) out_of_range);
a504d23a
LA		 19482 continue;
19483 }
19484
19485 insn = create_instruction_branch_absolute
82188b29 19486 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 19487
19488 /* The instruction is before the label. */
19489 target -= 4;
19490
19491 put_thumb2_insn (globals, output_bfd,
19492 (bfd_vma) insn, contents + target);
19493 }
19494 break;
19495
19496 case STM32L4XX_ERRATUM_VENEER:
19497 {
82188b29
NC		 19498 bfd_byte * veneer;
19499 bfd_byte * veneer_r;
a504d23a
LA		 19500 unsigned int insn;
19501
82188b29
NC		 19502 veneer = contents + target;
19503 veneer_r = veneer
19504 + stm32l4xx_errnode->u.b.veneer->vma
19505 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19506
19507 if ((signed) (veneer_r - veneer -
19508 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19509 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19510 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19511 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19512 || (signed) (veneer_r - veneer) >= (1 << 24))
19513 {
90b6238f
AM		 19514 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19515 "veneer"), output_bfd);
a504d23a
LA		 19516 continue;
19517 }
19518
19519 /* Original instruction. */
19520 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19521
19522 stm32l4xx_create_replacing_stub
19523 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19524 }
19525 break;
19526
19527 default:
19528 abort ();
19529 }
19530 }
19531 }
19532
2468f9c9
PB		 19533 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19534 {
19535 arm_unwind_table_edit *edit_node
99059e56 19536 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19537 /* Now, sec->size is the size of the section we will write. The original
99059e56 19538 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19539 markers) was sec->rawsize. (This isn't the case if we perform no
19540 edits, then rawsize will be zero and we should use size). */
21d799b5 19541 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19542 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19543 unsigned int in_index, out_index;
19544 bfd_vma add_to_offsets = 0;
19545
19546 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19547 {
2468f9c9
PB		 19548 if (edit_node)
19549 {
19550 unsigned int edit_index = edit_node->index;
b38cadfb 19551
2468f9c9 19552 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19553 {
2468f9c9
PB		 19554 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19555 contents + in_index * 8, add_to_offsets);
19556 out_index++;
19557 in_index++;
19558 }
19559 else if (in_index == edit_index
19560 || (in_index * 8 >= input_size
19561 && edit_index == UINT_MAX))
99059e56 19562 {
2468f9c9
PB		 19563 switch (edit_node->type)
19564 {
19565 case DELETE_EXIDX_ENTRY:
19566 in_index++;
19567 add_to_offsets += 8;
19568 break;
b38cadfb 19569
2468f9c9
PB		 19570 case INSERT_EXIDX_CANTUNWIND_AT_END:
19571 {
99059e56 19572 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19573 bfd_vma text_offset = text_sec->output_section->vma
19574 + text_sec->output_offset
19575 + text_sec->size;
19576 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19577 unsigned long prel31_offset;
2468f9c9
PB		 19578
19579 /* Note: this is meant to be equivalent to an
19580 R_ARM_PREL31 relocation. These synthetic
19581 EXIDX_CANTUNWIND markers are not relocated by the
19582 usual BFD method. */
19583 prel31_offset = (text_offset - exidx_offset)
19584 & 0x7ffffffful;
491d01d3
YU		 19585 if (bfd_link_relocatable (link_info))
19586 {
19587 /* Here relocation for new EXIDX_CANTUNWIND is
19588 created, so there is no need to
19589 adjust offset by hand. */
19590 prel31_offset = text_sec->output_offset
19591 + text_sec->size;
491d01d3 19592 }
2468f9c9
PB		 19593
19594 /* First address we can't unwind. */
19595 bfd_put_32 (output_bfd, prel31_offset,
19596 &edited_contents[out_index * 8]);
19597
19598 /* Code for EXIDX_CANTUNWIND. */
19599 bfd_put_32 (output_bfd, 0x1,
19600 &edited_contents[out_index * 8 + 4]);
19601
19602 out_index++;
19603 add_to_offsets -= 8;
19604 }
19605 break;
19606 }
b38cadfb 19607
2468f9c9
PB		 19608 edit_node = edit_node->next;
19609 }
19610 }
19611 else
19612 {
19613 /* No more edits, copy remaining entries verbatim. */
19614 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19615 contents + in_index * 8, add_to_offsets);
19616 out_index++;
19617 in_index++;
19618 }
19619 }
19620
19621 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19622 bfd_set_section_contents (output_bfd, sec->output_section,
19623 edited_contents,
19624 (file_ptr) sec->output_offset, sec->size);
19625
19626 return TRUE;
19627 }
19628
48229727
JB		 19629 /* Fix code to point to Cortex-A8 erratum stubs. */
19630 if (globals->fix_cortex_a8)
19631 {
19632 struct a8_branch_to_stub_data data;
19633
19634 data.writing_section = sec;
19635 data.contents = contents;
19636
a504d23a
LA		 19637 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19638 & data);
48229727
JB		 19639 }
19640
e489d0ae
PB		 19641 if (mapcount == 0)
19642 return FALSE;
19643
c7b8f16e 19644 if (globals->byteswap_code)
e489d0ae 19645 {
c7b8f16e 19646 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19647
c7b8f16e
JB		 19648 ptr = map[0].vma;
19649 for (i = 0; i < mapcount; i++)
99059e56
RM		 19650 {
19651 if (i == mapcount - 1)
c7b8f16e 19652 end = sec->size;
99059e56
RM		 19653 else
19654 end = map[i + 1].vma;
e489d0ae 19655
99059e56 19656 switch (map[i].type)
e489d0ae 19657 {
c7b8f16e
JB		 19658 case 'a':
19659 /* Byte swap code words. */
19660 while (ptr + 3 < end)
99059e56
RM		 19661 {
19662 tmp = contents[ptr];
19663 contents[ptr] = contents[ptr + 3];
19664 contents[ptr + 3] = tmp;
19665 tmp = contents[ptr + 1];
19666 contents[ptr + 1] = contents[ptr + 2];
19667 contents[ptr + 2] = tmp;
19668 ptr += 4;
19669 }
c7b8f16e 19670 break;
e489d0ae 19671
c7b8f16e
JB		 19672 case 't':
19673 /* Byte swap code halfwords. */
19674 while (ptr + 1 < end)
99059e56
RM		 19675 {
19676 tmp = contents[ptr];
19677 contents[ptr] = contents[ptr + 1];
19678 contents[ptr + 1] = tmp;
19679 ptr += 2;
19680 }
c7b8f16e
JB		 19681 break;
19682
19683 case 'd':
19684 /* Leave data alone. */
19685 break;
19686 }
99059e56
RM		 19687 ptr = end;
19688 }
e489d0ae 19689 }
8e3de13a 19690
93204d3a 19691 free (map);
47b2e99c 19692 arm_data->mapcount = -1;
c7b8f16e 19693 arm_data->mapsize = 0;
8e3de13a 19694 arm_data->map = NULL;
8e3de13a 19695
e489d0ae
PB		 19696 return FALSE;
19697}
19698
0beaef2b
PB		 19699/* Mangle thumb function symbols as we read them in. */
19700
8384fb8f 19701static bfd_boolean
0beaef2b
PB		 19702elf32_arm_swap_symbol_in (bfd * abfd,
19703 const void *psrc,
19704 const void *pshn,
19705 Elf_Internal_Sym *dst)
19706{
4ba2ef8f
TP		 19707 Elf_Internal_Shdr *symtab_hdr;
19708 const char *name = NULL;
19709
8384fb8f
AM		 19710 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19711 return FALSE;
39d911fc 19712 dst->st_target_internal = 0;
0beaef2b
PB		 19713
19714 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19715 the address. */
63e1a0fc
PB		 19716 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19717 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19718 {
63e1a0fc
PB		 19719 if (dst->st_value & 1)
19720 {
19721 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19722 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19723 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19724 }
19725 else
39d911fc 19726 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19727 }
19728 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19729 {
19730 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19731 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19732 }
35fc36a8 19733 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19734 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19735 else
39d911fc 19736 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19737
4ba2ef8f
TP		 19738 /* Mark CMSE special symbols. */
19739 symtab_hdr = & elf_symtab_hdr (abfd);
19740 if (symtab_hdr->sh_size)
19741 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
19742 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
19743 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
19744
8384fb8f 19745 return TRUE;
0beaef2b
PB		 19746}
19747
19748
19749/* Mangle thumb function symbols as we write them out. */
19750
19751static void
19752elf32_arm_swap_symbol_out (bfd *abfd,
19753 const Elf_Internal_Sym *src,
19754 void *cdst,
19755 void *shndx)
19756{
19757 Elf_Internal_Sym newsym;
19758
19759 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19760 of the address set, as per the new EABI. We do this unconditionally
19761 because objcopy does not set the elf header flags until after
19762 it writes out the symbol table. */
39d911fc 19763 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19764 {
19765 newsym = *src;
34e77a92
RS		 19766 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19767 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19768 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19769 {
19770 /* Do this only for defined symbols. At link type, the static
19771 linker will simulate the work of dynamic linker of resolving
19772 symbols and will carry over the thumbness of found symbols to
19773 the output symbol table. It's not clear how it happens, but
19774 the thumbness of undefined symbols can well be different at
19775 runtime, and writing '1' for them will be confusing for users
19776 and possibly for dynamic linker itself.
19777 */
19778 newsym.st_value |= 1;
19779 }
906e58ca 19780
0beaef2b
PB		 19781 src = &newsym;
19782 }
19783 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19784}
19785
b294bdf8
MM		 19786/* Add the PT_ARM_EXIDX program header. */
19787
19788static bfd_boolean
906e58ca 19789elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19790 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19791{
19792 struct elf_segment_map *m;
19793 asection *sec;
19794
19795 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19796 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19797 {
19798 /* If there is already a PT_ARM_EXIDX header, then we do not
19799 want to add another one. This situation arises when running
19800 "strip"; the input binary already has the header. */
12bd6957 19801 m = elf_seg_map (abfd);
b294bdf8
MM		 19802 while (m && m->p_type != PT_ARM_EXIDX)
19803 m = m->next;
19804 if (!m)
19805 {
21d799b5 19806 m = (struct elf_segment_map *)
99059e56 19807 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19808 if (m == NULL)
19809 return FALSE;
19810 m->p_type = PT_ARM_EXIDX;
19811 m->count = 1;
19812 m->sections[0] = sec;
19813
12bd6957
AM		 19814 m->next = elf_seg_map (abfd);
19815 elf_seg_map (abfd) = m;
b294bdf8
MM		 19816 }
19817 }
19818
19819 return TRUE;
19820}
19821
19822/* We may add a PT_ARM_EXIDX program header. */
19823
19824static int
a6b96beb
AM		 19825elf32_arm_additional_program_headers (bfd *abfd,
19826 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19827{
19828 asection *sec;
19829
19830 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19831 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19832 return 1;
19833 else
19834 return 0;
19835}
19836
34e77a92
RS		 19837/* Hook called by the linker routine which adds symbols from an object
19838 file. */
19839
19840static bfd_boolean
19841elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19842 Elf_Internal_Sym *sym, const char **namep,
19843 flagword *flagsp, asection **secp, bfd_vma *valp)
19844{
c792917c
NC		 19845 if (elf32_arm_hash_table (info) == NULL)
19846 return FALSE;
19847
34e77a92
RS		 19848 if (elf32_arm_hash_table (info)->vxworks_p
19849 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19850 flagsp, secp, valp))
19851 return FALSE;
19852
19853 return TRUE;
19854}
19855
0beaef2b 19856/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 19857const struct elf_size_info elf32_arm_size_info =
19858{
0beaef2b
PB		 19859 sizeof (Elf32_External_Ehdr),
19860 sizeof (Elf32_External_Phdr),
19861 sizeof (Elf32_External_Shdr),
19862 sizeof (Elf32_External_Rel),
19863 sizeof (Elf32_External_Rela),
19864 sizeof (Elf32_External_Sym),
19865 sizeof (Elf32_External_Dyn),
19866 sizeof (Elf_External_Note),
19867 4,
19868 1,
19869 32, 2,
19870 ELFCLASS32, EV_CURRENT,
19871 bfd_elf32_write_out_phdrs,
19872 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 19873 bfd_elf32_checksum_contents,
0beaef2b
PB		 19874 bfd_elf32_write_relocs,
19875 elf32_arm_swap_symbol_in,
19876 elf32_arm_swap_symbol_out,
19877 bfd_elf32_slurp_reloc_table,
19878 bfd_elf32_slurp_symbol_table,
19879 bfd_elf32_swap_dyn_in,
19880 bfd_elf32_swap_dyn_out,
19881 bfd_elf32_swap_reloc_in,
19882 bfd_elf32_swap_reloc_out,
19883 bfd_elf32_swap_reloca_in,
19884 bfd_elf32_swap_reloca_out
19885};
19886
685e70ae
VK		 19887static bfd_vma
19888read_code32 (const bfd *abfd, const bfd_byte *addr)
19889{
19890 /* V7 BE8 code is always little endian. */
19891 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19892 return bfd_getl32 (addr);
19893
19894 return bfd_get_32 (abfd, addr);
19895}
19896
19897static bfd_vma
19898read_code16 (const bfd *abfd, const bfd_byte *addr)
19899{
19900 /* V7 BE8 code is always little endian. */
19901 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19902 return bfd_getl16 (addr);
19903
19904 return bfd_get_16 (abfd, addr);
19905}
19906
6a631e86
YG		 19907/* Return size of plt0 entry starting at ADDR
19908 or (bfd_vma) -1 if size can not be determined. */
19909
19910static bfd_vma
19911elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19912{
19913 bfd_vma first_word;
19914 bfd_vma plt0_size;
19915
685e70ae 19916 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19917
19918 if (first_word == elf32_arm_plt0_entry[0])
19919 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19920 else if (first_word == elf32_thumb2_plt0_entry[0])
19921 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19922 else
19923 /* We don't yet handle this PLT format. */
19924 return (bfd_vma) -1;
19925
19926 return plt0_size;
19927}
19928
19929/* Return size of plt entry starting at offset OFFSET
19930 of plt section located at address START
19931 or (bfd_vma) -1 if size can not be determined. */
19932
19933static bfd_vma
19934elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19935{
19936 bfd_vma first_insn;
19937 bfd_vma plt_size = 0;
19938 const bfd_byte *addr = start + offset;
19939
19940 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19941 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19942 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19943
19944 /* Respect Thumb stub if necessary. */
685e70ae 19945 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19946 {
19947 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19948 }
19949
19950 /* Strip immediate from first add. */
685e70ae 19951 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19952
19953#ifdef FOUR_WORD_PLT
19954 if (first_insn == elf32_arm_plt_entry[0])
19955 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19956#else
19957 if (first_insn == elf32_arm_plt_entry_long[0])
19958 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19959 else if (first_insn == elf32_arm_plt_entry_short[0])
19960 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19961#endif
19962 else
19963 /* We don't yet handle this PLT format. */
19964 return (bfd_vma) -1;
19965
19966 return plt_size;
19967}
19968
19969/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19970
19971static long
19972elf32_arm_get_synthetic_symtab (bfd *abfd,
19973 long symcount ATTRIBUTE_UNUSED,
19974 asymbol **syms ATTRIBUTE_UNUSED,
19975 long dynsymcount,
19976 asymbol **dynsyms,
19977 asymbol **ret)
19978{
19979 asection *relplt;
19980 asymbol *s;
19981 arelent *p;
19982 long count, i, n;
19983 size_t size;
19984 Elf_Internal_Shdr *hdr;
19985 char *names;
19986 asection *plt;
19987 bfd_vma offset;
19988 bfd_byte *data;
19989
19990 *ret = NULL;
19991
19992 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19993 return 0;
19994
19995 if (dynsymcount <= 0)
19996 return 0;
19997
19998 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19999 if (relplt == NULL)
20000 return 0;
20001
20002 hdr = &elf_section_data (relplt)->this_hdr;
20003 if (hdr->sh_link != elf_dynsymtab (abfd)
20004 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20005 return 0;
20006
20007 plt = bfd_get_section_by_name (abfd, ".plt");
20008 if (plt == NULL)
20009 return 0;
20010
20011 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20012 return -1;
20013
20014 data = plt->contents;
20015 if (data == NULL)
20016 {
20017 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20018 return -1;
20019 bfd_cache_section_contents((asection *) plt, data);
20020 }
20021
20022 count = relplt->size / hdr->sh_entsize;
20023 size = count * sizeof (asymbol);
20024 p = relplt->relocation;
20025 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20026 {
20027 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20028 if (p->addend != 0)
20029 size += sizeof ("+0x") - 1 + 8;
20030 }
20031
20032 s = *ret = (asymbol *) bfd_malloc (size);
20033 if (s == NULL)
20034 return -1;
20035
20036 offset = elf32_arm_plt0_size (abfd, data);
20037 if (offset == (bfd_vma) -1)
20038 return -1;
20039
20040 names = (char *) (s + count);
20041 p = relplt->relocation;
20042 n = 0;
20043 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20044 {
20045 size_t len;
20046
20047 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20048 if (plt_size == (bfd_vma) -1)
20049 break;
20050
20051 *s = **p->sym_ptr_ptr;
20052 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20053 we are defining a symbol, ensure one of them is set. */
20054 if ((s->flags & BSF_LOCAL) == 0)
20055 s->flags |= BSF_GLOBAL;
20056 s->flags |= BSF_SYNTHETIC;
20057 s->section = plt;
20058 s->value = offset;
20059 s->name = names;
20060 s->udata.p = NULL;
20061 len = strlen ((*p->sym_ptr_ptr)->name);
20062 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20063 names += len;
20064 if (p->addend != 0)
20065 {
20066 char buf[30], *a;
20067
20068 memcpy (names, "+0x", sizeof ("+0x") - 1);
20069 names += sizeof ("+0x") - 1;
20070 bfd_sprintf_vma (abfd, buf, p->addend);
20071 for (a = buf; *a == '0'; ++a)
20072 ;
20073 len = strlen (a);
20074 memcpy (names, a, len);
20075 names += len;
20076 }
20077 memcpy (names, "@plt", sizeof ("@plt"));
20078 names += sizeof ("@plt");
20079 ++s, ++n;
20080 offset += plt_size;
20081 }
20082
20083 return n;
20084}
20085
ac4c9b04
MG		 20086static bfd_boolean
20087elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20088{
f0728ee3
AV		 20089 if (hdr->sh_flags & SHF_ARM_PURECODE)
20090 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20091 return TRUE;
20092}
20093
20094static flagword
20095elf32_arm_lookup_section_flags (char *flag_name)
20096{
f0728ee3
AV		 20097 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20098 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20099
20100 return SEC_NO_FLAGS;
20101}
20102
491d01d3
YU		 20103static unsigned int
20104elf32_arm_count_additional_relocs (asection *sec)
20105{
20106 struct _arm_elf_section_data *arm_data;
20107 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20108
6342be70 20109 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20110}
20111
5522f910 20112/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20113 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20114 FALSE otherwise. ISECTION is the best guess matching section from the
20115 input bfd IBFD, but it might be NULL. */
20116
20117static bfd_boolean
20118elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20119 bfd *obfd ATTRIBUTE_UNUSED,
20120 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20121 Elf_Internal_Shdr *osection)
20122{
20123 switch (osection->sh_type)
20124 {
20125 case SHT_ARM_EXIDX:
20126 {
20127 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20128 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20129 unsigned i = 0;
20130
20131 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20132 osection->sh_info = 0;
20133
20134 /* The sh_link field must be set to the text section associated with
20135 this index section. Unfortunately the ARM EHABI does not specify
20136 exactly how to determine this association. Our caller does try
20137 to match up OSECTION with its corresponding input section however
20138 so that is a good first guess. */
20139 if (isection != NULL
20140 && osection->bfd_section != NULL
20141 && isection->bfd_section != NULL
20142 && isection->bfd_section->output_section != NULL
20143 && isection->bfd_section->output_section == osection->bfd_section
20144 && iheaders != NULL
20145 && isection->sh_link > 0
20146 && isection->sh_link < elf_numsections (ibfd)
20147 && iheaders[isection->sh_link]->bfd_section != NULL
20148 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20149 )
20150 {
20151 for (i = elf_numsections (obfd); i-- > 0;)
20152 if (oheaders[i]->bfd_section
20153 == iheaders[isection->sh_link]->bfd_section->output_section)
20154 break;
20155 }
9eaff861 20156
5522f910
NC		 20157 if (i == 0)
20158 {
20159 /* Failing that we have to find a matching section ourselves. If
20160 we had the output section name available we could compare that
20161 with input section names. Unfortunately we don't. So instead
20162 we use a simple heuristic and look for the nearest executable
20163 section before this one. */
20164 for (i = elf_numsections (obfd); i-- > 0;)
20165 if (oheaders[i] == osection)
20166 break;
20167 if (i == 0)
20168 break;
20169
20170 while (i-- > 0)
20171 if (oheaders[i]->sh_type == SHT_PROGBITS
20172 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20173 == (SHF_ALLOC | SHF_EXECINSTR))
20174 break;
20175 }
20176
20177 if (i)
20178 {
20179 osection->sh_link = i;
20180 /* If the text section was part of a group
20181 then the index section should be too. */
20182 if (oheaders[i]->sh_flags & SHF_GROUP)
20183 osection->sh_flags |= SHF_GROUP;
20184 return TRUE;
20185 }
20186 }
20187 break;
20188
20189 case SHT_ARM_PREEMPTMAP:
20190 osection->sh_flags = SHF_ALLOC;
20191 break;
20192
20193 case SHT_ARM_ATTRIBUTES:
20194 case SHT_ARM_DEBUGOVERLAY:
20195 case SHT_ARM_OVERLAYSECTION:
20196 default:
20197 break;
20198 }
20199
20200 return FALSE;
20201}
20202
d691934d
NC		 20203/* Returns TRUE if NAME is an ARM mapping symbol.
20204 Traditionally the symbols $a, $d and $t have been used.
20205 The ARM ELF standard also defines $x (for A64 code). It also allows a
20206 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20207 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20208 not support them here. $t.x indicates the start of ThumbEE instructions. */
20209
20210static bfd_boolean
20211is_arm_mapping_symbol (const char * name)
20212{
20213 return name != NULL /* Paranoia. */
20214 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20215 the mapping symbols could have acquired a prefix.
20216 We do not support this here, since such symbols no
20217 longer conform to the ARM ELF ABI. */
20218 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20219 && (name[2] == 0 || name[2] == '.');
20220 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20221 any characters that follow the period are legal characters for the body
20222 of a symbol's name. For now we just assume that this is the case. */
20223}
20224
fca2a38f
NC		 20225/* Make sure that mapping symbols in object files are not removed via the
20226 "strip --strip-unneeded" tool. These symbols are needed in order to
20227 correctly generate interworking veneers, and for byte swapping code
20228 regions. Once an object file has been linked, it is safe to remove the
20229 symbols as they will no longer be needed. */
20230
20231static void
20232elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20233{
20234 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20235 && sym->section != bfd_abs_section_ptr
d691934d 20236 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20237 sym->flags |= BSF_KEEP;
20238}
20239
5522f910
NC		 20240#undef elf_backend_copy_special_section_fields
20241#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20242
252b5132 20243#define ELF_ARCH bfd_arch_arm
ae95ffa6 20244#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20245#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20246#ifdef __QNXTARGET__
20247#define ELF_MAXPAGESIZE 0x1000
20248#else
7572ca89 20249#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20250#endif
b1342370 20251#define ELF_MINPAGESIZE 0x1000
24718e3b 20252#define ELF_COMMONPAGESIZE 0x1000
252b5132 20253
07d6d2b8 20254#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20255
99e4ae17
AJ		 20256#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20257#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20258#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20259#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20260#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20261#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20262#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20263#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20264#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20265#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20266#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20267#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20268#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20269
07d6d2b8
AM		 20270#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20271#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20272#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20273#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20274#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20275#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20276#define elf_backend_write_section elf32_arm_write_section
252b5132 20277#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20278#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20279#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20280#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20281#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20282#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20283#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20284#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20285#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20286#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20287#define elf_backend_fake_sections elf32_arm_fake_sections
20288#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20289#define elf_backend_final_write_processing elf32_arm_final_write_processing
20290#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20291#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20292#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20293#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20294#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20295#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20296#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20297#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20298#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20299#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20300
20301#define elf_backend_can_refcount 1
20302#define elf_backend_can_gc_sections 1
20303#define elf_backend_plt_readonly 1
20304#define elf_backend_want_got_plt 1
20305#define elf_backend_want_plt_sym 0
5474d94f 20306#define elf_backend_want_dynrelro 1
906e58ca
NC		 20307#define elf_backend_may_use_rel_p 1
20308#define elf_backend_may_use_rela_p 0
4e7fd91e 20309#define elf_backend_default_use_rela_p 0
64f52338 20310#define elf_backend_dtrel_excludes_plt 1
252b5132 20311
04f7c78d 20312#define elf_backend_got_header_size 12
b68a20d6 20313#define elf_backend_extern_protected_data 1
04f7c78d 20314
07d6d2b8 20315#undef elf_backend_obj_attrs_vendor
906e58ca 20316#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20317#undef elf_backend_obj_attrs_section
906e58ca 20318#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20319#undef elf_backend_obj_attrs_arg_type
906e58ca 20320#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20321#undef elf_backend_obj_attrs_section_type
104d59d1 20322#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20323#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20324#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20325
07d6d2b8 20326#undef elf_backend_section_flags
ac4c9b04 20327#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20328#undef elf_backend_lookup_section_flags_hook
20329#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20330
a2f63b2e
MR		 20331#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20332
252b5132 20333#include "elf32-target.h"
7f266840 20334
b38cadfb
NC		 20335/* Native Client targets. */
20336
20337#undef TARGET_LITTLE_SYM
6d00b590 20338#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20339#undef TARGET_LITTLE_NAME
20340#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20341#undef TARGET_BIG_SYM
6d00b590 20342#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20343#undef TARGET_BIG_NAME
20344#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20345
20346/* Like elf32_arm_link_hash_table_create -- but overrides
20347 appropriately for NaCl. */
20348
20349static struct bfd_link_hash_table *
20350elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20351{
20352 struct bfd_link_hash_table *ret;
20353
20354 ret = elf32_arm_link_hash_table_create (abfd);
20355 if (ret)
20356 {
20357 struct elf32_arm_link_hash_table *htab
20358 = (struct elf32_arm_link_hash_table *) ret;
20359
20360 htab->nacl_p = 1;
20361
20362 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20363 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20364 }
20365 return ret;
20366}
20367
20368/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20369 really need to use elf32_arm_modify_segment_map. But we do it
20370 anyway just to reduce gratuitous differences with the stock ARM backend. */
20371
20372static bfd_boolean
20373elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20374{
20375 return (elf32_arm_modify_segment_map (abfd, info)
20376 && nacl_modify_segment_map (abfd, info));
20377}
20378
887badb3
RM		 20379static void
20380elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
20381{
20382 elf32_arm_final_write_processing (abfd, linker);
20383 nacl_final_write_processing (abfd, linker);
20384}
20385
6a631e86
YG		 20386static bfd_vma
20387elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20388 const arelent *rel ATTRIBUTE_UNUSED)
20389{
20390 return plt->vma
20391 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20392 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20393}
887badb3 20394
b38cadfb 20395#undef elf32_bed
6a631e86 20396#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20397#undef bfd_elf32_bfd_link_hash_table_create
20398#define bfd_elf32_bfd_link_hash_table_create \
20399 elf32_arm_nacl_link_hash_table_create
20400#undef elf_backend_plt_alignment
6a631e86 20401#define elf_backend_plt_alignment 4
b38cadfb
NC		 20402#undef elf_backend_modify_segment_map
20403#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20404#undef elf_backend_modify_program_headers
20405#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20406#undef elf_backend_final_write_processing
20407#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20408#undef bfd_elf32_get_synthetic_symtab
20409#undef elf_backend_plt_sym_val
20410#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20411#undef elf_backend_copy_special_section_fields
b38cadfb 20412
887badb3
RM		 20413#undef ELF_MINPAGESIZE
20414#undef ELF_COMMONPAGESIZE
20415
b38cadfb
NC		 20416
20417#include "elf32-target.h"
20418
20419/* Reset to defaults. */
20420#undef elf_backend_plt_alignment
20421#undef elf_backend_modify_segment_map
20422#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20423#undef elf_backend_modify_program_headers
887badb3
RM		 20424#undef elf_backend_final_write_processing
20425#define elf_backend_final_write_processing elf32_arm_final_write_processing
20426#undef ELF_MINPAGESIZE
20427#define ELF_MINPAGESIZE 0x1000
20428#undef ELF_COMMONPAGESIZE
20429#define ELF_COMMONPAGESIZE 0x1000
20430
b38cadfb 20431
617a5ada
CL		 20432/* FDPIC Targets. */
20433
20434#undef TARGET_LITTLE_SYM
20435#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20436#undef TARGET_LITTLE_NAME
20437#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20438#undef TARGET_BIG_SYM
20439#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20440#undef TARGET_BIG_NAME
20441#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20442#undef elf_match_priority
20443#define elf_match_priority 128
18a20338
CL		 20444#undef ELF_OSABI
20445#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20446
20447/* Like elf32_arm_link_hash_table_create -- but overrides
20448 appropriately for FDPIC. */
20449
20450static struct bfd_link_hash_table *
20451elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20452{
20453 struct bfd_link_hash_table *ret;
20454
20455 ret = elf32_arm_link_hash_table_create (abfd);
20456 if (ret)
20457 {
20458 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20459
20460 htab->fdpic_p = 1;
20461 }
20462 return ret;
20463}
20464
e8b09b87
CL		 20465/* We need dynamic symbols for every section, since segments can
20466 relocate independently. */
20467static bfd_boolean
20468elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20469 struct bfd_link_info *info
20470 ATTRIBUTE_UNUSED,
20471 asection *p ATTRIBUTE_UNUSED)
20472{
20473 switch (elf_section_data (p)->this_hdr.sh_type)
20474 {
20475 case SHT_PROGBITS:
20476 case SHT_NOBITS:
20477 /* If sh_type is yet undecided, assume it could be
20478 SHT_PROGBITS/SHT_NOBITS. */
20479 case SHT_NULL:
20480 return FALSE;
20481
20482 /* There shouldn't be section relative relocations
20483 against any other section. */
20484 default:
20485 return TRUE;
20486 }
20487}
20488
617a5ada
CL		 20489#undef elf32_bed
20490#define elf32_bed elf32_arm_fdpic_bed
20491
20492#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20493#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20494
e8b09b87
CL		 20495#undef elf_backend_omit_section_dynsym
20496#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20497
617a5ada 20498#include "elf32-target.h"
e8b09b87 20499
617a5ada 20500#undef elf_match_priority
18a20338 20501#undef ELF_OSABI
e8b09b87 20502#undef elf_backend_omit_section_dynsym
617a5ada 20503
906e58ca 20504/* VxWorks Targets. */
4e7fd91e 20505
07d6d2b8
AM		 20506#undef TARGET_LITTLE_SYM
20507#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20508#undef TARGET_LITTLE_NAME
20509#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20510#undef TARGET_BIG_SYM
20511#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20512#undef TARGET_BIG_NAME
20513#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20514
20515/* Like elf32_arm_link_hash_table_create -- but overrides
20516 appropriately for VxWorks. */
906e58ca 20517
4e7fd91e
PB		 20518static struct bfd_link_hash_table *
20519elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20520{
20521 struct bfd_link_hash_table *ret;
20522
20523 ret = elf32_arm_link_hash_table_create (abfd);
20524 if (ret)
20525 {
20526 struct elf32_arm_link_hash_table *htab
00a97672 20527 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20528 htab->use_rel = 0;
00a97672 20529 htab->vxworks_p = 1;
4e7fd91e
PB		 20530 }
20531 return ret;
906e58ca 20532}
4e7fd91e 20533
00a97672
RS		 20534static void
20535elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
20536{
20537 elf32_arm_final_write_processing (abfd, linker);
20538 elf_vxworks_final_write_processing (abfd, linker);
20539}
20540
906e58ca 20541#undef elf32_bed
4e7fd91e
PB		 20542#define elf32_bed elf32_arm_vxworks_bed
20543
906e58ca
NC		 20544#undef bfd_elf32_bfd_link_hash_table_create
20545#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20546#undef elf_backend_final_write_processing
20547#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20548#undef elf_backend_emit_relocs
9eaff861 20549#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20550
906e58ca 20551#undef elf_backend_may_use_rel_p
00a97672 20552#define elf_backend_may_use_rel_p 0
906e58ca 20553#undef elf_backend_may_use_rela_p
00a97672 20554#define elf_backend_may_use_rela_p 1
906e58ca 20555#undef elf_backend_default_use_rela_p
00a97672 20556#define elf_backend_default_use_rela_p 1
906e58ca 20557#undef elf_backend_want_plt_sym
00a97672 20558#define elf_backend_want_plt_sym 1
906e58ca 20559#undef ELF_MAXPAGESIZE
00a97672 20560#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20561
20562#include "elf32-target.h"
20563
20564
21d799b5
NC		 20565/* Merge backend specific data from an object file to the output
20566 object file when linking. */
20567
20568static bfd_boolean
50e03d47 20569elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20570{
50e03d47 20571 bfd *obfd = info->output_bfd;
21d799b5
NC		 20572 flagword out_flags;
20573 flagword in_flags;
20574 bfd_boolean flags_compatible = TRUE;
20575 asection *sec;
20576
cc643b88 20577 /* Check if we have the same endianness. */
50e03d47 20578 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20579 return FALSE;
20580
20581 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20582 return TRUE;
20583
50e03d47 20584 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20585 return FALSE;
20586
20587 /* The input BFD must have had its flags initialised. */
20588 /* The following seems bogus to me -- The flags are initialized in
20589 the assembler but I don't think an elf_flags_init field is
20590 written into the object. */
20591 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20592
20593 in_flags = elf_elfheader (ibfd)->e_flags;
20594 out_flags = elf_elfheader (obfd)->e_flags;
20595
20596 /* In theory there is no reason why we couldn't handle this. However
20597 in practice it isn't even close to working and there is no real
20598 reason to want it. */
20599 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20600 && !(ibfd->flags & DYNAMIC)
20601 && (in_flags & EF_ARM_BE8))
20602 {
871b3ab2 20603 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20604 ibfd);
20605 return FALSE;
20606 }
20607
20608 if (!elf_flags_init (obfd))
20609 {
20610 /* If the input is the default architecture and had the default
20611 flags then do not bother setting the flags for the output
20612 architecture, instead allow future merges to do this. If no
20613 future merges ever set these flags then they will retain their
99059e56
RM		 20614 uninitialised values, which surprise surprise, correspond
20615 to the default values. */
21d799b5
NC		 20616 if (bfd_get_arch_info (ibfd)->the_default
20617 && elf_elfheader (ibfd)->e_flags == 0)
20618 return TRUE;
20619
20620 elf_flags_init (obfd) = TRUE;
20621 elf_elfheader (obfd)->e_flags = in_flags;
20622
20623 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20624 && bfd_get_arch_info (obfd)->the_default)
20625 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20626
20627 return TRUE;
20628 }
20629
20630 /* Determine what should happen if the input ARM architecture
20631 does not match the output ARM architecture. */
20632 if (! bfd_arm_merge_machines (ibfd, obfd))
20633 return FALSE;
20634
20635 /* Identical flags must be compatible. */
20636 if (in_flags == out_flags)
20637 return TRUE;
20638
20639 /* Check to see if the input BFD actually contains any sections. If
20640 not, its flags may not have been initialised either, but it
20641 cannot actually cause any incompatiblity. Do not short-circuit
20642 dynamic objects; their section list may be emptied by
20643 elf_link_add_object_symbols.
20644
20645 Also check to see if there are no code sections in the input.
20646 In this case there is no need to check for code specific flags.
20647 XXX - do we need to worry about floating-point format compatability
20648 in data sections ? */
20649 if (!(ibfd->flags & DYNAMIC))
20650 {
20651 bfd_boolean null_input_bfd = TRUE;
20652 bfd_boolean only_data_sections = TRUE;
20653
20654 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20655 {
20656 /* Ignore synthetic glue sections. */
20657 if (strcmp (sec->name, ".glue_7")
20658 && strcmp (sec->name, ".glue_7t"))
20659 {
20660 if ((bfd_get_section_flags (ibfd, sec)
20661 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20662 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20663 only_data_sections = FALSE;
21d799b5
NC		 20664
20665 null_input_bfd = FALSE;
20666 break;
20667 }
20668 }
20669
20670 if (null_input_bfd || only_data_sections)
20671 return TRUE;
20672 }
20673
20674 /* Complain about various flag mismatches. */
20675 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20676 EF_ARM_EABI_VERSION (out_flags)))
20677 {
20678 _bfd_error_handler
90b6238f 20679 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20680 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20681 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20682 return FALSE;
20683 }
20684
20685 /* Not sure what needs to be checked for EABI versions >= 1. */
20686 /* VxWorks libraries do not use these flags. */
20687 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20688 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20689 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20690 {
20691 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20692 {
20693 _bfd_error_handler
871b3ab2 20694 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20695 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20696 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20697 flags_compatible = FALSE;
20698 }
20699
20700 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20701 {
20702 if (in_flags & EF_ARM_APCS_FLOAT)
20703 _bfd_error_handler
871b3ab2 20704 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20705 ibfd, obfd);
20706 else
20707 _bfd_error_handler
871b3ab2 20708 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20709 ibfd, obfd);
20710
20711 flags_compatible = FALSE;
20712 }
20713
20714 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20715 {
20716 if (in_flags & EF_ARM_VFP_FLOAT)
20717 _bfd_error_handler
90b6238f
AM		 20718 (_("error: %pB uses %s instructions, whereas %pB does not"),
20719 ibfd, "VFP", obfd);
21d799b5
NC		 20720 else
20721 _bfd_error_handler
90b6238f
AM		 20722 (_("error: %pB uses %s instructions, whereas %pB does not"),
20723 ibfd, "FPA", obfd);
21d799b5
NC		 20724
20725 flags_compatible = FALSE;
20726 }
20727
20728 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20729 {
20730 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20731 _bfd_error_handler
90b6238f
AM		 20732 (_("error: %pB uses %s instructions, whereas %pB does not"),
20733 ibfd, "Maverick", obfd);
21d799b5
NC		 20734 else
20735 _bfd_error_handler
90b6238f
AM		 20736 (_("error: %pB does not use %s instructions, whereas %pB does"),
20737 ibfd, "Maverick", obfd);
21d799b5
NC		 20738
20739 flags_compatible = FALSE;
20740 }
20741
20742#ifdef EF_ARM_SOFT_FLOAT
20743 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20744 {
20745 /* We can allow interworking between code that is VFP format
20746 layout, and uses either soft float or integer regs for
20747 passing floating point arguments and results. We already
20748 know that the APCS_FLOAT flags match; similarly for VFP
20749 flags. */
20750 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20751 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20752 {
20753 if (in_flags & EF_ARM_SOFT_FLOAT)
20754 _bfd_error_handler
871b3ab2 20755 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20756 ibfd, obfd);
20757 else
20758 _bfd_error_handler
871b3ab2 20759 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20760 ibfd, obfd);
20761
20762 flags_compatible = FALSE;
20763 }
20764 }
20765#endif
20766
20767 /* Interworking mismatch is only a warning. */
20768 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20769 {
20770 if (in_flags & EF_ARM_INTERWORK)
20771 {
20772 _bfd_error_handler
90b6238f 20773 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20774 ibfd, obfd);
20775 }
20776 else
20777 {
20778 _bfd_error_handler
90b6238f 20779 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20780 ibfd, obfd);
20781 }
20782 }
20783 }
20784
20785 return flags_compatible;
20786}
20787
20788
906e58ca 20789/* Symbian OS Targets. */
7f266840 20790
07d6d2b8
AM		 20791#undef TARGET_LITTLE_SYM
20792#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20793#undef TARGET_LITTLE_NAME
20794#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20795#undef TARGET_BIG_SYM
20796#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20797#undef TARGET_BIG_NAME
20798#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20799
20800/* Like elf32_arm_link_hash_table_create -- but overrides
20801 appropriately for Symbian OS. */
906e58ca 20802
7f266840
DJ		 20803static struct bfd_link_hash_table *
20804elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20805{
20806 struct bfd_link_hash_table *ret;
20807
20808 ret = elf32_arm_link_hash_table_create (abfd);
20809 if (ret)
20810 {
20811 struct elf32_arm_link_hash_table *htab
20812 = (struct elf32_arm_link_hash_table *)ret;
20813 /* There is no PLT header for Symbian OS. */
20814 htab->plt_header_size = 0;
95720a86
DJ		 20815 /* The PLT entries are each one instruction and one word. */
20816 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20817 htab->symbian_p = 1;
33bfe774
JB		 20818 /* Symbian uses armv5t or above, so use_blx is always true. */
20819 htab->use_blx = 1;
67687978 20820 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20821 }
20822 return ret;
906e58ca 20823}
7f266840 20824
b35d266b 20825static const struct bfd_elf_special_section
551b43fd 20826elf32_arm_symbian_special_sections[] =
7f266840 20827{
5cd3778d
MM		 20828 /* In a BPABI executable, the dynamic linking sections do not go in
20829 the loadable read-only segment. The post-linker may wish to
20830 refer to these sections, but they are not part of the final
20831 program image. */
07d6d2b8
AM		 20832 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20833 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20834 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20835 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20836 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20837 /* These sections do not need to be writable as the SymbianOS
20838 postlinker will arrange things so that no dynamic relocation is
20839 required. */
07d6d2b8
AM		 20840 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20841 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20842 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20843 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20844};
20845
c3c76620 20846static void
906e58ca 20847elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20848 struct bfd_link_info *link_info)
c3c76620
MM		 20849{
20850 /* BPABI objects are never loaded directly by an OS kernel; they are
20851 processed by a postlinker first, into an OS-specific format. If
20852 the D_PAGED bit is set on the file, BFD will align segments on
20853 page boundaries, so that an OS can directly map the file. With
20854 BPABI objects, that just results in wasted space. In addition,
20855 because we clear the D_PAGED bit, map_sections_to_segments will
20856 recognize that the program headers should not be mapped into any
20857 loadable segment. */
20858 abfd->flags &= ~D_PAGED;
906e58ca 20859 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 20860}
7f266840
DJ		 20861
20862static bfd_boolean
906e58ca 20863elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 20864 struct bfd_link_info *info)
7f266840
DJ		 20865{
20866 struct elf_segment_map *m;
20867 asection *dynsec;
20868
7f266840
DJ		 20869 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20870 segment. However, because the .dynamic section is not marked
20871 with SEC_LOAD, the generic ELF code will not create such a
20872 segment. */
20873 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
20874 if (dynsec)
20875 {
12bd6957 20876 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 20877 if (m->p_type == PT_DYNAMIC)
20878 break;
20879
20880 if (m == NULL)
20881 {
20882 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 20883 m->next = elf_seg_map (abfd);
20884 elf_seg_map (abfd) = m;
8ded5a0f 20885 }
7f266840
DJ		 20886 }
20887
b294bdf8
MM		 20888 /* Also call the generic arm routine. */
20889 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 20890}
20891
95720a86
DJ		 20892/* Return address for Ith PLT stub in section PLT, for relocation REL
20893 or (bfd_vma) -1 if it should not be included. */
20894
20895static bfd_vma
20896elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
20897 const arelent *rel ATTRIBUTE_UNUSED)
20898{
20899 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
20900}
20901
8029a119 20902#undef elf32_bed
7f266840
DJ		 20903#define elf32_bed elf32_arm_symbian_bed
20904
20905/* The dynamic sections are not allocated on SymbianOS; the postlinker
20906 will process them and then discard them. */
906e58ca 20907#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 20908#define ELF_DYNAMIC_SEC_FLAGS \
20909 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20910
9eaff861 20911#undef elf_backend_emit_relocs
c3c76620 20912
906e58ca
NC		 20913#undef bfd_elf32_bfd_link_hash_table_create
20914#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20915#undef elf_backend_special_sections
07d6d2b8 20916#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 20917#undef elf_backend_begin_write_processing
20918#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20919#undef elf_backend_final_write_processing
20920#define elf_backend_final_write_processing elf32_arm_final_write_processing
20921
20922#undef elf_backend_modify_segment_map
7f266840
DJ		 20923#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20924
20925/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 20926#undef elf_backend_got_header_size
7f266840
DJ		 20927#define elf_backend_got_header_size 0
20928
20929/* Similarly, there is no .got.plt section. */
906e58ca 20930#undef elf_backend_want_got_plt
7f266840
DJ		 20931#define elf_backend_want_got_plt 0
20932
906e58ca 20933#undef elf_backend_plt_sym_val
95720a86
DJ		 20934#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20935
906e58ca 20936#undef elf_backend_may_use_rel_p
00a97672 20937#define elf_backend_may_use_rel_p 1
906e58ca 20938#undef elf_backend_may_use_rela_p
00a97672 20939#define elf_backend_may_use_rela_p 0
906e58ca 20940#undef elf_backend_default_use_rela_p
00a97672 20941#define elf_backend_default_use_rela_p 0
906e58ca 20942#undef elf_backend_want_plt_sym
00a97672 20943#define elf_backend_want_plt_sym 0
64f52338
AM		 20944#undef elf_backend_dtrel_excludes_plt
20945#define elf_backend_dtrel_excludes_plt 0
906e58ca 20946#undef ELF_MAXPAGESIZE
00a97672 20947#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 20948
7f266840 20949#include "elf32-target.h"
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