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99c513f6 1/* Renesas RL78 specific support for 32-bit ELF.
fd67aa11 2 Copyright (C) 2011-2024 Free Software Foundation, Inc.
99c513f6
DD		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
863f7a5f
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
99c513f6
DD		 20
21#include "sysdep.h"
22#include "bfd.h"
99c513f6
DD		 23#include "libbfd.h"
24#include "elf-bfd.h"
25#include "elf/rl78.h"
26#include "libiberty.h"
27
28#define valid_16bit_address(v) ((v) <= 0x0ffff || (v) >= 0xf0000)
29
2ad55ffc 30#define RL78REL(n,sz,bit,mask,shift,complain,pcrel) \
99c513f6 31 HOWTO (R_RL78_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \
2ad55ffc 32 bfd_elf_generic_reloc, "R_RL78_" #n, false, 0, mask, false)
99c513f6 33
6ff71e76
NC		 34static bfd_reloc_status_type rl78_special_reloc (bfd *, arelent *, asymbol *, void *,
35 asection *, bfd *, char **);
36
2ad55ffc 37#define RL78_OP_REL(n,sz,bit,mask,shift,complain,pcrel) \
6ff71e76 38 HOWTO (R_RL78_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \
2ad55ffc 39 rl78_special_reloc, "R_RL78_" #n, false, 0, mask, false)
6ff71e76 40
99c513f6
DD		 41/* Note that the relocations around 0x7f are internal to this file;
42 feel free to move them as needed to avoid conflicts with published
43 relocation numbers. */
44
45static reloc_howto_type rl78_elf_howto_table [] =
46{
c94cb026
AM		 47 RL78REL (NONE, 0, 0, 0, 0, dont, false),
48 RL78REL (DIR32, 4, 32, 0xffffffff, 0, dont, false),
49 RL78REL (DIR24S, 4, 24, 0xffffff, 0, signed, false),
50 RL78REL (DIR16, 2, 16, 0xffff, 0, bitfield, false),
51 RL78REL (DIR16U, 2, 16, 0xffff, 0, unsigned, false),
52 RL78REL (DIR16S, 2, 16, 0xffff, 0, bitfield, false),
53 RL78REL (DIR8, 1, 8, 0xff, 0, dont, false),
54 RL78REL (DIR8U, 1, 8, 0xff, 0, unsigned, false),
55 RL78REL (DIR8S, 1, 8, 0xff, 0, bitfield, false),
56 RL78REL (DIR24S_PCREL, 4, 24, 0xffffff, 0, signed, true),
57 RL78REL (DIR16S_PCREL, 2, 16, 0xffff, 0, signed, true),
58 RL78REL (DIR8S_PCREL, 1, 8, 0xff, 0, signed, true),
59 RL78REL (DIR16UL, 2, 16, 0xffff, 2, unsigned, false),
60 RL78REL (DIR16UW, 2, 16, 0xffff, 1, unsigned, false),
61 RL78REL (DIR8UL, 1, 8, 0xff, 2, unsigned, false),
62 RL78REL (DIR8UW, 1, 8, 0xff, 1, unsigned, false),
63 RL78REL (DIR32_REV, 4, 32, 0xffffffff, 0, dont, false),
64 RL78REL (DIR16_REV, 2, 16, 0xffff, 0, bitfield, false),
65 RL78REL (DIR3U_PCREL, 1, 3, 0x7, 0, unsigned, true),
99c513f6
DD		 66
67 EMPTY_HOWTO (0x13),
68 EMPTY_HOWTO (0x14),
69 EMPTY_HOWTO (0x15),
70 EMPTY_HOWTO (0x16),
71 EMPTY_HOWTO (0x17),
72 EMPTY_HOWTO (0x18),
73 EMPTY_HOWTO (0x19),
74 EMPTY_HOWTO (0x1a),
75 EMPTY_HOWTO (0x1b),
76 EMPTY_HOWTO (0x1c),
77 EMPTY_HOWTO (0x1d),
78 EMPTY_HOWTO (0x1e),
79 EMPTY_HOWTO (0x1f),
80
81 EMPTY_HOWTO (0x20),
82 EMPTY_HOWTO (0x21),
83 EMPTY_HOWTO (0x22),
84 EMPTY_HOWTO (0x23),
85 EMPTY_HOWTO (0x24),
86 EMPTY_HOWTO (0x25),
87 EMPTY_HOWTO (0x26),
88 EMPTY_HOWTO (0x27),
89 EMPTY_HOWTO (0x28),
90 EMPTY_HOWTO (0x29),
91 EMPTY_HOWTO (0x2a),
92 EMPTY_HOWTO (0x2b),
93 EMPTY_HOWTO (0x2c),
99c513f6 94
c94cb026
AM		 95 RL78REL (RH_RELAX, 0, 0, 0, 0, dont, false),
96 RL78REL (RH_SFR, 1, 8, 0xff, 0, unsigned, false),
97 RL78REL (RH_SADDR, 1, 8, 0xff, 0, unsigned, false),
2ad55ffc 98
99c513f6
DD		 99 EMPTY_HOWTO (0x30),
100 EMPTY_HOWTO (0x31),
101 EMPTY_HOWTO (0x32),
102 EMPTY_HOWTO (0x33),
103 EMPTY_HOWTO (0x34),
104 EMPTY_HOWTO (0x35),
105 EMPTY_HOWTO (0x36),
106 EMPTY_HOWTO (0x37),
107 EMPTY_HOWTO (0x38),
108 EMPTY_HOWTO (0x39),
109 EMPTY_HOWTO (0x3a),
110 EMPTY_HOWTO (0x3b),
111 EMPTY_HOWTO (0x3c),
112 EMPTY_HOWTO (0x3d),
113 EMPTY_HOWTO (0x3e),
114 EMPTY_HOWTO (0x3f),
115 EMPTY_HOWTO (0x40),
116
c94cb026
AM		 117 RL78_OP_REL (ABS32, 4, 32, 0xffffffff, 0, dont, false),
118 RL78_OP_REL (ABS24S, 4, 24, 0xffffff, 0, signed, false),
119 RL78_OP_REL (ABS16, 2, 16, 0xffff, 0, bitfield, false),
120 RL78_OP_REL (ABS16U, 2, 16, 0xffff, 0, unsigned, false),
121 RL78_OP_REL (ABS16S, 2, 16, 0xffff, 0, signed, false),
122 RL78_OP_REL (ABS8, 1, 8, 0xff, 0, bitfield, false),
123 RL78_OP_REL (ABS8U, 1, 8, 0xff, 0, unsigned, false),
124 RL78_OP_REL (ABS8S, 1, 8, 0xff, 0, signed, false),
125 RL78_OP_REL (ABS24S_PCREL, 4, 24, 0xffffff, 0, signed, true),
126 RL78_OP_REL (ABS16S_PCREL, 2, 16, 0xffff, 0, signed, true),
127 RL78_OP_REL (ABS8S_PCREL, 1, 8, 0xff, 0, signed, true),
128 RL78_OP_REL (ABS16UL, 2, 16, 0xffff, 0, unsigned, false),
129 RL78_OP_REL (ABS16UW, 2, 16, 0xffff, 0, unsigned, false),
130 RL78_OP_REL (ABS8UL, 1, 8, 0xff, 0, unsigned, false),
131 RL78_OP_REL (ABS8UW, 1, 8, 0xff, 0, unsigned, false),
132 RL78_OP_REL (ABS32_REV, 4, 32, 0xffffffff, 0, dont, false),
133 RL78_OP_REL (ABS16_REV, 2, 16, 0xffff, 0, bitfield, false),
99c513f6
DD		 134
135#define STACK_REL_P(x) ((x) <= R_RL78_ABS16_REV && (x) >= R_RL78_ABS32)
136
137 EMPTY_HOWTO (0x52),
138 EMPTY_HOWTO (0x53),
139 EMPTY_HOWTO (0x54),
140 EMPTY_HOWTO (0x55),
141 EMPTY_HOWTO (0x56),
142 EMPTY_HOWTO (0x57),
143 EMPTY_HOWTO (0x58),
144 EMPTY_HOWTO (0x59),
145 EMPTY_HOWTO (0x5a),
146 EMPTY_HOWTO (0x5b),
147 EMPTY_HOWTO (0x5c),
148 EMPTY_HOWTO (0x5d),
149 EMPTY_HOWTO (0x5e),
150 EMPTY_HOWTO (0x5f),
151 EMPTY_HOWTO (0x60),
152 EMPTY_HOWTO (0x61),
153 EMPTY_HOWTO (0x62),
154 EMPTY_HOWTO (0x63),
155 EMPTY_HOWTO (0x64),
156 EMPTY_HOWTO (0x65),
157 EMPTY_HOWTO (0x66),
158 EMPTY_HOWTO (0x67),
159 EMPTY_HOWTO (0x68),
160 EMPTY_HOWTO (0x69),
161 EMPTY_HOWTO (0x6a),
162 EMPTY_HOWTO (0x6b),
163 EMPTY_HOWTO (0x6c),
164 EMPTY_HOWTO (0x6d),
165 EMPTY_HOWTO (0x6e),
166 EMPTY_HOWTO (0x6f),
167 EMPTY_HOWTO (0x70),
168 EMPTY_HOWTO (0x71),
169 EMPTY_HOWTO (0x72),
170 EMPTY_HOWTO (0x73),
171 EMPTY_HOWTO (0x74),
172 EMPTY_HOWTO (0x75),
173 EMPTY_HOWTO (0x76),
174 EMPTY_HOWTO (0x77),
175
176 EMPTY_HOWTO (0x78),
177 EMPTY_HOWTO (0x79),
178 EMPTY_HOWTO (0x7a),
179 EMPTY_HOWTO (0x7b),
180 EMPTY_HOWTO (0x7c),
181 EMPTY_HOWTO (0x7d),
182 EMPTY_HOWTO (0x7e),
183 EMPTY_HOWTO (0x7f),
184
c94cb026
AM		 185 RL78_OP_REL (SYM, 0, 0, 0, 0, dont, false),
186 RL78_OP_REL (OPneg, 0, 0, 0, 0, dont, false),
187 RL78_OP_REL (OPadd, 0, 0, 0, 0, dont, false),
188 RL78_OP_REL (OPsub, 0, 0, 0, 0, dont, false),
189 RL78_OP_REL (OPmul, 0, 0, 0, 0, dont, false),
190 RL78_OP_REL (OPdiv, 0, 0, 0, 0, dont, false),
191 RL78_OP_REL (OPshla, 0, 0, 0, 0, dont, false),
192 RL78_OP_REL (OPshra, 0, 0, 0, 0, dont, false),
193 RL78_OP_REL (OPsctsize, 0, 0, 0, 0, dont, false),
99c513f6
DD		 194 EMPTY_HOWTO (0x89),
195 EMPTY_HOWTO (0x8a),
196 EMPTY_HOWTO (0x8b),
197 EMPTY_HOWTO (0x8c),
c94cb026 198 RL78_OP_REL (OPscttop, 0, 0, 0, 0, dont, false),
99c513f6
DD		 199 EMPTY_HOWTO (0x8e),
200 EMPTY_HOWTO (0x8f),
c94cb026
AM		 201 RL78_OP_REL (OPand, 0, 0, 0, 0, dont, false),
202 RL78_OP_REL (OPor, 0, 0, 0, 0, dont, false),
203 RL78_OP_REL (OPxor, 0, 0, 0, 0, dont, false),
204 RL78_OP_REL (OPnot, 0, 0, 0, 0, dont, false),
205 RL78_OP_REL (OPmod, 0, 0, 0, 0, dont, false),
206 RL78_OP_REL (OPromtop, 0, 0, 0, 0, dont, false),
207 RL78_OP_REL (OPramtop, 0, 0, 0, 0, dont, false)
99c513f6
DD		 208};
209\f
210/* Map BFD reloc types to RL78 ELF reloc types. */
211
212struct rl78_reloc_map
213{
214 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 215 unsigned int rl78_reloc_val;
99c513f6
DD		 216};
217
218static const struct rl78_reloc_map rl78_reloc_map [] =
219{
220 { BFD_RELOC_NONE, R_RL78_NONE },
221 { BFD_RELOC_8, R_RL78_DIR8S },
222 { BFD_RELOC_16, R_RL78_DIR16S },
223 { BFD_RELOC_24, R_RL78_DIR24S },
224 { BFD_RELOC_32, R_RL78_DIR32 },
225 { BFD_RELOC_RL78_16_OP, R_RL78_DIR16 },
226 { BFD_RELOC_RL78_DIR3U_PCREL, R_RL78_DIR3U_PCREL },
227 { BFD_RELOC_8_PCREL, R_RL78_DIR8S_PCREL },
228 { BFD_RELOC_16_PCREL, R_RL78_DIR16S_PCREL },
229 { BFD_RELOC_24_PCREL, R_RL78_DIR24S_PCREL },
230 { BFD_RELOC_RL78_8U, R_RL78_DIR8U },
231 { BFD_RELOC_RL78_16U, R_RL78_DIR16U },
232 { BFD_RELOC_RL78_SYM, R_RL78_SYM },
233 { BFD_RELOC_RL78_OP_SUBTRACT, R_RL78_OPsub },
234 { BFD_RELOC_RL78_OP_NEG, R_RL78_OPneg },
235 { BFD_RELOC_RL78_OP_AND, R_RL78_OPand },
236 { BFD_RELOC_RL78_OP_SHRA, R_RL78_OPshra },
237 { BFD_RELOC_RL78_ABS8, R_RL78_ABS8 },
238 { BFD_RELOC_RL78_ABS16, R_RL78_ABS16 },
239 { BFD_RELOC_RL78_ABS16_REV, R_RL78_ABS16_REV },
240 { BFD_RELOC_RL78_ABS32, R_RL78_ABS32 },
241 { BFD_RELOC_RL78_ABS32_REV, R_RL78_ABS32_REV },
242 { BFD_RELOC_RL78_ABS16UL, R_RL78_ABS16UL },
243 { BFD_RELOC_RL78_ABS16UW, R_RL78_ABS16UW },
9cea966c 244 { BFD_RELOC_RL78_ABS16U, R_RL78_ABS16U },
54f66250 245 { BFD_RELOC_RL78_SADDR, R_RL78_RH_SADDR },
9cea966c 246 { BFD_RELOC_RL78_RELAX, R_RL78_RH_RELAX }
99c513f6
DD		 247};
248
249static reloc_howto_type *
250rl78_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
251 bfd_reloc_code_real_type code)
252{
253 unsigned int i;
254
255 if (code == BFD_RELOC_RL78_32_OP)
256 return rl78_elf_howto_table + R_RL78_DIR32;
257
0ba38529 258 for (i = ARRAY_SIZE (rl78_reloc_map); i--;)
99c513f6
DD		 259 if (rl78_reloc_map [i].bfd_reloc_val == code)
260 return rl78_elf_howto_table + rl78_reloc_map[i].rl78_reloc_val;
261
262 return NULL;
263}
264
265static reloc_howto_type *
266rl78_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, const char * r_name)
267{
268 unsigned int i;
269
270 for (i = 0; i < ARRAY_SIZE (rl78_elf_howto_table); i++)
271 if (rl78_elf_howto_table[i].name != NULL
272 && strcasecmp (rl78_elf_howto_table[i].name, r_name) == 0)
273 return rl78_elf_howto_table + i;
274
275 return NULL;
276}
277
278/* Set the howto pointer for an RL78 ELF reloc. */
279
0a1b45a2 280static bool
f3185997 281rl78_info_to_howto_rela (bfd * abfd,
07d6d2b8 282 arelent * cache_ptr,
99c513f6
DD		 283 Elf_Internal_Rela * dst)
284{
285 unsigned int r_type;
286
287 r_type = ELF32_R_TYPE (dst->r_info);
5860e3f8
NC		 288 if (r_type >= (unsigned int) R_RL78_max)
289 {
695344c0 290 /* xgettext:c-format */
0aa13fee
AM		 291 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
292 abfd, r_type);
f3185997 293 bfd_set_error (bfd_error_bad_value);
0a1b45a2 294 return false;
5860e3f8 295 }
99c513f6 296 cache_ptr->howto = rl78_elf_howto_table + r_type;
0a1b45a2 297 return true;
99c513f6
DD		 298}
299\f
300static bfd_vma
07d6d2b8 301get_symbol_value (const char * name,
99c513f6 302 struct bfd_link_info * info,
07d6d2b8
AM		 303 bfd * input_bfd,
304 asection * input_section,
99c513f6
DD		 305 int offset)
306{
99c513f6
DD		 307 struct bfd_link_hash_entry * h;
308
6ff71e76
NC		 309 if (info == NULL)
310 return 0;
311
0a1b45a2 312 h = bfd_link_hash_lookup (info->hash, name, false, false, true);
99c513f6
DD		 313
314 if (h == NULL
315 || (h->type != bfd_link_hash_defined
316 && h->type != bfd_link_hash_defweak))
6ff71e76 317 {
1a72702b 318 (*info->callbacks->undefined_symbol)
0a1b45a2 319 (info, name, input_bfd, input_section, offset, true);
6ff71e76
NC		 320 return 0;
321 }
99c513f6 322
6ff71e76
NC		 323 return (h->u.def.value
324 + h->u.def.section->output_section->vma
325 + h->u.def.section->output_offset);
99c513f6
DD		 326}
327
328static bfd_vma
1a72702b 329get_romstart (struct bfd_link_info * info,
07d6d2b8
AM		 330 bfd * abfd,
331 asection * sec,
99c513f6
DD		 332 int offset)
333{
0a1b45a2
AM		 334 static bool cached = false;
335 static bfd_vma cached_value = 0;
99c513f6
DD		 336
337 if (!cached)
338 {
1a72702b 339 cached_value = get_symbol_value ("_start", info, abfd, sec, offset);
0a1b45a2 340 cached = true;
99c513f6
DD		 341 }
342 return cached_value;
343}
344
345static bfd_vma
1a72702b 346get_ramstart (struct bfd_link_info * info,
07d6d2b8
AM		 347 bfd * abfd,
348 asection * sec,
99c513f6
DD		 349 int offset)
350{
0a1b45a2
AM		 351 static bool cached = false;
352 static bfd_vma cached_value = 0;
99c513f6
DD		 353
354 if (!cached)
355 {
1a72702b 356 cached_value = get_symbol_value ("__datastart", info, abfd, sec, offset);
0a1b45a2 357 cached = true;
99c513f6
DD		 358 }
359 return cached_value;
360}
361
362#define NUM_STACK_ENTRIES 16
363static int32_t rl78_stack [ NUM_STACK_ENTRIES ];
364static unsigned int rl78_stack_top;
365
983cdaec
AM		 366static inline void
367rl78_stack_push (bfd_vma val, bfd_reloc_status_type *r)
368{
369 if (rl78_stack_top < NUM_STACK_ENTRIES)
370 rl78_stack[rl78_stack_top++] = val;
371 else
372 *r = bfd_reloc_dangerous;
373}
374
375static inline bfd_vma
376rl78_stack_pop (bfd_reloc_status_type *r)
377{
378 if (rl78_stack_top > 0)
379 return rl78_stack[-- rl78_stack_top];
380 else
381 *r = bfd_reloc_dangerous;
382 return 0;
383}
99c513f6 384
6ff71e76
NC		 385/* Special handling for RL78 complex relocs. Returns the
386 value of the reloc, or 0 for relocs which do not generate
387 a result. SYMVAL is the value of the symbol for relocs
388 which use a symbolic argument. */
389
390static bfd_vma
391rl78_compute_complex_reloc (unsigned long r_type,
983cdaec
AM		 392 bfd_vma symval,
393 asection *input_section,
394 bfd_reloc_status_type *r,
395 char **error_message)
6ff71e76
NC		 396{
397 int32_t tmp1, tmp2;
983cdaec 398 bfd_vma relocation = 0;
3318d800 399 bfd_reloc_status_type status = bfd_reloc_ok;
6ff71e76
NC		 400
401 switch (r_type)
402 {
403 default:
3318d800 404 status = bfd_reloc_notsupported;
983cdaec 405 break;
6ff71e76
NC		 406
407 case R_RL78_ABS24S_PCREL:
408 case R_RL78_ABS16S_PCREL:
409 case R_RL78_ABS8S_PCREL:
3318d800 410 relocation = rl78_stack_pop (&status);
6ff71e76 411 relocation -= input_section->output_section->vma + input_section->output_offset;
983cdaec 412 break;
6ff71e76
NC		 413
414 case R_RL78_ABS32:
415 case R_RL78_ABS32_REV:
416 case R_RL78_ABS16:
417 case R_RL78_ABS16_REV:
418 case R_RL78_ABS16S:
419 case R_RL78_ABS16U:
420 case R_RL78_ABS8:
421 case R_RL78_ABS8U:
422 case R_RL78_ABS8S:
3318d800 423 relocation = rl78_stack_pop (&status);
983cdaec 424 break;
6ff71e76
NC		 425
426 case R_RL78_ABS16UL:
427 case R_RL78_ABS8UL:
3318d800 428 relocation = rl78_stack_pop (&status) >> 2;
983cdaec 429 break;;
6ff71e76
NC		 430
431 case R_RL78_ABS16UW:
432 case R_RL78_ABS8UW:
3318d800 433 relocation = rl78_stack_pop (&status) >> 1;
983cdaec 434 break;
6ff71e76
NC		 435
436 /* The rest of the relocs compute values and then push them onto the stack. */
437 case R_RL78_OPramtop:
438 case R_RL78_OPromtop:
439 case R_RL78_SYM:
3318d800 440 rl78_stack_push (symval, &status);
983cdaec 441 break;
1b786873 442
6ff71e76 443 case R_RL78_OPneg:
3318d800 444 tmp1 = rl78_stack_pop (&status);
6ff71e76 445 tmp1 = - tmp1;
3318d800 446 rl78_stack_push (tmp1, &status);
983cdaec 447 break;
6ff71e76
NC		 448
449 case R_RL78_OPadd:
3318d800
AM		 450 tmp2 = rl78_stack_pop (&status);
451 tmp1 = rl78_stack_pop (&status);
6ff71e76 452 tmp1 += tmp2;
3318d800 453 rl78_stack_push (tmp1, &status);
983cdaec 454 break;
6ff71e76
NC		 455
456 case R_RL78_OPsub:
457 /* For the expression "A - B", the assembler pushes A,
458 then B, then OPSUB. So the first op we pop is B, not A. */
3318d800
AM		 459 tmp2 = rl78_stack_pop (&status); /* B */
460 tmp1 = rl78_stack_pop (&status); /* A */
6ff71e76 461 tmp1 -= tmp2; /* A - B */
3318d800 462 rl78_stack_push (tmp1, &status);
983cdaec 463 break;
6ff71e76
NC		 464
465 case R_RL78_OPmul:
3318d800
AM		 466 tmp2 = rl78_stack_pop (&status);
467 tmp1 = rl78_stack_pop (&status);
6ff71e76 468 tmp1 *= tmp2;
3318d800 469 rl78_stack_push (tmp1, &status);
983cdaec 470 break;
6ff71e76
NC		 471
472 case R_RL78_OPdiv:
3318d800
AM		 473 tmp2 = rl78_stack_pop (&status);
474 tmp1 = rl78_stack_pop (&status);
983cdaec
AM		 475 if (tmp2 != 0)
476 tmp1 /= tmp2;
477 else
478 {
479 tmp1 = 0;
3318d800 480 status = bfd_reloc_overflow;
983cdaec 481 }
3318d800 482 rl78_stack_push (tmp1, &status);
983cdaec 483 break;
6ff71e76
NC		 484
485 case R_RL78_OPshla:
3318d800
AM		 486 tmp2 = rl78_stack_pop (&status);
487 tmp1 = rl78_stack_pop (&status);
6ff71e76 488 tmp1 <<= tmp2;
3318d800 489 rl78_stack_push (tmp1, &status);
983cdaec 490 break;
6ff71e76
NC		 491
492 case R_RL78_OPshra:
3318d800
AM		 493 tmp2 = rl78_stack_pop (&status);
494 tmp1 = rl78_stack_pop (&status);
6ff71e76 495 tmp1 >>= tmp2;
3318d800 496 rl78_stack_push (tmp1, &status);
983cdaec 497 break;
6ff71e76
NC		 498
499 case R_RL78_OPsctsize:
3318d800 500 rl78_stack_push (input_section->size, &status);
983cdaec 501 break;
6ff71e76
NC		 502
503 case R_RL78_OPscttop:
3318d800 504 rl78_stack_push (input_section->output_section->vma, &status);
983cdaec 505 break;
6ff71e76
NC		 506
507 case R_RL78_OPand:
3318d800
AM		 508 tmp2 = rl78_stack_pop (&status);
509 tmp1 = rl78_stack_pop (&status);
6ff71e76 510 tmp1 &= tmp2;
3318d800 511 rl78_stack_push (tmp1, &status);
983cdaec 512 break;
6ff71e76
NC		 513
514 case R_RL78_OPor:
3318d800
AM		 515 tmp2 = rl78_stack_pop (&status);
516 tmp1 = rl78_stack_pop (&status);
6ff71e76 517 tmp1 |= tmp2;
3318d800 518 rl78_stack_push (tmp1, &status);
983cdaec 519 break;
6ff71e76
NC		 520
521 case R_RL78_OPxor:
3318d800
AM		 522 tmp2 = rl78_stack_pop (&status);
523 tmp1 = rl78_stack_pop (&status);
6ff71e76 524 tmp1 ^= tmp2;
3318d800 525 rl78_stack_push (tmp1, &status);
983cdaec 526 break;
6ff71e76
NC		 527
528 case R_RL78_OPnot:
3318d800 529 tmp1 = rl78_stack_pop (&status);
6ff71e76 530 tmp1 = ~ tmp1;
3318d800 531 rl78_stack_push (tmp1, &status);
983cdaec 532 break;
6ff71e76
NC		 533
534 case R_RL78_OPmod:
3318d800
AM		 535 tmp2 = rl78_stack_pop (&status);
536 tmp1 = rl78_stack_pop (&status);
983cdaec
AM		 537 if (tmp2 != 0)
538 tmp1 %= tmp2;
539 else
540 {
541 tmp1 = 0;
3318d800 542 status = bfd_reloc_overflow;
983cdaec 543 }
3318d800 544 rl78_stack_push (tmp1, &status);
983cdaec 545 break;
6ff71e76 546 }
6ff71e76 547
983cdaec
AM		 548 if (r)
549 {
3318d800 550 if (status == bfd_reloc_dangerous)
983cdaec 551 *error_message = (_("RL78 reloc stack overflow/underflow"));
3318d800 552 else if (status == bfd_reloc_overflow)
983cdaec 553 {
3318d800 554 status = bfd_reloc_dangerous;
983cdaec
AM		 555 *error_message = (_("RL78 reloc divide by zero"));
556 }
3318d800 557 *r = status;
983cdaec
AM		 558 }
559 return relocation;
560}
6ff71e76 561
2ad55ffc
AM		 562/* Check whether RELOCATION overflows a relocation field described by
563 HOWTO. */
564
565static bfd_reloc_status_type
566check_overflow (reloc_howto_type *howto, bfd_vma relocation)
567{
568 switch (howto->complain_on_overflow)
569 {
570 case complain_overflow_dont:
571 break;
572
573 case complain_overflow_bitfield:
574 if ((bfd_signed_vma) relocation < -(1LL << (howto->bitsize - 1))
575 || (bfd_signed_vma) relocation >= 1LL << howto->bitsize)
576 return bfd_reloc_overflow;
577 break;
578
579 case complain_overflow_signed:
580 if ((bfd_signed_vma) relocation < -(1LL << (howto->bitsize - 1))
581 || (bfd_signed_vma) relocation >= 1LL << (howto->bitsize - 1))
582 return bfd_reloc_overflow;
583 break;
584
585 case complain_overflow_unsigned:
586 if (relocation >= 1ULL << howto->bitsize)
587 return bfd_reloc_overflow;
588 break;
589 }
590 return bfd_reloc_ok;
591}
6ff71e76
NC		 592
593static bfd_reloc_status_type
594rl78_special_reloc (bfd * input_bfd,
595 arelent * reloc,
596 asymbol * symbol,
597 void * data,
598 asection * input_section,
599 bfd * output_bfd ATTRIBUTE_UNUSED,
983cdaec 600 char ** error_message)
6ff71e76 601{
07d6d2b8
AM		 602 bfd_reloc_status_type r = bfd_reloc_ok;
603 bfd_vma relocation = 0;
604 unsigned long r_type = reloc->howto->type;
605 bfd_byte * contents = data;
6ff71e76
NC		 606
607 /* If necessary, compute the symbolic value of the relocation. */
608 switch (r_type)
609 {
610 case R_RL78_SYM:
611 relocation = (symbol->value
612 + symbol->section->output_section->vma
613 + symbol->section->output_offset
614 + reloc->addend);
615 break;
616
617 case R_RL78_OPromtop:
1a72702b 618 relocation = get_romstart (NULL, input_bfd, input_section,
6ff71e76
NC		 619 reloc->address);
620 break;
621
622 case R_RL78_OPramtop:
1a72702b 623 relocation = get_ramstart (NULL, input_bfd, input_section,
6ff71e76
NC		 624 reloc->address);
625 break;
626 }
627
628 /* Get the value of the relocation. */
983cdaec
AM		 629 relocation = rl78_compute_complex_reloc (r_type, relocation, input_section,
630 &r, error_message);
6ff71e76 631
2ad55ffc 632 if (STACK_REL_P (r_type))
6ff71e76 633 {
2ad55ffc
AM		 634 bfd_size_type limit;
635 unsigned int nbytes;
636
637 if (r == bfd_reloc_ok)
638 r = check_overflow (reloc->howto, relocation);
639
640 if (r_type == R_RL78_ABS16_REV)
641 relocation = ((relocation & 0xff) << 8) | ((relocation >> 8) & 0xff);
642 else if (r_type == R_RL78_ABS32_REV)
643 relocation = (((relocation & 0xff) << 24)
644 | ((relocation & 0xff00) << 8)
645 | ((relocation >> 8) & 0xff00)
646 | ((relocation >> 24) & 0xff));
647
648 limit = bfd_get_section_limit_octets (input_bfd, input_section);
649 nbytes = reloc->howto->bitsize / 8;
650 if (reloc->address < limit
651 && nbytes <= limit - reloc->address)
652 {
653 unsigned int i;
6ff71e76 654
2ad55ffc
AM		 655 for (i = 0; i < nbytes; i++)
656 {
657 contents[reloc->address + i] = relocation;
658 relocation >>= 8;
659 }
660 }
661 else
662 r = bfd_reloc_outofrange;
6ff71e76
NC		 663 }
664
665 return r;
666}
667
6ff71e76
NC		 668#define OP(i) (contents[rel->r_offset + (i)])
669
99c513f6
DD		 670/* Relocate an RL78 ELF section.
671 There is some attempt to make this function usable for many architectures,
672 both USE_REL and USE_RELA ['twould be nice if such a critter existed],
673 if only to serve as a learning tool.
674
675 The RELOCATE_SECTION function is called by the new ELF backend linker
676 to handle the relocations for a section.
677
678 The relocs are always passed as Rela structures; if the section
679 actually uses Rel structures, the r_addend field will always be
680 zero.
681
682 This function is responsible for adjusting the section contents as
683 necessary, and (if using Rela relocs and generating a relocatable
684 output file) adjusting the reloc addend as necessary.
685
686 This function does not have to worry about setting the reloc
687 address or the reloc symbol index.
688
689 LOCAL_SYMS is a pointer to the swapped in local symbols.
690
691 LOCAL_SECTIONS is an array giving the section in the input file
692 corresponding to the st_shndx field of each local symbol.
693
694 The global hash table entry for the global symbols can be found
695 via elf_sym_hashes (input_bfd).
696
697 When generating relocatable output, this function must handle
698 STB_LOCAL/STT_SECTION symbols specially. The output symbol is
699 going to be the section symbol corresponding to the output
700 section, which means that the addend must be adjusted
701 accordingly. */
702
0f684201 703static int
99c513f6 704rl78_elf_relocate_section
07d6d2b8 705 (bfd * output_bfd,
99c513f6 706 struct bfd_link_info * info,
07d6d2b8
AM		 707 bfd * input_bfd,
708 asection * input_section,
709 bfd_byte * contents,
99c513f6 710 Elf_Internal_Rela * relocs,
07d6d2b8
AM		 711 Elf_Internal_Sym * local_syms,
712 asection ** local_sections)
99c513f6 713{
07d6d2b8 714 Elf_Internal_Shdr * symtab_hdr;
99c513f6 715 struct elf_link_hash_entry ** sym_hashes;
07d6d2b8
AM		 716 Elf_Internal_Rela * rel;
717 Elf_Internal_Rela * relend;
99c513f6 718 asection *splt;
983cdaec 719 bool ret;
99c513f6
DD		 720
721 symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
722 sym_hashes = elf_sym_hashes (input_bfd);
723 relend = relocs + input_section->reloc_count;
724
ce558b89 725 splt = elf_hash_table (info)->splt;
983cdaec 726 ret = true;
99c513f6
DD		 727 for (rel = relocs; rel < relend; rel ++)
728 {
0a1b45a2
AM		 729 reloc_howto_type *howto;
730 unsigned long r_symndx;
731 Elf_Internal_Sym *sym;
732 asection *sec;
733 struct elf_link_hash_entry *h;
734 bfd_vma relocation;
735 bfd_reloc_status_type r;
736 const char *name = NULL;
737 bool unresolved_reloc = true;
738 int r_type;
983cdaec 739 char *error_message;
99c513f6
DD		 740
741 r_type = ELF32_R_TYPE (rel->r_info);
742 r_symndx = ELF32_R_SYM (rel->r_info);
743
744 howto = rl78_elf_howto_table + ELF32_R_TYPE (rel->r_info);
07d6d2b8 745 h = NULL;
99c513f6
DD		 746 sym = NULL;
747 sec = NULL;
748 relocation = 0;
749
750 if (r_symndx < symtab_hdr->sh_info)
751 {
752 sym = local_syms + r_symndx;
753 sec = local_sections [r_symndx];
754 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel);
755
756 name = bfd_elf_string_from_elf_section
757 (input_bfd, symtab_hdr->sh_link, sym->st_name);
fd361982 758 name = sym->st_name == 0 ? bfd_section_name (sec) : name;
99c513f6
DD		 759 }
760 else
761 {
0a1b45a2
AM		 762 bool warned ATTRIBUTE_UNUSED;
763 bool ignored ATTRIBUTE_UNUSED;
99c513f6
DD		 764
765 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
766 r_symndx, symtab_hdr, sym_hashes, h,
767 sec, relocation, unresolved_reloc,
62d887d4 768 warned, ignored);
99c513f6
DD		 769
770 name = h->root.root.string;
771 }
772
95b57ade 773 if (sec != NULL && discarded_section (sec))
99c513f6 774 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 775 rel, 1, relend, howto, 0, contents);
99c513f6 776
0e1862bb 777 if (bfd_link_relocatable (info))
99c513f6
DD		 778 {
779 /* This is a relocatable link. We don't have to change
07d6d2b8
AM		 780 anything, unless the reloc is against a section symbol,
781 in which case we have to adjust according to where the
782 section symbol winds up in the output section. */
99c513f6
DD		 783 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
784 rel->r_addend += sec->output_offset;
785 continue;
786 }
787
788 switch (ELF32_R_TYPE (rel->r_info))
789 {
790 case R_RL78_DIR16S:
791 {
792 bfd_vma *plt_offset;
793
794 if (h != NULL)
795 plt_offset = &h->plt.offset;
796 else
797 plt_offset = elf_local_got_offsets (input_bfd) + r_symndx;
798
9cea966c 799 if (! valid_16bit_address (relocation))
99c513f6 800 {
99c513f6
DD		 801 /* If this is the first time we've processed this symbol,
802 fill in the plt entry with the correct symbol address. */
803 if ((*plt_offset & 1) == 0)
804 {
805 unsigned int x;
806
807 x = 0x000000ec; /* br !!abs24 */
808 x |= (relocation << 8) & 0xffffff00;
809 bfd_put_32 (input_bfd, x, splt->contents + *plt_offset);
810 *plt_offset |= 1;
811 }
812
813 relocation = (splt->output_section->vma
814 + splt->output_offset
815 + (*plt_offset & -2));
816 if (name)
817 {
818 char *newname = bfd_malloc (strlen(name)+5);
819 strcpy (newname, name);
820 strcat(newname, ".plt");
821 _bfd_generic_link_add_one_symbol (info,
822 input_bfd,
823 newname,
824 BSF_FUNCTION | BSF_WEAK,
825 splt,
826 (*plt_offset & -2),
827 0,
828 1,
829 0,
830 0);
831 }
832 }
833 }
834 break;
835 }
836
837 if (h != NULL && h->root.type == bfd_link_hash_undefweak)
838 /* If the symbol is undefined and weak
839 then the relocation resolves to zero. */
840 relocation = 0;
841 else
842 {
843 if (howto->pc_relative)
844 {
845 relocation -= (input_section->output_section->vma
846 + input_section->output_offset
847 + rel->r_offset);
848 relocation -= bfd_get_reloc_size (howto);
849 }
850
851 relocation += rel->r_addend;
852 }
853
854 r = bfd_reloc_ok;
2ad55ffc
AM		 855 if (howto->bitsize != 0
856 && (rel->r_offset >= input_section->size
857 || ((howto->bitsize + 7u) / 8
858 > input_section->size - rel->r_offset)))
859 r = bfd_reloc_outofrange;
860 else
861 switch (r_type)
862 {
863 case R_RL78_NONE:
864 break;
865
866 case R_RL78_RH_RELAX:
867 break;
868
869 case R_RL78_DIR8S_PCREL:
870 OP (0) = relocation;
871 break;
872
873 case R_RL78_DIR8S:
874 OP (0) = relocation;
875 break;
876
877 case R_RL78_DIR8U:
878 OP (0) = relocation;
879 break;
880
881 case R_RL78_DIR16S_PCREL:
882 OP (0) = relocation;
883 OP (1) = relocation >> 8;
884 break;
885
886 case R_RL78_DIR16S:
887 if ((relocation & 0xf0000) == 0xf0000)
888 relocation &= 0xffff;
889 OP (0) = relocation;
890 OP (1) = relocation >> 8;
891 break;
892
893 case R_RL78_DIR16U:
894 OP (0) = relocation;
895 OP (1) = relocation >> 8;
896 break;
897
898 case R_RL78_DIR16:
899 OP (0) = relocation;
900 OP (1) = relocation >> 8;
901 break;
902
903 case R_RL78_DIR16_REV:
904 OP (1) = relocation;
905 OP (0) = relocation >> 8;
906 break;
907
908 case R_RL78_DIR3U_PCREL:
909 OP (0) &= 0xf8;
910 OP (0) |= relocation & 0x07;
911 /* Map [3, 10] to [0, 7]. The code below using howto
912 bitsize will check for unsigned overflow. */
913 relocation -= 3;
914 break;
915
916 case R_RL78_DIR24S_PCREL:
917 OP (0) = relocation;
918 OP (1) = relocation >> 8;
919 OP (2) = relocation >> 16;
920 break;
921
922 case R_RL78_DIR24S:
923 OP (0) = relocation;
924 OP (1) = relocation >> 8;
925 OP (2) = relocation >> 16;
926 break;
927
928 case R_RL78_DIR32:
929 OP (0) = relocation;
930 OP (1) = relocation >> 8;
931 OP (2) = relocation >> 16;
932 OP (3) = relocation >> 24;
933 break;
934
935 case R_RL78_DIR32_REV:
936 OP (3) = relocation;
937 OP (2) = relocation >> 8;
938 OP (1) = relocation >> 16;
939 OP (0) = relocation >> 24;
940 break;
941
942 case R_RL78_RH_SFR:
943 relocation -= 0xfff00;
944 OP (0) = relocation;
945 break;
946
947 case R_RL78_RH_SADDR:
948 relocation -= 0xffe20;
949 OP (0) = relocation;
950 break;
951
952 /* Complex reloc handling: */
953 case R_RL78_ABS32:
954 case R_RL78_ABS32_REV:
955 case R_RL78_ABS24S_PCREL:
956 case R_RL78_ABS24S:
957 case R_RL78_ABS16:
958 case R_RL78_ABS16_REV:
959 case R_RL78_ABS16S_PCREL:
960 case R_RL78_ABS16S:
961 case R_RL78_ABS16U:
962 case R_RL78_ABS16UL:
963 case R_RL78_ABS16UW:
964 case R_RL78_ABS8:
965 case R_RL78_ABS8U:
966 case R_RL78_ABS8UL:
967 case R_RL78_ABS8UW:
968 case R_RL78_ABS8S_PCREL:
969 case R_RL78_ABS8S:
970 case R_RL78_OPneg:
971 case R_RL78_OPadd:
972 case R_RL78_OPsub:
973 case R_RL78_OPmul:
974 case R_RL78_OPdiv:
975 case R_RL78_OPshla:
976 case R_RL78_OPshra:
977 case R_RL78_OPsctsize:
978 case R_RL78_OPscttop:
979 case R_RL78_OPand:
980 case R_RL78_OPor:
981 case R_RL78_OPxor:
982 case R_RL78_OPnot:
983 case R_RL78_OPmod:
984 relocation = rl78_compute_complex_reloc (r_type, 0, input_section,
985 &r, &error_message);
986
987 switch (r_type)
988 {
989 case R_RL78_ABS32:
990 OP (0) = relocation;
991 OP (1) = relocation >> 8;
992 OP (2) = relocation >> 16;
993 OP (3) = relocation >> 24;
994 break;
995
996 case R_RL78_ABS32_REV:
997 OP (3) = relocation;
998 OP (2) = relocation >> 8;
999 OP (1) = relocation >> 16;
1000 OP (0) = relocation >> 24;
1001 break;
1002
1003 case R_RL78_ABS24S_PCREL:
1004 case R_RL78_ABS24S:
1005 OP (0) = relocation;
1006 OP (1) = relocation >> 8;
1007 OP (2) = relocation >> 16;
1008 break;
1009
1010 case R_RL78_ABS16:
1011 OP (0) = relocation;
1012 OP (1) = relocation >> 8;
1013 break;
1014
1015 case R_RL78_ABS16_REV:
1016 OP (1) = relocation;
1017 OP (0) = relocation >> 8;
1018 break;
1019
1020 case R_RL78_ABS16S_PCREL:
1021 case R_RL78_ABS16S:
1022 OP (0) = relocation;
1023 OP (1) = relocation >> 8;
1024 break;
1025
1026 case R_RL78_ABS16U:
1027 case R_RL78_ABS16UL:
1028 case R_RL78_ABS16UW:
1029 OP (0) = relocation;
1030 OP (1) = relocation >> 8;
1031 break;
1032
1033 case R_RL78_ABS8:
1034 OP (0) = relocation;
1035 break;
1036
1037 case R_RL78_ABS8U:
1038 case R_RL78_ABS8UL:
1039 case R_RL78_ABS8UW:
1040 OP (0) = relocation;
1041 break;
1042
1043 case R_RL78_ABS8S_PCREL:
1044 case R_RL78_ABS8S:
1045 OP (0) = relocation;
1046 break;
1047
1048 default:
1049 break;
1050 }
1051 break;
1052
1053 case R_RL78_SYM:
1054 if (r_symndx < symtab_hdr->sh_info)
1055 relocation = sec->output_section->vma + sec->output_offset
1056 + sym->st_value + rel->r_addend;
1057 else if (h != NULL
1058 && (h->root.type == bfd_link_hash_defined
1059 || h->root.type == bfd_link_hash_defweak))
1060 relocation = h->root.u.def.value
1061 + sec->output_section->vma
1062 + sec->output_offset
1063 + rel->r_addend;
1064 else
1065 {
1066 relocation = 0;
1067 if (h->root.type != bfd_link_hash_undefweak)
1068 _bfd_error_handler
1069 (_("warning: RL78_SYM reloc with an unknown symbol"));
1070 }
1071 (void) rl78_compute_complex_reloc (r_type, relocation, input_section,
1072 &r, &error_message);
1073 break;
1074
1075 case R_RL78_OPromtop:
1076 relocation = get_romstart (info, input_bfd, input_section,
1077 rel->r_offset);
1078 (void) rl78_compute_complex_reloc (r_type, relocation, input_section,
1079 &r, &error_message);
1080 break;
1081
1082 case R_RL78_OPramtop:
1083 relocation = get_ramstart (info, input_bfd, input_section,
1084 rel->r_offset);
1085 (void) rl78_compute_complex_reloc (r_type, relocation, input_section,
1086 &r, &error_message);
1087 break;
1088
1089 default:
1090 r = bfd_reloc_notsupported;
1091 break;
1092 }
99c513f6 1093
2ad55ffc
AM		 1094 if (r == bfd_reloc_ok)
1095 r = check_overflow (howto, relocation);
99c513f6
DD		 1096
1097 if (r != bfd_reloc_ok)
1098 {
99c513f6
DD		 1099 switch (r)
1100 {
1101 case bfd_reloc_overflow:
983cdaec
AM		 1102 (*info->callbacks->reloc_overflow)
1103 (info, (h ? &h->root : NULL), name, howto->name, (bfd_vma) 0,
1104 input_bfd, input_section, rel->r_offset);
99c513f6
DD		 1105 break;
1106
1107 case bfd_reloc_undefined:
1a72702b 1108 (*info->callbacks->undefined_symbol)
0a1b45a2 1109 (info, name, input_bfd, input_section, rel->r_offset, true);
99c513f6
DD		 1110 break;
1111
99c513f6 1112 case bfd_reloc_outofrange:
983cdaec
AM		 1113 /* xgettext:c-format */
1114 (*info->callbacks->einfo)
1115 (_("%H: %s out of range\n"),
1116 input_bfd, input_section, rel->r_offset, howto->name);
99c513f6
DD		 1117 break;
1118
1119 case bfd_reloc_notsupported:
695344c0 1120 /* xgettext:c-format */
983cdaec
AM		 1121 (*info->callbacks->einfo)
1122 (_("%H: relocation type %u is not supported\n"),
1123 input_bfd, input_section, rel->r_offset, r_type);
99c513f6
DD		 1124 break;
1125
1126 case bfd_reloc_dangerous:
983cdaec
AM		 1127 (*info->callbacks->reloc_dangerous)
1128 (info, error_message, input_bfd, input_section, rel->r_offset);
99c513f6
DD		 1129 break;
1130
1131 default:
695344c0 1132 /* xgettext:c-format */
983cdaec
AM		 1133 (*info->callbacks->einfo)
1134 (_("%H: relocation %s returns an unrecognized value %x\n"),
1135 input_bfd, input_section, rel->r_offset, howto->name, r);
99c513f6
DD		 1136 break;
1137 }
983cdaec 1138 ret = false;
99c513f6
DD		 1139 }
1140 }
1141
983cdaec 1142 return ret;
99c513f6
DD		 1143}
1144\f
1145/* Function to set the ELF flag bits. */
1146
0a1b45a2 1147static bool
99c513f6
DD		 1148rl78_elf_set_private_flags (bfd * abfd, flagword flags)
1149{
1150 elf_elfheader (abfd)->e_flags = flags;
0a1b45a2
AM		 1151 elf_flags_init (abfd) = true;
1152 return true;
99c513f6
DD		 1153}
1154
0a1b45a2 1155static bool no_warn_mismatch = false;
99c513f6 1156
0a1b45a2 1157void bfd_elf32_rl78_set_target_flags (bool);
99c513f6
DD		 1158
1159void
0a1b45a2 1160bfd_elf32_rl78_set_target_flags (bool user_no_warn_mismatch)
99c513f6
DD		 1161{
1162 no_warn_mismatch = user_no_warn_mismatch;
1163}
1164
1740ba0c
NC		 1165static const char *
1166rl78_cpu_name (flagword flags)
1167{
1168 switch (flags & E_FLAG_RL78_CPU_MASK)
1169 {
1170 default: return "";
1171 case E_FLAG_RL78_G10: return "G10";
1172 case E_FLAG_RL78_G13: return "G13";
1173 case E_FLAG_RL78_G14: return "G14";
1174 }
1175}
1176
99c513f6
DD		 1177/* Merge backend specific data from an object file to the output
1178 object file when linking. */
1179
0a1b45a2 1180static bool
50e03d47 1181rl78_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
99c513f6 1182{
50e03d47 1183 bfd *obfd = info->output_bfd;
99c513f6 1184 flagword new_flags;
4046d87a 1185 flagword old_flags;
0a1b45a2 1186 bool error = false;
99c513f6
DD		 1187
1188 new_flags = elf_elfheader (ibfd)->e_flags;
4046d87a 1189 old_flags = elf_elfheader (obfd)->e_flags;
99c513f6
DD		 1190
1191 if (!elf_flags_init (obfd))
1192 {
1193 /* First call, no flags set. */
0a1b45a2 1194 elf_flags_init (obfd) = true;
99c513f6
DD		 1195 elf_elfheader (obfd)->e_flags = new_flags;
1196 }
4046d87a
NC		 1197 else if (old_flags != new_flags)
1198 {
1199 flagword changed_flags = old_flags ^ new_flags;
1200
1740ba0c 1201 if (changed_flags & E_FLAG_RL78_CPU_MASK)
4046d87a 1202 {
1740ba0c
NC		 1203 flagword out_cpu = old_flags & E_FLAG_RL78_CPU_MASK;
1204 flagword in_cpu = new_flags & E_FLAG_RL78_CPU_MASK;
4046d87a 1205
1740ba0c
NC		 1206 if (in_cpu == E_FLAG_RL78_ANY_CPU || in_cpu == out_cpu)
1207 /* It does not matter what new_cpu may have. */;
1208 else if (out_cpu == E_FLAG_RL78_ANY_CPU)
1209 {
1210 if (in_cpu == E_FLAG_RL78_G10)
1211 {
1212 /* G10 files can only be linked with other G10 files.
1213 If the output is set to "any" this means that it is
1214 a G14 file that does not use hardware multiply/divide,
1215 but that is still incompatible with the G10 ABI. */
0a1b45a2 1216 error = true;
1740ba0c 1217
4eca0228 1218 _bfd_error_handler
695344c0 1219 /* xgettext:c-format */
871b3ab2
AM		 1220 (_("RL78 ABI conflict: G10 file %pB cannot be linked"
1221 " with %s file %pB"),
dae82561 1222 ibfd, rl78_cpu_name (out_cpu), obfd);
1740ba0c
NC		 1223 }
1224 else
1225 {
1226 old_flags &= ~ E_FLAG_RL78_CPU_MASK;
1227 old_flags |= in_cpu;
1228 elf_elfheader (obfd)->e_flags = old_flags;
1229 }
1230 }
4046d87a 1231 else
1740ba0c 1232 {
0a1b45a2 1233 error = true;
1740ba0c 1234
4eca0228 1235 _bfd_error_handler
695344c0 1236 /* xgettext:c-format */
871b3ab2 1237 (_("RL78 ABI conflict: cannot link %s file %pB with %s file %pB"),
dae82561
AM		 1238 rl78_cpu_name (in_cpu), ibfd,
1239 rl78_cpu_name (out_cpu), obfd);
1740ba0c 1240 }
4046d87a 1241 }
856ea05c
KP		 1242
1243 if (changed_flags & E_FLAG_RL78_64BIT_DOUBLES)
1244 {
4eca0228 1245 _bfd_error_handler
856ea05c
KP		 1246 (_("RL78 merge conflict: cannot link 32-bit and 64-bit objects together"));
1247
1248 if (old_flags & E_FLAG_RL78_64BIT_DOUBLES)
695344c0 1249 /* xgettext:c-format */
871b3ab2 1250 _bfd_error_handler (_("- %pB is 64-bit, %pB is not"),
dae82561 1251 obfd, ibfd);
856ea05c 1252 else
695344c0 1253 /* xgettext:c-format */
871b3ab2 1254 _bfd_error_handler (_("- %pB is 64-bit, %pB is not"),
dae82561 1255 ibfd, obfd);
0a1b45a2 1256 error = true;
1b786873 1257 }
4046d87a 1258 }
99c513f6
DD		 1259
1260 return !error;
1261}
1262\f
0a1b45a2 1263static bool
99c513f6
DD		 1264rl78_elf_print_private_bfd_data (bfd * abfd, void * ptr)
1265{
1266 FILE * file = (FILE *) ptr;
1267 flagword flags;
1268
1269 BFD_ASSERT (abfd != NULL && ptr != NULL);
1270
1271 /* Print normal ELF private data. */
1272 _bfd_elf_print_private_bfd_data (abfd, ptr);
1273
1274 flags = elf_elfheader (abfd)->e_flags;
1275 fprintf (file, _("private flags = 0x%lx:"), (long) flags);
1276
1740ba0c
NC		 1277 if (flags & E_FLAG_RL78_CPU_MASK)
1278 fprintf (file, " [%s]", rl78_cpu_name (flags));
4046d87a 1279
856ea05c
KP		 1280 if (flags & E_FLAG_RL78_64BIT_DOUBLES)
1281 fprintf (file, _(" [64-bit doubles]"));
1282
99c513f6 1283 fputc ('\n', file);
0a1b45a2 1284 return true;
99c513f6
DD		 1285}
1286
1287/* Return the MACH for an e_flags value. */
1288
1289static int
1740ba0c 1290elf32_rl78_machine (bfd * abfd ATTRIBUTE_UNUSED)
99c513f6 1291{
1740ba0c 1292 return bfd_mach_rl78;
99c513f6
DD		 1293}
1294
0a1b45a2 1295static bool
99c513f6
DD		 1296rl78_elf_object_p (bfd * abfd)
1297{
1298 bfd_default_set_arch_mach (abfd, bfd_arch_rl78,
1299 elf32_rl78_machine (abfd));
0a1b45a2 1300 return true;
99c513f6 1301}
99c513f6
DD		 1302\f
1303/* support PLT for 16-bit references to 24-bit functions. */
1304
1305/* We support 16-bit pointers to code above 64k by generating a thunk
1306 below 64k containing a JMP instruction to the final address. */
68ffbac6 1307
0a1b45a2 1308static bool
99c513f6 1309rl78_elf_check_relocs
07d6d2b8 1310 (bfd * abfd,
99c513f6 1311 struct bfd_link_info * info,
07d6d2b8 1312 asection * sec,
99c513f6
DD		 1313 const Elf_Internal_Rela * relocs)
1314{
07d6d2b8 1315 Elf_Internal_Shdr * symtab_hdr;
99c513f6 1316 struct elf_link_hash_entry ** sym_hashes;
07d6d2b8
AM		 1317 const Elf_Internal_Rela * rel;
1318 const Elf_Internal_Rela * rel_end;
99c513f6
DD		 1319 bfd_vma *local_plt_offsets;
1320 asection *splt;
1321 bfd *dynobj;
1322
0e1862bb 1323 if (bfd_link_relocatable (info))
0a1b45a2 1324 return true;
68ffbac6 1325
99c513f6
DD		 1326 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1327 sym_hashes = elf_sym_hashes (abfd);
1328 local_plt_offsets = elf_local_got_offsets (abfd);
99c513f6
DD		 1329 dynobj = elf_hash_table(info)->dynobj;
1330
1331 rel_end = relocs + sec->reloc_count;
1332 for (rel = relocs; rel < rel_end; rel++)
1333 {
1334 struct elf_link_hash_entry *h;
1335 unsigned long r_symndx;
1336 bfd_vma *offset;
68ffbac6 1337
99c513f6
DD		 1338 r_symndx = ELF32_R_SYM (rel->r_info);
1339 if (r_symndx < symtab_hdr->sh_info)
07d6d2b8 1340 h = NULL;
99c513f6
DD		 1341 else
1342 {
1343 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
1344 while (h->root.type == bfd_link_hash_indirect
1345 || h->root.type == bfd_link_hash_warning)
1346 h = (struct elf_link_hash_entry *) h->root.u.i.link;
1347 }
68ffbac6 1348
99c513f6 1349 switch (ELF32_R_TYPE (rel->r_info))
07d6d2b8 1350 {
99c513f6
DD		 1351 /* This relocation describes a 16-bit pointer to a function.
1352 We may need to allocate a thunk in low memory; reserve memory
1353 for it now. */
1354 case R_RL78_DIR16S:
1355 if (dynobj == NULL)
1356 elf_hash_table (info)->dynobj = dynobj = abfd;
ce558b89 1357 splt = elf_hash_table (info)->splt;
99c513f6
DD		 1358 if (splt == NULL)
1359 {
ce558b89
AM		 1360 flagword flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
1361 | SEC_IN_MEMORY | SEC_LINKER_CREATED
1362 | SEC_READONLY | SEC_CODE);
1363 splt = bfd_make_section_anyway_with_flags (dynobj, ".plt",
1364 flags);
1365 elf_hash_table (info)->splt = splt;
1366 if (splt == NULL
fd361982 1367 || !bfd_set_section_alignment (splt, 1))
0a1b45a2 1368 return false;
99c513f6
DD		 1369 }
1370
1371 if (h != NULL)
1372 offset = &h->plt.offset;
1373 else
1374 {
1375 if (local_plt_offsets == NULL)
1376 {
1377 size_t size;
1378 unsigned int i;
1379
1380 size = symtab_hdr->sh_info * sizeof (bfd_vma);
1381 local_plt_offsets = (bfd_vma *) bfd_alloc (abfd, size);
1382 if (local_plt_offsets == NULL)
0a1b45a2 1383 return false;
99c513f6
DD		 1384 elf_local_got_offsets (abfd) = local_plt_offsets;
1385
1386 for (i = 0; i < symtab_hdr->sh_info; i++)
1387 local_plt_offsets[i] = (bfd_vma) -1;
1388 }
1389 offset = &local_plt_offsets[r_symndx];
1390 }
1391
1392 if (*offset == (bfd_vma) -1)
1393 {
1394 *offset = splt->size;
1395 splt->size += 4;
1396 }
1397 break;
07d6d2b8 1398 }
99c513f6 1399 }
68ffbac6 1400
0a1b45a2 1401 return true;
99c513f6
DD		 1402}
1403
1404/* This must exist if dynobj is ever set. */
1405
0a1b45a2 1406static bool
99c513f6 1407rl78_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
07d6d2b8 1408 struct bfd_link_info *info)
99c513f6
DD		 1409{
1410 bfd *dynobj;
1411 asection *splt;
1412
47fc0f1f 1413 if (!elf_hash_table (info)->dynamic_sections_created)
0a1b45a2 1414 return true;
47fc0f1f 1415
9cea966c
DD		 1416 /* As an extra sanity check, verify that all plt entries have been
1417 filled in. However, relaxing might have changed the relocs so
1418 that some plt entries don't get filled in, so we have to skip
1419 this check if we're relaxing. Unfortunately, check_relocs is
1420 called before relaxation. */
99c513f6 1421
1740ba0c 1422 if (info->relax_trip > 0)
0a1b45a2 1423 return true;
47fc0f1f 1424
ce558b89
AM		 1425 dynobj = elf_hash_table (info)->dynobj;
1426 splt = elf_hash_table (info)->splt;
1427 if (dynobj != NULL && splt != NULL)
99c513f6 1428 {
47fc0f1f
NC		 1429 bfd_byte *contents = splt->contents;
1430 unsigned int i, size = splt->size;
1431
1432 for (i = 0; i < size; i += 4)
99c513f6 1433 {
47fc0f1f
NC		 1434 unsigned int x = bfd_get_32 (dynobj, contents + i);
1435 BFD_ASSERT (x != 0);
99c513f6
DD		 1436 }
1437 }
1438
0a1b45a2 1439 return true;
99c513f6
DD		 1440}
1441
0a1b45a2 1442static bool
af969b14
AM		 1443rl78_elf_early_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
1444 struct bfd_link_info *info)
99c513f6
DD		 1445{
1446 bfd *dynobj;
1447 asection *splt;
1448
0e1862bb 1449 if (bfd_link_relocatable (info))
0a1b45a2 1450 return true;
99c513f6
DD		 1451
1452 dynobj = elf_hash_table (info)->dynobj;
1453 if (dynobj == NULL)
0a1b45a2 1454 return true;
99c513f6 1455
ce558b89 1456 splt = elf_hash_table (info)->splt;
99c513f6
DD		 1457 BFD_ASSERT (splt != NULL);
1458
1459 splt->contents = (bfd_byte *) bfd_zalloc (dynobj, splt->size);
1460 if (splt->contents == NULL)
0a1b45a2 1461 return false;
99c513f6 1462
0a1b45a2 1463 return true;
99c513f6
DD		 1464}
1465
1466\f
1467
1468/* Handle relaxing. */
1469
1470/* A subroutine of rl78_elf_relax_section. If the global symbol H
1471 is within the low 64k, remove any entry for it in the plt. */
1472
1473struct relax_plt_data
1474{
1475 asection *splt;
0a1b45a2 1476 bool *again;
99c513f6
DD		 1477};
1478
0a1b45a2 1479static bool
2c3fc389 1480rl78_relax_plt_check (struct elf_link_hash_entry *h, void * xdata)
99c513f6
DD		 1481{
1482 struct relax_plt_data *data = (struct relax_plt_data *) xdata;
1483
1484 if (h->plt.offset != (bfd_vma) -1)
1485 {
1486 bfd_vma address;
1487
1488 if (h->root.type == bfd_link_hash_undefined
1489 || h->root.type == bfd_link_hash_undefweak)
1490 address = 0;
1491 else
1492 address = (h->root.u.def.section->output_section->vma
1493 + h->root.u.def.section->output_offset
1494 + h->root.u.def.value);
1495
1496 if (valid_16bit_address (address))
1497 {
1498 h->plt.offset = -1;
1499 data->splt->size -= 4;
0a1b45a2 1500 *data->again = true;
99c513f6
DD		 1501 }
1502 }
1503
0a1b45a2 1504 return true;
99c513f6
DD		 1505}
1506
1507/* A subroutine of rl78_elf_relax_section. If the global symbol H
1508 previously had a plt entry, give it a new entry offset. */
1509
0a1b45a2 1510static bool
2c3fc389 1511rl78_relax_plt_realloc (struct elf_link_hash_entry *h, void * xdata)
99c513f6
DD		 1512{
1513 bfd_vma *entry = (bfd_vma *) xdata;
1514
1515 if (h->plt.offset != (bfd_vma) -1)
1516 {
1517 h->plt.offset = *entry;
1518 *entry += 4;
1519 }
1520
0a1b45a2 1521 return true;
99c513f6
DD		 1522}
1523
0a1b45a2 1524static bool
99c513f6 1525rl78_elf_relax_plt_section (bfd *dynobj,
07d6d2b8
AM		 1526 asection *splt,
1527 struct bfd_link_info *info,
0a1b45a2 1528 bool *again)
99c513f6
DD		 1529{
1530 struct relax_plt_data relax_plt_data;
1531 bfd *ibfd;
1532
1533 /* Assume nothing changes. */
0a1b45a2 1534 *again = false;
99c513f6 1535
0e1862bb 1536 if (bfd_link_relocatable (info))
0a1b45a2 1537 return true;
99c513f6
DD		 1538
1539 /* We only relax the .plt section at the moment. */
1540 if (dynobj != elf_hash_table (info)->dynobj
1541 || strcmp (splt->name, ".plt") != 0)
0a1b45a2 1542 return true;
99c513f6
DD		 1543
1544 /* Quick check for an empty plt. */
1545 if (splt->size == 0)
0a1b45a2 1546 return true;
99c513f6
DD		 1547
1548 /* Map across all global symbols; see which ones happen to
1549 fall in the low 64k. */
1550 relax_plt_data.splt = splt;
1551 relax_plt_data.again = again;
1552 elf_link_hash_traverse (elf_hash_table (info), rl78_relax_plt_check,
1553 &relax_plt_data);
1554
1555 /* Likewise for local symbols, though that's somewhat less convenient
1556 as we have to walk the list of input bfds and swap in symbol data. */
c72f2fb2 1557 for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link.next)
99c513f6
DD		 1558 {
1559 bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd);
1560 Elf_Internal_Shdr *symtab_hdr;
1561 Elf_Internal_Sym *isymbuf = NULL;
1562 unsigned int idx;
1563
1564 if (! local_plt_offsets)
1565 continue;
1566
1567 symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
1568 if (symtab_hdr->sh_info != 0)
1569 {
1570 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1571 if (isymbuf == NULL)
1572 isymbuf = bfd_elf_get_elf_syms (ibfd, symtab_hdr,
1573 symtab_hdr->sh_info, 0,
1574 NULL, NULL, NULL);
1575 if (isymbuf == NULL)
0a1b45a2 1576 return false;
99c513f6
DD		 1577 }
1578
1579 for (idx = 0; idx < symtab_hdr->sh_info; ++idx)
1580 {
1581 Elf_Internal_Sym *isym;
1582 asection *tsec;
1583 bfd_vma address;
1584
1585 if (local_plt_offsets[idx] == (bfd_vma) -1)
1586 continue;
1587
1588 isym = &isymbuf[idx];
1589 if (isym->st_shndx == SHN_UNDEF)
1590 continue;
1591 else if (isym->st_shndx == SHN_ABS)
1592 tsec = bfd_abs_section_ptr;
1593 else if (isym->st_shndx == SHN_COMMON)
1594 tsec = bfd_com_section_ptr;
1595 else
1596 tsec = bfd_section_from_elf_index (ibfd, isym->st_shndx);
1597
1598 address = (tsec->output_section->vma
1599 + tsec->output_offset
1600 + isym->st_value);
1601 if (valid_16bit_address (address))
1602 {
1603 local_plt_offsets[idx] = -1;
1604 splt->size -= 4;
0a1b45a2 1605 *again = true;
99c513f6
DD		 1606 }
1607 }
1608
1609 if (isymbuf != NULL
1610 && symtab_hdr->contents != (unsigned char *) isymbuf)
1611 {
1612 if (! info->keep_memory)
1613 free (isymbuf);
1614 else
1615 {
1616 /* Cache the symbols for elf_link_input_bfd. */
1617 symtab_hdr->contents = (unsigned char *) isymbuf;
1618 }
1619 }
1620 }
1621
1622 /* If we changed anything, walk the symbols again to reallocate
1623 .plt entry addresses. */
1624 if (*again && splt->size > 0)
1625 {
1626 bfd_vma entry = 0;
1627
1628 elf_link_hash_traverse (elf_hash_table (info),
1629 rl78_relax_plt_realloc, &entry);
1630
c72f2fb2 1631 for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link.next)
99c513f6
DD		 1632 {
1633 bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd);
1634 unsigned int nlocals = elf_tdata (ibfd)->symtab_hdr.sh_info;
1635 unsigned int idx;
1636
1637 if (! local_plt_offsets)
1638 continue;
1639
1640 for (idx = 0; idx < nlocals; ++idx)
1641 if (local_plt_offsets[idx] != (bfd_vma) -1)
1642 {
07d6d2b8 1643 local_plt_offsets[idx] = entry;
99c513f6
DD		 1644 entry += 4;
1645 }
1646 }
1647 }
1648
0a1b45a2 1649 return true;
99c513f6
DD		 1650}
1651
9cea966c
DD		 1652/* Delete some bytes from a section while relaxing. */
1653
0a1b45a2 1654static bool
9cea966c 1655elf32_rl78_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, int count,
1740ba0c 1656 Elf_Internal_Rela *alignment_rel, int force_snip)
9cea966c
DD		 1657{
1658 Elf_Internal_Shdr * symtab_hdr;
07d6d2b8
AM		 1659 unsigned int sec_shndx;
1660 bfd_byte * contents;
9cea966c
DD		 1661 Elf_Internal_Rela * irel;
1662 Elf_Internal_Rela * irelend;
1663 Elf_Internal_Sym * isym;
1664 Elf_Internal_Sym * isymend;
07d6d2b8
AM		 1665 bfd_vma toaddr;
1666 unsigned int symcount;
9cea966c
DD		 1667 struct elf_link_hash_entry ** sym_hashes;
1668 struct elf_link_hash_entry ** end_hashes;
1669
1670 if (!alignment_rel)
1671 force_snip = 1;
1672
1673 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1674
1675 contents = elf_section_data (sec)->this_hdr.contents;
1676
1677 /* The deletion must stop at the next alignment boundary, if
1678 ALIGNMENT_REL is non-NULL. */
1679 toaddr = sec->size;
1680 if (alignment_rel)
1681 toaddr = alignment_rel->r_offset;
1682
1683 irel = elf_section_data (sec)->relocs;
2bc56d66
DD		 1684 if (irel == NULL)
1685 {
0a1b45a2 1686 _bfd_elf_link_read_relocs (sec->owner, sec, NULL, NULL, true);
2bc56d66
DD		 1687 irel = elf_section_data (sec)->relocs;
1688 }
1689
9cea966c
DD		 1690 irelend = irel + sec->reloc_count;
1691
1692 /* Actually delete the bytes. */
1693 memmove (contents + addr, contents + addr + count,
1694 (size_t) (toaddr - addr - count));
1695
1696 /* If we don't have an alignment marker to worry about, we can just
1697 shrink the section. Otherwise, we have to fill in the newly
1698 created gap with NOP insns (0x03). */
1699 if (force_snip)
1700 sec->size -= count;
1701 else
1702 memset (contents + toaddr - count, 0x03, count);
1703
1704 /* Adjust all the relocs. */
2bc56d66 1705 for (; irel && irel < irelend; irel++)
9cea966c
DD		 1706 {
1707 /* Get the new reloc address. */
1708 if (irel->r_offset > addr
1709 && (irel->r_offset < toaddr
1710 || (force_snip && irel->r_offset == toaddr)))
1711 irel->r_offset -= count;
1712
1713 /* If we see an ALIGN marker at the end of the gap, we move it
1714 to the beginning of the gap, since marking these gaps is what
1715 they're for. */
1716 if (irel->r_offset == toaddr
1717 && ELF32_R_TYPE (irel->r_info) == R_RL78_RH_RELAX
1718 && irel->r_addend & RL78_RELAXA_ALIGN)
1719 irel->r_offset -= count;
1720 }
1721
1722 /* Adjust the local symbols defined in this section. */
1723 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1724 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1725 isymend = isym + symtab_hdr->sh_info;
1726
1727 for (; isym < isymend; isym++)
1728 {
1729 /* If the symbol is in the range of memory we just moved, we
1730 have to adjust its value. */
1731 if (isym->st_shndx == sec_shndx
1732 && isym->st_value > addr
1733 && isym->st_value < toaddr)
1734 isym->st_value -= count;
1735
1736 /* If the symbol *spans* the bytes we just deleted (i.e. it's
1737 *end* is in the moved bytes but it's *start* isn't), then we
1738 must adjust its size. */
1739 if (isym->st_shndx == sec_shndx
1740 && isym->st_value < addr
1741 && isym->st_value + isym->st_size > addr
1742 && isym->st_value + isym->st_size < toaddr)
1743 isym->st_size -= count;
1744 }
1745
1746 /* Now adjust the global symbols defined in this section. */
1747 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1748 - symtab_hdr->sh_info);
1749 sym_hashes = elf_sym_hashes (abfd);
1750 end_hashes = sym_hashes + symcount;
1751
1752 for (; sym_hashes < end_hashes; sym_hashes++)
1753 {
1754 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1755
1756 if ((sym_hash->root.type == bfd_link_hash_defined
1757 || sym_hash->root.type == bfd_link_hash_defweak)
1758 && sym_hash->root.u.def.section == sec)
1759 {
1760 /* As above, adjust the value if needed. */
1761 if (sym_hash->root.u.def.value > addr
1762 && sym_hash->root.u.def.value < toaddr)
1763 sym_hash->root.u.def.value -= count;
1764
1765 /* As above, adjust the size if needed. */
1766 if (sym_hash->root.u.def.value < addr
1767 && sym_hash->root.u.def.value + sym_hash->size > addr
1768 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1769 sym_hash->size -= count;
1770 }
1771 }
1772
0a1b45a2 1773 return true;
9cea966c
DD		 1774}
1775
1776/* Used to sort relocs by address. If relocs have the same address,
1777 we maintain their relative order, except that R_RL78_RH_RELAX
1778 alignment relocs must be the first reloc for any given address. */
1779
1780static void
1781reloc_bubblesort (Elf_Internal_Rela * r, int count)
1782{
1783 int i;
0a1b45a2
AM		 1784 bool again;
1785 bool swappit;
9cea966c
DD		 1786
1787 /* This is almost a classic bubblesort. It's the slowest sort, but
1788 we're taking advantage of the fact that the relocations are
1789 mostly in order already (the assembler emits them that way) and
1790 we need relocs with the same address to remain in the same
1791 relative order. */
0a1b45a2 1792 again = true;
9cea966c
DD		 1793 while (again)
1794 {
0a1b45a2 1795 again = false;
9cea966c
DD		 1796 for (i = 0; i < count - 1; i ++)
1797 {
1798 if (r[i].r_offset > r[i + 1].r_offset)
0a1b45a2 1799 swappit = true;
9cea966c 1800 else if (r[i].r_offset < r[i + 1].r_offset)
0a1b45a2 1801 swappit = false;
9cea966c
DD		 1802 else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RL78_RH_RELAX
1803 && (r[i + 1].r_addend & RL78_RELAXA_ALIGN))
0a1b45a2 1804 swappit = true;
9cea966c
DD		 1805 else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RL78_RH_RELAX
1806 && (r[i + 1].r_addend & RL78_RELAXA_ELIGN)
1807 && !(ELF32_R_TYPE (r[i].r_info) == R_RL78_RH_RELAX
1808 && (r[i].r_addend & RL78_RELAXA_ALIGN)))
0a1b45a2 1809 swappit = true;
9cea966c 1810 else
0a1b45a2 1811 swappit = false;
9cea966c
DD		 1812
1813 if (swappit)
1814 {
1815 Elf_Internal_Rela tmp;
1816
1817 tmp = r[i];
1818 r[i] = r[i + 1];
1819 r[i + 1] = tmp;
1820 /* If we do move a reloc back, re-scan to see if it
1821 needs to be moved even further back. This avoids
1822 most of the O(n^2) behavior for our cases. */
1823 if (i > 0)
1824 i -= 2;
0a1b45a2 1825 again = true;
9cea966c
DD		 1826 }
1827 }
1828 }
1829}
1830
1831
1832#define OFFSET_FOR_RELOC(rel, lrel, scale) \
1833 rl78_offset_for_reloc (abfd, rel + 1, symtab_hdr, shndx_buf, intsyms, \
6ff71e76 1834 lrel, abfd, sec, link_info, scale)
9cea966c
DD		 1835
1836static bfd_vma
07d6d2b8
AM		 1837rl78_offset_for_reloc (bfd * abfd,
1838 Elf_Internal_Rela * rel,
1839 Elf_Internal_Shdr * symtab_hdr,
806470a2 1840 bfd_byte * shndx_buf ATTRIBUTE_UNUSED,
07d6d2b8
AM		 1841 Elf_Internal_Sym * intsyms,
1842 Elf_Internal_Rela ** lrel,
1843 bfd * input_bfd,
1844 asection * input_section,
1845 struct bfd_link_info * info,
1846 int * scale)
9cea966c
DD		 1847{
1848 bfd_vma symval;
9cea966c
DD		 1849
1850 *scale = 1;
1851
1852 /* REL is the first of 1..N relocations. We compute the symbol
1853 value for each relocation, then combine them if needed. LREL
1854 gets a pointer to the last relocation used. */
1855 while (1)
1856 {
6ff71e76 1857 unsigned long r_type;
9cea966c
DD		 1858
1859 /* Get the value of the symbol referred to by the reloc. */
1860 if (ELF32_R_SYM (rel->r_info) < symtab_hdr->sh_info)
1861 {
1862 /* A local symbol. */
1863 Elf_Internal_Sym *isym;
1864 asection *ssec;
1865
1866 isym = intsyms + ELF32_R_SYM (rel->r_info);
1867
1868 if (isym->st_shndx == SHN_UNDEF)
1869 ssec = bfd_und_section_ptr;
1870 else if (isym->st_shndx == SHN_ABS)
1871 ssec = bfd_abs_section_ptr;
1872 else if (isym->st_shndx == SHN_COMMON)
1873 ssec = bfd_com_section_ptr;
1874 else
1875 ssec = bfd_section_from_elf_index (abfd,
1876 isym->st_shndx);
1877
1878 /* Initial symbol value. */
1879 symval = isym->st_value;
1880
1881 /* GAS may have made this symbol relative to a section, in
1882 which case, we have to add the addend to find the
1883 symbol. */
1884 if (ELF_ST_TYPE (isym->st_info) == STT_SECTION)
1885 symval += rel->r_addend;
1886
1887 if (ssec)
1888 {
1889 if ((ssec->flags & SEC_MERGE)
dbaa2011 1890 && ssec->sec_info_type == SEC_INFO_TYPE_MERGE)
9cea966c
DD		 1891 symval = _bfd_merged_section_offset (abfd, & ssec,
1892 elf_section_data (ssec)->sec_info,
1893 symval);
1894 }
1895
1896 /* Now make the offset relative to where the linker is putting it. */
1897 if (ssec)
1898 symval +=
1899 ssec->output_section->vma + ssec->output_offset;
1900
1901 symval += rel->r_addend;
1902 }
1903 else
1904 {
1905 unsigned long indx;
1906 struct elf_link_hash_entry * h;
1907
1908 /* An external symbol. */
1909 indx = ELF32_R_SYM (rel->r_info) - symtab_hdr->sh_info;
1910 h = elf_sym_hashes (abfd)[indx];
1911 BFD_ASSERT (h != NULL);
1912
1913 if (h->root.type != bfd_link_hash_defined
1914 && h->root.type != bfd_link_hash_defweak)
1915 {
1916 /* This appears to be a reference to an undefined
1917 symbol. Just ignore it--it will be caught by the
1918 regular reloc processing. */
1919 if (lrel)
1920 *lrel = rel;
1921 return 0;
1922 }
1923
1924 symval = (h->root.u.def.value
1925 + h->root.u.def.section->output_section->vma
1926 + h->root.u.def.section->output_offset);
1927
1928 symval += rel->r_addend;
1929 }
1930
6ff71e76
NC		 1931 r_type = ELF32_R_TYPE (rel->r_info);
1932 switch (r_type)
9cea966c
DD		 1933 {
1934 case R_RL78_SYM:
983cdaec
AM		 1935 (void) rl78_compute_complex_reloc (r_type, symval, input_section,
1936 NULL, NULL);
9cea966c
DD		 1937 break;
1938
6ff71e76 1939 case R_RL78_OPromtop:
1a72702b 1940 symval = get_romstart (info, input_bfd, input_section, rel->r_offset);
983cdaec
AM		 1941 (void) rl78_compute_complex_reloc (r_type, symval, input_section,
1942 NULL, NULL);
9cea966c
DD		 1943 break;
1944
6ff71e76 1945 case R_RL78_OPramtop:
1a72702b 1946 symval = get_ramstart (info, input_bfd, input_section, rel->r_offset);
983cdaec
AM		 1947 (void) rl78_compute_complex_reloc (r_type, symval, input_section,
1948 NULL, NULL);
9cea966c
DD		 1949 break;
1950
6ff71e76
NC		 1951 case R_RL78_OPneg:
1952 case R_RL78_OPadd:
9cea966c 1953 case R_RL78_OPsub:
9cea966c 1954 case R_RL78_OPmul:
9cea966c 1955 case R_RL78_OPdiv:
9cea966c 1956 case R_RL78_OPshla:
9cea966c 1957 case R_RL78_OPshra:
9cea966c 1958 case R_RL78_OPsctsize:
9cea966c 1959 case R_RL78_OPscttop:
9cea966c 1960 case R_RL78_OPand:
9cea966c 1961 case R_RL78_OPor:
9cea966c 1962 case R_RL78_OPxor:
9cea966c 1963 case R_RL78_OPnot:
9cea966c 1964 case R_RL78_OPmod:
983cdaec
AM		 1965 (void) rl78_compute_complex_reloc (r_type, 0, input_section,
1966 NULL, NULL);
9cea966c
DD		 1967 break;
1968
1969 case R_RL78_DIR16UL:
1970 case R_RL78_DIR8UL:
1971 case R_RL78_ABS16UL:
1972 case R_RL78_ABS8UL:
9cea966c 1973 *scale = 4;
6ff71e76 1974 goto reloc_computes_value;
9cea966c
DD		 1975
1976 case R_RL78_DIR16UW:
1977 case R_RL78_DIR8UW:
1978 case R_RL78_ABS16UW:
1979 case R_RL78_ABS8UW:
9cea966c 1980 *scale = 2;
6ff71e76 1981 goto reloc_computes_value;
1b786873 1982
9cea966c 1983 default:
6ff71e76 1984 reloc_computes_value:
983cdaec
AM		 1985 symval = rl78_compute_complex_reloc (r_type, symval, input_section,
1986 NULL, NULL);
1a0670f3 1987 /* Fall through. */
e896287c
DD		 1988 case R_RL78_DIR32:
1989 case R_RL78_DIR24S:
1990 case R_RL78_DIR16:
1991 case R_RL78_DIR16U:
1992 case R_RL78_DIR16S:
1993 case R_RL78_DIR24S_PCREL:
1994 case R_RL78_DIR16S_PCREL:
1995 case R_RL78_DIR8S_PCREL:
9cea966c
DD		 1996 if (lrel)
1997 *lrel = rel;
1998 return symval;
1999 }
2000
2001 rel ++;
2002 }
2003}
2004
bd38246a 2005const struct {
9cea966c
DD		 2006 int prefix; /* or -1 for "no prefix" */
2007 int insn; /* or -1 for "end of list" */
2008 int insn_for_saddr; /* or -1 for "no alternative" */
2009 int insn_for_sfr; /* or -1 for "no alternative" */
2010} relax_addr16[] = {
2011 { -1, 0x02, 0x06, -1 }, /* ADDW AX, !addr16 */
2012 { -1, 0x22, 0x26, -1 }, /* SUBW AX, !addr16 */
2013 { -1, 0x42, 0x46, -1 }, /* CMPW AX, !addr16 */
2014 { -1, 0x40, 0x4a, -1 }, /* CMP !addr16, #byte */
2015
2016 { -1, 0x0f, 0x0b, -1 }, /* ADD A, !addr16 */
2017 { -1, 0x1f, 0x1b, -1 }, /* ADDC A, !addr16 */
2018 { -1, 0x2f, 0x2b, -1 }, /* SUB A, !addr16 */
2019 { -1, 0x3f, 0x3b, -1 }, /* SUBC A, !addr16 */
2020 { -1, 0x4f, 0x4b, -1 }, /* CMP A, !addr16 */
2021 { -1, 0x5f, 0x5b, -1 }, /* AND A, !addr16 */
2022 { -1, 0x6f, 0x6b, -1 }, /* OR A, !addr16 */
2023 { -1, 0x7f, 0x7b, -1 }, /* XOR A, !addr16 */
2024
2025 { -1, 0x8f, 0x8d, 0x8e }, /* MOV A, !addr16 */
2026 { -1, 0x9f, 0x9d, 0x9e }, /* MOV !addr16, A */
2027 { -1, 0xaf, 0xad, 0xae }, /* MOVW AX, !addr16 */
2028 { -1, 0xbf, 0xbd, 0xbe }, /* MOVW !addr16, AX */
2029 { -1, 0xcf, 0xcd, 0xce }, /* MOVW !addr16, #word */
2030
2031 { -1, 0xa0, 0xa4, -1 }, /* INC !addr16 */
2032 { -1, 0xa2, 0xa6, -1 }, /* INCW !addr16 */
2033 { -1, 0xb0, 0xb4, -1 }, /* DEC !addr16 */
2034 { -1, 0xb2, 0xb6, -1 }, /* DECW !addr16 */
2035
2036 { -1, 0xd5, 0xd4, -1 }, /* CMP0 !addr16 */
2037 { -1, 0xe5, 0xe4, -1 }, /* ONEB !addr16 */
2038 { -1, 0xf5, 0xf4, -1 }, /* CLRB !addr16 */
2039
2040 { -1, 0xd9, 0xd8, -1 }, /* MOV X, !addr16 */
2041 { -1, 0xe9, 0xe8, -1 }, /* MOV B, !addr16 */
2042 { -1, 0xf9, 0xf8, -1 }, /* MOV C, !addr16 */
2043 { -1, 0xdb, 0xda, -1 }, /* MOVW BC, !addr16 */
2044 { -1, 0xeb, 0xea, -1 }, /* MOVW DE, !addr16 */
2045 { -1, 0xfb, 0xfa, -1 }, /* MOVW HL, !addr16 */
2046
2047 { 0x61, 0xaa, 0xa8, -1 }, /* XCH A, !addr16 */
2048
2049 { 0x71, 0x00, 0x02, 0x0a }, /* SET1 !addr16.0 */
2050 { 0x71, 0x10, 0x12, 0x1a }, /* SET1 !addr16.0 */
2051 { 0x71, 0x20, 0x22, 0x2a }, /* SET1 !addr16.0 */
2052 { 0x71, 0x30, 0x32, 0x3a }, /* SET1 !addr16.0 */
2053 { 0x71, 0x40, 0x42, 0x4a }, /* SET1 !addr16.0 */
2054 { 0x71, 0x50, 0x52, 0x5a }, /* SET1 !addr16.0 */
2055 { 0x71, 0x60, 0x62, 0x6a }, /* SET1 !addr16.0 */
2056 { 0x71, 0x70, 0x72, 0x7a }, /* SET1 !addr16.0 */
2057
2058 { 0x71, 0x08, 0x03, 0x0b }, /* CLR1 !addr16.0 */
2059 { 0x71, 0x18, 0x13, 0x1b }, /* CLR1 !addr16.0 */
2060 { 0x71, 0x28, 0x23, 0x2b }, /* CLR1 !addr16.0 */
2061 { 0x71, 0x38, 0x33, 0x3b }, /* CLR1 !addr16.0 */
2062 { 0x71, 0x48, 0x43, 0x4b }, /* CLR1 !addr16.0 */
2063 { 0x71, 0x58, 0x53, 0x5b }, /* CLR1 !addr16.0 */
2064 { 0x71, 0x68, 0x63, 0x6b }, /* CLR1 !addr16.0 */
2065 { 0x71, 0x78, 0x73, 0x7b }, /* CLR1 !addr16.0 */
68ffbac6 2066
9cea966c
DD		 2067 { -1, -1, -1, -1 }
2068};
2069
2070/* Relax one section. */
2071
0a1b45a2
AM		 2072static bool
2073rl78_elf_relax_section (bfd *abfd,
2074 asection *sec,
2075 struct bfd_link_info *link_info,
2076 bool *again)
99c513f6 2077{
9cea966c
DD		 2078 Elf_Internal_Shdr * symtab_hdr;
2079 Elf_Internal_Shdr * shndx_hdr;
2080 Elf_Internal_Rela * internal_relocs;
2081 Elf_Internal_Rela * free_relocs = NULL;
2082 Elf_Internal_Rela * irel;
2083 Elf_Internal_Rela * srel;
2084 Elf_Internal_Rela * irelend;
2085 Elf_Internal_Rela * next_alignment;
07d6d2b8
AM		 2086 bfd_byte * contents = NULL;
2087 bfd_byte * free_contents = NULL;
9cea966c
DD		 2088 Elf_Internal_Sym * intsyms = NULL;
2089 Elf_Internal_Sym * free_intsyms = NULL;
806470a2 2090 bfd_byte * shndx_buf = NULL;
9cea966c 2091 bfd_vma pc;
9cea966c
DD		 2092 bfd_vma symval ATTRIBUTE_UNUSED = 0;
2093 int pcrel ATTRIBUTE_UNUSED = 0;
2094 int code ATTRIBUTE_UNUSED = 0;
2095 int section_alignment_glue;
2096 int scale;
2097
99c513f6
DD		 2098 if (abfd == elf_hash_table (link_info)->dynobj
2099 && strcmp (sec->name, ".plt") == 0)
2100 return rl78_elf_relax_plt_section (abfd, sec, link_info, again);
2101
2102 /* Assume nothing changes. */
0a1b45a2 2103 *again = false;
9cea966c
DD		 2104
2105 /* We don't have to do anything for a relocatable link, if
2106 this section does not have relocs, or if this is not a
2107 code section. */
0e1862bb 2108 if (bfd_link_relocatable (link_info)
9cea966c 2109 || sec->reloc_count == 0
3a574cce
AM		 2110 || (sec->flags & SEC_RELOC) == 0
2111 || (sec->flags & SEC_HAS_CONTENTS) == 0
9cea966c 2112 || (sec->flags & SEC_CODE) == 0)
0a1b45a2 2113 return true;
9cea966c 2114
6a40cf0c
NC		 2115 symtab_hdr = & elf_symtab_hdr (abfd);
2116 if (elf_symtab_shndx_list (abfd))
2117 shndx_hdr = & elf_symtab_shndx_list (abfd)->hdr;
2118 else
2119 shndx_hdr = NULL;
9cea966c 2120
9cea966c
DD		 2121 /* Get the section contents. */
2122 if (elf_section_data (sec)->this_hdr.contents != NULL)
2123 contents = elf_section_data (sec)->this_hdr.contents;
2124 /* Go get them off disk. */
2125 else
2126 {
2127 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2128 goto error_return;
2129 elf_section_data (sec)->this_hdr.contents = contents;
2130 }
2131
2132 /* Read this BFD's symbols. */
2133 /* Get cached copy if it exists. */
2134 if (symtab_hdr->contents != NULL)
2135 intsyms = (Elf_Internal_Sym *) symtab_hdr->contents;
2136 else
2137 {
2138 intsyms = bfd_elf_get_elf_syms (abfd, symtab_hdr, symtab_hdr->sh_info, 0, NULL, NULL, NULL);
2139 symtab_hdr->contents = (bfd_byte *) intsyms;
2140 }
2141
6a40cf0c 2142 if (shndx_hdr && shndx_hdr->sh_size != 0)
9cea966c 2143 {
1f4361a7 2144 size_t amt;
9cea966c 2145
1f4361a7
AM		 2146 if (_bfd_mul_overflow (symtab_hdr->sh_info,
2147 sizeof (Elf_External_Sym_Shndx), &amt))
2148 {
2149 bfd_set_error (bfd_error_no_memory);
2150 goto error_return;
2151 }
2bb3687b 2152 if (bfd_seek (abfd, shndx_hdr->sh_offset, SEEK_SET) != 0)
9cea966c 2153 goto error_return;
2bb3687b
AM		 2154 shndx_buf = _bfd_malloc_and_read (abfd, amt, amt);
2155 if (shndx_buf == NULL)
9cea966c 2156 goto error_return;
806470a2 2157 shndx_hdr->contents = shndx_buf;
9cea966c
DD		 2158 }
2159
2160 /* Get a copy of the native relocations. */
2161 internal_relocs = (_bfd_elf_link_read_relocs
2c3fc389 2162 (abfd, sec, NULL, (Elf_Internal_Rela *) NULL,
9cea966c
DD		 2163 link_info->keep_memory));
2164 if (internal_relocs == NULL)
2165 goto error_return;
2166 if (! link_info->keep_memory)
2167 free_relocs = internal_relocs;
2168
2169 /* The RL_ relocs must be just before the operand relocs they go
2170 with, so we must sort them to guarantee this. We use bubblesort
2171 instead of qsort so we can guarantee that relocs with the same
2172 address remain in the same relative order. */
2173 reloc_bubblesort (internal_relocs, sec->reloc_count);
2174
2175 /* Walk through them looking for relaxing opportunities. */
2176 irelend = internal_relocs + sec->reloc_count;
2177
2178
2179 /* This will either be NULL or a pointer to the next alignment
2180 relocation. */
2181 next_alignment = internal_relocs;
9cea966c
DD		 2182
2183 /* We calculate worst case shrinkage caused by alignment directives.
2184 No fool-proof, but better than either ignoring the problem or
2185 doing heavy duty analysis of all the alignment markers in all
2186 input sections. */
2187 section_alignment_glue = 0;
2188 for (irel = internal_relocs; irel < irelend; irel++)
2189 if (ELF32_R_TYPE (irel->r_info) == R_RL78_RH_RELAX
2190 && irel->r_addend & RL78_RELAXA_ALIGN)
2191 {
2192 int this_glue = 1 << (irel->r_addend & RL78_RELAXA_ANUM);
2193
2194 if (section_alignment_glue < this_glue)
2195 section_alignment_glue = this_glue;
2196 }
2197 /* Worst case is all 0..N alignments, in order, causing 2*N-1 byte
2198 shrinkage. */
2199 section_alignment_glue *= 2;
2200
2201 for (irel = internal_relocs; irel < irelend; irel++)
2202 {
2203 unsigned char *insn;
2204 int nrelocs;
2205
2206 /* The insns we care about are all marked with one of these. */
2207 if (ELF32_R_TYPE (irel->r_info) != R_RL78_RH_RELAX)
2208 continue;
2209
2210 if (irel->r_addend & RL78_RELAXA_ALIGN
2211 || next_alignment == internal_relocs)
2212 {
2213 /* When we delete bytes, we need to maintain all the alignments
2214 indicated. In addition, we need to be careful about relaxing
2215 jumps across alignment boundaries - these displacements
2216 *grow* when we delete bytes. For now, don't shrink
2217 displacements across an alignment boundary, just in case.
2218 Note that this only affects relocations to the same
2219 section. */
9cea966c
DD		 2220 next_alignment += 2;
2221 while (next_alignment < irelend
2222 && (ELF32_R_TYPE (next_alignment->r_info) != R_RL78_RH_RELAX
2223 || !(next_alignment->r_addend & RL78_RELAXA_ELIGN)))
2224 next_alignment ++;
2225 if (next_alignment >= irelend || next_alignment->r_offset == 0)
2226 next_alignment = NULL;
2227 }
2228
2229 /* When we hit alignment markers, see if we've shrunk enough
2230 before them to reduce the gap without violating the alignment
2231 requirements. */
2232 if (irel->r_addend & RL78_RELAXA_ALIGN)
2233 {
2234 /* At this point, the next relocation *should* be the ELIGN
2235 end marker. */
2236 Elf_Internal_Rela *erel = irel + 1;
2237 unsigned int alignment, nbytes;
2238
2239 if (ELF32_R_TYPE (erel->r_info) != R_RL78_RH_RELAX)
2240 continue;
2241 if (!(erel->r_addend & RL78_RELAXA_ELIGN))
2242 continue;
2243
2244 alignment = 1 << (irel->r_addend & RL78_RELAXA_ANUM);
2245
2246 if (erel->r_offset - irel->r_offset < alignment)
2247 continue;
2248
2249 nbytes = erel->r_offset - irel->r_offset;
2250 nbytes /= alignment;
2251 nbytes *= alignment;
2252
1740ba0c
NC		 2253 elf32_rl78_relax_delete_bytes (abfd, sec, erel->r_offset - nbytes, nbytes,
2254 next_alignment, erel->r_offset == sec->size);
0a1b45a2 2255 *again = true;
9cea966c
DD		 2256
2257 continue;
2258 }
2259
2260 if (irel->r_addend & RL78_RELAXA_ELIGN)
2261 continue;
2262
2263 insn = contents + irel->r_offset;
2264
2265 nrelocs = irel->r_addend & RL78_RELAXA_RNUM;
2266
2267 /* At this point, we have an insn that is a candidate for linker
2268 relaxation. There are NRELOCS relocs following that may be
2269 relaxed, although each reloc may be made of more than one
2270 reloc entry (such as gp-rel symbols). */
2271
2272 /* Get the value of the symbol referred to by the reloc. Just
07d6d2b8
AM		 2273 in case this is the last reloc in the list, use the RL's
2274 addend to choose between this reloc (no addend) or the next
2275 (yes addend, which means at least one following reloc). */
9cea966c
DD		 2276
2277 /* srel points to the "current" reloction for this insn -
2278 actually the last reloc for a given operand, which is the one
2279 we need to update. We check the relaxations in the same
2280 order that the relocations happen, so we'll just push it
2281 along as we go. */
2282 srel = irel;
2283
2284 pc = sec->output_section->vma + sec->output_offset
2285 + srel->r_offset;
2286
1740ba0c
NC		 2287#define GET_RELOC \
2288 BFD_ASSERT (nrelocs > 0); \
2289 symval = OFFSET_FOR_RELOC (srel, &srel, &scale); \
2290 pcrel = symval - pc + srel->r_addend; \
9cea966c
DD		 2291 nrelocs --;
2292
2293#define SNIPNR(offset, nbytes) \
2294 elf32_rl78_relax_delete_bytes (abfd, sec, (insn - contents) + offset, nbytes, next_alignment, 0);
1740ba0c
NC		 2295
2296#define SNIP(offset, nbytes, newtype) \
07d6d2b8 2297 SNIPNR (offset, nbytes); \
9cea966c
DD		 2298 srel->r_info = ELF32_R_INFO (ELF32_R_SYM (srel->r_info), newtype)
2299
2300 /* The order of these bit tests must match the order that the
2301 relocs appear in. Since we sorted those by offset, we can
2302 predict them. */
2303
2304 /*----------------------------------------------------------------------*/
2305 /* EF ad BR $rel8 pcrel
2306 ED al ah BR !abs16 abs
2307 EE al ah BR $!rel16 pcrel
2308 EC al ah as BR !!abs20 abs
2309
2310 FD al ah CALL !abs16 abs
2311 FE al ah CALL $!rel16 pcrel
2312 FC al ah as CALL !!abs20 abs
2313
2314 DC ad BC $rel8
2315 DE ad BNC $rel8
2316 DD ad BZ $rel8
2317 DF ad BNZ $rel8
2318 61 C3 ad BH $rel8
2319 61 D3 ad BNH $rel8
2320 61 C8 EF ad SKC ; BR $rel8
2321 61 D8 EF ad SKNC ; BR $rel8
2322 61 E8 EF ad SKZ ; BR $rel8
2323 61 F8 EF ad SKNZ ; BR $rel8
2324 61 E3 EF ad SKH ; BR $rel8
2325 61 F3 EF ad SKNH ; BR $rel8
2326 */
2327
32e79d39 2328 if ((irel->r_addend & RL78_RELAXA_MASK) == RL78_RELAXA_BRA)
9cea966c 2329 {
1122dc88
DD		 2330 /* SKIP opcodes that skip non-branches will have a relax tag
2331 but no corresponding symbol to relax against; we just
2332 skip those. */
2333 if (irel->r_addend & RL78_RELAXA_RNUM)
2334 {
2335 GET_RELOC;
2336 }
9cea966c
DD		 2337
2338 switch (insn[0])
2339 {
e896287c
DD		 2340 case 0xdc: /* BC */
2341 case 0xdd: /* BZ */
2342 case 0xde: /* BNC */
2343 case 0xdf: /* BNZ */
2344 if (insn[1] == 0x03 && insn[2] == 0xee /* BR */
2345 && (srel->r_offset - irel->r_offset) > 1) /* a B<c> without its own reloc */
2346 {
2347 /* This is a "long" conditional as generated by gas:
2348 DC 03 EE ad.dr */
2349 if (pcrel < 127
2350 && pcrel > -127)
2351 {
2352 insn[0] ^= 0x02; /* invert conditional */
2353 SNIPNR (4, 1);
2354 SNIP (1, 2, R_RL78_DIR8S_PCREL);
2355 insn[1] = pcrel;
0a1b45a2 2356 *again = true;
e896287c
DD		 2357 }
2358 }
2359 break;
2360
9cea966c
DD		 2361 case 0xec: /* BR !!abs20 */
2362
2363 if (pcrel < 127
2364 && pcrel > -127)
2365 {
2366 insn[0] = 0xef;
2367 insn[1] = pcrel;
2368 SNIP (2, 2, R_RL78_DIR8S_PCREL);
0a1b45a2 2369 *again = true;
9cea966c
DD		 2370 }
2371 else if (symval < 65536)
2372 {
2373 insn[0] = 0xed;
2374 insn[1] = symval & 0xff;
2375 insn[2] = symval >> 8;
e896287c 2376 SNIP (2, 1, R_RL78_DIR16U);
0a1b45a2 2377 *again = true;
9cea966c
DD		 2378 }
2379 else if (pcrel < 32767
2380 && pcrel > -32767)
2381 {
2382 insn[0] = 0xee;
2383 insn[1] = pcrel & 0xff;
2384 insn[2] = pcrel >> 8;
2385 SNIP (2, 1, R_RL78_DIR16S_PCREL);
0a1b45a2 2386 *again = true;
9cea966c
DD		 2387 }
2388 break;
2389
2390 case 0xee: /* BR $!pcrel16 */
2391 case 0xed: /* BR $!abs16 */
2392 if (pcrel < 127
2393 && pcrel > -127)
2394 {
2395 insn[0] = 0xef;
2396 insn[1] = pcrel;
2397 SNIP (2, 1, R_RL78_DIR8S_PCREL);
0a1b45a2 2398 *again = true;
9cea966c
DD		 2399 }
2400 break;
2401
2402 case 0xfc: /* CALL !!abs20 */
2403 if (symval < 65536)
2404 {
2405 insn[0] = 0xfd;
2406 insn[1] = symval & 0xff;
2407 insn[2] = symval >> 8;
e896287c 2408 SNIP (2, 1, R_RL78_DIR16U);
0a1b45a2 2409 *again = true;
9cea966c
DD		 2410 }
2411 else if (pcrel < 32767
2412 && pcrel > -32767)
2413 {
2414 insn[0] = 0xfe;
2415 insn[1] = pcrel & 0xff;
2416 insn[2] = pcrel >> 8;
2417 SNIP (2, 1, R_RL78_DIR16S_PCREL);
0a1b45a2 2418 *again = true;
9cea966c
DD		 2419 }
2420 break;
2421
2422 case 0x61: /* PREFIX */
2423 /* For SKIP/BR, we change the BR opcode and delete the
2424 SKIP. That way, we don't have to find and change the
2425 relocation for the BR. */
1122dc88
DD		 2426 /* Note that, for the case where we're skipping some
2427 other insn, we have no "other" reloc but that's safe
2428 here anyway. */
9cea966c
DD		 2429 switch (insn[1])
2430 {
e896287c
DD		 2431 case 0xd3: /* BNH */
2432 case 0xc3: /* BH */
2433 if (insn[2] == 0x03 && insn[3] == 0xee
2434 && (srel->r_offset - irel->r_offset) > 2) /* a B<c> without its own reloc */
2435 {
2436 /* Another long branch by gas:
2437 61 D3 03 EE ad.dr */
2438 if (pcrel < 127
2439 && pcrel > -127)
2440 {
2441 insn[1] ^= 0x10; /* invert conditional */
2442 SNIPNR (5, 1);
2443 SNIP (2, 2, R_RL78_DIR8S_PCREL);
2444 insn[2] = pcrel;
0a1b45a2 2445 *again = true;
e896287c
DD		 2446 }
2447 }
2448 break;
2449
9cea966c
DD		 2450 case 0xc8: /* SKC */
2451 if (insn[2] == 0xef)
2452 {
2453 insn[2] = 0xde; /* BNC */
2454 SNIPNR (0, 2);
2455 }
2456 break;
2457
2458 case 0xd8: /* SKNC */
2459 if (insn[2] == 0xef)
2460 {
2461 insn[2] = 0xdc; /* BC */
2462 SNIPNR (0, 2);
2463 }
2464 break;
2465
2466 case 0xe8: /* SKZ */
2467 if (insn[2] == 0xef)
2468 {
2469 insn[2] = 0xdf; /* BNZ */
2470 SNIPNR (0, 2);
2471 }
2472 break;
2473
2474 case 0xf8: /* SKNZ */
2475 if (insn[2] == 0xef)
2476 {
2477 insn[2] = 0xdd; /* BZ */
2478 SNIPNR (0, 2);
2479 }
2480 break;
2481
2482 case 0xe3: /* SKH */
2483 if (insn[2] == 0xef)
2484 {
2485 insn[2] = 0xd3; /* BNH */
2486 SNIPNR (1, 1); /* we reuse the 0x61 prefix from the SKH */
2487 }
2488 break;
2489
2490 case 0xf3: /* SKNH */
2491 if (insn[2] == 0xef)
2492 {
2493 insn[2] = 0xc3; /* BH */
2494 SNIPNR (1, 1); /* we reuse the 0x61 prefix from the SKH */
2495 }
2496 break;
2497 }
2498 break;
2499 }
9cea966c
DD		 2500 }
2501
71eef2bd 2502 if ((irel->r_addend & RL78_RELAXA_MASK) == RL78_RELAXA_ADDR16
07d6d2b8 2503 && nrelocs > 0)
9cea966c
DD		 2504 {
2505 /*----------------------------------------------------------------------*/
2506 /* Some insns have both a 16-bit address operand and an 8-bit
2507 variant if the address is within a special range:
2508
2509 Address 16-bit operand SADDR range SFR range
2510 FFF00-FFFFF 0xff00-0xffff 0x00-0xff
07d6d2b8 2511 FFE20-FFF1F 0xfe20-0xff1f 0x00-0xff
9cea966c
DD		 2512
2513 The RELAX_ADDR16[] array has the insn encodings for the
2514 16-bit operand version, as well as the SFR and SADDR
2515 variants. We only need to replace the encodings and
2516 adjust the operand.
2517
2518 Note: we intentionally do not attempt to decode and skip
2519 any ES: prefix, as adding ES: means the addr16 (likely)
2520 no longer points to saddr/sfr space.
2521 */
2522
2523 int is_sfr;
2524 int is_saddr;
2525 int idx;
2526 int poff;
2527
2528 GET_RELOC;
2529
9cea966c
DD		 2530 if (0xffe20 <= symval && symval <= 0xfffff)
2531 {
2532
2533 is_saddr = (0xffe20 <= symval && symval <= 0xfff1f);
2534 is_sfr = (0xfff00 <= symval && symval <= 0xfffff);
2535
2536 for (idx = 0; relax_addr16[idx].insn != -1; idx ++)
2537 {
2538 if (relax_addr16[idx].prefix != -1
2539 && insn[0] == relax_addr16[idx].prefix
2540 && insn[1] == relax_addr16[idx].insn)
2541 {
2542 poff = 1;
2543 }
2544 else if (relax_addr16[idx].prefix == -1
2545 && insn[0] == relax_addr16[idx].insn)
2546 {
2547 poff = 0;
2548 }
2549 else
2550 continue;
2551
2552 /* We have a matched insn, and poff is 0 or 1 depending
2553 on the base pattern size. */
2554
2555 if (is_sfr && relax_addr16[idx].insn_for_sfr != -1)
2556 {
2557 insn[poff] = relax_addr16[idx].insn_for_sfr;
2558 SNIP (poff+2, 1, R_RL78_RH_SFR);
9cea966c
DD		 2559 }
2560
2561 else if (is_saddr && relax_addr16[idx].insn_for_saddr != -1)
2562 {
2563 insn[poff] = relax_addr16[idx].insn_for_saddr;
2564 SNIP (poff+2, 1, R_RL78_RH_SADDR);
9cea966c 2565 }
9cea966c
DD		 2566 }
2567 }
2568 }
9cea966c 2569 /*----------------------------------------------------------------------*/
9cea966c
DD		 2570 }
2571
0a1b45a2 2572 return true;
9cea966c
DD		 2573
2574 error_return:
c9594989
AM		 2575 free (free_relocs);
2576 free (free_contents);
9cea966c
DD		 2577
2578 if (shndx_buf != NULL)
2579 {
2580 shndx_hdr->contents = NULL;
2581 free (shndx_buf);
2582 }
2583
c9594989 2584 free (free_intsyms);
9cea966c 2585
0a1b45a2 2586 return true;
99c513f6
DD		 2587}
2588
2589\f
2590
2591#define ELF_ARCH bfd_arch_rl78
2592#define ELF_MACHINE_CODE EM_RL78
2593#define ELF_MAXPAGESIZE 0x1000
2594
6d00b590 2595#define TARGET_LITTLE_SYM rl78_elf32_vec
99c513f6
DD		 2596#define TARGET_LITTLE_NAME "elf32-rl78"
2597
2598#define elf_info_to_howto_rel NULL
2599#define elf_info_to_howto rl78_info_to_howto_rela
2600#define elf_backend_object_p rl78_elf_object_p
2601#define elf_backend_relocate_section rl78_elf_relocate_section
07d6d2b8 2602#define elf_symbol_leading_char ('_')
99c513f6
DD		 2603#define elf_backend_can_gc_sections 1
2604
2605#define bfd_elf32_bfd_reloc_type_lookup rl78_reloc_type_lookup
2606#define bfd_elf32_bfd_reloc_name_lookup rl78_reloc_name_lookup
2607#define bfd_elf32_bfd_set_private_flags rl78_elf_set_private_flags
2608#define bfd_elf32_bfd_merge_private_bfd_data rl78_elf_merge_private_bfd_data
2609#define bfd_elf32_bfd_print_private_bfd_data rl78_elf_print_private_bfd_data
2610
2611#define bfd_elf32_bfd_relax_section rl78_elf_relax_section
07d6d2b8 2612#define elf_backend_check_relocs rl78_elf_check_relocs
af969b14
AM		 2613#define elf_backend_early_size_sections \
2614 rl78_elf_early_size_sections
99c513f6
DD		 2615#define elf_backend_finish_dynamic_sections \
2616 rl78_elf_finish_dynamic_sections
2617
2618#include "elf32-target.h"
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