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[gdb/exp] Fix cast handling for indirection
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1; Toshiba MeP FMAX Coprocessor description. -*- Scheme -*-
2; Copyright 2011 Free Software Foundation, Inc.
3;
4; Contributed by Red Hat Inc;
5;
6; This file is part of the GNU Binutils.
7;
8; This program is free software; you can redistribute it and/or modify
9; it under the terms of the GNU General Public License as published by
10; the Free Software Foundation; either version 3 of the License, or
11; (at your option) any later version.
12;
13; This program is distributed in the hope that it will be useful,
14; but WITHOUT ANY WARRANTY; without even the implied warranty of
15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16; GNU General Public License for more details.
17;
18; You should have received a copy of the GNU General Public License
19; along with this program; if not, write to the Free Software
20; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21; MA 02110-1301, USA.
22
23;------------------------------------------------------------------------------
24; MeP-Integrator will redefine the isa pmacros below to allow the bit widths
25; specified below for each ME_MODULE using this coprocessor.
26; This coprocessor requires only the 32 bit insns in the core.
27;------------------------------------------------------------------------------
28; begin-isas
29(define-pmacro fmax-core-isa () (ISA ext_core2))
30(define-pmacro all-fmax-isas () (ISA ext_core2))
31; end-isas
32
33;******************************************************************************
34; ifields
35;------------------------------------------------------------------------------
36; opcodes
37(dnf f-fmax-0-4 "opcode" (all-fmax-isas) 0 4)
38(dnf f-fmax-4-4 "opcode" (all-fmax-isas) 4 4)
39(dnf f-fmax-8-4 "opcode" (all-fmax-isas) 8 4)
40(dnf f-fmax-12-4 "opcode" (all-fmax-isas) 12 4)
41(dnf f-fmax-16-4 "opcode" (all-fmax-isas) 16 4)
42(dnf f-fmax-20-4 "opcode" (all-fmax-isas) 20 4)
43(dnf f-fmax-24-4 "opcode" (all-fmax-isas) 24 4)
44(dnf f-fmax-28-1 "opcode" (all-fmax-isas) 28 1)
45(dnf f-fmax-29-1 "opcode" (all-fmax-isas) 29 1)
46(dnf f-fmax-30-1 "opcode" (all-fmax-isas) 30 1)
47(dnf f-fmax-31-1 "opcode" (all-fmax-isas) 31 1)
48
49;------------------------------------------------------------------------------
50; FR registers
51(define-multi-ifield
52 (name f-fmax-frd)
53 (comment "FRd register")
54 (attrs all-fmax-isas)
55 (mode UINT)
56 (subfields f-fmax-28-1 f-fmax-4-4)
57 (insert (sequence ()
58 (set (ifield f-fmax-4-4) (and (ifield f-fmax-frd) #xf))
59 (set (ifield f-fmax-28-1) (srl (ifield f-fmax-frd) 4))))
60 (extract (set (ifield f-fmax-frd)
61 (or (sll (ifield f-fmax-28-1) 4) (ifield f-fmax-4-4))))
62)
63(define-multi-ifield
64 (name f-fmax-frn)
65 (comment "FRn register")
66 (attrs all-fmax-isas)
67 (mode UINT)
68 (subfields f-fmax-29-1 f-fmax-20-4)
69 (insert (sequence ()
70 (set (ifield f-fmax-20-4) (and (ifield f-fmax-frn) #xf))
71 (set (ifield f-fmax-29-1) (srl (ifield f-fmax-frn) 4))))
72 (extract (set (ifield f-fmax-frn)
73 (or (sll (ifield f-fmax-29-1) 4) (ifield f-fmax-20-4))))
74)
75(define-multi-ifield
76 (name f-fmax-frm)
77 (comment "FRm register")
78 (attrs all-fmax-isas)
79 (mode UINT)
80 (subfields f-fmax-30-1 f-fmax-24-4)
81 (insert (sequence ()
82 (set (ifield f-fmax-24-4) (and (ifield f-fmax-frm) #xf))
83 (set (ifield f-fmax-30-1) (srl (ifield f-fmax-frm) 4))))
84 (extract (set (ifield f-fmax-frm)
85 (or (sll (ifield f-fmax-30-1) 4) (ifield f-fmax-24-4))))
86)
87
88;------------------------------------------------------------------------------
89; Core General registers
90(dnf f-fmax-rm "opcode" (all-fmax-isas) 8 4)
91
92;------------------------------------------------------------------------------
93; Condition opcodes enum
94(define-normal-insn-enum fmax-cond "condition opcode enum" (all-fmax-isas) FMAX_ f-fmax-8-4
95 ("f" "u" "e" "ue" "l" "ul" "le" "ule"
96 "fi" "ui" "ei" "uei" "li" "uli" "lei" "ulei")
97)
98
99;******************************************************************************
100; Hardware
101;------------------------------------------------------------------------------
102; FR registers
103
104; Given a coprocessor register number N, expand to a
105; name/index pair: ($frN N)
106(define-pmacro (-fmax-fr-reg-pair n) ((.sym "fr" n) n))
107(define-pmacro (-fmax-cr-reg-pair n) ((.sym "c" n) n))
108
109; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
110; GDB will use the hardware table generated from this declaration. The operands use h-cr
111; from mep-core.cpu so that SID's semantic trace will be consistent between
112; the core and the coprocessor but use parse/print handlers which reference the hardware table
113; generated from this declarations
114(define-hardware
115 (name h-cr-fmax)
116 (comment "Floating point registers")
117 (attrs all-fmax-isas VIRTUAL IS_FLOAT)
118 (type register SF (32))
119 (indices keyword "$"
120 (.splice (.unsplice (.map -fmax-fr-reg-pair (.iota 32)))
121 (.unsplice (.map -fmax-cr-reg-pair (.iota 32))))
122 )
123 (get (index) (c-call SF "fmax_fr_get_handler" index))
124 (set (index newval) (c-call VOID "fmax_fr_set_handler" index newval))
125)
126
127;------------------------------------------------------------------------------
128; Control registers
129; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
130; GDB will use the hardware table generated from this declaration. The operands use h-ccr
131; from mep-core.cpu so that SID's semantic trace will be consistent between
132; the core and the coprocessor but use parse/print handlers which reference the hardware table
133; generated from this declarations
134(define-hardware
135 (name h-ccr-fmax)
136 (comment "Coprocessor Identifier and Revision Register")
137 (attrs all-fmax-isas VIRTUAL)
138 (type register USI (16))
139 (indices keyword "$" (
140 ("cirr" 0) ("fcr0" 0) ("ccr0" 0)
141 ("cbcr" 1) ("fcr1" 1) ("ccr1" 1)
142 ("cerr" 15) ("fcr15" 15) ("ccr15" 15)
143 )
144 )
145 (set (index newval) (c-call VOID "h_ccr_set" index newval))
146 (get (index) (c-call SI "h_ccr_get" index))
147)
148
149;------------------------------------------------------------------------------
150; Misc
151(define-hardware
152 (name h-fmax-compare-i-p)
153 (comment "flag")
154 (attrs all-fmax-isas)
155 (type register USI)
156)
157
158;******************************************************************************
159; Operands
160;------------------------------------------------------------------------------
161; FR Registers
162(define-full-operand fmax-FRd "FRd" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ())
163(define-full-operand fmax-FRn "FRn" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ())
164(define-full-operand fmax-FRm "FRm" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frm ((parse "fmax_cr") (print "fmax_cr")) () ())
165
166(define-full-operand fmax-FRd-int "FRd as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ())
167(define-full-operand fmax-FRn-int "FRn as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ())
168
169;------------------------------------------------------------------------------
170; Control registers
171(define-full-operand fmax-CCRn "CCRn" (all-fmax-isas (CDATA REGNUM)) h-ccr DFLT f-fmax-4-4 ((parse "fmax_ccr") (print "fmax_ccr")) () ())
172
173(dnop fmax-CIRR "CIRR" (all-fmax-isas SEM-ONLY) h-ccr 0)
174(dnop fmax-CBCR "CBCR" (all-fmax-isas SEM-ONLY) h-ccr 1)
175(dnop fmax-CERR "CERR" (all-fmax-isas SEM-ONLY) h-ccr 15)
176
177;------------------------------------------------------------------------------
178; Core General Registers
179(dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm)
180
181;------------------------------------------------------------------------------
182; misc
183(dnop fmax-Compare-i-p "flag" (all-fmax-isas SEM-ONLY) h-fmax-compare-i-p f-nil)
184
185;******************************************************************************
186; Instructions
187;------------------------------------------------------------------------------
188; Binary Arithmetic
189(define-pmacro (fmax-binary-arith op opc sem)
190 (dni op
191 (.str op " FRd,FRn,FRm")
192 (all-fmax-isas MAY_TRAP)
193 (.str op " ${fmax-FRd},${fmax-FRn},${fmax-FRm}")
194 (+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7) (f-fmax-16-4 0)
195 fmax-FRn fmax-FRm (f-fmax-31-1 0))
196 sem
197 ()
198 )
199)
200
201(fmax-binary-arith fadds #x0 (set fmax-FRd (add fmax-FRn fmax-FRm)))
202(fmax-binary-arith fsubs #x1 (set fmax-FRd (sub fmax-FRn fmax-FRm)))
203(fmax-binary-arith fmuls #x2 (set fmax-FRd (mul fmax-FRn fmax-FRm)))
204(fmax-binary-arith fdivs #x3 (set fmax-FRd (div fmax-FRn fmax-FRm)))
205
206;------------------------------------------------------------------------------
207; Unary Arithmetic
208(define-pmacro (fmax-unary-arith op opc sem)
209 (dni op
210 (.str op " FRd,FRn")
211 (all-fmax-isas MAY_TRAP)
212 (.str op " ${fmax-FRd},${fmax-FRn}")
213 (+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7)
214 (f-fmax-16-4 0) fmax-FRn (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
215 sem
216 ()
217 )
218)
219
220(fmax-unary-arith fsqrts #x4 (set fmax-FRd (sqrt fmax-FRn)))
221(fmax-unary-arith fabss #x5 (set fmax-FRd (abs fmax-FRn)))
222(fmax-unary-arith fnegs #x7 (set fmax-FRd (neg fmax-FRn)))
223(fmax-unary-arith fmovs #x6 (set fmax-FRd fmax-FRn))
224
225;------------------------------------------------------------------------------
226; Conversions
227(define-pmacro (fmax-conv op opc1 opc2 opnd1 opnd2 sem)
228 (dni op
229 (.str op " FRd,FRn")
230 (all-fmax-isas MAY_TRAP)
231 (.str op " ${" opnd1 "},${" opnd2 "}")
232 (+ (f-fmax-0-4 #xF) opnd1 (f-fmax-8-4 opc1) (f-fmax-12-4 #x7)
233 (f-fmax-16-4 opc2) opnd2 (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
234 sem
235 ()
236 )
237)
238
239(fmax-conv froundws #xC #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_froundws" fmax-FRn)))
240(fmax-conv ftruncws #xD #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ftruncws" fmax-FRn)))
241(fmax-conv fceilws #xE #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fceilws" fmax-FRn)))
242(fmax-conv ffloorws #xF #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ffloorws" fmax-FRn)))
243(fmax-conv fcvtws #x4 #x1 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fcvtws" fmax-FRn)))
244(fmax-conv fcvtsw #x0 #x9 fmax-FRd fmax-FRn-int (set fmax-FRd (float SF FPCONV-DEFAULT fmax-FRn-int)))
245
246;------------------------------------------------------------------------------
247; Comparisons
248;
249; Comparison with no exceptions
250(define-pmacro (fmax-f-sem x y) (andif (gt x y) (lt x y))) ; do this to get exception detection
251(define-pmacro (fmax-u-sem x y) (not (orif (lt x y) (orif (eq x y) (gt x y)))))
252(define-pmacro (fmax-e-sem x y) (eq x y))
253(define-pmacro (fmax-ue-sem x y) (not (orif (lt x y) (gt x y))))
254(define-pmacro (fmax-l-sem x y) (lt x y))
255(define-pmacro (fmax-ul-sem x y) (not (orif (gt x y) (eq x y))))
256(define-pmacro (fmax-le-sem x y) (orif (lt x y) (eq x y)))
257(define-pmacro (fmax-ule-sem x y) (not (gt x y)))
258
259(define-pmacro (fmax-comp cond suffix exceptions)
260 (dni (.sym fcmp cond suffix s)
261 (.str "fcmp" cond suffix "s FRn,FRm")
262 ;; Even though the instruction doesn't really trap if EXCEPTIONS
263 ;; is zero, we don't want gcc to put it in a repeat or erepeat
264 ;; block because of the hazards between fcmp instructions and
265 ;; anything that reads CBCR.
266 (all-fmax-isas MAY_TRAP)
267 (.str "fcmp" cond suffix "s ${fmax-FRn},${fmax-FRm}")
268 (+ (f-fmax-0-4 #xF) (f-fmax-4-4 0) (.sym FMAX_ cond suffix) (f-fmax-12-4 #x7)
269 (f-fmax-16-4 #x2) (f-fmax-28-1 0) fmax-FRn fmax-FRm (f-fmax-31-1 0))
270 (sequence ()
271 (set fmax-Compare-i-p exceptions)
272 (set fmax-CBCR ((.sym fmax- cond -sem) fmax-FRn fmax-FRm))
273 (set fmax-Compare-i-p 0)
274 )
275 ()
276 )
277)
278
279; Comparison with no exceptions
280(fmax-comp f "" 0)
281(fmax-comp u "" 0)
282(fmax-comp e "" 0)
283(fmax-comp ue "" 0)
284(fmax-comp l "" 0)
285(fmax-comp ul "" 0)
286(fmax-comp le "" 0)
287(fmax-comp ule "" 0)
288
289; Comparison with exceptions
290(fmax-comp f i 1)
291(fmax-comp u i 1)
292(fmax-comp e i 1)
293(fmax-comp ue i 1)
294(fmax-comp l i 1)
295(fmax-comp ul i 1)
296(fmax-comp le i 1)
297(fmax-comp ule i 1)
298
299;------------------------------------------------------------------------------
300; Move to/from core registers
301(dni cmov-frn-rm
302 "cmov FRn,Rm"
303 (all-fmax-isas (INTRINSIC "cmov1"))
304 "cmov ${fmax-FRd-int},${fmax-Rm}"
305 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
306 (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
307 (f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
308 (set fmax-FRd-int fmax-Rm)
309 ()
310)
311(dni cmov-rm-frn
312 "cmov Rm,FRn"
313 (all-fmax-isas (INTRINSIC "cmov2"))
314 "cmov ${fmax-Rm},${fmax-FRd-int}"
315 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
316 (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
317 (f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 1))
318 (set fmax-Rm fmax-FRd-int)
319 ()
320)
321(dni cmovc-ccrn-rm
322 "cmovc CCRn,Rm"
323 (all-fmax-isas (INTRINSIC "cmovc1"))
324 "cmovc ${fmax-CCRn},${fmax-Rm}"
325 (+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7)
326 (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
327 (f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 0))
328 (set fmax-CCRn fmax-Rm)
329 ()
330)
331(dni cmovc-rm-ccrn
332 "cmovc Rm,CCRn"
333 (all-fmax-isas (INTRINSIC "cmovc2"))
334 "cmovc ${fmax-Rm},${fmax-CCRn}"
335 (+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7)
336 (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
337 (f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 1))
338 (set fmax-Rm fmax-CCRn)
339 ()
340)