[thirdparty/binutils-gdb.git] / cpu / or1korfpx.cpu

; OpenRISC 1000 architecture.  -*- Scheme -*-
; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed by Peter Gavin, pgavin@gmail.com
; Modified by Andrey Bacherov, avbacherov@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, see <http://www.gnu.org/licenses/>

; Initial ORFPX32 instruction set

; I'm not sure how CGEN handles rounding in FP operations, except for
; in conversions to/from integers.  So lf.add, lf.sub, lf.mul, and
; lf.div do not round according to the FPCSR RM field.
; NaN, overflow, and underflow are not yet handled either.

(define-normal-insn-enum insn-opcode-float-regreg
  "floating point reg/reg insn opcode enums" ()
  OPC_FLOAT_REGREG_ f-op-7-8
  (("ADD_S"  #x00)
   ("SUB_S"  #x01)
   ("MUL_S"  #x02)
   ("DIV_S"  #x03)
   ("ITOF_S" #x04)
   ("FTOI_S" #x05)
   ("REM_S"  #x06)
   ("MADD_S" #x07)
   ("SFEQ_S" #x08)
   ("SFNE_S" #x09)
   ("SFGT_S" #x0a)
   ("SFGE_S" #x0b)
   ("SFLT_S" #x0c)
   ("SFLE_S" #x0d)
   ("ADD_D"  #x10)
   ("SUB_D"  #x11)
   ("MUL_D"  #x12)
   ("DIV_D"  #x13)
   ("ITOF_D" #x14)
   ("FTOI_D" #x15)
   ("REM_D"  #x16)
   ("MADD_D" #x17)
   ("SFEQ_D" #x18)
   ("SFNE_D" #x19)
   ("SFGT_D" #x1a)
   ("SFGE_D" #x1b)
   ("SFLT_D" #x1c)
   ("SFLE_D" #x1d)
   ("SFUEQ_S" #x28)
   ("SFUNE_S" #x29)
   ("SFUGT_S" #x2a)
   ("SFUGE_S" #x2b)
   ("SFULT_S" #x2c)
   ("SFULE_S" #x2d)
   ("SFUN_S" #x2e)
   ("SFUEQ_D" #x38)
   ("SFUNE_D" #x39)
   ("SFUGT_D" #x3a)
   ("SFUGE_D" #x3b)
   ("SFULT_D" #x3c)
   ("SFULE_D" #x3d)
   ("SFUN_D" #x3e)
   ("CUST1_S" #xd0)
   ("CUST1_D" #xe0)
   )
  )

; Register offset flags, if set offset is 2 otherwise offset is 1
(dnf f-rdoff-10-1   "destination register pair offset flag" ((MACH ORFPX64A32-MACHS)) 10 1)
(dnf f-raoff-9-1    "source register A pair offset flag"    ((MACH ORFPX64A32-MACHS)) 9 1)
(dnf f-rboff-8-1    "source register B pair offset flag"    ((MACH ORFPX64A32-MACHS)) 8 1)

(dsh h-roff1        "1-bit offset flag"                     () (register BI))

(dnop rDSF "destination register (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r1)
(dnop rASF "source register A (single floating point mode)"    ((MACH ORFPX32-MACHS)) h-fsr f-r2)
(dnop rBSF "source register B (single floating point mode)"    ((MACH ORFPX32-MACHS)) h-fsr f-r3)

(define-pmacro (double-field-and-ops mnemonic reg offbit op-comment)
  (begin
    (define-multi-ifield
      (name (.sym "f-r" (.downcase mnemonic) "d32"))
      (comment op-comment)
      (attrs (MACH ORFPX64A32-MACHS))
      (mode SI)
      (subfields reg offbit)
      ; From the multi-ifield insert the bits into subfields
      (insert (sequence
		()
		(set (ifield reg)
		  (and (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
		       (const #x1f))
		  )
		(set (ifield offbit)
		  (and (sra (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
		            (const 5))
		       (const 1))
		  )
		)
	)
      ; Extract the multi-ifield from the subfield bits
      (extract
	       (set (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
		    (or (ifield reg)
			(sll (ifield offbit)
			     (const 5)))
		 )
        )
      )
    (define-operand
      (name (.sym "r" (.upcase mnemonic) "D32F"))
      (comment (.str op-comment " (double floating point pair)"))
      (attrs (MACH ORFPX64A32-MACHS))
      (type h-fd32r)
      (index (.sym "f-r" (.downcase mnemonic) "d32"))
      (handlers (parse "regpair") (print "regpair"))
      )
    (define-operand
      (name (.sym "r" (.upcase mnemonic) "DI"))
      (comment (.str op-comment " (double integer pair)"))
      (attrs (MACH ORFPX64A32-MACHS))
      (type h-i64r)
      (index (.sym "f-r" (.downcase mnemonic) "d32"))
      (handlers (parse "regpair") (print "regpair"))
      )
    )
  )

(double-field-and-ops D f-r1 f-rdoff-10-1 "destination register")
(double-field-and-ops A f-r2 f-raoff-9-1  "source register A")
(double-field-and-ops B f-r3 f-rboff-8-1  "source register B")

(define-pmacro (float-regreg-insn mnemonic)
  (begin
    (dni (.sym lf- mnemonic -s)
         (.str "lf." mnemonic ".s reg/reg/reg")
         ((MACH ORFPX32-MACHS))
         (.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
         (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
         (set SF rDSF (mnemonic SF rASF rBSF))
         ()
         )
    (dni (.sym lf- mnemonic -d32)
         (.str "lf." mnemonic ".d regpair/regpair/regpair")
         ((MACH ORFPX64A32-MACHS))
         (.str "lf." mnemonic ".d $rDD32F,$rAD32F,$rBD32F")
         (+ OPC_FLOAT rDD32F rAD32F rBD32F (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
         (set DF rDD32F (mnemonic DF rAD32F rBD32F))
         ()
         )
    )
  )

(float-regreg-insn add)
(float-regreg-insn sub)
(float-regreg-insn mul)
(float-regreg-insn div)

(dni lf-rem-s
     "lf.rem.s reg/reg/reg"
     ((MACH ORFPX32-MACHS))
     "lf.rem.s $rDSF,$rASF,$rBSF"
     (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
     (set SF rDSF (rem SF rASF rBSF))
     ()
     )

(dni lf-rem-d32
     "lf.rem.d regpair/regpair/regpair"
     ((MACH ORFPX64A32-MACHS))
     "lf.rem.d $rDD32F,$rAD32F,$rBD32F"
     (+ OPC_FLOAT rDD32F rAD32F rBD32F OPC_FLOAT_REGREG_REM_D)
     (set DF rDD32F (rem DF rAD32F rBD32F))
     ()
     )

(define-pmacro (get-rounding-mode)
  (case INT sys-fpcsr-rm
        ((0) 1) ; TIES-TO-EVEN -- I'm assuming this is what is meant by "round to nearest"
        ((1) 3) ; TOWARD-ZERO
        ((2) 4) ; TOWARD-POSITIVE
        (else 5) ; TOWARD-NEGATIVE
        )
  )

(dni lf-itof-s
     "lf.itof.s reg/reg"
     ((MACH ORFPX32-MACHS))
     "lf.itof.s $rDSF,$rA"
     (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
     (set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
     ()
     )

(dni lf-itof-d32
     "lf.itof.d regpair/regpair"
     ((MACH ORFPX64A32-MACHS))
     "lf.itof.d $rDD32F,$rADI"
     (+ OPC_FLOAT rDD32F rADI (f-r3 0) (f-resv-8-1 0) OPC_FLOAT_REGREG_ITOF_D)
     (set DF rDD32F (float DF (get-rounding-mode) rADI))
     ()
     )

(dni lf-ftoi-s
     "lf.ftoi.s reg/reg"
     ((MACH ORFPX32-MACHS))
     "lf.ftoi.s $rD,$rASF"
     (+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
     (set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
     ()
     )

(dni lf-ftoi-d32
     "lf.ftoi.d regpair/regpair"
     ((MACH ORFPX64A32-MACHS))
     "lf.ftoi.d $rDDI,$rAD32F"
     (+ OPC_FLOAT rDDI rAD32F (f-r3 0) (f-resv-8-1 0) OPC_FLOAT_REGREG_FTOI_D)
     (set DI rDDI (fix DI (get-rounding-mode) rAD32F))
     ()
     )

(define-pmacro (float-setflag-insn-base mnemonic rtx-mnemonic symantics)
  (begin
    (dni (.sym lf-sf mnemonic -s)
         (.str "lf.sf" mnemonic ".s reg/reg")
         ((MACH ORFPX32-MACHS))
         (.str "lf.sf" mnemonic ".s $rASF,$rBSF")
         (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
         (symantics rtx-mnemonic SF rASF rBSF)
         ()
         )
    (dni (.sym lf-sf mnemonic -d32)
         (.str "lf.sf" mnemonic ".d regpair/regpair")
         ((MACH ORFPX64A32-MACHS))
         (.str "lf.sf" mnemonic ".d $rAD32F,$rBD32F")
         (+ OPC_FLOAT (f-r1 0) rAD32F rBD32F (f-resv-10-1 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
         (symantics rtx-mnemonic DF rAD32F rBD32F)
         ()
         )
    )
  )

(define-pmacro (float-setflag-symantics mnemonic mode r1 r2)
  (set BI sys-sr-f (mnemonic mode r1 r2)))

(define-pmacro (float-setflag-insn mnemonic)
  (float-setflag-insn-base mnemonic mnemonic float-setflag-symantics))

(define-pmacro (float-setflag-unordered-cmp-symantics mnemonic mode r1 r2)
  (set BI sys-sr-f (or (unordered mode r1 r2)
                       (mnemonic mode r1 r2))))

(define-pmacro (float-setflag-unordered-symantics mnemonic mode r1 r2)
  (set BI sys-sr-f (unordered mode r1 r2)))

(define-pmacro (float-setflag-unordered-insn mnemonic)
  (float-setflag-insn-base (.str "u" mnemonic)
                           mnemonic
                           float-setflag-unordered-cmp-symantics))

(float-setflag-insn eq)
(float-setflag-insn ne)
(float-setflag-insn ge)
(float-setflag-insn gt)
(float-setflag-insn lt)
(float-setflag-insn le)
(float-setflag-unordered-insn eq)
(float-setflag-unordered-insn ne)
(float-setflag-unordered-insn gt)
(float-setflag-unordered-insn ge)
(float-setflag-unordered-insn lt)
(float-setflag-unordered-insn le)
(float-setflag-insn-base un () float-setflag-unordered-symantics)

(dni lf-madd-s
     "lf.madd.s reg/reg/reg"
     ((MACH ORFPX32-MACHS))
     "lf.madd.s $rDSF,$rASF,$rBSF"
     (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
     (set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
     ()
     )

(dni lf-madd-d32
     "lf.madd.d regpair/regpair/regpair"
     ((MACH ORFPX64A32-MACHS))
     "lf.madd.d $rDD32F,$rAD32F,$rBD32F"
     (+ OPC_FLOAT rDD32F rAD32F rBD32F OPC_FLOAT_REGREG_MADD_D)
     (set DF rDD32F (add DF (mul DF rAD32F rBD32F) rDD32F))
     ()
     )

(define-pmacro (float-cust-insn cust-num)
  (begin
    (dni (.sym "lf-cust" cust-num "-s")
         (.str "lf.cust" cust-num ".s")
         ((MACH ORFPX32-MACHS))
         (.str "lf.cust" cust-num ".s $rASF,$rBSF")
         (+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
         (nop)
         ()
         )
    (dni (.sym "lf-cust" cust-num "-d32")
         (.str "lf.cust" cust-num ".d")
         ((MACH ORFPX64A32-MACHS))
         (.str "lf.cust" cust-num ".d")
         (+ OPC_FLOAT (f-resv-25-5 0) rAD32F rBD32F (f-resv-10-1 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
         (nop)
         ()
         )
    )
  )

(float-cust-insn "1")
Commit	Line	Data
73589c9d	1	; OpenRISC 1000 architecture. -- Scheme --
6ce26ac7	2	; Copyright 2000-2019 Free Software Foundation, Inc.
73589c9d	3	; Contributed by Peter Gavin, pgavin@gmail.com
6ce26ac7	4	; Modified by Andrey Bacherov, avbacherov@opencores.org
73589c9d CS	5	;
	6	; This program is free software; you can redistribute it and/or modify
	7	; it under the terms of the GNU General Public License as published by
	8	; the Free Software Foundation; either version 3 of the License, or
	9	; (at your option) any later version.
	10	;
	11	; This program is distributed in the hope that it will be useful,
	12	; but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	; GNU General Public License for more details.
	15	;
	16	; You should have received a copy of the GNU General Public License
	17	; along with this program; if not, see <http://www.gnu.org/licenses/>
	18
	19	; Initial ORFPX32 instruction set
	20
	21	; I'm not sure how CGEN handles rounding in FP operations, except for
	22	; in conversions to/from integers. So lf.add, lf.sub, lf.mul, and
	23	; lf.div do not round according to the FPCSR RM field.
	24	; NaN, overflow, and underflow are not yet handled either.
	25
	26	(define-normal-insn-enum insn-opcode-float-regreg
	27	"floating point reg/reg insn opcode enums" ()
	28	OPC_FLOAT_REGREG_ f-op-7-8
	29	(("ADD_S" #x00)
	30	("SUB_S" #x01)
	31	("MUL_S" #x02)
	32	("DIV_S" #x03)
	33	("ITOF_S" #x04)
	34	("FTOI_S" #x05)
	35	("REM_S" #x06)
	36	("MADD_S" #x07)
	37	("SFEQ_S" #x08)
	38	("SFNE_S" #x09)
	39	("SFGT_S" #x0a)
	40	("SFGE_S" #x0b)
	41	("SFLT_S" #x0c)
	42	("SFLE_S" #x0d)
	43	("ADD_D" #x10)
	44	("SUB_D" #x11)
	45	("MUL_D" #x12)
	46	("DIV_D" #x13)
	47	("ITOF_D" #x14)
	48	("FTOI_D" #x15)
	49	("REM_D" #x16)
	50	("MADD_D" #x17)
	51	("SFEQ_D" #x18)
	52	("SFNE_D" #x19)
	53	("SFGT_D" #x1a)
	54	("SFGE_D" #x1b)
	55	("SFLT_D" #x1c)
	56	("SFLE_D" #x1d)
d3ad6278 SH	57	("SFUEQ_S" #x28)
	58	("SFUNE_S" #x29)
	59	("SFUGT_S" #x2a)
	60	("SFUGE_S" #x2b)
	61	("SFULT_S" #x2c)
	62	("SFULE_S" #x2d)
	63	("SFUN_S" #x2e)
	64	("SFUEQ_D" #x38)
	65	("SFUNE_D" #x39)
	66	("SFUGT_D" #x3a)
	67	("SFUGE_D" #x3b)
	68	("SFULT_D" #x3c)
	69	("SFULE_D" #x3d)
	70	("SFUN_D" #x3e)
73589c9d CS	71	("CUST1_S" #xd0)
	72	("CUST1_D" #xe0)
	73	)
	74	)
	75
6ce26ac7 SH	76	; Register offset flags, if set offset is 2 otherwise offset is 1
	77	(dnf f-rdoff-10-1 "destination register pair offset flag" ((MACH ORFPX64A32-MACHS)) 10 1)
	78	(dnf f-raoff-9-1 "source register A pair offset flag" ((MACH ORFPX64A32-MACHS)) 9 1)
	79	(dnf f-rboff-8-1 "source register B pair offset flag" ((MACH ORFPX64A32-MACHS)) 8 1)
73589c9d	80
6ce26ac7 SH	81	(dsh h-roff1 "1-bit offset flag" () (register BI))
	82
	83	(dnop rDSF "destination register (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r1)
	84	(dnop rASF "source register A (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r2)
	85	(dnop rBSF "source register B (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r3)
	86
6ce26ac7 SH	87	(define-pmacro (double-field-and-ops mnemonic reg offbit op-comment)
	88	(begin
	89	(define-multi-ifield
	90	(name (.sym "f-r" (.downcase mnemonic) "d32"))
	91	(comment op-comment)
	92	(attrs (MACH ORFPX64A32-MACHS))
	93	(mode SI)
	94	(subfields reg offbit)
	95	; From the multi-ifield insert the bits into subfields
	96	(insert (sequence
	97	()
	98	(set (ifield reg)
	99	(and (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
	100	(const #x1f))
	101	)
	102	(set (ifield offbit)
	103	(and (sra (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
	104	(const 5))
	105	(const 1))
	106	)
	107	)
	108	)
	109	; Extract the multi-ifield from the subfield bits
	110	(extract
	111	(set (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
	112	(or (ifield reg)
	113	(sll (ifield offbit)
	114	(const 5)))
	115	)
	116	)
	117	)
	118	(define-operand
	119	(name (.sym "r" (.upcase mnemonic) "D32F"))
	120	(comment (.str op-comment " (double floating point pair)"))
	121	(attrs (MACH ORFPX64A32-MACHS))
	122	(type h-fd32r)
	123	(index (.sym "f-r" (.downcase mnemonic) "d32"))
	124	(handlers (parse "regpair") (print "regpair"))
	125	)
	126	(define-operand
	127	(name (.sym "r" (.upcase mnemonic) "DI"))
	128	(comment (.str op-comment " (double integer pair)"))
	129	(attrs (MACH ORFPX64A32-MACHS))
	130	(type h-i64r)
	131	(index (.sym "f-r" (.downcase mnemonic) "d32"))
	132	(handlers (parse "regpair") (print "regpair"))
	133	)
	134	)
	135	)
	136
	137	(double-field-and-ops D f-r1 f-rdoff-10-1 "destination register")
	138	(double-field-and-ops A f-r2 f-raoff-9-1 "source register A")
	139	(double-field-and-ops B f-r3 f-rboff-8-1 "source register B")
73589c9d CS	140
	141	(define-pmacro (float-regreg-insn mnemonic)
	142	(begin
	143	(dni (.sym lf- mnemonic -s)
	144	(.str "lf." mnemonic ".s reg/reg/reg")
6ce26ac7	145	((MACH ORFPX32-MACHS))
73589c9d CS	146	(.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
	147	(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
	148	(set SF rDSF (mnemonic SF rASF rBSF))
	149	()
	150	)
6ce26ac7 SH	151	(dni (.sym lf- mnemonic -d32)
	152	(.str "lf." mnemonic ".d regpair/regpair/regpair")
	153	((MACH ORFPX64A32-MACHS))
	154	(.str "lf." mnemonic ".d $rDD32F,$rAD32F,$rBD32F")
	155	(+ OPC_FLOAT rDD32F rAD32F rBD32F (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
	156	(set DF rDD32F (mnemonic DF rAD32F rBD32F))
	157	()
	158	)
73589c9d CS	159	)
	160	)
	161
	162	(float-regreg-insn add)
	163	(float-regreg-insn sub)
	164	(float-regreg-insn mul)
	165	(float-regreg-insn div)
	166
	167	(dni lf-rem-s
	168	"lf.rem.s reg/reg/reg"
6ce26ac7	169	((MACH ORFPX32-MACHS))
73589c9d CS	170	"lf.rem.s $rDSF,$rASF,$rBSF"
	171	(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
	172	(set SF rDSF (rem SF rASF rBSF))
	173	()
	174	)
6ce26ac7	175
6ce26ac7 SH	176	(dni lf-rem-d32
	177	"lf.rem.d regpair/regpair/regpair"
	178	((MACH ORFPX64A32-MACHS))
	179	"lf.rem.d $rDD32F,$rAD32F,$rBD32F"
	180	(+ OPC_FLOAT rDD32F rAD32F rBD32F OPC_FLOAT_REGREG_REM_D)
	181	(set DF rDD32F (rem DF rAD32F rBD32F))
73589c9d CS	182	()
	183	)
	184
	185	(define-pmacro (get-rounding-mode)
	186	(case INT sys-fpcsr-rm
	187	((0) 1) ; TIES-TO-EVEN -- I'm assuming this is what is meant by "round to nearest"
	188	((1) 3) ; TOWARD-ZERO
	189	((2) 4) ; TOWARD-POSITIVE
	190	(else 5) ; TOWARD-NEGATIVE
	191	)
	192	)
	193
	194	(dni lf-itof-s
	195	"lf.itof.s reg/reg"
6ce26ac7	196	((MACH ORFPX32-MACHS))
73589c9d CS	197	"lf.itof.s $rDSF,$rA"
	198	(+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
	199	(set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
	200	()
	201	)
6ce26ac7	202
6ce26ac7 SH	203	(dni lf-itof-d32
	204	"lf.itof.d regpair/regpair"
	205	((MACH ORFPX64A32-MACHS))
	206	"lf.itof.d $rDD32F,$rADI"
	207	(+ OPC_FLOAT rDD32F rADI (f-r3 0) (f-resv-8-1 0) OPC_FLOAT_REGREG_ITOF_D)
	208	(set DF rDD32F (float DF (get-rounding-mode) rADI))
	209	()
	210	)
	211
73589c9d CS	212	(dni lf-ftoi-s
73589c9d CS	213	"lf.ftoi.s reg/reg"
6ce26ac7	214	((MACH ORFPX32-MACHS))
73589c9d CS	215	"lf.ftoi.s $rD,$rASF"
	216	(+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
	217	(set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
	218	()
	219	)
	220
6ce26ac7 SH	221	(dni lf-ftoi-d32
	222	"lf.ftoi.d regpair/regpair"
	223	((MACH ORFPX64A32-MACHS))
	224	"lf.ftoi.d $rDDI,$rAD32F"
	225	(+ OPC_FLOAT rDDI rAD32F (f-r3 0) (f-resv-8-1 0) OPC_FLOAT_REGREG_FTOI_D)
	226	(set DI rDDI (fix DI (get-rounding-mode) rAD32F))
73589c9d CS	227	()
	228	)
	229
d3ad6278	230	(define-pmacro (float-setflag-insn-base mnemonic rtx-mnemonic symantics)
73589c9d	231	(begin
a2e4218f	232	(dni (.sym lf-sf mnemonic -s)
73589c9d	233	(.str "lf.sf" mnemonic ".s reg/reg")
6ce26ac7	234	((MACH ORFPX32-MACHS))
73589c9d CS	235	(.str "lf.sf" mnemonic ".s $rASF,$rBSF")
73589c9d CS	236	(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
d3ad6278	237	(symantics rtx-mnemonic SF rASF rBSF)
73589c9d CS	238	()
73589c9d CS	239	)
a2e4218f	240	(dni (.sym lf-sf mnemonic -d32)
6ce26ac7 SH	241	(.str "lf.sf" mnemonic ".d regpair/regpair")
	242	((MACH ORFPX64A32-MACHS))
	243	(.str "lf.sf" mnemonic ".d $rAD32F,$rBD32F")
	244	(+ OPC_FLOAT (f-r1 0) rAD32F rBD32F (f-resv-10-1 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
d3ad6278	245	(symantics rtx-mnemonic DF rAD32F rBD32F)
6ce26ac7 SH	246	()
6ce26ac7 SH	247	)
73589c9d CS	248	)
	249	)
	250
d3ad6278 SH	251	(define-pmacro (float-setflag-symantics mnemonic mode r1 r2)
	252	(set BI sys-sr-f (mnemonic mode r1 r2)))
	253
	254	(define-pmacro (float-setflag-insn mnemonic)
	255	(float-setflag-insn-base mnemonic mnemonic float-setflag-symantics))
	256
	257	(define-pmacro (float-setflag-unordered-cmp-symantics mnemonic mode r1 r2)
	258	(set BI sys-sr-f (or (unordered mode r1 r2)
	259	(mnemonic mode r1 r2))))
	260
	261	(define-pmacro (float-setflag-unordered-symantics mnemonic mode r1 r2)
	262	(set BI sys-sr-f (unordered mode r1 r2)))
	263
	264	(define-pmacro (float-setflag-unordered-insn mnemonic)
	265	(float-setflag-insn-base (.str "u" mnemonic)
	266	mnemonic
	267	float-setflag-unordered-cmp-symantics))
	268
73589c9d CS	269	(float-setflag-insn eq)
	270	(float-setflag-insn ne)
	271	(float-setflag-insn ge)
	272	(float-setflag-insn gt)
	273	(float-setflag-insn lt)
	274	(float-setflag-insn le)
d3ad6278 SH	275	(float-setflag-unordered-insn eq)
	276	(float-setflag-unordered-insn ne)
	277	(float-setflag-unordered-insn gt)
	278	(float-setflag-unordered-insn ge)
	279	(float-setflag-unordered-insn lt)
	280	(float-setflag-unordered-insn le)
	281	(float-setflag-insn-base un () float-setflag-unordered-symantics)
73589c9d CS	282
	283	(dni lf-madd-s
	284	"lf.madd.s reg/reg/reg"
6ce26ac7	285	((MACH ORFPX32-MACHS))
73589c9d CS	286	"lf.madd.s $rDSF,$rASF,$rBSF"
	287	(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
	288	(set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
	289	()
	290	)
6ce26ac7	291
6ce26ac7 SH	292	(dni lf-madd-d32
	293	"lf.madd.d regpair/regpair/regpair"
	294	((MACH ORFPX64A32-MACHS))
	295	"lf.madd.d $rDD32F,$rAD32F,$rBD32F"
	296	(+ OPC_FLOAT rDD32F rAD32F rBD32F OPC_FLOAT_REGREG_MADD_D)
	297	(set DF rDD32F (add DF (mul DF rAD32F rBD32F) rDD32F))
	298	()
	299	)
	300
73589c9d CS	301	(define-pmacro (float-cust-insn cust-num)
	302	(begin
	303	(dni (.sym "lf-cust" cust-num "-s")
	304	(.str "lf.cust" cust-num ".s")
6ce26ac7	305	((MACH ORFPX32-MACHS))
73589c9d CS	306	(.str "lf.cust" cust-num ".s $rASF,$rBSF")
	307	(+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
	308	(nop)
	309	()
	310	)
6ce26ac7 SH	311	(dni (.sym "lf-cust" cust-num "-d32")
	312	(.str "lf.cust" cust-num ".d")
	313	((MACH ORFPX64A32-MACHS))
	314	(.str "lf.cust" cust-num ".d")
	315	(+ OPC_FLOAT (f-resv-25-5 0) rAD32F rBD32F (f-resv-10-1 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
	316	(nop)
	317	()
	318	)
73589c9d CS	319	)
	320	)
	321
	322	(float-cust-insn "1")