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a06ea964 NC |
1 | /* tc-aarch64.c -- Assemble for the AArch64 ISA |
2 | ||
b3adc24a | 3 | Copyright (C) 2009-2020 Free Software Foundation, Inc. |
a06ea964 NC |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GAS. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the license, or | |
11 | (at your option) any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING3. If not, | |
20 | see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "as.h" | |
23 | #include <limits.h> | |
24 | #include <stdarg.h> | |
25 | #include "bfd_stdint.h" | |
26 | #define NO_RELOC 0 | |
27 | #include "safe-ctype.h" | |
28 | #include "subsegs.h" | |
29 | #include "obstack.h" | |
8b21361b | 30 | #include "cpu-aarch64.h" |
a06ea964 NC |
31 | |
32 | #ifdef OBJ_ELF | |
33 | #include "elf/aarch64.h" | |
34 | #include "dw2gencfi.h" | |
35 | #endif | |
36 | ||
37 | #include "dwarf2dbg.h" | |
38 | ||
39 | /* Types of processor to assemble for. */ | |
40 | #ifndef CPU_DEFAULT | |
41 | #define CPU_DEFAULT AARCH64_ARCH_V8 | |
42 | #endif | |
43 | ||
44 | #define streq(a, b) (strcmp (a, b) == 0) | |
45 | ||
f4c51f60 JW |
46 | #define END_OF_INSN '\0' |
47 | ||
3979cf50 SP |
48 | #define MAP_CUR_INSN (AARCH64_CPU_HAS_FEATURE (cpu_variant, \ |
49 | AARCH64_FEATURE_C64) \ | |
50 | ? MAP_C64 : MAP_INSN) | |
51 | ||
8b21361b SP |
52 | #define IS_C64 (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64) \ |
53 | ? 1 : 0) | |
54 | ||
a06ea964 NC |
55 | static aarch64_feature_set cpu_variant; |
56 | ||
57 | /* Variables that we set while parsing command-line options. Once all | |
58 | options have been read we re-process these values to set the real | |
59 | assembly flags. */ | |
60 | static const aarch64_feature_set *mcpu_cpu_opt = NULL; | |
61 | static const aarch64_feature_set *march_cpu_opt = NULL; | |
62 | ||
63 | /* Constants for known architecture features. */ | |
64 | static const aarch64_feature_set cpu_default = CPU_DEFAULT; | |
65 | ||
7e84b55d TC |
66 | /* Currently active instruction sequence. */ |
67 | static aarch64_instr_sequence *insn_sequence = NULL; | |
68 | ||
a06ea964 NC |
69 | #ifdef OBJ_ELF |
70 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ | |
71 | static symbolS *GOT_symbol; | |
cec5225b | 72 | |
69091a2c YZ |
73 | /* Which ABI to use. */ |
74 | enum aarch64_abi_type | |
75 | { | |
3c0367d0 JW |
76 | AARCH64_ABI_NONE = 0, |
77 | AARCH64_ABI_LP64 = 1, | |
78 | AARCH64_ABI_ILP32 = 2 | |
69091a2c YZ |
79 | }; |
80 | ||
3c0367d0 JW |
81 | #ifndef DEFAULT_ARCH |
82 | #define DEFAULT_ARCH "aarch64" | |
83 | #endif | |
84 | ||
85 | /* DEFAULT_ARCH is initialized in gas/configure.tgt. */ | |
86 | static const char *default_arch = DEFAULT_ARCH; | |
87 | ||
69091a2c | 88 | /* AArch64 ABI for the output file. */ |
3c0367d0 | 89 | static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_NONE; |
69091a2c | 90 | |
cec5225b YZ |
91 | /* When non-zero, program to a 32-bit model, in which the C data types |
92 | int, long and all pointer types are 32-bit objects (ILP32); or to a | |
93 | 64-bit model, in which the C int type is 32-bits but the C long type | |
94 | and all pointer types are 64-bit objects (LP64). */ | |
69091a2c | 95 | #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32) |
a06ea964 NC |
96 | #endif |
97 | ||
f06935a5 | 98 | enum vector_el_type |
a06ea964 NC |
99 | { |
100 | NT_invtype = -1, | |
101 | NT_b, | |
102 | NT_h, | |
103 | NT_s, | |
104 | NT_d, | |
d50c751e RS |
105 | NT_q, |
106 | NT_zero, | |
107 | NT_merge | |
a06ea964 NC |
108 | }; |
109 | ||
8f9a77af | 110 | /* Bits for DEFINED field in vector_type_el. */ |
f11ad6bc RS |
111 | #define NTA_HASTYPE 1 |
112 | #define NTA_HASINDEX 2 | |
113 | #define NTA_HASVARWIDTH 4 | |
a06ea964 | 114 | |
8f9a77af | 115 | struct vector_type_el |
a06ea964 | 116 | { |
f06935a5 | 117 | enum vector_el_type type; |
a06ea964 NC |
118 | unsigned char defined; |
119 | unsigned width; | |
120 | int64_t index; | |
121 | }; | |
122 | ||
123 | #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001 | |
f0070c1e | 124 | #define FIXUP_F_C64 0x00000002 |
a06ea964 NC |
125 | |
126 | struct reloc | |
127 | { | |
128 | bfd_reloc_code_real_type type; | |
129 | expressionS exp; | |
130 | int pc_rel; | |
131 | enum aarch64_opnd opnd; | |
132 | uint32_t flags; | |
133 | unsigned need_libopcodes_p : 1; | |
134 | }; | |
135 | ||
136 | struct aarch64_instruction | |
137 | { | |
138 | /* libopcodes structure for instruction intermediate representation. */ | |
139 | aarch64_inst base; | |
140 | /* Record assembly errors found during the parsing. */ | |
141 | struct | |
142 | { | |
143 | enum aarch64_operand_error_kind kind; | |
144 | const char *error; | |
145 | } parsing_error; | |
146 | /* The condition that appears in the assembly line. */ | |
147 | int cond; | |
148 | /* Relocation information (including the GAS internal fixup). */ | |
149 | struct reloc reloc; | |
150 | /* Need to generate an immediate in the literal pool. */ | |
151 | unsigned gen_lit_pool : 1; | |
152 | }; | |
153 | ||
154 | typedef struct aarch64_instruction aarch64_instruction; | |
155 | ||
156 | static aarch64_instruction inst; | |
157 | ||
158 | static bfd_boolean parse_operands (char *, const aarch64_opcode *); | |
159 | static bfd_boolean programmer_friendly_fixup (aarch64_instruction *); | |
160 | ||
7e84b55d TC |
161 | #ifdef OBJ_ELF |
162 | # define now_instr_sequence seg_info \ | |
163 | (now_seg)->tc_segment_info_data.insn_sequence | |
164 | #else | |
165 | static struct aarch64_instr_sequence now_instr_sequence; | |
166 | #endif | |
167 | ||
33eaf5de | 168 | /* Diagnostics inline function utilities. |
a06ea964 | 169 | |
33eaf5de | 170 | These are lightweight utilities which should only be called by parse_operands |
a06ea964 NC |
171 | and other parsers. GAS processes each assembly line by parsing it against |
172 | instruction template(s), in the case of multiple templates (for the same | |
173 | mnemonic name), those templates are tried one by one until one succeeds or | |
174 | all fail. An assembly line may fail a few templates before being | |
175 | successfully parsed; an error saved here in most cases is not a user error | |
176 | but an error indicating the current template is not the right template. | |
177 | Therefore it is very important that errors can be saved at a low cost during | |
178 | the parsing; we don't want to slow down the whole parsing by recording | |
179 | non-user errors in detail. | |
180 | ||
33eaf5de | 181 | Remember that the objective is to help GAS pick up the most appropriate |
a06ea964 NC |
182 | error message in the case of multiple templates, e.g. FMOV which has 8 |
183 | templates. */ | |
184 | ||
185 | static inline void | |
186 | clear_error (void) | |
187 | { | |
188 | inst.parsing_error.kind = AARCH64_OPDE_NIL; | |
189 | inst.parsing_error.error = NULL; | |
190 | } | |
191 | ||
192 | static inline bfd_boolean | |
193 | error_p (void) | |
194 | { | |
195 | return inst.parsing_error.kind != AARCH64_OPDE_NIL; | |
196 | } | |
197 | ||
198 | static inline const char * | |
199 | get_error_message (void) | |
200 | { | |
201 | return inst.parsing_error.error; | |
202 | } | |
203 | ||
a06ea964 NC |
204 | static inline enum aarch64_operand_error_kind |
205 | get_error_kind (void) | |
206 | { | |
207 | return inst.parsing_error.kind; | |
208 | } | |
209 | ||
a06ea964 NC |
210 | static inline void |
211 | set_error (enum aarch64_operand_error_kind kind, const char *error) | |
212 | { | |
213 | inst.parsing_error.kind = kind; | |
214 | inst.parsing_error.error = error; | |
215 | } | |
216 | ||
217 | static inline void | |
218 | set_recoverable_error (const char *error) | |
219 | { | |
220 | set_error (AARCH64_OPDE_RECOVERABLE, error); | |
221 | } | |
222 | ||
223 | /* Use the DESC field of the corresponding aarch64_operand entry to compose | |
224 | the error message. */ | |
225 | static inline void | |
226 | set_default_error (void) | |
227 | { | |
228 | set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL); | |
229 | } | |
230 | ||
231 | static inline void | |
232 | set_syntax_error (const char *error) | |
233 | { | |
234 | set_error (AARCH64_OPDE_SYNTAX_ERROR, error); | |
235 | } | |
236 | ||
237 | static inline void | |
238 | set_first_syntax_error (const char *error) | |
239 | { | |
240 | if (! error_p ()) | |
241 | set_error (AARCH64_OPDE_SYNTAX_ERROR, error); | |
242 | } | |
243 | ||
244 | static inline void | |
245 | set_fatal_syntax_error (const char *error) | |
246 | { | |
247 | set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error); | |
248 | } | |
249 | \f | |
a06ea964 NC |
250 | /* Return value for certain parsers when the parsing fails; those parsers |
251 | return the information of the parsed result, e.g. register number, on | |
252 | success. */ | |
253 | #define PARSE_FAIL -1 | |
254 | ||
255 | /* This is an invalid condition code that means no conditional field is | |
256 | present. */ | |
257 | #define COND_ALWAYS 0x10 | |
258 | ||
a06ea964 NC |
259 | typedef struct |
260 | { | |
261 | const char *template; | |
262 | uint32_t value; | |
263 | } asm_nzcv; | |
264 | ||
265 | struct reloc_entry | |
266 | { | |
267 | char *name; | |
268 | bfd_reloc_code_real_type reloc; | |
269 | }; | |
270 | ||
a06ea964 NC |
271 | /* Macros to define the register types and masks for the purpose |
272 | of parsing. */ | |
273 | ||
274 | #undef AARCH64_REG_TYPES | |
275 | #define AARCH64_REG_TYPES \ | |
276 | BASIC_REG_TYPE(R_32) /* w[0-30] */ \ | |
277 | BASIC_REG_TYPE(R_64) /* x[0-30] */ \ | |
278 | BASIC_REG_TYPE(SP_32) /* wsp */ \ | |
279 | BASIC_REG_TYPE(SP_64) /* sp */ \ | |
280 | BASIC_REG_TYPE(Z_32) /* wzr */ \ | |
281 | BASIC_REG_TYPE(Z_64) /* xzr */ \ | |
282 | BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\ | |
283 | BASIC_REG_TYPE(FP_H) /* h[0-31] */ \ | |
284 | BASIC_REG_TYPE(FP_S) /* s[0-31] */ \ | |
285 | BASIC_REG_TYPE(FP_D) /* d[0-31] */ \ | |
286 | BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \ | |
3493da5c SP |
287 | BASIC_REG_TYPE(CA_N) /* c[0-30] */ \ |
288 | BASIC_REG_TYPE(CA_SP) /* csp */ \ | |
289 | BASIC_REG_TYPE(CA_Z) /* czr */ \ | |
290 | BASIC_REG_TYPE(CA_D) /* ddc */ \ | |
a06ea964 | 291 | BASIC_REG_TYPE(VN) /* v[0-31] */ \ |
f11ad6bc RS |
292 | BASIC_REG_TYPE(ZN) /* z[0-31] */ \ |
293 | BASIC_REG_TYPE(PN) /* p[0-15] */ \ | |
e1b988bb | 294 | /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \ |
a06ea964 | 295 | MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \ |
4df068de RS |
296 | /* Typecheck: same, plus SVE registers. */ \ |
297 | MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \ | |
298 | | REG_TYPE(ZN)) \ | |
e1b988bb RS |
299 | /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \ |
300 | MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \ | |
301 | | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \ | |
4df068de RS |
302 | /* Typecheck: same, plus SVE registers. */ \ |
303 | MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \ | |
304 | | REG_TYPE(Z_32) | REG_TYPE(Z_64) \ | |
305 | | REG_TYPE(ZN)) \ | |
e1b988bb RS |
306 | /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \ |
307 | MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \ | |
308 | | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \ | |
309 | /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \ | |
a06ea964 NC |
310 | MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \ |
311 | | REG_TYPE(SP_32) | REG_TYPE(SP_64) \ | |
312 | | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \ | |
313 | /* Typecheck: any [BHSDQ]P FP. */ \ | |
314 | MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \ | |
315 | | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \ | |
e1b988bb | 316 | /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \ |
a06ea964 NC |
317 | MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \ |
318 | | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \ | |
319 | | REG_TYPE(FP_B) | REG_TYPE(FP_H) \ | |
320 | | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \ | |
5b2b928e JB |
321 | /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \ |
322 | be used for SVE instructions, since Zn and Pn are valid symbols \ | |
c0890d26 | 323 | in other contexts. */ \ |
5b2b928e JB |
324 | MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \ |
325 | | REG_TYPE(SP_32) | REG_TYPE(SP_64) \ | |
c0890d26 RS |
326 | | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \ |
327 | | REG_TYPE(FP_B) | REG_TYPE(FP_H) \ | |
328 | | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \ | |
329 | | REG_TYPE(ZN) | REG_TYPE(PN)) \ | |
a06ea964 NC |
330 | /* Any integer register; used for error messages only. */ \ |
331 | MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \ | |
332 | | REG_TYPE(SP_32) | REG_TYPE(SP_64) \ | |
333 | | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \ | |
3493da5c SP |
334 | /* Typecheck: any capability register (inc CSP) */ \ |
335 | MULTI_REG_TYPE(CA_N_SP, REG_TYPE(CA_N) | REG_TYPE(CA_SP)) \ | |
336 | MULTI_REG_TYPE(CA_N_Z, REG_TYPE(CA_N) | REG_TYPE(CA_Z)) \ | |
a06ea964 NC |
337 | /* Pseudo type to mark the end of the enumerator sequence. */ \ |
338 | BASIC_REG_TYPE(MAX) | |
339 | ||
340 | #undef BASIC_REG_TYPE | |
341 | #define BASIC_REG_TYPE(T) REG_TYPE_##T, | |
342 | #undef MULTI_REG_TYPE | |
343 | #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T) | |
344 | ||
345 | /* Register type enumerators. */ | |
8a0b252a | 346 | typedef enum aarch64_reg_type_ |
a06ea964 NC |
347 | { |
348 | /* A list of REG_TYPE_*. */ | |
349 | AARCH64_REG_TYPES | |
350 | } aarch64_reg_type; | |
351 | ||
352 | #undef BASIC_REG_TYPE | |
353 | #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T, | |
354 | #undef REG_TYPE | |
355 | #define REG_TYPE(T) (1 << REG_TYPE_##T) | |
356 | #undef MULTI_REG_TYPE | |
357 | #define MULTI_REG_TYPE(T,V) V, | |
358 | ||
8a0b252a TS |
359 | /* Structure for a hash table entry for a register. */ |
360 | typedef struct | |
361 | { | |
362 | const char *name; | |
363 | unsigned char number; | |
364 | ENUM_BITFIELD (aarch64_reg_type_) type : 8; | |
365 | unsigned char builtin; | |
366 | } reg_entry; | |
367 | ||
a06ea964 NC |
368 | /* Values indexed by aarch64_reg_type to assist the type checking. */ |
369 | static const unsigned reg_type_masks[] = | |
370 | { | |
371 | AARCH64_REG_TYPES | |
372 | }; | |
373 | ||
374 | #undef BASIC_REG_TYPE | |
375 | #undef REG_TYPE | |
376 | #undef MULTI_REG_TYPE | |
377 | #undef AARCH64_REG_TYPES | |
378 | ||
379 | /* Diagnostics used when we don't get a register of the expected type. | |
380 | Note: this has to synchronized with aarch64_reg_type definitions | |
381 | above. */ | |
382 | static const char * | |
383 | get_reg_expected_msg (aarch64_reg_type reg_type) | |
384 | { | |
385 | const char *msg; | |
386 | ||
387 | switch (reg_type) | |
388 | { | |
389 | case REG_TYPE_R_32: | |
390 | msg = N_("integer 32-bit register expected"); | |
391 | break; | |
392 | case REG_TYPE_R_64: | |
393 | msg = N_("integer 64-bit register expected"); | |
394 | break; | |
395 | case REG_TYPE_R_N: | |
396 | msg = N_("integer register expected"); | |
397 | break; | |
e1b988bb RS |
398 | case REG_TYPE_R64_SP: |
399 | msg = N_("64-bit integer or SP register expected"); | |
400 | break; | |
4df068de RS |
401 | case REG_TYPE_SVE_BASE: |
402 | msg = N_("base register expected"); | |
403 | break; | |
e1b988bb RS |
404 | case REG_TYPE_R_Z: |
405 | msg = N_("integer or zero register expected"); | |
406 | break; | |
4df068de RS |
407 | case REG_TYPE_SVE_OFFSET: |
408 | msg = N_("offset register expected"); | |
409 | break; | |
e1b988bb RS |
410 | case REG_TYPE_R_SP: |
411 | msg = N_("integer or SP register expected"); | |
412 | break; | |
a06ea964 NC |
413 | case REG_TYPE_R_Z_SP: |
414 | msg = N_("integer, zero or SP register expected"); | |
415 | break; | |
416 | case REG_TYPE_FP_B: | |
417 | msg = N_("8-bit SIMD scalar register expected"); | |
418 | break; | |
419 | case REG_TYPE_FP_H: | |
420 | msg = N_("16-bit SIMD scalar or floating-point half precision " | |
421 | "register expected"); | |
422 | break; | |
423 | case REG_TYPE_FP_S: | |
424 | msg = N_("32-bit SIMD scalar or floating-point single precision " | |
425 | "register expected"); | |
426 | break; | |
427 | case REG_TYPE_FP_D: | |
428 | msg = N_("64-bit SIMD scalar or floating-point double precision " | |
429 | "register expected"); | |
430 | break; | |
431 | case REG_TYPE_FP_Q: | |
432 | msg = N_("128-bit SIMD scalar or floating-point quad precision " | |
433 | "register expected"); | |
434 | break; | |
a06ea964 | 435 | case REG_TYPE_R_Z_BHSDQ_V: |
5b2b928e | 436 | case REG_TYPE_R_Z_SP_BHSDQ_VZP: |
a06ea964 NC |
437 | msg = N_("register expected"); |
438 | break; | |
439 | case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */ | |
440 | msg = N_("SIMD scalar or floating-point register expected"); | |
441 | break; | |
442 | case REG_TYPE_VN: /* any V reg */ | |
443 | msg = N_("vector register expected"); | |
444 | break; | |
f11ad6bc RS |
445 | case REG_TYPE_ZN: |
446 | msg = N_("SVE vector register expected"); | |
447 | break; | |
448 | case REG_TYPE_PN: | |
449 | msg = N_("SVE predicate register expected"); | |
450 | break; | |
3493da5c SP |
451 | case REG_TYPE_CA_N: |
452 | msg = N_("Capability register C0 - C30 expected"); | |
453 | break; | |
454 | case REG_TYPE_CA_SP: | |
455 | msg = N_("Capability register CSP expected"); | |
456 | break; | |
457 | case REG_TYPE_CA_N_SP: | |
458 | msg = N_("Capability register C0 - C30 or CSP expected"); | |
459 | break; | |
460 | case REG_TYPE_CA_Z: | |
461 | msg = N_("Capability register CZR expected"); | |
462 | break; | |
a06ea964 NC |
463 | default: |
464 | as_fatal (_("invalid register type %d"), reg_type); | |
465 | } | |
466 | return msg; | |
467 | } | |
468 | ||
469 | /* Some well known registers that we refer to directly elsewhere. */ | |
470 | #define REG_SP 31 | |
c469c864 | 471 | #define REG_ZR 31 |
fa6ca5e2 SP |
472 | #define REG_DW_CSP (31 + 198) |
473 | #define REG_DW_CLR (30 + 198) | |
a06ea964 NC |
474 | |
475 | /* Instructions take 4 bytes in the object file. */ | |
476 | #define INSN_SIZE 4 | |
477 | ||
629310ab ML |
478 | static htab_t aarch64_ops_hsh; |
479 | static htab_t aarch64_cond_hsh; | |
480 | static htab_t aarch64_shift_hsh; | |
481 | static htab_t aarch64_sys_regs_hsh; | |
482 | static htab_t aarch64_pstatefield_hsh; | |
483 | static htab_t aarch64_sys_regs_ic_hsh; | |
484 | static htab_t aarch64_sys_regs_dc_hsh; | |
485 | static htab_t aarch64_sys_regs_at_hsh; | |
486 | static htab_t aarch64_sys_regs_tlbi_hsh; | |
487 | static htab_t aarch64_sys_regs_sr_hsh; | |
488 | static htab_t aarch64_reg_hsh; | |
489 | static htab_t aarch64_barrier_opt_hsh; | |
490 | static htab_t aarch64_nzcv_hsh; | |
491 | static htab_t aarch64_pldop_hsh; | |
492 | static htab_t aarch64_hint_opt_hsh; | |
a06ea964 NC |
493 | |
494 | /* Stuff needed to resolve the label ambiguity | |
495 | As: | |
496 | ... | |
497 | label: <insn> | |
498 | may differ from: | |
499 | ... | |
500 | label: | |
501 | <insn> */ | |
502 | ||
503 | static symbolS *last_label_seen; | |
504 | ||
505 | /* Literal pool structure. Held on a per-section | |
506 | and per-sub-section basis. */ | |
507 | ||
508 | #define MAX_LITERAL_POOL_SIZE 1024 | |
55d9b4c1 NC |
509 | typedef struct literal_expression |
510 | { | |
511 | expressionS exp; | |
512 | /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */ | |
513 | LITTLENUM_TYPE * bignum; | |
514 | } literal_expression; | |
515 | ||
a06ea964 NC |
516 | typedef struct literal_pool |
517 | { | |
55d9b4c1 | 518 | literal_expression literals[MAX_LITERAL_POOL_SIZE]; |
a06ea964 NC |
519 | unsigned int next_free_entry; |
520 | unsigned int id; | |
521 | symbolS *symbol; | |
522 | segT section; | |
523 | subsegT sub_section; | |
524 | int size; | |
525 | struct literal_pool *next; | |
526 | } literal_pool; | |
527 | ||
528 | /* Pointer to a linked list of literal pools. */ | |
529 | static literal_pool *list_of_pools = NULL; | |
530 | \f | |
531 | /* Pure syntax. */ | |
532 | ||
533 | /* This array holds the chars that always start a comment. If the | |
534 | pre-processor is disabled, these aren't very useful. */ | |
535 | const char comment_chars[] = ""; | |
536 | ||
537 | /* This array holds the chars that only start a comment at the beginning of | |
538 | a line. If the line seems to have the form '# 123 filename' | |
539 | .line and .file directives will appear in the pre-processed output. */ | |
540 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
541 | first line of the input file. This is because the compiler outputs | |
542 | #NO_APP at the beginning of its output. */ | |
543 | /* Also note that comments like this one will always work. */ | |
544 | const char line_comment_chars[] = "#"; | |
545 | ||
546 | const char line_separator_chars[] = ";"; | |
547 | ||
548 | /* Chars that can be used to separate mant | |
549 | from exp in floating point numbers. */ | |
550 | const char EXP_CHARS[] = "eE"; | |
551 | ||
552 | /* Chars that mean this number is a floating point constant. */ | |
553 | /* As in 0f12.456 */ | |
554 | /* or 0d1.2345e12 */ | |
555 | ||
b20d3859 | 556 | const char FLT_CHARS[] = "rRsSfFdDxXeEpPhH"; |
a06ea964 NC |
557 | |
558 | /* Prefix character that indicates the start of an immediate value. */ | |
559 | #define is_immediate_prefix(C) ((C) == '#') | |
560 | ||
561 | /* Separator character handling. */ | |
562 | ||
563 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
564 | ||
565 | static inline bfd_boolean | |
566 | skip_past_char (char **str, char c) | |
567 | { | |
568 | if (**str == c) | |
569 | { | |
570 | (*str)++; | |
571 | return TRUE; | |
572 | } | |
573 | else | |
574 | return FALSE; | |
575 | } | |
576 | ||
577 | #define skip_past_comma(str) skip_past_char (str, ',') | |
578 | ||
579 | /* Arithmetic expressions (possibly involving symbols). */ | |
580 | ||
a06ea964 NC |
581 | static bfd_boolean in_my_get_expression_p = FALSE; |
582 | ||
583 | /* Third argument to my_get_expression. */ | |
584 | #define GE_NO_PREFIX 0 | |
585 | #define GE_OPT_PREFIX 1 | |
586 | ||
587 | /* Return TRUE if the string pointed by *STR is successfully parsed | |
588 | as an valid expression; *EP will be filled with the information of | |
589 | such an expression. Otherwise return FALSE. */ | |
590 | ||
591 | static bfd_boolean | |
592 | my_get_expression (expressionS * ep, char **str, int prefix_mode, | |
593 | int reject_absent) | |
594 | { | |
595 | char *save_in; | |
596 | segT seg; | |
597 | int prefix_present_p = 0; | |
598 | ||
599 | switch (prefix_mode) | |
600 | { | |
601 | case GE_NO_PREFIX: | |
602 | break; | |
603 | case GE_OPT_PREFIX: | |
604 | if (is_immediate_prefix (**str)) | |
605 | { | |
606 | (*str)++; | |
607 | prefix_present_p = 1; | |
608 | } | |
609 | break; | |
610 | default: | |
611 | abort (); | |
612 | } | |
613 | ||
614 | memset (ep, 0, sizeof (expressionS)); | |
615 | ||
616 | save_in = input_line_pointer; | |
617 | input_line_pointer = *str; | |
618 | in_my_get_expression_p = TRUE; | |
619 | seg = expression (ep); | |
620 | in_my_get_expression_p = FALSE; | |
621 | ||
622 | if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent)) | |
623 | { | |
624 | /* We found a bad expression in md_operand(). */ | |
625 | *str = input_line_pointer; | |
626 | input_line_pointer = save_in; | |
627 | if (prefix_present_p && ! error_p ()) | |
628 | set_fatal_syntax_error (_("bad expression")); | |
629 | else | |
630 | set_first_syntax_error (_("bad expression")); | |
631 | return FALSE; | |
632 | } | |
633 | ||
634 | #ifdef OBJ_AOUT | |
635 | if (seg != absolute_section | |
636 | && seg != text_section | |
637 | && seg != data_section | |
638 | && seg != bss_section && seg != undefined_section) | |
639 | { | |
640 | set_syntax_error (_("bad segment")); | |
641 | *str = input_line_pointer; | |
642 | input_line_pointer = save_in; | |
643 | return FALSE; | |
644 | } | |
645 | #else | |
646 | (void) seg; | |
647 | #endif | |
648 | ||
a06ea964 NC |
649 | *str = input_line_pointer; |
650 | input_line_pointer = save_in; | |
651 | return TRUE; | |
652 | } | |
653 | ||
654 | /* Turn a string in input_line_pointer into a floating point constant | |
655 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
656 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
657 | returned, or NULL on OK. */ | |
658 | ||
6d4af3c2 | 659 | const char * |
a06ea964 NC |
660 | md_atof (int type, char *litP, int *sizeP) |
661 | { | |
eb5bbc48 MM |
662 | /* If this is a bfloat16 type, then parse it slightly differently - |
663 | as it does not follow the IEEE standard exactly. */ | |
664 | if (type == 'b') | |
665 | { | |
666 | char * t; | |
667 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
668 | FLONUM_TYPE generic_float; | |
669 | ||
670 | t = atof_ieee_detail (input_line_pointer, 1, 8, words, &generic_float); | |
671 | ||
672 | if (t) | |
673 | input_line_pointer = t; | |
674 | else | |
675 | return _("invalid floating point number"); | |
676 | ||
677 | switch (generic_float.sign) | |
678 | { | |
679 | /* Is +Inf. */ | |
680 | case 'P': | |
681 | words[0] = 0x7f80; | |
682 | break; | |
683 | ||
684 | /* Is -Inf. */ | |
685 | case 'N': | |
686 | words[0] = 0xff80; | |
687 | break; | |
688 | ||
689 | /* Is NaN. */ | |
690 | /* bfloat16 has two types of NaN - quiet and signalling. | |
691 | Quiet NaN has bit[6] == 1 && faction != 0, whereas | |
692 | signalling Nan's have bit[0] == 0 && fraction != 0. | |
693 | Chose this specific encoding as it is the same form | |
694 | as used by other IEEE 754 encodings in GAS. */ | |
695 | case 0: | |
696 | words[0] = 0x7fff; | |
697 | break; | |
698 | ||
699 | default: | |
700 | break; | |
701 | } | |
702 | ||
703 | *sizeP = 2; | |
704 | ||
705 | md_number_to_chars (litP, (valueT) words[0], sizeof (LITTLENUM_TYPE)); | |
706 | ||
707 | return NULL; | |
708 | } | |
709 | ||
a06ea964 NC |
710 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
711 | } | |
712 | ||
713 | /* We handle all bad expressions here, so that we can report the faulty | |
714 | instruction in the error message. */ | |
715 | void | |
716 | md_operand (expressionS * exp) | |
717 | { | |
718 | if (in_my_get_expression_p) | |
719 | exp->X_op = O_illegal; | |
720 | } | |
721 | ||
722 | /* Immediate values. */ | |
723 | ||
724 | /* Errors may be set multiple times during parsing or bit encoding | |
725 | (particularly in the Neon bits), but usually the earliest error which is set | |
726 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
727 | errors by calling this function. */ | |
728 | ||
729 | static void | |
730 | first_error (const char *error) | |
731 | { | |
732 | if (! error_p ()) | |
733 | set_syntax_error (error); | |
734 | } | |
735 | ||
2b0f3761 | 736 | /* Similar to first_error, but this function accepts formatted error |
a06ea964 NC |
737 | message. */ |
738 | static void | |
739 | first_error_fmt (const char *format, ...) | |
740 | { | |
741 | va_list args; | |
742 | enum | |
743 | { size = 100 }; | |
744 | /* N.B. this single buffer will not cause error messages for different | |
745 | instructions to pollute each other; this is because at the end of | |
746 | processing of each assembly line, error message if any will be | |
747 | collected by as_bad. */ | |
748 | static char buffer[size]; | |
749 | ||
750 | if (! error_p ()) | |
751 | { | |
3e0baa28 | 752 | int ret ATTRIBUTE_UNUSED; |
a06ea964 NC |
753 | va_start (args, format); |
754 | ret = vsnprintf (buffer, size, format, args); | |
755 | know (ret <= size - 1 && ret >= 0); | |
756 | va_end (args); | |
757 | set_syntax_error (buffer); | |
758 | } | |
759 | } | |
760 | ||
761 | /* Register parsing. */ | |
762 | ||
763 | /* Generic register parser which is called by other specialized | |
764 | register parsers. | |
765 | CCP points to what should be the beginning of a register name. | |
766 | If it is indeed a valid register name, advance CCP over it and | |
767 | return the reg_entry structure; otherwise return NULL. | |
768 | It does not issue diagnostics. */ | |
769 | ||
770 | static reg_entry * | |
771 | parse_reg (char **ccp) | |
772 | { | |
773 | char *start = *ccp; | |
774 | char *p; | |
775 | reg_entry *reg; | |
776 | ||
777 | #ifdef REGISTER_PREFIX | |
778 | if (*start != REGISTER_PREFIX) | |
779 | return NULL; | |
780 | start++; | |
781 | #endif | |
782 | ||
783 | p = start; | |
784 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
785 | return NULL; | |
786 | ||
787 | do | |
788 | p++; | |
789 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
790 | ||
629310ab | 791 | reg = (reg_entry *) str_hash_find_n (aarch64_reg_hsh, start, p - start); |
a06ea964 NC |
792 | |
793 | if (!reg) | |
794 | return NULL; | |
795 | ||
796 | *ccp = p; | |
797 | return reg; | |
798 | } | |
799 | ||
800 | /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise | |
801 | return FALSE. */ | |
802 | static bfd_boolean | |
803 | aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type) | |
804 | { | |
e1b988bb | 805 | return (reg_type_masks[type] & (1 << reg->type)) != 0; |
a06ea964 NC |
806 | } |
807 | ||
4df068de RS |
808 | /* Try to parse a base or offset register. Allow SVE base and offset |
809 | registers if REG_TYPE includes SVE registers. Return the register | |
810 | entry on success, setting *QUALIFIER to the register qualifier. | |
811 | Return null otherwise. | |
e1b988bb | 812 | |
a06ea964 NC |
813 | Note that this function does not issue any diagnostics. */ |
814 | ||
e1b988bb | 815 | static const reg_entry * |
4df068de RS |
816 | aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type, |
817 | aarch64_opnd_qualifier_t *qualifier) | |
a06ea964 NC |
818 | { |
819 | char *str = *ccp; | |
820 | const reg_entry *reg = parse_reg (&str); | |
821 | ||
822 | if (reg == NULL) | |
e1b988bb | 823 | return NULL; |
a06ea964 NC |
824 | |
825 | switch (reg->type) | |
826 | { | |
e1b988bb | 827 | case REG_TYPE_R_32: |
a06ea964 | 828 | case REG_TYPE_SP_32: |
e1b988bb RS |
829 | case REG_TYPE_Z_32: |
830 | *qualifier = AARCH64_OPND_QLF_W; | |
a06ea964 | 831 | break; |
e1b988bb | 832 | |
a06ea964 | 833 | case REG_TYPE_R_64: |
e1b988bb | 834 | case REG_TYPE_SP_64: |
a06ea964 | 835 | case REG_TYPE_Z_64: |
e1b988bb | 836 | *qualifier = AARCH64_OPND_QLF_X; |
a06ea964 | 837 | break; |
e1b988bb | 838 | |
4df068de RS |
839 | case REG_TYPE_ZN: |
840 | if ((reg_type_masks[reg_type] & (1 << REG_TYPE_ZN)) == 0 | |
841 | || str[0] != '.') | |
842 | return NULL; | |
843 | switch (TOLOWER (str[1])) | |
844 | { | |
845 | case 's': | |
846 | *qualifier = AARCH64_OPND_QLF_S_S; | |
847 | break; | |
848 | case 'd': | |
849 | *qualifier = AARCH64_OPND_QLF_S_D; | |
850 | break; | |
851 | default: | |
852 | return NULL; | |
853 | } | |
854 | str += 2; | |
855 | break; | |
856 | ||
3493da5c SP |
857 | case REG_TYPE_CA_N: |
858 | case REG_TYPE_CA_SP: | |
859 | *qualifier = AARCH64_OPND_QLF_CA; | |
860 | break; | |
861 | ||
a06ea964 | 862 | default: |
e1b988bb | 863 | return NULL; |
a06ea964 NC |
864 | } |
865 | ||
866 | *ccp = str; | |
867 | ||
e1b988bb | 868 | return reg; |
a06ea964 NC |
869 | } |
870 | ||
4df068de RS |
871 | /* Try to parse a base or offset register. Return the register entry |
872 | on success, setting *QUALIFIER to the register qualifier. Return null | |
873 | otherwise. | |
874 | ||
875 | Note that this function does not issue any diagnostics. */ | |
876 | ||
877 | static const reg_entry * | |
878 | aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier) | |
879 | { | |
880 | return aarch64_addr_reg_parse (ccp, REG_TYPE_R_Z_SP, qualifier); | |
881 | } | |
882 | ||
f11ad6bc RS |
883 | /* Parse the qualifier of a vector register or vector element of type |
884 | REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing | |
885 | succeeds; otherwise return FALSE. | |
a06ea964 NC |
886 | |
887 | Accept only one occurrence of: | |
65a55fbb | 888 | 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d |
a06ea964 NC |
889 | b h s d q */ |
890 | static bfd_boolean | |
f11ad6bc RS |
891 | parse_vector_type_for_operand (aarch64_reg_type reg_type, |
892 | struct vector_type_el *parsed_type, char **str) | |
a06ea964 NC |
893 | { |
894 | char *ptr = *str; | |
895 | unsigned width; | |
896 | unsigned element_size; | |
f06935a5 | 897 | enum vector_el_type type; |
a06ea964 NC |
898 | |
899 | /* skip '.' */ | |
d50c751e | 900 | gas_assert (*ptr == '.'); |
a06ea964 NC |
901 | ptr++; |
902 | ||
f11ad6bc | 903 | if (reg_type == REG_TYPE_ZN || reg_type == REG_TYPE_PN || !ISDIGIT (*ptr)) |
a06ea964 NC |
904 | { |
905 | width = 0; | |
906 | goto elt_size; | |
907 | } | |
908 | width = strtoul (ptr, &ptr, 10); | |
909 | if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16) | |
910 | { | |
911 | first_error_fmt (_("bad size %d in vector width specifier"), width); | |
912 | return FALSE; | |
913 | } | |
914 | ||
dc1e8a47 | 915 | elt_size: |
a06ea964 NC |
916 | switch (TOLOWER (*ptr)) |
917 | { | |
918 | case 'b': | |
919 | type = NT_b; | |
920 | element_size = 8; | |
921 | break; | |
922 | case 'h': | |
923 | type = NT_h; | |
924 | element_size = 16; | |
925 | break; | |
926 | case 's': | |
927 | type = NT_s; | |
928 | element_size = 32; | |
929 | break; | |
930 | case 'd': | |
931 | type = NT_d; | |
932 | element_size = 64; | |
933 | break; | |
934 | case 'q': | |
582e12bf | 935 | if (reg_type == REG_TYPE_ZN || width == 1) |
a06ea964 NC |
936 | { |
937 | type = NT_q; | |
938 | element_size = 128; | |
939 | break; | |
940 | } | |
941 | /* fall through. */ | |
942 | default: | |
943 | if (*ptr != '\0') | |
944 | first_error_fmt (_("unexpected character `%c' in element size"), *ptr); | |
945 | else | |
946 | first_error (_("missing element size")); | |
947 | return FALSE; | |
948 | } | |
65a55fbb TC |
949 | if (width != 0 && width * element_size != 64 |
950 | && width * element_size != 128 | |
951 | && !(width == 2 && element_size == 16) | |
952 | && !(width == 4 && element_size == 8)) | |
a06ea964 NC |
953 | { |
954 | first_error_fmt (_ | |
955 | ("invalid element size %d and vector size combination %c"), | |
956 | width, *ptr); | |
957 | return FALSE; | |
958 | } | |
959 | ptr++; | |
960 | ||
961 | parsed_type->type = type; | |
962 | parsed_type->width = width; | |
963 | ||
964 | *str = ptr; | |
965 | ||
966 | return TRUE; | |
967 | } | |
968 | ||
d50c751e RS |
969 | /* *STR contains an SVE zero/merge predication suffix. Parse it into |
970 | *PARSED_TYPE and point *STR at the end of the suffix. */ | |
971 | ||
972 | static bfd_boolean | |
973 | parse_predication_for_operand (struct vector_type_el *parsed_type, char **str) | |
974 | { | |
975 | char *ptr = *str; | |
976 | ||
977 | /* Skip '/'. */ | |
978 | gas_assert (*ptr == '/'); | |
979 | ptr++; | |
980 | switch (TOLOWER (*ptr)) | |
981 | { | |
982 | case 'z': | |
983 | parsed_type->type = NT_zero; | |
984 | break; | |
985 | case 'm': | |
986 | parsed_type->type = NT_merge; | |
987 | break; | |
988 | default: | |
989 | if (*ptr != '\0' && *ptr != ',') | |
990 | first_error_fmt (_("unexpected character `%c' in predication type"), | |
991 | *ptr); | |
992 | else | |
993 | first_error (_("missing predication type")); | |
994 | return FALSE; | |
995 | } | |
996 | parsed_type->width = 0; | |
997 | *str = ptr + 1; | |
998 | return TRUE; | |
999 | } | |
1000 | ||
a06ea964 NC |
1001 | /* Parse a register of the type TYPE. |
1002 | ||
1003 | Return PARSE_FAIL if the string pointed by *CCP is not a valid register | |
1004 | name or the parsed register is not of TYPE. | |
1005 | ||
1006 | Otherwise return the register number, and optionally fill in the actual | |
1007 | type of the register in *RTYPE when multiple alternatives were given, and | |
1008 | return the register shape and element index information in *TYPEINFO. | |
1009 | ||
1010 | IN_REG_LIST should be set with TRUE if the caller is parsing a register | |
1011 | list. */ | |
1012 | ||
1013 | static int | |
1014 | parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype, | |
8f9a77af | 1015 | struct vector_type_el *typeinfo, bfd_boolean in_reg_list) |
a06ea964 NC |
1016 | { |
1017 | char *str = *ccp; | |
1018 | const reg_entry *reg = parse_reg (&str); | |
8f9a77af RS |
1019 | struct vector_type_el atype; |
1020 | struct vector_type_el parsetype; | |
a06ea964 NC |
1021 | bfd_boolean is_typed_vecreg = FALSE; |
1022 | ||
1023 | atype.defined = 0; | |
1024 | atype.type = NT_invtype; | |
1025 | atype.width = -1; | |
1026 | atype.index = 0; | |
1027 | ||
1028 | if (reg == NULL) | |
1029 | { | |
1030 | if (typeinfo) | |
1031 | *typeinfo = atype; | |
1032 | set_default_error (); | |
1033 | return PARSE_FAIL; | |
1034 | } | |
1035 | ||
1036 | if (! aarch64_check_reg_type (reg, type)) | |
1037 | { | |
1038 | DEBUG_TRACE ("reg type check failed"); | |
1039 | set_default_error (); | |
1040 | return PARSE_FAIL; | |
1041 | } | |
1042 | type = reg->type; | |
1043 | ||
f11ad6bc | 1044 | if ((type == REG_TYPE_VN || type == REG_TYPE_ZN || type == REG_TYPE_PN) |
d50c751e | 1045 | && (*str == '.' || (type == REG_TYPE_PN && *str == '/'))) |
a06ea964 | 1046 | { |
d50c751e RS |
1047 | if (*str == '.') |
1048 | { | |
1049 | if (!parse_vector_type_for_operand (type, &parsetype, &str)) | |
1050 | return PARSE_FAIL; | |
1051 | } | |
1052 | else | |
1053 | { | |
1054 | if (!parse_predication_for_operand (&parsetype, &str)) | |
1055 | return PARSE_FAIL; | |
1056 | } | |
a235d3ae | 1057 | |
a06ea964 NC |
1058 | /* Register if of the form Vn.[bhsdq]. */ |
1059 | is_typed_vecreg = TRUE; | |
1060 | ||
f11ad6bc RS |
1061 | if (type == REG_TYPE_ZN || type == REG_TYPE_PN) |
1062 | { | |
1063 | /* The width is always variable; we don't allow an integer width | |
1064 | to be specified. */ | |
1065 | gas_assert (parsetype.width == 0); | |
1066 | atype.defined |= NTA_HASVARWIDTH | NTA_HASTYPE; | |
1067 | } | |
1068 | else if (parsetype.width == 0) | |
a06ea964 NC |
1069 | /* Expect index. In the new scheme we cannot have |
1070 | Vn.[bhsdq] represent a scalar. Therefore any | |
1071 | Vn.[bhsdq] should have an index following it. | |
33eaf5de | 1072 | Except in reglists of course. */ |
a06ea964 NC |
1073 | atype.defined |= NTA_HASINDEX; |
1074 | else | |
1075 | atype.defined |= NTA_HASTYPE; | |
1076 | ||
1077 | atype.type = parsetype.type; | |
1078 | atype.width = parsetype.width; | |
1079 | } | |
1080 | ||
1081 | if (skip_past_char (&str, '[')) | |
1082 | { | |
1083 | expressionS exp; | |
1084 | ||
1085 | /* Reject Sn[index] syntax. */ | |
1086 | if (!is_typed_vecreg) | |
1087 | { | |
1088 | first_error (_("this type of register can't be indexed")); | |
1089 | return PARSE_FAIL; | |
1090 | } | |
1091 | ||
535b785f | 1092 | if (in_reg_list) |
a06ea964 NC |
1093 | { |
1094 | first_error (_("index not allowed inside register list")); | |
1095 | return PARSE_FAIL; | |
1096 | } | |
1097 | ||
1098 | atype.defined |= NTA_HASINDEX; | |
1099 | ||
1100 | my_get_expression (&exp, &str, GE_NO_PREFIX, 1); | |
1101 | ||
1102 | if (exp.X_op != O_constant) | |
1103 | { | |
1104 | first_error (_("constant expression required")); | |
1105 | return PARSE_FAIL; | |
1106 | } | |
1107 | ||
1108 | if (! skip_past_char (&str, ']')) | |
1109 | return PARSE_FAIL; | |
1110 | ||
1111 | atype.index = exp.X_add_number; | |
1112 | } | |
1113 | else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0) | |
1114 | { | |
1115 | /* Indexed vector register expected. */ | |
1116 | first_error (_("indexed vector register expected")); | |
1117 | return PARSE_FAIL; | |
1118 | } | |
1119 | ||
1120 | /* A vector reg Vn should be typed or indexed. */ | |
1121 | if (type == REG_TYPE_VN && atype.defined == 0) | |
1122 | { | |
1123 | first_error (_("invalid use of vector register")); | |
1124 | } | |
1125 | ||
1126 | if (typeinfo) | |
1127 | *typeinfo = atype; | |
1128 | ||
1129 | if (rtype) | |
1130 | *rtype = type; | |
1131 | ||
1132 | *ccp = str; | |
1133 | ||
1134 | return reg->number; | |
1135 | } | |
1136 | ||
1137 | /* Parse register. | |
1138 | ||
1139 | Return the register number on success; return PARSE_FAIL otherwise. | |
1140 | ||
1141 | If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of | |
1142 | the register (e.g. NEON double or quad reg when either has been requested). | |
1143 | ||
1144 | If this is a NEON vector register with additional type information, fill | |
1145 | in the struct pointed to by VECTYPE (if non-NULL). | |
1146 | ||
1147 | This parser does not handle register list. */ | |
1148 | ||
1149 | static int | |
1150 | aarch64_reg_parse (char **ccp, aarch64_reg_type type, | |
8f9a77af | 1151 | aarch64_reg_type *rtype, struct vector_type_el *vectype) |
a06ea964 | 1152 | { |
8f9a77af | 1153 | struct vector_type_el atype; |
a06ea964 NC |
1154 | char *str = *ccp; |
1155 | int reg = parse_typed_reg (&str, type, rtype, &atype, | |
1156 | /*in_reg_list= */ FALSE); | |
1157 | ||
1158 | if (reg == PARSE_FAIL) | |
1159 | return PARSE_FAIL; | |
1160 | ||
1161 | if (vectype) | |
1162 | *vectype = atype; | |
1163 | ||
1164 | *ccp = str; | |
1165 | ||
1166 | return reg; | |
1167 | } | |
1168 | ||
1169 | static inline bfd_boolean | |
8f9a77af | 1170 | eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2) |
a06ea964 NC |
1171 | { |
1172 | return | |
1173 | e1.type == e2.type | |
1174 | && e1.defined == e2.defined | |
1175 | && e1.width == e2.width && e1.index == e2.index; | |
1176 | } | |
1177 | ||
10d76650 RS |
1178 | /* This function parses a list of vector registers of type TYPE. |
1179 | On success, it returns the parsed register list information in the | |
1180 | following encoded format: | |
a06ea964 NC |
1181 | |
1182 | bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1 | |
1183 | 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg | |
1184 | ||
1185 | The information of the register shape and/or index is returned in | |
1186 | *VECTYPE. | |
1187 | ||
1188 | It returns PARSE_FAIL if the register list is invalid. | |
1189 | ||
1190 | The list contains one to four registers. | |
1191 | Each register can be one of: | |
1192 | <Vt>.<T>[<index>] | |
1193 | <Vt>.<T> | |
1194 | All <T> should be identical. | |
1195 | All <index> should be identical. | |
1196 | There are restrictions on <Vt> numbers which are checked later | |
1197 | (by reg_list_valid_p). */ | |
1198 | ||
1199 | static int | |
10d76650 RS |
1200 | parse_vector_reg_list (char **ccp, aarch64_reg_type type, |
1201 | struct vector_type_el *vectype) | |
a06ea964 NC |
1202 | { |
1203 | char *str = *ccp; | |
1204 | int nb_regs; | |
8f9a77af | 1205 | struct vector_type_el typeinfo, typeinfo_first; |
a06ea964 NC |
1206 | int val, val_range; |
1207 | int in_range; | |
1208 | int ret_val; | |
1209 | int i; | |
1210 | bfd_boolean error = FALSE; | |
1211 | bfd_boolean expect_index = FALSE; | |
1212 | ||
1213 | if (*str != '{') | |
1214 | { | |
1215 | set_syntax_error (_("expecting {")); | |
1216 | return PARSE_FAIL; | |
1217 | } | |
1218 | str++; | |
1219 | ||
1220 | nb_regs = 0; | |
1221 | typeinfo_first.defined = 0; | |
1222 | typeinfo_first.type = NT_invtype; | |
1223 | typeinfo_first.width = -1; | |
1224 | typeinfo_first.index = 0; | |
1225 | ret_val = 0; | |
1226 | val = -1; | |
1227 | val_range = -1; | |
1228 | in_range = 0; | |
1229 | do | |
1230 | { | |
1231 | if (in_range) | |
1232 | { | |
1233 | str++; /* skip over '-' */ | |
1234 | val_range = val; | |
1235 | } | |
10d76650 | 1236 | val = parse_typed_reg (&str, type, NULL, &typeinfo, |
a06ea964 NC |
1237 | /*in_reg_list= */ TRUE); |
1238 | if (val == PARSE_FAIL) | |
1239 | { | |
1240 | set_first_syntax_error (_("invalid vector register in list")); | |
1241 | error = TRUE; | |
1242 | continue; | |
1243 | } | |
1244 | /* reject [bhsd]n */ | |
f11ad6bc | 1245 | if (type == REG_TYPE_VN && typeinfo.defined == 0) |
a06ea964 NC |
1246 | { |
1247 | set_first_syntax_error (_("invalid scalar register in list")); | |
1248 | error = TRUE; | |
1249 | continue; | |
1250 | } | |
1251 | ||
1252 | if (typeinfo.defined & NTA_HASINDEX) | |
1253 | expect_index = TRUE; | |
1254 | ||
1255 | if (in_range) | |
1256 | { | |
1257 | if (val < val_range) | |
1258 | { | |
1259 | set_first_syntax_error | |
1260 | (_("invalid range in vector register list")); | |
1261 | error = TRUE; | |
1262 | } | |
1263 | val_range++; | |
1264 | } | |
1265 | else | |
1266 | { | |
1267 | val_range = val; | |
1268 | if (nb_regs == 0) | |
1269 | typeinfo_first = typeinfo; | |
8f9a77af | 1270 | else if (! eq_vector_type_el (typeinfo_first, typeinfo)) |
a06ea964 NC |
1271 | { |
1272 | set_first_syntax_error | |
1273 | (_("type mismatch in vector register list")); | |
1274 | error = TRUE; | |
1275 | } | |
1276 | } | |
1277 | if (! error) | |
1278 | for (i = val_range; i <= val; i++) | |
1279 | { | |
1280 | ret_val |= i << (5 * nb_regs); | |
1281 | nb_regs++; | |
1282 | } | |
1283 | in_range = 0; | |
1284 | } | |
1285 | while (skip_past_comma (&str) || (in_range = 1, *str == '-')); | |
1286 | ||
1287 | skip_whitespace (str); | |
1288 | if (*str != '}') | |
1289 | { | |
1290 | set_first_syntax_error (_("end of vector register list not found")); | |
1291 | error = TRUE; | |
1292 | } | |
1293 | str++; | |
1294 | ||
1295 | skip_whitespace (str); | |
1296 | ||
1297 | if (expect_index) | |
1298 | { | |
1299 | if (skip_past_char (&str, '[')) | |
1300 | { | |
1301 | expressionS exp; | |
1302 | ||
1303 | my_get_expression (&exp, &str, GE_NO_PREFIX, 1); | |
1304 | if (exp.X_op != O_constant) | |
1305 | { | |
1306 | set_first_syntax_error (_("constant expression required.")); | |
1307 | error = TRUE; | |
1308 | } | |
1309 | if (! skip_past_char (&str, ']')) | |
1310 | error = TRUE; | |
1311 | else | |
1312 | typeinfo_first.index = exp.X_add_number; | |
1313 | } | |
1314 | else | |
1315 | { | |
1316 | set_first_syntax_error (_("expected index")); | |
1317 | error = TRUE; | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | if (nb_regs > 4) | |
1322 | { | |
1323 | set_first_syntax_error (_("too many registers in vector register list")); | |
1324 | error = TRUE; | |
1325 | } | |
1326 | else if (nb_regs == 0) | |
1327 | { | |
1328 | set_first_syntax_error (_("empty vector register list")); | |
1329 | error = TRUE; | |
1330 | } | |
1331 | ||
1332 | *ccp = str; | |
1333 | if (! error) | |
1334 | *vectype = typeinfo_first; | |
1335 | ||
1336 | return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1); | |
1337 | } | |
1338 | ||
1339 | /* Directives: register aliases. */ | |
1340 | ||
1341 | static reg_entry * | |
1342 | insert_reg_alias (char *str, int number, aarch64_reg_type type) | |
1343 | { | |
1344 | reg_entry *new; | |
1345 | const char *name; | |
1346 | ||
629310ab | 1347 | if ((new = str_hash_find (aarch64_reg_hsh, str)) != 0) |
a06ea964 NC |
1348 | { |
1349 | if (new->builtin) | |
1350 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), | |
1351 | str); | |
1352 | ||
1353 | /* Only warn about a redefinition if it's not defined as the | |
1354 | same register. */ | |
1355 | else if (new->number != number || new->type != type) | |
1356 | as_warn (_("ignoring redefinition of register alias '%s'"), str); | |
1357 | ||
1358 | return NULL; | |
1359 | } | |
1360 | ||
1361 | name = xstrdup (str); | |
add39d23 | 1362 | new = XNEW (reg_entry); |
a06ea964 NC |
1363 | |
1364 | new->name = name; | |
1365 | new->number = number; | |
1366 | new->type = type; | |
1367 | new->builtin = FALSE; | |
1368 | ||
fe0e921f | 1369 | str_hash_insert (aarch64_reg_hsh, name, new, 0); |
a06ea964 NC |
1370 | |
1371 | return new; | |
1372 | } | |
1373 | ||
1374 | /* Look for the .req directive. This is of the form: | |
1375 | ||
1376 | new_register_name .req existing_register_name | |
1377 | ||
1378 | If we find one, or if it looks sufficiently like one that we want to | |
1379 | handle any error here, return TRUE. Otherwise return FALSE. */ | |
1380 | ||
1381 | static bfd_boolean | |
1382 | create_register_alias (char *newname, char *p) | |
1383 | { | |
1384 | const reg_entry *old; | |
1385 | char *oldname, *nbuf; | |
1386 | size_t nlen; | |
1387 | ||
1388 | /* The input scrubber ensures that whitespace after the mnemonic is | |
1389 | collapsed to single spaces. */ | |
1390 | oldname = p; | |
1391 | if (strncmp (oldname, " .req ", 6) != 0) | |
1392 | return FALSE; | |
1393 | ||
1394 | oldname += 6; | |
1395 | if (*oldname == '\0') | |
1396 | return FALSE; | |
1397 | ||
629310ab | 1398 | old = str_hash_find (aarch64_reg_hsh, oldname); |
a06ea964 NC |
1399 | if (!old) |
1400 | { | |
1401 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); | |
1402 | return TRUE; | |
1403 | } | |
1404 | ||
1405 | /* If TC_CASE_SENSITIVE is defined, then newname already points to | |
1406 | the desired alias name, and p points to its end. If not, then | |
1407 | the desired alias name is in the global original_case_string. */ | |
1408 | #ifdef TC_CASE_SENSITIVE | |
1409 | nlen = p - newname; | |
1410 | #else | |
1411 | newname = original_case_string; | |
1412 | nlen = strlen (newname); | |
1413 | #endif | |
1414 | ||
29a2809e | 1415 | nbuf = xmemdup0 (newname, nlen); |
a06ea964 NC |
1416 | |
1417 | /* Create aliases under the new name as stated; an all-lowercase | |
1418 | version of the new name; and an all-uppercase version of the new | |
1419 | name. */ | |
1420 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) | |
1421 | { | |
1422 | for (p = nbuf; *p; p++) | |
1423 | *p = TOUPPER (*p); | |
1424 | ||
1425 | if (strncmp (nbuf, newname, nlen)) | |
1426 | { | |
1427 | /* If this attempt to create an additional alias fails, do not bother | |
1428 | trying to create the all-lower case alias. We will fail and issue | |
1429 | a second, duplicate error message. This situation arises when the | |
1430 | programmer does something like: | |
1431 | foo .req r0 | |
1432 | Foo .req r1 | |
1433 | The second .req creates the "Foo" alias but then fails to create | |
1434 | the artificial FOO alias because it has already been created by the | |
1435 | first .req. */ | |
1436 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
e1fa0163 NC |
1437 | { |
1438 | free (nbuf); | |
1439 | return TRUE; | |
1440 | } | |
a06ea964 NC |
1441 | } |
1442 | ||
1443 | for (p = nbuf; *p; p++) | |
1444 | *p = TOLOWER (*p); | |
1445 | ||
1446 | if (strncmp (nbuf, newname, nlen)) | |
1447 | insert_reg_alias (nbuf, old->number, old->type); | |
1448 | } | |
1449 | ||
e1fa0163 | 1450 | free (nbuf); |
a06ea964 NC |
1451 | return TRUE; |
1452 | } | |
1453 | ||
1454 | /* Should never be called, as .req goes between the alias and the | |
1455 | register name, not at the beginning of the line. */ | |
1456 | static void | |
1457 | s_req (int a ATTRIBUTE_UNUSED) | |
1458 | { | |
1459 | as_bad (_("invalid syntax for .req directive")); | |
1460 | } | |
1461 | ||
1462 | /* The .unreq directive deletes an alias which was previously defined | |
1463 | by .req. For example: | |
1464 | ||
1465 | my_alias .req r11 | |
1466 | .unreq my_alias */ | |
1467 | ||
1468 | static void | |
1469 | s_unreq (int a ATTRIBUTE_UNUSED) | |
1470 | { | |
1471 | char *name; | |
1472 | char saved_char; | |
1473 | ||
1474 | name = input_line_pointer; | |
1475 | ||
1476 | while (*input_line_pointer != 0 | |
1477 | && *input_line_pointer != ' ' && *input_line_pointer != '\n') | |
1478 | ++input_line_pointer; | |
1479 | ||
1480 | saved_char = *input_line_pointer; | |
1481 | *input_line_pointer = 0; | |
1482 | ||
1483 | if (!*name) | |
1484 | as_bad (_("invalid syntax for .unreq directive")); | |
1485 | else | |
1486 | { | |
629310ab | 1487 | reg_entry *reg = str_hash_find (aarch64_reg_hsh, name); |
a06ea964 NC |
1488 | |
1489 | if (!reg) | |
1490 | as_bad (_("unknown register alias '%s'"), name); | |
1491 | else if (reg->builtin) | |
1492 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
1493 | name); | |
1494 | else | |
1495 | { | |
1496 | char *p; | |
1497 | char *nbuf; | |
1498 | ||
629310ab | 1499 | str_hash_delete (aarch64_reg_hsh, name); |
a06ea964 NC |
1500 | free ((char *) reg->name); |
1501 | free (reg); | |
1502 | ||
1503 | /* Also locate the all upper case and all lower case versions. | |
1504 | Do not complain if we cannot find one or the other as it | |
1505 | was probably deleted above. */ | |
1506 | ||
1507 | nbuf = strdup (name); | |
1508 | for (p = nbuf; *p; p++) | |
1509 | *p = TOUPPER (*p); | |
629310ab | 1510 | reg = str_hash_find (aarch64_reg_hsh, nbuf); |
a06ea964 NC |
1511 | if (reg) |
1512 | { | |
629310ab | 1513 | str_hash_delete (aarch64_reg_hsh, nbuf); |
a06ea964 NC |
1514 | free ((char *) reg->name); |
1515 | free (reg); | |
1516 | } | |
1517 | ||
1518 | for (p = nbuf; *p; p++) | |
1519 | *p = TOLOWER (*p); | |
629310ab | 1520 | reg = str_hash_find (aarch64_reg_hsh, nbuf); |
a06ea964 NC |
1521 | if (reg) |
1522 | { | |
629310ab | 1523 | str_hash_delete (aarch64_reg_hsh, nbuf); |
a06ea964 NC |
1524 | free ((char *) reg->name); |
1525 | free (reg); | |
1526 | } | |
1527 | ||
1528 | free (nbuf); | |
1529 | } | |
1530 | } | |
1531 | ||
1532 | *input_line_pointer = saved_char; | |
1533 | demand_empty_rest_of_line (); | |
1534 | } | |
1535 | ||
1536 | /* Directives: Instruction set selection. */ | |
1537 | ||
1538 | #ifdef OBJ_ELF | |
1539 | /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF | |
1540 | spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05). | |
1541 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
1542 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
1543 | ||
1544 | /* Create a new mapping symbol for the transition to STATE. */ | |
1545 | ||
1546 | static void | |
1547 | make_mapping_symbol (enum mstate state, valueT value, fragS * frag) | |
1548 | { | |
1549 | symbolS *symbolP; | |
1550 | const char *symname; | |
1551 | int type; | |
1552 | ||
1553 | switch (state) | |
1554 | { | |
1555 | case MAP_DATA: | |
1556 | symname = "$d"; | |
1557 | type = BSF_NO_FLAGS; | |
1558 | break; | |
1559 | case MAP_INSN: | |
1560 | symname = "$x"; | |
1561 | type = BSF_NO_FLAGS; | |
1562 | break; | |
3979cf50 SP |
1563 | case MAP_C64: |
1564 | symname = "$c"; | |
1565 | type = BSF_NO_FLAGS; | |
1566 | break; | |
a06ea964 NC |
1567 | default: |
1568 | abort (); | |
1569 | } | |
1570 | ||
e01e1cee | 1571 | symbolP = symbol_new (symname, now_seg, frag, value); |
a06ea964 NC |
1572 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
1573 | ||
8b21361b SP |
1574 | if (state == MAP_C64) |
1575 | AARCH64_SET_C64 (symbolP, 1); | |
1576 | else if (state == MAP_INSN) | |
1577 | AARCH64_SET_C64 (symbolP, 0); | |
1578 | ||
a06ea964 NC |
1579 | /* Save the mapping symbols for future reference. Also check that |
1580 | we do not place two mapping symbols at the same offset within a | |
1581 | frag. We'll handle overlap between frags in | |
1582 | check_mapping_symbols. | |
1583 | ||
1584 | If .fill or other data filling directive generates zero sized data, | |
1585 | the mapping symbol for the following code will have the same value | |
1586 | as the one generated for the data filling directive. In this case, | |
1587 | we replace the old symbol with the new one at the same address. */ | |
1588 | if (value == 0) | |
1589 | { | |
1590 | if (frag->tc_frag_data.first_map != NULL) | |
1591 | { | |
1592 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
1593 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, | |
1594 | &symbol_lastP); | |
1595 | } | |
1596 | frag->tc_frag_data.first_map = symbolP; | |
1597 | } | |
1598 | if (frag->tc_frag_data.last_map != NULL) | |
1599 | { | |
1600 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= | |
1601 | S_GET_VALUE (symbolP)); | |
1602 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) | |
1603 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, | |
1604 | &symbol_lastP); | |
1605 | } | |
1606 | frag->tc_frag_data.last_map = symbolP; | |
1607 | } | |
1608 | ||
1609 | /* We must sometimes convert a region marked as code to data during | |
1610 | code alignment, if an odd number of bytes have to be padded. The | |
1611 | code mapping symbol is pushed to an aligned address. */ | |
1612 | ||
1613 | static void | |
1614 | insert_data_mapping_symbol (enum mstate state, | |
1615 | valueT value, fragS * frag, offsetT bytes) | |
1616 | { | |
1617 | /* If there was already a mapping symbol, remove it. */ | |
1618 | if (frag->tc_frag_data.last_map != NULL | |
1619 | && S_GET_VALUE (frag->tc_frag_data.last_map) == | |
1620 | frag->fr_address + value) | |
1621 | { | |
1622 | symbolS *symp = frag->tc_frag_data.last_map; | |
1623 | ||
1624 | if (value == 0) | |
1625 | { | |
1626 | know (frag->tc_frag_data.first_map == symp); | |
1627 | frag->tc_frag_data.first_map = NULL; | |
1628 | } | |
1629 | frag->tc_frag_data.last_map = NULL; | |
1630 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
1631 | } | |
1632 | ||
1633 | make_mapping_symbol (MAP_DATA, value, frag); | |
1634 | make_mapping_symbol (state, value + bytes, frag); | |
1635 | } | |
1636 | ||
1637 | static void mapping_state_2 (enum mstate state, int max_chars); | |
1638 | ||
1639 | /* Set the mapping state to STATE. Only call this when about to | |
1640 | emit some STATE bytes to the file. */ | |
1641 | ||
1642 | void | |
1643 | mapping_state (enum mstate state) | |
1644 | { | |
1645 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; | |
1646 | ||
3979cf50 | 1647 | if (state == MAP_CUR_INSN) |
a578ef7e JW |
1648 | /* AArch64 instructions require 4-byte alignment. When emitting |
1649 | instructions into any section, record the appropriate section | |
1650 | alignment. */ | |
1651 | record_alignment (now_seg, 2); | |
1652 | ||
448eb63d RL |
1653 | if (mapstate == state) |
1654 | /* The mapping symbol has already been emitted. | |
1655 | There is nothing else to do. */ | |
1656 | return; | |
1657 | ||
c1baaddf | 1658 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
a97902de RL |
1659 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA) && !subseg_text_p (now_seg)) |
1660 | /* Emit MAP_DATA within executable section in order. Otherwise, it will be | |
c1baaddf | 1661 | evaluated later in the next else. */ |
a06ea964 | 1662 | return; |
3979cf50 | 1663 | else if (TRANSITION (MAP_UNDEFINED, MAP_CUR_INSN)) |
c1baaddf RL |
1664 | { |
1665 | /* Only add the symbol if the offset is > 0: | |
1666 | if we're at the first frag, check it's size > 0; | |
1667 | if we're not at the first frag, then for sure | |
1668 | the offset is > 0. */ | |
1669 | struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
1670 | const int add_symbol = (frag_now != frag_first) | |
1671 | || (frag_now_fix () > 0); | |
1672 | ||
1673 | if (add_symbol) | |
1674 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
1675 | } | |
1676 | #undef TRANSITION | |
a06ea964 NC |
1677 | |
1678 | mapping_state_2 (state, 0); | |
a06ea964 NC |
1679 | } |
1680 | ||
1681 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
1682 | allocated. Put the mapping symbol that far back. */ | |
1683 | ||
1684 | static void | |
1685 | mapping_state_2 (enum mstate state, int max_chars) | |
1686 | { | |
1687 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; | |
1688 | ||
1689 | if (!SEG_NORMAL (now_seg)) | |
1690 | return; | |
1691 | ||
1692 | if (mapstate == state) | |
1693 | /* The mapping symbol has already been emitted. | |
1694 | There is nothing else to do. */ | |
1695 | return; | |
1696 | ||
1697 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; | |
1698 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
1699 | } | |
1700 | #else | |
1701 | #define mapping_state(x) /* nothing */ | |
1702 | #define mapping_state_2(x, y) /* nothing */ | |
1703 | #endif | |
1704 | ||
1705 | /* Directives: sectioning and alignment. */ | |
1706 | ||
1707 | static void | |
1708 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
1709 | { | |
1710 | /* We don't support putting frags in the BSS segment, we fake it by | |
1711 | marking in_bss, then looking at s_skip for clues. */ | |
1712 | subseg_set (bss_section, 0); | |
1713 | demand_empty_rest_of_line (); | |
1714 | mapping_state (MAP_DATA); | |
1715 | } | |
1716 | ||
1717 | static void | |
1718 | s_even (int ignore ATTRIBUTE_UNUSED) | |
1719 | { | |
1720 | /* Never make frag if expect extra pass. */ | |
1721 | if (!need_pass_2) | |
1722 | frag_align (1, 0, 0); | |
1723 | ||
1724 | record_alignment (now_seg, 1); | |
1725 | ||
1726 | demand_empty_rest_of_line (); | |
1727 | } | |
1728 | ||
1729 | /* Directives: Literal pools. */ | |
1730 | ||
1731 | static literal_pool * | |
1732 | find_literal_pool (int size) | |
1733 | { | |
1734 | literal_pool *pool; | |
1735 | ||
1736 | for (pool = list_of_pools; pool != NULL; pool = pool->next) | |
1737 | { | |
1738 | if (pool->section == now_seg | |
1739 | && pool->sub_section == now_subseg && pool->size == size) | |
1740 | break; | |
1741 | } | |
1742 | ||
1743 | return pool; | |
1744 | } | |
1745 | ||
1746 | static literal_pool * | |
1747 | find_or_make_literal_pool (int size) | |
1748 | { | |
1749 | /* Next literal pool ID number. */ | |
1750 | static unsigned int latest_pool_num = 1; | |
1751 | literal_pool *pool; | |
1752 | ||
1753 | pool = find_literal_pool (size); | |
1754 | ||
1755 | if (pool == NULL) | |
1756 | { | |
1757 | /* Create a new pool. */ | |
add39d23 | 1758 | pool = XNEW (literal_pool); |
a06ea964 NC |
1759 | if (!pool) |
1760 | return NULL; | |
1761 | ||
1762 | /* Currently we always put the literal pool in the current text | |
1763 | section. If we were generating "small" model code where we | |
1764 | knew that all code and initialised data was within 1MB then | |
1765 | we could output literals to mergeable, read-only data | |
1766 | sections. */ | |
1767 | ||
1768 | pool->next_free_entry = 0; | |
1769 | pool->section = now_seg; | |
1770 | pool->sub_section = now_subseg; | |
1771 | pool->size = size; | |
1772 | pool->next = list_of_pools; | |
1773 | pool->symbol = NULL; | |
1774 | ||
1775 | /* Add it to the list. */ | |
1776 | list_of_pools = pool; | |
1777 | } | |
1778 | ||
1779 | /* New pools, and emptied pools, will have a NULL symbol. */ | |
1780 | if (pool->symbol == NULL) | |
1781 | { | |
1782 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, | |
e01e1cee | 1783 | &zero_address_frag, 0); |
a06ea964 NC |
1784 | pool->id = latest_pool_num++; |
1785 | } | |
1786 | ||
1787 | /* Done. */ | |
1788 | return pool; | |
1789 | } | |
1790 | ||
1791 | /* Add the literal of size SIZE in *EXP to the relevant literal pool. | |
1792 | Return TRUE on success, otherwise return FALSE. */ | |
1793 | static bfd_boolean | |
1794 | add_to_lit_pool (expressionS *exp, int size) | |
1795 | { | |
1796 | literal_pool *pool; | |
1797 | unsigned int entry; | |
1798 | ||
1799 | pool = find_or_make_literal_pool (size); | |
1800 | ||
1801 | /* Check if this literal value is already in the pool. */ | |
1802 | for (entry = 0; entry < pool->next_free_entry; entry++) | |
1803 | { | |
55d9b4c1 NC |
1804 | expressionS * litexp = & pool->literals[entry].exp; |
1805 | ||
1806 | if ((litexp->X_op == exp->X_op) | |
a06ea964 | 1807 | && (exp->X_op == O_constant) |
55d9b4c1 NC |
1808 | && (litexp->X_add_number == exp->X_add_number) |
1809 | && (litexp->X_unsigned == exp->X_unsigned)) | |
a06ea964 NC |
1810 | break; |
1811 | ||
55d9b4c1 | 1812 | if ((litexp->X_op == exp->X_op) |
a06ea964 | 1813 | && (exp->X_op == O_symbol) |
55d9b4c1 NC |
1814 | && (litexp->X_add_number == exp->X_add_number) |
1815 | && (litexp->X_add_symbol == exp->X_add_symbol) | |
1816 | && (litexp->X_op_symbol == exp->X_op_symbol)) | |
a06ea964 NC |
1817 | break; |
1818 | } | |
1819 | ||
1820 | /* Do we need to create a new entry? */ | |
1821 | if (entry == pool->next_free_entry) | |
1822 | { | |
1823 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
1824 | { | |
1825 | set_syntax_error (_("literal pool overflow")); | |
1826 | return FALSE; | |
1827 | } | |
1828 | ||
55d9b4c1 | 1829 | pool->literals[entry].exp = *exp; |
a06ea964 | 1830 | pool->next_free_entry += 1; |
55d9b4c1 NC |
1831 | if (exp->X_op == O_big) |
1832 | { | |
1833 | /* PR 16688: Bignums are held in a single global array. We must | |
1834 | copy and preserve that value now, before it is overwritten. */ | |
add39d23 TS |
1835 | pool->literals[entry].bignum = XNEWVEC (LITTLENUM_TYPE, |
1836 | exp->X_add_number); | |
55d9b4c1 NC |
1837 | memcpy (pool->literals[entry].bignum, generic_bignum, |
1838 | CHARS_PER_LITTLENUM * exp->X_add_number); | |
1839 | } | |
1840 | else | |
1841 | pool->literals[entry].bignum = NULL; | |
a06ea964 NC |
1842 | } |
1843 | ||
1844 | exp->X_op = O_symbol; | |
1845 | exp->X_add_number = ((int) entry) * size; | |
1846 | exp->X_add_symbol = pool->symbol; | |
1847 | ||
1848 | return TRUE; | |
1849 | } | |
1850 | ||
1851 | /* Can't use symbol_new here, so have to create a symbol and then at | |
33eaf5de | 1852 | a later date assign it a value. That's what these functions do. */ |
a06ea964 NC |
1853 | |
1854 | static void | |
1855 | symbol_locate (symbolS * symbolP, | |
1856 | const char *name,/* It is copied, the caller can modify. */ | |
1857 | segT segment, /* Segment identifier (SEG_<something>). */ | |
1858 | valueT valu, /* Symbol value. */ | |
1859 | fragS * frag) /* Associated fragment. */ | |
1860 | { | |
e57e6ddc | 1861 | size_t name_length; |
a06ea964 NC |
1862 | char *preserved_copy_of_name; |
1863 | ||
1864 | name_length = strlen (name) + 1; /* +1 for \0. */ | |
1865 | obstack_grow (¬es, name, name_length); | |
1866 | preserved_copy_of_name = obstack_finish (¬es); | |
1867 | ||
1868 | #ifdef tc_canonicalize_symbol_name | |
1869 | preserved_copy_of_name = | |
1870 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
1871 | #endif | |
1872 | ||
1873 | S_SET_NAME (symbolP, preserved_copy_of_name); | |
1874 | ||
1875 | S_SET_SEGMENT (symbolP, segment); | |
1876 | S_SET_VALUE (symbolP, valu); | |
1877 | symbol_clear_list_pointers (symbolP); | |
1878 | ||
1879 | symbol_set_frag (symbolP, frag); | |
1880 | ||
1881 | /* Link to end of symbol chain. */ | |
1882 | { | |
1883 | extern int symbol_table_frozen; | |
1884 | ||
1885 | if (symbol_table_frozen) | |
1886 | abort (); | |
1887 | } | |
1888 | ||
1889 | symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP); | |
1890 | ||
1891 | obj_symbol_new_hook (symbolP); | |
1892 | ||
1893 | #ifdef tc_symbol_new_hook | |
1894 | tc_symbol_new_hook (symbolP); | |
1895 | #endif | |
1896 | ||
1897 | #ifdef DEBUG_SYMS | |
1898 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
1899 | #endif /* DEBUG_SYMS */ | |
1900 | } | |
1901 | ||
1902 | ||
1903 | static void | |
1904 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
1905 | { | |
1906 | unsigned int entry; | |
1907 | literal_pool *pool; | |
1908 | char sym_name[20]; | |
1909 | int align; | |
1910 | ||
67a32447 | 1911 | for (align = 2; align <= 4; align++) |
a06ea964 NC |
1912 | { |
1913 | int size = 1 << align; | |
1914 | ||
1915 | pool = find_literal_pool (size); | |
1916 | if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0) | |
1917 | continue; | |
1918 | ||
a06ea964 NC |
1919 | /* Align pool as you have word accesses. |
1920 | Only make a frag if we have to. */ | |
1921 | if (!need_pass_2) | |
1922 | frag_align (align, 0, 0); | |
1923 | ||
7ea12e5c NC |
1924 | mapping_state (MAP_DATA); |
1925 | ||
a06ea964 NC |
1926 | record_alignment (now_seg, align); |
1927 | ||
1928 | sprintf (sym_name, "$$lit_\002%x", pool->id); | |
1929 | ||
1930 | symbol_locate (pool->symbol, sym_name, now_seg, | |
1931 | (valueT) frag_now_fix (), frag_now); | |
1932 | symbol_table_insert (pool->symbol); | |
1933 | ||
1934 | for (entry = 0; entry < pool->next_free_entry; entry++) | |
55d9b4c1 NC |
1935 | { |
1936 | expressionS * exp = & pool->literals[entry].exp; | |
1937 | ||
1938 | if (exp->X_op == O_big) | |
1939 | { | |
1940 | /* PR 16688: Restore the global bignum value. */ | |
1941 | gas_assert (pool->literals[entry].bignum != NULL); | |
1942 | memcpy (generic_bignum, pool->literals[entry].bignum, | |
1943 | CHARS_PER_LITTLENUM * exp->X_add_number); | |
1944 | } | |
1945 | ||
1946 | /* First output the expression in the instruction to the pool. */ | |
1947 | emit_expr (exp, size); /* .word|.xword */ | |
1948 | ||
1949 | if (exp->X_op == O_big) | |
1950 | { | |
1951 | free (pool->literals[entry].bignum); | |
1952 | pool->literals[entry].bignum = NULL; | |
1953 | } | |
1954 | } | |
a06ea964 NC |
1955 | |
1956 | /* Mark the pool as empty. */ | |
1957 | pool->next_free_entry = 0; | |
1958 | pool->symbol = NULL; | |
1959 | } | |
1960 | } | |
1961 | ||
1962 | #ifdef OBJ_ELF | |
1963 | /* Forward declarations for functions below, in the MD interface | |
1964 | section. */ | |
1965 | static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int); | |
1966 | static struct reloc_table_entry * find_reloc_table_entry (char **); | |
1967 | ||
1968 | /* Directives: Data. */ | |
1969 | /* N.B. the support for relocation suffix in this directive needs to be | |
1970 | implemented properly. */ | |
1971 | ||
1972 | static void | |
1973 | s_aarch64_elf_cons (int nbytes) | |
1974 | { | |
1975 | expressionS exp; | |
1976 | ||
1977 | #ifdef md_flush_pending_output | |
1978 | md_flush_pending_output (); | |
1979 | #endif | |
1980 | ||
1981 | if (is_it_end_of_statement ()) | |
1982 | { | |
1983 | demand_empty_rest_of_line (); | |
1984 | return; | |
1985 | } | |
1986 | ||
1987 | #ifdef md_cons_align | |
1988 | md_cons_align (nbytes); | |
1989 | #endif | |
1990 | ||
1991 | mapping_state (MAP_DATA); | |
1992 | do | |
1993 | { | |
1994 | struct reloc_table_entry *reloc; | |
1995 | ||
1996 | expression (&exp); | |
1997 | ||
1998 | if (exp.X_op != O_symbol) | |
1999 | emit_expr (&exp, (unsigned int) nbytes); | |
2000 | else | |
2001 | { | |
2002 | skip_past_char (&input_line_pointer, '#'); | |
2003 | if (skip_past_char (&input_line_pointer, ':')) | |
2004 | { | |
2005 | reloc = find_reloc_table_entry (&input_line_pointer); | |
2006 | if (reloc == NULL) | |
2007 | as_bad (_("unrecognized relocation suffix")); | |
2008 | else | |
2009 | as_bad (_("unimplemented relocation suffix")); | |
2010 | ignore_rest_of_line (); | |
2011 | return; | |
2012 | } | |
2013 | else | |
2014 | emit_expr (&exp, (unsigned int) nbytes); | |
2015 | } | |
2016 | } | |
2017 | while (*input_line_pointer++ == ','); | |
2018 | ||
2019 | /* Put terminator back into stream. */ | |
2020 | input_line_pointer--; | |
2021 | demand_empty_rest_of_line (); | |
2022 | } | |
2023 | ||
f166ae01 SN |
2024 | /* Mark symbol that it follows a variant PCS convention. */ |
2025 | ||
2026 | static void | |
2027 | s_variant_pcs (int ignored ATTRIBUTE_UNUSED) | |
2028 | { | |
2029 | char *name; | |
2030 | char c; | |
2031 | symbolS *sym; | |
2032 | asymbol *bfdsym; | |
2033 | elf_symbol_type *elfsym; | |
2034 | ||
2035 | c = get_symbol_name (&name); | |
2036 | if (!*name) | |
2037 | as_bad (_("Missing symbol name in directive")); | |
2038 | sym = symbol_find_or_make (name); | |
2039 | restore_line_pointer (c); | |
2040 | demand_empty_rest_of_line (); | |
2041 | bfdsym = symbol_get_bfdsym (sym); | |
c1229f84 | 2042 | elfsym = elf_symbol_from (bfdsym); |
f166ae01 SN |
2043 | gas_assert (elfsym); |
2044 | elfsym->internal_elf_sym.st_other |= STO_AARCH64_VARIANT_PCS; | |
2045 | } | |
a06ea964 NC |
2046 | #endif /* OBJ_ELF */ |
2047 | ||
2048 | /* Output a 32-bit word, but mark as an instruction. */ | |
2049 | ||
2050 | static void | |
2051 | s_aarch64_inst (int ignored ATTRIBUTE_UNUSED) | |
2052 | { | |
2053 | expressionS exp; | |
2054 | ||
2055 | #ifdef md_flush_pending_output | |
2056 | md_flush_pending_output (); | |
2057 | #endif | |
2058 | ||
2059 | if (is_it_end_of_statement ()) | |
2060 | { | |
2061 | demand_empty_rest_of_line (); | |
2062 | return; | |
2063 | } | |
2064 | ||
a97902de | 2065 | /* Sections are assumed to start aligned. In executable section, there is no |
c1baaddf | 2066 | MAP_DATA symbol pending. So we only align the address during |
3979cf50 | 2067 | MAP_DATA --> MAP_CUR_INSN transition. |
eb9d6cc9 | 2068 | For other sections, this is not guaranteed. */ |
c1baaddf | 2069 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
eb9d6cc9 | 2070 | if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA) |
a06ea964 | 2071 | frag_align_code (2, 0); |
c1baaddf | 2072 | |
a06ea964 | 2073 | #ifdef OBJ_ELF |
3979cf50 | 2074 | mapping_state (MAP_CUR_INSN); |
a06ea964 NC |
2075 | #endif |
2076 | ||
2077 | do | |
2078 | { | |
2079 | expression (&exp); | |
2080 | if (exp.X_op != O_constant) | |
2081 | { | |
2082 | as_bad (_("constant expression required")); | |
2083 | ignore_rest_of_line (); | |
2084 | return; | |
2085 | } | |
2086 | ||
2087 | if (target_big_endian) | |
2088 | { | |
2089 | unsigned int val = exp.X_add_number; | |
2090 | exp.X_add_number = SWAP_32 (val); | |
2091 | } | |
2092 | emit_expr (&exp, 4); | |
2093 | } | |
2094 | while (*input_line_pointer++ == ','); | |
2095 | ||
2096 | /* Put terminator back into stream. */ | |
2097 | input_line_pointer--; | |
2098 | demand_empty_rest_of_line (); | |
2099 | } | |
2100 | ||
3a67e1a6 ST |
2101 | static void |
2102 | s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED) | |
2103 | { | |
2104 | demand_empty_rest_of_line (); | |
2105 | struct fde_entry *fde = frchain_now->frch_cfi_data->cur_fde_data; | |
fa6ca5e2 | 2106 | fde->entry_extras.pauth_key = AARCH64_PAUTH_KEY_B; |
3a67e1a6 ST |
2107 | } |
2108 | ||
a06ea964 | 2109 | #ifdef OBJ_ELF |
43a357f9 RL |
2110 | /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */ |
2111 | ||
2112 | static void | |
2113 | s_tlsdescadd (int ignored ATTRIBUTE_UNUSED) | |
2114 | { | |
2115 | expressionS exp; | |
2116 | ||
2117 | expression (&exp); | |
2118 | frag_grow (4); | |
2119 | fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0, | |
2120 | BFD_RELOC_AARCH64_TLSDESC_ADD); | |
2121 | ||
2122 | demand_empty_rest_of_line (); | |
2123 | } | |
2124 | ||
a06ea964 NC |
2125 | /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */ |
2126 | ||
2127 | static void | |
2128 | s_tlsdesccall (int ignored ATTRIBUTE_UNUSED) | |
2129 | { | |
2130 | expressionS exp; | |
2131 | ||
2132 | /* Since we're just labelling the code, there's no need to define a | |
2133 | mapping symbol. */ | |
2134 | expression (&exp); | |
2135 | /* Make sure there is enough room in this frag for the following | |
2136 | blr. This trick only works if the blr follows immediately after | |
2137 | the .tlsdesc directive. */ | |
2138 | frag_grow (4); | |
2139 | fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0, | |
4ca9b406 SP |
2140 | (IS_C64 ? BFD_RELOC_MORELLO_TLSDESC_CALL |
2141 | : BFD_RELOC_AARCH64_TLSDESC_CALL)); | |
a06ea964 NC |
2142 | |
2143 | demand_empty_rest_of_line (); | |
2144 | } | |
43a357f9 RL |
2145 | |
2146 | /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */ | |
2147 | ||
2148 | static void | |
2149 | s_tlsdescldr (int ignored ATTRIBUTE_UNUSED) | |
2150 | { | |
2151 | expressionS exp; | |
2152 | ||
2153 | expression (&exp); | |
2154 | frag_grow (4); | |
2155 | fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0, | |
2156 | BFD_RELOC_AARCH64_TLSDESC_LDR); | |
2157 | ||
2158 | demand_empty_rest_of_line (); | |
2159 | } | |
40bbb79e SP |
2160 | |
2161 | static void | |
2162 | s_aarch64_capinit (int ignored ATTRIBUTE_UNUSED) | |
2163 | { | |
2164 | expressionS exp; | |
2165 | ||
2166 | expression (&exp); | |
2167 | if (exp.X_op != O_symbol) | |
2168 | { | |
2169 | as_bad (_(".capinit expects a target symbol as an argument")); | |
2170 | return; | |
2171 | } | |
2172 | ||
f4a5fecc MM |
2173 | frag_grow (16); |
2174 | fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 16, &exp, 0, | |
40bbb79e SP |
2175 | BFD_RELOC_MORELLO_CAPINIT); |
2176 | ||
2177 | demand_empty_rest_of_line (); | |
2178 | } | |
fb1a9e59 MM |
2179 | |
2180 | static void | |
2181 | s_aarch64_chericap (int ignored ATTRIBUTE_UNUSED) | |
2182 | { | |
2183 | expressionS exp; | |
2184 | ||
2185 | expression (&exp); | |
2186 | if (exp.X_op != O_symbol) | |
2187 | { | |
2188 | as_bad (_(".chericap expects a target symbol as an argument")); | |
2189 | return; | |
2190 | } | |
2191 | ||
2192 | #ifdef md_flush_pending_output | |
2193 | md_flush_pending_output (); | |
2194 | #endif | |
2195 | ||
2196 | frag_grow (16); | |
2197 | fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 16, &exp, 0, | |
2198 | BFD_RELOC_MORELLO_CAPINIT); | |
2199 | ||
2200 | mapping_state (MAP_DATA); | |
2201 | for (int i = 0; i < 4; i++) | |
2202 | { | |
2203 | /* The documentation of our md_number_to_chars says the greatest value | |
2204 | size it can handle is 4 bytes. */ | |
2205 | char *p = frag_more (4); | |
2206 | md_number_to_chars (p, 0, 4); | |
2207 | } | |
2208 | demand_empty_rest_of_line (); | |
2209 | } | |
a06ea964 NC |
2210 | #endif /* OBJ_ELF */ |
2211 | ||
2212 | static void s_aarch64_arch (int); | |
2213 | static void s_aarch64_cpu (int); | |
ae527cd8 | 2214 | static void s_aarch64_arch_extension (int); |
a06ea964 NC |
2215 | |
2216 | /* This table describes all the machine specific pseudo-ops the assembler | |
2217 | has to support. The fields are: | |
2218 | pseudo-op name without dot | |
2219 | function to call to execute this pseudo-op | |
2220 | Integer arg to pass to the function. */ | |
2221 | ||
2222 | const pseudo_typeS md_pseudo_table[] = { | |
2223 | /* Never called because '.req' does not start a line. */ | |
2224 | {"req", s_req, 0}, | |
2225 | {"unreq", s_unreq, 0}, | |
2226 | {"bss", s_bss, 0}, | |
2227 | {"even", s_even, 0}, | |
2228 | {"ltorg", s_ltorg, 0}, | |
2229 | {"pool", s_ltorg, 0}, | |
2230 | {"cpu", s_aarch64_cpu, 0}, | |
2231 | {"arch", s_aarch64_arch, 0}, | |
ae527cd8 | 2232 | {"arch_extension", s_aarch64_arch_extension, 0}, |
a06ea964 | 2233 | {"inst", s_aarch64_inst, 0}, |
3a67e1a6 | 2234 | {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame, 0}, |
a06ea964 | 2235 | #ifdef OBJ_ELF |
43a357f9 | 2236 | {"tlsdescadd", s_tlsdescadd, 0}, |
a06ea964 | 2237 | {"tlsdesccall", s_tlsdesccall, 0}, |
43a357f9 | 2238 | {"tlsdescldr", s_tlsdescldr, 0}, |
a06ea964 NC |
2239 | {"word", s_aarch64_elf_cons, 4}, |
2240 | {"long", s_aarch64_elf_cons, 4}, | |
2241 | {"xword", s_aarch64_elf_cons, 8}, | |
2242 | {"dword", s_aarch64_elf_cons, 8}, | |
f166ae01 | 2243 | {"variant_pcs", s_variant_pcs, 0}, |
40bbb79e | 2244 | {"capinit", s_aarch64_capinit, 0}, |
fb1a9e59 | 2245 | {"chericap", s_aarch64_chericap, 0}, |
a06ea964 | 2246 | #endif |
b20d3859 | 2247 | {"float16", float_cons, 'h'}, |
eb5bbc48 | 2248 | {"bfloat16", float_cons, 'b'}, |
a06ea964 NC |
2249 | {0, 0, 0} |
2250 | }; | |
2251 | \f | |
2252 | ||
2253 | /* Check whether STR points to a register name followed by a comma or the | |
2254 | end of line; REG_TYPE indicates which register types are checked | |
2255 | against. Return TRUE if STR is such a register name; otherwise return | |
2256 | FALSE. The function does not intend to produce any diagnostics, but since | |
2257 | the register parser aarch64_reg_parse, which is called by this function, | |
2258 | does produce diagnostics, we call clear_error to clear any diagnostics | |
2259 | that may be generated by aarch64_reg_parse. | |
2260 | Also, the function returns FALSE directly if there is any user error | |
2261 | present at the function entry. This prevents the existing diagnostics | |
2262 | state from being spoiled. | |
2263 | The function currently serves parse_constant_immediate and | |
2264 | parse_big_immediate only. */ | |
2265 | static bfd_boolean | |
2266 | reg_name_p (char *str, aarch64_reg_type reg_type) | |
2267 | { | |
2268 | int reg; | |
2269 | ||
2270 | /* Prevent the diagnostics state from being spoiled. */ | |
2271 | if (error_p ()) | |
2272 | return FALSE; | |
2273 | ||
2274 | reg = aarch64_reg_parse (&str, reg_type, NULL, NULL); | |
2275 | ||
2276 | /* Clear the parsing error that may be set by the reg parser. */ | |
2277 | clear_error (); | |
2278 | ||
2279 | if (reg == PARSE_FAIL) | |
2280 | return FALSE; | |
2281 | ||
2282 | skip_whitespace (str); | |
f405494f | 2283 | if (*str == ',' || is_end_of_line[(unsigned char) *str]) |
a06ea964 NC |
2284 | return TRUE; |
2285 | ||
2286 | return FALSE; | |
2287 | } | |
2288 | ||
2289 | /* Parser functions used exclusively in instruction operands. */ | |
2290 | ||
2291 | /* Parse an immediate expression which may not be constant. | |
2292 | ||
2293 | To prevent the expression parser from pushing a register name | |
2294 | into the symbol table as an undefined symbol, firstly a check is | |
1799c0d0 RS |
2295 | done to find out whether STR is a register of type REG_TYPE followed |
2296 | by a comma or the end of line. Return FALSE if STR is such a string. */ | |
a06ea964 NC |
2297 | |
2298 | static bfd_boolean | |
1799c0d0 RS |
2299 | parse_immediate_expression (char **str, expressionS *exp, |
2300 | aarch64_reg_type reg_type) | |
a06ea964 | 2301 | { |
1799c0d0 | 2302 | if (reg_name_p (*str, reg_type)) |
a06ea964 NC |
2303 | { |
2304 | set_recoverable_error (_("immediate operand required")); | |
2305 | return FALSE; | |
2306 | } | |
2307 | ||
2308 | my_get_expression (exp, str, GE_OPT_PREFIX, 1); | |
2309 | ||
2310 | if (exp->X_op == O_absent) | |
2311 | { | |
2312 | set_fatal_syntax_error (_("missing immediate expression")); | |
2313 | return FALSE; | |
2314 | } | |
2315 | ||
2316 | return TRUE; | |
2317 | } | |
2318 | ||
2319 | /* Constant immediate-value read function for use in insn parsing. | |
2320 | STR points to the beginning of the immediate (with the optional | |
1799c0d0 RS |
2321 | leading #); *VAL receives the value. REG_TYPE says which register |
2322 | names should be treated as registers rather than as symbolic immediates. | |
a06ea964 NC |
2323 | |
2324 | Return TRUE on success; otherwise return FALSE. */ | |
2325 | ||
2326 | static bfd_boolean | |
1799c0d0 | 2327 | parse_constant_immediate (char **str, int64_t *val, aarch64_reg_type reg_type) |
a06ea964 NC |
2328 | { |
2329 | expressionS exp; | |
2330 | ||
1799c0d0 | 2331 | if (! parse_immediate_expression (str, &exp, reg_type)) |
a06ea964 NC |
2332 | return FALSE; |
2333 | ||
2334 | if (exp.X_op != O_constant) | |
2335 | { | |
2336 | set_syntax_error (_("constant expression required")); | |
2337 | return FALSE; | |
2338 | } | |
2339 | ||
2340 | *val = exp.X_add_number; | |
2341 | return TRUE; | |
2342 | } | |
2343 | ||
2344 | static uint32_t | |
2345 | encode_imm_float_bits (uint32_t imm) | |
2346 | { | |
2347 | return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */ | |
2348 | | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */ | |
2349 | } | |
2350 | ||
62b0d0d5 YZ |
2351 | /* Return TRUE if the single-precision floating-point value encoded in IMM |
2352 | can be expressed in the AArch64 8-bit signed floating-point format with | |
2353 | 3-bit exponent and normalized 4 bits of precision; in other words, the | |
2354 | floating-point value must be expressable as | |
2355 | (+/-) n / 16 * power (2, r) | |
2356 | where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */ | |
2357 | ||
a06ea964 NC |
2358 | static bfd_boolean |
2359 | aarch64_imm_float_p (uint32_t imm) | |
2360 | { | |
62b0d0d5 YZ |
2361 | /* If a single-precision floating-point value has the following bit |
2362 | pattern, it can be expressed in the AArch64 8-bit floating-point | |
2363 | format: | |
2364 | ||
2365 | 3 32222222 2221111111111 | |
a06ea964 | 2366 | 1 09876543 21098765432109876543210 |
62b0d0d5 YZ |
2367 | n Eeeeeexx xxxx0000000000000000000 |
2368 | ||
2369 | where n, e and each x are either 0 or 1 independently, with | |
2370 | E == ~ e. */ | |
a06ea964 | 2371 | |
62b0d0d5 YZ |
2372 | uint32_t pattern; |
2373 | ||
2374 | /* Prepare the pattern for 'Eeeeee'. */ | |
2375 | if (((imm >> 30) & 0x1) == 0) | |
2376 | pattern = 0x3e000000; | |
a06ea964 | 2377 | else |
62b0d0d5 YZ |
2378 | pattern = 0x40000000; |
2379 | ||
2380 | return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */ | |
2381 | && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */ | |
a06ea964 NC |
2382 | } |
2383 | ||
04a3379a RS |
2384 | /* Return TRUE if the IEEE double value encoded in IMM can be expressed |
2385 | as an IEEE float without any loss of precision. Store the value in | |
2386 | *FPWORD if so. */ | |
62b0d0d5 | 2387 | |
a06ea964 | 2388 | static bfd_boolean |
04a3379a | 2389 | can_convert_double_to_float (uint64_t imm, uint32_t *fpword) |
62b0d0d5 YZ |
2390 | { |
2391 | /* If a double-precision floating-point value has the following bit | |
04a3379a | 2392 | pattern, it can be expressed in a float: |
62b0d0d5 | 2393 | |
04a3379a RS |
2394 | 6 66655555555 5544 44444444 33333333 33222222 22221111 111111 |
2395 | 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210 | |
2396 | n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000 | |
62b0d0d5 | 2397 | |
04a3379a RS |
2398 | -----------------------------> nEeeeeee esssssss ssssssss sssssSSS |
2399 | if Eeee_eeee != 1111_1111 | |
2400 | ||
2401 | where n, e, s and S are either 0 or 1 independently and where ~ is the | |
2402 | inverse of E. */ | |
62b0d0d5 YZ |
2403 | |
2404 | uint32_t pattern; | |
2405 | uint32_t high32 = imm >> 32; | |
04a3379a | 2406 | uint32_t low32 = imm; |
62b0d0d5 | 2407 | |
04a3379a RS |
2408 | /* Lower 29 bits need to be 0s. */ |
2409 | if ((imm & 0x1fffffff) != 0) | |
62b0d0d5 YZ |
2410 | return FALSE; |
2411 | ||
2412 | /* Prepare the pattern for 'Eeeeeeeee'. */ | |
2413 | if (((high32 >> 30) & 0x1) == 0) | |
04a3379a | 2414 | pattern = 0x38000000; |
62b0d0d5 YZ |
2415 | else |
2416 | pattern = 0x40000000; | |
2417 | ||
04a3379a RS |
2418 | /* Check E~~~. */ |
2419 | if ((high32 & 0x78000000) != pattern) | |
62b0d0d5 | 2420 | return FALSE; |
04a3379a RS |
2421 | |
2422 | /* Check Eeee_eeee != 1111_1111. */ | |
2423 | if ((high32 & 0x7ff00000) == 0x47f00000) | |
2424 | return FALSE; | |
2425 | ||
2426 | *fpword = ((high32 & 0xc0000000) /* 1 n bit and 1 E bit. */ | |
2427 | | ((high32 << 3) & 0x3ffffff8) /* 7 e and 20 s bits. */ | |
2428 | | (low32 >> 29)); /* 3 S bits. */ | |
2429 | return TRUE; | |
62b0d0d5 YZ |
2430 | } |
2431 | ||
165d4950 RS |
2432 | /* Return true if we should treat OPERAND as a double-precision |
2433 | floating-point operand rather than a single-precision one. */ | |
2434 | static bfd_boolean | |
2435 | double_precision_operand_p (const aarch64_opnd_info *operand) | |
2436 | { | |
2437 | /* Check for unsuffixed SVE registers, which are allowed | |
2438 | for LDR and STR but not in instructions that require an | |
2439 | immediate. We get better error messages if we arbitrarily | |
2440 | pick one size, parse the immediate normally, and then | |
2441 | report the match failure in the normal way. */ | |
2442 | return (operand->qualifier == AARCH64_OPND_QLF_NIL | |
2443 | || aarch64_get_qualifier_esize (operand->qualifier) == 8); | |
2444 | } | |
2445 | ||
62b0d0d5 YZ |
2446 | /* Parse a floating-point immediate. Return TRUE on success and return the |
2447 | value in *IMMED in the format of IEEE754 single-precision encoding. | |
2448 | *CCP points to the start of the string; DP_P is TRUE when the immediate | |
2449 | is expected to be in double-precision (N.B. this only matters when | |
1799c0d0 RS |
2450 | hexadecimal representation is involved). REG_TYPE says which register |
2451 | names should be treated as registers rather than as symbolic immediates. | |
62b0d0d5 | 2452 | |
874d7e6e RS |
2453 | This routine accepts any IEEE float; it is up to the callers to reject |
2454 | invalid ones. */ | |
62b0d0d5 YZ |
2455 | |
2456 | static bfd_boolean | |
1799c0d0 RS |
2457 | parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p, |
2458 | aarch64_reg_type reg_type) | |
a06ea964 NC |
2459 | { |
2460 | char *str = *ccp; | |
2461 | char *fpnum; | |
2462 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
62b0d0d5 YZ |
2463 | int64_t val = 0; |
2464 | unsigned fpword = 0; | |
2465 | bfd_boolean hex_p = FALSE; | |
a06ea964 NC |
2466 | |
2467 | skip_past_char (&str, '#'); | |
2468 | ||
a06ea964 NC |
2469 | fpnum = str; |
2470 | skip_whitespace (fpnum); | |
2471 | ||
2472 | if (strncmp (fpnum, "0x", 2) == 0) | |
62b0d0d5 YZ |
2473 | { |
2474 | /* Support the hexadecimal representation of the IEEE754 encoding. | |
2475 | Double-precision is expected when DP_P is TRUE, otherwise the | |
2476 | representation should be in single-precision. */ | |
1799c0d0 | 2477 | if (! parse_constant_immediate (&str, &val, reg_type)) |
62b0d0d5 YZ |
2478 | goto invalid_fp; |
2479 | ||
2480 | if (dp_p) | |
2481 | { | |
04a3379a | 2482 | if (!can_convert_double_to_float (val, &fpword)) |
62b0d0d5 YZ |
2483 | goto invalid_fp; |
2484 | } | |
2485 | else if ((uint64_t) val > 0xffffffff) | |
2486 | goto invalid_fp; | |
2487 | else | |
2488 | fpword = val; | |
2489 | ||
2490 | hex_p = TRUE; | |
2491 | } | |
66881839 TC |
2492 | else if (reg_name_p (str, reg_type)) |
2493 | { | |
2494 | set_recoverable_error (_("immediate operand required")); | |
2495 | return FALSE; | |
a06ea964 NC |
2496 | } |
2497 | ||
62b0d0d5 | 2498 | if (! hex_p) |
a06ea964 | 2499 | { |
a06ea964 NC |
2500 | int i; |
2501 | ||
62b0d0d5 YZ |
2502 | if ((str = atof_ieee (str, 's', words)) == NULL) |
2503 | goto invalid_fp; | |
2504 | ||
a06ea964 NC |
2505 | /* Our FP word must be 32 bits (single-precision FP). */ |
2506 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
2507 | { | |
2508 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
2509 | fpword |= words[i]; | |
2510 | } | |
62b0d0d5 | 2511 | } |
a06ea964 | 2512 | |
874d7e6e RS |
2513 | *immed = fpword; |
2514 | *ccp = str; | |
2515 | return TRUE; | |
a06ea964 | 2516 | |
dc1e8a47 | 2517 | invalid_fp: |
a06ea964 NC |
2518 | set_fatal_syntax_error (_("invalid floating-point constant")); |
2519 | return FALSE; | |
2520 | } | |
2521 | ||
2522 | /* Less-generic immediate-value read function with the possibility of loading | |
2523 | a big (64-bit) immediate, as required by AdvSIMD Modified immediate | |
2524 | instructions. | |
2525 | ||
2526 | To prevent the expression parser from pushing a register name into the | |
2527 | symbol table as an undefined symbol, a check is firstly done to find | |
1799c0d0 RS |
2528 | out whether STR is a register of type REG_TYPE followed by a comma or |
2529 | the end of line. Return FALSE if STR is such a register. */ | |
a06ea964 NC |
2530 | |
2531 | static bfd_boolean | |
1799c0d0 | 2532 | parse_big_immediate (char **str, int64_t *imm, aarch64_reg_type reg_type) |
a06ea964 NC |
2533 | { |
2534 | char *ptr = *str; | |
2535 | ||
1799c0d0 | 2536 | if (reg_name_p (ptr, reg_type)) |
a06ea964 NC |
2537 | { |
2538 | set_syntax_error (_("immediate operand required")); | |
2539 | return FALSE; | |
2540 | } | |
2541 | ||
2542 | my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1); | |
2543 | ||
2544 | if (inst.reloc.exp.X_op == O_constant) | |
2545 | *imm = inst.reloc.exp.X_add_number; | |
2546 | ||
2547 | *str = ptr; | |
2548 | ||
2549 | return TRUE; | |
2550 | } | |
2551 | ||
2552 | /* Set operand IDX of the *INSTR that needs a GAS internal fixup. | |
2553 | if NEED_LIBOPCODES is non-zero, the fixup will need | |
2554 | assistance from the libopcodes. */ | |
2555 | ||
2556 | static inline void | |
2557 | aarch64_set_gas_internal_fixup (struct reloc *reloc, | |
2558 | const aarch64_opnd_info *operand, | |
2559 | int need_libopcodes_p) | |
2560 | { | |
2561 | reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP; | |
2562 | reloc->opnd = operand->type; | |
2563 | if (need_libopcodes_p) | |
2564 | reloc->need_libopcodes_p = 1; | |
2565 | }; | |
2566 | ||
2567 | /* Return TRUE if the instruction needs to be fixed up later internally by | |
2568 | the GAS; otherwise return FALSE. */ | |
2569 | ||
2570 | static inline bfd_boolean | |
2571 | aarch64_gas_internal_fixup_p (void) | |
2572 | { | |
2573 | return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP; | |
2574 | } | |
2575 | ||
33eaf5de | 2576 | /* Assign the immediate value to the relevant field in *OPERAND if |
a06ea964 NC |
2577 | RELOC->EXP is a constant expression; otherwise, flag that *OPERAND |
2578 | needs an internal fixup in a later stage. | |
2579 | ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or | |
2580 | IMM.VALUE that may get assigned with the constant. */ | |
2581 | static inline void | |
2582 | assign_imm_if_const_or_fixup_later (struct reloc *reloc, | |
2583 | aarch64_opnd_info *operand, | |
2584 | int addr_off_p, | |
2585 | int need_libopcodes_p, | |
2586 | int skip_p) | |
2587 | { | |
2588 | if (reloc->exp.X_op == O_constant) | |
2589 | { | |
2590 | if (addr_off_p) | |
2591 | operand->addr.offset.imm = reloc->exp.X_add_number; | |
2592 | else | |
2593 | operand->imm.value = reloc->exp.X_add_number; | |
2594 | reloc->type = BFD_RELOC_UNUSED; | |
2595 | } | |
2596 | else | |
2597 | { | |
2598 | aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p); | |
2599 | /* Tell libopcodes to ignore this operand or not. This is helpful | |
2600 | when one of the operands needs to be fixed up later but we need | |
2601 | libopcodes to check the other operands. */ | |
2602 | operand->skip = skip_p; | |
2603 | } | |
2604 | } | |
2605 | ||
2606 | /* Relocation modifiers. Each entry in the table contains the textual | |
2607 | name for the relocation which may be placed before a symbol used as | |
2608 | a load/store offset, or add immediate. It must be surrounded by a | |
2609 | leading and trailing colon, for example: | |
2610 | ||
2611 | ldr x0, [x1, #:rello:varsym] | |
2612 | add x0, x1, #:rello:varsym */ | |
2613 | ||
2614 | struct reloc_table_entry | |
2615 | { | |
2616 | const char *name; | |
2617 | int pc_rel; | |
6f4a313b | 2618 | bfd_reloc_code_real_type adr_type; |
a06ea964 | 2619 | bfd_reloc_code_real_type adrp_type; |
92504105 | 2620 | bfd_reloc_code_real_type c64_adrp_type; |
a06ea964 NC |
2621 | bfd_reloc_code_real_type movw_type; |
2622 | bfd_reloc_code_real_type add_type; | |
2623 | bfd_reloc_code_real_type ldst_type; | |
74ad790c | 2624 | bfd_reloc_code_real_type ld_literal_type; |
a06ea964 NC |
2625 | }; |
2626 | ||
2627 | static struct reloc_table_entry reloc_table[] = { | |
2628 | /* Low 12 bits of absolute address: ADD/i and LDR/STR */ | |
2629 | {"lo12", 0, | |
6f4a313b | 2630 | 0, /* adr_type */ |
a06ea964 NC |
2631 | 0, |
2632 | 0, | |
92504105 | 2633 | 0, |
a06ea964 | 2634 | BFD_RELOC_AARCH64_ADD_LO12, |
74ad790c MS |
2635 | BFD_RELOC_AARCH64_LDST_LO12, |
2636 | 0}, | |
a06ea964 NC |
2637 | |
2638 | /* Higher 21 bits of pc-relative page offset: ADRP */ | |
2639 | {"pg_hi21", 1, | |
6f4a313b | 2640 | 0, /* adr_type */ |
a06ea964 | 2641 | BFD_RELOC_AARCH64_ADR_HI21_PCREL, |
92504105 | 2642 | BFD_RELOC_MORELLO_ADR_HI20_PCREL, |
a06ea964 NC |
2643 | 0, |
2644 | 0, | |
74ad790c | 2645 | 0, |
a06ea964 NC |
2646 | 0}, |
2647 | ||
92504105 SP |
2648 | /* Higher 21 bits (20 bits for C64) of pc-relative page offset: ADRP, no |
2649 | check */ | |
a06ea964 | 2650 | {"pg_hi21_nc", 1, |
6f4a313b | 2651 | 0, /* adr_type */ |
a06ea964 | 2652 | BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL, |
92504105 | 2653 | BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL, |
a06ea964 NC |
2654 | 0, |
2655 | 0, | |
74ad790c | 2656 | 0, |
a06ea964 NC |
2657 | 0}, |
2658 | ||
2659 | /* Most significant bits 0-15 of unsigned address/value: MOVZ */ | |
2660 | {"abs_g0", 0, | |
6f4a313b | 2661 | 0, /* adr_type */ |
a06ea964 | 2662 | 0, |
92504105 | 2663 | 0, |
a06ea964 NC |
2664 | BFD_RELOC_AARCH64_MOVW_G0, |
2665 | 0, | |
74ad790c | 2666 | 0, |
a06ea964 NC |
2667 | 0}, |
2668 | ||
2669 | /* Most significant bits 0-15 of signed address/value: MOVN/Z */ | |
2670 | {"abs_g0_s", 0, | |
6f4a313b | 2671 | 0, /* adr_type */ |
a06ea964 | 2672 | 0, |
92504105 | 2673 | 0, |
a06ea964 NC |
2674 | BFD_RELOC_AARCH64_MOVW_G0_S, |
2675 | 0, | |
74ad790c | 2676 | 0, |
a06ea964 NC |
2677 | 0}, |
2678 | ||
2679 | /* Less significant bits 0-15 of address/value: MOVK, no check */ | |
2680 | {"abs_g0_nc", 0, | |
6f4a313b | 2681 | 0, /* adr_type */ |
a06ea964 | 2682 | 0, |
92504105 | 2683 | 0, |
a06ea964 NC |
2684 | BFD_RELOC_AARCH64_MOVW_G0_NC, |
2685 | 0, | |
74ad790c | 2686 | 0, |
a06ea964 NC |
2687 | 0}, |
2688 | ||
2689 | /* Most significant bits 16-31 of unsigned address/value: MOVZ */ | |
2690 | {"abs_g1", 0, | |
6f4a313b | 2691 | 0, /* adr_type */ |
a06ea964 | 2692 | 0, |
92504105 | 2693 | 0, |
a06ea964 NC |
2694 | BFD_RELOC_AARCH64_MOVW_G1, |
2695 | 0, | |
74ad790c | 2696 | 0, |
a06ea964 NC |
2697 | 0}, |
2698 | ||
2699 | /* Most significant bits 16-31 of signed address/value: MOVN/Z */ | |
2700 | {"abs_g1_s", 0, | |
6f4a313b | 2701 | 0, /* adr_type */ |
a06ea964 | 2702 | 0, |
92504105 | 2703 | 0, |
a06ea964 NC |
2704 | BFD_RELOC_AARCH64_MOVW_G1_S, |
2705 | 0, | |
74ad790c | 2706 | 0, |
a06ea964 NC |
2707 | 0}, |
2708 | ||
2709 | /* Less significant bits 16-31 of address/value: MOVK, no check */ | |
2710 | {"abs_g1_nc", 0, | |
6f4a313b | 2711 | 0, /* adr_type */ |
a06ea964 | 2712 | 0, |
92504105 | 2713 | 0, |
a06ea964 NC |
2714 | BFD_RELOC_AARCH64_MOVW_G1_NC, |
2715 | 0, | |
74ad790c | 2716 | 0, |
a06ea964 NC |
2717 | 0}, |
2718 | ||
2719 | /* Most significant bits 32-47 of unsigned address/value: MOVZ */ | |
2720 | {"abs_g2", 0, | |
6f4a313b | 2721 | 0, /* adr_type */ |
a06ea964 | 2722 | 0, |
92504105 | 2723 | 0, |
a06ea964 NC |
2724 | BFD_RELOC_AARCH64_MOVW_G2, |
2725 | 0, | |
74ad790c | 2726 | 0, |
a06ea964 NC |
2727 | 0}, |
2728 | ||
2729 | /* Most significant bits 32-47 of signed address/value: MOVN/Z */ | |
2730 | {"abs_g2_s", 0, | |
6f4a313b | 2731 | 0, /* adr_type */ |
a06ea964 | 2732 | 0, |
92504105 | 2733 | 0, |
a06ea964 NC |
2734 | BFD_RELOC_AARCH64_MOVW_G2_S, |
2735 | 0, | |
74ad790c | 2736 | 0, |
a06ea964 NC |
2737 | 0}, |
2738 | ||
2739 | /* Less significant bits 32-47 of address/value: MOVK, no check */ | |
2740 | {"abs_g2_nc", 0, | |
6f4a313b | 2741 | 0, /* adr_type */ |
a06ea964 | 2742 | 0, |
92504105 | 2743 | 0, |
a06ea964 NC |
2744 | BFD_RELOC_AARCH64_MOVW_G2_NC, |
2745 | 0, | |
74ad790c | 2746 | 0, |
a06ea964 NC |
2747 | 0}, |
2748 | ||
2749 | /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */ | |
2750 | {"abs_g3", 0, | |
6f4a313b | 2751 | 0, /* adr_type */ |
a06ea964 | 2752 | 0, |
92504105 | 2753 | 0, |
a06ea964 NC |
2754 | BFD_RELOC_AARCH64_MOVW_G3, |
2755 | 0, | |
74ad790c | 2756 | 0, |
a06ea964 | 2757 | 0}, |
4aa2c5e2 | 2758 | |
32247401 RL |
2759 | /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */ |
2760 | {"prel_g0", 1, | |
2761 | 0, /* adr_type */ | |
2762 | 0, | |
92504105 | 2763 | 0, |
32247401 RL |
2764 | BFD_RELOC_AARCH64_MOVW_PREL_G0, |
2765 | 0, | |
2766 | 0, | |
2767 | 0}, | |
2768 | ||
2769 | /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */ | |
2770 | {"prel_g0_nc", 1, | |
2771 | 0, /* adr_type */ | |
2772 | 0, | |
92504105 | 2773 | 0, |
32247401 RL |
2774 | BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, |
2775 | 0, | |
2776 | 0, | |
2777 | 0}, | |
2778 | ||
2779 | /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */ | |
2780 | {"prel_g1", 1, | |
2781 | 0, /* adr_type */ | |
2782 | 0, | |
92504105 | 2783 | 0, |
32247401 RL |
2784 | BFD_RELOC_AARCH64_MOVW_PREL_G1, |
2785 | 0, | |
2786 | 0, | |
2787 | 0}, | |
2788 | ||
2789 | /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */ | |
2790 | {"prel_g1_nc", 1, | |
2791 | 0, /* adr_type */ | |
2792 | 0, | |
92504105 | 2793 | 0, |
32247401 RL |
2794 | BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, |
2795 | 0, | |
2796 | 0, | |
2797 | 0}, | |
2798 | ||
2799 | /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */ | |
2800 | {"prel_g2", 1, | |
2801 | 0, /* adr_type */ | |
2802 | 0, | |
92504105 | 2803 | 0, |
32247401 RL |
2804 | BFD_RELOC_AARCH64_MOVW_PREL_G2, |
2805 | 0, | |
2806 | 0, | |
2807 | 0}, | |
2808 | ||
2809 | /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */ | |
2810 | {"prel_g2_nc", 1, | |
2811 | 0, /* adr_type */ | |
2812 | 0, | |
92504105 | 2813 | 0, |
32247401 RL |
2814 | BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, |
2815 | 0, | |
2816 | 0, | |
2817 | 0}, | |
2818 | ||
2819 | /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */ | |
2820 | {"prel_g3", 1, | |
2821 | 0, /* adr_type */ | |
2822 | 0, | |
92504105 | 2823 | 0, |
32247401 RL |
2824 | BFD_RELOC_AARCH64_MOVW_PREL_G3, |
2825 | 0, | |
2826 | 0, | |
2827 | 0}, | |
2828 | ||
a06ea964 NC |
2829 | /* Get to the page containing GOT entry for a symbol. */ |
2830 | {"got", 1, | |
6f4a313b | 2831 | 0, /* adr_type */ |
a06ea964 | 2832 | BFD_RELOC_AARCH64_ADR_GOT_PAGE, |
92504105 | 2833 | BFD_RELOC_MORELLO_ADR_GOT_PAGE, |
a06ea964 NC |
2834 | 0, |
2835 | 0, | |
74ad790c | 2836 | 0, |
4aa2c5e2 MS |
2837 | BFD_RELOC_AARCH64_GOT_LD_PREL19}, |
2838 | ||
a06ea964 NC |
2839 | /* 12 bit offset into the page containing GOT entry for that symbol. */ |
2840 | {"got_lo12", 0, | |
6f4a313b | 2841 | 0, /* adr_type */ |
a06ea964 NC |
2842 | 0, |
2843 | 0, | |
2844 | 0, | |
92504105 | 2845 | 0, |
74ad790c MS |
2846 | BFD_RELOC_AARCH64_LD_GOT_LO12_NC, |
2847 | 0}, | |
a06ea964 | 2848 | |
ca632371 RL |
2849 | /* 0-15 bits of address/value: MOVk, no check. */ |
2850 | {"gotoff_g0_nc", 0, | |
2851 | 0, /* adr_type */ | |
2852 | 0, | |
92504105 | 2853 | 0, |
ca632371 RL |
2854 | BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC, |
2855 | 0, | |
2856 | 0, | |
2857 | 0}, | |
2858 | ||
654248e7 RL |
2859 | /* Most significant bits 16-31 of address/value: MOVZ. */ |
2860 | {"gotoff_g1", 0, | |
2861 | 0, /* adr_type */ | |
2862 | 0, | |
92504105 | 2863 | 0, |
654248e7 RL |
2864 | BFD_RELOC_AARCH64_MOVW_GOTOFF_G1, |
2865 | 0, | |
2866 | 0, | |
2867 | 0}, | |
2868 | ||
87f5fbcc RL |
2869 | /* 15 bit offset into the page containing GOT entry for that symbol. */ |
2870 | {"gotoff_lo15", 0, | |
2871 | 0, /* adr_type */ | |
2872 | 0, | |
2873 | 0, | |
2874 | 0, | |
92504105 | 2875 | 0, |
87f5fbcc RL |
2876 | BFD_RELOC_AARCH64_LD64_GOTOFF_LO15, |
2877 | 0}, | |
2878 | ||
3b957e5b RL |
2879 | /* Get to the page containing GOT TLS entry for a symbol */ |
2880 | {"gottprel_g0_nc", 0, | |
2881 | 0, /* adr_type */ | |
2882 | 0, | |
92504105 | 2883 | 0, |
3b957e5b RL |
2884 | BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, |
2885 | 0, | |
2886 | 0, | |
2887 | 0}, | |
2888 | ||
2889 | /* Get to the page containing GOT TLS entry for a symbol */ | |
2890 | {"gottprel_g1", 0, | |
2891 | 0, /* adr_type */ | |
2892 | 0, | |
92504105 | 2893 | 0, |
3b957e5b RL |
2894 | BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1, |
2895 | 0, | |
2896 | 0, | |
2897 | 0}, | |
2898 | ||
a06ea964 NC |
2899 | /* Get to the page containing GOT TLS entry for a symbol */ |
2900 | {"tlsgd", 0, | |
3c12b054 | 2901 | BFD_RELOC_AARCH64_TLSGD_ADR_PREL21, /* adr_type */ |
a06ea964 NC |
2902 | BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21, |
2903 | 0, | |
2904 | 0, | |
74ad790c | 2905 | 0, |
92504105 | 2906 | 0, |
a06ea964 NC |
2907 | 0}, |
2908 | ||
2909 | /* 12 bit offset into the page containing GOT TLS entry for a symbol */ | |
2910 | {"tlsgd_lo12", 0, | |
6f4a313b | 2911 | 0, /* adr_type */ |
a06ea964 NC |
2912 | 0, |
2913 | 0, | |
92504105 | 2914 | 0, |
a06ea964 | 2915 | BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC, |
74ad790c | 2916 | 0, |
a06ea964 NC |
2917 | 0}, |
2918 | ||
3e8286c0 RL |
2919 | /* Lower 16 bits address/value: MOVk. */ |
2920 | {"tlsgd_g0_nc", 0, | |
2921 | 0, /* adr_type */ | |
2922 | 0, | |
92504105 | 2923 | 0, |
3e8286c0 RL |
2924 | BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC, |
2925 | 0, | |
2926 | 0, | |
2927 | 0}, | |
2928 | ||
1aa66fb1 RL |
2929 | /* Most significant bits 16-31 of address/value: MOVZ. */ |
2930 | {"tlsgd_g1", 0, | |
2931 | 0, /* adr_type */ | |
2932 | 0, | |
92504105 | 2933 | 0, |
1aa66fb1 RL |
2934 | BFD_RELOC_AARCH64_TLSGD_MOVW_G1, |
2935 | 0, | |
2936 | 0, | |
2937 | 0}, | |
2938 | ||
a06ea964 NC |
2939 | /* Get to the page containing GOT TLS entry for a symbol */ |
2940 | {"tlsdesc", 0, | |
389b8029 | 2941 | BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21, /* adr_type */ |
418009c2 | 2942 | BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21, |
4ca9b406 | 2943 | BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20, |
a06ea964 | 2944 | 0, |
74ad790c | 2945 | 0, |
92504105 | 2946 | 0, |
1ada945d | 2947 | BFD_RELOC_AARCH64_TLSDESC_LD_PREL19}, |
a06ea964 NC |
2948 | |
2949 | /* 12 bit offset into the page containing GOT TLS entry for a symbol */ | |
2950 | {"tlsdesc_lo12", 0, | |
6f4a313b | 2951 | 0, /* adr_type */ |
a06ea964 NC |
2952 | 0, |
2953 | 0, | |
92504105 | 2954 | 0, |
f955cccf | 2955 | BFD_RELOC_AARCH64_TLSDESC_ADD_LO12, |
74ad790c MS |
2956 | BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC, |
2957 | 0}, | |
a06ea964 | 2958 | |
6c37fedc JW |
2959 | /* Get to the page containing GOT TLS entry for a symbol. |
2960 | The same as GD, we allocate two consecutive GOT slots | |
2961 | for module index and module offset, the only difference | |
33eaf5de | 2962 | with GD is the module offset should be initialized to |
6c37fedc JW |
2963 | zero without any outstanding runtime relocation. */ |
2964 | {"tlsldm", 0, | |
2965 | BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */ | |
1107e076 | 2966 | BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21, |
6c37fedc JW |
2967 | 0, |
2968 | 0, | |
2969 | 0, | |
92504105 | 2970 | 0, |
6c37fedc JW |
2971 | 0}, |
2972 | ||
a12fad50 JW |
2973 | /* 12 bit offset into the page containing GOT TLS entry for a symbol */ |
2974 | {"tlsldm_lo12_nc", 0, | |
2975 | 0, /* adr_type */ | |
2976 | 0, | |
2977 | 0, | |
92504105 | 2978 | 0, |
a12fad50 JW |
2979 | BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC, |
2980 | 0, | |
2981 | 0}, | |
2982 | ||
70151fb5 JW |
2983 | /* 12 bit offset into the module TLS base address. */ |
2984 | {"dtprel_lo12", 0, | |
2985 | 0, /* adr_type */ | |
2986 | 0, | |
2987 | 0, | |
92504105 | 2988 | 0, |
70151fb5 | 2989 | BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12, |
4c562523 | 2990 | BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, |
70151fb5 JW |
2991 | 0}, |
2992 | ||
13289c10 JW |
2993 | /* Same as dtprel_lo12, no overflow check. */ |
2994 | {"dtprel_lo12_nc", 0, | |
2995 | 0, /* adr_type */ | |
2996 | 0, | |
2997 | 0, | |
92504105 | 2998 | 0, |
13289c10 | 2999 | BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC, |
4c562523 | 3000 | BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC, |
13289c10 JW |
3001 | 0}, |
3002 | ||
49df5539 JW |
3003 | /* bits[23:12] of offset to the module TLS base address. */ |
3004 | {"dtprel_hi12", 0, | |
3005 | 0, /* adr_type */ | |
3006 | 0, | |
3007 | 0, | |
92504105 | 3008 | 0, |
49df5539 JW |
3009 | BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12, |
3010 | 0, | |
3011 | 0}, | |
3012 | ||
3013 | /* bits[15:0] of offset to the module TLS base address. */ | |
3014 | {"dtprel_g0", 0, | |
3015 | 0, /* adr_type */ | |
3016 | 0, | |
92504105 | 3017 | 0, |
49df5539 JW |
3018 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0, |
3019 | 0, | |
3020 | 0, | |
3021 | 0}, | |
3022 | ||
3023 | /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */ | |
3024 | {"dtprel_g0_nc", 0, | |
3025 | 0, /* adr_type */ | |
3026 | 0, | |
92504105 | 3027 | 0, |
49df5539 JW |
3028 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC, |
3029 | 0, | |
3030 | 0, | |
3031 | 0}, | |
3032 | ||
3033 | /* bits[31:16] of offset to the module TLS base address. */ | |
3034 | {"dtprel_g1", 0, | |
3035 | 0, /* adr_type */ | |
3036 | 0, | |
92504105 | 3037 | 0, |
49df5539 JW |
3038 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1, |
3039 | 0, | |
3040 | 0, | |
3041 | 0}, | |
3042 | ||
3043 | /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */ | |
3044 | {"dtprel_g1_nc", 0, | |
3045 | 0, /* adr_type */ | |
3046 | 0, | |
92504105 | 3047 | 0, |
49df5539 JW |
3048 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC, |
3049 | 0, | |
3050 | 0, | |
3051 | 0}, | |
3052 | ||
3053 | /* bits[47:32] of offset to the module TLS base address. */ | |
3054 | {"dtprel_g2", 0, | |
3055 | 0, /* adr_type */ | |
3056 | 0, | |
92504105 | 3057 | 0, |
49df5539 JW |
3058 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2, |
3059 | 0, | |
3060 | 0, | |
3061 | 0}, | |
3062 | ||
43a357f9 RL |
3063 | /* Lower 16 bit offset into GOT entry for a symbol */ |
3064 | {"tlsdesc_off_g0_nc", 0, | |
3065 | 0, /* adr_type */ | |
3066 | 0, | |
92504105 | 3067 | 0, |
43a357f9 RL |
3068 | BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC, |
3069 | 0, | |
3070 | 0, | |
3071 | 0}, | |
3072 | ||
3073 | /* Higher 16 bit offset into GOT entry for a symbol */ | |
3074 | {"tlsdesc_off_g1", 0, | |
3075 | 0, /* adr_type */ | |
3076 | 0, | |
92504105 | 3077 | 0, |
43a357f9 RL |
3078 | BFD_RELOC_AARCH64_TLSDESC_OFF_G1, |
3079 | 0, | |
3080 | 0, | |
3081 | 0}, | |
3082 | ||
a06ea964 NC |
3083 | /* Get to the page containing GOT TLS entry for a symbol */ |
3084 | {"gottprel", 0, | |
6f4a313b | 3085 | 0, /* adr_type */ |
a06ea964 NC |
3086 | BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, |
3087 | 0, | |
3088 | 0, | |
74ad790c | 3089 | 0, |
92504105 | 3090 | 0, |
043bf05a | 3091 | BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19}, |
a06ea964 NC |
3092 | |
3093 | /* 12 bit offset into the page containing GOT TLS entry for a symbol */ | |
3094 | {"gottprel_lo12", 0, | |
6f4a313b | 3095 | 0, /* adr_type */ |
a06ea964 NC |
3096 | 0, |
3097 | 0, | |
3098 | 0, | |
92504105 | 3099 | 0, |
74ad790c MS |
3100 | BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC, |
3101 | 0}, | |
a06ea964 NC |
3102 | |
3103 | /* Get tp offset for a symbol. */ | |
3104 | {"tprel", 0, | |
6f4a313b | 3105 | 0, /* adr_type */ |
a06ea964 NC |
3106 | 0, |
3107 | 0, | |
92504105 | 3108 | 0, |
a06ea964 | 3109 | BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12, |
74ad790c | 3110 | 0, |
a06ea964 NC |
3111 | 0}, |
3112 | ||
3113 | /* Get tp offset for a symbol. */ | |
3114 | {"tprel_lo12", 0, | |
6f4a313b | 3115 | 0, /* adr_type */ |
a06ea964 NC |
3116 | 0, |
3117 | 0, | |
92504105 | 3118 | 0, |
a06ea964 | 3119 | BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12, |
84f1b9fb | 3120 | BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, |
a06ea964 NC |
3121 | 0}, |
3122 | ||
3123 | /* Get tp offset for a symbol. */ | |
3124 | {"tprel_hi12", 0, | |
6f4a313b | 3125 | 0, /* adr_type */ |
a06ea964 NC |
3126 | 0, |
3127 | 0, | |
92504105 | 3128 | 0, |
a06ea964 | 3129 | BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12, |
74ad790c | 3130 | 0, |
a06ea964 NC |
3131 | 0}, |
3132 | ||
3133 | /* Get tp offset for a symbol. */ | |
3134 | {"tprel_lo12_nc", 0, | |
6f4a313b | 3135 | 0, /* adr_type */ |
a06ea964 NC |
3136 | 0, |
3137 | 0, | |
92504105 | 3138 | 0, |
a06ea964 | 3139 | BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC, |
84f1b9fb | 3140 | BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC, |
a06ea964 NC |
3141 | 0}, |
3142 | ||
3143 | /* Most significant bits 32-47 of address/value: MOVZ. */ | |
3144 | {"tprel_g2", 0, | |
6f4a313b | 3145 | 0, /* adr_type */ |
a06ea964 | 3146 | 0, |
92504105 | 3147 | 0, |
a06ea964 NC |
3148 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2, |
3149 | 0, | |
74ad790c | 3150 | 0, |
a06ea964 NC |
3151 | 0}, |
3152 | ||
3153 | /* Most significant bits 16-31 of address/value: MOVZ. */ | |
3154 | {"tprel_g1", 0, | |
6f4a313b | 3155 | 0, /* adr_type */ |
a06ea964 | 3156 | 0, |
92504105 | 3157 | 0, |
a06ea964 NC |
3158 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1, |
3159 | 0, | |
74ad790c | 3160 | 0, |
a06ea964 NC |
3161 | 0}, |
3162 | ||
3163 | /* Most significant bits 16-31 of address/value: MOVZ, no check. */ | |
3164 | {"tprel_g1_nc", 0, | |
6f4a313b | 3165 | 0, /* adr_type */ |
a06ea964 | 3166 | 0, |
92504105 | 3167 | 0, |
a06ea964 NC |
3168 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC, |
3169 | 0, | |
74ad790c | 3170 | 0, |
a06ea964 NC |
3171 | 0}, |
3172 | ||
3173 | /* Most significant bits 0-15 of address/value: MOVZ. */ | |
3174 | {"tprel_g0", 0, | |
6f4a313b | 3175 | 0, /* adr_type */ |
a06ea964 | 3176 | 0, |
92504105 | 3177 | 0, |
a06ea964 NC |
3178 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0, |
3179 | 0, | |
74ad790c | 3180 | 0, |
a06ea964 NC |
3181 | 0}, |
3182 | ||
3183 | /* Most significant bits 0-15 of address/value: MOVZ, no check. */ | |
3184 | {"tprel_g0_nc", 0, | |
6f4a313b | 3185 | 0, /* adr_type */ |
a06ea964 | 3186 | 0, |
92504105 | 3187 | 0, |
a06ea964 NC |
3188 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC, |
3189 | 0, | |
74ad790c | 3190 | 0, |
a06ea964 | 3191 | 0}, |
a921b5bd JW |
3192 | |
3193 | /* 15bit offset from got entry to base address of GOT table. */ | |
3194 | {"gotpage_lo15", 0, | |
3195 | 0, | |
3196 | 0, | |
3197 | 0, | |
3198 | 0, | |
92504105 | 3199 | 0, |
a921b5bd JW |
3200 | BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15, |
3201 | 0}, | |
3d715ce4 JW |
3202 | |
3203 | /* 14bit offset from got entry to base address of GOT table. */ | |
3204 | {"gotpage_lo14", 0, | |
3205 | 0, | |
3206 | 0, | |
3207 | 0, | |
3208 | 0, | |
92504105 | 3209 | 0, |
3d715ce4 JW |
3210 | BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14, |
3211 | 0}, | |
a06ea964 NC |
3212 | }; |
3213 | ||
3214 | /* Given the address of a pointer pointing to the textual name of a | |
3215 | relocation as may appear in assembler source, attempt to find its | |
3216 | details in reloc_table. The pointer will be updated to the character | |
3217 | after the trailing colon. On failure, NULL will be returned; | |
3218 | otherwise return the reloc_table_entry. */ | |
3219 | ||
3220 | static struct reloc_table_entry * | |
3221 | find_reloc_table_entry (char **str) | |
3222 | { | |
3223 | unsigned int i; | |
3224 | for (i = 0; i < ARRAY_SIZE (reloc_table); i++) | |
3225 | { | |
3226 | int length = strlen (reloc_table[i].name); | |
3227 | ||
3228 | if (strncasecmp (reloc_table[i].name, *str, length) == 0 | |
3229 | && (*str)[length] == ':') | |
3230 | { | |
3231 | *str += (length + 1); | |
3232 | return &reloc_table[i]; | |
3233 | } | |
3234 | } | |
3235 | ||
3236 | return NULL; | |
3237 | } | |
3238 | ||
3239 | /* Mode argument to parse_shift and parser_shifter_operand. */ | |
3240 | enum parse_shift_mode | |
3241 | { | |
98907a70 | 3242 | SHIFTED_NONE, /* no shifter allowed */ |
a06ea964 NC |
3243 | SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or |
3244 | "#imm{,lsl #n}" */ | |
3245 | SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or | |
3246 | "#imm" */ | |
3247 | SHIFTED_LSL, /* bare "lsl #n" */ | |
2442d846 | 3248 | SHIFTED_MUL, /* bare "mul #n" */ |
a06ea964 | 3249 | SHIFTED_LSL_MSL, /* "lsl|msl #n" */ |
98907a70 | 3250 | SHIFTED_MUL_VL, /* "mul vl" */ |
a06ea964 NC |
3251 | SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */ |
3252 | }; | |
3253 | ||
3254 | /* Parse a <shift> operator on an AArch64 data processing instruction. | |
3255 | Return TRUE on success; otherwise return FALSE. */ | |
3256 | static bfd_boolean | |
3257 | parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode) | |
3258 | { | |
3259 | const struct aarch64_name_value_pair *shift_op; | |
3260 | enum aarch64_modifier_kind kind; | |
3261 | expressionS exp; | |
3262 | int exp_has_prefix; | |
3263 | char *s = *str; | |
3264 | char *p = s; | |
3265 | ||
3266 | for (p = *str; ISALPHA (*p); p++) | |
3267 | ; | |
3268 | ||
3269 | if (p == *str) | |
3270 | { | |
3271 | set_syntax_error (_("shift expression expected")); | |
3272 | return FALSE; | |
3273 | } | |
3274 | ||
629310ab | 3275 | shift_op = str_hash_find_n (aarch64_shift_hsh, *str, p - *str); |
a06ea964 NC |
3276 | |
3277 | if (shift_op == NULL) | |
3278 | { | |
3279 | set_syntax_error (_("shift operator expected")); | |
3280 | return FALSE; | |
3281 | } | |
3282 | ||
3283 | kind = aarch64_get_operand_modifier (shift_op); | |
3284 | ||
3285 | if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL) | |
3286 | { | |
3287 | set_syntax_error (_("invalid use of 'MSL'")); | |
3288 | return FALSE; | |
3289 | } | |
3290 | ||
2442d846 | 3291 | if (kind == AARCH64_MOD_MUL |
98907a70 RS |
3292 | && mode != SHIFTED_MUL |
3293 | && mode != SHIFTED_MUL_VL) | |
2442d846 RS |
3294 | { |
3295 | set_syntax_error (_("invalid use of 'MUL'")); | |
3296 | return FALSE; | |
3297 | } | |
3298 | ||
a06ea964 NC |
3299 | switch (mode) |
3300 | { | |
3301 | case SHIFTED_LOGIC_IMM: | |
535b785f | 3302 | if (aarch64_extend_operator_p (kind)) |
a06ea964 NC |
3303 | { |
3304 | set_syntax_error (_("extending shift is not permitted")); | |
3305 | return FALSE; | |
3306 | } | |
3307 | break; | |
3308 | ||
3309 | case SHIFTED_ARITH_IMM: | |
3310 | if (kind == AARCH64_MOD_ROR) | |
3311 | { | |
3312 | set_syntax_error (_("'ROR' shift is not permitted")); | |
3313 | return FALSE; | |
3314 | } | |
3315 | break; | |
3316 | ||
3317 | case SHIFTED_LSL: | |
3318 | if (kind != AARCH64_MOD_LSL) | |
3319 | { | |
3320 | set_syntax_error (_("only 'LSL' shift is permitted")); | |
3321 | return FALSE; | |
3322 | } | |
3323 | break; | |
3324 | ||
2442d846 RS |
3325 | case SHIFTED_MUL: |
3326 | if (kind != AARCH64_MOD_MUL) | |
3327 | { | |
3328 | set_syntax_error (_("only 'MUL' is permitted")); | |
3329 | return FALSE; | |
3330 | } | |
3331 | break; | |
3332 | ||
98907a70 RS |
3333 | case SHIFTED_MUL_VL: |
3334 | /* "MUL VL" consists of two separate tokens. Require the first | |
3335 | token to be "MUL" and look for a following "VL". */ | |
3336 | if (kind == AARCH64_MOD_MUL) | |
3337 | { | |
3338 | skip_whitespace (p); | |
3339 | if (strncasecmp (p, "vl", 2) == 0 && !ISALPHA (p[2])) | |
3340 | { | |
3341 | p += 2; | |
3342 | kind = AARCH64_MOD_MUL_VL; | |
3343 | break; | |
3344 | } | |
3345 | } | |
3346 | set_syntax_error (_("only 'MUL VL' is permitted")); | |
3347 | return FALSE; | |
3348 | ||
a06ea964 NC |
3349 | case SHIFTED_REG_OFFSET: |
3350 | if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL | |
3351 | && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX) | |
3352 | { | |
3353 | set_fatal_syntax_error | |
3354 | (_("invalid shift for the register offset addressing mode")); | |
3355 | return FALSE; | |
3356 | } | |
3357 | break; | |
3358 | ||
3359 | case SHIFTED_LSL_MSL: | |
3360 | if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL) | |
3361 | { | |
3362 | set_syntax_error (_("invalid shift operator")); | |
3363 | return FALSE; | |
3364 | } | |
3365 | break; | |
3366 | ||
3367 | default: | |
3368 | abort (); | |
3369 | } | |
3370 | ||
3371 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
3372 | skip_whitespace (p); | |
3373 | ||
3374 | /* Parse shift amount. */ | |
3375 | exp_has_prefix = 0; | |
98907a70 | 3376 | if ((mode == SHIFTED_REG_OFFSET && *p == ']') || kind == AARCH64_MOD_MUL_VL) |
a06ea964 NC |
3377 | exp.X_op = O_absent; |
3378 | else | |
3379 | { | |
3380 | if (is_immediate_prefix (*p)) | |
3381 | { | |
3382 | p++; | |
3383 | exp_has_prefix = 1; | |
3384 | } | |
3385 | my_get_expression (&exp, &p, GE_NO_PREFIX, 0); | |
3386 | } | |
98907a70 RS |
3387 | if (kind == AARCH64_MOD_MUL_VL) |
3388 | /* For consistency, give MUL VL the same shift amount as an implicit | |
3389 | MUL #1. */ | |
3390 | operand->shifter.amount = 1; | |
3391 | else if (exp.X_op == O_absent) | |
a06ea964 | 3392 | { |
535b785f | 3393 | if (!aarch64_extend_operator_p (kind) || exp_has_prefix) |
a06ea964 NC |
3394 | { |
3395 | set_syntax_error (_("missing shift amount")); | |
3396 | return FALSE; | |
3397 | } | |
3398 | operand->shifter.amount = 0; | |
3399 | } | |
3400 | else if (exp.X_op != O_constant) | |
3401 | { | |
3402 | set_syntax_error (_("constant shift amount required")); | |
3403 | return FALSE; | |
3404 | } | |
2442d846 RS |
3405 | /* For parsing purposes, MUL #n has no inherent range. The range |
3406 | depends on the operand and will be checked by operand-specific | |
3407 | routines. */ | |
3408 | else if (kind != AARCH64_MOD_MUL | |
3409 | && (exp.X_add_number < 0 || exp.X_add_number > 63)) | |
a06ea964 NC |
3410 | { |
3411 | set_fatal_syntax_error (_("shift amount out of range 0 to 63")); | |
3412 | return FALSE; | |
3413 | } | |
3414 | else | |
3415 | { | |
3416 | operand->shifter.amount = exp.X_add_number; | |
3417 | operand->shifter.amount_present = 1; | |
3418 | } | |
3419 | ||
3420 | operand->shifter.operator_present = 1; | |
3421 | operand->shifter.kind = kind; | |
3422 | ||
3423 | *str = p; | |
3424 | return TRUE; | |
3425 | } | |
3426 | ||
3427 | /* Parse a <shifter_operand> for a data processing instruction: | |
3428 | ||
3429 | #<immediate> | |
3430 | #<immediate>, LSL #imm | |
3431 | ||
3432 | Validation of immediate operands is deferred to md_apply_fix. | |
3433 | ||
3434 | Return TRUE on success; otherwise return FALSE. */ | |
3435 | ||
3436 | static bfd_boolean | |
3437 | parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand, | |
3438 | enum parse_shift_mode mode) | |
3439 | { | |
3440 | char *p; | |
3441 | ||
3442 | if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM) | |
3443 | return FALSE; | |
3444 | ||
3445 | p = *str; | |
3446 | ||
3447 | /* Accept an immediate expression. */ | |
3448 | if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1)) | |
3449 | return FALSE; | |
3450 | ||
3451 | /* Accept optional LSL for arithmetic immediate values. */ | |
3452 | if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p)) | |
3453 | if (! parse_shift (&p, operand, SHIFTED_LSL)) | |
3454 | return FALSE; | |
3455 | ||
3456 | /* Not accept any shifter for logical immediate values. */ | |
3457 | if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p) | |
3458 | && parse_shift (&p, operand, mode)) | |
3459 | { | |
3460 | set_syntax_error (_("unexpected shift operator")); | |
3461 | return FALSE; | |
3462 | } | |
3463 | ||
3464 | *str = p; | |
3465 | return TRUE; | |
3466 | } | |
3467 | ||
3468 | /* Parse a <shifter_operand> for a data processing instruction: | |
3469 | ||
3470 | <Rm> | |
3471 | <Rm>, <shift> | |
3472 | #<immediate> | |
3473 | #<immediate>, LSL #imm | |
3474 | ||
3475 | where <shift> is handled by parse_shift above, and the last two | |
3476 | cases are handled by the function above. | |
3477 | ||
3478 | Validation of immediate operands is deferred to md_apply_fix. | |
3479 | ||
3480 | Return TRUE on success; otherwise return FALSE. */ | |
3481 | ||
3482 | static bfd_boolean | |
3483 | parse_shifter_operand (char **str, aarch64_opnd_info *operand, | |
3484 | enum parse_shift_mode mode) | |
3485 | { | |
e1b988bb RS |
3486 | const reg_entry *reg; |
3487 | aarch64_opnd_qualifier_t qualifier; | |
a06ea964 NC |
3488 | enum aarch64_operand_class opd_class |
3489 | = aarch64_get_operand_class (operand->type); | |
3490 | ||
e1b988bb RS |
3491 | reg = aarch64_reg_parse_32_64 (str, &qualifier); |
3492 | if (reg) | |
a06ea964 NC |
3493 | { |
3494 | if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE) | |
3495 | { | |
3496 | set_syntax_error (_("unexpected register in the immediate operand")); | |
3497 | return FALSE; | |
3498 | } | |
3499 | ||
e1b988bb | 3500 | if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z)) |
a06ea964 | 3501 | { |
e1b988bb | 3502 | set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z))); |
a06ea964 NC |
3503 | return FALSE; |
3504 | } | |
3505 | ||
e1b988bb RS |
3506 | operand->reg.regno = reg->number; |
3507 | operand->qualifier = qualifier; | |
a06ea964 NC |
3508 | |
3509 | /* Accept optional shift operation on register. */ | |
3510 | if (! skip_past_comma (str)) | |
3511 | return TRUE; | |
3512 | ||
3513 | if (! parse_shift (str, operand, mode)) | |
3514 | return FALSE; | |
3515 | ||
3516 | return TRUE; | |
3517 | } | |
3518 | else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG) | |
3519 | { | |
3520 | set_syntax_error | |
3521 | (_("integer register expected in the extended/shifted operand " | |
3522 | "register")); | |
3523 | return FALSE; | |
3524 | } | |
3525 | ||
3526 | /* We have a shifted immediate variable. */ | |
3527 | return parse_shifter_operand_imm (str, operand, mode); | |
3528 | } | |
3529 | ||
3530 | /* Return TRUE on success; return FALSE otherwise. */ | |
3531 | ||
3532 | static bfd_boolean | |
3533 | parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand, | |
3534 | enum parse_shift_mode mode) | |
3535 | { | |
3536 | char *p = *str; | |
3537 | ||
3538 | /* Determine if we have the sequence of characters #: or just : | |
3539 | coming next. If we do, then we check for a :rello: relocation | |
3540 | modifier. If we don't, punt the whole lot to | |
3541 | parse_shifter_operand. */ | |
3542 | ||
3543 | if ((p[0] == '#' && p[1] == ':') || p[0] == ':') | |
3544 | { | |
3545 | struct reloc_table_entry *entry; | |
3546 | ||
3547 | if (p[0] == '#') | |
3548 | p += 2; | |
3549 | else | |
3550 | p++; | |
3551 | *str = p; | |
3552 | ||
3553 | /* Try to parse a relocation. Anything else is an error. */ | |
3554 | if (!(entry = find_reloc_table_entry (str))) | |
3555 | { | |
3556 | set_syntax_error (_("unknown relocation modifier")); | |
3557 | return FALSE; | |
3558 | } | |
3559 | ||
3560 | if (entry->add_type == 0) | |
3561 | { | |
3562 | set_syntax_error | |
3563 | (_("this relocation modifier is not allowed on this instruction")); | |
3564 | return FALSE; | |
3565 | } | |
3566 | ||
3567 | /* Save str before we decompose it. */ | |
3568 | p = *str; | |
3569 | ||
3570 | /* Next, we parse the expression. */ | |
3571 | if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1)) | |
3572 | return FALSE; | |
3573 | ||
3574 | /* Record the relocation type (use the ADD variant here). */ | |
3575 | inst.reloc.type = entry->add_type; | |
3576 | inst.reloc.pc_rel = entry->pc_rel; | |
3577 | ||
3578 | /* If str is empty, we've reached the end, stop here. */ | |
3579 | if (**str == '\0') | |
3580 | return TRUE; | |
3581 | ||
55d9b4c1 | 3582 | /* Otherwise, we have a shifted reloc modifier, so rewind to |
a06ea964 NC |
3583 | recover the variable name and continue parsing for the shifter. */ |
3584 | *str = p; | |
3585 | return parse_shifter_operand_imm (str, operand, mode); | |
3586 | } | |
3587 | ||
3588 | return parse_shifter_operand (str, operand, mode); | |
3589 | } | |
3590 | ||
3591 | /* Parse all forms of an address expression. Information is written | |
3592 | to *OPERAND and/or inst.reloc. | |
3593 | ||
3594 | The A64 instruction set has the following addressing modes: | |
3595 | ||
3596 | Offset | |
4df068de RS |
3597 | [base] // in SIMD ld/st structure |
3598 | [base{,#0}] // in ld/st exclusive | |
a06ea964 NC |
3599 | [base{,#imm}] |
3600 | [base,Xm{,LSL #imm}] | |
3601 | [base,Xm,SXTX {#imm}] | |
3602 | [base,Wm,(S|U)XTW {#imm}] | |
3603 | Pre-indexed | |
1820262b | 3604 | [base]! // in ldraa/ldrab exclusive |
a06ea964 NC |
3605 | [base,#imm]! |
3606 | Post-indexed | |
3607 | [base],#imm | |
4df068de | 3608 | [base],Xm // in SIMD ld/st structure |
a06ea964 NC |
3609 | PC-relative (literal) |
3610 | label | |
4df068de | 3611 | SVE: |
98907a70 | 3612 | [base,#imm,MUL VL] |
4df068de RS |
3613 | [base,Zm.D{,LSL #imm}] |
3614 | [base,Zm.S,(S|U)XTW {#imm}] | |
3615 | [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements | |
3616 | [Zn.S,#imm] | |
3617 | [Zn.D,#imm] | |
c469c864 | 3618 | [Zn.S{, Xm}] |
4df068de RS |
3619 | [Zn.S,Zm.S{,LSL #imm}] // in ADR |
3620 | [Zn.D,Zm.D{,LSL #imm}] // in ADR | |
3621 | [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR | |
a06ea964 NC |
3622 | |
3623 | (As a convenience, the notation "=immediate" is permitted in conjunction | |
3624 | with the pc-relative literal load instructions to automatically place an | |
3625 | immediate value or symbolic address in a nearby literal pool and generate | |
3626 | a hidden label which references it.) | |
3627 | ||
3628 | Upon a successful parsing, the address structure in *OPERAND will be | |
3629 | filled in the following way: | |
3630 | ||
3631 | .base_regno = <base> | |
3632 | .offset.is_reg // 1 if the offset is a register | |
3633 | .offset.imm = <imm> | |
3634 | .offset.regno = <Rm> | |
3635 | ||
3636 | For different addressing modes defined in the A64 ISA: | |
3637 | ||
3638 | Offset | |
3639 | .pcrel=0; .preind=1; .postind=0; .writeback=0 | |
3640 | Pre-indexed | |
3641 | .pcrel=0; .preind=1; .postind=0; .writeback=1 | |
3642 | Post-indexed | |
3643 | .pcrel=0; .preind=0; .postind=1; .writeback=1 | |
3644 | PC-relative (literal) | |
3645 | .pcrel=1; .preind=1; .postind=0; .writeback=0 | |
3646 | ||
3647 | The shift/extension information, if any, will be stored in .shifter. | |
4df068de RS |
3648 | The base and offset qualifiers will be stored in *BASE_QUALIFIER and |
3649 | *OFFSET_QUALIFIER respectively, with NIL being used if there's no | |
3650 | corresponding register. | |
a06ea964 | 3651 | |
4df068de | 3652 | BASE_TYPE says which types of base register should be accepted and |
98907a70 RS |
3653 | OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE |
3654 | is the type of shifter that is allowed for immediate offsets, | |
3655 | or SHIFTED_NONE if none. | |
3656 | ||
3657 | In all other respects, it is the caller's responsibility to check | |
3658 | for addressing modes not supported by the instruction, and to set | |
3659 | inst.reloc.type. */ | |
a06ea964 NC |
3660 | |
3661 | static bfd_boolean | |
4df068de RS |
3662 | parse_address_main (char **str, aarch64_opnd_info *operand, |
3663 | aarch64_opnd_qualifier_t *base_qualifier, | |
3664 | aarch64_opnd_qualifier_t *offset_qualifier, | |
98907a70 RS |
3665 | aarch64_reg_type base_type, aarch64_reg_type offset_type, |
3666 | enum parse_shift_mode imm_shift_mode) | |
a06ea964 NC |
3667 | { |
3668 | char *p = *str; | |
e1b988bb | 3669 | const reg_entry *reg; |
a06ea964 NC |
3670 | expressionS *exp = &inst.reloc.exp; |
3671 | ||
4df068de RS |
3672 | *base_qualifier = AARCH64_OPND_QLF_NIL; |
3673 | *offset_qualifier = AARCH64_OPND_QLF_NIL; | |
a06ea964 NC |
3674 | if (! skip_past_char (&p, '[')) |
3675 | { | |
3676 | /* =immediate or label. */ | |
3677 | operand->addr.pcrel = 1; | |
3678 | operand->addr.preind = 1; | |
3679 | ||
f41aef5f RE |
3680 | /* #:<reloc_op>:<symbol> */ |
3681 | skip_past_char (&p, '#'); | |
73866052 | 3682 | if (skip_past_char (&p, ':')) |
f41aef5f | 3683 | { |
6f4a313b | 3684 | bfd_reloc_code_real_type ty; |
f41aef5f RE |
3685 | struct reloc_table_entry *entry; |
3686 | ||
3687 | /* Try to parse a relocation modifier. Anything else is | |
3688 | an error. */ | |
3689 | entry = find_reloc_table_entry (&p); | |
3690 | if (! entry) | |
3691 | { | |
3692 | set_syntax_error (_("unknown relocation modifier")); | |
3693 | return FALSE; | |
3694 | } | |
3695 | ||
6f4a313b MS |
3696 | switch (operand->type) |
3697 | { | |
3698 | case AARCH64_OPND_ADDR_PCREL21: | |
3699 | /* adr */ | |
3700 | ty = entry->adr_type; | |
3701 | break; | |
3702 | ||
3703 | default: | |
74ad790c | 3704 | ty = entry->ld_literal_type; |
6f4a313b MS |
3705 | break; |
3706 | } | |
3707 | ||
3708 | if (ty == 0) | |
f41aef5f RE |
3709 | { |
3710 | set_syntax_error | |
3711 | (_("this relocation modifier is not allowed on this " | |
3712 | "instruction")); | |
3713 | return FALSE; | |
3714 | } | |
3715 | ||
3716 | /* #:<reloc_op>: */ | |
3717 | if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1)) | |
3718 | { | |
3719 | set_syntax_error (_("invalid relocation expression")); | |
3720 | return FALSE; | |
3721 | } | |
a06ea964 | 3722 | |
f41aef5f | 3723 | /* #:<reloc_op>:<expr> */ |
6f4a313b MS |
3724 | /* Record the relocation type. */ |
3725 | inst.reloc.type = ty; | |
f41aef5f RE |
3726 | inst.reloc.pc_rel = entry->pc_rel; |
3727 | } | |
3728 | else | |
a06ea964 | 3729 | { |
f41aef5f RE |
3730 | |
3731 | if (skip_past_char (&p, '=')) | |
3732 | /* =immediate; need to generate the literal in the literal pool. */ | |
3733 | inst.gen_lit_pool = 1; | |
3734 | ||
3735 | if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1)) | |
3736 | { | |
3737 | set_syntax_error (_("invalid address")); | |
3738 | return FALSE; | |
3739 | } | |
a06ea964 NC |
3740 | } |
3741 | ||
3742 | *str = p; | |
3743 | return TRUE; | |
3744 | } | |
3745 | ||
3746 | /* [ */ | |
3747 | ||
4df068de RS |
3748 | reg = aarch64_addr_reg_parse (&p, base_type, base_qualifier); |
3749 | if (!reg || !aarch64_check_reg_type (reg, base_type)) | |
a06ea964 | 3750 | { |
4df068de | 3751 | set_syntax_error (_(get_reg_expected_msg (base_type))); |
a06ea964 NC |
3752 | return FALSE; |
3753 | } | |
e1b988bb | 3754 | operand->addr.base_regno = reg->number; |
a06ea964 NC |
3755 | |
3756 | /* [Xn */ | |
3757 | if (skip_past_comma (&p)) | |
3758 | { | |
3759 | /* [Xn, */ | |
3760 | operand->addr.preind = 1; | |
3761 | ||
4df068de | 3762 | reg = aarch64_addr_reg_parse (&p, offset_type, offset_qualifier); |
e1b988bb | 3763 | if (reg) |
a06ea964 | 3764 | { |
4df068de | 3765 | if (!aarch64_check_reg_type (reg, offset_type)) |
e1b988bb | 3766 | { |
4df068de | 3767 | set_syntax_error (_(get_reg_expected_msg (offset_type))); |
e1b988bb RS |
3768 | return FALSE; |
3769 | } | |
3770 | ||
a06ea964 | 3771 | /* [Xn,Rm */ |
e1b988bb | 3772 | operand->addr.offset.regno = reg->number; |
a06ea964 NC |
3773 | operand->addr.offset.is_reg = 1; |
3774 | /* Shifted index. */ | |
3775 | if (skip_past_comma (&p)) | |
3776 | { | |
3777 | /* [Xn,Rm, */ | |
3778 | if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET)) | |
3779 | /* Use the diagnostics set in parse_shift, so not set new | |
3780 | error message here. */ | |
3781 | return FALSE; | |
3782 | } | |
3783 | /* We only accept: | |
c469c864 | 3784 | [base,Xm] # For vector plus scalar SVE2 indexing. |
a06ea964 NC |
3785 | [base,Xm{,LSL #imm}] |
3786 | [base,Xm,SXTX {#imm}] | |
3787 | [base,Wm,(S|U)XTW {#imm}] */ | |
3788 | if (operand->shifter.kind == AARCH64_MOD_NONE | |
3789 | || operand->shifter.kind == AARCH64_MOD_LSL | |
3790 | || operand->shifter.kind == AARCH64_MOD_SXTX) | |
3791 | { | |
4df068de | 3792 | if (*offset_qualifier == AARCH64_OPND_QLF_W) |
a06ea964 NC |
3793 | { |
3794 | set_syntax_error (_("invalid use of 32-bit register offset")); | |
3795 | return FALSE; | |
3796 | } | |
4df068de | 3797 | if (aarch64_get_qualifier_esize (*base_qualifier) |
c469c864 MM |
3798 | != aarch64_get_qualifier_esize (*offset_qualifier) |
3799 | && (operand->type != AARCH64_OPND_SVE_ADDR_ZX | |
3800 | || *base_qualifier != AARCH64_OPND_QLF_S_S | |
f260da95 SP |
3801 | || *offset_qualifier != AARCH64_OPND_QLF_X) |
3802 | /* Capabilities can have W as well as X registers as | |
3803 | offsets. */ | |
3804 | && (*base_qualifier != AARCH64_OPND_QLF_CA)) | |
4df068de RS |
3805 | { |
3806 | set_syntax_error (_("offset has different size from base")); | |
3807 | return FALSE; | |
3808 | } | |
a06ea964 | 3809 | } |
4df068de | 3810 | else if (*offset_qualifier == AARCH64_OPND_QLF_X) |
a06ea964 NC |
3811 | { |
3812 | set_syntax_error (_("invalid use of 64-bit register offset")); | |
3813 | return FALSE; | |
3814 | } | |
3815 | } | |
3816 | else | |
3817 | { | |
3818 | /* [Xn,#:<reloc_op>:<symbol> */ | |
3819 | skip_past_char (&p, '#'); | |
73866052 | 3820 | if (skip_past_char (&p, ':')) |
a06ea964 NC |
3821 | { |
3822 | struct reloc_table_entry *entry; | |
3823 | ||
3824 | /* Try to parse a relocation modifier. Anything else is | |
3825 | an error. */ | |
3826 | if (!(entry = find_reloc_table_entry (&p))) | |
3827 | { | |
3828 | set_syntax_error (_("unknown relocation modifier")); | |
3829 | return FALSE; | |
3830 | } | |
3831 | ||
3832 | if (entry->ldst_type == 0) | |
3833 | { | |
3834 | set_syntax_error | |
3835 | (_("this relocation modifier is not allowed on this " | |
3836 | "instruction")); | |
3837 | return FALSE; | |
3838 | } | |
3839 | ||
3840 | /* [Xn,#:<reloc_op>: */ | |
3841 | /* We now have the group relocation table entry corresponding to | |
3842 | the name in the assembler source. Next, we parse the | |
3843 | expression. */ | |
3844 | if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1)) | |
3845 | { | |
3846 | set_syntax_error (_("invalid relocation expression")); | |
3847 | return FALSE; | |
3848 | } | |
3849 | ||
3850 | /* [Xn,#:<reloc_op>:<expr> */ | |
3851 | /* Record the load/store relocation type. */ | |
3852 | inst.reloc.type = entry->ldst_type; | |
3853 | inst.reloc.pc_rel = entry->pc_rel; | |
3854 | } | |
98907a70 | 3855 | else |
a06ea964 | 3856 | { |
98907a70 RS |
3857 | if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1)) |
3858 | { | |
3859 | set_syntax_error (_("invalid expression in the address")); | |
3860 | return FALSE; | |
3861 | } | |
3862 | /* [Xn,<expr> */ | |
3863 | if (imm_shift_mode != SHIFTED_NONE && skip_past_comma (&p)) | |
3864 | /* [Xn,<expr>,<shifter> */ | |
3865 | if (! parse_shift (&p, operand, imm_shift_mode)) | |
3866 | return FALSE; | |
a06ea964 | 3867 | } |
a06ea964 NC |
3868 | } |
3869 | } | |
3870 | ||
3871 | if (! skip_past_char (&p, ']')) | |
3872 | { | |
3873 | set_syntax_error (_("']' expected")); | |
3874 | return FALSE; | |
3875 | } | |
3876 | ||
3877 | if (skip_past_char (&p, '!')) | |
3878 | { | |
3879 | if (operand->addr.preind && operand->addr.offset.is_reg) | |
3880 | { | |
3881 | set_syntax_error (_("register offset not allowed in pre-indexed " | |
3882 | "addressing mode")); | |
3883 | return FALSE; | |
3884 | } | |
3885 | /* [Xn]! */ | |
3886 | operand->addr.writeback = 1; | |
3887 | } | |
3888 | else if (skip_past_comma (&p)) | |
3889 | { | |
3890 | /* [Xn], */ | |
3891 | operand->addr.postind = 1; | |
3892 | operand->addr.writeback = 1; | |
3893 | ||
3894 | if (operand->addr.preind) | |
3895 | { | |
3896 | set_syntax_error (_("cannot combine pre- and post-indexing")); | |
3897 | return FALSE; | |
3898 | } | |
3899 | ||
4df068de | 3900 | reg = aarch64_reg_parse_32_64 (&p, offset_qualifier); |
73866052 | 3901 | if (reg) |
a06ea964 NC |
3902 | { |
3903 | /* [Xn],Xm */ | |
e1b988bb | 3904 | if (!aarch64_check_reg_type (reg, REG_TYPE_R_64)) |
a06ea964 | 3905 | { |
e1b988bb | 3906 | set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64))); |
a06ea964 NC |
3907 | return FALSE; |
3908 | } | |
e1b988bb RS |
3909 | |
3910 | operand->addr.offset.regno = reg->number; | |
a06ea964 NC |
3911 | operand->addr.offset.is_reg = 1; |
3912 | } | |
3913 | else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1)) | |
3914 | { | |
3915 | /* [Xn],#expr */ | |
3916 | set_syntax_error (_("invalid expression in the address")); | |
3917 | return FALSE; | |
3918 | } | |
3919 | } | |
3920 | ||
3921 | /* If at this point neither .preind nor .postind is set, we have a | |
1820262b DB |
3922 | bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and |
3923 | ldrab, accept [Rn] as a shorthand for [Rn,#0]. | |
c469c864 MM |
3924 | For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for |
3925 | [Zn.<T>, xzr]. */ | |
a06ea964 NC |
3926 | if (operand->addr.preind == 0 && operand->addr.postind == 0) |
3927 | { | |
550fd7bf | 3928 | if (operand->addr.writeback) |
a06ea964 | 3929 | { |
1820262b DB |
3930 | if (operand->type == AARCH64_OPND_ADDR_SIMM10) |
3931 | { | |
3932 | /* Accept [Rn]! as a shorthand for [Rn,#0]! */ | |
3933 | operand->addr.offset.is_reg = 0; | |
3934 | operand->addr.offset.imm = 0; | |
3935 | operand->addr.preind = 1; | |
3936 | } | |
3937 | else | |
3938 | { | |
3939 | /* Reject [Rn]! */ | |
3940 | set_syntax_error (_("missing offset in the pre-indexed address")); | |
3941 | return FALSE; | |
3942 | } | |
a06ea964 | 3943 | } |
1820262b | 3944 | else |
c469c864 | 3945 | { |
1820262b DB |
3946 | operand->addr.preind = 1; |
3947 | if (operand->type == AARCH64_OPND_SVE_ADDR_ZX) | |
3948 | { | |
3949 | operand->addr.offset.is_reg = 1; | |
3950 | operand->addr.offset.regno = REG_ZR; | |
3951 | *offset_qualifier = AARCH64_OPND_QLF_X; | |
3952 | } | |
3953 | else | |
3954 | { | |
3955 | inst.reloc.exp.X_op = O_constant; | |
3956 | inst.reloc.exp.X_add_number = 0; | |
3957 | } | |
c469c864 | 3958 | } |
a06ea964 NC |
3959 | } |
3960 | ||
3961 | *str = p; | |
3962 | return TRUE; | |
3963 | } | |
3964 | ||
73866052 RS |
3965 | /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE |
3966 | on success. */ | |
a06ea964 | 3967 | static bfd_boolean |
73866052 | 3968 | parse_address (char **str, aarch64_opnd_info *operand) |
a06ea964 | 3969 | { |
4df068de | 3970 | aarch64_opnd_qualifier_t base_qualifier, offset_qualifier; |
3493da5c SP |
3971 | |
3972 | aarch64_reg_type base; | |
3973 | ||
3974 | if (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64)) | |
3975 | base = REG_TYPE_CA_N_SP; | |
3976 | else | |
3977 | base = REG_TYPE_R64_SP; | |
3978 | ||
4df068de | 3979 | return parse_address_main (str, operand, &base_qualifier, &offset_qualifier, |
3493da5c | 3980 | base, REG_TYPE_R_Z, SHIFTED_NONE); |
4df068de RS |
3981 | } |
3982 | ||
f260da95 SP |
3983 | /* Parse a base capability address. Return TRUE on success. */ |
3984 | static bfd_boolean | |
3985 | parse_cap_address (char **str, aarch64_opnd_info *operand, | |
3986 | enum aarch64_insn_class class) | |
3987 | { | |
3988 | aarch64_opnd_qualifier_t base_qualifier, offset_qualifier; | |
3989 | aarch64_reg_type base; | |
3990 | ||
3991 | if (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64) | |
3992 | && class != br_capaddr) | |
3993 | base = REG_TYPE_R64_SP; | |
3994 | else | |
3995 | base = REG_TYPE_CA_N_SP; | |
3996 | ||
3997 | return parse_address_main (str, operand, &base_qualifier, &offset_qualifier, | |
3998 | base, REG_TYPE_R_Z, SHIFTED_NONE); | |
3999 | } | |
4000 | ||
98907a70 | 4001 | /* Parse an address in which SVE vector registers and MUL VL are allowed. |
4df068de RS |
4002 | The arguments have the same meaning as for parse_address_main. |
4003 | Return TRUE on success. */ | |
4004 | static bfd_boolean | |
4005 | parse_sve_address (char **str, aarch64_opnd_info *operand, | |
4006 | aarch64_opnd_qualifier_t *base_qualifier, | |
4007 | aarch64_opnd_qualifier_t *offset_qualifier) | |
4008 | { | |
4009 | return parse_address_main (str, operand, base_qualifier, offset_qualifier, | |
98907a70 RS |
4010 | REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET, |
4011 | SHIFTED_MUL_VL); | |
a06ea964 NC |
4012 | } |
4013 | ||
4014 | /* Parse an operand for a MOVZ, MOVN or MOVK instruction. | |
4015 | Return TRUE on success; otherwise return FALSE. */ | |
4016 | static bfd_boolean | |
4017 | parse_half (char **str, int *internal_fixup_p) | |
4018 | { | |
671eeb28 | 4019 | char *p = *str; |
a06ea964 | 4020 | |
a06ea964 NC |
4021 | skip_past_char (&p, '#'); |
4022 | ||
4023 | gas_assert (internal_fixup_p); | |
4024 | *internal_fixup_p = 0; | |
4025 | ||
4026 | if (*p == ':') | |
4027 | { | |
4028 | struct reloc_table_entry *entry; | |
4029 | ||
4030 | /* Try to parse a relocation. Anything else is an error. */ | |
4031 | ++p; | |
4032 | if (!(entry = find_reloc_table_entry (&p))) | |
4033 | { | |
4034 | set_syntax_error (_("unknown relocation modifier")); | |
4035 | return FALSE; | |
4036 | } | |
4037 | ||
4038 | if (entry->movw_type == 0) | |
4039 | { | |
4040 | set_syntax_error | |
4041 | (_("this relocation modifier is not allowed on this instruction")); | |
4042 | return FALSE; | |
4043 | } | |
4044 | ||
4045 | inst.reloc.type = entry->movw_type; | |
4046 | } | |
4047 | else | |
4048 | *internal_fixup_p = 1; | |
4049 | ||
a06ea964 NC |
4050 | if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1)) |
4051 | return FALSE; | |
4052 | ||
4053 | *str = p; | |
4054 | return TRUE; | |
4055 | } | |
4056 | ||
4057 | /* Parse an operand for an ADRP instruction: | |
4058 | ADRP <Xd>, <label> | |
4059 | Return TRUE on success; otherwise return FALSE. */ | |
4060 | ||
4061 | static bfd_boolean | |
4062 | parse_adrp (char **str) | |
4063 | { | |
4064 | char *p; | |
4065 | ||
4066 | p = *str; | |
4067 | if (*p == ':') | |
4068 | { | |
4069 | struct reloc_table_entry *entry; | |
92504105 | 4070 | bfd_reloc_code_real_type adrp_type; |
a06ea964 NC |
4071 | |
4072 | /* Try to parse a relocation. Anything else is an error. */ | |
4073 | ++p; | |
4074 | if (!(entry = find_reloc_table_entry (&p))) | |
4075 | { | |
4076 | set_syntax_error (_("unknown relocation modifier")); | |
4077 | return FALSE; | |
4078 | } | |
4079 | ||
92504105 SP |
4080 | adrp_type = (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64) |
4081 | ? entry->c64_adrp_type : entry->adrp_type); | |
4082 | ||
4083 | if (adrp_type == 0) | |
a06ea964 NC |
4084 | { |
4085 | set_syntax_error | |
4086 | (_("this relocation modifier is not allowed on this instruction")); | |
4087 | return FALSE; | |
4088 | } | |
4089 | ||
92504105 | 4090 | inst.reloc.type = adrp_type; |
a06ea964 NC |
4091 | } |
4092 | else | |
92504105 SP |
4093 | inst.reloc.type = (AARCH64_CPU_HAS_FEATURE (cpu_variant, |
4094 | AARCH64_FEATURE_C64) | |
4095 | ? BFD_RELOC_MORELLO_ADR_HI20_PCREL | |
4096 | : BFD_RELOC_AARCH64_ADR_HI21_PCREL); | |
a06ea964 NC |
4097 | |
4098 | inst.reloc.pc_rel = 1; | |
4099 | ||
4100 | if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1)) | |
4101 | return FALSE; | |
4102 | ||
4103 | *str = p; | |
4104 | return TRUE; | |
4105 | } | |
4106 | ||
4107 | /* Miscellaneous. */ | |
4108 | ||
245d2e3f RS |
4109 | /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array |
4110 | of SIZE tokens in which index I gives the token for field value I, | |
4111 | or is null if field value I is invalid. REG_TYPE says which register | |
4112 | names should be treated as registers rather than as symbolic immediates. | |
4113 | ||
4114 | Return true on success, moving *STR past the operand and storing the | |
4115 | field value in *VAL. */ | |
4116 | ||
4117 | static int | |
4118 | parse_enum_string (char **str, int64_t *val, const char *const *array, | |
4119 | size_t size, aarch64_reg_type reg_type) | |
4120 | { | |
4121 | expressionS exp; | |
4122 | char *p, *q; | |
4123 | size_t i; | |
4124 | ||
4125 | /* Match C-like tokens. */ | |
4126 | p = q = *str; | |
4127 | while (ISALNUM (*q)) | |
4128 | q++; | |
4129 | ||
4130 | for (i = 0; i < size; ++i) | |
4131 | if (array[i] | |
4132 | && strncasecmp (array[i], p, q - p) == 0 | |
4133 | && array[i][q - p] == 0) | |
4134 | { | |
4135 | *val = i; | |
4136 | *str = q; | |
4137 | return TRUE; | |
4138 | } | |
4139 | ||
4140 | if (!parse_immediate_expression (&p, &exp, reg_type)) | |
4141 | return FALSE; | |
4142 | ||
4143 | if (exp.X_op == O_constant | |
4144 | && (uint64_t) exp.X_add_number < size) | |
4145 | { | |
4146 | *val = exp.X_add_number; | |
4147 | *str = p; | |
4148 | return TRUE; | |
4149 | } | |
4150 | ||
4151 | /* Use the default error for this operand. */ | |
4152 | return FALSE; | |
4153 | } | |
4154 | ||
a06ea964 NC |
4155 | /* Parse an option for a preload instruction. Returns the encoding for the |
4156 | option, or PARSE_FAIL. */ | |
4157 | ||
4158 | static int | |
4159 | parse_pldop (char **str) | |
4160 | { | |
4161 | char *p, *q; | |
4162 | const struct aarch64_name_value_pair *o; | |
4163 | ||
4164 | p = q = *str; | |
4165 | while (ISALNUM (*q)) | |
4166 | q++; | |
4167 | ||
629310ab | 4168 | o = str_hash_find_n (aarch64_pldop_hsh, p, q - p); |
a06ea964 NC |
4169 | if (!o) |
4170 | return PARSE_FAIL; | |
4171 | ||
4172 | *str = q; | |
4173 | return o->value; | |
4174 | } | |
4175 | ||
4176 | /* Parse an option for a barrier instruction. Returns the encoding for the | |
4177 | option, or PARSE_FAIL. */ | |
4178 | ||
4179 | static int | |
4180 | parse_barrier (char **str) | |
4181 | { | |
4182 | char *p, *q; | |
05cfb0d8 | 4183 | const struct aarch64_name_value_pair *o; |
a06ea964 NC |
4184 | |
4185 | p = q = *str; | |
4186 | while (ISALPHA (*q)) | |
4187 | q++; | |
4188 | ||
629310ab | 4189 | o = str_hash_find_n (aarch64_barrier_opt_hsh, p, q - p); |
a06ea964 NC |
4190 | if (!o) |
4191 | return PARSE_FAIL; | |
4192 | ||
4193 | *str = q; | |
4194 | return o->value; | |
4195 | } | |
4196 | ||
1e6f4800 MW |
4197 | /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record |
4198 | return 0 if successful. Otherwise return PARSE_FAIL. */ | |
4199 | ||
4200 | static int | |
4201 | parse_barrier_psb (char **str, | |
4202 | const struct aarch64_name_value_pair ** hint_opt) | |
4203 | { | |
4204 | char *p, *q; | |
4205 | const struct aarch64_name_value_pair *o; | |
4206 | ||
4207 | p = q = *str; | |
4208 | while (ISALPHA (*q)) | |
4209 | q++; | |
4210 | ||
629310ab | 4211 | o = str_hash_find_n (aarch64_hint_opt_hsh, p, q - p); |
1e6f4800 MW |
4212 | if (!o) |
4213 | { | |
4214 | set_fatal_syntax_error | |
c2e5c986 | 4215 | ( _("unknown or missing option to PSB/TSB")); |
1e6f4800 MW |
4216 | return PARSE_FAIL; |
4217 | } | |
4218 | ||
4219 | if (o->value != 0x11) | |
4220 | { | |
4221 | /* PSB only accepts option name 'CSYNC'. */ | |
4222 | set_syntax_error | |
c2e5c986 | 4223 | (_("the specified option is not accepted for PSB/TSB")); |
1e6f4800 MW |
4224 | return PARSE_FAIL; |
4225 | } | |
4226 | ||
4227 | *str = q; | |
4228 | *hint_opt = o; | |
4229 | return 0; | |
4230 | } | |
4231 | ||
ff605452 SD |
4232 | /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record |
4233 | return 0 if successful. Otherwise return PARSE_FAIL. */ | |
4234 | ||
4235 | static int | |
4236 | parse_bti_operand (char **str, | |
4237 | const struct aarch64_name_value_pair ** hint_opt) | |
4238 | { | |
4239 | char *p, *q; | |
4240 | const struct aarch64_name_value_pair *o; | |
4241 | ||
4242 | p = q = *str; | |
4243 | while (ISALPHA (*q)) | |
4244 | q++; | |
4245 | ||
629310ab | 4246 | o = str_hash_find_n (aarch64_hint_opt_hsh, p, q - p); |
ff605452 SD |
4247 | if (!o) |
4248 | { | |
4249 | set_fatal_syntax_error | |
4250 | ( _("unknown option to BTI")); | |
4251 | return PARSE_FAIL; | |
4252 | } | |
4253 | ||
4254 | switch (o->value) | |
4255 | { | |
4256 | /* Valid BTI operands. */ | |
4257 | case HINT_OPD_C: | |
4258 | case HINT_OPD_J: | |
4259 | case HINT_OPD_JC: | |
4260 | break; | |
4261 | ||
4262 | default: | |
4263 | set_syntax_error | |
4264 | (_("unknown option to BTI")); | |
4265 | return PARSE_FAIL; | |
4266 | } | |
4267 | ||
4268 | *str = q; | |
4269 | *hint_opt = o; | |
4270 | return 0; | |
4271 | } | |
4272 | ||
a06ea964 | 4273 | /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. |
a203d9b7 | 4274 | Returns the encoding for the option, or PARSE_FAIL. |
a06ea964 NC |
4275 | |
4276 | If IMPLE_DEFINED_P is non-zero, the function will also try to parse the | |
72ca8fad MW |
4277 | implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>. |
4278 | ||
4279 | If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE | |
4280 | field, otherwise as a system register. | |
4281 | */ | |
a06ea964 NC |
4282 | |
4283 | static int | |
801f0a7d | 4284 | parse_sys_reg (const aarch64_opcode *opcode, char **str, htab_t sys_regs, |
561a72d4 TC |
4285 | int imple_defined_p, int pstatefield_p, |
4286 | uint32_t* flags) | |
a06ea964 NC |
4287 | { |
4288 | char *p, *q; | |
fa63795f | 4289 | char buf[AARCH64_MAX_SYSREG_NAME_LEN]; |
49eec193 | 4290 | const aarch64_sys_reg *o; |
a06ea964 NC |
4291 | int value; |
4292 | ||
4293 | p = buf; | |
4294 | for (q = *str; ISALNUM (*q) || *q == '_'; q++) | |
fa63795f | 4295 | if (p < buf + (sizeof (buf) - 1)) |
a06ea964 NC |
4296 | *p++ = TOLOWER (*q); |
4297 | *p = '\0'; | |
fa63795f AC |
4298 | |
4299 | /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a | |
4300 | valid system register. This is enforced by construction of the hash | |
4301 | table. */ | |
4302 | if (p - buf != q - *str) | |
4303 | return PARSE_FAIL; | |
a06ea964 | 4304 | |
629310ab | 4305 | o = str_hash_find (sys_regs, buf); |
a06ea964 NC |
4306 | if (!o) |
4307 | { | |
4308 | if (!imple_defined_p) | |
4309 | return PARSE_FAIL; | |
4310 | else | |
4311 | { | |
df7b4545 | 4312 | /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */ |
a06ea964 | 4313 | unsigned int op0, op1, cn, cm, op2; |
df7b4545 JW |
4314 | |
4315 | if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) | |
4316 | != 5) | |
a06ea964 | 4317 | return PARSE_FAIL; |
df7b4545 | 4318 | if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7) |
a06ea964 NC |
4319 | return PARSE_FAIL; |
4320 | value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2; | |
561a72d4 TC |
4321 | if (flags) |
4322 | *flags = 0; | |
a06ea964 NC |
4323 | } |
4324 | } | |
4325 | else | |
49eec193 | 4326 | { |
801f0a7d SP |
4327 | if (!aarch64_sys_reg_capreg_supported_p (opcode->iclass, o)) |
4328 | return PARSE_FAIL; | |
4329 | ||
72ca8fad MW |
4330 | if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o)) |
4331 | as_bad (_("selected processor does not support PSTATE field " | |
4332 | "name '%s'"), buf); | |
f7cb161e | 4333 | if (!pstatefield_p |
38cf07a6 AC |
4334 | && !aarch64_sys_ins_reg_supported_p (cpu_variant, o->name, |
4335 | o->value, o->flags, o->features)) | |
72ca8fad MW |
4336 | as_bad (_("selected processor does not support system register " |
4337 | "name '%s'"), buf); | |
f7cb161e | 4338 | if (aarch64_sys_reg_deprecated_p (o->flags)) |
49eec193 | 4339 | as_warn (_("system register name '%s' is deprecated and may be " |
72ca8fad | 4340 | "removed in a future release"), buf); |
49eec193 | 4341 | value = o->value; |
561a72d4 TC |
4342 | if (flags) |
4343 | *flags = o->flags; | |
49eec193 | 4344 | } |
a06ea964 NC |
4345 | |
4346 | *str = q; | |
4347 | return value; | |
4348 | } | |
4349 | ||
4350 | /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry | |
4351 | for the option, or NULL. */ | |
4352 | ||
4353 | static const aarch64_sys_ins_reg * | |
629310ab | 4354 | parse_sys_ins_reg (char **str, htab_t sys_ins_regs) |
a06ea964 NC |
4355 | { |
4356 | char *p, *q; | |
fa63795f | 4357 | char buf[AARCH64_MAX_SYSREG_NAME_LEN]; |
a06ea964 NC |
4358 | const aarch64_sys_ins_reg *o; |
4359 | ||
4360 | p = buf; | |
4361 | for (q = *str; ISALNUM (*q) || *q == '_'; q++) | |
fa63795f | 4362 | if (p < buf + (sizeof (buf) - 1)) |
a06ea964 NC |
4363 | *p++ = TOLOWER (*q); |
4364 | *p = '\0'; | |
4365 | ||
fa63795f AC |
4366 | /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a |
4367 | valid system register. This is enforced by construction of the hash | |
4368 | table. */ | |
4369 | if (p - buf != q - *str) | |
4370 | return NULL; | |
4371 | ||
629310ab | 4372 | o = str_hash_find (sys_ins_regs, buf); |
a06ea964 NC |
4373 | if (!o) |
4374 | return NULL; | |
4375 | ||
38cf07a6 AC |
4376 | if (!aarch64_sys_ins_reg_supported_p (cpu_variant, |
4377 | o->name, o->value, o->flags, 0)) | |
d6bf7ce6 MW |
4378 | as_bad (_("selected processor does not support system register " |
4379 | "name '%s'"), buf); | |
f7cb161e PW |
4380 | if (aarch64_sys_reg_deprecated_p (o->flags)) |
4381 | as_warn (_("system register name '%s' is deprecated and may be " | |
4382 | "removed in a future release"), buf); | |
d6bf7ce6 | 4383 | |
a06ea964 NC |
4384 | *str = q; |
4385 | return o; | |
4386 | } | |
4387 | \f | |
4388 | #define po_char_or_fail(chr) do { \ | |
4389 | if (! skip_past_char (&str, chr)) \ | |
4390 | goto failure; \ | |
4391 | } while (0) | |
4392 | ||
4393 | #define po_reg_or_fail(regtype) do { \ | |
4394 | val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \ | |
4395 | if (val == PARSE_FAIL) \ | |
4396 | { \ | |
4397 | set_default_error (); \ | |
4398 | goto failure; \ | |
4399 | } \ | |
4400 | } while (0) | |
4401 | ||
e1b988bb RS |
4402 | #define po_int_reg_or_fail(reg_type) do { \ |
4403 | reg = aarch64_reg_parse_32_64 (&str, &qualifier); \ | |
4404 | if (!reg || !aarch64_check_reg_type (reg, reg_type)) \ | |
a06ea964 NC |
4405 | { \ |
4406 | set_default_error (); \ | |
4407 | goto failure; \ | |
4408 | } \ | |
e1b988bb RS |
4409 | info->reg.regno = reg->number; \ |
4410 | info->qualifier = qualifier; \ | |
a06ea964 NC |
4411 | } while (0) |
4412 | ||
4413 | #define po_imm_nc_or_fail() do { \ | |
1799c0d0 | 4414 | if (! parse_constant_immediate (&str, &val, imm_reg_type)) \ |
a06ea964 NC |
4415 | goto failure; \ |
4416 | } while (0) | |
4417 | ||
4418 | #define po_imm_or_fail(min, max) do { \ | |
1799c0d0 | 4419 | if (! parse_constant_immediate (&str, &val, imm_reg_type)) \ |
a06ea964 NC |
4420 | goto failure; \ |
4421 | if (val < min || val > max) \ | |
4422 | { \ | |
4423 | set_fatal_syntax_error (_("immediate value out of range "\ | |
4424 | #min " to "#max)); \ | |
4425 | goto failure; \ | |
4426 | } \ | |
4427 | } while (0) | |
4428 | ||
245d2e3f RS |
4429 | #define po_enum_or_fail(array) do { \ |
4430 | if (!parse_enum_string (&str, &val, array, \ | |
4431 | ARRAY_SIZE (array), imm_reg_type)) \ | |
4432 | goto failure; \ | |
4433 | } while (0) | |
4434 | ||
a06ea964 NC |
4435 | #define po_misc_or_fail(expr) do { \ |
4436 | if (!expr) \ | |
4437 | goto failure; \ | |
4438 | } while (0) | |
4439 | \f | |
4440 | /* encode the 12-bit imm field of Add/sub immediate */ | |
4441 | static inline uint32_t | |
4442 | encode_addsub_imm (uint32_t imm) | |
4443 | { | |
4444 | return imm << 10; | |
4445 | } | |
4446 | ||
4447 | /* encode the shift amount field of Add/sub immediate */ | |
4448 | static inline uint32_t | |
4449 | encode_addsub_imm_shift_amount (uint32_t cnt) | |
4450 | { | |
4451 | return cnt << 22; | |
4452 | } | |
4453 | ||
4454 | ||
4455 | /* encode the imm field of Adr instruction */ | |
4456 | static inline uint32_t | |
4457 | encode_adr_imm (uint32_t imm) | |
4458 | { | |
4459 | return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */ | |
4460 | | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */ | |
4461 | } | |
4462 | ||
4463 | /* encode the immediate field of Move wide immediate */ | |
4464 | static inline uint32_t | |
4465 | encode_movw_imm (uint32_t imm) | |
4466 | { | |
4467 | return imm << 5; | |
4468 | } | |
4469 | ||
4470 | /* encode the 26-bit offset of unconditional branch */ | |
4471 | static inline uint32_t | |
4472 | encode_branch_ofs_26 (uint32_t ofs) | |
4473 | { | |
4474 | return ofs & ((1 << 26) - 1); | |
4475 | } | |
4476 | ||
4477 | /* encode the 19-bit offset of conditional branch and compare & branch */ | |
4478 | static inline uint32_t | |
4479 | encode_cond_branch_ofs_19 (uint32_t ofs) | |
4480 | { | |
4481 | return (ofs & ((1 << 19) - 1)) << 5; | |
4482 | } | |
4483 | ||
f7d2c675 SP |
4484 | /* encode the 17-bit offset of ld literal */ |
4485 | static inline uint32_t | |
4486 | encode_ld_lit_ofs_17 (uint32_t ofs) | |
4487 | { | |
4488 | return (ofs & ((1 << 17) - 1)) << 5; | |
4489 | } | |
4490 | ||
a06ea964 NC |
4491 | /* encode the 19-bit offset of ld literal */ |
4492 | static inline uint32_t | |
4493 | encode_ld_lit_ofs_19 (uint32_t ofs) | |
4494 | { | |
4495 | return (ofs & ((1 << 19) - 1)) << 5; | |
4496 | } | |
4497 | ||
4498 | /* Encode the 14-bit offset of test & branch. */ | |
4499 | static inline uint32_t | |
4500 | encode_tst_branch_ofs_14 (uint32_t ofs) | |
4501 | { | |
4502 | return (ofs & ((1 << 14) - 1)) << 5; | |
4503 | } | |
4504 | ||
4505 | /* Encode the 16-bit imm field of svc/hvc/smc. */ | |
4506 | static inline uint32_t | |
4507 | encode_svc_imm (uint32_t imm) | |
4508 | { | |
4509 | return imm << 5; | |
4510 | } | |
4511 | ||
4512 | /* Reencode add(s) to sub(s), or sub(s) to add(s). */ | |
4513 | static inline uint32_t | |
4514 | reencode_addsub_switch_add_sub (uint32_t opcode) | |
4515 | { | |
4516 | return opcode ^ (1 << 30); | |
4517 | } | |
4518 | ||
4519 | static inline uint32_t | |
4520 | reencode_movzn_to_movz (uint32_t opcode) | |
4521 | { | |
4522 | return opcode | (1 << 30); | |
4523 | } | |
4524 | ||
4525 | static inline uint32_t | |
4526 | reencode_movzn_to_movn (uint32_t opcode) | |
4527 | { | |
4528 | return opcode & ~(1 << 30); | |
4529 | } | |
4530 | ||
4531 | /* Overall per-instruction processing. */ | |
4532 | ||
4533 | /* We need to be able to fix up arbitrary expressions in some statements. | |
4534 | This is so that we can handle symbols that are an arbitrary distance from | |
4535 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
4536 | which returns part of an address in a form which will be valid for | |
4537 | a data instruction. We do this by pushing the expression into a symbol | |
4538 | in the expr_section, and creating a fix for that. */ | |
4539 | ||
4540 | static fixS * | |
4541 | fix_new_aarch64 (fragS * frag, | |
4542 | int where, | |
f7cb161e PW |
4543 | short int size, |
4544 | expressionS * exp, | |
4545 | int pc_rel, | |
4546 | int reloc) | |
a06ea964 NC |
4547 | { |
4548 | fixS *new_fix; | |
4549 | ||
4550 | switch (exp->X_op) | |
4551 | { | |
4552 | case O_constant: | |
4553 | case O_symbol: | |
4554 | case O_add: | |
4555 | case O_subtract: | |
4556 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
4557 | break; | |
4558 | ||
4559 | default: | |
4560 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
4561 | pc_rel, reloc); | |
4562 | break; | |
4563 | } | |
4564 | return new_fix; | |
4565 | } | |
4566 | \f | |
4567 | /* Diagnostics on operands errors. */ | |
4568 | ||
a52e6fd3 YZ |
4569 | /* By default, output verbose error message. |
4570 | Disable the verbose error message by -mno-verbose-error. */ | |
4571 | static int verbose_error_p = 1; | |
a06ea964 NC |
4572 | |
4573 | #ifdef DEBUG_AARCH64 | |
4574 | /* N.B. this is only for the purpose of debugging. */ | |
4575 | const char* operand_mismatch_kind_names[] = | |
4576 | { | |
4577 | "AARCH64_OPDE_NIL", | |
4578 | "AARCH64_OPDE_RECOVERABLE", | |
4579 | "AARCH64_OPDE_SYNTAX_ERROR", | |
4580 | "AARCH64_OPDE_FATAL_SYNTAX_ERROR", | |
4581 | "AARCH64_OPDE_INVALID_VARIANT", | |
4582 | "AARCH64_OPDE_OUT_OF_RANGE", | |
4583 | "AARCH64_OPDE_UNALIGNED", | |
4584 | "AARCH64_OPDE_REG_LIST", | |
4585 | "AARCH64_OPDE_OTHER_ERROR", | |
4586 | }; | |
4587 | #endif /* DEBUG_AARCH64 */ | |
4588 | ||
4589 | /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE. | |
4590 | ||
4591 | When multiple errors of different kinds are found in the same assembly | |
4592 | line, only the error of the highest severity will be picked up for | |
4593 | issuing the diagnostics. */ | |
4594 | ||
4595 | static inline bfd_boolean | |
4596 | operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs, | |
4597 | enum aarch64_operand_error_kind rhs) | |
4598 | { | |
4599 | gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL); | |
4600 | gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE); | |
4601 | gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR); | |
4602 | gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR); | |
4603 | gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT); | |
4604 | gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE); | |
4605 | gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED); | |
4606 | gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST); | |
4607 | return lhs > rhs; | |
4608 | } | |
4609 | ||
4610 | /* Helper routine to get the mnemonic name from the assembly instruction | |
4611 | line; should only be called for the diagnosis purpose, as there is | |
4612 | string copy operation involved, which may affect the runtime | |
4613 | performance if used in elsewhere. */ | |
4614 | ||
4615 | static const char* | |
4616 | get_mnemonic_name (const char *str) | |
4617 | { | |
4618 | static char mnemonic[32]; | |
4619 | char *ptr; | |
4620 | ||
4621 | /* Get the first 15 bytes and assume that the full name is included. */ | |
4622 | strncpy (mnemonic, str, 31); | |
4623 | mnemonic[31] = '\0'; | |
4624 | ||
4625 | /* Scan up to the end of the mnemonic, which must end in white space, | |
4626 | '.', or end of string. */ | |
4627 | for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr) | |
4628 | ; | |
4629 | ||
4630 | *ptr = '\0'; | |
4631 | ||
4632 | /* Append '...' to the truncated long name. */ | |
4633 | if (ptr - mnemonic == 31) | |
4634 | mnemonic[28] = mnemonic[29] = mnemonic[30] = '.'; | |
4635 | ||
4636 | return mnemonic; | |
4637 | } | |
4638 | ||
4639 | static void | |
4640 | reset_aarch64_instruction (aarch64_instruction *instruction) | |
4641 | { | |
4642 | memset (instruction, '\0', sizeof (aarch64_instruction)); | |
4643 | instruction->reloc.type = BFD_RELOC_UNUSED; | |
4644 | } | |
4645 | ||
33eaf5de | 4646 | /* Data structures storing one user error in the assembly code related to |
a06ea964 NC |
4647 | operands. */ |
4648 | ||
4649 | struct operand_error_record | |
4650 | { | |
4651 | const aarch64_opcode *opcode; | |
4652 | aarch64_operand_error detail; | |
4653 | struct operand_error_record *next; | |
4654 | }; | |
4655 | ||
4656 | typedef struct operand_error_record operand_error_record; | |
4657 | ||
4658 | struct operand_errors | |
4659 | { | |
4660 | operand_error_record *head; | |
4661 | operand_error_record *tail; | |
4662 | }; | |
4663 | ||
4664 | typedef struct operand_errors operand_errors; | |
4665 | ||
4666 | /* Top-level data structure reporting user errors for the current line of | |
4667 | the assembly code. | |
4668 | The way md_assemble works is that all opcodes sharing the same mnemonic | |
4669 | name are iterated to find a match to the assembly line. In this data | |
4670 | structure, each of the such opcodes will have one operand_error_record | |
4671 | allocated and inserted. In other words, excessive errors related with | |
4672 | a single opcode are disregarded. */ | |
4673 | operand_errors operand_error_report; | |
4674 | ||
4675 | /* Free record nodes. */ | |
4676 | static operand_error_record *free_opnd_error_record_nodes = NULL; | |
4677 | ||
4678 | /* Initialize the data structure that stores the operand mismatch | |
4679 | information on assembling one line of the assembly code. */ | |
4680 | static void | |
4681 | init_operand_error_report (void) | |
4682 | { | |
4683 | if (operand_error_report.head != NULL) | |
4684 | { | |
4685 | gas_assert (operand_error_report.tail != NULL); | |
4686 | operand_error_report.tail->next = free_opnd_error_record_nodes; | |
4687 | free_opnd_error_record_nodes = operand_error_report.head; | |
4688 | operand_error_report.head = NULL; | |
4689 | operand_error_report.tail = NULL; | |
4690 | return; | |
4691 | } | |
4692 | gas_assert (operand_error_report.tail == NULL); | |
4693 | } | |
4694 | ||
4695 | /* Return TRUE if some operand error has been recorded during the | |
4696 | parsing of the current assembly line using the opcode *OPCODE; | |
4697 | otherwise return FALSE. */ | |
4698 | static inline bfd_boolean | |
4699 | opcode_has_operand_error_p (const aarch64_opcode *opcode) | |
4700 | { | |
4701 | operand_error_record *record = operand_error_report.head; | |
4702 | return record && record->opcode == opcode; | |
4703 | } | |
4704 | ||
4705 | /* Add the error record *NEW_RECORD to operand_error_report. The record's | |
4706 | OPCODE field is initialized with OPCODE. | |
4707 | N.B. only one record for each opcode, i.e. the maximum of one error is | |
4708 | recorded for each instruction template. */ | |
4709 | ||
4710 | static void | |
4711 | add_operand_error_record (const operand_error_record* new_record) | |
4712 | { | |
4713 | const aarch64_opcode *opcode = new_record->opcode; | |
4714 | operand_error_record* record = operand_error_report.head; | |
4715 | ||
4716 | /* The record may have been created for this opcode. If not, we need | |
4717 | to prepare one. */ | |
4718 | if (! opcode_has_operand_error_p (opcode)) | |
4719 | { | |
4720 | /* Get one empty record. */ | |
4721 | if (free_opnd_error_record_nodes == NULL) | |
4722 | { | |
325801bd | 4723 | record = XNEW (operand_error_record); |
a06ea964 NC |
4724 | } |
4725 | else | |
4726 | { | |
4727 | record = free_opnd_error_record_nodes; | |
4728 | free_opnd_error_record_nodes = record->next; | |
4729 | } | |
4730 | record->opcode = opcode; | |
4731 | /* Insert at the head. */ | |
4732 | record->next = operand_error_report.head; | |
4733 | operand_error_report.head = record; | |
4734 | if (operand_error_report.tail == NULL) | |
4735 | operand_error_report.tail = record; | |
4736 | } | |
4737 | else if (record->detail.kind != AARCH64_OPDE_NIL | |
4738 | && record->detail.index <= new_record->detail.index | |
4739 | && operand_error_higher_severity_p (record->detail.kind, | |
4740 | new_record->detail.kind)) | |
4741 | { | |
4742 | /* In the case of multiple errors found on operands related with a | |
4743 | single opcode, only record the error of the leftmost operand and | |
4744 | only if the error is of higher severity. */ | |
4745 | DEBUG_TRACE ("error %s on operand %d not added to the report due to" | |
4746 | " the existing error %s on operand %d", | |
4747 | operand_mismatch_kind_names[new_record->detail.kind], | |
4748 | new_record->detail.index, | |
4749 | operand_mismatch_kind_names[record->detail.kind], | |
4750 | record->detail.index); | |
4751 | return; | |
4752 | } | |
4753 | ||
4754 | record->detail = new_record->detail; | |
4755 | } | |
4756 | ||
4757 | static inline void | |
4758 | record_operand_error_info (const aarch64_opcode *opcode, | |
4759 | aarch64_operand_error *error_info) | |
4760 | { | |
4761 | operand_error_record record; | |
4762 | record.opcode = opcode; | |
4763 | record.detail = *error_info; | |
4764 | add_operand_error_record (&record); | |
4765 | } | |
4766 | ||
4767 | /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed | |
4768 | error message *ERROR, for operand IDX (count from 0). */ | |
4769 | ||
4770 | static void | |
4771 | record_operand_error (const aarch64_opcode *opcode, int idx, | |
4772 | enum aarch64_operand_error_kind kind, | |
4773 | const char* error) | |
4774 | { | |
4775 | aarch64_operand_error info; | |
4776 | memset(&info, 0, sizeof (info)); | |
4777 | info.index = idx; | |
4778 | info.kind = kind; | |
4779 | info.error = error; | |
2a9b2c1a | 4780 | info.non_fatal = FALSE; |
a06ea964 NC |
4781 | record_operand_error_info (opcode, &info); |
4782 | } | |
4783 | ||
4784 | static void | |
4785 | record_operand_error_with_data (const aarch64_opcode *opcode, int idx, | |
4786 | enum aarch64_operand_error_kind kind, | |
4787 | const char* error, const int *extra_data) | |
4788 | { | |
4789 | aarch64_operand_error info; | |
4790 | info.index = idx; | |
4791 | info.kind = kind; | |
4792 | info.error = error; | |
4793 | info.data[0] = extra_data[0]; | |
4794 | info.data[1] = extra_data[1]; | |
4795 | info.data[2] = extra_data[2]; | |
2a9b2c1a | 4796 | info.non_fatal = FALSE; |
a06ea964 NC |
4797 | record_operand_error_info (opcode, &info); |
4798 | } | |
4799 | ||
4800 | static void | |
4801 | record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx, | |
4802 | const char* error, int lower_bound, | |
4803 | int upper_bound) | |
4804 | { | |
4805 | int data[3] = {lower_bound, upper_bound, 0}; | |
4806 | record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE, | |
4807 | error, data); | |
4808 | } | |
4809 | ||
4810 | /* Remove the operand error record for *OPCODE. */ | |
4811 | static void ATTRIBUTE_UNUSED | |
4812 | remove_operand_error_record (const aarch64_opcode *opcode) | |
4813 | { | |
4814 | if (opcode_has_operand_error_p (opcode)) | |
4815 | { | |
4816 | operand_error_record* record = operand_error_report.head; | |
4817 | gas_assert (record != NULL && operand_error_report.tail != NULL); | |
4818 | operand_error_report.head = record->next; | |
4819 | record->next = free_opnd_error_record_nodes; | |
4820 | free_opnd_error_record_nodes = record; | |
4821 | if (operand_error_report.head == NULL) | |
4822 | { | |
4823 | gas_assert (operand_error_report.tail == record); | |
4824 | operand_error_report.tail = NULL; | |
4825 | } | |
4826 | } | |
4827 | } | |
4828 | ||
4829 | /* Given the instruction in *INSTR, return the index of the best matched | |
4830 | qualifier sequence in the list (an array) headed by QUALIFIERS_LIST. | |
4831 | ||
4832 | Return -1 if there is no qualifier sequence; return the first match | |
4833 | if there is multiple matches found. */ | |
4834 | ||
4835 | static int | |
4836 | find_best_match (const aarch64_inst *instr, | |
4837 | const aarch64_opnd_qualifier_seq_t *qualifiers_list) | |
4838 | { | |
4839 | int i, num_opnds, max_num_matched, idx; | |
4840 | ||
4841 | num_opnds = aarch64_num_of_operands (instr->opcode); | |
4842 | if (num_opnds == 0) | |
4843 | { | |
4844 | DEBUG_TRACE ("no operand"); | |
4845 | return -1; | |
4846 | } | |
4847 | ||
4848 | max_num_matched = 0; | |
4989adac | 4849 | idx = 0; |
a06ea964 NC |
4850 | |
4851 | /* For each pattern. */ | |
4852 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list) | |
4853 | { | |
4854 | int j, num_matched; | |
4855 | const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list; | |
4856 | ||
4857 | /* Most opcodes has much fewer patterns in the list. */ | |
535b785f | 4858 | if (empty_qualifier_sequence_p (qualifiers)) |
a06ea964 NC |
4859 | { |
4860 | DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence"); | |
a06ea964 NC |
4861 | break; |
4862 | } | |
4863 | ||
4864 | for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers) | |
4865 | if (*qualifiers == instr->operands[j].qualifier) | |
4866 | ++num_matched; | |
4867 | ||
4868 | if (num_matched > max_num_matched) | |
4869 | { | |
4870 | max_num_matched = num_matched; | |
4871 | idx = i; | |
4872 | } | |
4873 | } | |
4874 | ||
4875 | DEBUG_TRACE ("return with %d", idx); | |
4876 | return idx; | |
4877 | } | |
4878 | ||
33eaf5de | 4879 | /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the |
a06ea964 NC |
4880 | corresponding operands in *INSTR. */ |
4881 | ||
4882 | static inline void | |
4883 | assign_qualifier_sequence (aarch64_inst *instr, | |
4884 | const aarch64_opnd_qualifier_t *qualifiers) | |
4885 | { | |
4886 | int i = 0; | |
4887 | int num_opnds = aarch64_num_of_operands (instr->opcode); | |
4888 | gas_assert (num_opnds); | |
4889 | for (i = 0; i < num_opnds; ++i, ++qualifiers) | |
4890 | instr->operands[i].qualifier = *qualifiers; | |
4891 | } | |
4892 | ||
4893 | /* Print operands for the diagnosis purpose. */ | |
4894 | ||
4895 | static void | |
4896 | print_operands (char *buf, const aarch64_opcode *opcode, | |
4897 | const aarch64_opnd_info *opnds) | |
4898 | { | |
4899 | int i; | |
4900 | ||
4901 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
4902 | { | |
08d3b0cc | 4903 | char str[128]; |
a06ea964 NC |
4904 | |
4905 | /* We regard the opcode operand info more, however we also look into | |
4906 | the inst->operands to support the disassembling of the optional | |
4907 | operand. | |
4908 | The two operand code should be the same in all cases, apart from | |
4909 | when the operand can be optional. */ | |
4910 | if (opcode->operands[i] == AARCH64_OPND_NIL | |
4911 | || opnds[i].type == AARCH64_OPND_NIL) | |
4912 | break; | |
4913 | ||
4914 | /* Generate the operand string in STR. */ | |
7d02540a | 4915 | aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL, |
38cf07a6 | 4916 | NULL, cpu_variant); |
a06ea964 NC |
4917 | |
4918 | /* Delimiter. */ | |
4919 | if (str[0] != '\0') | |
ad43e107 | 4920 | strcat (buf, i == 0 ? " " : ", "); |
a06ea964 NC |
4921 | |
4922 | /* Append the operand string. */ | |
4923 | strcat (buf, str); | |
4924 | } | |
4925 | } | |
4926 | ||
4927 | /* Send to stderr a string as information. */ | |
4928 | ||
4929 | static void | |
4930 | output_info (const char *format, ...) | |
4931 | { | |
3b4dbbbf | 4932 | const char *file; |
a06ea964 NC |
4933 | unsigned int line; |
4934 | va_list args; | |
4935 | ||
3b4dbbbf | 4936 | file = as_where (&line); |
a06ea964 NC |
4937 | if (file) |
4938 | { | |
4939 | if (line != 0) | |
4940 | fprintf (stderr, "%s:%u: ", file, line); | |
4941 | else | |
4942 | fprintf (stderr, "%s: ", file); | |
4943 | } | |
4944 | fprintf (stderr, _("Info: ")); | |
4945 | va_start (args, format); | |
4946 | vfprintf (stderr, format, args); | |
4947 | va_end (args); | |
4948 | (void) putc ('\n', stderr); | |
4949 | } | |
4950 | ||
4951 | /* Output one operand error record. */ | |
4952 | ||
4953 | static void | |
4954 | output_operand_error_record (const operand_error_record *record, char *str) | |
4955 | { | |
28f013d5 JB |
4956 | const aarch64_operand_error *detail = &record->detail; |
4957 | int idx = detail->index; | |
a06ea964 | 4958 | const aarch64_opcode *opcode = record->opcode; |
28f013d5 | 4959 | enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx] |
a06ea964 | 4960 | : AARCH64_OPND_NIL); |
a06ea964 | 4961 | |
7d02540a TC |
4962 | typedef void (*handler_t)(const char *format, ...); |
4963 | handler_t handler = detail->non_fatal ? as_warn : as_bad; | |
4964 | ||
a06ea964 NC |
4965 | switch (detail->kind) |
4966 | { | |
4967 | case AARCH64_OPDE_NIL: | |
4968 | gas_assert (0); | |
4969 | break; | |
a06ea964 NC |
4970 | case AARCH64_OPDE_SYNTAX_ERROR: |
4971 | case AARCH64_OPDE_RECOVERABLE: | |
4972 | case AARCH64_OPDE_FATAL_SYNTAX_ERROR: | |
4973 | case AARCH64_OPDE_OTHER_ERROR: | |
a06ea964 NC |
4974 | /* Use the prepared error message if there is, otherwise use the |
4975 | operand description string to describe the error. */ | |
4976 | if (detail->error != NULL) | |
4977 | { | |
28f013d5 | 4978 | if (idx < 0) |
7d02540a | 4979 | handler (_("%s -- `%s'"), detail->error, str); |
a06ea964 | 4980 | else |
7d02540a TC |
4981 | handler (_("%s at operand %d -- `%s'"), |
4982 | detail->error, idx + 1, str); | |
a06ea964 NC |
4983 | } |
4984 | else | |
28f013d5 JB |
4985 | { |
4986 | gas_assert (idx >= 0); | |
7d02540a TC |
4987 | handler (_("operand %d must be %s -- `%s'"), idx + 1, |
4988 | aarch64_get_operand_desc (opd_code), str); | |
28f013d5 | 4989 | } |
a06ea964 NC |
4990 | break; |
4991 | ||
4992 | case AARCH64_OPDE_INVALID_VARIANT: | |
7d02540a | 4993 | handler (_("operand mismatch -- `%s'"), str); |
a06ea964 NC |
4994 | if (verbose_error_p) |
4995 | { | |
4996 | /* We will try to correct the erroneous instruction and also provide | |
4997 | more information e.g. all other valid variants. | |
4998 | ||
4999 | The string representation of the corrected instruction and other | |
5000 | valid variants are generated by | |
5001 | ||
5002 | 1) obtaining the intermediate representation of the erroneous | |
5003 | instruction; | |
5004 | 2) manipulating the IR, e.g. replacing the operand qualifier; | |
5005 | 3) printing out the instruction by calling the printer functions | |
5006 | shared with the disassembler. | |
5007 | ||
5008 | The limitation of this method is that the exact input assembly | |
5009 | line cannot be accurately reproduced in some cases, for example an | |
5010 | optional operand present in the actual assembly line will be | |
5011 | omitted in the output; likewise for the optional syntax rules, | |
5012 | e.g. the # before the immediate. Another limitation is that the | |
5013 | assembly symbols and relocation operations in the assembly line | |
5014 | currently cannot be printed out in the error report. Last but not | |
5015 | least, when there is other error(s) co-exist with this error, the | |
5016 | 'corrected' instruction may be still incorrect, e.g. given | |
5017 | 'ldnp h0,h1,[x0,#6]!' | |
5018 | this diagnosis will provide the version: | |
5019 | 'ldnp s0,s1,[x0,#6]!' | |
5020 | which is still not right. */ | |
5021 | size_t len = strlen (get_mnemonic_name (str)); | |
5022 | int i, qlf_idx; | |
5023 | bfd_boolean result; | |
08d3b0cc | 5024 | char buf[2048]; |
a06ea964 NC |
5025 | aarch64_inst *inst_base = &inst.base; |
5026 | const aarch64_opnd_qualifier_seq_t *qualifiers_list; | |
5027 | ||
5028 | /* Init inst. */ | |
5029 | reset_aarch64_instruction (&inst); | |
5030 | inst_base->opcode = opcode; | |
5031 | ||
5032 | /* Reset the error report so that there is no side effect on the | |
5033 | following operand parsing. */ | |
5034 | init_operand_error_report (); | |
5035 | ||
5036 | /* Fill inst. */ | |
5037 | result = parse_operands (str + len, opcode) | |
5038 | && programmer_friendly_fixup (&inst); | |
5039 | gas_assert (result); | |
3979cf50 SP |
5040 | result = aarch64_opcode_encode (cpu_variant, opcode, inst_base, |
5041 | &inst_base->value, NULL, NULL, | |
5042 | insn_sequence); | |
a06ea964 NC |
5043 | gas_assert (!result); |
5044 | ||
5045 | /* Find the most matched qualifier sequence. */ | |
5046 | qlf_idx = find_best_match (inst_base, opcode->qualifiers_list); | |
5047 | gas_assert (qlf_idx > -1); | |
5048 | ||
5049 | /* Assign the qualifiers. */ | |
5050 | assign_qualifier_sequence (inst_base, | |
5051 | opcode->qualifiers_list[qlf_idx]); | |
5052 | ||
5053 | /* Print the hint. */ | |
5054 | output_info (_(" did you mean this?")); | |
08d3b0cc | 5055 | snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str)); |
a06ea964 NC |
5056 | print_operands (buf, opcode, inst_base->operands); |
5057 | output_info (_(" %s"), buf); | |
5058 | ||
5059 | /* Print out other variant(s) if there is any. */ | |
5060 | if (qlf_idx != 0 || | |
5061 | !empty_qualifier_sequence_p (opcode->qualifiers_list[1])) | |
5062 | output_info (_(" other valid variant(s):")); | |
5063 | ||
5064 | /* For each pattern. */ | |
5065 | qualifiers_list = opcode->qualifiers_list; | |
5066 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list) | |
5067 | { | |
5068 | /* Most opcodes has much fewer patterns in the list. | |
5069 | First NIL qualifier indicates the end in the list. */ | |
535b785f | 5070 | if (empty_qualifier_sequence_p (*qualifiers_list)) |
a06ea964 NC |
5071 | break; |
5072 | ||
5073 | if (i != qlf_idx) | |
5074 | { | |
5075 | /* Mnemonics name. */ | |
08d3b0cc | 5076 | snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str)); |
a06ea964 NC |
5077 | |
5078 | /* Assign the qualifiers. */ | |
5079 | assign_qualifier_sequence (inst_base, *qualifiers_list); | |
5080 | ||
5081 | /* Print instruction. */ | |
5082 | print_operands (buf, opcode, inst_base->operands); | |
5083 | ||
5084 | output_info (_(" %s"), buf); | |
5085 | } | |
5086 | } | |
5087 | } | |
5088 | break; | |
5089 | ||
0c608d6b | 5090 | case AARCH64_OPDE_UNTIED_OPERAND: |
7d02540a TC |
5091 | handler (_("operand %d must be the same register as operand 1 -- `%s'"), |
5092 | detail->index + 1, str); | |
0c608d6b RS |
5093 | break; |
5094 | ||
a06ea964 | 5095 | case AARCH64_OPDE_OUT_OF_RANGE: |
f5555712 | 5096 | if (detail->data[0] != detail->data[1]) |
7d02540a TC |
5097 | handler (_("%s out of range %d to %d at operand %d -- `%s'"), |
5098 | detail->error ? detail->error : _("immediate value"), | |
5099 | detail->data[0], detail->data[1], idx + 1, str); | |
f5555712 | 5100 | else |
7d02540a TC |
5101 | handler (_("%s must be %d at operand %d -- `%s'"), |
5102 | detail->error ? detail->error : _("immediate value"), | |
5103 | detail->data[0], idx + 1, str); | |
a06ea964 NC |
5104 | break; |
5105 | ||
5106 | case AARCH64_OPDE_REG_LIST: | |
5107 | if (detail->data[0] == 1) | |
7d02540a TC |
5108 | handler (_("invalid number of registers in the list; " |
5109 | "only 1 register is expected at operand %d -- `%s'"), | |
5110 | idx + 1, str); | |
a06ea964 | 5111 | else |
7d02540a TC |
5112 | handler (_("invalid number of registers in the list; " |
5113 | "%d registers are expected at operand %d -- `%s'"), | |
5114 | detail->data[0], idx + 1, str); | |
a06ea964 NC |
5115 | break; |
5116 | ||
5117 | case AARCH64_OPDE_UNALIGNED: | |
7d02540a TC |
5118 | handler (_("immediate value must be a multiple of " |
5119 | "%d at operand %d -- `%s'"), | |
5120 | detail->data[0], idx + 1, str); | |
a06ea964 NC |
5121 | break; |
5122 | ||
5123 | default: | |
5124 | gas_assert (0); | |
5125 | break; | |
5126 | } | |
5127 | } | |
5128 | ||
5129 | /* Process and output the error message about the operand mismatching. | |
5130 | ||
5131 | When this function is called, the operand error information had | |
5132 | been collected for an assembly line and there will be multiple | |
33eaf5de | 5133 | errors in the case of multiple instruction templates; output the |
7d02540a TC |
5134 | error message that most closely describes the problem. |
5135 | ||
5136 | The errors to be printed can be filtered on printing all errors | |
5137 | or only non-fatal errors. This distinction has to be made because | |
5138 | the error buffer may already be filled with fatal errors we don't want to | |
5139 | print due to the different instruction templates. */ | |
a06ea964 NC |
5140 | |
5141 | static void | |
7d02540a | 5142 | output_operand_error_report (char *str, bfd_boolean non_fatal_only) |
a06ea964 | 5143 | { |
261dde89 SP |
5144 | int largest_error_pos, largest_error_pos2; |
5145 | const char *msg = NULL, *msg2 = NULL; | |
a06ea964 NC |
5146 | enum aarch64_operand_error_kind kind; |
5147 | operand_error_record *curr; | |
5148 | operand_error_record *head = operand_error_report.head; | |
261dde89 | 5149 | operand_error_record *record = NULL, *record2 = NULL; |
a06ea964 NC |
5150 | |
5151 | /* No error to report. */ | |
5152 | if (head == NULL) | |
5153 | return; | |
5154 | ||
5155 | gas_assert (head != NULL && operand_error_report.tail != NULL); | |
5156 | ||
5157 | /* Only one error. */ | |
5158 | if (head == operand_error_report.tail) | |
5159 | { | |
7d02540a TC |
5160 | /* If the only error is a non-fatal one and we don't want to print it, |
5161 | just exit. */ | |
5162 | if (!non_fatal_only || head->detail.non_fatal) | |
5163 | { | |
5164 | DEBUG_TRACE ("single opcode entry with error kind: %s", | |
5165 | operand_mismatch_kind_names[head->detail.kind]); | |
5166 | output_operand_error_record (head, str); | |
5167 | } | |
a06ea964 NC |
5168 | return; |
5169 | } | |
5170 | ||
5171 | /* Find the error kind of the highest severity. */ | |
33eaf5de | 5172 | DEBUG_TRACE ("multiple opcode entries with error kind"); |
a06ea964 NC |
5173 | kind = AARCH64_OPDE_NIL; |
5174 | for (curr = head; curr != NULL; curr = curr->next) | |
5175 | { | |
5176 | gas_assert (curr->detail.kind != AARCH64_OPDE_NIL); | |
5177 | DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]); | |
a68f4cd2 TC |
5178 | if (operand_error_higher_severity_p (curr->detail.kind, kind) |
5179 | && (!non_fatal_only || (non_fatal_only && curr->detail.non_fatal))) | |
a06ea964 NC |
5180 | kind = curr->detail.kind; |
5181 | } | |
a68f4cd2 TC |
5182 | |
5183 | gas_assert (kind != AARCH64_OPDE_NIL || non_fatal_only); | |
a06ea964 NC |
5184 | |
5185 | /* Pick up one of errors of KIND to report. */ | |
5186 | largest_error_pos = -2; /* Index can be -1 which means unknown index. */ | |
261dde89 | 5187 | largest_error_pos2 = -2; /* Index can be -1 which means unknown index. */ |
a06ea964 NC |
5188 | for (curr = head; curr != NULL; curr = curr->next) |
5189 | { | |
7d02540a TC |
5190 | /* If we don't want to print non-fatal errors then don't consider them |
5191 | at all. */ | |
5192 | if (curr->detail.kind != kind | |
af81c43b | 5193 | || (non_fatal_only && !curr->detail.non_fatal)) |
a06ea964 NC |
5194 | continue; |
5195 | /* If there are multiple errors, pick up the one with the highest | |
5196 | mismatching operand index. In the case of multiple errors with | |
5197 | the equally highest operand index, pick up the first one or the | |
5198 | first one with non-NULL error message. */ | |
261dde89 | 5199 | if (AARCH64_CPU_HAS_FEATURE (cpu_variant, *curr->opcode->avariant)) |
a06ea964 | 5200 | { |
261dde89 SP |
5201 | if (curr->detail.index > largest_error_pos |
5202 | || (curr->detail.index == largest_error_pos && msg == NULL | |
5203 | && curr->detail.error != NULL)) | |
5204 | { | |
5205 | largest_error_pos = curr->detail.index; | |
5206 | record = curr; | |
5207 | msg = record->detail.error; | |
5208 | } | |
5209 | } | |
5210 | else | |
5211 | { | |
5212 | if (curr->detail.index > largest_error_pos2 | |
5213 | || (curr->detail.index == largest_error_pos2 && msg2 == NULL | |
5214 | && curr->detail.error != NULL)) | |
5215 | { | |
5216 | largest_error_pos2 = curr->detail.index; | |
5217 | record2 = curr; | |
5218 | msg2 = record2->detail.error; | |
5219 | } | |
a06ea964 NC |
5220 | } |
5221 | } | |
5222 | ||
261dde89 SP |
5223 | /* No errors in enabled cpu feature variants, look for errors in the disabled |
5224 | ones. XXX we should do this segregation when prioritizing too. */ | |
5225 | if (!record) | |
5226 | { | |
5227 | largest_error_pos = largest_error_pos2; | |
5228 | record = record2; | |
5229 | msg = msg2; | |
5230 | } | |
5231 | ||
7d02540a TC |
5232 | /* The way errors are collected in the back-end is a bit non-intuitive. But |
5233 | essentially, because each operand template is tried recursively you may | |
5234 | always have errors collected from the previous tried OPND. These are | |
5235 | usually skipped if there is one successful match. However now with the | |
5236 | non-fatal errors we have to ignore those previously collected hard errors | |
5237 | when we're only interested in printing the non-fatal ones. This condition | |
5238 | prevents us from printing errors that are not appropriate, since we did | |
5239 | match a condition, but it also has warnings that it wants to print. */ | |
5240 | if (non_fatal_only && !record) | |
5241 | return; | |
5242 | ||
a06ea964 NC |
5243 | gas_assert (largest_error_pos != -2 && record != NULL); |
5244 | DEBUG_TRACE ("Pick up error kind %s to report", | |
5245 | operand_mismatch_kind_names[record->detail.kind]); | |
5246 | ||
5247 | /* Output. */ | |
5248 | output_operand_error_record (record, str); | |
5249 | } | |
5250 | \f | |
5251 | /* Write an AARCH64 instruction to buf - always little-endian. */ | |
5252 | static void | |
5253 | put_aarch64_insn (char *buf, uint32_t insn) | |
5254 | { | |
5255 | unsigned char *where = (unsigned char *) buf; | |
5256 | where[0] = insn; | |
5257 | where[1] = insn >> 8; | |
5258 | where[2] = insn >> 16; | |
5259 | where[3] = insn >> 24; | |
5260 | } | |
5261 | ||
5262 | static uint32_t | |
5263 | get_aarch64_insn (char *buf) | |
5264 | { | |
5265 | unsigned char *where = (unsigned char *) buf; | |
5266 | uint32_t result; | |
4f7cc141 AM |
5267 | result = ((where[0] | (where[1] << 8) | (where[2] << 16) |
5268 | | ((uint32_t) where[3] << 24))); | |
a06ea964 NC |
5269 | return result; |
5270 | } | |
5271 | ||
5272 | static void | |
5273 | output_inst (struct aarch64_inst *new_inst) | |
5274 | { | |
5275 | char *to = NULL; | |
5276 | ||
5277 | to = frag_more (INSN_SIZE); | |
5278 | ||
5279 | frag_now->tc_frag_data.recorded = 1; | |
5280 | ||
5281 | put_aarch64_insn (to, inst.base.value); | |
5282 | ||
5283 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5284 | { | |
5285 | fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal, | |
5286 | INSN_SIZE, &inst.reloc.exp, | |
5287 | inst.reloc.pc_rel, | |
5288 | inst.reloc.type); | |
5289 | DEBUG_TRACE ("Prepared relocation fix up"); | |
5290 | /* Don't check the addend value against the instruction size, | |
5291 | that's the job of our code in md_apply_fix(). */ | |
5292 | fixp->fx_no_overflow = 1; | |
5293 | if (new_inst != NULL) | |
5294 | fixp->tc_fix_data.inst = new_inst; | |
5295 | if (aarch64_gas_internal_fixup_p ()) | |
5296 | { | |
5297 | gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL); | |
5298 | fixp->tc_fix_data.opnd = inst.reloc.opnd; | |
5299 | fixp->fx_addnumber = inst.reloc.flags; | |
5300 | } | |
f0070c1e SP |
5301 | if (inst.reloc.flags & FIXUP_F_C64) |
5302 | fixp->tc_fix_data.c64 = TRUE; | |
a06ea964 NC |
5303 | } |
5304 | ||
5305 | dwarf2_emit_insn (INSN_SIZE); | |
5306 | } | |
5307 | ||
5308 | /* Link together opcodes of the same name. */ | |
5309 | ||
5310 | struct templates | |
5311 | { | |
5312 | aarch64_opcode *opcode; | |
5313 | struct templates *next; | |
5314 | }; | |
5315 | ||
5316 | typedef struct templates templates; | |
5317 | ||
5318 | static templates * | |
5319 | lookup_mnemonic (const char *start, int len) | |
5320 | { | |
5321 | templates *templ = NULL; | |
5322 | ||
629310ab | 5323 | templ = str_hash_find_n (aarch64_ops_hsh, start, len); |
a06ea964 NC |
5324 | return templ; |
5325 | } | |
5326 | ||
5327 | /* Subroutine of md_assemble, responsible for looking up the primary | |
5328 | opcode from the mnemonic the user wrote. STR points to the | |
5329 | beginning of the mnemonic. */ | |
5330 | ||
5331 | static templates * | |
5332 | opcode_lookup (char **str) | |
5333 | { | |
bb7eff52 | 5334 | char *end, *base, *dot; |
a06ea964 NC |
5335 | const aarch64_cond *cond; |
5336 | char condname[16]; | |
5337 | int len; | |
5338 | ||
5339 | /* Scan up to the end of the mnemonic, which must end in white space, | |
5340 | '.', or end of string. */ | |
bb7eff52 | 5341 | dot = 0; |
a06ea964 | 5342 | for (base = end = *str; is_part_of_name(*end); end++) |
bb7eff52 RS |
5343 | if (*end == '.' && !dot) |
5344 | dot = end; | |
a06ea964 | 5345 | |
bb7eff52 | 5346 | if (end == base || dot == base) |
a06ea964 NC |
5347 | return 0; |
5348 | ||
5349 | inst.cond = COND_ALWAYS; | |
5350 | ||
5351 | /* Handle a possible condition. */ | |
bb7eff52 | 5352 | if (dot) |
a06ea964 | 5353 | { |
629310ab | 5354 | cond = str_hash_find_n (aarch64_cond_hsh, dot + 1, end - dot - 1); |
a06ea964 NC |
5355 | if (cond) |
5356 | { | |
5357 | inst.cond = cond->value; | |
bb7eff52 | 5358 | *str = end; |
a06ea964 NC |
5359 | } |
5360 | else | |
5361 | { | |
bb7eff52 | 5362 | *str = dot; |
a06ea964 NC |
5363 | return 0; |
5364 | } | |
bb7eff52 | 5365 | len = dot - base; |
a06ea964 NC |
5366 | } |
5367 | else | |
bb7eff52 RS |
5368 | { |
5369 | *str = end; | |
5370 | len = end - base; | |
5371 | } | |
a06ea964 NC |
5372 | |
5373 | if (inst.cond == COND_ALWAYS) | |
5374 | { | |
5375 | /* Look for unaffixed mnemonic. */ | |
5376 | return lookup_mnemonic (base, len); | |
5377 | } | |
5378 | else if (len <= 13) | |
5379 | { | |
5380 | /* append ".c" to mnemonic if conditional */ | |
5381 | memcpy (condname, base, len); | |
5382 | memcpy (condname + len, ".c", 2); | |
5383 | base = condname; | |
5384 | len += 2; | |
5385 | return lookup_mnemonic (base, len); | |
5386 | } | |
5387 | ||
5388 | return NULL; | |
5389 | } | |
5390 | ||
8f9a77af RS |
5391 | /* Internal helper routine converting a vector_type_el structure *VECTYPE |
5392 | to a corresponding operand qualifier. */ | |
a06ea964 NC |
5393 | |
5394 | static inline aarch64_opnd_qualifier_t | |
8f9a77af | 5395 | vectype_to_qualifier (const struct vector_type_el *vectype) |
a06ea964 | 5396 | { |
f06935a5 | 5397 | /* Element size in bytes indexed by vector_el_type. */ |
a06ea964 NC |
5398 | const unsigned char ele_size[5] |
5399 | = {1, 2, 4, 8, 16}; | |
65f2205d MW |
5400 | const unsigned int ele_base [5] = |
5401 | { | |
a3b3345a | 5402 | AARCH64_OPND_QLF_V_4B, |
3067d3b9 | 5403 | AARCH64_OPND_QLF_V_2H, |
65f2205d MW |
5404 | AARCH64_OPND_QLF_V_2S, |
5405 | AARCH64_OPND_QLF_V_1D, | |
5406 | AARCH64_OPND_QLF_V_1Q | |
5407 | }; | |
a06ea964 NC |
5408 | |
5409 | if (!vectype->defined || vectype->type == NT_invtype) | |
5410 | goto vectype_conversion_fail; | |
5411 | ||
d50c751e RS |
5412 | if (vectype->type == NT_zero) |
5413 | return AARCH64_OPND_QLF_P_Z; | |
5414 | if (vectype->type == NT_merge) | |
5415 | return AARCH64_OPND_QLF_P_M; | |
5416 | ||
a06ea964 NC |
5417 | gas_assert (vectype->type >= NT_b && vectype->type <= NT_q); |
5418 | ||
f11ad6bc | 5419 | if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH)) |
00c2093f TC |
5420 | { |
5421 | /* Special case S_4B. */ | |
5422 | if (vectype->type == NT_b && vectype->width == 4) | |
5423 | return AARCH64_OPND_QLF_S_4B; | |
5424 | ||
df678013 MM |
5425 | /* Special case S_2H. */ |
5426 | if (vectype->type == NT_h && vectype->width == 2) | |
5427 | return AARCH64_OPND_QLF_S_2H; | |
5428 | ||
00c2093f TC |
5429 | /* Vector element register. */ |
5430 | return AARCH64_OPND_QLF_S_B + vectype->type; | |
5431 | } | |
a06ea964 NC |
5432 | else |
5433 | { | |
5434 | /* Vector register. */ | |
5435 | int reg_size = ele_size[vectype->type] * vectype->width; | |
5436 | unsigned offset; | |
65f2205d | 5437 | unsigned shift; |
3067d3b9 | 5438 | if (reg_size != 16 && reg_size != 8 && reg_size != 4) |
a06ea964 | 5439 | goto vectype_conversion_fail; |
65f2205d MW |
5440 | |
5441 | /* The conversion is by calculating the offset from the base operand | |
5442 | qualifier for the vector type. The operand qualifiers are regular | |
5443 | enough that the offset can established by shifting the vector width by | |
5444 | a vector-type dependent amount. */ | |
5445 | shift = 0; | |
5446 | if (vectype->type == NT_b) | |
a3b3345a | 5447 | shift = 3; |
3067d3b9 | 5448 | else if (vectype->type == NT_h || vectype->type == NT_s) |
65f2205d MW |
5449 | shift = 2; |
5450 | else if (vectype->type >= NT_d) | |
5451 | shift = 1; | |
5452 | else | |
5453 | gas_assert (0); | |
5454 | ||
5455 | offset = ele_base [vectype->type] + (vectype->width >> shift); | |
a3b3345a | 5456 | gas_assert (AARCH64_OPND_QLF_V_4B <= offset |
65f2205d MW |
5457 | && offset <= AARCH64_OPND_QLF_V_1Q); |
5458 | return offset; | |
a06ea964 NC |
5459 | } |
5460 | ||
dc1e8a47 | 5461 | vectype_conversion_fail: |
a06ea964 NC |
5462 | first_error (_("bad vector arrangement type")); |
5463 | return AARCH64_OPND_QLF_NIL; | |
5464 | } | |
5465 | ||
5466 | /* Process an optional operand that is found omitted from the assembly line. | |
5467 | Fill *OPERAND for such an operand of type TYPE. OPCODE points to the | |
5468 | instruction's opcode entry while IDX is the index of this omitted operand. | |
5469 | */ | |
5470 | ||
5471 | static void | |
5472 | process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, | |
5473 | int idx, aarch64_opnd_info *operand) | |
5474 | { | |
5475 | aarch64_insn default_value = get_optional_operand_default_value (opcode); | |
5476 | gas_assert (optional_operand_p (opcode, idx)); | |
5477 | gas_assert (!operand->present); | |
5478 | ||
5479 | switch (type) | |
5480 | { | |
adffaa8e | 5481 | case AARCH64_OPND_Can: |
bbb36683 | 5482 | case AARCH64_OPND_Cat_SYS: |
a06ea964 NC |
5483 | case AARCH64_OPND_Rd: |
5484 | case AARCH64_OPND_Rn: | |
5485 | case AARCH64_OPND_Rm: | |
5486 | case AARCH64_OPND_Rt: | |
5487 | case AARCH64_OPND_Rt2: | |
bd7ceb8d | 5488 | case AARCH64_OPND_Rt_SP: |
a06ea964 NC |
5489 | case AARCH64_OPND_Rs: |
5490 | case AARCH64_OPND_Ra: | |
5491 | case AARCH64_OPND_Rt_SYS: | |
5492 | case AARCH64_OPND_Rd_SP: | |
5493 | case AARCH64_OPND_Rn_SP: | |
c84364ec | 5494 | case AARCH64_OPND_Rm_SP: |
a06ea964 NC |
5495 | case AARCH64_OPND_Fd: |
5496 | case AARCH64_OPND_Fn: | |
5497 | case AARCH64_OPND_Fm: | |
5498 | case AARCH64_OPND_Fa: | |
5499 | case AARCH64_OPND_Ft: | |
5500 | case AARCH64_OPND_Ft2: | |
5501 | case AARCH64_OPND_Sd: | |
5502 | case AARCH64_OPND_Sn: | |
5503 | case AARCH64_OPND_Sm: | |
f42f1a1d | 5504 | case AARCH64_OPND_Va: |
a06ea964 NC |
5505 | case AARCH64_OPND_Vd: |
5506 | case AARCH64_OPND_Vn: | |
5507 | case AARCH64_OPND_Vm: | |
5508 | case AARCH64_OPND_VdD1: | |
5509 | case AARCH64_OPND_VnD1: | |
5510 | operand->reg.regno = default_value; | |
5511 | break; | |
5512 | ||
5513 | case AARCH64_OPND_Ed: | |
5514 | case AARCH64_OPND_En: | |
5515 | case AARCH64_OPND_Em: | |
369c9167 | 5516 | case AARCH64_OPND_Em16: |
f42f1a1d | 5517 | case AARCH64_OPND_SM3_IMM2: |
a06ea964 NC |
5518 | operand->reglane.regno = default_value; |
5519 | break; | |
5520 | ||
5521 | case AARCH64_OPND_IDX: | |
5522 | case AARCH64_OPND_BIT_NUM: | |
5523 | case AARCH64_OPND_IMMR: | |
5524 | case AARCH64_OPND_IMMS: | |
5525 | case AARCH64_OPND_SHLL_IMM: | |
5526 | case AARCH64_OPND_IMM_VLSL: | |
5527 | case AARCH64_OPND_IMM_VLSR: | |
5528 | case AARCH64_OPND_CCMP_IMM: | |
5529 | case AARCH64_OPND_FBITS: | |
5530 | case AARCH64_OPND_UIMM4: | |
5531 | case AARCH64_OPND_UIMM3_OP1: | |
5532 | case AARCH64_OPND_UIMM3_OP2: | |
5533 | case AARCH64_OPND_IMM: | |
f42f1a1d | 5534 | case AARCH64_OPND_IMM_2: |
a06ea964 NC |
5535 | case AARCH64_OPND_WIDTH: |
5536 | case AARCH64_OPND_UIMM7: | |
5537 | case AARCH64_OPND_NZCV: | |
245d2e3f RS |
5538 | case AARCH64_OPND_SVE_PATTERN: |
5539 | case AARCH64_OPND_SVE_PRFOP: | |
a06ea964 NC |
5540 | operand->imm.value = default_value; |
5541 | break; | |
5542 | ||
2442d846 RS |
5543 | case AARCH64_OPND_SVE_PATTERN_SCALED: |
5544 | operand->imm.value = default_value; | |
5545 | operand->shifter.kind = AARCH64_MOD_MUL; | |
5546 | operand->shifter.amount = 1; | |
5547 | break; | |
5548 | ||
a06ea964 NC |
5549 | case AARCH64_OPND_EXCEPTION: |
5550 | inst.reloc.type = BFD_RELOC_UNUSED; | |
5551 | break; | |
5552 | ||
5553 | case AARCH64_OPND_BARRIER_ISB: | |
5554 | operand->barrier = aarch64_barrier_options + default_value; | |
ff605452 SD |
5555 | break; |
5556 | ||
5557 | case AARCH64_OPND_BTI_TARGET: | |
5558 | operand->hint_option = aarch64_hint_options + default_value; | |
5559 | break; | |
a06ea964 NC |
5560 | |
5561 | default: | |
5562 | break; | |
5563 | } | |
5564 | } | |
5565 | ||
5566 | /* Process the relocation type for move wide instructions. | |
5567 | Return TRUE on success; otherwise return FALSE. */ | |
5568 | ||
5569 | static bfd_boolean | |
5570 | process_movw_reloc_info (void) | |
5571 | { | |
5572 | int is32; | |
5573 | unsigned shift; | |
5574 | ||
5575 | is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0; | |
5576 | ||
5577 | if (inst.base.opcode->op == OP_MOVK) | |
5578 | switch (inst.reloc.type) | |
5579 | { | |
5580 | case BFD_RELOC_AARCH64_MOVW_G0_S: | |
5581 | case BFD_RELOC_AARCH64_MOVW_G1_S: | |
5582 | case BFD_RELOC_AARCH64_MOVW_G2_S: | |
32247401 RL |
5583 | case BFD_RELOC_AARCH64_MOVW_PREL_G0: |
5584 | case BFD_RELOC_AARCH64_MOVW_PREL_G1: | |
5585 | case BFD_RELOC_AARCH64_MOVW_PREL_G2: | |
5586 | case BFD_RELOC_AARCH64_MOVW_PREL_G3: | |
1aa66fb1 | 5587 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
a06ea964 | 5588 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
a06ea964 | 5589 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: |
a06ea964 NC |
5590 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: |
5591 | set_syntax_error | |
5592 | (_("the specified relocation type is not allowed for MOVK")); | |
5593 | return FALSE; | |
5594 | default: | |
5595 | break; | |
5596 | } | |
5597 | ||
5598 | switch (inst.reloc.type) | |
5599 | { | |
5600 | case BFD_RELOC_AARCH64_MOVW_G0: | |
a06ea964 | 5601 | case BFD_RELOC_AARCH64_MOVW_G0_NC: |
f09c556a | 5602 | case BFD_RELOC_AARCH64_MOVW_G0_S: |
ca632371 | 5603 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC: |
32247401 RL |
5604 | case BFD_RELOC_AARCH64_MOVW_PREL_G0: |
5605 | case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC: | |
43a357f9 | 5606 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: |
3e8286c0 | 5607 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: |
3b957e5b | 5608 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: |
49df5539 JW |
5609 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0: |
5610 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: | |
a06ea964 NC |
5611 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
5612 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: | |
5613 | shift = 0; | |
5614 | break; | |
5615 | case BFD_RELOC_AARCH64_MOVW_G1: | |
a06ea964 | 5616 | case BFD_RELOC_AARCH64_MOVW_G1_NC: |
f09c556a | 5617 | case BFD_RELOC_AARCH64_MOVW_G1_S: |
654248e7 | 5618 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: |
32247401 RL |
5619 | case BFD_RELOC_AARCH64_MOVW_PREL_G1: |
5620 | case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC: | |
43a357f9 | 5621 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: |
1aa66fb1 | 5622 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
3b957e5b | 5623 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1: |
49df5539 JW |
5624 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1: |
5625 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: | |
a06ea964 NC |
5626 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: |
5627 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: | |
5628 | shift = 16; | |
5629 | break; | |
5630 | case BFD_RELOC_AARCH64_MOVW_G2: | |
a06ea964 | 5631 | case BFD_RELOC_AARCH64_MOVW_G2_NC: |
f09c556a | 5632 | case BFD_RELOC_AARCH64_MOVW_G2_S: |
32247401 RL |
5633 | case BFD_RELOC_AARCH64_MOVW_PREL_G2: |
5634 | case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC: | |
49df5539 | 5635 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2: |
a06ea964 NC |
5636 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: |
5637 | if (is32) | |
5638 | { | |
5639 | set_fatal_syntax_error | |
5640 | (_("the specified relocation type is not allowed for 32-bit " | |
5641 | "register")); | |
5642 | return FALSE; | |
5643 | } | |
5644 | shift = 32; | |
5645 | break; | |
5646 | case BFD_RELOC_AARCH64_MOVW_G3: | |
32247401 | 5647 | case BFD_RELOC_AARCH64_MOVW_PREL_G3: |
a06ea964 NC |
5648 | if (is32) |
5649 | { | |
5650 | set_fatal_syntax_error | |
5651 | (_("the specified relocation type is not allowed for 32-bit " | |
5652 | "register")); | |
5653 | return FALSE; | |
5654 | } | |
5655 | shift = 48; | |
5656 | break; | |
5657 | default: | |
5658 | /* More cases should be added when more MOVW-related relocation types | |
5659 | are supported in GAS. */ | |
5660 | gas_assert (aarch64_gas_internal_fixup_p ()); | |
5661 | /* The shift amount should have already been set by the parser. */ | |
5662 | return TRUE; | |
5663 | } | |
5664 | inst.base.operands[1].shifter.amount = shift; | |
5665 | return TRUE; | |
5666 | } | |
5667 | ||
33eaf5de | 5668 | /* A primitive log calculator. */ |
a06ea964 NC |
5669 | |
5670 | static inline unsigned int | |
5671 | get_logsz (unsigned int size) | |
5672 | { | |
5673 | const unsigned char ls[16] = | |
5674 | {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4}; | |
5675 | if (size > 16) | |
5676 | { | |
5677 | gas_assert (0); | |
5678 | return -1; | |
5679 | } | |
5680 | gas_assert (ls[size - 1] != (unsigned char)-1); | |
5681 | return ls[size - 1]; | |
5682 | } | |
5683 | ||
5684 | /* Determine and return the real reloc type code for an instruction | |
5685 | with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */ | |
5686 | ||
5687 | static inline bfd_reloc_code_real_type | |
5688 | ldst_lo12_determine_real_reloc_type (void) | |
5689 | { | |
4c562523 | 5690 | unsigned logsz; |
a06ea964 NC |
5691 | enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier; |
5692 | enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier; | |
5693 | ||
84f1b9fb | 5694 | const bfd_reloc_code_real_type reloc_ldst_lo12[5][5] = { |
4c562523 JW |
5695 | { |
5696 | BFD_RELOC_AARCH64_LDST8_LO12, | |
5697 | BFD_RELOC_AARCH64_LDST16_LO12, | |
5698 | BFD_RELOC_AARCH64_LDST32_LO12, | |
5699 | BFD_RELOC_AARCH64_LDST64_LO12, | |
a06ea964 | 5700 | BFD_RELOC_AARCH64_LDST128_LO12 |
4c562523 JW |
5701 | }, |
5702 | { | |
5703 | BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, | |
5704 | BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, | |
5705 | BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, | |
5706 | BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, | |
5707 | BFD_RELOC_AARCH64_NONE | |
5708 | }, | |
5709 | { | |
5710 | BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC, | |
5711 | BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, | |
5712 | BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, | |
5713 | BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC, | |
5714 | BFD_RELOC_AARCH64_NONE | |
84f1b9fb RL |
5715 | }, |
5716 | { | |
5717 | BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, | |
5718 | BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, | |
5719 | BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, | |
5720 | BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, | |
5721 | BFD_RELOC_AARCH64_NONE | |
5722 | }, | |
5723 | { | |
5724 | BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC, | |
5725 | BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC, | |
5726 | BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC, | |
5727 | BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC, | |
5728 | BFD_RELOC_AARCH64_NONE | |
4c562523 | 5729 | } |
a06ea964 NC |
5730 | }; |
5731 | ||
4c562523 JW |
5732 | gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12 |
5733 | || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 | |
5734 | || (inst.reloc.type | |
84f1b9fb RL |
5735 | == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC) |
5736 | || (inst.reloc.type | |
5737 | == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12) | |
5738 | || (inst.reloc.type | |
5739 | == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC)); | |
d2beed31 SP |
5740 | gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12 |
5741 | || inst.base.opcode->operands[1] == AARCH64_OPND_CAPADDR_UIMM9); | |
a06ea964 NC |
5742 | |
5743 | if (opd1_qlf == AARCH64_OPND_QLF_NIL) | |
5744 | opd1_qlf = | |
5745 | aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list, | |
5746 | 1, opd0_qlf, 0); | |
5747 | gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL); | |
5748 | ||
5749 | logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf)); | |
4c562523 | 5750 | if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 |
84f1b9fb RL |
5751 | || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC |
5752 | || inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12 | |
5753 | || inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC) | |
4c562523 JW |
5754 | gas_assert (logsz <= 3); |
5755 | else | |
5756 | gas_assert (logsz <= 4); | |
a06ea964 | 5757 | |
4c562523 | 5758 | /* In reloc.c, these pseudo relocation types should be defined in similar |
33eaf5de | 5759 | order as above reloc_ldst_lo12 array. Because the array index calculation |
4c562523 JW |
5760 | below relies on this. */ |
5761 | return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz]; | |
a06ea964 NC |
5762 | } |
5763 | ||
5764 | /* Check whether a register list REGINFO is valid. The registers must be | |
5765 | numbered in increasing order (modulo 32), in increments of one or two. | |
5766 | ||
5767 | If ACCEPT_ALTERNATE is non-zero, the register numbers should be in | |
5768 | increments of two. | |
5769 | ||
5770 | Return FALSE if such a register list is invalid, otherwise return TRUE. */ | |
5771 | ||
5772 | static bfd_boolean | |
5773 | reg_list_valid_p (uint32_t reginfo, int accept_alternate) | |
5774 | { | |
5775 | uint32_t i, nb_regs, prev_regno, incr; | |
5776 | ||
5777 | nb_regs = 1 + (reginfo & 0x3); | |
5778 | reginfo >>= 2; | |
5779 | prev_regno = reginfo & 0x1f; | |
5780 | incr = accept_alternate ? 2 : 1; | |
5781 | ||
5782 | for (i = 1; i < nb_regs; ++i) | |
5783 | { | |
5784 | uint32_t curr_regno; | |
5785 | reginfo >>= 5; | |
5786 | curr_regno = reginfo & 0x1f; | |
5787 | if (curr_regno != ((prev_regno + incr) & 0x1f)) | |
5788 | return FALSE; | |
5789 | prev_regno = curr_regno; | |
5790 | } | |
5791 | ||
5792 | return TRUE; | |
5793 | } | |
5794 | ||
3e2ac3d2 SP |
5795 | static bfd_boolean |
5796 | parse_perms (char **str, aarch64_opnd_info *info) | |
5797 | { | |
5798 | char *p = *str; | |
5799 | char c; | |
5800 | aarch64_insn perms = 0; | |
5801 | ||
5802 | /* Numeric value of permissions. */ | |
5803 | if (ISDIGIT (*p) || (*p == '#' && p++)) | |
5804 | { | |
5805 | perms = *p - '0'; | |
5806 | if (p[1] > 0 || perms > 7) | |
5807 | { | |
5808 | set_syntax_error (_("invalid permission value")); | |
5809 | return FALSE; | |
5810 | } | |
5811 | p += 2; | |
5812 | goto out; | |
5813 | } | |
5814 | ||
5815 | /* Permission specifier mnemonics r, w and x, in that order. Do not accept | |
5816 | jumbled up sequences such as rxw, wrx, etc. and also reject duplicate | |
5817 | permissions such as rrxw. */ | |
5818 | while ((c = *p++) != '\0') | |
5819 | { | |
5820 | aarch64_insn i = get_perm_bit (c); | |
5821 | if (i > 7 || i & perms || (i - 1) & perms) | |
5822 | { | |
5823 | set_syntax_error (_("invalid permissions")); | |
5824 | return FALSE; | |
5825 | } | |
5826 | perms |= i; | |
5827 | } | |
5828 | ||
5829 | out: | |
5830 | *str = p - 1; | |
5831 | info->perm = perms; | |
5832 | return TRUE; | |
5833 | } | |
5834 | ||
a06ea964 NC |
5835 | /* Generic instruction operand parser. This does no encoding and no |
5836 | semantic validation; it merely squirrels values away in the inst | |
5837 | structure. Returns TRUE or FALSE depending on whether the | |
5838 | specified grammar matched. */ | |
5839 | ||
5840 | static bfd_boolean | |
5841 | parse_operands (char *str, const aarch64_opcode *opcode) | |
5842 | { | |
5843 | int i; | |
5844 | char *backtrack_pos = 0; | |
5845 | const enum aarch64_opnd *operands = opcode->operands; | |
1799c0d0 | 5846 | aarch64_reg_type imm_reg_type; |
a06ea964 NC |
5847 | |
5848 | clear_error (); | |
5849 | skip_whitespace (str); | |
5850 | ||
c0890d26 | 5851 | if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE, *opcode->avariant)) |
5b2b928e | 5852 | imm_reg_type = REG_TYPE_R_Z_SP_BHSDQ_VZP; |
c0890d26 RS |
5853 | else |
5854 | imm_reg_type = REG_TYPE_R_Z_BHSDQ_V; | |
1799c0d0 | 5855 | |
a06ea964 NC |
5856 | for (i = 0; operands[i] != AARCH64_OPND_NIL; i++) |
5857 | { | |
5858 | int64_t val; | |
e1b988bb | 5859 | const reg_entry *reg; |
a06ea964 NC |
5860 | int comma_skipped_p = 0; |
5861 | aarch64_reg_type rtype; | |
8f9a77af | 5862 | struct vector_type_el vectype; |
4df068de | 5863 | aarch64_opnd_qualifier_t qualifier, base_qualifier, offset_qualifier; |
a06ea964 | 5864 | aarch64_opnd_info *info = &inst.base.operands[i]; |
f11ad6bc | 5865 | aarch64_reg_type reg_type; |
a06ea964 NC |
5866 | |
5867 | DEBUG_TRACE ("parse operand %d", i); | |
5868 | ||
5869 | /* Assign the operand code. */ | |
5870 | info->type = operands[i]; | |
5871 | ||
5872 | if (optional_operand_p (opcode, i)) | |
5873 | { | |
5874 | /* Remember where we are in case we need to backtrack. */ | |
5875 | gas_assert (!backtrack_pos); | |
5876 | backtrack_pos = str; | |
5877 | } | |
5878 | ||
33eaf5de | 5879 | /* Expect comma between operands; the backtrack mechanism will take |
a06ea964 NC |
5880 | care of cases of omitted optional operand. */ |
5881 | if (i > 0 && ! skip_past_char (&str, ',')) | |
5882 | { | |
5883 | set_syntax_error (_("comma expected between operands")); | |
5884 | goto failure; | |
5885 | } | |
5886 | else | |
5887 | comma_skipped_p = 1; | |
5888 | ||
5889 | switch (operands[i]) | |
5890 | { | |
477ec121 SP |
5891 | case AARCH64_OPND_Wt: |
5892 | po_int_reg_or_fail (REG_TYPE_R_32); | |
5893 | break; | |
5894 | ||
08da6e93 | 5895 | case AARCH64_OPND_Rsz: |
ec87fc0f | 5896 | case AARCH64_OPND_Rsz2: |
a06ea964 NC |
5897 | case AARCH64_OPND_Rd: |
5898 | case AARCH64_OPND_Rn: | |
5899 | case AARCH64_OPND_Rm: | |
5900 | case AARCH64_OPND_Rt: | |
5901 | case AARCH64_OPND_Rt2: | |
5902 | case AARCH64_OPND_Rs: | |
5903 | case AARCH64_OPND_Ra: | |
5904 | case AARCH64_OPND_Rt_SYS: | |
ee804238 | 5905 | case AARCH64_OPND_PAIRREG: |
047cd301 | 5906 | case AARCH64_OPND_SVE_Rm: |
e1b988bb | 5907 | po_int_reg_or_fail (REG_TYPE_R_Z); |
a06ea964 NC |
5908 | break; |
5909 | ||
5910 | case AARCH64_OPND_Rd_SP: | |
5911 | case AARCH64_OPND_Rn_SP: | |
bd7ceb8d | 5912 | case AARCH64_OPND_Rt_SP: |
047cd301 | 5913 | case AARCH64_OPND_SVE_Rn_SP: |
c84364ec | 5914 | case AARCH64_OPND_Rm_SP: |
e1b988bb | 5915 | po_int_reg_or_fail (REG_TYPE_R_SP); |
a06ea964 NC |
5916 | break; |
5917 | ||
dc64c2ba | 5918 | case AARCH64_OPND_A64C_Rm_EXT: |
a06ea964 NC |
5919 | case AARCH64_OPND_Rm_EXT: |
5920 | case AARCH64_OPND_Rm_SFT: | |
5921 | po_misc_or_fail (parse_shifter_operand | |
dc64c2ba SP |
5922 | (&str, info, (operands[i] == AARCH64_OPND_Rm_SFT |
5923 | ? SHIFTED_LOGIC_IMM | |
5924 | : SHIFTED_ARITH_IMM))); | |
a06ea964 NC |
5925 | if (!info->shifter.operator_present) |
5926 | { | |
5927 | /* Default to LSL if not present. Libopcodes prefers shifter | |
5928 | kind to be explicit. */ | |
5929 | gas_assert (info->shifter.kind == AARCH64_MOD_NONE); | |
5930 | info->shifter.kind = AARCH64_MOD_LSL; | |
5931 | /* For Rm_EXT, libopcodes will carry out further check on whether | |
5932 | or not stack pointer is used in the instruction (Recall that | |
5933 | "the extend operator is not optional unless at least one of | |
5934 | "Rd" or "Rn" is '11111' (i.e. WSP)"). */ | |
5935 | } | |
5936 | break; | |
5937 | ||
ec87fc0f | 5938 | case AARCH64_OPND_Fsz: |
a06ea964 NC |
5939 | case AARCH64_OPND_Fd: |
5940 | case AARCH64_OPND_Fn: | |
5941 | case AARCH64_OPND_Fm: | |
5942 | case AARCH64_OPND_Fa: | |
5943 | case AARCH64_OPND_Ft: | |
5944 | case AARCH64_OPND_Ft2: | |
5945 | case AARCH64_OPND_Sd: | |
5946 | case AARCH64_OPND_Sn: | |
5947 | case AARCH64_OPND_Sm: | |
ec87fc0f | 5948 | case AARCH64_OPND_St: |
047cd301 RS |
5949 | case AARCH64_OPND_SVE_VZn: |
5950 | case AARCH64_OPND_SVE_Vd: | |
5951 | case AARCH64_OPND_SVE_Vm: | |
5952 | case AARCH64_OPND_SVE_Vn: | |
a06ea964 NC |
5953 | val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL); |
5954 | if (val == PARSE_FAIL) | |
5955 | { | |
5956 | first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ))); | |
5957 | goto failure; | |
5958 | } | |
5959 | gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q); | |
5960 | ||
5961 | info->reg.regno = val; | |
5962 | info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B); | |
5963 | break; | |
5964 | ||
f11ad6bc RS |
5965 | case AARCH64_OPND_SVE_Pd: |
5966 | case AARCH64_OPND_SVE_Pg3: | |
5967 | case AARCH64_OPND_SVE_Pg4_5: | |
5968 | case AARCH64_OPND_SVE_Pg4_10: | |
5969 | case AARCH64_OPND_SVE_Pg4_16: | |
5970 | case AARCH64_OPND_SVE_Pm: | |
5971 | case AARCH64_OPND_SVE_Pn: | |
5972 | case AARCH64_OPND_SVE_Pt: | |
5973 | reg_type = REG_TYPE_PN; | |
5974 | goto vector_reg; | |
5975 | ||
5976 | case AARCH64_OPND_SVE_Za_5: | |
5977 | case AARCH64_OPND_SVE_Za_16: | |
5978 | case AARCH64_OPND_SVE_Zd: | |
5979 | case AARCH64_OPND_SVE_Zm_5: | |
5980 | case AARCH64_OPND_SVE_Zm_16: | |
5981 | case AARCH64_OPND_SVE_Zn: | |
5982 | case AARCH64_OPND_SVE_Zt: | |
5983 | reg_type = REG_TYPE_ZN; | |
5984 | goto vector_reg; | |
5985 | ||
f42f1a1d | 5986 | case AARCH64_OPND_Va: |
a06ea964 NC |
5987 | case AARCH64_OPND_Vd: |
5988 | case AARCH64_OPND_Vn: | |
5989 | case AARCH64_OPND_Vm: | |
f11ad6bc RS |
5990 | reg_type = REG_TYPE_VN; |
5991 | vector_reg: | |
5992 | val = aarch64_reg_parse (&str, reg_type, NULL, &vectype); | |
a06ea964 NC |
5993 | if (val == PARSE_FAIL) |
5994 | { | |
f11ad6bc | 5995 | first_error (_(get_reg_expected_msg (reg_type))); |
a06ea964 NC |
5996 | goto failure; |
5997 | } | |
5998 | if (vectype.defined & NTA_HASINDEX) | |
5999 | goto failure; | |
6000 | ||
6001 | info->reg.regno = val; | |
f11ad6bc RS |
6002 | if ((reg_type == REG_TYPE_PN || reg_type == REG_TYPE_ZN) |
6003 | && vectype.type == NT_invtype) | |
6004 | /* Unqualified Pn and Zn registers are allowed in certain | |
6005 | contexts. Rely on F_STRICT qualifier checking to catch | |
6006 | invalid uses. */ | |
6007 | info->qualifier = AARCH64_OPND_QLF_NIL; | |
6008 | else | |
6009 | { | |
6010 | info->qualifier = vectype_to_qualifier (&vectype); | |
6011 | if (info->qualifier == AARCH64_OPND_QLF_NIL) | |
6012 | goto failure; | |
6013 | } | |
a06ea964 NC |
6014 | break; |
6015 | ||
6016 | case AARCH64_OPND_VdD1: | |
6017 | case AARCH64_OPND_VnD1: | |
6018 | val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype); | |
6019 | if (val == PARSE_FAIL) | |
6020 | { | |
6021 | set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN))); | |
6022 | goto failure; | |
6023 | } | |
6024 | if (vectype.type != NT_d || vectype.index != 1) | |
6025 | { | |
6026 | set_fatal_syntax_error | |
6027 | (_("the top half of a 128-bit FP/SIMD register is expected")); | |
6028 | goto failure; | |
6029 | } | |
6030 | info->reg.regno = val; | |
6031 | /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register | |
6032 | here; it is correct for the purpose of encoding/decoding since | |
6033 | only the register number is explicitly encoded in the related | |
6034 | instructions, although this appears a bit hacky. */ | |
6035 | info->qualifier = AARCH64_OPND_QLF_S_D; | |
6036 | break; | |
6037 | ||
582e12bf RS |
6038 | case AARCH64_OPND_SVE_Zm3_INDEX: |
6039 | case AARCH64_OPND_SVE_Zm3_22_INDEX: | |
116adc27 | 6040 | case AARCH64_OPND_SVE_Zm3_11_INDEX: |
31e36ab3 | 6041 | case AARCH64_OPND_SVE_Zm4_11_INDEX: |
582e12bf | 6042 | case AARCH64_OPND_SVE_Zm4_INDEX: |
f11ad6bc RS |
6043 | case AARCH64_OPND_SVE_Zn_INDEX: |
6044 | reg_type = REG_TYPE_ZN; | |
6045 | goto vector_reg_index; | |
6046 | ||
a06ea964 NC |
6047 | case AARCH64_OPND_Ed: |
6048 | case AARCH64_OPND_En: | |
6049 | case AARCH64_OPND_Em: | |
369c9167 | 6050 | case AARCH64_OPND_Em16: |
f42f1a1d | 6051 | case AARCH64_OPND_SM3_IMM2: |
f11ad6bc RS |
6052 | reg_type = REG_TYPE_VN; |
6053 | vector_reg_index: | |
6054 | val = aarch64_reg_parse (&str, reg_type, NULL, &vectype); | |
a06ea964 NC |
6055 | if (val == PARSE_FAIL) |
6056 | { | |
f11ad6bc | 6057 | first_error (_(get_reg_expected_msg (reg_type))); |
a06ea964 NC |
6058 | goto failure; |
6059 | } | |
6060 | if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX)) | |
6061 | goto failure; | |
6062 | ||
6063 | info->reglane.regno = val; | |
6064 | info->reglane.index = vectype.index; | |
6065 | info->qualifier = vectype_to_qualifier (&vectype); | |
6066 | if (info->qualifier == AARCH64_OPND_QLF_NIL) | |
6067 | goto failure; | |
6068 | break; | |
6069 | ||
f11ad6bc RS |
6070 | case AARCH64_OPND_SVE_ZnxN: |
6071 | case AARCH64_OPND_SVE_ZtxN: | |
6072 | reg_type = REG_TYPE_ZN; | |
6073 | goto vector_reg_list; | |
6074 | ||
a06ea964 NC |
6075 | case AARCH64_OPND_LVn: |
6076 | case AARCH64_OPND_LVt: | |
6077 | case AARCH64_OPND_LVt_AL: | |
6078 | case AARCH64_OPND_LEt: | |
f11ad6bc RS |
6079 | reg_type = REG_TYPE_VN; |
6080 | vector_reg_list: | |
6081 | if (reg_type == REG_TYPE_ZN | |
6082 | && get_opcode_dependent_value (opcode) == 1 | |
6083 | && *str != '{') | |
a06ea964 | 6084 | { |
f11ad6bc RS |
6085 | val = aarch64_reg_parse (&str, reg_type, NULL, &vectype); |
6086 | if (val == PARSE_FAIL) | |
6087 | { | |
6088 | first_error (_(get_reg_expected_msg (reg_type))); | |
6089 | goto failure; | |
6090 | } | |
6091 | info->reglist.first_regno = val; | |
6092 | info->reglist.num_regs = 1; | |
6093 | } | |
6094 | else | |
6095 | { | |
6096 | val = parse_vector_reg_list (&str, reg_type, &vectype); | |
6097 | if (val == PARSE_FAIL) | |
6098 | goto failure; | |
163b2c58 | 6099 | |
f11ad6bc RS |
6100 | if (! reg_list_valid_p (val, /* accept_alternate */ 0)) |
6101 | { | |
6102 | set_fatal_syntax_error (_("invalid register list")); | |
6103 | goto failure; | |
6104 | } | |
163b2c58 BW |
6105 | |
6106 | if (vectype.width != 0 && *str != ',') | |
6107 | { | |
6108 | set_fatal_syntax_error | |
6109 | (_("expected element type rather than vector type")); | |
6110 | goto failure; | |
6111 | } | |
6112 | ||
f11ad6bc RS |
6113 | info->reglist.first_regno = (val >> 2) & 0x1f; |
6114 | info->reglist.num_regs = (val & 0x3) + 1; | |
a06ea964 | 6115 | } |
a06ea964 NC |
6116 | if (operands[i] == AARCH64_OPND_LEt) |
6117 | { | |
6118 | if (!(vectype.defined & NTA_HASINDEX)) | |
6119 | goto failure; | |
6120 | info->reglist.has_index = 1; | |
6121 | info->reglist.index = vectype.index; | |
6122 | } | |
f11ad6bc RS |
6123 | else |
6124 | { | |
6125 | if (vectype.defined & NTA_HASINDEX) | |
6126 | goto failure; | |
6127 | if (!(vectype.defined & NTA_HASTYPE)) | |
6128 | { | |
6129 | if (reg_type == REG_TYPE_ZN) | |
6130 | set_fatal_syntax_error (_("missing type suffix")); | |
6131 | goto failure; | |
6132 | } | |
6133 | } | |
a06ea964 NC |
6134 | info->qualifier = vectype_to_qualifier (&vectype); |
6135 | if (info->qualifier == AARCH64_OPND_QLF_NIL) | |
6136 | goto failure; | |
6137 | break; | |
6138 | ||
ec145252 SP |
6139 | case AARCH64_OPND_Can: |
6140 | case AARCH64_OPND_Cam: | |
6141 | case AARCH64_OPND_Cas: | |
6142 | case AARCH64_OPND_Cad: | |
6143 | case AARCH64_OPND_Cat: | |
6144 | case AARCH64_OPND_Cat2: | |
bbb36683 | 6145 | case AARCH64_OPND_Cat_SYS: |
ec145252 SP |
6146 | po_reg_or_fail (REG_TYPE_CA_N_Z); |
6147 | if (opcode->op == OP_MOV_C_ZR && operands[i] == AARCH64_OPND_Can | |
6148 | && val != 31) | |
6149 | { | |
6150 | set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CA_Z))); | |
6151 | goto failure; | |
6152 | } | |
6153 | if (val > 31) | |
6154 | { | |
6155 | set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CA_N))); | |
6156 | goto failure; | |
6157 | } | |
6158 | info->reg.regno = val; | |
6159 | info->qualifier = AARCH64_OPND_QLF_CA; | |
6160 | break; | |
6161 | ||
adffaa8e SP |
6162 | case AARCH64_OPND_A64C_CST_REG: |
6163 | po_reg_or_fail (REG_TYPE_CA_N); | |
6164 | if (val != 29 | |
6165 | && (opcode->iclass == br_sealed)) | |
6166 | { | |
6167 | set_fatal_syntax_error | |
6168 | (_(N_ ("Capability register c29 expected"))); | |
6169 | goto failure; | |
6170 | } | |
6171 | info->reg.regno = val; | |
6172 | info->qualifier = AARCH64_OPND_QLF_CA; | |
6173 | break; | |
6174 | ||
6175 | case AARCH64_OPND_Cam_SP: | |
ec145252 SP |
6176 | case AARCH64_OPND_Can_SP: |
6177 | case AARCH64_OPND_Cad_SP: | |
6178 | po_reg_or_fail (REG_TYPE_CA_N_SP); | |
6179 | info->reg.regno = val; | |
6180 | info->qualifier = AARCH64_OPND_QLF_CA; | |
6181 | break; | |
6182 | ||
a6a51754 RL |
6183 | case AARCH64_OPND_CRn: |
6184 | case AARCH64_OPND_CRm: | |
a06ea964 | 6185 | { |
a6a51754 RL |
6186 | char prefix = *(str++); |
6187 | if (prefix != 'c' && prefix != 'C') | |
6188 | goto failure; | |
6189 | ||
6190 | po_imm_nc_or_fail (); | |
6191 | if (val > 15) | |
6192 | { | |
6193 | set_fatal_syntax_error (_(N_ ("C0 - C15 expected"))); | |
6194 | goto failure; | |
6195 | } | |
6196 | info->qualifier = AARCH64_OPND_QLF_CR; | |
6197 | info->imm.value = val; | |
6198 | break; | |
a06ea964 | 6199 | } |
a06ea964 NC |
6200 | |
6201 | case AARCH64_OPND_SHLL_IMM: | |
6202 | case AARCH64_OPND_IMM_VLSR: | |
6203 | po_imm_or_fail (1, 64); | |
6204 | info->imm.value = val; | |
6205 | break; | |
6206 | ||
9e5e0b29 | 6207 | case AARCH64_OPND_A64C_IMM8: |
a06ea964 | 6208 | case AARCH64_OPND_CCMP_IMM: |
e950b345 | 6209 | case AARCH64_OPND_SIMM5: |
a06ea964 | 6210 | case AARCH64_OPND_FBITS: |
b83b4b13 | 6211 | case AARCH64_OPND_TME_UIMM16: |
a06ea964 | 6212 | case AARCH64_OPND_UIMM4: |
193614f2 SD |
6213 | case AARCH64_OPND_UIMM4_ADDG: |
6214 | case AARCH64_OPND_UIMM10: | |
a06ea964 NC |
6215 | case AARCH64_OPND_UIMM3_OP1: |
6216 | case AARCH64_OPND_UIMM3_OP2: | |
6217 | case AARCH64_OPND_IMM_VLSL: | |
6218 | case AARCH64_OPND_IMM: | |
f42f1a1d | 6219 | case AARCH64_OPND_IMM_2: |
a06ea964 | 6220 | case AARCH64_OPND_WIDTH: |
e950b345 RS |
6221 | case AARCH64_OPND_SVE_INV_LIMM: |
6222 | case AARCH64_OPND_SVE_LIMM: | |
6223 | case AARCH64_OPND_SVE_LIMM_MOV: | |
6224 | case AARCH64_OPND_SVE_SHLIMM_PRED: | |
6225 | case AARCH64_OPND_SVE_SHLIMM_UNPRED: | |
28ed815a | 6226 | case AARCH64_OPND_SVE_SHLIMM_UNPRED_22: |
e950b345 RS |
6227 | case AARCH64_OPND_SVE_SHRIMM_PRED: |
6228 | case AARCH64_OPND_SVE_SHRIMM_UNPRED: | |
3c17238b | 6229 | case AARCH64_OPND_SVE_SHRIMM_UNPRED_22: |
e950b345 RS |
6230 | case AARCH64_OPND_SVE_SIMM5: |
6231 | case AARCH64_OPND_SVE_SIMM5B: | |
6232 | case AARCH64_OPND_SVE_SIMM6: | |
6233 | case AARCH64_OPND_SVE_SIMM8: | |
6234 | case AARCH64_OPND_SVE_UIMM3: | |
6235 | case AARCH64_OPND_SVE_UIMM7: | |
6236 | case AARCH64_OPND_SVE_UIMM8: | |
6237 | case AARCH64_OPND_SVE_UIMM8_53: | |
c2c4ff8d SN |
6238 | case AARCH64_OPND_IMM_ROT1: |
6239 | case AARCH64_OPND_IMM_ROT2: | |
6240 | case AARCH64_OPND_IMM_ROT3: | |
582e12bf RS |
6241 | case AARCH64_OPND_SVE_IMM_ROT1: |
6242 | case AARCH64_OPND_SVE_IMM_ROT2: | |
adccc507 | 6243 | case AARCH64_OPND_SVE_IMM_ROT3: |
a06ea964 NC |
6244 | po_imm_nc_or_fail (); |
6245 | info->imm.value = val; | |
6246 | break; | |
6247 | ||
e950b345 RS |
6248 | case AARCH64_OPND_SVE_AIMM: |
6249 | case AARCH64_OPND_SVE_ASIMM: | |
6250 | po_imm_nc_or_fail (); | |
6251 | info->imm.value = val; | |
6252 | skip_whitespace (str); | |
6253 | if (skip_past_comma (&str)) | |
6254 | po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL)); | |
6255 | else | |
6256 | inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL; | |
6257 | break; | |
6258 | ||
245d2e3f RS |
6259 | case AARCH64_OPND_SVE_PATTERN: |
6260 | po_enum_or_fail (aarch64_sve_pattern_array); | |
6261 | info->imm.value = val; | |
6262 | break; | |
6263 | ||
2442d846 RS |
6264 | case AARCH64_OPND_SVE_PATTERN_SCALED: |
6265 | po_enum_or_fail (aarch64_sve_pattern_array); | |
6266 | info->imm.value = val; | |
6267 | if (skip_past_comma (&str) | |
6268 | && !parse_shift (&str, info, SHIFTED_MUL)) | |
6269 | goto failure; | |
6270 | if (!info->shifter.operator_present) | |
6271 | { | |
6272 | gas_assert (info->shifter.kind == AARCH64_MOD_NONE); | |
6273 | info->shifter.kind = AARCH64_MOD_MUL; | |
6274 | info->shifter.amount = 1; | |
6275 | } | |
6276 | break; | |
6277 | ||
245d2e3f RS |
6278 | case AARCH64_OPND_SVE_PRFOP: |
6279 | po_enum_or_fail (aarch64_sve_prfop_array); | |
6280 | info->imm.value = val; | |
6281 | break; | |
6282 | ||
a06ea964 NC |
6283 | case AARCH64_OPND_UIMM7: |
6284 | po_imm_or_fail (0, 127); | |
6285 | info->imm.value = val; | |
6286 | break; | |
6287 | ||
6288 | case AARCH64_OPND_IDX: | |
f42f1a1d | 6289 | case AARCH64_OPND_MASK: |
a06ea964 NC |
6290 | case AARCH64_OPND_BIT_NUM: |
6291 | case AARCH64_OPND_IMMR: | |
6292 | case AARCH64_OPND_IMMS: | |
6293 | po_imm_or_fail (0, 63); | |
6294 | info->imm.value = val; | |
6295 | break; | |
6296 | ||
adffaa8e SP |
6297 | case AARCH64_OPND_A64C_IMMV4: |
6298 | po_imm_nc_or_fail (); | |
6299 | if (val != 4) | |
6300 | { | |
6301 | set_fatal_syntax_error (_("immediate #4 expected")); | |
6302 | goto failure; | |
6303 | } | |
6304 | info->imm.value = 4; | |
6305 | break; | |
6306 | ||
a06ea964 NC |
6307 | case AARCH64_OPND_IMM0: |
6308 | po_imm_nc_or_fail (); | |
6309 | if (val != 0) | |
6310 | { | |
6311 | set_fatal_syntax_error (_("immediate zero expected")); | |
6312 | goto failure; | |
6313 | } | |
6314 | info->imm.value = 0; | |
6315 | break; | |
6316 | ||
6317 | case AARCH64_OPND_FPIMM0: | |
6318 | { | |
6319 | int qfloat; | |
6320 | bfd_boolean res1 = FALSE, res2 = FALSE; | |
6321 | /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected, | |
6322 | it is probably not worth the effort to support it. */ | |
1799c0d0 RS |
6323 | if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE, |
6324 | imm_reg_type)) | |
6a9deabe RS |
6325 | && (error_p () |
6326 | || !(res2 = parse_constant_immediate (&str, &val, | |
6327 | imm_reg_type)))) | |
a06ea964 NC |
6328 | goto failure; |
6329 | if ((res1 && qfloat == 0) || (res2 && val == 0)) | |
6330 | { | |
6331 | info->imm.value = 0; | |
6332 | info->imm.is_fp = 1; | |
6333 | break; | |
6334 | } | |
6335 | set_fatal_syntax_error (_("immediate zero expected")); | |
6336 | goto failure; | |
6337 | } | |
6338 | ||
6339 | case AARCH64_OPND_IMM_MOV: | |
6340 | { | |
6341 | char *saved = str; | |
8db49cc2 WN |
6342 | if (reg_name_p (str, REG_TYPE_R_Z_SP) || |
6343 | reg_name_p (str, REG_TYPE_VN)) | |
a06ea964 NC |
6344 | goto failure; |
6345 | str = saved; | |
6346 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6347 | GE_OPT_PREFIX, 1)); | |
6348 | /* The MOV immediate alias will be fixed up by fix_mov_imm_insn | |
6349 | later. fix_mov_imm_insn will try to determine a machine | |
6350 | instruction (MOVZ, MOVN or ORR) for it and will issue an error | |
6351 | message if the immediate cannot be moved by a single | |
6352 | instruction. */ | |
6353 | aarch64_set_gas_internal_fixup (&inst.reloc, info, 1); | |
6354 | inst.base.operands[i].skip = 1; | |
6355 | } | |
6356 | break; | |
6357 | ||
6358 | case AARCH64_OPND_SIMD_IMM: | |
6359 | case AARCH64_OPND_SIMD_IMM_SFT: | |
1799c0d0 | 6360 | if (! parse_big_immediate (&str, &val, imm_reg_type)) |
a06ea964 NC |
6361 | goto failure; |
6362 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, | |
6363 | /* addr_off_p */ 0, | |
6364 | /* need_libopcodes_p */ 1, | |
6365 | /* skip_p */ 1); | |
6366 | /* Parse shift. | |
6367 | N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any | |
6368 | shift, we don't check it here; we leave the checking to | |
6369 | the libopcodes (operand_general_constraint_met_p). By | |
6370 | doing this, we achieve better diagnostics. */ | |
6371 | if (skip_past_comma (&str) | |
6372 | && ! parse_shift (&str, info, SHIFTED_LSL_MSL)) | |
6373 | goto failure; | |
6374 | if (!info->shifter.operator_present | |
6375 | && info->type == AARCH64_OPND_SIMD_IMM_SFT) | |
6376 | { | |
6377 | /* Default to LSL if not present. Libopcodes prefers shifter | |
6378 | kind to be explicit. */ | |
6379 | gas_assert (info->shifter.kind == AARCH64_MOD_NONE); | |
6380 | info->shifter.kind = AARCH64_MOD_LSL; | |
6381 | } | |
6382 | break; | |
6383 | ||
6384 | case AARCH64_OPND_FPIMM: | |
6385 | case AARCH64_OPND_SIMD_FPIMM: | |
165d4950 | 6386 | case AARCH64_OPND_SVE_FPIMM8: |
a06ea964 NC |
6387 | { |
6388 | int qfloat; | |
165d4950 RS |
6389 | bfd_boolean dp_p; |
6390 | ||
6391 | dp_p = double_precision_operand_p (&inst.base.operands[0]); | |
6a9deabe | 6392 | if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type) |
874d7e6e | 6393 | || !aarch64_imm_float_p (qfloat)) |
a06ea964 | 6394 | { |
6a9deabe RS |
6395 | if (!error_p ()) |
6396 | set_fatal_syntax_error (_("invalid floating-point" | |
6397 | " constant")); | |
a06ea964 NC |
6398 | goto failure; |
6399 | } | |
6400 | inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat); | |
6401 | inst.base.operands[i].imm.is_fp = 1; | |
6402 | } | |
6403 | break; | |
6404 | ||
165d4950 RS |
6405 | case AARCH64_OPND_SVE_I1_HALF_ONE: |
6406 | case AARCH64_OPND_SVE_I1_HALF_TWO: | |
6407 | case AARCH64_OPND_SVE_I1_ZERO_ONE: | |
6408 | { | |
6409 | int qfloat; | |
6410 | bfd_boolean dp_p; | |
6411 | ||
6412 | dp_p = double_precision_operand_p (&inst.base.operands[0]); | |
6413 | if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type)) | |
6414 | { | |
6415 | if (!error_p ()) | |
6416 | set_fatal_syntax_error (_("invalid floating-point" | |
6417 | " constant")); | |
6418 | goto failure; | |
6419 | } | |
6420 | inst.base.operands[i].imm.value = qfloat; | |
6421 | inst.base.operands[i].imm.is_fp = 1; | |
6422 | } | |
6423 | break; | |
6424 | ||
a06ea964 NC |
6425 | case AARCH64_OPND_LIMM: |
6426 | po_misc_or_fail (parse_shifter_operand (&str, info, | |
6427 | SHIFTED_LOGIC_IMM)); | |
6428 | if (info->shifter.operator_present) | |
6429 | { | |
6430 | set_fatal_syntax_error | |
6431 | (_("shift not allowed for bitmask immediate")); | |
6432 | goto failure; | |
6433 | } | |
6434 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, | |
6435 | /* addr_off_p */ 0, | |
6436 | /* need_libopcodes_p */ 1, | |
6437 | /* skip_p */ 1); | |
6438 | break; | |
6439 | ||
0bd71233 SP |
6440 | case AARCH64_OPND_A64C_IMM6_EXT: |
6441 | po_misc_or_fail (parse_shifter_operand_imm (&str, info, | |
6442 | SHIFTED_ARITH_IMM)); | |
6443 | ||
6444 | /* Try to coerce into shifted form if the immediate is out of | |
6445 | range. */ | |
6446 | if (inst.reloc.exp.X_add_number > 63 && (info->imm.value & 16) == 0 | |
6447 | && (inst.reloc.exp.X_add_number >> 4) <= 64 | |
6448 | && info->shifter.amount == 0) | |
6449 | { | |
6450 | info->shifter.amount = 4; | |
6451 | info->shifter.kind = AARCH64_MOD_LSL; | |
6452 | info->imm.value = inst.reloc.exp.X_add_number >> 4; | |
6453 | } | |
6454 | else | |
6455 | info->imm.value = inst.reloc.exp.X_add_number; | |
6456 | break; | |
6457 | ||
a06ea964 | 6458 | case AARCH64_OPND_AIMM: |
dc64c2ba SP |
6459 | case AARCH64_OPND_A64C_AIMM: |
6460 | if (opcode->op == OP_ADD || opcode->op == OP_A64C_ADD) | |
a06ea964 NC |
6461 | /* ADD may have relocation types. */ |
6462 | po_misc_or_fail (parse_shifter_operand_reloc (&str, info, | |
6463 | SHIFTED_ARITH_IMM)); | |
6464 | else | |
6465 | po_misc_or_fail (parse_shifter_operand (&str, info, | |
6466 | SHIFTED_ARITH_IMM)); | |
6467 | switch (inst.reloc.type) | |
6468 | { | |
6469 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: | |
6470 | info->shifter.amount = 12; | |
6471 | break; | |
6472 | case BFD_RELOC_UNUSED: | |
6473 | aarch64_set_gas_internal_fixup (&inst.reloc, info, 0); | |
6474 | if (info->shifter.kind != AARCH64_MOD_NONE) | |
6475 | inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT; | |
6476 | inst.reloc.pc_rel = 0; | |
6477 | break; | |
6478 | default: | |
6479 | break; | |
6480 | } | |
6481 | info->imm.value = 0; | |
6482 | if (!info->shifter.operator_present) | |
6483 | { | |
6484 | /* Default to LSL if not present. Libopcodes prefers shifter | |
6485 | kind to be explicit. */ | |
6486 | gas_assert (info->shifter.kind == AARCH64_MOD_NONE); | |
6487 | info->shifter.kind = AARCH64_MOD_LSL; | |
6488 | } | |
6489 | break; | |
6490 | ||
6491 | case AARCH64_OPND_HALF: | |
6492 | { | |
6493 | /* #<imm16> or relocation. */ | |
6494 | int internal_fixup_p; | |
6495 | po_misc_or_fail (parse_half (&str, &internal_fixup_p)); | |
6496 | if (internal_fixup_p) | |
6497 | aarch64_set_gas_internal_fixup (&inst.reloc, info, 0); | |
6498 | skip_whitespace (str); | |
6499 | if (skip_past_comma (&str)) | |
6500 | { | |
6501 | /* {, LSL #<shift>} */ | |
6502 | if (! aarch64_gas_internal_fixup_p ()) | |
6503 | { | |
6504 | set_fatal_syntax_error (_("can't mix relocation modifier " | |
6505 | "with explicit shift")); | |
6506 | goto failure; | |
6507 | } | |
6508 | po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL)); | |
6509 | } | |
6510 | else | |
6511 | inst.base.operands[i].shifter.amount = 0; | |
6512 | inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL; | |
6513 | inst.base.operands[i].imm.value = 0; | |
6514 | if (! process_movw_reloc_info ()) | |
6515 | goto failure; | |
6516 | } | |
6517 | break; | |
6518 | ||
6519 | case AARCH64_OPND_EXCEPTION: | |
09c1e68a | 6520 | case AARCH64_OPND_UNDEFINED: |
1799c0d0 RS |
6521 | po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp, |
6522 | imm_reg_type)); | |
a06ea964 NC |
6523 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, |
6524 | /* addr_off_p */ 0, | |
6525 | /* need_libopcodes_p */ 0, | |
6526 | /* skip_p */ 1); | |
6527 | break; | |
6528 | ||
6529 | case AARCH64_OPND_NZCV: | |
6530 | { | |
629310ab | 6531 | const asm_nzcv *nzcv = str_hash_find_n (aarch64_nzcv_hsh, str, 4); |
a06ea964 NC |
6532 | if (nzcv != NULL) |
6533 | { | |
6534 | str += 4; | |
6535 | info->imm.value = nzcv->value; | |
6536 | break; | |
6537 | } | |
6538 | po_imm_or_fail (0, 15); | |
6539 | info->imm.value = val; | |
6540 | } | |
6541 | break; | |
6542 | ||
3e2ac3d2 SP |
6543 | case AARCH64_OPND_PERM: |
6544 | po_misc_or_fail (parse_perms (&str, info)); | |
6545 | break; | |
6546 | ||
7ce74d61 SP |
6547 | case AARCH64_OPND_FORM: |
6548 | { | |
6549 | char *start = str; | |
6550 | do | |
6551 | str++; | |
6552 | while (ISALPHA (*str)); | |
6553 | info->form = get_form_from_str (start, str - start); | |
6554 | if (info->form == NULL) | |
6555 | { | |
6556 | set_syntax_error (_("invalid form")); | |
6557 | goto failure; | |
6558 | } | |
6559 | } | |
6560 | break; | |
6561 | ||
a06ea964 | 6562 | case AARCH64_OPND_COND: |
68a64283 | 6563 | case AARCH64_OPND_COND1: |
bb7eff52 RS |
6564 | { |
6565 | char *start = str; | |
6566 | do | |
6567 | str++; | |
6568 | while (ISALPHA (*str)); | |
629310ab | 6569 | info->cond = str_hash_find_n (aarch64_cond_hsh, start, str - start); |
bb7eff52 RS |
6570 | if (info->cond == NULL) |
6571 | { | |
6572 | set_syntax_error (_("invalid condition")); | |
6573 | goto failure; | |
6574 | } | |
6575 | else if (operands[i] == AARCH64_OPND_COND1 | |
6576 | && (info->cond->value & 0xe) == 0xe) | |
6577 | { | |
6578 | /* Do not allow AL or NV. */ | |
6579 | set_default_error (); | |
6580 | goto failure; | |
6581 | } | |
6582 | } | |
a06ea964 NC |
6583 | break; |
6584 | ||
321c4e1a SP |
6585 | /* ADRP variants. Clear the value as operand needs to be |
6586 | relocated. */ | |
6587 | case AARCH64_OPND_A64C_ADDR_ADRDP: | |
6588 | if (!AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64)) | |
6589 | { | |
6590 | as_bad (_("instruction not allowed on this processor")); | |
6591 | goto failure; | |
6592 | } | |
6593 | po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp, | |
6594 | imm_reg_type)); | |
6595 | if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool) | |
6596 | { | |
6597 | info->imm.value = inst.reloc.exp.X_add_number; | |
6598 | inst.reloc.type = BFD_RELOC_UNUSED; | |
6599 | if (info->imm.value & 0xfff) | |
6600 | goto bad_adrdp; | |
6601 | ||
6602 | info->imm.value >>= 12; | |
6603 | break; | |
6604 | } | |
6605 | bad_adrdp: | |
6606 | set_syntax_error | |
6607 | (_("20-bit 4K page aligned integer constant expected")); | |
6608 | goto failure; | |
6609 | ||
a06ea964 | 6610 | case AARCH64_OPND_ADDR_ADRP: |
321c4e1a SP |
6611 | if (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64)) |
6612 | info->imm.value = 1UL << 20; | |
6613 | else | |
6614 | info->imm.value = 0; | |
6615 | ||
a06ea964 | 6616 | po_misc_or_fail (parse_adrp (&str)); |
a06ea964 NC |
6617 | break; |
6618 | ||
6619 | case AARCH64_OPND_ADDR_PCREL14: | |
f7d2c675 | 6620 | case AARCH64_OPND_ADDR_PCREL17: |
a06ea964 NC |
6621 | case AARCH64_OPND_ADDR_PCREL19: |
6622 | case AARCH64_OPND_ADDR_PCREL21: | |
6623 | case AARCH64_OPND_ADDR_PCREL26: | |
73866052 | 6624 | po_misc_or_fail (parse_address (&str, info)); |
a06ea964 NC |
6625 | if (!info->addr.pcrel) |
6626 | { | |
6627 | set_syntax_error (_("invalid pc-relative address")); | |
6628 | goto failure; | |
6629 | } | |
6630 | if (inst.gen_lit_pool | |
6631 | && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT)) | |
6632 | { | |
6633 | /* Only permit "=value" in the literal load instructions. | |
6634 | The literal will be generated by programmer_friendly_fixup. */ | |
6635 | set_syntax_error (_("invalid use of \"=immediate\"")); | |
6636 | goto failure; | |
6637 | } | |
6638 | if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str)) | |
6639 | { | |
6640 | set_syntax_error (_("unrecognized relocation suffix")); | |
6641 | goto failure; | |
6642 | } | |
6643 | if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool) | |
6644 | { | |
6645 | info->imm.value = inst.reloc.exp.X_add_number; | |
6646 | inst.reloc.type = BFD_RELOC_UNUSED; | |
6647 | } | |
6648 | else | |
6649 | { | |
f0070c1e SP |
6650 | bfd_boolean c64 = AARCH64_CPU_HAS_FEATURE (cpu_variant, |
6651 | AARCH64_FEATURE_C64); | |
6652 | ||
a06ea964 | 6653 | info->imm.value = 0; |
f41aef5f RE |
6654 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
6655 | switch (opcode->iclass) | |
6656 | { | |
6657 | case compbranch: | |
6658 | case condbranch: | |
6659 | /* e.g. CBZ or B.COND */ | |
6660 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19); | |
e19e9199 SP |
6661 | inst.reloc.type = (c64 ? BFD_RELOC_MORELLO_BRANCH19 |
6662 | : BFD_RELOC_AARCH64_BRANCH19); | |
f41aef5f RE |
6663 | break; |
6664 | case testbranch: | |
6665 | /* e.g. TBZ */ | |
6666 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14); | |
e19e9199 SP |
6667 | inst.reloc.type = (c64 ? BFD_RELOC_MORELLO_TSTBR14 |
6668 | : BFD_RELOC_AARCH64_TSTBR14); | |
f41aef5f RE |
6669 | break; |
6670 | case branch_imm: | |
6671 | /* e.g. B or BL */ | |
e19e9199 | 6672 | { |
8f2cd652 | 6673 | bfd_reloc_code_real_type jump, call; |
e19e9199 SP |
6674 | |
6675 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26); | |
6676 | ||
6677 | jump = (c64 ? BFD_RELOC_MORELLO_JUMP26 | |
6678 | : BFD_RELOC_AARCH64_JUMP26); | |
6679 | call = (c64 ? BFD_RELOC_MORELLO_CALL26 | |
6680 | : BFD_RELOC_AARCH64_CALL26); | |
6681 | ||
6682 | inst.reloc.type = opcode->op == OP_BL ? call : jump; | |
6683 | } | |
f41aef5f RE |
6684 | break; |
6685 | case loadlit: | |
f7d2c675 SP |
6686 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19 |
6687 | || operands[i] == AARCH64_OPND_ADDR_PCREL17); | |
6688 | inst.reloc.type = (operands[i] == AARCH64_OPND_ADDR_PCREL19 | |
6689 | ? BFD_RELOC_AARCH64_LD_LO19_PCREL | |
6690 | : BFD_RELOC_MORELLO_LD_LO17_PCREL); | |
f41aef5f RE |
6691 | break; |
6692 | case pcreladdr: | |
6693 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21); | |
6694 | inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL; | |
8b21361b SP |
6695 | if (inst.reloc.exp.X_op == O_symbol |
6696 | && inst.reloc.exp.X_add_symbol != NULL) | |
6697 | { | |
6698 | symbolS *sym = inst.reloc.exp.X_add_symbol; | |
6699 | ||
6700 | /* We set LSB for C64 local functions. We do not do | |
6701 | this for local labels even in code section because | |
6702 | it could be embedded data. */ | |
6703 | if (S_IS_DEFINED (sym) && AARCH64_IS_C64 (sym) | |
6704 | && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION)) | |
6705 | { | |
6706 | inst.reloc.exp.X_add_number += 1; | |
6707 | } | |
6708 | } | |
6709 | ||
f41aef5f RE |
6710 | break; |
6711 | default: | |
6712 | gas_assert (0); | |
6713 | abort (); | |
6714 | } | |
f0070c1e SP |
6715 | if (c64) |
6716 | inst.reloc.flags = FIXUP_F_C64; | |
a06ea964 NC |
6717 | inst.reloc.pc_rel = 1; |
6718 | } | |
6719 | break; | |
6720 | ||
6721 | case AARCH64_OPND_ADDR_SIMPLE: | |
6722 | case AARCH64_OPND_SIMD_ADDR_SIMPLE: | |
e1b988bb RS |
6723 | { |
6724 | /* [<Xn|SP>{, #<simm>}] */ | |
6725 | char *start = str; | |
6726 | /* First use the normal address-parsing routines, to get | |
6727 | the usual syntax errors. */ | |
73866052 | 6728 | po_misc_or_fail (parse_address (&str, info)); |
e1b988bb RS |
6729 | if (info->addr.pcrel || info->addr.offset.is_reg |
6730 | || !info->addr.preind || info->addr.postind | |
550fd7bf | 6731 | || info->addr.writeback) |
e1b988bb RS |
6732 | { |
6733 | set_syntax_error (_("invalid addressing mode")); | |
6734 | goto failure; | |
6735 | } | |
6736 | ||
6737 | /* Then retry, matching the specific syntax of these addresses. */ | |
6738 | str = start; | |
6739 | po_char_or_fail ('['); | |
3493da5c SP |
6740 | po_reg_or_fail (AARCH64_CPU_HAS_FEATURE (cpu_variant, |
6741 | AARCH64_FEATURE_C64) | |
6742 | ? REG_TYPE_CA_N_SP : REG_TYPE_R64_SP); | |
6743 | ||
e1b988bb RS |
6744 | /* Accept optional ", #0". */ |
6745 | if (operands[i] == AARCH64_OPND_ADDR_SIMPLE | |
6746 | && skip_past_char (&str, ',')) | |
6747 | { | |
6748 | skip_past_char (&str, '#'); | |
6749 | if (! skip_past_char (&str, '0')) | |
6750 | { | |
6751 | set_fatal_syntax_error | |
6752 | (_("the optional immediate offset can only be 0")); | |
6753 | goto failure; | |
6754 | } | |
6755 | } | |
6756 | po_char_or_fail (']'); | |
6757 | break; | |
6758 | } | |
a06ea964 | 6759 | |
08da6e93 SP |
6760 | case AARCH64_OPND_CAPADDR_REGOFF: |
6761 | po_misc_or_fail (parse_cap_address (&str, info, opcode->iclass)); | |
6762 | goto regoff_addr; | |
6763 | ||
a06ea964 NC |
6764 | case AARCH64_OPND_ADDR_REGOFF: |
6765 | /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */ | |
73866052 | 6766 | po_misc_or_fail (parse_address (&str, info)); |
4df068de | 6767 | regoff_addr: |
a06ea964 NC |
6768 | if (info->addr.pcrel || !info->addr.offset.is_reg |
6769 | || !info->addr.preind || info->addr.postind | |
6770 | || info->addr.writeback) | |
6771 | { | |
6772 | set_syntax_error (_("invalid addressing mode")); | |
6773 | goto failure; | |
6774 | } | |
6775 | if (!info->shifter.operator_present) | |
6776 | { | |
6777 | /* Default to LSL if not present. Libopcodes prefers shifter | |
6778 | kind to be explicit. */ | |
6779 | gas_assert (info->shifter.kind == AARCH64_MOD_NONE); | |
6780 | info->shifter.kind = AARCH64_MOD_LSL; | |
6781 | } | |
6782 | /* Qualifier to be deduced by libopcodes. */ | |
6783 | break; | |
6784 | ||
f260da95 SP |
6785 | case AARCH64_OPND_CAPADDR_SIMPLE: |
6786 | case AARCH64_OPND_CAPADDR_SIMM7: | |
6787 | { | |
6788 | /* A little hack to prevent the address parser from trying to | |
6789 | pretend that a BLR with a register may be a BLR with an | |
6790 | address. It fails the addressing mode test below, but still | |
6791 | ends up adding a symbol with the name of the register. */ | |
6792 | char *start = str; | |
6793 | po_char_or_fail ('['); | |
6794 | str = start; | |
6795 | ||
6796 | po_misc_or_fail (parse_cap_address (&str, info, opcode->iclass)); | |
6797 | if (info->addr.pcrel || info->addr.offset.is_reg | |
6798 | || (!info->addr.preind && !info->addr.postind) | |
6799 | || info->addr.writeback) | |
6800 | { | |
6801 | set_syntax_error (_("invalid addressing mode")); | |
6802 | goto failure; | |
6803 | } | |
6804 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
6805 | { | |
6806 | set_syntax_error (_("relocation not allowed")); | |
6807 | goto failure; | |
6808 | } | |
6809 | if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool) | |
6810 | info->addr.offset.imm = inst.reloc.exp.X_add_number; | |
6811 | else | |
6812 | { | |
6813 | set_syntax_error (_("Invalid offset constant")); | |
6814 | goto failure; | |
6815 | } | |
6816 | if (info->type == AARCH64_OPND_CAPADDR_SIMPLE | |
6817 | && info->addr.offset.imm != 0) | |
6818 | { | |
6819 | set_syntax_error (_("non-zero offset not allowed")); | |
6820 | goto failure; | |
6821 | } | |
6822 | break; | |
6823 | } | |
6824 | ||
e9af8aad | 6825 | case AARCH64_OPND_A64C_ADDR_SIMM7: |
a06ea964 | 6826 | case AARCH64_OPND_ADDR_SIMM7: |
73866052 | 6827 | po_misc_or_fail (parse_address (&str, info)); |
a06ea964 NC |
6828 | if (info->addr.pcrel || info->addr.offset.is_reg |
6829 | || (!info->addr.preind && !info->addr.postind)) | |
6830 | { | |
6831 | set_syntax_error (_("invalid addressing mode")); | |
6832 | goto failure; | |
6833 | } | |
73866052 RS |
6834 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
6835 | { | |
6836 | set_syntax_error (_("relocation not allowed")); | |
6837 | goto failure; | |
6838 | } | |
a06ea964 NC |
6839 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, |
6840 | /* addr_off_p */ 1, | |
6841 | /* need_libopcodes_p */ 1, | |
6842 | /* skip_p */ 0); | |
6843 | break; | |
6844 | ||
ec87fc0f SP |
6845 | case AARCH64_OPND_CAPADDR_SIMM9: |
6846 | po_misc_or_fail (parse_cap_address (&str, info, opcode->iclass)); | |
6847 | goto addr_simm; | |
6848 | ||
324988cf | 6849 | case AARCH64_OPND_A64C_ADDR_SIMM9: |
a06ea964 NC |
6850 | case AARCH64_OPND_ADDR_SIMM9: |
6851 | case AARCH64_OPND_ADDR_SIMM9_2: | |
fb3265b3 SD |
6852 | case AARCH64_OPND_ADDR_SIMM11: |
6853 | case AARCH64_OPND_ADDR_SIMM13: | |
73866052 | 6854 | po_misc_or_fail (parse_address (&str, info)); |
ec87fc0f | 6855 | addr_simm: |
a06ea964 NC |
6856 | if (info->addr.pcrel || info->addr.offset.is_reg |
6857 | || (!info->addr.preind && !info->addr.postind) | |
6858 | || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2 | |
6859 | && info->addr.writeback)) | |
6860 | { | |
6861 | set_syntax_error (_("invalid addressing mode")); | |
6862 | goto failure; | |
6863 | } | |
6864 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
6865 | { | |
6866 | set_syntax_error (_("relocation not allowed")); | |
6867 | goto failure; | |
6868 | } | |
6869 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, | |
6870 | /* addr_off_p */ 1, | |
6871 | /* need_libopcodes_p */ 1, | |
6872 | /* skip_p */ 0); | |
6873 | break; | |
6874 | ||
3f06e550 | 6875 | case AARCH64_OPND_ADDR_SIMM10: |
f42f1a1d | 6876 | case AARCH64_OPND_ADDR_OFFSET: |
3f06e550 SN |
6877 | po_misc_or_fail (parse_address (&str, info)); |
6878 | if (info->addr.pcrel || info->addr.offset.is_reg | |
6879 | || !info->addr.preind || info->addr.postind) | |
6880 | { | |
6881 | set_syntax_error (_("invalid addressing mode")); | |
6882 | goto failure; | |
6883 | } | |
6884 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
6885 | { | |
6886 | set_syntax_error (_("relocation not allowed")); | |
6887 | goto failure; | |
6888 | } | |
6889 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, | |
6890 | /* addr_off_p */ 1, | |
6891 | /* need_libopcodes_p */ 1, | |
6892 | /* skip_p */ 0); | |
6893 | break; | |
6894 | ||
08da6e93 SP |
6895 | case AARCH64_OPND_CAPADDR_UIMM9: |
6896 | po_misc_or_fail (parse_cap_address (&str, info, opcode->iclass)); | |
cd0042b3 | 6897 | goto addr_uimm; |
08da6e93 | 6898 | |
a06ea964 | 6899 | case AARCH64_OPND_ADDR_UIMM12: |
73866052 | 6900 | po_misc_or_fail (parse_address (&str, info)); |
cd0042b3 | 6901 | addr_uimm: |
a06ea964 NC |
6902 | if (info->addr.pcrel || info->addr.offset.is_reg |
6903 | || !info->addr.preind || info->addr.writeback) | |
6904 | { | |
6905 | set_syntax_error (_("invalid addressing mode")); | |
6906 | goto failure; | |
6907 | } | |
6908 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
6909 | aarch64_set_gas_internal_fixup (&inst.reloc, info, 1); | |
4c562523 JW |
6910 | else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12 |
6911 | || (inst.reloc.type | |
6912 | == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12) | |
6913 | || (inst.reloc.type | |
84f1b9fb RL |
6914 | == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC) |
6915 | || (inst.reloc.type | |
6916 | == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12) | |
6917 | || (inst.reloc.type | |
6918 | == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC)) | |
d2beed31 SP |
6919 | { |
6920 | /* The altbase ldrb instruction does not have enough range to | |
6921 | accommodate a LO12 relocation. */ | |
6922 | if (opcode->flags & F_NOSHIFT && opcode->iclass == ldst_altbase) | |
6923 | { | |
6924 | set_syntax_error (_("relocation not allowed")); | |
6925 | goto failure; | |
6926 | } | |
6927 | ||
6928 | inst.reloc.type = ldst_lo12_determine_real_reloc_type (); | |
6929 | } | |
4ca9b406 SP |
6930 | else if ((inst.reloc.type == BFD_RELOC_AARCH64_LD_GOT_LO12_NC |
6931 | || inst.reloc.type == BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC) | |
a1bdea65 SP |
6932 | && inst.base.operands[0].qualifier == AARCH64_OPND_QLF_CA) |
6933 | inst.reloc.flags = FIXUP_F_C64; | |
d2beed31 | 6934 | |
a06ea964 NC |
6935 | /* Leave qualifier to be determined by libopcodes. */ |
6936 | break; | |
6937 | ||
6938 | case AARCH64_OPND_SIMD_ADDR_POST: | |
6939 | /* [<Xn|SP>], <Xm|#<amount>> */ | |
73866052 | 6940 | po_misc_or_fail (parse_address (&str, info)); |
a06ea964 NC |
6941 | if (!info->addr.postind || !info->addr.writeback) |
6942 | { | |
6943 | set_syntax_error (_("invalid addressing mode")); | |
6944 | goto failure; | |
6945 | } | |
6946 | if (!info->addr.offset.is_reg) | |
6947 | { | |
6948 | if (inst.reloc.exp.X_op == O_constant) | |
6949 | info->addr.offset.imm = inst.reloc.exp.X_add_number; | |
6950 | else | |
6951 | { | |
6952 | set_fatal_syntax_error | |
ab3b8fcf | 6953 | (_("writeback value must be an immediate constant")); |
a06ea964 NC |
6954 | goto failure; |
6955 | } | |
6956 | } | |
6957 | /* No qualifier. */ | |
6958 | break; | |
6959 | ||
582e12bf | 6960 | case AARCH64_OPND_SVE_ADDR_RI_S4x16: |
8382113f | 6961 | case AARCH64_OPND_SVE_ADDR_RI_S4x32: |
98907a70 RS |
6962 | case AARCH64_OPND_SVE_ADDR_RI_S4xVL: |
6963 | case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL: | |
6964 | case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL: | |
6965 | case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL: | |
6966 | case AARCH64_OPND_SVE_ADDR_RI_S6xVL: | |
6967 | case AARCH64_OPND_SVE_ADDR_RI_S9xVL: | |
4df068de RS |
6968 | case AARCH64_OPND_SVE_ADDR_RI_U6: |
6969 | case AARCH64_OPND_SVE_ADDR_RI_U6x2: | |
6970 | case AARCH64_OPND_SVE_ADDR_RI_U6x4: | |
6971 | case AARCH64_OPND_SVE_ADDR_RI_U6x8: | |
98907a70 RS |
6972 | /* [X<n>{, #imm, MUL VL}] |
6973 | [X<n>{, #imm}] | |
4df068de RS |
6974 | but recognizing SVE registers. */ |
6975 | po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, | |
6976 | &offset_qualifier)); | |
6977 | if (base_qualifier != AARCH64_OPND_QLF_X) | |
6978 | { | |
6979 | set_syntax_error (_("invalid addressing mode")); | |
6980 | goto failure; | |
6981 | } | |
6982 | sve_regimm: | |
6983 | if (info->addr.pcrel || info->addr.offset.is_reg | |
6984 | || !info->addr.preind || info->addr.writeback) | |
6985 | { | |
6986 | set_syntax_error (_("invalid addressing mode")); | |
6987 | goto failure; | |
6988 | } | |
6989 | if (inst.reloc.type != BFD_RELOC_UNUSED | |
6990 | || inst.reloc.exp.X_op != O_constant) | |
6991 | { | |
6992 | /* Make sure this has priority over | |
6993 | "invalid addressing mode". */ | |
6994 | set_fatal_syntax_error (_("constant offset required")); | |
6995 | goto failure; | |
6996 | } | |
6997 | info->addr.offset.imm = inst.reloc.exp.X_add_number; | |
6998 | break; | |
6999 | ||
c8d59609 NC |
7000 | case AARCH64_OPND_SVE_ADDR_R: |
7001 | /* [<Xn|SP>{, <R><m>}] | |
7002 | but recognizing SVE registers. */ | |
7003 | po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, | |
7004 | &offset_qualifier)); | |
7005 | if (offset_qualifier == AARCH64_OPND_QLF_NIL) | |
7006 | { | |
7007 | offset_qualifier = AARCH64_OPND_QLF_X; | |
7008 | info->addr.offset.is_reg = 1; | |
7009 | info->addr.offset.regno = 31; | |
7010 | } | |
7011 | else if (base_qualifier != AARCH64_OPND_QLF_X | |
7012 | || offset_qualifier != AARCH64_OPND_QLF_X) | |
7013 | { | |
7014 | set_syntax_error (_("invalid addressing mode")); | |
7015 | goto failure; | |
7016 | } | |
7017 | goto regoff_addr; | |
7018 | ||
4df068de RS |
7019 | case AARCH64_OPND_SVE_ADDR_RR: |
7020 | case AARCH64_OPND_SVE_ADDR_RR_LSL1: | |
7021 | case AARCH64_OPND_SVE_ADDR_RR_LSL2: | |
7022 | case AARCH64_OPND_SVE_ADDR_RR_LSL3: | |
7023 | case AARCH64_OPND_SVE_ADDR_RX: | |
7024 | case AARCH64_OPND_SVE_ADDR_RX_LSL1: | |
7025 | case AARCH64_OPND_SVE_ADDR_RX_LSL2: | |
7026 | case AARCH64_OPND_SVE_ADDR_RX_LSL3: | |
7027 | /* [<Xn|SP>, <R><m>{, lsl #<amount>}] | |
7028 | but recognizing SVE registers. */ | |
7029 | po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, | |
7030 | &offset_qualifier)); | |
7031 | if (base_qualifier != AARCH64_OPND_QLF_X | |
7032 | || offset_qualifier != AARCH64_OPND_QLF_X) | |
7033 | { | |
7034 | set_syntax_error (_("invalid addressing mode")); | |
7035 | goto failure; | |
7036 | } | |
7037 | goto regoff_addr; | |
7038 | ||
7039 | case AARCH64_OPND_SVE_ADDR_RZ: | |
7040 | case AARCH64_OPND_SVE_ADDR_RZ_LSL1: | |
7041 | case AARCH64_OPND_SVE_ADDR_RZ_LSL2: | |
7042 | case AARCH64_OPND_SVE_ADDR_RZ_LSL3: | |
7043 | case AARCH64_OPND_SVE_ADDR_RZ_XTW_14: | |
7044 | case AARCH64_OPND_SVE_ADDR_RZ_XTW_22: | |
7045 | case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14: | |
7046 | case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22: | |
7047 | case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14: | |
7048 | case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22: | |
7049 | case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14: | |
7050 | case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22: | |
7051 | /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}] | |
7052 | [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */ | |
7053 | po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, | |
7054 | &offset_qualifier)); | |
7055 | if (base_qualifier != AARCH64_OPND_QLF_X | |
7056 | || (offset_qualifier != AARCH64_OPND_QLF_S_S | |
7057 | && offset_qualifier != AARCH64_OPND_QLF_S_D)) | |
7058 | { | |
7059 | set_syntax_error (_("invalid addressing mode")); | |
7060 | goto failure; | |
7061 | } | |
7062 | info->qualifier = offset_qualifier; | |
7063 | goto regoff_addr; | |
7064 | ||
c469c864 MM |
7065 | case AARCH64_OPND_SVE_ADDR_ZX: |
7066 | /* [Zn.<T>{, <Xm>}]. */ | |
7067 | po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, | |
7068 | &offset_qualifier)); | |
7069 | /* Things to check: | |
7070 | base_qualifier either S_S or S_D | |
7071 | offset_qualifier must be X | |
7072 | */ | |
7073 | if ((base_qualifier != AARCH64_OPND_QLF_S_S | |
7074 | && base_qualifier != AARCH64_OPND_QLF_S_D) | |
7075 | || offset_qualifier != AARCH64_OPND_QLF_X) | |
7076 | { | |
7077 | set_syntax_error (_("invalid addressing mode")); | |
7078 | goto failure; | |
7079 | } | |
7080 | info->qualifier = base_qualifier; | |
7081 | if (!info->addr.offset.is_reg || info->addr.pcrel | |
7082 | || !info->addr.preind || info->addr.writeback | |
7083 | || info->shifter.operator_present != 0) | |
7084 | { | |
7085 | set_syntax_error (_("invalid addressing mode")); | |
7086 | goto failure; | |
7087 | } | |
7088 | info->shifter.kind = AARCH64_MOD_LSL; | |
7089 | break; | |
7090 | ||
7091 | ||
4df068de RS |
7092 | case AARCH64_OPND_SVE_ADDR_ZI_U5: |
7093 | case AARCH64_OPND_SVE_ADDR_ZI_U5x2: | |
7094 | case AARCH64_OPND_SVE_ADDR_ZI_U5x4: | |
7095 | case AARCH64_OPND_SVE_ADDR_ZI_U5x8: | |
7096 | /* [Z<n>.<T>{, #imm}] */ | |
7097 | po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, | |
7098 | &offset_qualifier)); | |
7099 | if (base_qualifier != AARCH64_OPND_QLF_S_S | |
7100 | && base_qualifier != AARCH64_OPND_QLF_S_D) | |
7101 | { | |
7102 | set_syntax_error (_("invalid addressing mode")); | |
7103 | goto failure; | |
7104 | } | |
7105 | info->qualifier = base_qualifier; | |
7106 | goto sve_regimm; | |
7107 | ||
7108 | case AARCH64_OPND_SVE_ADDR_ZZ_LSL: | |
7109 | case AARCH64_OPND_SVE_ADDR_ZZ_SXTW: | |
7110 | case AARCH64_OPND_SVE_ADDR_ZZ_UXTW: | |
7111 | /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}] | |
7112 | [Z<n>.D, Z<m>.D, <extend> {#<amount>}] | |
7113 | ||
7114 | We don't reject: | |
7115 | ||
7116 | [Z<n>.S, Z<m>.S, <extend> {#<amount>}] | |
7117 | ||
7118 | here since we get better error messages by leaving it to | |
7119 | the qualifier checking routines. */ | |
7120 | po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, | |
7121 | &offset_qualifier)); | |
7122 | if ((base_qualifier != AARCH64_OPND_QLF_S_S | |
7123 | && base_qualifier != AARCH64_OPND_QLF_S_D) | |
7124 | || offset_qualifier != base_qualifier) | |
7125 | { | |
7126 | set_syntax_error (_("invalid addressing mode")); | |
7127 | goto failure; | |
7128 | } | |
7129 | info->qualifier = base_qualifier; | |
7130 | goto regoff_addr; | |
7131 | ||
a06ea964 | 7132 | case AARCH64_OPND_SYSREG: |
7d02540a TC |
7133 | { |
7134 | uint32_t sysreg_flags; | |
801f0a7d SP |
7135 | |
7136 | if ((val = parse_sys_reg (opcode, &str, aarch64_sys_regs_hsh, 1, 0, | |
7d02540a TC |
7137 | &sysreg_flags)) == PARSE_FAIL) |
7138 | { | |
7139 | set_syntax_error (_("unknown or missing system register name")); | |
7140 | goto failure; | |
7141 | } | |
7142 | inst.base.operands[i].sysreg.value = val; | |
7143 | inst.base.operands[i].sysreg.flags = sysreg_flags; | |
7144 | break; | |
7145 | } | |
a06ea964 NC |
7146 | |
7147 | case AARCH64_OPND_PSTATEFIELD: | |
801f0a7d SP |
7148 | if ((val = parse_sys_reg (opcode, &str, aarch64_pstatefield_hsh, 0, 1, |
7149 | NULL)) | |
a3251895 | 7150 | == PARSE_FAIL) |
a06ea964 NC |
7151 | { |
7152 | set_syntax_error (_("unknown or missing PSTATE field name")); | |
7153 | goto failure; | |
7154 | } | |
7155 | inst.base.operands[i].pstatefield = val; | |
7156 | break; | |
7157 | ||
7158 | case AARCH64_OPND_SYSREG_IC: | |
7159 | inst.base.operands[i].sysins_op = | |
7160 | parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh); | |
7161 | goto sys_reg_ins; | |
2ac435d4 | 7162 | |
a06ea964 NC |
7163 | case AARCH64_OPND_SYSREG_DC: |
7164 | inst.base.operands[i].sysins_op = | |
7165 | parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh); | |
7166 | goto sys_reg_ins; | |
2ac435d4 | 7167 | |
a06ea964 NC |
7168 | case AARCH64_OPND_SYSREG_AT: |
7169 | inst.base.operands[i].sysins_op = | |
7170 | parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh); | |
7171 | goto sys_reg_ins; | |
2ac435d4 SD |
7172 | |
7173 | case AARCH64_OPND_SYSREG_SR: | |
7174 | inst.base.operands[i].sysins_op = | |
7175 | parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh); | |
7176 | goto sys_reg_ins; | |
7177 | ||
a06ea964 NC |
7178 | case AARCH64_OPND_SYSREG_TLBI: |
7179 | inst.base.operands[i].sysins_op = | |
7180 | parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh); | |
dc1e8a47 | 7181 | sys_reg_ins: |
a06ea964 NC |
7182 | if (inst.base.operands[i].sysins_op == NULL) |
7183 | { | |
7184 | set_fatal_syntax_error ( _("unknown or missing operation name")); | |
7185 | goto failure; | |
7186 | } | |
7187 | break; | |
7188 | ||
7189 | case AARCH64_OPND_BARRIER: | |
7190 | case AARCH64_OPND_BARRIER_ISB: | |
7191 | val = parse_barrier (&str); | |
7192 | if (val != PARSE_FAIL | |
7193 | && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf) | |
7194 | { | |
7195 | /* ISB only accepts options name 'sy'. */ | |
7196 | set_syntax_error | |
7197 | (_("the specified option is not accepted in ISB")); | |
7198 | /* Turn off backtrack as this optional operand is present. */ | |
7199 | backtrack_pos = 0; | |
7200 | goto failure; | |
7201 | } | |
7202 | /* This is an extension to accept a 0..15 immediate. */ | |
7203 | if (val == PARSE_FAIL) | |
7204 | po_imm_or_fail (0, 15); | |
7205 | info->barrier = aarch64_barrier_options + val; | |
7206 | break; | |
7207 | ||
7208 | case AARCH64_OPND_PRFOP: | |
7209 | val = parse_pldop (&str); | |
7210 | /* This is an extension to accept a 0..31 immediate. */ | |
7211 | if (val == PARSE_FAIL) | |
7212 | po_imm_or_fail (0, 31); | |
7213 | inst.base.operands[i].prfop = aarch64_prfops + val; | |
7214 | break; | |
7215 | ||
1e6f4800 MW |
7216 | case AARCH64_OPND_BARRIER_PSB: |
7217 | val = parse_barrier_psb (&str, &(info->hint_option)); | |
7218 | if (val == PARSE_FAIL) | |
7219 | goto failure; | |
7220 | break; | |
7221 | ||
ff605452 SD |
7222 | case AARCH64_OPND_BTI_TARGET: |
7223 | val = parse_bti_operand (&str, &(info->hint_option)); | |
7224 | if (val == PARSE_FAIL) | |
7225 | goto failure; | |
7226 | break; | |
7227 | ||
a06ea964 NC |
7228 | default: |
7229 | as_fatal (_("unhandled operand code %d"), operands[i]); | |
7230 | } | |
7231 | ||
7232 | /* If we get here, this operand was successfully parsed. */ | |
7233 | inst.base.operands[i].present = 1; | |
7234 | continue; | |
7235 | ||
dc1e8a47 | 7236 | failure: |
a06ea964 NC |
7237 | /* The parse routine should already have set the error, but in case |
7238 | not, set a default one here. */ | |
7239 | if (! error_p ()) | |
7240 | set_default_error (); | |
7241 | ||
7242 | if (! backtrack_pos) | |
7243 | goto parse_operands_return; | |
7244 | ||
f4c51f60 JW |
7245 | { |
7246 | /* We reach here because this operand is marked as optional, and | |
7247 | either no operand was supplied or the operand was supplied but it | |
7248 | was syntactically incorrect. In the latter case we report an | |
7249 | error. In the former case we perform a few more checks before | |
7250 | dropping through to the code to insert the default operand. */ | |
7251 | ||
7252 | char *tmp = backtrack_pos; | |
7253 | char endchar = END_OF_INSN; | |
7254 | ||
7255 | if (i != (aarch64_num_of_operands (opcode) - 1)) | |
7256 | endchar = ','; | |
7257 | skip_past_char (&tmp, ','); | |
7258 | ||
7259 | if (*tmp != endchar) | |
7260 | /* The user has supplied an operand in the wrong format. */ | |
7261 | goto parse_operands_return; | |
7262 | ||
7263 | /* Make sure there is not a comma before the optional operand. | |
7264 | For example the fifth operand of 'sys' is optional: | |
7265 | ||
7266 | sys #0,c0,c0,#0, <--- wrong | |
7267 | sys #0,c0,c0,#0 <--- correct. */ | |
7268 | if (comma_skipped_p && i && endchar == END_OF_INSN) | |
7269 | { | |
7270 | set_fatal_syntax_error | |
7271 | (_("unexpected comma before the omitted optional operand")); | |
7272 | goto parse_operands_return; | |
7273 | } | |
7274 | } | |
7275 | ||
a06ea964 NC |
7276 | /* Reaching here means we are dealing with an optional operand that is |
7277 | omitted from the assembly line. */ | |
7278 | gas_assert (optional_operand_p (opcode, i)); | |
7279 | info->present = 0; | |
7280 | process_omitted_operand (operands[i], opcode, i, info); | |
7281 | ||
7282 | /* Try again, skipping the optional operand at backtrack_pos. */ | |
7283 | str = backtrack_pos; | |
7284 | backtrack_pos = 0; | |
7285 | ||
a06ea964 NC |
7286 | /* Clear any error record after the omitted optional operand has been |
7287 | successfully handled. */ | |
7288 | clear_error (); | |
7289 | } | |
7290 | ||
7291 | /* Check if we have parsed all the operands. */ | |
7292 | if (*str != '\0' && ! error_p ()) | |
7293 | { | |
7294 | /* Set I to the index of the last present operand; this is | |
7295 | for the purpose of diagnostics. */ | |
7296 | for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i) | |
7297 | ; | |
7298 | set_fatal_syntax_error | |
7299 | (_("unexpected characters following instruction")); | |
7300 | } | |
7301 | ||
dc1e8a47 | 7302 | parse_operands_return: |
a06ea964 NC |
7303 | |
7304 | if (error_p ()) | |
7305 | { | |
7306 | DEBUG_TRACE ("parsing FAIL: %s - %s", | |
7307 | operand_mismatch_kind_names[get_error_kind ()], | |
7308 | get_error_message ()); | |
7309 | /* Record the operand error properly; this is useful when there | |
7310 | are multiple instruction templates for a mnemonic name, so that | |
7311 | later on, we can select the error that most closely describes | |
7312 | the problem. */ | |
7313 | record_operand_error (opcode, i, get_error_kind (), | |
7314 | get_error_message ()); | |
7315 | return FALSE; | |
7316 | } | |
7317 | else | |
7318 | { | |
7319 | DEBUG_TRACE ("parsing SUCCESS"); | |
7320 | return TRUE; | |
7321 | } | |
7322 | } | |
7323 | ||
7324 | /* It does some fix-up to provide some programmer friendly feature while | |
7325 | keeping the libopcodes happy, i.e. libopcodes only accepts | |
7326 | the preferred architectural syntax. | |
7327 | Return FALSE if there is any failure; otherwise return TRUE. */ | |
7328 | ||
7329 | static bfd_boolean | |
7330 | programmer_friendly_fixup (aarch64_instruction *instr) | |
7331 | { | |
7332 | aarch64_inst *base = &instr->base; | |
7333 | const aarch64_opcode *opcode = base->opcode; | |
7334 | enum aarch64_op op = opcode->op; | |
7335 | aarch64_opnd_info *operands = base->operands; | |
7336 | ||
7337 | DEBUG_TRACE ("enter"); | |
7338 | ||
7339 | switch (opcode->iclass) | |
7340 | { | |
7341 | case testbranch: | |
7342 | /* TBNZ Xn|Wn, #uimm6, label | |
7343 | Test and Branch Not Zero: conditionally jumps to label if bit number | |
7344 | uimm6 in register Xn is not zero. The bit number implies the width of | |
7345 | the register, which may be written and should be disassembled as Wn if | |
7346 | uimm is less than 32. */ | |
7347 | if (operands[0].qualifier == AARCH64_OPND_QLF_W) | |
7348 | { | |
7349 | if (operands[1].imm.value >= 32) | |
7350 | { | |
7351 | record_operand_out_of_range_error (opcode, 1, _("immediate value"), | |
7352 | 0, 31); | |
7353 | return FALSE; | |
7354 | } | |
7355 | operands[0].qualifier = AARCH64_OPND_QLF_X; | |
7356 | } | |
7357 | break; | |
7358 | case loadlit: | |
7359 | /* LDR Wt, label | =value | |
7360 | As a convenience assemblers will typically permit the notation | |
7361 | "=value" in conjunction with the pc-relative literal load instructions | |
7362 | to automatically place an immediate value or symbolic address in a | |
7363 | nearby literal pool and generate a hidden label which references it. | |
7364 | ISREG has been set to 0 in the case of =value. */ | |
7365 | if (instr->gen_lit_pool | |
f7d2c675 SP |
7366 | && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT |
7367 | || op == OP_LDR_LIT_2)) | |
a06ea964 NC |
7368 | { |
7369 | int size = aarch64_get_qualifier_esize (operands[0].qualifier); | |
7370 | if (op == OP_LDRSW_LIT) | |
7371 | size = 4; | |
7372 | if (instr->reloc.exp.X_op != O_constant | |
67a32447 | 7373 | && instr->reloc.exp.X_op != O_big |
a06ea964 NC |
7374 | && instr->reloc.exp.X_op != O_symbol) |
7375 | { | |
7376 | record_operand_error (opcode, 1, | |
7377 | AARCH64_OPDE_FATAL_SYNTAX_ERROR, | |
7378 | _("constant expression expected")); | |
7379 | return FALSE; | |
7380 | } | |
7381 | if (! add_to_lit_pool (&instr->reloc.exp, size)) | |
7382 | { | |
7383 | record_operand_error (opcode, 1, | |
7384 | AARCH64_OPDE_OTHER_ERROR, | |
7385 | _("literal pool insertion failed")); | |
7386 | return FALSE; | |
7387 | } | |
7388 | } | |
7389 | break; | |
a06ea964 NC |
7390 | case log_shift: |
7391 | case bitfield: | |
7392 | /* UXT[BHW] Wd, Wn | |
7393 | Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias | |
7394 | for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is | |
7395 | encoded using ORR Wd, WZR, Wn (MOV Wd,Wn). | |
7396 | A programmer-friendly assembler should accept a destination Xd in | |
7397 | place of Wd, however that is not the preferred form for disassembly. | |
7398 | */ | |
7399 | if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW) | |
7400 | && operands[1].qualifier == AARCH64_OPND_QLF_W | |
7401 | && operands[0].qualifier == AARCH64_OPND_QLF_X) | |
7402 | operands[0].qualifier = AARCH64_OPND_QLF_W; | |
7403 | break; | |
7404 | ||
7405 | case addsub_ext: | |
7406 | { | |
7407 | /* In the 64-bit form, the final register operand is written as Wm | |
7408 | for all but the (possibly omitted) UXTX/LSL and SXTX | |
7409 | operators. | |
7410 | As a programmer-friendly assembler, we accept e.g. | |
7411 | ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to | |
7412 | ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */ | |
7413 | int idx = aarch64_operand_index (opcode->operands, | |
7414 | AARCH64_OPND_Rm_EXT); | |
7415 | gas_assert (idx == 1 || idx == 2); | |
7416 | if (operands[0].qualifier == AARCH64_OPND_QLF_X | |
7417 | && operands[idx].qualifier == AARCH64_OPND_QLF_X | |
7418 | && operands[idx].shifter.kind != AARCH64_MOD_LSL | |
7419 | && operands[idx].shifter.kind != AARCH64_MOD_UXTX | |
7420 | && operands[idx].shifter.kind != AARCH64_MOD_SXTX) | |
7421 | operands[idx].qualifier = AARCH64_OPND_QLF_W; | |
7422 | } | |
7423 | break; | |
7424 | ||
7425 | default: | |
7426 | break; | |
7427 | } | |
7428 | ||
7429 | DEBUG_TRACE ("exit with SUCCESS"); | |
7430 | return TRUE; | |
7431 | } | |
7432 | ||
5c47e525 | 7433 | /* Check for loads and stores that will cause unpredictable behavior. */ |
54a28c4c JW |
7434 | |
7435 | static void | |
7436 | warn_unpredictable_ldst (aarch64_instruction *instr, char *str) | |
7437 | { | |
7438 | aarch64_inst *base = &instr->base; | |
7439 | const aarch64_opcode *opcode = base->opcode; | |
7440 | const aarch64_opnd_info *opnds = base->operands; | |
7441 | switch (opcode->iclass) | |
7442 | { | |
7443 | case ldst_pos: | |
7444 | case ldst_imm9: | |
3f06e550 | 7445 | case ldst_imm10: |
54a28c4c JW |
7446 | case ldst_unscaled: |
7447 | case ldst_unpriv: | |
5c47e525 RE |
7448 | /* Loading/storing the base register is unpredictable if writeback. */ |
7449 | if ((aarch64_get_operand_class (opnds[0].type) | |
7450 | == AARCH64_OPND_CLASS_INT_REG) | |
7451 | && opnds[0].reg.regno == opnds[1].addr.base_regno | |
4bf8c6e8 | 7452 | && opnds[1].addr.base_regno != REG_SP |
69105ce4 SD |
7453 | /* Exempt STG/STZG/ST2G/STZ2G. */ |
7454 | && !(opnds[1].type == AARCH64_OPND_ADDR_SIMM13) | |
54a28c4c | 7455 | && opnds[1].addr.writeback) |
5c47e525 | 7456 | as_warn (_("unpredictable transfer with writeback -- `%s'"), str); |
54a28c4c | 7457 | break; |
503ba600 | 7458 | |
54a28c4c JW |
7459 | case ldstpair_off: |
7460 | case ldstnapair_offs: | |
7461 | case ldstpair_indexed: | |
5c47e525 RE |
7462 | /* Loading/storing the base register is unpredictable if writeback. */ |
7463 | if ((aarch64_get_operand_class (opnds[0].type) | |
7464 | == AARCH64_OPND_CLASS_INT_REG) | |
7465 | && (opnds[0].reg.regno == opnds[2].addr.base_regno | |
7466 | || opnds[1].reg.regno == opnds[2].addr.base_regno) | |
4bf8c6e8 | 7467 | && opnds[2].addr.base_regno != REG_SP |
fb3265b3 SD |
7468 | /* Exempt STGP. */ |
7469 | && !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11) | |
54a28c4c | 7470 | && opnds[2].addr.writeback) |
5c47e525 RE |
7471 | as_warn (_("unpredictable transfer with writeback -- `%s'"), str); |
7472 | /* Load operations must load different registers. */ | |
54a28c4c JW |
7473 | if ((opcode->opcode & (1 << 22)) |
7474 | && opnds[0].reg.regno == opnds[1].reg.regno) | |
7475 | as_warn (_("unpredictable load of register pair -- `%s'"), str); | |
7476 | break; | |
ee943970 RR |
7477 | |
7478 | case ldstexcl: | |
7479 | /* It is unpredictable if the destination and status registers are the | |
7480 | same. */ | |
7481 | if ((aarch64_get_operand_class (opnds[0].type) | |
7482 | == AARCH64_OPND_CLASS_INT_REG) | |
7483 | && (aarch64_get_operand_class (opnds[1].type) | |
e9af8aad SP |
7484 | == AARCH64_OPND_CLASS_INT_REG |
7485 | || (aarch64_get_operand_class (opnds[1].type) | |
7486 | == AARCH64_OPND_CLASS_CAP_REG)) | |
ee943970 RR |
7487 | && (opnds[0].reg.regno == opnds[1].reg.regno |
7488 | || opnds[0].reg.regno == opnds[2].reg.regno)) | |
7489 | as_warn (_("unpredictable: identical transfer and status registers" | |
7490 | " --`%s'"), | |
7491 | str); | |
7492 | ||
7493 | break; | |
7494 | ||
54a28c4c JW |
7495 | default: |
7496 | break; | |
7497 | } | |
7498 | } | |
7499 | ||
4f5d2536 TC |
7500 | static void |
7501 | force_automatic_sequence_close (void) | |
7502 | { | |
7503 | if (now_instr_sequence.instr) | |
7504 | { | |
7505 | as_warn (_("previous `%s' sequence has not been closed"), | |
7506 | now_instr_sequence.instr->opcode->name); | |
7507 | init_insn_sequence (NULL, &now_instr_sequence); | |
7508 | } | |
7509 | } | |
7510 | ||
a06ea964 NC |
7511 | /* A wrapper function to interface with libopcodes on encoding and |
7512 | record the error message if there is any. | |
7513 | ||
7514 | Return TRUE on success; otherwise return FALSE. */ | |
7515 | ||
7516 | static bfd_boolean | |
7517 | do_encode (const aarch64_opcode *opcode, aarch64_inst *instr, | |
7518 | aarch64_insn *code) | |
7519 | { | |
7520 | aarch64_operand_error error_info; | |
7d02540a | 7521 | memset (&error_info, '\0', sizeof (error_info)); |
a06ea964 | 7522 | error_info.kind = AARCH64_OPDE_NIL; |
3979cf50 SP |
7523 | if (aarch64_opcode_encode (cpu_variant, opcode, instr, code, NULL, |
7524 | &error_info, insn_sequence) | |
7d02540a | 7525 | && !error_info.non_fatal) |
a06ea964 | 7526 | return TRUE; |
7d02540a TC |
7527 | |
7528 | gas_assert (error_info.kind != AARCH64_OPDE_NIL); | |
7529 | record_operand_error_info (opcode, &error_info); | |
7530 | return error_info.non_fatal; | |
a06ea964 NC |
7531 | } |
7532 | ||
7533 | #ifdef DEBUG_AARCH64 | |
7534 | static inline void | |
7535 | dump_opcode_operands (const aarch64_opcode *opcode) | |
7536 | { | |
7537 | int i = 0; | |
7538 | while (opcode->operands[i] != AARCH64_OPND_NIL) | |
7539 | { | |
7540 | aarch64_verbose ("\t\t opnd%d: %s", i, | |
7541 | aarch64_get_operand_name (opcode->operands[i])[0] != '\0' | |
7542 | ? aarch64_get_operand_name (opcode->operands[i]) | |
7543 | : aarch64_get_operand_desc (opcode->operands[i])); | |
7544 | ++i; | |
7545 | } | |
7546 | } | |
7547 | #endif /* DEBUG_AARCH64 */ | |
7548 | ||
7549 | /* This is the guts of the machine-dependent assembler. STR points to a | |
7550 | machine dependent instruction. This function is supposed to emit | |
7551 | the frags/bytes it assembles to. */ | |
7552 | ||
7553 | void | |
7554 | md_assemble (char *str) | |
7555 | { | |
7556 | char *p = str; | |
7557 | templates *template; | |
7558 | aarch64_opcode *opcode; | |
7559 | aarch64_inst *inst_base; | |
7560 | unsigned saved_cond; | |
7561 | ||
7562 | /* Align the previous label if needed. */ | |
7563 | if (last_label_seen != NULL) | |
7564 | { | |
7565 | symbol_set_frag (last_label_seen, frag_now); | |
7566 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
7567 | S_SET_SEGMENT (last_label_seen, now_seg); | |
7568 | } | |
7569 | ||
7e84b55d TC |
7570 | /* Update the current insn_sequence from the segment. */ |
7571 | insn_sequence = &seg_info (now_seg)->tc_segment_info_data.insn_sequence; | |
7572 | ||
a06ea964 NC |
7573 | inst.reloc.type = BFD_RELOC_UNUSED; |
7574 | ||
7575 | DEBUG_TRACE ("\n\n"); | |
7576 | DEBUG_TRACE ("=============================="); | |
7577 | DEBUG_TRACE ("Enter md_assemble with %s", str); | |
7578 | ||
7579 | template = opcode_lookup (&p); | |
7580 | if (!template) | |
7581 | { | |
7582 | /* It wasn't an instruction, but it might be a register alias of | |
7583 | the form alias .req reg directive. */ | |
7584 | if (!create_register_alias (str, p)) | |
7585 | as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str), | |
7586 | str); | |
7587 | return; | |
7588 | } | |
7589 | ||
7590 | skip_whitespace (p); | |
7591 | if (*p == ',') | |
7592 | { | |
7593 | as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"), | |
7594 | get_mnemonic_name (str), str); | |
7595 | return; | |
7596 | } | |
7597 | ||
7598 | init_operand_error_report (); | |
7599 | ||
eb9d6cc9 RL |
7600 | /* Sections are assumed to start aligned. In executable section, there is no |
7601 | MAP_DATA symbol pending. So we only align the address during | |
3979cf50 | 7602 | MAP_DATA --> MAP_CUR_INSN transition. |
eb9d6cc9 RL |
7603 | For other sections, this is not guaranteed. */ |
7604 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; | |
7605 | if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA) | |
7606 | frag_align_code (2, 0); | |
7607 | ||
a06ea964 NC |
7608 | saved_cond = inst.cond; |
7609 | reset_aarch64_instruction (&inst); | |
7610 | inst.cond = saved_cond; | |
7611 | ||
7612 | /* Iterate through all opcode entries with the same mnemonic name. */ | |
7613 | do | |
7614 | { | |
7615 | opcode = template->opcode; | |
7616 | ||
7617 | DEBUG_TRACE ("opcode %s found", opcode->name); | |
7618 | #ifdef DEBUG_AARCH64 | |
7619 | if (debug_dump) | |
7620 | dump_opcode_operands (opcode); | |
7621 | #endif /* DEBUG_AARCH64 */ | |
7622 | ||
3979cf50 | 7623 | mapping_state (MAP_CUR_INSN); |
a06ea964 NC |
7624 | |
7625 | inst_base = &inst.base; | |
7626 | inst_base->opcode = opcode; | |
7627 | ||
7628 | /* Truly conditionally executed instructions, e.g. b.cond. */ | |
7629 | if (opcode->flags & F_COND) | |
7630 | { | |
7631 | gas_assert (inst.cond != COND_ALWAYS); | |
7632 | inst_base->cond = get_cond_from_value (inst.cond); | |
7633 | DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]); | |
7634 | } | |
7635 | else if (inst.cond != COND_ALWAYS) | |
7636 | { | |
7637 | /* It shouldn't arrive here, where the assembly looks like a | |
7638 | conditional instruction but the found opcode is unconditional. */ | |
7639 | gas_assert (0); | |
7640 | continue; | |
7641 | } | |
7642 | ||
7643 | if (parse_operands (p, opcode) | |
7644 | && programmer_friendly_fixup (&inst) | |
7645 | && do_encode (inst_base->opcode, &inst.base, &inst_base->value)) | |
7646 | { | |
3f06bfce YZ |
7647 | /* Check that this instruction is supported for this CPU. */ |
7648 | if (!opcode->avariant | |
93d8990c | 7649 | || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant)) |
3f06bfce YZ |
7650 | { |
7651 | as_bad (_("selected processor does not support `%s'"), str); | |
7652 | return; | |
7653 | } | |
7654 | ||
54a28c4c JW |
7655 | warn_unpredictable_ldst (&inst, str); |
7656 | ||
a06ea964 NC |
7657 | if (inst.reloc.type == BFD_RELOC_UNUSED |
7658 | || !inst.reloc.need_libopcodes_p) | |
7659 | output_inst (NULL); | |
7660 | else | |
7661 | { | |
7662 | /* If there is relocation generated for the instruction, | |
7663 | store the instruction information for the future fix-up. */ | |
7664 | struct aarch64_inst *copy; | |
7665 | gas_assert (inst.reloc.type != BFD_RELOC_UNUSED); | |
325801bd | 7666 | copy = XNEW (struct aarch64_inst); |
a06ea964 NC |
7667 | memcpy (copy, &inst.base, sizeof (struct aarch64_inst)); |
7668 | output_inst (copy); | |
7669 | } | |
7d02540a TC |
7670 | |
7671 | /* Issue non-fatal messages if any. */ | |
7672 | output_operand_error_report (str, TRUE); | |
a06ea964 NC |
7673 | return; |
7674 | } | |
7675 | ||
7676 | template = template->next; | |
7677 | if (template != NULL) | |
7678 | { | |
7679 | reset_aarch64_instruction (&inst); | |
7680 | inst.cond = saved_cond; | |
7681 | } | |
7682 | } | |
7683 | while (template != NULL); | |
7684 | ||
7685 | /* Issue the error messages if any. */ | |
7d02540a | 7686 | output_operand_error_report (str, FALSE); |
a06ea964 NC |
7687 | } |
7688 | ||
7689 | /* Various frobbings of labels and their addresses. */ | |
7690 | ||
7691 | void | |
7692 | aarch64_start_line_hook (void) | |
7693 | { | |
7694 | last_label_seen = NULL; | |
7695 | } | |
7696 | ||
7697 | void | |
7698 | aarch64_frob_label (symbolS * sym) | |
7699 | { | |
7700 | last_label_seen = sym; | |
7701 | ||
8b21361b | 7702 | AARCH64_SET_C64 (sym, IS_C64); |
d30dd5cf MM |
7703 | if (AARCH64_IS_C64 (sym) && S_IS_FUNCTION (sym)) |
7704 | *symbol_X_add_number (sym) += 1; | |
8b21361b | 7705 | |
a06ea964 NC |
7706 | dwarf2_emit_label (sym); |
7707 | } | |
7708 | ||
4f5d2536 TC |
7709 | void |
7710 | aarch64_frob_section (asection *sec ATTRIBUTE_UNUSED) | |
7711 | { | |
7712 | /* Check to see if we have a block to close. */ | |
7713 | force_automatic_sequence_close (); | |
7714 | } | |
7715 | ||
a06ea964 NC |
7716 | int |
7717 | aarch64_data_in_code (void) | |
7718 | { | |
7719 | if (!strncmp (input_line_pointer + 1, "data:", 5)) | |
7720 | { | |
7721 | *input_line_pointer = '/'; | |
7722 | input_line_pointer += 5; | |
7723 | *input_line_pointer = 0; | |
7724 | return 1; | |
7725 | } | |
7726 | ||
7727 | return 0; | |
7728 | } | |
7729 | ||
7730 | char * | |
7731 | aarch64_canonicalize_symbol_name (char *name) | |
7732 | { | |
7733 | int len; | |
7734 | ||
7735 | if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data")) | |
7736 | *(name + len - 5) = 0; | |
7737 | ||
7738 | return name; | |
7739 | } | |
7740 | \f | |
7741 | /* Table of all register names defined by default. The user can | |
7742 | define additional names with .req. Note that all register names | |
7743 | should appear in both upper and lowercase variants. Some registers | |
7744 | also have mixed-case names. */ | |
7745 | ||
7746 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE } | |
8975f864 | 7747 | #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE} |
a06ea964 | 7748 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
f11ad6bc | 7749 | #define REGSET16(p,t) \ |
a06ea964 NC |
7750 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ |
7751 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
7752 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
f11ad6bc RS |
7753 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) |
7754 | #define REGSET31(p,t) \ | |
7755 | REGSET16(p, t), \ | |
a06ea964 NC |
7756 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ |
7757 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
7758 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
7759 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t) | |
7760 | #define REGSET(p,t) \ | |
7761 | REGSET31(p,t), REGNUM(p,31,t) | |
7762 | ||
7763 | /* These go into aarch64_reg_hsh hash-table. */ | |
7764 | static const reg_entry reg_names[] = { | |
7765 | /* Integer registers. */ | |
7766 | REGSET31 (x, R_64), REGSET31 (X, R_64), | |
7767 | REGSET31 (w, R_32), REGSET31 (W, R_32), | |
7768 | ||
8975f864 | 7769 | REGDEF_ALIAS (ip0, 16, R_64), REGDEF_ALIAS (IP0, 16, R_64), |
f10e937a | 7770 | REGDEF_ALIAS (ip1, 17, R_64), REGDEF_ALIAS (IP1, 17, R_64), |
8975f864 RR |
7771 | REGDEF_ALIAS (fp, 29, R_64), REGDEF_ALIAS (FP, 29, R_64), |
7772 | REGDEF_ALIAS (lr, 30, R_64), REGDEF_ALIAS (LR, 30, R_64), | |
a06ea964 NC |
7773 | REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32), |
7774 | REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64), | |
7775 | ||
7776 | REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32), | |
7777 | REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64), | |
7778 | ||
3493da5c SP |
7779 | /* Capability Registers. */ |
7780 | REGSET31 (c, CA_N), REGSET31 (C, CA_N), | |
7781 | REGDEF (csp, 31, CA_SP), REGDEF (CSP, 31, CA_SP), | |
7782 | REGDEF (czr, 31, CA_Z), REGDEF (CZR, 31, CA_Z), | |
7783 | REGDEF (ddc, 33, CA_D), REGDEF (DDC, 33, CA_D), | |
7784 | REGDEF_ALIAS (clr, 30, CA_N), REGDEF_ALIAS (CLR, 30, CA_N), | |
7785 | ||
a06ea964 NC |
7786 | /* Floating-point single precision registers. */ |
7787 | REGSET (s, FP_S), REGSET (S, FP_S), | |
7788 | ||
7789 | /* Floating-point double precision registers. */ | |
7790 | REGSET (d, FP_D), REGSET (D, FP_D), | |
7791 | ||
7792 | /* Floating-point half precision registers. */ | |
7793 | REGSET (h, FP_H), REGSET (H, FP_H), | |
7794 | ||
7795 | /* Floating-point byte precision registers. */ | |
7796 | REGSET (b, FP_B), REGSET (B, FP_B), | |
7797 | ||
7798 | /* Floating-point quad precision registers. */ | |
7799 | REGSET (q, FP_Q), REGSET (Q, FP_Q), | |
7800 | ||
7801 | /* FP/SIMD registers. */ | |
7802 | REGSET (v, VN), REGSET (V, VN), | |
f11ad6bc RS |
7803 | |
7804 | /* SVE vector registers. */ | |
7805 | REGSET (z, ZN), REGSET (Z, ZN), | |
7806 | ||
7807 | /* SVE predicate registers. */ | |
7808 | REGSET16 (p, PN), REGSET16 (P, PN) | |
a06ea964 NC |
7809 | }; |
7810 | ||
7811 | #undef REGDEF | |
8975f864 | 7812 | #undef REGDEF_ALIAS |
a06ea964 | 7813 | #undef REGNUM |
f11ad6bc RS |
7814 | #undef REGSET16 |
7815 | #undef REGSET31 | |
a06ea964 NC |
7816 | #undef REGSET |
7817 | ||
7818 | #define N 1 | |
7819 | #define n 0 | |
7820 | #define Z 1 | |
7821 | #define z 0 | |
7822 | #define C 1 | |
7823 | #define c 0 | |
7824 | #define V 1 | |
7825 | #define v 0 | |
7826 | #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d)) | |
7827 | static const asm_nzcv nzcv_names[] = { | |
7828 | {"nzcv", B (n, z, c, v)}, | |
7829 | {"nzcV", B (n, z, c, V)}, | |
7830 | {"nzCv", B (n, z, C, v)}, | |
7831 | {"nzCV", B (n, z, C, V)}, | |
7832 | {"nZcv", B (n, Z, c, v)}, | |
7833 | {"nZcV", B (n, Z, c, V)}, | |
7834 | {"nZCv", B (n, Z, C, v)}, | |
7835 | {"nZCV", B (n, Z, C, V)}, | |
7836 | {"Nzcv", B (N, z, c, v)}, | |
7837 | {"NzcV", B (N, z, c, V)}, | |
7838 | {"NzCv", B (N, z, C, v)}, | |
7839 | {"NzCV", B (N, z, C, V)}, | |
7840 | {"NZcv", B (N, Z, c, v)}, | |
7841 | {"NZcV", B (N, Z, c, V)}, | |
7842 | {"NZCv", B (N, Z, C, v)}, | |
7843 | {"NZCV", B (N, Z, C, V)} | |
7844 | }; | |
7845 | ||
7846 | #undef N | |
7847 | #undef n | |
7848 | #undef Z | |
7849 | #undef z | |
7850 | #undef C | |
7851 | #undef c | |
7852 | #undef V | |
7853 | #undef v | |
7854 | #undef B | |
7855 | \f | |
7856 | /* MD interface: bits in the object file. */ | |
7857 | ||
7858 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate | |
7859 | for use in the a.out file, and stores them in the array pointed to by buf. | |
7860 | This knows about the endian-ness of the target machine and does | |
7861 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
7862 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
7863 | LITTLENUMS (shorts, here at least). */ | |
7864 | ||
7865 | void | |
7866 | md_number_to_chars (char *buf, valueT val, int n) | |
7867 | { | |
7868 | if (target_big_endian) | |
7869 | number_to_chars_bigendian (buf, val, n); | |
7870 | else | |
7871 | number_to_chars_littleendian (buf, val, n); | |
7872 | } | |
7873 | ||
7874 | /* MD interface: Sections. */ | |
7875 | ||
7876 | /* Estimate the size of a frag before relaxing. Assume everything fits in | |
7877 | 4 bytes. */ | |
7878 | ||
7879 | int | |
7880 | md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED) | |
7881 | { | |
7882 | fragp->fr_var = 4; | |
7883 | return 4; | |
7884 | } | |
7885 | ||
7886 | /* Round up a section size to the appropriate boundary. */ | |
7887 | ||
7888 | valueT | |
7889 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) | |
7890 | { | |
7891 | return size; | |
7892 | } | |
7893 | ||
7894 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents | |
f803aa8e DPT |
7895 | of an rs_align_code fragment. |
7896 | ||
7897 | Here we fill the frag with the appropriate info for padding the | |
7898 | output stream. The resulting frag will consist of a fixed (fr_fix) | |
7899 | and of a repeating (fr_var) part. | |
7900 | ||
7901 | The fixed content is always emitted before the repeating content and | |
7902 | these two parts are used as follows in constructing the output: | |
7903 | - the fixed part will be used to align to a valid instruction word | |
7904 | boundary, in case that we start at a misaligned address; as no | |
7905 | executable instruction can live at the misaligned location, we | |
7906 | simply fill with zeros; | |
7907 | - the variable part will be used to cover the remaining padding and | |
7908 | we fill using the AArch64 NOP instruction. | |
7909 | ||
7910 | Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide | |
7911 | enough storage space for up to 3 bytes for padding the back to a valid | |
7912 | instruction alignment and exactly 4 bytes to store the NOP pattern. */ | |
a06ea964 NC |
7913 | |
7914 | void | |
7915 | aarch64_handle_align (fragS * fragP) | |
7916 | { | |
7917 | /* NOP = d503201f */ | |
7918 | /* AArch64 instructions are always little-endian. */ | |
d9235011 | 7919 | static unsigned char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 }; |
a06ea964 NC |
7920 | |
7921 | int bytes, fix, noop_size; | |
7922 | char *p; | |
a06ea964 NC |
7923 | |
7924 | if (fragP->fr_type != rs_align_code) | |
7925 | return; | |
7926 | ||
7927 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
7928 | p = fragP->fr_literal + fragP->fr_fix; | |
a06ea964 NC |
7929 | |
7930 | #ifdef OBJ_ELF | |
7931 | gas_assert (fragP->tc_frag_data.recorded); | |
7932 | #endif | |
7933 | ||
a06ea964 | 7934 | noop_size = sizeof (aarch64_noop); |
a06ea964 | 7935 | |
f803aa8e DPT |
7936 | fix = bytes & (noop_size - 1); |
7937 | if (fix) | |
a06ea964 | 7938 | { |
a06ea964 | 7939 | #ifdef OBJ_ELF |
3979cf50 | 7940 | insert_data_mapping_symbol (MAP_CUR_INSN, fragP->fr_fix, fragP, fix); |
a06ea964 NC |
7941 | #endif |
7942 | memset (p, 0, fix); | |
7943 | p += fix; | |
f803aa8e | 7944 | fragP->fr_fix += fix; |
a06ea964 NC |
7945 | } |
7946 | ||
f803aa8e DPT |
7947 | if (noop_size) |
7948 | memcpy (p, aarch64_noop, noop_size); | |
7949 | fragP->fr_var = noop_size; | |
a06ea964 NC |
7950 | } |
7951 | ||
7952 | /* Perform target specific initialisation of a frag. | |
7953 | Note - despite the name this initialisation is not done when the frag | |
7954 | is created, but only when its type is assigned. A frag can be created | |
7955 | and used a long time before its type is set, so beware of assuming that | |
33eaf5de | 7956 | this initialisation is performed first. */ |
a06ea964 NC |
7957 | |
7958 | #ifndef OBJ_ELF | |
7959 | void | |
7960 | aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED, | |
7961 | int max_chars ATTRIBUTE_UNUSED) | |
7962 | { | |
7963 | } | |
7964 | ||
7965 | #else /* OBJ_ELF is defined. */ | |
7966 | void | |
7967 | aarch64_init_frag (fragS * fragP, int max_chars) | |
7968 | { | |
7969 | /* Record a mapping symbol for alignment frags. We will delete this | |
7970 | later if the alignment ends up empty. */ | |
7971 | if (!fragP->tc_frag_data.recorded) | |
c7ad08e6 RL |
7972 | fragP->tc_frag_data.recorded = 1; |
7973 | ||
e8d84ca1 NC |
7974 | /* PR 21809: Do not set a mapping state for debug sections |
7975 | - it just confuses other tools. */ | |
fd361982 | 7976 | if (bfd_section_flags (now_seg) & SEC_DEBUGGING) |
e8d84ca1 NC |
7977 | return; |
7978 | ||
c7ad08e6 | 7979 | switch (fragP->fr_type) |
a06ea964 | 7980 | { |
c7ad08e6 RL |
7981 | case rs_align_test: |
7982 | case rs_fill: | |
7983 | mapping_state_2 (MAP_DATA, max_chars); | |
7984 | break; | |
7ea12e5c NC |
7985 | case rs_align: |
7986 | /* PR 20364: We can get alignment frags in code sections, | |
7987 | so do not just assume that we should use the MAP_DATA state. */ | |
3979cf50 | 7988 | mapping_state_2 (subseg_text_p (now_seg) ? MAP_CUR_INSN : MAP_DATA, max_chars); |
7ea12e5c | 7989 | break; |
c7ad08e6 | 7990 | case rs_align_code: |
3979cf50 | 7991 | mapping_state_2 (MAP_CUR_INSN, max_chars); |
c7ad08e6 RL |
7992 | break; |
7993 | default: | |
7994 | break; | |
a06ea964 NC |
7995 | } |
7996 | } | |
7997 | \f | |
7998 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
7999 | ||
8000 | void | |
8001 | tc_aarch64_frame_initial_instructions (void) | |
8002 | { | |
fa6ca5e2 SP |
8003 | if (IS_C64) |
8004 | { | |
8005 | cfi_set_return_column (REG_DW_CLR); | |
8006 | cfi_add_CFA_def_cfa (REG_DW_CSP, 0); | |
8007 | } | |
8008 | else | |
8009 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
8010 | } | |
8011 | ||
8012 | ||
8013 | /* The extra initialisation steps needed by AArch64 in alloc_fde_entry. | |
8014 | Currently only used to initialise the key used to sign the return | |
8015 | address. */ | |
8016 | void | |
8017 | tc_aarch64_fde_entry_init_extra(struct fde_entry *fde) | |
8018 | { | |
8019 | fde->entry_extras.pauth_key = AARCH64_PAUTH_KEY_A; | |
8020 | fde->entry_extras.c64 = IS_C64; | |
8021 | } | |
8022 | ||
8023 | bfd_boolean | |
8024 | tc_aarch64_cfi_startproc_exp (const char *arg) | |
8025 | { | |
8026 | // Allow purecap only for C64 functions. | |
8027 | if (!strcmp ("purecap", arg) && IS_C64) | |
8028 | return TRUE; | |
8029 | ||
8030 | return FALSE; | |
a06ea964 | 8031 | } |
fa6ca5e2 | 8032 | |
a06ea964 NC |
8033 | #endif /* OBJ_ELF */ |
8034 | ||
8035 | /* Convert REGNAME to a DWARF-2 register number. */ | |
8036 | ||
8037 | int | |
8038 | tc_aarch64_regname_to_dw2regnum (char *regname) | |
8039 | { | |
8040 | const reg_entry *reg = parse_reg (®name); | |
8041 | if (reg == NULL) | |
8042 | return -1; | |
8043 | ||
8044 | switch (reg->type) | |
8045 | { | |
8046 | case REG_TYPE_SP_32: | |
8047 | case REG_TYPE_SP_64: | |
8048 | case REG_TYPE_R_32: | |
8049 | case REG_TYPE_R_64: | |
a2cac51c RH |
8050 | return reg->number; |
8051 | ||
a06ea964 NC |
8052 | case REG_TYPE_FP_B: |
8053 | case REG_TYPE_FP_H: | |
8054 | case REG_TYPE_FP_S: | |
8055 | case REG_TYPE_FP_D: | |
8056 | case REG_TYPE_FP_Q: | |
a2cac51c RH |
8057 | return reg->number + 64; |
8058 | ||
fa6ca5e2 SP |
8059 | case REG_TYPE_CA_N: |
8060 | case REG_TYPE_CA_SP: | |
8061 | case REG_TYPE_CA_D: | |
8062 | return reg->number + 198; | |
8063 | ||
a06ea964 NC |
8064 | default: |
8065 | break; | |
8066 | } | |
8067 | return -1; | |
8068 | } | |
8069 | ||
cec5225b YZ |
8070 | /* Implement DWARF2_ADDR_SIZE. */ |
8071 | ||
8072 | int | |
8073 | aarch64_dwarf2_addr_size (void) | |
8074 | { | |
8075 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
8076 | if (ilp32_p) | |
8077 | return 4; | |
8078 | #endif | |
8079 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
8080 | } | |
8081 | ||
a06ea964 NC |
8082 | /* MD interface: Symbol and relocation handling. */ |
8083 | ||
8084 | /* Return the address within the segment that a PC-relative fixup is | |
8085 | relative to. For AArch64 PC-relative fixups applied to instructions | |
8086 | are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */ | |
8087 | ||
8088 | long | |
8089 | md_pcrel_from_section (fixS * fixP, segT seg) | |
8090 | { | |
8091 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; | |
8092 | ||
8093 | /* If this is pc-relative and we are going to emit a relocation | |
8094 | then we just want to put out any pipeline compensation that the linker | |
8095 | will need. Otherwise we want to use the calculated base. */ | |
8096 | if (fixP->fx_pcrel | |
8097 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
8098 | || aarch64_force_relocation (fixP))) | |
8099 | base = 0; | |
8100 | ||
8101 | /* AArch64 should be consistent for all pc-relative relocations. */ | |
8102 | return base + AARCH64_PCREL_OFFSET; | |
8103 | } | |
8104 | ||
8105 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. | |
8106 | Otherwise we have no need to default values of symbols. */ | |
8107 | ||
8108 | symbolS * | |
8109 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) | |
8110 | { | |
8111 | #ifdef OBJ_ELF | |
8112 | if (name[0] == '_' && name[1] == 'G' | |
8113 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
8114 | { | |
8115 | if (!GOT_symbol) | |
8116 | { | |
8117 | if (symbol_find (name)) | |
8118 | as_bad (_("GOT already in the symbol table")); | |
8119 | ||
8120 | GOT_symbol = symbol_new (name, undefined_section, | |
e01e1cee | 8121 | &zero_address_frag, 0); |
a06ea964 NC |
8122 | } |
8123 | ||
8124 | return GOT_symbol; | |
8125 | } | |
8126 | #endif | |
8127 | ||
8128 | return 0; | |
8129 | } | |
8130 | ||
8131 | /* Return non-zero if the indicated VALUE has overflowed the maximum | |
8132 | range expressible by a unsigned number with the indicated number of | |
8133 | BITS. */ | |
8134 | ||
8135 | static bfd_boolean | |
8136 | unsigned_overflow (valueT value, unsigned bits) | |
8137 | { | |
8138 | valueT lim; | |
8139 | if (bits >= sizeof (valueT) * 8) | |
8140 | return FALSE; | |
8141 | lim = (valueT) 1 << bits; | |
8142 | return (value >= lim); | |
8143 | } | |
8144 | ||
8145 | ||
8146 | /* Return non-zero if the indicated VALUE has overflowed the maximum | |
8147 | range expressible by an signed number with the indicated number of | |
8148 | BITS. */ | |
8149 | ||
8150 | static bfd_boolean | |
8151 | signed_overflow (offsetT value, unsigned bits) | |
8152 | { | |
8153 | offsetT lim; | |
8154 | if (bits >= sizeof (offsetT) * 8) | |
8155 | return FALSE; | |
8156 | lim = (offsetT) 1 << (bits - 1); | |
8157 | return (value < -lim || value >= lim); | |
8158 | } | |
8159 | ||
8160 | /* Given an instruction in *INST, which is expected to be a scaled, 12-bit, | |
8161 | unsigned immediate offset load/store instruction, try to encode it as | |
8162 | an unscaled, 9-bit, signed immediate offset load/store instruction. | |
8163 | Return TRUE if it is successful; otherwise return FALSE. | |
8164 | ||
8165 | As a programmer-friendly assembler, LDUR/STUR instructions can be generated | |
8166 | in response to the standard LDR/STR mnemonics when the immediate offset is | |
8167 | unambiguous, i.e. when it is negative or unaligned. */ | |
8168 | ||
8169 | static bfd_boolean | |
8170 | try_to_encode_as_unscaled_ldst (aarch64_inst *instr) | |
8171 | { | |
8172 | int idx; | |
8173 | enum aarch64_op new_op; | |
8174 | const aarch64_opcode *new_opcode; | |
cd0042b3 SP |
8175 | enum aarch64_opnd target; |
8176 | ||
8177 | gas_assert (instr->opcode->iclass == ldst_pos | |
8178 | || instr->opcode->iclass == ldst_altbase); | |
a06ea964 | 8179 | |
cd0042b3 SP |
8180 | target = (instr->opcode->iclass == ldst_pos ? AARCH64_OPND_ADDR_SIMM9 |
8181 | : AARCH64_OPND_CAPADDR_SIMM9); | |
a06ea964 NC |
8182 | |
8183 | switch (instr->opcode->op) | |
8184 | { | |
8185 | case OP_LDRB_POS:new_op = OP_LDURB; break; | |
8186 | case OP_STRB_POS: new_op = OP_STURB; break; | |
8187 | case OP_LDRSB_POS: new_op = OP_LDURSB; break; | |
8188 | case OP_LDRH_POS: new_op = OP_LDURH; break; | |
8189 | case OP_STRH_POS: new_op = OP_STURH; break; | |
8190 | case OP_LDRSH_POS: new_op = OP_LDURSH; break; | |
8191 | case OP_LDR_POS: new_op = OP_LDUR; break; | |
8192 | case OP_STR_POS: new_op = OP_STUR; break; | |
8193 | case OP_LDRF_POS: new_op = OP_LDURV; break; | |
8194 | case OP_STRF_POS: new_op = OP_STURV; break; | |
8195 | case OP_LDRSW_POS: new_op = OP_LDURSW; break; | |
8196 | case OP_PRFM_POS: new_op = OP_PRFUM; break; | |
cd0042b3 SP |
8197 | case OP_LDR_POS_C: new_op = OP_LDUR_C; break; |
8198 | case OP_STR_POS_C: new_op = OP_STUR_C; break; | |
8199 | case OP_LDRB_POS_A:new_op = OP_LDURB_A; break; | |
8200 | case OP_STRB_POS_A: new_op = OP_STURB_A; break; | |
8201 | case OP_LDR_POS_AC: new_op = OP_LDUR_AC; break; | |
8202 | case OP_LDR_POS_AX: new_op = OP_LDUR_AX; break; | |
8203 | case OP_STR_POS_AC: new_op = OP_STUR_AC; break; | |
8204 | case OP_STR_POS_AX: new_op = OP_STUR_AX; break; | |
a06ea964 NC |
8205 | default: new_op = OP_NIL; break; |
8206 | } | |
8207 | ||
8208 | if (new_op == OP_NIL) | |
8209 | return FALSE; | |
8210 | ||
8211 | new_opcode = aarch64_get_opcode (new_op); | |
8212 | gas_assert (new_opcode != NULL); | |
8213 | ||
8214 | DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d", | |
8215 | instr->opcode->op, new_opcode->op); | |
8216 | ||
8217 | aarch64_replace_opcode (instr, new_opcode); | |
8218 | ||
cd0042b3 | 8219 | /* Clear up the address operand's qualifier; otherwise the |
a06ea964 NC |
8220 | qualifier matching may fail because the out-of-date qualifier will |
8221 | prevent the operand being updated with a new and correct qualifier. */ | |
8222 | idx = aarch64_operand_index (instr->opcode->operands, | |
cd0042b3 | 8223 | target); |
a06ea964 NC |
8224 | gas_assert (idx == 1); |
8225 | instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL; | |
8226 | ||
8227 | DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB"); | |
8228 | ||
3979cf50 SP |
8229 | if (!aarch64_opcode_encode (cpu_variant, instr->opcode, instr, &instr->value, |
8230 | NULL, NULL, insn_sequence)) | |
a06ea964 NC |
8231 | return FALSE; |
8232 | ||
8233 | return TRUE; | |
8234 | } | |
8235 | ||
8236 | /* Called by fix_insn to fix a MOV immediate alias instruction. | |
8237 | ||
8238 | Operand for a generic move immediate instruction, which is an alias | |
8239 | instruction that generates a single MOVZ, MOVN or ORR instruction to loads | |
8240 | a 32-bit/64-bit immediate value into general register. An assembler error | |
8241 | shall result if the immediate cannot be created by a single one of these | |
8242 | instructions. If there is a choice, then to ensure reversability an | |
8243 | assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */ | |
8244 | ||
8245 | static void | |
8246 | fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value) | |
8247 | { | |
8248 | const aarch64_opcode *opcode; | |
8249 | ||
8250 | /* Need to check if the destination is SP/ZR. The check has to be done | |
8251 | before any aarch64_replace_opcode. */ | |
8252 | int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]); | |
8253 | int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]); | |
8254 | ||
8255 | instr->operands[1].imm.value = value; | |
8256 | instr->operands[1].skip = 0; | |
8257 | ||
8258 | if (try_mov_wide_p) | |
8259 | { | |
8260 | /* Try the MOVZ alias. */ | |
8261 | opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE); | |
8262 | aarch64_replace_opcode (instr, opcode); | |
3979cf50 | 8263 | if (aarch64_opcode_encode (cpu_variant, instr->opcode, instr, |
7e84b55d | 8264 | &instr->value, NULL, NULL, insn_sequence)) |
a06ea964 NC |
8265 | { |
8266 | put_aarch64_insn (buf, instr->value); | |
8267 | return; | |
8268 | } | |
8269 | /* Try the MOVK alias. */ | |
8270 | opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN); | |
8271 | aarch64_replace_opcode (instr, opcode); | |
3979cf50 | 8272 | if (aarch64_opcode_encode (cpu_variant, instr->opcode, instr, |
7e84b55d | 8273 | &instr->value, NULL, NULL, insn_sequence)) |
a06ea964 NC |
8274 | { |
8275 | put_aarch64_insn (buf, instr->value); | |
8276 | return; | |
8277 | } | |
8278 | } | |
8279 | ||
8280 | if (try_mov_bitmask_p) | |
8281 | { | |
8282 | /* Try the ORR alias. */ | |
8283 | opcode = aarch64_get_opcode (OP_MOV_IMM_LOG); | |
8284 | aarch64_replace_opcode (instr, opcode); | |
3979cf50 | 8285 | if (aarch64_opcode_encode (cpu_variant, instr->opcode, instr, |
7e84b55d | 8286 | &instr->value, NULL, NULL, insn_sequence)) |
a06ea964 NC |
8287 | { |
8288 | put_aarch64_insn (buf, instr->value); | |
8289 | return; | |
8290 | } | |
8291 | } | |
8292 | ||
8293 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8294 | _("immediate cannot be moved by a single instruction")); | |
8295 | } | |
8296 | ||
8297 | /* An instruction operand which is immediate related may have symbol used | |
8298 | in the assembly, e.g. | |
8299 | ||
8300 | mov w0, u32 | |
8301 | .set u32, 0x00ffff00 | |
8302 | ||
8303 | At the time when the assembly instruction is parsed, a referenced symbol, | |
8304 | like 'u32' in the above example may not have been seen; a fixS is created | |
8305 | in such a case and is handled here after symbols have been resolved. | |
8306 | Instruction is fixed up with VALUE using the information in *FIXP plus | |
8307 | extra information in FLAGS. | |
8308 | ||
8309 | This function is called by md_apply_fix to fix up instructions that need | |
8310 | a fix-up described above but does not involve any linker-time relocation. */ | |
8311 | ||
8312 | static void | |
8313 | fix_insn (fixS *fixP, uint32_t flags, offsetT value) | |
8314 | { | |
8315 | int idx; | |
8316 | uint32_t insn; | |
8317 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
8318 | enum aarch64_opnd opnd = fixP->tc_fix_data.opnd; | |
8319 | aarch64_inst *new_inst = fixP->tc_fix_data.inst; | |
8320 | ||
8321 | if (new_inst) | |
8322 | { | |
8323 | /* Now the instruction is about to be fixed-up, so the operand that | |
8324 | was previously marked as 'ignored' needs to be unmarked in order | |
8325 | to get the encoding done properly. */ | |
8326 | idx = aarch64_operand_index (new_inst->opcode->operands, opnd); | |
8327 | new_inst->operands[idx].skip = 0; | |
8328 | } | |
8329 | ||
8330 | gas_assert (opnd != AARCH64_OPND_NIL); | |
8331 | ||
8332 | switch (opnd) | |
8333 | { | |
8334 | case AARCH64_OPND_EXCEPTION: | |
09c1e68a | 8335 | case AARCH64_OPND_UNDEFINED: |
a06ea964 NC |
8336 | if (unsigned_overflow (value, 16)) |
8337 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8338 | _("immediate out of range")); | |
8339 | insn = get_aarch64_insn (buf); | |
09c1e68a | 8340 | insn |= (opnd == AARCH64_OPND_EXCEPTION) ? encode_svc_imm (value) : value; |
a06ea964 NC |
8341 | put_aarch64_insn (buf, insn); |
8342 | break; | |
8343 | ||
8344 | case AARCH64_OPND_AIMM: | |
dc64c2ba | 8345 | case AARCH64_OPND_A64C_AIMM: |
a06ea964 NC |
8346 | /* ADD or SUB with immediate. |
8347 | NOTE this assumes we come here with a add/sub shifted reg encoding | |
8348 | 3 322|2222|2 2 2 21111 111111 | |
8349 | 1 098|7654|3 2 1 09876 543210 98765 43210 | |
8350 | 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD | |
8351 | 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS | |
8352 | 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB | |
8353 | 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS | |
8354 | -> | |
8355 | 3 322|2222|2 2 221111111111 | |
8356 | 1 098|7654|3 2 109876543210 98765 43210 | |
8357 | 11000000 sf 001|0001|shift imm12 Rn Rd ADD | |
8358 | 31000000 sf 011|0001|shift imm12 Rn Rd ADDS | |
8359 | 51000000 sf 101|0001|shift imm12 Rn Rd SUB | |
8360 | 71000000 sf 111|0001|shift imm12 Rn Rd SUBS | |
8361 | Fields sf Rn Rd are already set. */ | |
8362 | insn = get_aarch64_insn (buf); | |
8363 | if (value < 0) | |
8364 | { | |
8365 | /* Add <-> sub. */ | |
8366 | insn = reencode_addsub_switch_add_sub (insn); | |
8367 | value = -value; | |
8368 | } | |
8369 | ||
8370 | if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0 | |
8371 | && unsigned_overflow (value, 12)) | |
8372 | { | |
8373 | /* Try to shift the value by 12 to make it fit. */ | |
8374 | if (((value >> 12) << 12) == value | |
8375 | && ! unsigned_overflow (value, 12 + 12)) | |
8376 | { | |
8377 | value >>= 12; | |
8378 | insn |= encode_addsub_imm_shift_amount (1); | |
8379 | } | |
8380 | } | |
8381 | ||
8382 | if (unsigned_overflow (value, 12)) | |
8383 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8384 | _("immediate out of range")); | |
8385 | ||
8386 | insn |= encode_addsub_imm (value); | |
8387 | ||
8388 | put_aarch64_insn (buf, insn); | |
8389 | break; | |
8390 | ||
8391 | case AARCH64_OPND_SIMD_IMM: | |
8392 | case AARCH64_OPND_SIMD_IMM_SFT: | |
8393 | case AARCH64_OPND_LIMM: | |
8394 | /* Bit mask immediate. */ | |
8395 | gas_assert (new_inst != NULL); | |
8396 | idx = aarch64_operand_index (new_inst->opcode->operands, opnd); | |
8397 | new_inst->operands[idx].imm.value = value; | |
3979cf50 | 8398 | if (aarch64_opcode_encode (cpu_variant, new_inst->opcode, new_inst, |
7e84b55d | 8399 | &new_inst->value, NULL, NULL, insn_sequence)) |
a06ea964 NC |
8400 | put_aarch64_insn (buf, new_inst->value); |
8401 | else | |
8402 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8403 | _("invalid immediate")); | |
8404 | break; | |
8405 | ||
8406 | case AARCH64_OPND_HALF: | |
8407 | /* 16-bit unsigned immediate. */ | |
8408 | if (unsigned_overflow (value, 16)) | |
8409 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8410 | _("immediate out of range")); | |
8411 | insn = get_aarch64_insn (buf); | |
8412 | insn |= encode_movw_imm (value & 0xffff); | |
8413 | put_aarch64_insn (buf, insn); | |
8414 | break; | |
8415 | ||
8416 | case AARCH64_OPND_IMM_MOV: | |
8417 | /* Operand for a generic move immediate instruction, which is | |
8418 | an alias instruction that generates a single MOVZ, MOVN or ORR | |
8419 | instruction to loads a 32-bit/64-bit immediate value into general | |
8420 | register. An assembler error shall result if the immediate cannot be | |
8421 | created by a single one of these instructions. If there is a choice, | |
8422 | then to ensure reversability an assembler must prefer a MOVZ to MOVN, | |
8423 | and MOVZ or MOVN to ORR. */ | |
8424 | gas_assert (new_inst != NULL); | |
8425 | fix_mov_imm_insn (fixP, buf, new_inst, value); | |
8426 | break; | |
8427 | ||
cd0042b3 | 8428 | case AARCH64_OPND_CAPADDR_UIMM9: |
324988cf | 8429 | case AARCH64_OPND_A64C_ADDR_SIMM9: |
e9af8aad | 8430 | case AARCH64_OPND_A64C_ADDR_SIMM7: |
a06ea964 NC |
8431 | case AARCH64_OPND_ADDR_SIMM7: |
8432 | case AARCH64_OPND_ADDR_SIMM9: | |
8433 | case AARCH64_OPND_ADDR_SIMM9_2: | |
3f06e550 | 8434 | case AARCH64_OPND_ADDR_SIMM10: |
a06ea964 | 8435 | case AARCH64_OPND_ADDR_UIMM12: |
fb3265b3 SD |
8436 | case AARCH64_OPND_ADDR_SIMM11: |
8437 | case AARCH64_OPND_ADDR_SIMM13: | |
a06ea964 NC |
8438 | /* Immediate offset in an address. */ |
8439 | insn = get_aarch64_insn (buf); | |
8440 | ||
8441 | gas_assert (new_inst != NULL && new_inst->value == insn); | |
8442 | gas_assert (new_inst->opcode->operands[1] == opnd | |
8443 | || new_inst->opcode->operands[2] == opnd); | |
8444 | ||
8445 | /* Get the index of the address operand. */ | |
8446 | if (new_inst->opcode->operands[1] == opnd) | |
8447 | /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
8448 | idx = 1; | |
8449 | else | |
8450 | /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ | |
8451 | idx = 2; | |
8452 | ||
8453 | /* Update the resolved offset value. */ | |
8454 | new_inst->operands[idx].addr.offset.imm = value; | |
8455 | ||
8456 | /* Encode/fix-up. */ | |
3979cf50 | 8457 | if (aarch64_opcode_encode (cpu_variant, new_inst->opcode, new_inst, |
7e84b55d | 8458 | &new_inst->value, NULL, NULL, insn_sequence)) |
a06ea964 NC |
8459 | { |
8460 | put_aarch64_insn (buf, new_inst->value); | |
8461 | break; | |
8462 | } | |
cd0042b3 SP |
8463 | else if ((new_inst->opcode->iclass == ldst_pos |
8464 | || new_inst->opcode->iclass == ldst_altbase) | |
a06ea964 NC |
8465 | && try_to_encode_as_unscaled_ldst (new_inst)) |
8466 | { | |
8467 | put_aarch64_insn (buf, new_inst->value); | |
8468 | break; | |
8469 | } | |
8470 | ||
8471 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8472 | _("immediate offset out of range")); | |
8473 | break; | |
8474 | ||
8475 | default: | |
8476 | gas_assert (0); | |
8477 | as_fatal (_("unhandled operand code %d"), opnd); | |
8478 | } | |
8479 | } | |
8480 | ||
8481 | /* Apply a fixup (fixP) to segment data, once it has been determined | |
8482 | by our caller that we have all the info we need to fix it up. | |
8483 | ||
8484 | Parameter valP is the pointer to the value of the bits. */ | |
8485 | ||
8486 | void | |
8487 | md_apply_fix (fixS * fixP, valueT * valP, segT seg) | |
8488 | { | |
8489 | offsetT value = *valP; | |
8490 | uint32_t insn; | |
8491 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
8492 | int scale; | |
8493 | unsigned flags = fixP->fx_addnumber; | |
8494 | ||
8495 | DEBUG_TRACE ("\n\n"); | |
8496 | DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~"); | |
8497 | DEBUG_TRACE ("Enter md_apply_fix"); | |
8498 | ||
8499 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); | |
8500 | ||
8501 | /* Note whether this will delete the relocation. */ | |
8502 | ||
8503 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
8504 | fixP->fx_done = 1; | |
8505 | ||
8506 | /* Process the relocations. */ | |
8507 | switch (fixP->fx_r_type) | |
8508 | { | |
8509 | case BFD_RELOC_NONE: | |
8510 | /* This will need to go in the object file. */ | |
8511 | fixP->fx_done = 0; | |
8512 | break; | |
8513 | ||
8514 | case BFD_RELOC_8: | |
8515 | case BFD_RELOC_8_PCREL: | |
8516 | if (fixP->fx_done || !seg->use_rela_p) | |
8517 | md_number_to_chars (buf, value, 1); | |
8518 | break; | |
8519 | ||
8520 | case BFD_RELOC_16: | |
8521 | case BFD_RELOC_16_PCREL: | |
8522 | if (fixP->fx_done || !seg->use_rela_p) | |
8523 | md_number_to_chars (buf, value, 2); | |
8524 | break; | |
8525 | ||
8526 | case BFD_RELOC_32: | |
8527 | case BFD_RELOC_32_PCREL: | |
8528 | if (fixP->fx_done || !seg->use_rela_p) | |
8529 | md_number_to_chars (buf, value, 4); | |
8530 | break; | |
8531 | ||
8532 | case BFD_RELOC_64: | |
8533 | case BFD_RELOC_64_PCREL: | |
8534 | if (fixP->fx_done || !seg->use_rela_p) | |
8535 | md_number_to_chars (buf, value, 8); | |
8536 | break; | |
8537 | ||
8538 | case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP: | |
8539 | /* We claim that these fixups have been processed here, even if | |
8540 | in fact we generate an error because we do not have a reloc | |
8541 | for them, so tc_gen_reloc() will reject them. */ | |
8542 | fixP->fx_done = 1; | |
8543 | if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy)) | |
8544 | { | |
8545 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8546 | _("undefined symbol %s used as an immediate value"), | |
8547 | S_GET_NAME (fixP->fx_addsy)); | |
8548 | goto apply_fix_return; | |
8549 | } | |
8550 | fix_insn (fixP, flags, value); | |
8551 | break; | |
8552 | ||
f7d2c675 SP |
8553 | case BFD_RELOC_MORELLO_LD_LO17_PCREL: |
8554 | if (fixP->fx_done || !seg->use_rela_p) | |
8555 | { | |
8556 | /* The LDR-immediate that uses LO17 aligns the address down to | |
8557 | 16-byte boundary to get the final address of the capability. | |
8558 | Since the fixed up immediate also needs to be 16-byte aligned, | |
8559 | align it up to the 16-byte boundary so that the downward alignment | |
8560 | of the load literal instruction gets us the correct address. */ | |
8561 | value = (value + 0xf) & ~(offsetT) 0xf; | |
8562 | ||
8563 | if (signed_overflow (value, 21)) | |
8564 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8565 | _("pcc-relative load offset out of range")); | |
8566 | insn = get_aarch64_insn (buf); | |
8567 | insn |= encode_ld_lit_ofs_17 (value >> 4); | |
8568 | put_aarch64_insn (buf, insn); | |
8569 | } | |
8570 | break; | |
8571 | ||
a06ea964 | 8572 | case BFD_RELOC_AARCH64_LD_LO19_PCREL: |
a06ea964 NC |
8573 | if (fixP->fx_done || !seg->use_rela_p) |
8574 | { | |
89d2a2a3 MS |
8575 | if (value & 3) |
8576 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8577 | _("pc-relative load offset not word aligned")); | |
8578 | if (signed_overflow (value, 21)) | |
8579 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8580 | _("pc-relative load offset out of range")); | |
a06ea964 NC |
8581 | insn = get_aarch64_insn (buf); |
8582 | insn |= encode_ld_lit_ofs_19 (value >> 2); | |
8583 | put_aarch64_insn (buf, insn); | |
8584 | } | |
8585 | break; | |
8586 | ||
8587 | case BFD_RELOC_AARCH64_ADR_LO21_PCREL: | |
a06ea964 NC |
8588 | if (fixP->fx_done || !seg->use_rela_p) |
8589 | { | |
89d2a2a3 MS |
8590 | if (signed_overflow (value, 21)) |
8591 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8592 | _("pc-relative address offset out of range")); | |
a06ea964 NC |
8593 | insn = get_aarch64_insn (buf); |
8594 | insn |= encode_adr_imm (value); | |
8595 | put_aarch64_insn (buf, insn); | |
8596 | } | |
8597 | break; | |
8598 | ||
8599 | case BFD_RELOC_AARCH64_BRANCH19: | |
e19e9199 | 8600 | case BFD_RELOC_MORELLO_BRANCH19: |
a06ea964 NC |
8601 | if (fixP->fx_done || !seg->use_rela_p) |
8602 | { | |
89d2a2a3 MS |
8603 | if (value & 3) |
8604 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8605 | _("conditional branch target not word aligned")); | |
8606 | if (signed_overflow (value, 21)) | |
8607 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8608 | _("conditional branch out of range")); | |
a06ea964 NC |
8609 | insn = get_aarch64_insn (buf); |
8610 | insn |= encode_cond_branch_ofs_19 (value >> 2); | |
8611 | put_aarch64_insn (buf, insn); | |
8612 | } | |
8613 | break; | |
8614 | ||
e19e9199 | 8615 | case BFD_RELOC_MORELLO_TSTBR14: |
a06ea964 | 8616 | case BFD_RELOC_AARCH64_TSTBR14: |
a06ea964 NC |
8617 | if (fixP->fx_done || !seg->use_rela_p) |
8618 | { | |
89d2a2a3 MS |
8619 | if (value & 3) |
8620 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8621 | _("conditional branch target not word aligned")); | |
8622 | if (signed_overflow (value, 16)) | |
8623 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8624 | _("conditional branch out of range")); | |
a06ea964 NC |
8625 | insn = get_aarch64_insn (buf); |
8626 | insn |= encode_tst_branch_ofs_14 (value >> 2); | |
8627 | put_aarch64_insn (buf, insn); | |
8628 | } | |
8629 | break; | |
8630 | ||
e19e9199 SP |
8631 | case BFD_RELOC_MORELLO_CALL26: |
8632 | case BFD_RELOC_MORELLO_JUMP26: | |
a06ea964 | 8633 | case BFD_RELOC_AARCH64_CALL26: |
f09c556a | 8634 | case BFD_RELOC_AARCH64_JUMP26: |
a06ea964 NC |
8635 | if (fixP->fx_done || !seg->use_rela_p) |
8636 | { | |
89d2a2a3 MS |
8637 | if (value & 3) |
8638 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8639 | _("branch target not word aligned")); | |
8640 | if (signed_overflow (value, 28)) | |
8641 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8642 | _("branch out of range")); | |
a06ea964 NC |
8643 | insn = get_aarch64_insn (buf); |
8644 | insn |= encode_branch_ofs_26 (value >> 2); | |
8645 | put_aarch64_insn (buf, insn); | |
8646 | } | |
8647 | break; | |
8648 | ||
8649 | case BFD_RELOC_AARCH64_MOVW_G0: | |
a06ea964 | 8650 | case BFD_RELOC_AARCH64_MOVW_G0_NC: |
f09c556a | 8651 | case BFD_RELOC_AARCH64_MOVW_G0_S: |
ca632371 | 8652 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC: |
32247401 RL |
8653 | case BFD_RELOC_AARCH64_MOVW_PREL_G0: |
8654 | case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC: | |
a06ea964 NC |
8655 | scale = 0; |
8656 | goto movw_common; | |
8657 | case BFD_RELOC_AARCH64_MOVW_G1: | |
a06ea964 | 8658 | case BFD_RELOC_AARCH64_MOVW_G1_NC: |
f09c556a | 8659 | case BFD_RELOC_AARCH64_MOVW_G1_S: |
654248e7 | 8660 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: |
32247401 RL |
8661 | case BFD_RELOC_AARCH64_MOVW_PREL_G1: |
8662 | case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC: | |
a06ea964 NC |
8663 | scale = 16; |
8664 | goto movw_common; | |
43a357f9 RL |
8665 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: |
8666 | scale = 0; | |
8667 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
8668 | /* Should always be exported to object file, see | |
8669 | aarch64_force_relocation(). */ | |
8670 | gas_assert (!fixP->fx_done); | |
8671 | gas_assert (seg->use_rela_p); | |
8672 | goto movw_common; | |
8673 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: | |
8674 | scale = 16; | |
8675 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
8676 | /* Should always be exported to object file, see | |
8677 | aarch64_force_relocation(). */ | |
8678 | gas_assert (!fixP->fx_done); | |
8679 | gas_assert (seg->use_rela_p); | |
8680 | goto movw_common; | |
a06ea964 | 8681 | case BFD_RELOC_AARCH64_MOVW_G2: |
a06ea964 | 8682 | case BFD_RELOC_AARCH64_MOVW_G2_NC: |
f09c556a | 8683 | case BFD_RELOC_AARCH64_MOVW_G2_S: |
32247401 RL |
8684 | case BFD_RELOC_AARCH64_MOVW_PREL_G2: |
8685 | case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC: | |
a06ea964 NC |
8686 | scale = 32; |
8687 | goto movw_common; | |
8688 | case BFD_RELOC_AARCH64_MOVW_G3: | |
32247401 | 8689 | case BFD_RELOC_AARCH64_MOVW_PREL_G3: |
a06ea964 NC |
8690 | scale = 48; |
8691 | movw_common: | |
8692 | if (fixP->fx_done || !seg->use_rela_p) | |
8693 | { | |
8694 | insn = get_aarch64_insn (buf); | |
8695 | ||
8696 | if (!fixP->fx_done) | |
8697 | { | |
8698 | /* REL signed addend must fit in 16 bits */ | |
8699 | if (signed_overflow (value, 16)) | |
8700 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8701 | _("offset out of range")); | |
8702 | } | |
8703 | else | |
8704 | { | |
8705 | /* Check for overflow and scale. */ | |
8706 | switch (fixP->fx_r_type) | |
8707 | { | |
8708 | case BFD_RELOC_AARCH64_MOVW_G0: | |
8709 | case BFD_RELOC_AARCH64_MOVW_G1: | |
8710 | case BFD_RELOC_AARCH64_MOVW_G2: | |
8711 | case BFD_RELOC_AARCH64_MOVW_G3: | |
654248e7 | 8712 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: |
43a357f9 | 8713 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: |
a06ea964 NC |
8714 | if (unsigned_overflow (value, scale + 16)) |
8715 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8716 | _("unsigned value out of range")); | |
8717 | break; | |
8718 | case BFD_RELOC_AARCH64_MOVW_G0_S: | |
8719 | case BFD_RELOC_AARCH64_MOVW_G1_S: | |
8720 | case BFD_RELOC_AARCH64_MOVW_G2_S: | |
32247401 RL |
8721 | case BFD_RELOC_AARCH64_MOVW_PREL_G0: |
8722 | case BFD_RELOC_AARCH64_MOVW_PREL_G1: | |
8723 | case BFD_RELOC_AARCH64_MOVW_PREL_G2: | |
a06ea964 NC |
8724 | /* NOTE: We can only come here with movz or movn. */ |
8725 | if (signed_overflow (value, scale + 16)) | |
8726 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8727 | _("signed value out of range")); | |
8728 | if (value < 0) | |
8729 | { | |
8730 | /* Force use of MOVN. */ | |
8731 | value = ~value; | |
8732 | insn = reencode_movzn_to_movn (insn); | |
8733 | } | |
8734 | else | |
8735 | { | |
8736 | /* Force use of MOVZ. */ | |
8737 | insn = reencode_movzn_to_movz (insn); | |
8738 | } | |
8739 | break; | |
8740 | default: | |
8741 | /* Unchecked relocations. */ | |
8742 | break; | |
8743 | } | |
8744 | value >>= scale; | |
8745 | } | |
8746 | ||
8747 | /* Insert value into MOVN/MOVZ/MOVK instruction. */ | |
8748 | insn |= encode_movw_imm (value & 0xffff); | |
8749 | ||
8750 | put_aarch64_insn (buf, insn); | |
8751 | } | |
8752 | break; | |
8753 | ||
a6bb11b2 YZ |
8754 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC: |
8755 | fixP->fx_r_type = (ilp32_p | |
8756 | ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC | |
8757 | : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC); | |
8758 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
8759 | /* Should always be exported to object file, see | |
8760 | aarch64_force_relocation(). */ | |
8761 | gas_assert (!fixP->fx_done); | |
8762 | gas_assert (seg->use_rela_p); | |
8763 | break; | |
8764 | ||
8765 | case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC: | |
4ca9b406 SP |
8766 | if (fixP->tc_fix_data.c64) |
8767 | fixP->fx_r_type = BFD_RELOC_MORELLO_TLSDESC_LD128_LO12; | |
8768 | else if (ilp32_p) | |
8769 | fixP->fx_r_type = BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC; | |
8770 | else | |
8771 | fixP->fx_r_type = BFD_RELOC_AARCH64_TLSDESC_LD64_LO12; | |
a6bb11b2 YZ |
8772 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
8773 | /* Should always be exported to object file, see | |
8774 | aarch64_force_relocation(). */ | |
8775 | gas_assert (!fixP->fx_done); | |
8776 | gas_assert (seg->use_rela_p); | |
8777 | break; | |
8778 | ||
f955cccf | 8779 | case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12: |
4ca9b406 | 8780 | case BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20: |
2c0a3565 | 8781 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: |
389b8029 | 8782 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21: |
2c0a3565 | 8783 | case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC: |
f955cccf | 8784 | case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12: |
4ca9b406 | 8785 | case BFD_RELOC_MORELLO_TLSDESC_LD128_LO12: |
1ada945d | 8786 | case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: |
a06ea964 | 8787 | case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: |
2c0a3565 | 8788 | case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: |
3c12b054 | 8789 | case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: |
3e8286c0 | 8790 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: |
1aa66fb1 | 8791 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
a06ea964 | 8792 | case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: |
a6bb11b2 | 8793 | case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC: |
2c0a3565 | 8794 | case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: |
043bf05a | 8795 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19: |
3b957e5b RL |
8796 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: |
8797 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1: | |
49df5539 | 8798 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12: |
70151fb5 | 8799 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12: |
13289c10 | 8800 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: |
a12fad50 | 8801 | case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC: |
1107e076 | 8802 | case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21: |
6c37fedc | 8803 | case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21: |
4c562523 JW |
8804 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12: |
8805 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC: | |
8806 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12: | |
8807 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC: | |
8808 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12: | |
8809 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC: | |
8810 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12: | |
8811 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC: | |
49df5539 JW |
8812 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0: |
8813 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: | |
8814 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1: | |
8815 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: | |
8816 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2: | |
84f1b9fb RL |
8817 | case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12: |
8818 | case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC: | |
8819 | case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12: | |
8820 | case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC: | |
8821 | case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12: | |
8822 | case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC: | |
8823 | case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12: | |
8824 | case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC: | |
a06ea964 | 8825 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: |
2c0a3565 | 8826 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12: |
a06ea964 | 8827 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC: |
a06ea964 NC |
8828 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
8829 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: | |
2c0a3565 MS |
8830 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: |
8831 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: | |
8832 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: | |
a06ea964 NC |
8833 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
8834 | /* Should always be exported to object file, see | |
8835 | aarch64_force_relocation(). */ | |
8836 | gas_assert (!fixP->fx_done); | |
8837 | gas_assert (seg->use_rela_p); | |
8838 | break; | |
8839 | ||
a6bb11b2 YZ |
8840 | case BFD_RELOC_AARCH64_LD_GOT_LO12_NC: |
8841 | /* Should always be exported to object file, see | |
8842 | aarch64_force_relocation(). */ | |
a1bdea65 SP |
8843 | if (fixP->tc_fix_data.c64) |
8844 | fixP->fx_r_type = BFD_RELOC_MORELLO_LD128_GOT_LO12_NC; | |
8845 | else if (ilp32_p) | |
8846 | fixP->fx_r_type = BFD_RELOC_AARCH64_LD32_GOT_LO12_NC; | |
8847 | else | |
8848 | fixP->fx_r_type = BFD_RELOC_AARCH64_LD64_GOT_LO12_NC; | |
a6bb11b2 YZ |
8849 | gas_assert (!fixP->fx_done); |
8850 | gas_assert (seg->use_rela_p); | |
8851 | break; | |
8852 | ||
a06ea964 | 8853 | case BFD_RELOC_AARCH64_ADD_LO12: |
f09c556a | 8854 | case BFD_RELOC_AARCH64_ADR_GOT_PAGE: |
92504105 SP |
8855 | case BFD_RELOC_MORELLO_ADR_GOT_PAGE: |
8856 | case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL: | |
8857 | case BFD_RELOC_MORELLO_ADR_HI20_PCREL: | |
f09c556a JW |
8858 | case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: |
8859 | case BFD_RELOC_AARCH64_ADR_HI21_PCREL: | |
8860 | case BFD_RELOC_AARCH64_GOT_LD_PREL19: | |
8861 | case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC: | |
3d715ce4 | 8862 | case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14: |
87f5fbcc | 8863 | case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15: |
a921b5bd | 8864 | case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15: |
f09c556a JW |
8865 | case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC: |
8866 | case BFD_RELOC_AARCH64_LDST128_LO12: | |
a06ea964 NC |
8867 | case BFD_RELOC_AARCH64_LDST16_LO12: |
8868 | case BFD_RELOC_AARCH64_LDST32_LO12: | |
8869 | case BFD_RELOC_AARCH64_LDST64_LO12: | |
f09c556a | 8870 | case BFD_RELOC_AARCH64_LDST8_LO12: |
a1bdea65 | 8871 | case BFD_RELOC_MORELLO_LD128_GOT_LO12_NC: |
a06ea964 NC |
8872 | /* Should always be exported to object file, see |
8873 | aarch64_force_relocation(). */ | |
8874 | gas_assert (!fixP->fx_done); | |
8875 | gas_assert (seg->use_rela_p); | |
8876 | break; | |
8877 | ||
8878 | case BFD_RELOC_AARCH64_TLSDESC_ADD: | |
a06ea964 | 8879 | case BFD_RELOC_AARCH64_TLSDESC_CALL: |
4ca9b406 | 8880 | case BFD_RELOC_MORELLO_TLSDESC_CALL: |
f09c556a | 8881 | case BFD_RELOC_AARCH64_TLSDESC_LDR: |
40bbb79e | 8882 | case BFD_RELOC_MORELLO_CAPINIT: |
a06ea964 NC |
8883 | break; |
8884 | ||
b97e87cc NC |
8885 | case BFD_RELOC_UNUSED: |
8886 | /* An error will already have been reported. */ | |
8887 | break; | |
8888 | ||
a06ea964 NC |
8889 | default: |
8890 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8891 | _("unexpected %s fixup"), | |
8892 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
8893 | break; | |
8894 | } | |
8895 | ||
dc1e8a47 | 8896 | apply_fix_return: |
a06ea964 NC |
8897 | /* Free the allocated the struct aarch64_inst. |
8898 | N.B. currently there are very limited number of fix-up types actually use | |
8899 | this field, so the impact on the performance should be minimal . */ | |
9fbb53c7 | 8900 | free (fixP->tc_fix_data.inst); |
a06ea964 NC |
8901 | |
8902 | return; | |
8903 | } | |
8904 | ||
8905 | /* Translate internal representation of relocation info to BFD target | |
8906 | format. */ | |
8907 | ||
8908 | arelent * | |
8909 | tc_gen_reloc (asection * section, fixS * fixp) | |
8910 | { | |
8911 | arelent *reloc; | |
8912 | bfd_reloc_code_real_type code; | |
8913 | ||
325801bd | 8914 | reloc = XNEW (arelent); |
a06ea964 | 8915 | |
325801bd | 8916 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
a06ea964 NC |
8917 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
8918 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
8919 | ||
8920 | if (fixp->fx_pcrel) | |
8921 | { | |
8922 | if (section->use_rela_p) | |
8923 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
8924 | else | |
8925 | fixp->fx_offset = reloc->address; | |
8926 | } | |
8927 | reloc->addend = fixp->fx_offset; | |
8928 | ||
8929 | code = fixp->fx_r_type; | |
8930 | switch (code) | |
8931 | { | |
8932 | case BFD_RELOC_16: | |
8933 | if (fixp->fx_pcrel) | |
8934 | code = BFD_RELOC_16_PCREL; | |
8935 | break; | |
8936 | ||
8937 | case BFD_RELOC_32: | |
8938 | if (fixp->fx_pcrel) | |
8939 | code = BFD_RELOC_32_PCREL; | |
8940 | break; | |
8941 | ||
8942 | case BFD_RELOC_64: | |
8943 | if (fixp->fx_pcrel) | |
8944 | code = BFD_RELOC_64_PCREL; | |
8945 | break; | |
8946 | ||
8947 | default: | |
8948 | break; | |
8949 | } | |
8950 | ||
8951 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
8952 | if (reloc->howto == NULL) | |
8953 | { | |
8954 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
8955 | _ | |
8956 | ("cannot represent %s relocation in this object file format"), | |
8957 | bfd_get_reloc_code_name (code)); | |
8958 | return NULL; | |
8959 | } | |
8960 | ||
8961 | return reloc; | |
8962 | } | |
8963 | ||
8964 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ | |
8965 | ||
8966 | void | |
8967 | cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp) | |
8968 | { | |
8969 | bfd_reloc_code_real_type type; | |
8970 | int pcrel = 0; | |
8971 | ||
8972 | /* Pick a reloc. | |
8973 | FIXME: @@ Should look at CPU word size. */ | |
8974 | switch (size) | |
8975 | { | |
8976 | case 1: | |
8977 | type = BFD_RELOC_8; | |
8978 | break; | |
8979 | case 2: | |
8980 | type = BFD_RELOC_16; | |
8981 | break; | |
8982 | case 4: | |
8983 | type = BFD_RELOC_32; | |
8984 | break; | |
8985 | case 8: | |
8986 | type = BFD_RELOC_64; | |
8987 | break; | |
8988 | default: | |
8989 | as_bad (_("cannot do %u-byte relocation"), size); | |
8990 | type = BFD_RELOC_UNUSED; | |
8991 | break; | |
8992 | } | |
8993 | ||
8994 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); | |
8995 | } | |
8996 | ||
8997 | int | |
8998 | aarch64_force_relocation (struct fix *fixp) | |
8999 | { | |
9000 | switch (fixp->fx_r_type) | |
9001 | { | |
9002 | case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP: | |
9003 | /* Perform these "immediate" internal relocations | |
9004 | even if the symbol is extern or weak. */ | |
9005 | return 0; | |
9006 | ||
a6bb11b2 | 9007 | case BFD_RELOC_AARCH64_LD_GOT_LO12_NC: |
f09c556a JW |
9008 | case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC: |
9009 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC: | |
a6bb11b2 YZ |
9010 | /* Pseudo relocs that need to be fixed up according to |
9011 | ilp32_p. */ | |
9012 | return 0; | |
9013 | ||
2c0a3565 MS |
9014 | case BFD_RELOC_AARCH64_ADD_LO12: |
9015 | case BFD_RELOC_AARCH64_ADR_GOT_PAGE: | |
92504105 SP |
9016 | case BFD_RELOC_MORELLO_ADR_GOT_PAGE: |
9017 | case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL: | |
9018 | case BFD_RELOC_MORELLO_ADR_HI20_PCREL: | |
2c0a3565 MS |
9019 | case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: |
9020 | case BFD_RELOC_AARCH64_ADR_HI21_PCREL: | |
9021 | case BFD_RELOC_AARCH64_GOT_LD_PREL19: | |
9022 | case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC: | |
3d715ce4 | 9023 | case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14: |
87f5fbcc | 9024 | case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15: |
a921b5bd | 9025 | case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15: |
2c0a3565 | 9026 | case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC: |
a1bdea65 | 9027 | case BFD_RELOC_MORELLO_LD128_GOT_LO12_NC: |
2c0a3565 MS |
9028 | case BFD_RELOC_AARCH64_LDST128_LO12: |
9029 | case BFD_RELOC_AARCH64_LDST16_LO12: | |
9030 | case BFD_RELOC_AARCH64_LDST32_LO12: | |
9031 | case BFD_RELOC_AARCH64_LDST64_LO12: | |
9032 | case BFD_RELOC_AARCH64_LDST8_LO12: | |
f955cccf | 9033 | case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12: |
4ca9b406 | 9034 | case BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20: |
2c0a3565 | 9035 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: |
389b8029 | 9036 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21: |
2c0a3565 | 9037 | case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC: |
f955cccf | 9038 | case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12: |
4ca9b406 | 9039 | case BFD_RELOC_MORELLO_TLSDESC_LD128_LO12: |
1ada945d | 9040 | case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: |
43a357f9 RL |
9041 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: |
9042 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: | |
a06ea964 | 9043 | case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: |
2c0a3565 | 9044 | case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: |
3c12b054 | 9045 | case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: |
3e8286c0 | 9046 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: |
1aa66fb1 | 9047 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
a06ea964 | 9048 | case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: |
a6bb11b2 | 9049 | case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC: |
2c0a3565 | 9050 | case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: |
043bf05a | 9051 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19: |
3b957e5b RL |
9052 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: |
9053 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1: | |
9054 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12: | |
70151fb5 | 9055 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12: |
13289c10 | 9056 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: |
a12fad50 | 9057 | case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC: |
1107e076 | 9058 | case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21: |
6c37fedc | 9059 | case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21: |
4c562523 JW |
9060 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12: |
9061 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC: | |
9062 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12: | |
9063 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC: | |
9064 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12: | |
9065 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC: | |
9066 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12: | |
9067 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC: | |
49df5539 JW |
9068 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0: |
9069 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: | |
9070 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1: | |
9071 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: | |
9072 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2: | |
84f1b9fb RL |
9073 | case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12: |
9074 | case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC: | |
9075 | case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12: | |
9076 | case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC: | |
9077 | case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12: | |
9078 | case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC: | |
9079 | case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12: | |
9080 | case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC: | |
a06ea964 | 9081 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: |
2c0a3565 | 9082 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12: |
a06ea964 | 9083 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC: |
a06ea964 NC |
9084 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
9085 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: | |
2c0a3565 MS |
9086 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: |
9087 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: | |
9088 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: | |
a06ea964 NC |
9089 | /* Always leave these relocations for the linker. */ |
9090 | return 1; | |
9091 | ||
f0070c1e | 9092 | case BFD_RELOC_AARCH64_ADR_LO21_PCREL: |
e19e9199 SP |
9093 | case BFD_RELOC_MORELLO_BRANCH19: |
9094 | case BFD_RELOC_MORELLO_TSTBR14: | |
f0070c1e SP |
9095 | case BFD_RELOC_AARCH64_BRANCH19: |
9096 | case BFD_RELOC_AARCH64_TSTBR14: | |
e19e9199 SP |
9097 | case BFD_RELOC_MORELLO_CALL26: |
9098 | case BFD_RELOC_MORELLO_JUMP26: | |
f0070c1e SP |
9099 | case BFD_RELOC_AARCH64_CALL26: |
9100 | case BFD_RELOC_AARCH64_JUMP26: | |
9101 | gas_assert (fixp->fx_addsy != NULL); | |
9102 | ||
9103 | /* A jump/call destination will get adjusted to section+offset only | |
9104 | if both caller and callee are of the same type. */ | |
9105 | if (symbol_section_p (fixp->fx_addsy)) | |
9106 | break; | |
9107 | ||
9108 | if ((fixp->tc_fix_data.c64 | |
9109 | && !AARCH64_IS_C64 (fixp->fx_addsy)) | |
9110 | || (!fixp->tc_fix_data.c64 | |
9111 | && AARCH64_IS_C64 (fixp->fx_addsy))) | |
9112 | return 1; | |
9113 | ||
9114 | break; | |
9115 | ||
a06ea964 NC |
9116 | default: |
9117 | break; | |
9118 | } | |
9119 | ||
9120 | return generic_force_reloc (fixp); | |
9121 | } | |
9122 | ||
9123 | #ifdef OBJ_ELF | |
9124 | ||
3c0367d0 JW |
9125 | /* Implement md_after_parse_args. This is the earliest time we need to decide |
9126 | ABI. If no -mabi specified, the ABI will be decided by target triplet. */ | |
9127 | ||
9128 | void | |
9129 | aarch64_after_parse_args (void) | |
9130 | { | |
9131 | if (aarch64_abi != AARCH64_ABI_NONE) | |
9132 | return; | |
9133 | ||
9134 | /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */ | |
9135 | if (strlen (default_arch) > 7 && strcmp (default_arch + 7, ":32") == 0) | |
9136 | aarch64_abi = AARCH64_ABI_ILP32; | |
9137 | else | |
9138 | aarch64_abi = AARCH64_ABI_LP64; | |
9139 | } | |
9140 | ||
a06ea964 NC |
9141 | const char * |
9142 | elf64_aarch64_target_format (void) | |
9143 | { | |
12400dcc AM |
9144 | #ifdef TE_CLOUDABI |
9145 | /* FIXME: What to do for ilp32_p ? */ | |
9146 | if (target_big_endian) | |
9147 | return "elf64-bigaarch64-cloudabi"; | |
9148 | else | |
9149 | return "elf64-littleaarch64-cloudabi"; | |
9150 | #else | |
a06ea964 | 9151 | if (target_big_endian) |
cec5225b | 9152 | return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64"; |
a06ea964 | 9153 | else |
cec5225b | 9154 | return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64"; |
12400dcc | 9155 | #endif |
a06ea964 NC |
9156 | } |
9157 | ||
9158 | void | |
9159 | aarch64elf_frob_symbol (symbolS * symp, int *puntp) | |
9160 | { | |
9161 | elf_frob_symbol (symp, puntp); | |
9162 | } | |
9163 | #endif | |
9164 | ||
9165 | /* MD interface: Finalization. */ | |
9166 | ||
9167 | /* A good place to do this, although this was probably not intended | |
9168 | for this kind of use. We need to dump the literal pool before | |
9169 | references are made to a null symbol pointer. */ | |
9170 | ||
9171 | void | |
9172 | aarch64_cleanup (void) | |
9173 | { | |
9174 | literal_pool *pool; | |
9175 | ||
9176 | for (pool = list_of_pools; pool; pool = pool->next) | |
9177 | { | |
9178 | /* Put it at the end of the relevant section. */ | |
9179 | subseg_set (pool->section, pool->sub_section); | |
9180 | s_ltorg (0); | |
9181 | } | |
9182 | } | |
9183 | ||
9184 | #ifdef OBJ_ELF | |
9185 | /* Remove any excess mapping symbols generated for alignment frags in | |
9186 | SEC. We may have created a mapping symbol before a zero byte | |
9187 | alignment; remove it if there's a mapping symbol after the | |
9188 | alignment. */ | |
9189 | static void | |
9190 | check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec, | |
9191 | void *dummy ATTRIBUTE_UNUSED) | |
9192 | { | |
9193 | segment_info_type *seginfo = seg_info (sec); | |
9194 | fragS *fragp; | |
9195 | ||
9196 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
9197 | return; | |
9198 | ||
9199 | for (fragp = seginfo->frchainP->frch_root; | |
9200 | fragp != NULL; fragp = fragp->fr_next) | |
9201 | { | |
9202 | symbolS *sym = fragp->tc_frag_data.last_map; | |
9203 | fragS *next = fragp->fr_next; | |
9204 | ||
9205 | /* Variable-sized frags have been converted to fixed size by | |
9206 | this point. But if this was variable-sized to start with, | |
9207 | there will be a fixed-size frag after it. So don't handle | |
9208 | next == NULL. */ | |
9209 | if (sym == NULL || next == NULL) | |
9210 | continue; | |
9211 | ||
9212 | if (S_GET_VALUE (sym) < next->fr_address) | |
9213 | /* Not at the end of this frag. */ | |
9214 | continue; | |
9215 | know (S_GET_VALUE (sym) == next->fr_address); | |
9216 | ||
9217 | do | |
9218 | { | |
9219 | if (next->tc_frag_data.first_map != NULL) | |
9220 | { | |
9221 | /* Next frag starts with a mapping symbol. Discard this | |
9222 | one. */ | |
9223 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
9224 | break; | |
9225 | } | |
9226 | ||
9227 | if (next->fr_next == NULL) | |
9228 | { | |
9229 | /* This mapping symbol is at the end of the section. Discard | |
9230 | it. */ | |
9231 | know (next->fr_fix == 0 && next->fr_var == 0); | |
9232 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
9233 | break; | |
9234 | } | |
9235 | ||
9236 | /* As long as we have empty frags without any mapping symbols, | |
9237 | keep looking. */ | |
9238 | /* If the next frag is non-empty and does not start with a | |
9239 | mapping symbol, then this mapping symbol is required. */ | |
9240 | if (next->fr_address != next->fr_next->fr_address) | |
9241 | break; | |
9242 | ||
9243 | next = next->fr_next; | |
9244 | } | |
9245 | while (next != NULL); | |
9246 | } | |
9247 | } | |
9248 | #endif | |
9249 | ||
8b21361b SP |
9250 | /* Avoid relocations from using section symbols in some cases. */ |
9251 | bfd_boolean | |
9252 | aarch64_fix_adjustable (struct fix *fixP) | |
9253 | { | |
40bbb79e SP |
9254 | /* We need size information of the target symbols to initialise |
9255 | capabilities. */ | |
9256 | if (fixP->fx_r_type == BFD_RELOC_MORELLO_CAPINIT) | |
9257 | return FALSE; | |
9258 | ||
8b21361b SP |
9259 | switch (fixP->fx_r_type) |
9260 | { | |
f0070c1e SP |
9261 | /* We need to retain symbol information when jumping between A64 and C64 |
9262 | states or between two C64 functions. In the C64 -> C64 situation it's | |
9263 | really only a corner case that breaks when symbols get replaced with | |
9264 | section symbols; this is when the jump distance is longer than what a | |
9265 | branch instruction can handle and we want to branch through a stub. | |
9266 | In such a case, the linker needs to know the symbol types of the | |
9267 | source and the destination and section symbols are an unreliable | |
9268 | source of this information. */ | |
8b21361b SP |
9269 | case BFD_RELOC_AARCH64_ADR_LO21_PCREL: |
9270 | case BFD_RELOC_AARCH64_ADD_LO12: | |
9271 | case BFD_RELOC_AARCH64_BRANCH19: | |
9272 | case BFD_RELOC_AARCH64_TSTBR14: | |
9273 | case BFD_RELOC_AARCH64_JUMP26: | |
9274 | case BFD_RELOC_AARCH64_CALL26: | |
e19e9199 SP |
9275 | case BFD_RELOC_MORELLO_BRANCH19: |
9276 | case BFD_RELOC_MORELLO_TSTBR14: | |
9277 | case BFD_RELOC_MORELLO_JUMP26: | |
9278 | case BFD_RELOC_MORELLO_CALL26: | |
f0070c1e | 9279 | if (fixP->tc_fix_data.c64 || AARCH64_IS_C64 (fixP->fx_addsy)) |
8b21361b SP |
9280 | return FALSE; |
9281 | break; | |
9282 | default: | |
9283 | break; | |
9284 | } | |
9285 | ||
9286 | return TRUE; | |
9287 | } | |
9288 | ||
a06ea964 NC |
9289 | /* Adjust the symbol table. */ |
9290 | ||
9291 | void | |
9292 | aarch64_adjust_symtab (void) | |
9293 | { | |
9294 | #ifdef OBJ_ELF | |
8b21361b SP |
9295 | symbolS * sym; |
9296 | ||
9297 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
9298 | { | |
9299 | if (AARCH64_IS_C64 (sym) | |
9300 | && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION)) | |
9301 | { | |
9302 | elf_symbol_type * elf_sym; | |
9303 | ||
9304 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); | |
9305 | ||
9306 | if (!bfd_is_aarch64_special_symbol_name | |
9307 | (elf_sym->symbol.name, BFD_AARCH64_SPECIAL_SYM_TYPE_ANY)) | |
9308 | elf_sym->internal_elf_sym.st_target_internal = ST_BRANCH_TO_C64; | |
9309 | } | |
9310 | } | |
9311 | ||
a06ea964 NC |
9312 | /* Remove any overlapping mapping symbols generated by alignment frags. */ |
9313 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
9314 | /* Now do generic ELF adjustments. */ | |
9315 | elf_adjust_symtab (); | |
9316 | #endif | |
9317 | } | |
9318 | ||
9319 | static void | |
629310ab | 9320 | checked_hash_insert (htab_t table, const char *key, void *value) |
a06ea964 | 9321 | { |
fe0e921f | 9322 | str_hash_insert (table, key, value, 0); |
a06ea964 NC |
9323 | } |
9324 | ||
fa63795f | 9325 | static void |
629310ab | 9326 | sysreg_hash_insert (htab_t table, const char *key, void *value) |
fa63795f AC |
9327 | { |
9328 | gas_assert (strlen (key) < AARCH64_MAX_SYSREG_NAME_LEN); | |
9329 | checked_hash_insert (table, key, value); | |
9330 | } | |
9331 | ||
a06ea964 NC |
9332 | static void |
9333 | fill_instruction_hash_table (void) | |
9334 | { | |
9335 | aarch64_opcode *opcode = aarch64_opcode_table; | |
9336 | ||
9337 | while (opcode->name != NULL) | |
9338 | { | |
9339 | templates *templ, *new_templ; | |
629310ab | 9340 | templ = str_hash_find (aarch64_ops_hsh, opcode->name); |
a06ea964 | 9341 | |
add39d23 | 9342 | new_templ = XNEW (templates); |
a06ea964 NC |
9343 | new_templ->opcode = opcode; |
9344 | new_templ->next = NULL; | |
9345 | ||
9346 | if (!templ) | |
9347 | checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ); | |
9348 | else | |
9349 | { | |
9350 | new_templ->next = templ->next; | |
9351 | templ->next = new_templ; | |
9352 | } | |
9353 | ++opcode; | |
9354 | } | |
9355 | } | |
9356 | ||
9357 | static inline void | |
9358 | convert_to_upper (char *dst, const char *src, size_t num) | |
9359 | { | |
9360 | unsigned int i; | |
9361 | for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src) | |
9362 | *dst = TOUPPER (*src); | |
9363 | *dst = '\0'; | |
9364 | } | |
9365 | ||
9366 | /* Assume STR point to a lower-case string, allocate, convert and return | |
9367 | the corresponding upper-case string. */ | |
9368 | static inline const char* | |
9369 | get_upper_str (const char *str) | |
9370 | { | |
9371 | char *ret; | |
9372 | size_t len = strlen (str); | |
325801bd | 9373 | ret = XNEWVEC (char, len + 1); |
a06ea964 NC |
9374 | convert_to_upper (ret, str, len); |
9375 | return ret; | |
9376 | } | |
9377 | ||
9378 | /* MD interface: Initialization. */ | |
9379 | ||
9380 | void | |
9381 | md_begin (void) | |
9382 | { | |
9383 | unsigned mach; | |
9384 | unsigned int i; | |
9385 | ||
f16c3d4f AM |
9386 | aarch64_ops_hsh = str_htab_create (); |
9387 | aarch64_cond_hsh = str_htab_create (); | |
9388 | aarch64_shift_hsh = str_htab_create (); | |
9389 | aarch64_sys_regs_hsh = str_htab_create (); | |
9390 | aarch64_pstatefield_hsh = str_htab_create (); | |
9391 | aarch64_sys_regs_ic_hsh = str_htab_create (); | |
9392 | aarch64_sys_regs_dc_hsh = str_htab_create (); | |
9393 | aarch64_sys_regs_at_hsh = str_htab_create (); | |
9394 | aarch64_sys_regs_tlbi_hsh = str_htab_create (); | |
9395 | aarch64_sys_regs_sr_hsh = str_htab_create (); | |
9396 | aarch64_reg_hsh = str_htab_create (); | |
9397 | aarch64_barrier_opt_hsh = str_htab_create (); | |
9398 | aarch64_nzcv_hsh = str_htab_create (); | |
9399 | aarch64_pldop_hsh = str_htab_create (); | |
9400 | aarch64_hint_opt_hsh = str_htab_create (); | |
a06ea964 NC |
9401 | |
9402 | fill_instruction_hash_table (); | |
9403 | ||
9404 | for (i = 0; aarch64_sys_regs[i].name != NULL; ++i) | |
fa63795f | 9405 | sysreg_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name, |
a06ea964 NC |
9406 | (void *) (aarch64_sys_regs + i)); |
9407 | ||
9408 | for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) | |
fa63795f | 9409 | sysreg_hash_insert (aarch64_pstatefield_hsh, |
a06ea964 NC |
9410 | aarch64_pstatefields[i].name, |
9411 | (void *) (aarch64_pstatefields + i)); | |
9412 | ||
875880c6 | 9413 | for (i = 0; aarch64_sys_regs_ic[i].name != NULL; i++) |
fa63795f | 9414 | sysreg_hash_insert (aarch64_sys_regs_ic_hsh, |
875880c6 | 9415 | aarch64_sys_regs_ic[i].name, |
a06ea964 NC |
9416 | (void *) (aarch64_sys_regs_ic + i)); |
9417 | ||
875880c6 | 9418 | for (i = 0; aarch64_sys_regs_dc[i].name != NULL; i++) |
fa63795f | 9419 | sysreg_hash_insert (aarch64_sys_regs_dc_hsh, |
875880c6 | 9420 | aarch64_sys_regs_dc[i].name, |
a06ea964 NC |
9421 | (void *) (aarch64_sys_regs_dc + i)); |
9422 | ||
875880c6 | 9423 | for (i = 0; aarch64_sys_regs_at[i].name != NULL; i++) |
fa63795f | 9424 | sysreg_hash_insert (aarch64_sys_regs_at_hsh, |
875880c6 | 9425 | aarch64_sys_regs_at[i].name, |
a06ea964 NC |
9426 | (void *) (aarch64_sys_regs_at + i)); |
9427 | ||
875880c6 | 9428 | for (i = 0; aarch64_sys_regs_tlbi[i].name != NULL; i++) |
fa63795f | 9429 | sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh, |
875880c6 | 9430 | aarch64_sys_regs_tlbi[i].name, |
a06ea964 NC |
9431 | (void *) (aarch64_sys_regs_tlbi + i)); |
9432 | ||
2ac435d4 | 9433 | for (i = 0; aarch64_sys_regs_sr[i].name != NULL; i++) |
fa63795f | 9434 | sysreg_hash_insert (aarch64_sys_regs_sr_hsh, |
2ac435d4 SD |
9435 | aarch64_sys_regs_sr[i].name, |
9436 | (void *) (aarch64_sys_regs_sr + i)); | |
9437 | ||
a06ea964 NC |
9438 | for (i = 0; i < ARRAY_SIZE (reg_names); i++) |
9439 | checked_hash_insert (aarch64_reg_hsh, reg_names[i].name, | |
9440 | (void *) (reg_names + i)); | |
9441 | ||
9442 | for (i = 0; i < ARRAY_SIZE (nzcv_names); i++) | |
9443 | checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template, | |
9444 | (void *) (nzcv_names + i)); | |
9445 | ||
9446 | for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++) | |
9447 | { | |
9448 | const char *name = aarch64_operand_modifiers[i].name; | |
9449 | checked_hash_insert (aarch64_shift_hsh, name, | |
9450 | (void *) (aarch64_operand_modifiers + i)); | |
9451 | /* Also hash the name in the upper case. */ | |
9452 | checked_hash_insert (aarch64_shift_hsh, get_upper_str (name), | |
9453 | (void *) (aarch64_operand_modifiers + i)); | |
9454 | } | |
9455 | ||
9456 | for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++) | |
9457 | { | |
9458 | unsigned int j; | |
9459 | /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are | |
9460 | the same condition code. */ | |
9461 | for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j) | |
9462 | { | |
9463 | const char *name = aarch64_conds[i].names[j]; | |
9464 | if (name == NULL) | |
9465 | break; | |
9466 | checked_hash_insert (aarch64_cond_hsh, name, | |
9467 | (void *) (aarch64_conds + i)); | |
9468 | /* Also hash the name in the upper case. */ | |
9469 | checked_hash_insert (aarch64_cond_hsh, get_upper_str (name), | |
9470 | (void *) (aarch64_conds + i)); | |
9471 | } | |
9472 | } | |
9473 | ||
9474 | for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++) | |
9475 | { | |
9476 | const char *name = aarch64_barrier_options[i].name; | |
9477 | /* Skip xx00 - the unallocated values of option. */ | |
9478 | if ((i & 0x3) == 0) | |
9479 | continue; | |
9480 | checked_hash_insert (aarch64_barrier_opt_hsh, name, | |
9481 | (void *) (aarch64_barrier_options + i)); | |
9482 | /* Also hash the name in the upper case. */ | |
9483 | checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name), | |
9484 | (void *) (aarch64_barrier_options + i)); | |
9485 | } | |
9486 | ||
9487 | for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++) | |
9488 | { | |
9489 | const char* name = aarch64_prfops[i].name; | |
a1ccaec9 YZ |
9490 | /* Skip the unallocated hint encodings. */ |
9491 | if (name == NULL) | |
a06ea964 NC |
9492 | continue; |
9493 | checked_hash_insert (aarch64_pldop_hsh, name, | |
9494 | (void *) (aarch64_prfops + i)); | |
9495 | /* Also hash the name in the upper case. */ | |
9496 | checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name), | |
9497 | (void *) (aarch64_prfops + i)); | |
9498 | } | |
9499 | ||
1e6f4800 MW |
9500 | for (i = 0; aarch64_hint_options[i].name != NULL; i++) |
9501 | { | |
9502 | const char* name = aarch64_hint_options[i].name; | |
0a821c4f | 9503 | const char* upper_name = get_upper_str(name); |
1e6f4800 MW |
9504 | |
9505 | checked_hash_insert (aarch64_hint_opt_hsh, name, | |
9506 | (void *) (aarch64_hint_options + i)); | |
0a821c4f AP |
9507 | |
9508 | /* Also hash the name in the upper case if not the same. */ | |
9509 | if (strcmp (name, upper_name) != 0) | |
9510 | checked_hash_insert (aarch64_hint_opt_hsh, upper_name, | |
9511 | (void *) (aarch64_hint_options + i)); | |
1e6f4800 MW |
9512 | } |
9513 | ||
a06ea964 NC |
9514 | /* Set the cpu variant based on the command-line options. */ |
9515 | if (!mcpu_cpu_opt) | |
9516 | mcpu_cpu_opt = march_cpu_opt; | |
9517 | ||
9518 | if (!mcpu_cpu_opt) | |
9519 | mcpu_cpu_opt = &cpu_default; | |
9520 | ||
9521 | cpu_variant = *mcpu_cpu_opt; | |
9522 | ||
9523 | /* Record the CPU type. */ | |
cec5225b | 9524 | mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64; |
a06ea964 NC |
9525 | |
9526 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
9527 | } | |
9528 | ||
9529 | /* Command line processing. */ | |
9530 | ||
9531 | const char *md_shortopts = "m:"; | |
9532 | ||
9533 | #ifdef AARCH64_BI_ENDIAN | |
9534 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
9535 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
9536 | #else | |
9537 | #if TARGET_BYTES_BIG_ENDIAN | |
9538 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
9539 | #else | |
9540 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
9541 | #endif | |
9542 | #endif | |
9543 | ||
9544 | struct option md_longopts[] = { | |
9545 | #ifdef OPTION_EB | |
9546 | {"EB", no_argument, NULL, OPTION_EB}, | |
9547 | #endif | |
9548 | #ifdef OPTION_EL | |
9549 | {"EL", no_argument, NULL, OPTION_EL}, | |
9550 | #endif | |
9551 | {NULL, no_argument, NULL, 0} | |
9552 | }; | |
9553 | ||
9554 | size_t md_longopts_size = sizeof (md_longopts); | |
9555 | ||
9556 | struct aarch64_option_table | |
9557 | { | |
e0471c16 TS |
9558 | const char *option; /* Option name to match. */ |
9559 | const char *help; /* Help information. */ | |
a06ea964 NC |
9560 | int *var; /* Variable to change. */ |
9561 | int value; /* What to change it to. */ | |
9562 | char *deprecated; /* If non-null, print this message. */ | |
9563 | }; | |
9564 | ||
9565 | static struct aarch64_option_table aarch64_opts[] = { | |
9566 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
9567 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
9568 | NULL}, | |
9569 | #ifdef DEBUG_AARCH64 | |
9570 | {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL}, | |
9571 | #endif /* DEBUG_AARCH64 */ | |
9572 | {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1, | |
9573 | NULL}, | |
a52e6fd3 YZ |
9574 | {"mno-verbose-error", N_("do not output verbose error messages"), |
9575 | &verbose_error_p, 0, NULL}, | |
a06ea964 NC |
9576 | {NULL, NULL, NULL, 0, NULL} |
9577 | }; | |
9578 | ||
9579 | struct aarch64_cpu_option_table | |
9580 | { | |
e0471c16 | 9581 | const char *name; |
a06ea964 NC |
9582 | const aarch64_feature_set value; |
9583 | /* The canonical name of the CPU, or NULL to use NAME converted to upper | |
9584 | case. */ | |
9585 | const char *canonical_name; | |
9586 | }; | |
9587 | ||
9588 | /* This list should, at a minimum, contain all the cpu names | |
9589 | recognized by GCC. */ | |
9590 | static const struct aarch64_cpu_option_table aarch64_cpus[] = { | |
9591 | {"all", AARCH64_ANY, NULL}, | |
546053ac DZ |
9592 | {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8, |
9593 | AARCH64_FEATURE_CRC), "Cortex-A34"}, | |
9c352f1c JG |
9594 | {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8, |
9595 | AARCH64_FEATURE_CRC), "Cortex-A35"}, | |
aa31c464 JW |
9596 | {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8, |
9597 | AARCH64_FEATURE_CRC), "Cortex-A53"}, | |
9598 | {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8, | |
9599 | AARCH64_FEATURE_CRC), "Cortex-A57"}, | |
2abdd192 JW |
9600 | {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8, |
9601 | AARCH64_FEATURE_CRC), "Cortex-A72"}, | |
1aa70332 KT |
9602 | {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8, |
9603 | AARCH64_FEATURE_CRC), "Cortex-A73"}, | |
1e292627 | 9604 | {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2, |
1c5c938a | 9605 | AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD), |
1e292627 JG |
9606 | "Cortex-A55"}, |
9607 | {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2, | |
1c5c938a | 9608 | AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD), |
1e292627 | 9609 | "Cortex-A75"}, |
c2a0f929 | 9610 | {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2, |
9611 | AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD), | |
9612 | "Cortex-A76"}, | |
546053ac DZ |
9613 | {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2, |
9614 | AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC | |
9615 | | AARCH64_FEATURE_DOTPROD | |
9616 | | AARCH64_FEATURE_SSBS), | |
9617 | "Cortex-A76AE"}, | |
9618 | {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2, | |
9619 | AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC | |
9620 | | AARCH64_FEATURE_DOTPROD | |
9621 | | AARCH64_FEATURE_SSBS), | |
9622 | "Cortex-A77"}, | |
9623 | {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2, | |
9624 | AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC | |
9625 | | AARCH64_FEATURE_DOTPROD | |
9626 | | AARCH64_FEATURE_SSBS), | |
9627 | "Cortex-A65"}, | |
9628 | {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2, | |
9629 | AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC | |
9630 | | AARCH64_FEATURE_DOTPROD | |
9631 | | AARCH64_FEATURE_SSBS), | |
9632 | "Cortex-A65AE"}, | |
77718e5b PW |
9633 | {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2, |
9634 | AARCH64_FEATURE_F16 | |
9635 | | AARCH64_FEATURE_RCPC | |
9636 | | AARCH64_FEATURE_DOTPROD | |
9637 | | AARCH64_FEATURE_SSBS | |
9638 | | AARCH64_FEATURE_PROFILE), | |
9639 | "Cortex-A78"}, | |
9640 | {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2, | |
9641 | AARCH64_FEATURE_F16 | |
9642 | | AARCH64_FEATURE_RCPC | |
9643 | | AARCH64_FEATURE_DOTPROD | |
9644 | | AARCH64_FEATURE_SSBS | |
9645 | | AARCH64_FEATURE_PROFILE), | |
9646 | "Cortex-A78AE"}, | |
c8fcc360 KT |
9647 | {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2, |
9648 | AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | |
9649 | | AARCH64_FEATURE_DOTPROD | |
9650 | | AARCH64_FEATURE_PROFILE), | |
9651 | "Ares"}, | |
2412d878 EM |
9652 | {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8, |
9653 | AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), | |
9654 | "Samsung Exynos M1"}, | |
2fe9c2a0 | 9655 | {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8, |
e58ff055 JW |
9656 | AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO |
9657 | | AARCH64_FEATURE_RDMA), | |
2fe9c2a0 | 9658 | "Qualcomm Falkor"}, |
516dbc44 KT |
9659 | {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2, |
9660 | AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | |
9661 | | AARCH64_FEATURE_DOTPROD | |
9662 | | AARCH64_FEATURE_SSBS), | |
9663 | "Neoverse E1"}, | |
38e75bf2 KT |
9664 | {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2, |
9665 | AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | |
9666 | | AARCH64_FEATURE_DOTPROD | |
9667 | | AARCH64_FEATURE_PROFILE), | |
9668 | "Neoverse N1"}, | |
990e5268 AC |
9669 | {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5, |
9670 | AARCH64_FEATURE_BFLOAT16 | |
9671 | | AARCH64_FEATURE_I8MM | |
9672 | | AARCH64_FEATURE_F16 | |
9673 | | AARCH64_FEATURE_SVE | |
9674 | | AARCH64_FEATURE_SVE2 | |
9675 | | AARCH64_FEATURE_SVE2_BITPERM | |
9676 | | AARCH64_FEATURE_MEMTAG | |
9677 | | AARCH64_FEATURE_RNG), | |
9678 | "Neoverse N2"}, | |
c769fd6a AC |
9679 | {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4, |
9680 | AARCH64_FEATURE_PROFILE | |
9681 | | AARCH64_FEATURE_CVADP | |
9682 | | AARCH64_FEATURE_SVE | |
9683 | | AARCH64_FEATURE_SSBS | |
9684 | | AARCH64_FEATURE_RNG | |
9685 | | AARCH64_FEATURE_F16 | |
9686 | | AARCH64_FEATURE_BFLOAT16 | |
9687 | | AARCH64_FEATURE_I8MM), "Neoverse V1"}, | |
6b21c2bf | 9688 | {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8, |
e58ff055 JW |
9689 | AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO |
9690 | | AARCH64_FEATURE_RDMA), | |
6b21c2bf | 9691 | "Qualcomm QDF24XX"}, |
eb5c42e5 | 9692 | {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4, |
7605d944 SP |
9693 | AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_PROFILE), |
9694 | "Qualcomm Saphira"}, | |
faade851 JW |
9695 | {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8, |
9696 | AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), | |
9697 | "Cavium ThunderX"}, | |
9f99c22e VP |
9698 | {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1, |
9699 | AARCH64_FEATURE_CRYPTO), | |
0a8be2fe | 9700 | "Broadcom Vulcan"}, |
070cb956 PT |
9701 | /* The 'xgene-1' name is an older name for 'xgene1', which was used |
9702 | in earlier releases and is superseded by 'xgene1' in all | |
9703 | tools. */ | |
9877c63c | 9704 | {"xgene-1", AARCH64_ARCH_V8, "APM X-Gene 1"}, |
070cb956 | 9705 | {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"}, |
aa31c464 JW |
9706 | {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8, |
9707 | AARCH64_FEATURE_CRC), "APM X-Gene 2"}, | |
f1363b0f | 9708 | {"cortex-r82", AARCH64_ARCH_V8_R, "Cortex-R82"}, |
47e1f9de | 9709 | {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2, |
f9b1d75e PW |
9710 | AARCH64_FEATURE_F16 |
9711 | | AARCH64_FEATURE_RCPC | |
9712 | | AARCH64_FEATURE_DOTPROD | |
9713 | | AARCH64_FEATURE_SSBS | |
9714 | | AARCH64_FEATURE_PROFILE), | |
9715 | "Cortex-X1"}, | |
a06ea964 NC |
9716 | {"generic", AARCH64_ARCH_V8, NULL}, |
9717 | ||
a06ea964 NC |
9718 | {NULL, AARCH64_ARCH_NONE, NULL} |
9719 | }; | |
9720 | ||
9721 | struct aarch64_arch_option_table | |
9722 | { | |
e0471c16 | 9723 | const char *name; |
a06ea964 NC |
9724 | const aarch64_feature_set value; |
9725 | }; | |
9726 | ||
9727 | /* This list should, at a minimum, contain all the architecture names | |
9728 | recognized by GCC. */ | |
9729 | static const struct aarch64_arch_option_table aarch64_archs[] = { | |
9730 | {"all", AARCH64_ANY}, | |
5a1ad39d | 9731 | {"armv8-a", AARCH64_ARCH_V8}, |
88f0ea34 | 9732 | {"armv8.1-a", AARCH64_ARCH_V8_1}, |
acb787b0 | 9733 | {"armv8.2-a", AARCH64_ARCH_V8_2}, |
1924ff75 | 9734 | {"armv8.3-a", AARCH64_ARCH_V8_3}, |
b6b9ca0c | 9735 | {"armv8.4-a", AARCH64_ARCH_V8_4}, |
70d56181 | 9736 | {"armv8.5-a", AARCH64_ARCH_V8_5}, |
8ae2d3d9 | 9737 | {"armv8.6-a", AARCH64_ARCH_V8_6}, |
95830c98 | 9738 | {"armv8-r", AARCH64_ARCH_V8_R}, |
3493da5c | 9739 | {"morello", AARCH64_ARCH_MORELLO}, |
a06ea964 NC |
9740 | {NULL, AARCH64_ARCH_NONE} |
9741 | }; | |
9742 | ||
9743 | /* ISA extensions. */ | |
9744 | struct aarch64_option_cpu_value_table | |
9745 | { | |
e0471c16 | 9746 | const char *name; |
a06ea964 | 9747 | const aarch64_feature_set value; |
93d8990c | 9748 | const aarch64_feature_set require; /* Feature dependencies. */ |
a06ea964 NC |
9749 | }; |
9750 | ||
9751 | static const struct aarch64_option_cpu_value_table aarch64_features[] = { | |
93d8990c SN |
9752 | {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0), |
9753 | AARCH64_ARCH_NONE}, | |
2dc4b12f | 9754 | {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0), |
fa09f4ea | 9755 | AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)}, |
93d8990c SN |
9756 | {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0), |
9757 | AARCH64_ARCH_NONE}, | |
9758 | {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0), | |
9759 | AARCH64_ARCH_NONE}, | |
9760 | {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0), | |
fa09f4ea | 9761 | AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)}, |
93d8990c SN |
9762 | {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0), |
9763 | AARCH64_ARCH_NONE}, | |
9764 | {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0), | |
9765 | AARCH64_ARCH_NONE}, | |
9766 | {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0), | |
9767 | AARCH64_ARCH_NONE}, | |
9768 | {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0), | |
9769 | AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)}, | |
9770 | {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16, 0), | |
9771 | AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)}, | |
d0f7791c TC |
9772 | {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML, 0), |
9773 | AARCH64_FEATURE (AARCH64_FEATURE_FP | |
9774 | | AARCH64_FEATURE_F16, 0)}, | |
93d8990c SN |
9775 | {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0), |
9776 | AARCH64_ARCH_NONE}, | |
c0890d26 | 9777 | {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0), |
582e12bf RS |
9778 | AARCH64_FEATURE (AARCH64_FEATURE_F16 |
9779 | | AARCH64_FEATURE_SIMD | |
9780 | | AARCH64_FEATURE_COMPNUM, 0)}, | |
b83b4b13 SD |
9781 | {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME, 0), |
9782 | AARCH64_ARCH_NONE}, | |
f482d304 RS |
9783 | {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0), |
9784 | AARCH64_FEATURE (AARCH64_FEATURE_F16 | |
9785 | | AARCH64_FEATURE_SIMD, 0)}, | |
d74d4880 SN |
9786 | {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0), |
9787 | AARCH64_ARCH_NONE}, | |
65a55fbb TC |
9788 | {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD, 0), |
9789 | AARCH64_ARCH_NONE}, | |
c0e7cef7 NC |
9790 | {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2, 0), |
9791 | AARCH64_ARCH_NONE}, | |
68dfbb92 SD |
9792 | {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB, 0), |
9793 | AARCH64_ARCH_NONE}, | |
2ac435d4 SD |
9794 | {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0), |
9795 | AARCH64_ARCH_NONE}, | |
c0e7cef7 NC |
9796 | {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES, 0), |
9797 | AARCH64_ARCH_NONE}, | |
b6b9ca0c TC |
9798 | {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0), |
9799 | AARCH64_ARCH_NONE}, | |
d4340f89 JB |
9800 | {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3, 0), |
9801 | AARCH64_FEATURE (AARCH64_FEATURE_SHA2, 0)}, | |
af4bcb4c SD |
9802 | {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0), |
9803 | AARCH64_ARCH_NONE}, | |
104fefee SD |
9804 | {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0), |
9805 | AARCH64_ARCH_NONE}, | |
73b605ec SD |
9806 | {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0), |
9807 | AARCH64_ARCH_NONE}, | |
7ce2460a MM |
9808 | {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0), |
9809 | AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)}, | |
9810 | {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4, 0), | |
9811 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | |
9812 | | AARCH64_FEATURE_SM4, 0)}, | |
9813 | {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES, 0), | |
9814 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | |
9815 | | AARCH64_FEATURE_AES, 0)}, | |
9816 | {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3, 0), | |
9817 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | |
9818 | | AARCH64_FEATURE_SHA3, 0)}, | |
ccbdd22f | 9819 | {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0), |
7ce2460a | 9820 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)}, |
df678013 MM |
9821 | {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0), |
9822 | AARCH64_ARCH_NONE}, | |
8382113f MM |
9823 | {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0), |
9824 | AARCH64_ARCH_NONE}, | |
9825 | {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM, 0), | |
82e9597c | 9826 | AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)}, |
8382113f | 9827 | {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0), |
82e9597c | 9828 | AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)}, |
3493da5c SP |
9829 | {"a64c", AARCH64_FEATURE (AARCH64_FEATURE_A64C, 0), |
9830 | AARCH64_ARCH_NONE}, | |
9831 | {"c64", AARCH64_FEATURE (AARCH64_FEATURE_C64, 0), | |
9832 | AARCH64_FEATURE (AARCH64_FEATURE_A64C, 0)}, | |
93d8990c | 9833 | {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE}, |
a06ea964 NC |
9834 | }; |
9835 | ||
9836 | struct aarch64_long_option_table | |
9837 | { | |
e0471c16 TS |
9838 | const char *option; /* Substring to match. */ |
9839 | const char *help; /* Help information. */ | |
17b9d67d | 9840 | int (*func) (const char *subopt); /* Function to decode sub-option. */ |
a06ea964 NC |
9841 | char *deprecated; /* If non-null, print this message. */ |
9842 | }; | |
9843 | ||
93d8990c SN |
9844 | /* Transitive closure of features depending on set. */ |
9845 | static aarch64_feature_set | |
9846 | aarch64_feature_disable_set (aarch64_feature_set set) | |
9847 | { | |
9848 | const struct aarch64_option_cpu_value_table *opt; | |
9849 | aarch64_feature_set prev = 0; | |
9850 | ||
9851 | while (prev != set) { | |
9852 | prev = set; | |
9853 | for (opt = aarch64_features; opt->name != NULL; opt++) | |
9854 | if (AARCH64_CPU_HAS_ANY_FEATURES (opt->require, set)) | |
9855 | AARCH64_MERGE_FEATURE_SETS (set, set, opt->value); | |
9856 | } | |
9857 | return set; | |
9858 | } | |
9859 | ||
9860 | /* Transitive closure of dependencies of set. */ | |
9861 | static aarch64_feature_set | |
9862 | aarch64_feature_enable_set (aarch64_feature_set set) | |
9863 | { | |
9864 | const struct aarch64_option_cpu_value_table *opt; | |
9865 | aarch64_feature_set prev = 0; | |
9866 | ||
9867 | while (prev != set) { | |
9868 | prev = set; | |
9869 | for (opt = aarch64_features; opt->name != NULL; opt++) | |
9870 | if (AARCH64_CPU_HAS_FEATURE (set, opt->value)) | |
9871 | AARCH64_MERGE_FEATURE_SETS (set, set, opt->require); | |
9872 | } | |
9873 | return set; | |
9874 | } | |
9875 | ||
a06ea964 | 9876 | static int |
82b8a785 | 9877 | aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p, |
ae527cd8 | 9878 | bfd_boolean ext_only) |
a06ea964 NC |
9879 | { |
9880 | /* We insist on extensions being added before being removed. We achieve | |
9881 | this by using the ADDING_VALUE variable to indicate whether we are | |
9882 | adding an extension (1) or removing it (0) and only allowing it to | |
9883 | change in the order -1 -> 1 -> 0. */ | |
9884 | int adding_value = -1; | |
325801bd | 9885 | aarch64_feature_set *ext_set = XNEW (aarch64_feature_set); |
a06ea964 NC |
9886 | |
9887 | /* Copy the feature set, so that we can modify it. */ | |
9888 | *ext_set = **opt_p; | |
9889 | *opt_p = ext_set; | |
9890 | ||
9891 | while (str != NULL && *str != 0) | |
9892 | { | |
9893 | const struct aarch64_option_cpu_value_table *opt; | |
82b8a785 | 9894 | const char *ext = NULL; |
a06ea964 NC |
9895 | int optlen; |
9896 | ||
ae527cd8 | 9897 | if (!ext_only) |
a06ea964 | 9898 | { |
ae527cd8 JB |
9899 | if (*str != '+') |
9900 | { | |
9901 | as_bad (_("invalid architectural extension")); | |
9902 | return 0; | |
9903 | } | |
a06ea964 | 9904 | |
ae527cd8 JB |
9905 | ext = strchr (++str, '+'); |
9906 | } | |
a06ea964 NC |
9907 | |
9908 | if (ext != NULL) | |
9909 | optlen = ext - str; | |
9910 | else | |
9911 | optlen = strlen (str); | |
9912 | ||
9913 | if (optlen >= 2 && strncmp (str, "no", 2) == 0) | |
9914 | { | |
9915 | if (adding_value != 0) | |
9916 | adding_value = 0; | |
9917 | optlen -= 2; | |
9918 | str += 2; | |
9919 | } | |
9920 | else if (optlen > 0) | |
9921 | { | |
9922 | if (adding_value == -1) | |
9923 | adding_value = 1; | |
9924 | else if (adding_value != 1) | |
9925 | { | |
9926 | as_bad (_("must specify extensions to add before specifying " | |
9927 | "those to remove")); | |
9928 | return FALSE; | |
9929 | } | |
9930 | } | |
9931 | ||
9932 | if (optlen == 0) | |
9933 | { | |
9934 | as_bad (_("missing architectural extension")); | |
9935 | return 0; | |
9936 | } | |
9937 | ||
9938 | gas_assert (adding_value != -1); | |
9939 | ||
9940 | for (opt = aarch64_features; opt->name != NULL; opt++) | |
9941 | if (strncmp (opt->name, str, optlen) == 0) | |
9942 | { | |
93d8990c SN |
9943 | aarch64_feature_set set; |
9944 | ||
a06ea964 NC |
9945 | /* Add or remove the extension. */ |
9946 | if (adding_value) | |
93d8990c SN |
9947 | { |
9948 | set = aarch64_feature_enable_set (opt->value); | |
9949 | AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, set); | |
9950 | } | |
a06ea964 | 9951 | else |
93d8990c SN |
9952 | { |
9953 | set = aarch64_feature_disable_set (opt->value); | |
9954 | AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, set); | |
9955 | } | |
a06ea964 NC |
9956 | break; |
9957 | } | |
9958 | ||
9959 | if (opt->name == NULL) | |
9960 | { | |
9961 | as_bad (_("unknown architectural extension `%s'"), str); | |
9962 | return 0; | |
9963 | } | |
9964 | ||
9965 | str = ext; | |
9966 | }; | |
9967 | ||
9968 | return 1; | |
9969 | } | |
9970 | ||
9971 | static int | |
17b9d67d | 9972 | aarch64_parse_cpu (const char *str) |
a06ea964 NC |
9973 | { |
9974 | const struct aarch64_cpu_option_table *opt; | |
82b8a785 | 9975 | const char *ext = strchr (str, '+'); |
a06ea964 NC |
9976 | size_t optlen; |
9977 | ||
9978 | if (ext != NULL) | |
9979 | optlen = ext - str; | |
9980 | else | |
9981 | optlen = strlen (str); | |
9982 | ||
9983 | if (optlen == 0) | |
9984 | { | |
9985 | as_bad (_("missing cpu name `%s'"), str); | |
9986 | return 0; | |
9987 | } | |
9988 | ||
9989 | for (opt = aarch64_cpus; opt->name != NULL; opt++) | |
9990 | if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0) | |
9991 | { | |
9992 | mcpu_cpu_opt = &opt->value; | |
9993 | if (ext != NULL) | |
ae527cd8 | 9994 | return aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE); |
a06ea964 NC |
9995 | |
9996 | return 1; | |
9997 | } | |
9998 | ||
9999 | as_bad (_("unknown cpu `%s'"), str); | |
10000 | return 0; | |
10001 | } | |
10002 | ||
10003 | static int | |
17b9d67d | 10004 | aarch64_parse_arch (const char *str) |
a06ea964 NC |
10005 | { |
10006 | const struct aarch64_arch_option_table *opt; | |
82b8a785 | 10007 | const char *ext = strchr (str, '+'); |
a06ea964 NC |
10008 | size_t optlen; |
10009 | ||
10010 | if (ext != NULL) | |
10011 | optlen = ext - str; | |
10012 | else | |
10013 | optlen = strlen (str); | |
10014 | ||
10015 | if (optlen == 0) | |
10016 | { | |
10017 | as_bad (_("missing architecture name `%s'"), str); | |
10018 | return 0; | |
10019 | } | |
10020 | ||
10021 | for (opt = aarch64_archs; opt->name != NULL; opt++) | |
10022 | if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0) | |
10023 | { | |
10024 | march_cpu_opt = &opt->value; | |
10025 | if (ext != NULL) | |
ae527cd8 | 10026 | return aarch64_parse_features (ext, &march_cpu_opt, FALSE); |
a06ea964 NC |
10027 | |
10028 | return 1; | |
10029 | } | |
10030 | ||
10031 | as_bad (_("unknown architecture `%s'\n"), str); | |
10032 | return 0; | |
10033 | } | |
10034 | ||
69091a2c YZ |
10035 | /* ABIs. */ |
10036 | struct aarch64_option_abi_value_table | |
10037 | { | |
e0471c16 | 10038 | const char *name; |
69091a2c YZ |
10039 | enum aarch64_abi_type value; |
10040 | }; | |
10041 | ||
10042 | static const struct aarch64_option_abi_value_table aarch64_abis[] = { | |
10043 | {"ilp32", AARCH64_ABI_ILP32}, | |
10044 | {"lp64", AARCH64_ABI_LP64}, | |
69091a2c YZ |
10045 | }; |
10046 | ||
10047 | static int | |
17b9d67d | 10048 | aarch64_parse_abi (const char *str) |
69091a2c | 10049 | { |
5703197e | 10050 | unsigned int i; |
69091a2c | 10051 | |
5703197e | 10052 | if (str[0] == '\0') |
69091a2c YZ |
10053 | { |
10054 | as_bad (_("missing abi name `%s'"), str); | |
10055 | return 0; | |
10056 | } | |
10057 | ||
5703197e TS |
10058 | for (i = 0; i < ARRAY_SIZE (aarch64_abis); i++) |
10059 | if (strcmp (str, aarch64_abis[i].name) == 0) | |
69091a2c | 10060 | { |
5703197e | 10061 | aarch64_abi = aarch64_abis[i].value; |
69091a2c YZ |
10062 | return 1; |
10063 | } | |
10064 | ||
10065 | as_bad (_("unknown abi `%s'\n"), str); | |
10066 | return 0; | |
10067 | } | |
10068 | ||
a06ea964 | 10069 | static struct aarch64_long_option_table aarch64_long_opts[] = { |
69091a2c YZ |
10070 | #ifdef OBJ_ELF |
10071 | {"mabi=", N_("<abi name>\t specify for ABI <abi name>"), | |
10072 | aarch64_parse_abi, NULL}, | |
10073 | #endif /* OBJ_ELF */ | |
a06ea964 NC |
10074 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), |
10075 | aarch64_parse_cpu, NULL}, | |
10076 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
10077 | aarch64_parse_arch, NULL}, | |
10078 | {NULL, NULL, 0, NULL} | |
10079 | }; | |
10080 | ||
10081 | int | |
17b9d67d | 10082 | md_parse_option (int c, const char *arg) |
a06ea964 NC |
10083 | { |
10084 | struct aarch64_option_table *opt; | |
10085 | struct aarch64_long_option_table *lopt; | |
10086 | ||
10087 | switch (c) | |
10088 | { | |
10089 | #ifdef OPTION_EB | |
10090 | case OPTION_EB: | |
10091 | target_big_endian = 1; | |
10092 | break; | |
10093 | #endif | |
10094 | ||
10095 | #ifdef OPTION_EL | |
10096 | case OPTION_EL: | |
10097 | target_big_endian = 0; | |
10098 | break; | |
10099 | #endif | |
10100 | ||
10101 | case 'a': | |
10102 | /* Listing option. Just ignore these, we don't support additional | |
10103 | ones. */ | |
10104 | return 0; | |
10105 | ||
10106 | default: | |
10107 | for (opt = aarch64_opts; opt->option != NULL; opt++) | |
10108 | { | |
10109 | if (c == opt->option[0] | |
10110 | && ((arg == NULL && opt->option[1] == 0) | |
10111 | || streq (arg, opt->option + 1))) | |
10112 | { | |
10113 | /* If the option is deprecated, tell the user. */ | |
10114 | if (opt->deprecated != NULL) | |
10115 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
10116 | arg ? arg : "", _(opt->deprecated)); | |
10117 | ||
10118 | if (opt->var != NULL) | |
10119 | *opt->var = opt->value; | |
10120 | ||
10121 | return 1; | |
10122 | } | |
10123 | } | |
10124 | ||
10125 | for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++) | |
10126 | { | |
10127 | /* These options are expected to have an argument. */ | |
10128 | if (c == lopt->option[0] | |
10129 | && arg != NULL | |
10130 | && strncmp (arg, lopt->option + 1, | |
10131 | strlen (lopt->option + 1)) == 0) | |
10132 | { | |
10133 | /* If the option is deprecated, tell the user. */ | |
10134 | if (lopt->deprecated != NULL) | |
10135 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, | |
10136 | _(lopt->deprecated)); | |
10137 | ||
10138 | /* Call the sup-option parser. */ | |
10139 | return lopt->func (arg + strlen (lopt->option) - 1); | |
10140 | } | |
10141 | } | |
10142 | ||
10143 | return 0; | |
10144 | } | |
10145 | ||
10146 | return 1; | |
10147 | } | |
10148 | ||
10149 | void | |
10150 | md_show_usage (FILE * fp) | |
10151 | { | |
10152 | struct aarch64_option_table *opt; | |
10153 | struct aarch64_long_option_table *lopt; | |
10154 | ||
10155 | fprintf (fp, _(" AArch64-specific assembler options:\n")); | |
10156 | ||
10157 | for (opt = aarch64_opts; opt->option != NULL; opt++) | |
10158 | if (opt->help != NULL) | |
10159 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
10160 | ||
10161 | for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++) | |
10162 | if (lopt->help != NULL) | |
10163 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
10164 | ||
10165 | #ifdef OPTION_EB | |
10166 | fprintf (fp, _("\ | |
10167 | -EB assemble code for a big-endian cpu\n")); | |
10168 | #endif | |
10169 | ||
10170 | #ifdef OPTION_EL | |
10171 | fprintf (fp, _("\ | |
10172 | -EL assemble code for a little-endian cpu\n")); | |
10173 | #endif | |
10174 | } | |
10175 | ||
10176 | /* Parse a .cpu directive. */ | |
10177 | ||
10178 | static void | |
10179 | s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED) | |
10180 | { | |
10181 | const struct aarch64_cpu_option_table *opt; | |
10182 | char saved_char; | |
10183 | char *name; | |
10184 | char *ext; | |
10185 | size_t optlen; | |
10186 | ||
10187 | name = input_line_pointer; | |
10188 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
10189 | input_line_pointer++; | |
10190 | saved_char = *input_line_pointer; | |
10191 | *input_line_pointer = 0; | |
10192 | ||
10193 | ext = strchr (name, '+'); | |
10194 | ||
10195 | if (ext != NULL) | |
10196 | optlen = ext - name; | |
10197 | else | |
10198 | optlen = strlen (name); | |
10199 | ||
10200 | /* Skip the first "all" entry. */ | |
10201 | for (opt = aarch64_cpus + 1; opt->name != NULL; opt++) | |
10202 | if (strlen (opt->name) == optlen | |
10203 | && strncmp (name, opt->name, optlen) == 0) | |
10204 | { | |
10205 | mcpu_cpu_opt = &opt->value; | |
10206 | if (ext != NULL) | |
ae527cd8 | 10207 | if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE)) |
a06ea964 NC |
10208 | return; |
10209 | ||
10210 | cpu_variant = *mcpu_cpu_opt; | |
10211 | ||
10212 | *input_line_pointer = saved_char; | |
10213 | demand_empty_rest_of_line (); | |
10214 | return; | |
10215 | } | |
10216 | as_bad (_("unknown cpu `%s'"), name); | |
10217 | *input_line_pointer = saved_char; | |
10218 | ignore_rest_of_line (); | |
10219 | } | |
10220 | ||
10221 | ||
10222 | /* Parse a .arch directive. */ | |
10223 | ||
10224 | static void | |
10225 | s_aarch64_arch (int ignored ATTRIBUTE_UNUSED) | |
10226 | { | |
10227 | const struct aarch64_arch_option_table *opt; | |
10228 | char saved_char; | |
10229 | char *name; | |
10230 | char *ext; | |
10231 | size_t optlen; | |
10232 | ||
10233 | name = input_line_pointer; | |
10234 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
10235 | input_line_pointer++; | |
10236 | saved_char = *input_line_pointer; | |
10237 | *input_line_pointer = 0; | |
10238 | ||
10239 | ext = strchr (name, '+'); | |
10240 | ||
10241 | if (ext != NULL) | |
10242 | optlen = ext - name; | |
10243 | else | |
10244 | optlen = strlen (name); | |
10245 | ||
10246 | /* Skip the first "all" entry. */ | |
10247 | for (opt = aarch64_archs + 1; opt->name != NULL; opt++) | |
10248 | if (strlen (opt->name) == optlen | |
10249 | && strncmp (name, opt->name, optlen) == 0) | |
10250 | { | |
10251 | mcpu_cpu_opt = &opt->value; | |
10252 | if (ext != NULL) | |
ae527cd8 | 10253 | if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE)) |
a06ea964 NC |
10254 | return; |
10255 | ||
10256 | cpu_variant = *mcpu_cpu_opt; | |
10257 | ||
10258 | *input_line_pointer = saved_char; | |
10259 | demand_empty_rest_of_line (); | |
10260 | return; | |
10261 | } | |
10262 | ||
10263 | as_bad (_("unknown architecture `%s'\n"), name); | |
10264 | *input_line_pointer = saved_char; | |
10265 | ignore_rest_of_line (); | |
10266 | } | |
10267 | ||
ae527cd8 JB |
10268 | /* Parse a .arch_extension directive. */ |
10269 | ||
10270 | static void | |
10271 | s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
10272 | { | |
10273 | char saved_char; | |
10274 | char *ext = input_line_pointer;; | |
10275 | ||
10276 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
10277 | input_line_pointer++; | |
10278 | saved_char = *input_line_pointer; | |
10279 | *input_line_pointer = 0; | |
10280 | ||
10281 | if (!aarch64_parse_features (ext, &mcpu_cpu_opt, TRUE)) | |
10282 | return; | |
10283 | ||
10284 | cpu_variant = *mcpu_cpu_opt; | |
10285 | ||
10286 | *input_line_pointer = saved_char; | |
10287 | demand_empty_rest_of_line (); | |
10288 | } | |
10289 | ||
a06ea964 NC |
10290 | /* Copy symbol information. */ |
10291 | ||
10292 | void | |
10293 | aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src) | |
10294 | { | |
10295 | AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src); | |
10296 | } | |
0b4eac57 SN |
10297 | |
10298 | #ifdef OBJ_ELF | |
10299 | /* Same as elf_copy_symbol_attributes, but without copying st_other. | |
10300 | This is needed so AArch64 specific st_other values can be independently | |
10301 | specified for an IFUNC resolver (that is called by the dynamic linker) | |
10302 | and the symbol it resolves (aliased to the resolver). In particular, | |
10303 | if a function symbol has special st_other value set via directives, | |
10304 | then attaching an IFUNC resolver to that symbol should not override | |
10305 | the st_other setting. Requiring the directive on the IFUNC resolver | |
10306 | symbol would be unexpected and problematic in C code, where the two | |
10307 | symbols appear as two independent function declarations. */ | |
10308 | ||
10309 | void | |
10310 | aarch64_elf_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
10311 | { | |
10312 | struct elf_obj_sy *srcelf = symbol_get_obj (src); | |
10313 | struct elf_obj_sy *destelf = symbol_get_obj (dest); | |
10314 | if (srcelf->size) | |
10315 | { | |
10316 | if (destelf->size == NULL) | |
10317 | destelf->size = XNEW (expressionS); | |
10318 | *destelf->size = *srcelf->size; | |
10319 | } | |
10320 | else | |
10321 | { | |
9fbb53c7 | 10322 | free (destelf->size); |
0b4eac57 SN |
10323 | destelf->size = NULL; |
10324 | } | |
10325 | S_SET_SIZE (dest, S_GET_SIZE (src)); | |
10326 | } | |
10327 | #endif |