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[thirdparty/binutils-gdb.git] / gas / config / tc-arc.c
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252b5132 1/* tc-arc.c -- Assembler for the ARC
d87bef3a 2 Copyright (C) 1994-2023 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
886a2506 25#include "dwarf2dbg.h"
726c18e1 26#include "dw2gencfi.h"
3882b010 27#include "safe-ctype.h"
886a2506 28
252b5132 29#include "opcode/arc.h"
53a346d8 30#include "opcode/arc-attrs.h"
252b5132 31#include "elf/arc.h"
b99747ae 32#include "../opcodes/arc-ext.h"
252b5132 33
886a2506 34/* Defines section. */
0d2bcfaf 35
886a2506
NC		 36#define MAX_INSN_FIXUPS 2
37#define MAX_CONSTR_STR 20
4670103e 38#define FRAG_MAX_GROWTH 8
0d2bcfaf 39
886a2506
NC		 40#ifdef DEBUG
41# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42#else
43# define pr_debug(fmt, args...)
44#endif
45
46#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 48#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
886a2506 50
9004b6bd 51#ifndef TARGET_WITH_CPU
675b9d61 52#define TARGET_WITH_CPU "arc700"
9004b6bd
AB		 53#endif /* TARGET_WITH_CPU */
54
53a346d8
CZ		 55#define ARC_GET_FLAG(s) (*symbol_get_tc (s))
56#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
57#define streq(a, b) (strcmp (a, b) == 0)
58
4670103e
CZ		 59/* Enum used to enumerate the relaxable ins operands. */
60enum rlx_operand_type
61{
62 EMPTY = 0,
63 REGISTER,
64 REGISTER_S, /* Register for short instruction(s). */
65 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
66 REGISTER_DUP, /* Duplication of previous operand of type register. */
67 IMMEDIATE,
68 BRACKET
69};
70
71enum arc_rlx_types
72{
73 ARC_RLX_NONE = 0,
74 ARC_RLX_BL_S,
75 ARC_RLX_BL,
76 ARC_RLX_B_S,
77 ARC_RLX_B,
78 ARC_RLX_ADD_U3,
79 ARC_RLX_ADD_U6,
80 ARC_RLX_ADD_LIMM,
81 ARC_RLX_LD_U7,
82 ARC_RLX_LD_S9,
83 ARC_RLX_LD_LIMM,
84 ARC_RLX_MOV_U8,
85 ARC_RLX_MOV_S12,
86 ARC_RLX_MOV_LIMM,
87 ARC_RLX_SUB_U3,
88 ARC_RLX_SUB_U6,
89 ARC_RLX_SUB_LIMM,
90 ARC_RLX_MPY_U6,
91 ARC_RLX_MPY_LIMM,
92 ARC_RLX_MOV_RU6,
93 ARC_RLX_MOV_RLIMM,
94 ARC_RLX_ADD_RRU6,
95 ARC_RLX_ADD_RRLIMM,
96};
97
886a2506
NC		 98/* Macros section. */
99
100#define regno(x) ((x) & 0x3F)
101#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 102#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
103#define is_spfp_p(op) (((sc) == SPX))
104#define is_dpfp_p(op) (((sc) == DPX))
105#define is_fpuda_p(op) (((sc) == DPA))
cf9bdae9 106#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
107 || (op)->insn_class == JUMP \
108 || (op)->insn_class == BRCC \
109 || (op)->insn_class == BBIT0 \
110 || (op)->insn_class == BBIT1 \
111 || (op)->insn_class == BI \
112 || (op)->insn_class == EI \
113 || (op)->insn_class == ENTER \
114 || (op)->insn_class == JLI \
115 || (op)->insn_class == LOOP \
116 || (op)->insn_class == LEAVE \
117 ))
c810e0b8 118#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 119#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 120
886a2506
NC		 121/* Generic assembler global variables which must be defined by all
122 targets. */
0d2bcfaf 123
886a2506 124/* Characters which always start a comment. */
252b5132
RH		 125const char comment_chars[] = "#;";
126
886a2506 127/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 128const char line_comment_chars[] = "#";
129
886a2506
NC		 130/* Characters which may be used to separate multiple commands on a
131 single line. */
132const char line_separator_chars[] = "`";
252b5132 133
886a2506
NC		 134/* Characters which are used to indicate an exponent in a floating
135 point number. */
252b5132
RH		 136const char EXP_CHARS[] = "eE";
137
bcee8eb8
AM		 138/* Chars that mean this number is a floating point constant
139 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 140const char FLT_CHARS[] = "rRsSfFdD";
141
142/* Byte order. */
143extern int target_big_endian;
144const char *arc_target_format = DEFAULT_TARGET_FORMAT;
145static int byte_order = DEFAULT_BYTE_ORDER;
146
b99747ae
CZ		 147/* Arc extension section. */
148static segT arcext_section;
149
4670103e
CZ		 150/* By default relaxation is disabled. */
151static int relaxation_state = 0;
152
886a2506 153extern int arc_get_mach (char *);
0d2bcfaf 154
4670103e 155/* Forward declarations. */
886a2506
NC		 156static void arc_lcomm (int);
157static void arc_option (int);
158static void arc_extra_reloc (int);
b99747ae 159static void arc_extinsn (int);
f36e33da 160static void arc_extcorereg (int);
53a346d8 161static void arc_attribute (int);
4670103e 162
886a2506 163const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 164{
165 /* Make sure that .word is 32 bits. */
166 { "word", cons, 4 },
886a2506 167
6f4b1afc
CM		 168 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
169 { "lcomm", arc_lcomm, 0 },
170 { "lcommon", arc_lcomm, 0 },
171 { "cpu", arc_option, 0 },
252b5132 172
53a346d8 173 { "arc_attribute", arc_attribute, 0 },
f36e33da
CZ		 174 { "extinstruction", arc_extinsn, 0 },
175 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
176 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
177 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 178
6f4b1afc
CM		 179 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
180 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 181
6f4b1afc
CM		 182 { NULL, NULL, 0 }
183};
252b5132 184
252b5132 185const char *md_shortopts = "";
ea1562b3
NC		 186
187enum options
6f4b1afc
CM		 188{
189 OPTION_EB = OPTION_MD_BASE,
190 OPTION_EL,
191
192 OPTION_ARC600,
193 OPTION_ARC601,
194 OPTION_ARC700,
195 OPTION_ARCEM,
196 OPTION_ARCHS,
197
198 OPTION_MCPU,
199 OPTION_CD,
4670103e 200 OPTION_RELAX,
bdd582db 201 OPTION_NPS400,
6f4b1afc 202
ce440d63
GM		 203 OPTION_SPFP,
204 OPTION_DPFP,
205 OPTION_FPUDA,
206
6f4b1afc
CM		 207 /* The following options are deprecated and provided here only for
208 compatibility reasons. */
209 OPTION_USER_MODE,
210 OPTION_LD_EXT_MASK,
211 OPTION_SWAP,
212 OPTION_NORM,
213 OPTION_BARREL_SHIFT,
214 OPTION_MIN_MAX,
215 OPTION_NO_MPY,
216 OPTION_EA,
217 OPTION_MUL64,
218 OPTION_SIMD,
6f4b1afc
CM		 219 OPTION_XMAC_D16,
220 OPTION_XMAC_24,
221 OPTION_DSP_PACKA,
222 OPTION_CRC,
223 OPTION_DVBF,
224 OPTION_TELEPHONY,
225 OPTION_XYMEMORY,
226 OPTION_LOCK,
227 OPTION_SWAPE,
ce440d63 228 OPTION_RTSC
6f4b1afc 229};
ea1562b3
NC		 230
231struct option md_longopts[] =
6f4b1afc
CM		 232{
233 { "EB", no_argument, NULL, OPTION_EB },
234 { "EL", no_argument, NULL, OPTION_EL },
235 { "mcpu", required_argument, NULL, OPTION_MCPU },
236 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 237 { "mARC600", no_argument, NULL, OPTION_ARC600 },
238 { "mARC601", no_argument, NULL, OPTION_ARC601 },
239 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 240 { "mA7", no_argument, NULL, OPTION_ARC700 },
241 { "mEM", no_argument, NULL, OPTION_ARCEM },
242 { "mHS", no_argument, NULL, OPTION_ARCHS },
243 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 244 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 245 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 246
ce440d63
GM		 247 /* Floating point options */
248 { "mspfp", no_argument, NULL, OPTION_SPFP},
249 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
250 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
251 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
252 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
253 { "mdpfp", no_argument, NULL, OPTION_DPFP},
254 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
255 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
256 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
257 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
258 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
259
6f4b1afc
CM		 260 /* The following options are deprecated and provided here only for
261 compatibility reasons. */
262 { "mav2em", no_argument, NULL, OPTION_ARCEM },
263 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
264 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
265 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
266 { "mswap", no_argument, NULL, OPTION_SWAP },
267 { "mnorm", no_argument, NULL, OPTION_NORM },
268 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
269 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
270 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
271 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
272 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
273 { "mea", no_argument, NULL, OPTION_EA },
274 { "mEA", no_argument, NULL, OPTION_EA },
275 { "mmul64", no_argument, NULL, OPTION_MUL64 },
276 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 277 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
278 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
279 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
280 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
281 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
282 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
283 { "mcrc", no_argument, NULL, OPTION_CRC},
284 { "mdvbf", no_argument, NULL, OPTION_DVBF},
285 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
286 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
287 { "mlock", no_argument, NULL, OPTION_LOCK},
288 { "mswape", no_argument, NULL, OPTION_SWAPE},
289 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 290
291 { NULL, no_argument, NULL, 0 }
292};
252b5132 293
886a2506 294size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 295
886a2506 296/* Local data and data types. */
252b5132 297
886a2506
NC		 298/* Used since new relocation types are introduced in this
299 file (DUMMY_RELOC_LITUSE_*). */
300typedef int extended_bfd_reloc_code_real_type;
252b5132 301
886a2506 302struct arc_fixup
252b5132 303{
886a2506 304 expressionS exp;
252b5132 305
886a2506 306 extended_bfd_reloc_code_real_type reloc;
252b5132 307
886a2506
NC		 308 /* index into arc_operands. */
309 unsigned int opindex;
252b5132 310
886a2506
NC		 311 /* PC-relative, used by internals fixups. */
312 unsigned char pcrel;
252b5132 313
886a2506 314 /* TRUE if this fixup is for LIMM operand. */
5b7c81bd 315 bool islong;
886a2506 316};
252b5132 317
886a2506
NC		 318struct arc_insn
319{
bdfe53e3 320 unsigned long long int insn;
886a2506
NC		 321 int nfixups;
322 struct arc_fixup fixups[MAX_INSN_FIXUPS];
323 long limm;
5b7c81bd
AM		 324 unsigned int len; /* Length of instruction in bytes. */
325 bool has_limm; /* Boolean value: TRUE if limm field is valid. */
326 bool relax; /* Boolean value: TRUE if needs relaxation. */
886a2506 327};
ea1562b3 328
886a2506
NC		 329/* Structure to hold any last two instructions. */
330static struct arc_last_insn
252b5132 331{
886a2506
NC		 332 /* Saved instruction opcode. */
333 const struct arc_opcode *opcode;
252b5132 334
886a2506 335 /* Boolean value: TRUE if current insn is short. */
5b7c81bd 336 bool has_limm;
252b5132 337
886a2506 338 /* Boolean value: TRUE if current insn has delay slot. */
5b7c81bd 339 bool has_delay_slot;
886a2506 340} arc_last_insns[2];
252b5132 341
b99747ae
CZ		 342/* Extension instruction suffix classes. */
343typedef struct
344{
345 const char *name;
346 int len;
c810e0b8 347 int attr_class;
b99747ae
CZ		 348} attributes_t;
349
350static const attributes_t suffixclass[] =
351{
352 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
353 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
354 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
355};
356
357/* Extension instruction syntax classes. */
358static const attributes_t syntaxclass[] =
359{
360 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 361 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
362 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
363 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 364};
365
366/* Extension instruction syntax classes modifiers. */
367static const attributes_t syntaxclassmod[] =
368{
369 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
370 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
371};
372
f36e33da
CZ		 373/* Extension register type. */
374typedef struct
375{
376 char *name;
377 int number;
378 int imode;
379} extRegister_t;
380
381/* A structure to hold the additional conditional codes. */
382static struct
383{
384 struct arc_flag_operand *arc_ext_condcode;
385 int size;
386} ext_condcode = { NULL, 0 };
387
da5be039
AB		 388/* Structure to hold an entry in ARC_OPCODE_HASH. */
389struct arc_opcode_hash_entry
390{
391 /* The number of pointers in the OPCODE list. */
392 size_t count;
393
394 /* Points to a list of opcode pointers. */
395 const struct arc_opcode **opcode;
396};
397
1328504b
AB		 398/* Structure used for iterating through an arc_opcode_hash_entry. */
399struct arc_opcode_hash_entry_iterator
400{
401 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
402 size_t index;
403
404 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
405 returned by this iterator. */
406 const struct arc_opcode *opcode;
407};
408
4670103e
CZ		 409/* Forward declaration. */
410static void assemble_insn
411 (const struct arc_opcode *, const expressionS *, int,
412 const struct arc_flags *, int, struct arc_insn *);
413
bb65a718
AB		 414/* The selection of the machine type can come from different sources. This
415 enum is used to track how the selection was made in order to perform
416 error checks. */
417enum mach_selection_type
418 {
419 MACH_SELECTION_NONE,
420 MACH_SELECTION_FROM_DEFAULT,
421 MACH_SELECTION_FROM_CPU_DIRECTIVE,
422 MACH_SELECTION_FROM_COMMAND_LINE
423 };
424
425/* How the current machine type was selected. */
426static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 427
886a2506 428/* The hash table of instruction opcodes. */
629310ab 429static htab_t arc_opcode_hash;
0d2bcfaf 430
886a2506 431/* The hash table of register symbols. */
629310ab 432static htab_t arc_reg_hash;
252b5132 433
f36e33da 434/* The hash table of aux register symbols. */
629310ab 435static htab_t arc_aux_hash;
f36e33da 436
db18dbab 437/* The hash table of address types. */
629310ab 438static htab_t arc_addrtype_hash;
db18dbab 439
a9752fdf
CZ		 440#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
441 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
442 E_ARC_MACH_ARC600, EXTRA}
443#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
444 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
445 E_ARC_MACH_ARC700, EXTRA}
446#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
447 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
448 EF_ARC_CPU_ARCV2EM, EXTRA}
449#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
450 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
451 EF_ARC_CPU_ARCV2HS, EXTRA}
940171d0
AK		 452#define ARC_CPU_TYPE_NONE \
453 { 0, 0, 0, 0, 0 }
a9752fdf 454
886a2506
NC		 455/* A table of CPU names and opcode sets. */
456static const struct cpu_type
457{
458 const char *name;
459 unsigned flags;
460 int mach;
461 unsigned eflags;
462 unsigned features;
252b5132 463}
886a2506 464 cpu_types[] =
252b5132 465{
940171d0 466 #include "elf/arc-cpu.def"
886a2506 467};
252b5132 468
bb65a718 469/* Information about the cpu/variant we're assembling for. */
53a346d8 470static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
bb050a69 471
63741043 472/* TRUE if current assembly code uses RF16 only registers. */
5b7c81bd 473static bool rf16_only = true;
63741043 474
53a346d8
CZ		 475/* MPY option. */
476static unsigned mpy_option = 0;
477
478/* Use PIC. */
479static unsigned pic_option = 0;
480
481/* Use small data. */
482static unsigned sda_option = 0;
483
484/* Use TLS. */
485static unsigned tls_option = 0;
bb65a718 486
a9752fdf
CZ		 487/* Command line given features. */
488static unsigned cl_features = 0;
489
886a2506
NC		 490/* Used by the arc_reloc_op table. Order is important. */
491#define O_gotoff O_md1 /* @gotoff relocation. */
492#define O_gotpc O_md2 /* @gotpc relocation. */
493#define O_plt O_md3 /* @plt relocation. */
494#define O_sda O_md4 /* @sda relocation. */
495#define O_pcl O_md5 /* @pcl relocation. */
496#define O_tlsgd O_md6 /* @tlsgd relocation. */
497#define O_tlsie O_md7 /* @tlsie relocation. */
498#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
499#define O_tpoff O_md9 /* @tpoff relocation. */
500#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
501#define O_dtpoff O_md11 /* @dtpoff relocation. */
502#define O_last O_dtpoff
503
504/* Used to define a bracket as operand in tokens. */
505#define O_bracket O_md32
506
db18dbab
GM		 507/* Used to define a colon as an operand in tokens. */
508#define O_colon O_md31
509
510/* Used to define address types in nps400. */
511#define O_addrtype O_md30
512
886a2506
NC		 513/* Dummy relocation, to be sorted out. */
514#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
515
516#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
517
518/* A table to map the spelling of a relocation operand into an appropriate
519 bfd_reloc_code_real_type type. The table is assumed to be ordered such
520 that op-O_literal indexes into it. */
521#define ARC_RELOC_TABLE(op) \
522 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
523 ? (abort (), 0) \
524 : (int) (op) - (int) O_gotoff) ])
525
526#define DEF(NAME, RELOC, REQ) \
527 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
528
529static const struct arc_reloc_op_tag
530{
531 /* String to lookup. */
532 const char *name;
533 /* Size of the string. */
534 size_t length;
535 /* Which operator to use. */
536 operatorT op;
537 extended_bfd_reloc_code_real_type reloc;
538 /* Allows complex relocation expression like identifier@reloc +
539 const. */
540 unsigned int complex_expr : 1;
541}
542 arc_reloc_op[] =
6f4b1afc
CM		 543{
544 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
545 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
546 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
547 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
548 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
549 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
550 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
551 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 552 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 553 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 554 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 555};
252b5132 556
886a2506
NC		 557static const int arc_num_reloc_op
558= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
559
4670103e
CZ		 560/* Structure for relaxable instruction that have to be swapped with a
561 smaller alternative instruction. */
562struct arc_relaxable_ins
563{
564 /* Mnemonic that should be checked. */
565 const char *mnemonic_r;
566
567 /* Operands that should be checked.
568 Indexes of operands from operand array. */
569 enum rlx_operand_type operands[6];
570
571 /* Flags that should be checked. */
572 unsigned flag_classes[5];
573
574 /* Mnemonic (smaller) alternative to be used later for relaxation. */
575 const char *mnemonic_alt;
576
577 /* Index of operand that generic relaxation has to check. */
578 unsigned opcheckidx;
579
580 /* Base subtype index used. */
581 enum arc_rlx_types subtype;
582};
583
584#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
585 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
586 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
587 (SIZE), \
588 (NEXT) } \
589
590#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
591 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
592 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
593 (SIZE), \
594 (NEXT) } \
595
596
597/* ARC relaxation table. */
598const relax_typeS md_relax_table[] =
599{
600 /* Fake entry. */
601 {0, 0, 0, 0},
602
603 /* BL_S s13 ->
604 BL s25. */
db18dbab
GM		 605 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
606 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 607
608 /* B_S s10 ->
609 B s25. */
db18dbab
GM		 610 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
611 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 612
613 /* ADD_S c,b, u3 ->
614 ADD<.f> a,b,u6 ->
615 ADD<.f> a,b,limm. */
db18dbab
GM		 616 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
617 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
618 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 619
620 /* LD_S a, [b, u7] ->
621 LD<zz><.x><.aa><.di> a, [b, s9] ->
622 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 623 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
624 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
625 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 626
627 /* MOV_S b, u8 ->
628 MOV<.f> b, s12 ->
629 MOV<.f> b, limm. */
db18dbab
GM		 630 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
631 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
632 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 633
634 /* SUB_S c, b, u3 ->
635 SUB<.f> a, b, u6 ->
636 SUB<.f> a, b, limm. */
db18dbab
GM		 637 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
638 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
639 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 640
641 /* MPY<.f> a, b, u6 ->
642 MPY<.f> a, b, limm. */
db18dbab
GM		 643 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
644 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 645
646 /* MOV<.f><.cc> b, u6 ->
647 MOV<.f><.cc> b, limm. */
db18dbab
GM		 648 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
649 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 650
651 /* ADD<.f><.cc> b, b, u6 ->
652 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 653 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
654 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 655};
656
657/* Order of this table's entries matters! */
658const struct arc_relaxable_ins arc_relaxable_insns[] =
659{
660 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
661 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
662 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
663 2, ARC_RLX_ADD_RRU6},
664 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
665 ARC_RLX_ADD_U3 },
666 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
667 ARC_RLX_ADD_U6 },
668 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
669 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
670 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
671 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
672 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
673 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
674 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
675 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
676 ARC_RLX_SUB_U3 },
677 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
678 ARC_RLX_SUB_U6 },
679 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
680 ARC_RLX_MPY_U6 },
681};
682
683const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
684
886a2506
NC		 685/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
686symbolS * GOT_symbol = 0;
687
688/* Set to TRUE when we assemble instructions. */
5b7c81bd 689static bool assembling_insn = false;
886a2506 690
53a346d8 691/* List with attributes set explicitly. */
5b7c81bd 692static bool attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
53a346d8 693
886a2506
NC		 694/* Functions implementation. */
695
b9b47ab7
AB		 696/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
697 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
698 are no matching entries in ARC_OPCODE_HASH. */
da5be039 699
b9b47ab7 700static const struct arc_opcode_hash_entry *
da5be039
AB		 701arc_find_opcode (const char *name)
702{
703 const struct arc_opcode_hash_entry *entry;
da5be039 704
629310ab 705 entry = str_hash_find (arc_opcode_hash, name);
b9b47ab7 706 return entry;
da5be039
AB		 707}
708
1328504b
AB		 709/* Initialise the iterator ITER. */
710
711static void
712arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
713{
714 iter->index = 0;
715 iter->opcode = NULL;
716}
717
718/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
719 calls to this function. Return NULL when all ARC_OPCODE entries have
720 been returned. */
721
722static const struct arc_opcode *
723arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
724 struct arc_opcode_hash_entry_iterator *iter)
725{
726 if (iter->opcode == NULL && iter->index == 0)
727 {
728 gas_assert (entry->count > 0);
729 iter->opcode = entry->opcode[iter->index];
730 }
731 else if (iter->opcode != NULL)
732 {
733 const char *old_name = iter->opcode->name;
734
735 iter->opcode++;
fe779266
AB		 736 if (iter->opcode->name == NULL
737 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 738 {
739 iter->index++;
740 if (iter->index == entry->count)
741 iter->opcode = NULL;
742 else
743 iter->opcode = entry->opcode[iter->index];
744 }
745 }
746
747 return iter->opcode;
748}
749
b99747ae
CZ		 750/* Insert an opcode into opcode hash structure. */
751
752static void
753arc_insert_opcode (const struct arc_opcode *opcode)
754{
629310ab 755 const char *name;
b99747ae
CZ		 756 struct arc_opcode_hash_entry *entry;
757 name = opcode->name;
758
629310ab 759 entry = str_hash_find (arc_opcode_hash, name);
b99747ae
CZ		 760 if (entry == NULL)
761 {
add39d23 762 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 763 entry->count = 0;
764 entry->opcode = NULL;
765
fe0e921f
AM		 766 if (str_hash_insert (arc_opcode_hash, name, entry, 0) != NULL)
767 as_fatal (_("duplicate %s"), name);
b99747ae
CZ		 768 }
769
add39d23
TS		 770 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
771 entry->count + 1);
b99747ae 772
b99747ae
CZ		 773 entry->opcode[entry->count] = opcode;
774 entry->count++;
775}
776
a51628a9
AM		 777static void
778arc_opcode_free (void *elt)
779{
780 string_tuple_t *tuple = (string_tuple_t *) elt;
781 struct arc_opcode_hash_entry *entry = (void *) tuple->value;
782 free (entry->opcode);
783 free (entry);
784 free (tuple);
785}
b99747ae 786
bdfe53e3
AB		 787/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
788 value, is encoded as 'middle-endian' for a little-endian target. This
789 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 790
791static void
bdfe53e3 792md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 793{
bdfe53e3 794 switch (n)
886a2506 795 {
bdfe53e3
AB		 796 case 2:
797 md_number_to_chars (buf, val, n);
798 break;
799 case 6:
53b6d6f5 800 md_number_to_chars (buf, (val & 0xffff00000000ull) >> 32, 2);
bdfe53e3
AB		 801 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
802 break;
803 case 4:
886a2506
NC		 804 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
805 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 806 break;
807 case 8:
53b6d6f5 808 md_number_to_chars_midend (buf, (val & 0xffffffff00000000ull) >> 32, 4);
bdfe53e3
AB		 809 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
810 break;
811 default:
812 abort ();
886a2506 813 }
252b5132
RH		 814}
815
bb050a69
CZ		 816/* Check if a feature is allowed for a specific CPU. */
817
818static void
819arc_check_feature (void)
820{
821 unsigned i;
822
823 if (!selected_cpu.features
824 || !selected_cpu.name)
825 return;
53a346d8
CZ		 826
827 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
828 if ((selected_cpu.features & feature_list[i].feature)
829 && !(selected_cpu.flags & feature_list[i].cpus))
830 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
831 selected_cpu.name);
832
833 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
834 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
835 as_bad(_("conflicting ISA extension attributes."));
bb050a69
CZ		 836}
837
24740d83 838/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 839 the relevant static global variables. Parameter SEL describes where
840 this selection originated from. */
24740d83
AB		 841
842static void
bb65a718 843arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 844{
24740d83 845 int i;
5e4f7e05 846 static struct cpu_type old_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
24740d83 847
bb65a718
AB		 848 /* We should only set a default if we've not made a selection from some
849 other source. */
850 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
851 || mach_selection_mode == MACH_SELECTION_NONE);
852
bb050a69
CZ		 853 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
854 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
855 as_bad (_("Multiple .cpu directives found"));
856
bb65a718 857 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 858 for (i = 0; cpu_types[i].name; ++i)
859 {
860 if (!strcasecmp (cpu_types[i].name, arg))
861 {
bb65a718
AB		 862 /* If a previous selection was made on the command line, then we
863 allow later selections on the command line to override earlier
864 ones. However, a selection from a '.cpu NAME' directive must
865 match the command line selection, or we give a warning. */
866 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
867 {
868 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
869 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
870 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
871 && selected_cpu.mach != cpu_types[i].mach)
872 {
873 as_warn (_("Command-line value overrides \".cpu\" directive"));
bb65a718 874 }
bb050a69 875 return;
bb65a718 876 }
bb050a69
CZ		 877 /* Initialise static global data about selected machine type. */
878 selected_cpu.flags = cpu_types[i].flags;
879 selected_cpu.name = cpu_types[i].name;
a9752fdf 880 selected_cpu.features = cpu_types[i].features | cl_features;
bb050a69 881 selected_cpu.mach = cpu_types[i].mach;
53a346d8
CZ		 882 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
883 | cpu_types[i].eflags);
24740d83
AB		 884 break;
885 }
886 }
887
888 if (!cpu_types[i].name)
889 as_fatal (_("unknown architecture: %s\n"), arg);
bb050a69
CZ		 890
891 /* Check if set features are compatible with the chosen CPU. */
892 arc_check_feature ();
53a346d8 893
5e4f7e05
CZ		 894 /* If we change the CPU, we need to re-init the bfd. */
895 if (mach_selection_mode != MACH_SELECTION_NONE
896 && (old_cpu.mach != selected_cpu.mach))
897 {
898 bfd_find_target (arc_target_format, stdoutput);
899 if (! bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
900 as_warn (_("Could not set architecture and machine"));
901 }
902
bb65a718 903 mach_selection_mode = sel;
5e4f7e05 904 old_cpu = selected_cpu;
24740d83
AB		 905}
906
886a2506
NC		 907/* Here ends all the ARCompact extension instruction assembling
908 stuff. */
252b5132 909
886a2506
NC		 910static void
911arc_extra_reloc (int r_type)
ea1562b3 912{
886a2506
NC		 913 char *sym_name, c;
914 symbolS *sym, *lab = NULL;
915
916 if (*input_line_pointer == '@')
917 input_line_pointer++;
918 c = get_symbol_name (&sym_name);
919 sym = symbol_find_or_make (sym_name);
920 restore_line_pointer (c);
921 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
922 {
923 ++input_line_pointer;
924 char *lab_name;
925 c = get_symbol_name (&lab_name);
926 lab = symbol_find_or_make (lab_name);
927 restore_line_pointer (c);
928 }
841fdfcd
CZ		 929
930 /* These relocations exist as a mechanism for the compiler to tell the
931 linker how to patch the code if the tls model is optimised. However,
932 the relocation itself does not require any space within the assembler
933 fragment, and so we pass a size of 0.
934
935 The lines that generate these relocations look like this:
936
937 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
938
939 The '.tls_gd_ld @.tdata' is processed first and generates the
940 additional relocation, while the 'bl __tls_get_addr@plt' is processed
941 second and generates the additional branch.
942
943 It is possible that the additional relocation generated by the
944 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
945 while the 'bl __tls_get_addr@plt' will be generated as the first thing
946 in the next fragment. This will be fine; both relocations will still
947 appear to be at the same address in the generated object file.
948 However, this only works as the additional relocation is generated
949 with size of 0 bytes. */
886a2506
NC		 950 fixS *fixP
951 = fix_new (frag_now, /* Which frag? */
952 frag_now_fix (), /* Where in that frag? */
841fdfcd 953 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 954 sym, /* X_add_symbol. */
955 0, /* X_add_number. */
5b7c81bd 956 false, /* TRUE if PC-relative relocation. */
886a2506
NC		 957 r_type /* Relocation type. */);
958 fixP->fx_subsy = lab;
959}
252b5132 960
886a2506
NC		 961static symbolS *
962arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
963 symbolS *symbolP, addressT size)
964{
965 addressT align = 0;
966 SKIP_WHITESPACE ();
252b5132 967
886a2506
NC		 968 if (*input_line_pointer == ',')
969 {
970 align = parse_align (1);
252b5132 971
886a2506
NC		 972 if (align == (addressT) -1)
973 return NULL;
974 }
975 else
976 {
977 if (size >= 8)
978 align = 3;
979 else if (size >= 4)
980 align = 2;
981 else if (size >= 2)
982 align = 1;
983 else
984 align = 0;
985 }
252b5132 986
886a2506
NC		 987 bss_alloc (symbolP, size, align);
988 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 989
886a2506
NC		 990 return symbolP;
991}
ea1562b3 992
886a2506
NC		 993static void
994arc_lcomm (int ignore)
995{
996 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 997
886a2506
NC		 998 if (symbolP)
999 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
1000}
ea1562b3 1001
886a2506 1002/* Select the cpu we're assembling for. */
ea1562b3 1003
886a2506
NC		 1004static void
1005arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 1006{
886a2506
NC		 1007 char c;
1008 char *cpu;
bb65a718 1009 const char *cpu_name;
252b5132 1010
886a2506 1011 c = get_symbol_name (&cpu);
252b5132 1012
a9752fdf 1013 cpu_name = cpu;
bb65a718
AB		 1014 if ((!strcmp ("ARC600", cpu))
1015 || (!strcmp ("ARC601", cpu))
1016 || (!strcmp ("A6", cpu)))
1017 cpu_name = "arc600";
1018 else if ((!strcmp ("ARC700", cpu))
1019 || (!strcmp ("A7", cpu)))
1020 cpu_name = "arc700";
1021 else if (!strcmp ("EM", cpu))
1022 cpu_name = "arcem";
1023 else if (!strcmp ("HS", cpu))
1024 cpu_name = "archs";
1025 else if (!strcmp ("NPS400", cpu))
1026 cpu_name = "nps400";
886a2506 1027
a9752fdf 1028 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
24b368f8 1029
24b368f8 1030 restore_line_pointer (c);
886a2506 1031 demand_empty_rest_of_line ();
ea1562b3 1032}
252b5132 1033
886a2506
NC		 1034/* Smartly print an expression. */
1035
ea1562b3 1036static void
886a2506 1037debug_exp (expressionS *t)
ea1562b3 1038{
886a2506
NC		 1039 const char *name ATTRIBUTE_UNUSED;
1040 const char *namemd ATTRIBUTE_UNUSED;
252b5132 1041
886a2506 1042 pr_debug ("debug_exp: ");
252b5132 1043
886a2506 1044 switch (t->X_op)
252b5132 1045 {
886a2506
NC		 1046 default: name = "unknown"; break;
1047 case O_illegal: name = "O_illegal"; break;
1048 case O_absent: name = "O_absent"; break;
1049 case O_constant: name = "O_constant"; break;
1050 case O_symbol: name = "O_symbol"; break;
1051 case O_symbol_rva: name = "O_symbol_rva"; break;
1052 case O_register: name = "O_register"; break;
1053 case O_big: name = "O_big"; break;
1054 case O_uminus: name = "O_uminus"; break;
1055 case O_bit_not: name = "O_bit_not"; break;
1056 case O_logical_not: name = "O_logical_not"; break;
1057 case O_multiply: name = "O_multiply"; break;
1058 case O_divide: name = "O_divide"; break;
1059 case O_modulus: name = "O_modulus"; break;
1060 case O_left_shift: name = "O_left_shift"; break;
1061 case O_right_shift: name = "O_right_shift"; break;
1062 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1063 case O_bit_or_not: name = "O_bit_or_not"; break;
1064 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1065 case O_bit_and: name = "O_bit_and"; break;
1066 case O_add: name = "O_add"; break;
1067 case O_subtract: name = "O_subtract"; break;
1068 case O_eq: name = "O_eq"; break;
1069 case O_ne: name = "O_ne"; break;
1070 case O_lt: name = "O_lt"; break;
1071 case O_le: name = "O_le"; break;
1072 case O_ge: name = "O_ge"; break;
1073 case O_gt: name = "O_gt"; break;
1074 case O_logical_and: name = "O_logical_and"; break;
1075 case O_logical_or: name = "O_logical_or"; break;
1076 case O_index: name = "O_index"; break;
1077 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1078 case O_colon: name = "O_colon"; break;
1079 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1080 }
252b5132 1081
886a2506 1082 switch (t->X_md)
ea1562b3 1083 {
886a2506
NC		 1084 default: namemd = "unknown"; break;
1085 case O_gotoff: namemd = "O_gotoff"; break;
1086 case O_gotpc: namemd = "O_gotpc"; break;
1087 case O_plt: namemd = "O_plt"; break;
1088 case O_sda: namemd = "O_sda"; break;
1089 case O_pcl: namemd = "O_pcl"; break;
1090 case O_tlsgd: namemd = "O_tlsgd"; break;
1091 case O_tlsie: namemd = "O_tlsie"; break;
1092 case O_tpoff9: namemd = "O_tpoff9"; break;
1093 case O_tpoff: namemd = "O_tpoff"; break;
1094 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1095 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1096 }
252b5132 1097
886a2506
NC		 1098 pr_debug ("%s (%s, %s, %d, %s)", name,
1099 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1100 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1101 (int) t->X_add_number,
1102 (t->X_md) ? namemd : "--");
1103 pr_debug ("\n");
1104 fflush (stderr);
1105}
252b5132 1106
2a1ebfb2
CZ		 1107/* Helper for parsing an argument, used for sorting out the relocation
1108 type. */
1109
1110static void
1111parse_reloc_symbol (expressionS *resultP)
1112{
1113 char *reloc_name, c, *sym_name;
1114 size_t len;
1115 int i;
1116 const struct arc_reloc_op_tag *r;
1117 expressionS right;
1118 symbolS *base;
1119
1120 /* A relocation operand has the following form
1121 @identifier@relocation_type. The identifier is already in
1122 tok! */
1123 if (resultP->X_op != O_symbol)
1124 {
1125 as_bad (_("No valid label relocation operand"));
1126 resultP->X_op = O_illegal;
1127 return;
1128 }
1129
1130 /* Parse @relocation_type. */
1131 input_line_pointer++;
1132 c = get_symbol_name (&reloc_name);
1133 len = input_line_pointer - reloc_name;
1134 if (len == 0)
1135 {
1136 as_bad (_("No relocation operand"));
1137 resultP->X_op = O_illegal;
1138 return;
1139 }
1140
1141 /* Go through known relocation and try to find a match. */
1142 r = &arc_reloc_op[0];
1143 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
1144 if (len == r->length
1145 && memcmp (reloc_name, r->name, len) == 0)
1146 break;
1147 if (i < 0)
1148 {
1149 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
1150 resultP->X_op = O_illegal;
1151 return;
1152 }
1153
1154 *input_line_pointer = c;
1155 SKIP_WHITESPACE_AFTER_NAME ();
1156 /* Extra check for TLS: base. */
1157 if (*input_line_pointer == '@')
1158 {
1159 if (resultP->X_op_symbol != NULL
1160 || resultP->X_op != O_symbol)
1161 {
1162 as_bad (_("Unable to parse TLS base: %s"),
1163 input_line_pointer);
1164 resultP->X_op = O_illegal;
1165 return;
1166 }
1167 input_line_pointer++;
1168 c = get_symbol_name (&sym_name);
1169 base = symbol_find_or_make (sym_name);
1170 resultP->X_op = O_subtract;
1171 resultP->X_op_symbol = base;
1172 restore_line_pointer (c);
1173 right.X_add_number = 0;
1174 }
1175
1176 if ((*input_line_pointer != '+')
1177 && (*input_line_pointer != '-'))
1178 right.X_add_number = 0;
1179 else
1180 {
1181 /* Parse the constant of a complex relocation expression
1182 like @identifier@reloc +/- const. */
1183 if (! r->complex_expr)
1184 {
1185 as_bad (_("@%s is not a complex relocation."), r->name);
1186 resultP->X_op = O_illegal;
1187 return;
1188 }
1189 expression (&right);
1190 if (right.X_op != O_constant)
1191 {
1192 as_bad (_("Bad expression: @%s + %s."),
1193 r->name, input_line_pointer);
1194 resultP->X_op = O_illegal;
1195 return;
1196 }
1197 }
1198
1199 resultP->X_md = r->op;
1200 resultP->X_add_number = right.X_add_number;
1201}
1202
886a2506
NC		 1203/* Parse the arguments to an opcode. */
1204
1205static int
1206tokenize_arguments (char *str,
1207 expressionS *tok,
1208 int ntok)
1209{
1210 char *old_input_line_pointer;
5b7c81bd
AM		 1211 bool saw_comma = false;
1212 bool saw_arg = false;
886a2506
NC		 1213 int brk_lvl = 0;
1214 int num_args = 0;
886a2506
NC		 1215
1216 memset (tok, 0, sizeof (*tok) * ntok);
1217
1218 /* Save and restore input_line_pointer around this function. */
1219 old_input_line_pointer = input_line_pointer;
1220 input_line_pointer = str;
ea1562b3 1221
886a2506 1222 while (*input_line_pointer)
ea1562b3
NC		 1223 {
1224 SKIP_WHITESPACE ();
886a2506 1225 switch (*input_line_pointer)
252b5132 1226 {
886a2506
NC		 1227 case '\0':
1228 goto fini;
1229
1230 case ',':
1231 input_line_pointer++;
1232 if (saw_comma || !saw_arg)
1233 goto err;
5b7c81bd 1234 saw_comma = true;
886a2506 1235 break;
252b5132 1236
886a2506
NC		 1237 case '}':
1238 case ']':
1239 ++input_line_pointer;
1240 --brk_lvl;
3b889a78 1241 if (!saw_arg || num_args == ntok)
886a2506
NC		 1242 goto err;
1243 tok->X_op = O_bracket;
1244 ++tok;
1245 ++num_args;
1246 break;
ea1562b3 1247
886a2506
NC		 1248 case '{':
1249 case '[':
1250 input_line_pointer++;
3b889a78 1251 if (brk_lvl || num_args == ntok)
886a2506
NC		 1252 goto err;
1253 ++brk_lvl;
1254 tok->X_op = O_bracket;
1255 ++tok;
1256 ++num_args;
1257 break;
1258
db18dbab
GM		 1259 case ':':
1260 input_line_pointer++;
1261 if (!saw_arg || num_args == ntok)
1262 goto err;
1263 tok->X_op = O_colon;
5b7c81bd 1264 saw_arg = false;
db18dbab
GM		 1265 ++tok;
1266 ++num_args;
1267 break;
1268
886a2506
NC		 1269 case '@':
1270 /* We have labels, function names and relocations, all
1271 starting with @ symbol. Sort them out. */
3b889a78 1272 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1273 goto err;
1274
1275 /* Parse @label. */
2a1ebfb2 1276 input_line_pointer++;
886a2506
NC		 1277 tok->X_op = O_symbol;
1278 tok->X_md = O_absent;
1279 expression (tok);
886a2506 1280
886a2506 1281 if (*input_line_pointer == '@')
2a1ebfb2 1282 parse_reloc_symbol (tok);
1e07b820 1283
886a2506 1284 debug_exp (tok);
ea1562b3 1285
2a1ebfb2
CZ		 1286 if (tok->X_op == O_illegal
1287 || tok->X_op == O_absent
1288 || num_args == ntok)
1289 goto err;
1290
5b7c81bd
AM		 1291 saw_comma = false;
1292 saw_arg = true;
886a2506
NC		 1293 tok++;
1294 num_args++;
1295 break;
252b5132 1296
886a2506
NC		 1297 case '%':
1298 /* Can be a register. */
1299 ++input_line_pointer;
1300 /* Fall through. */
1301 default:
252b5132 1302
3b889a78 1303 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1304 goto err;
252b5132 1305
886a2506 1306 tok->X_op = O_absent;
6f4b1afc 1307 tok->X_md = O_absent;
886a2506 1308 expression (tok);
252b5132 1309
6f4b1afc
CM		 1310 /* Legacy: There are cases when we have
1311 identifier@relocation_type, if it is the case parse the
1312 relocation type as well. */
1313 if (*input_line_pointer == '@')
2a1ebfb2 1314 parse_reloc_symbol (tok);
d50c498a
JB		 1315 else
1316 resolve_register (tok);
6f4b1afc 1317
886a2506 1318 debug_exp (tok);
252b5132 1319
3b889a78
AB		 1320 if (tok->X_op == O_illegal
1321 || tok->X_op == O_absent
1322 || num_args == ntok)
886a2506 1323 goto err;
252b5132 1324
5b7c81bd
AM		 1325 saw_comma = false;
1326 saw_arg = true;
886a2506
NC		 1327 tok++;
1328 num_args++;
1329 break;
1330 }
ea1562b3 1331 }
252b5132 1332
886a2506
NC		 1333 fini:
1334 if (saw_comma || brk_lvl)
1335 goto err;
1336 input_line_pointer = old_input_line_pointer;
252b5132 1337
886a2506 1338 return num_args;
252b5132 1339
886a2506
NC		 1340 err:
1341 if (brk_lvl)
1342 as_bad (_("Brackets in operand field incorrect"));
1343 else if (saw_comma)
1344 as_bad (_("extra comma"));
1345 else if (!saw_arg)
1346 as_bad (_("missing argument"));
1347 else
1348 as_bad (_("missing comma or colon"));
1349 input_line_pointer = old_input_line_pointer;
1350 return -1;
252b5132 1351}
ea1562b3 1352
886a2506
NC		 1353/* Parse the flags to a structure. */
1354
1355static int
1356tokenize_flags (const char *str,
1357 struct arc_flags flags[],
1358 int nflg)
252b5132 1359{
886a2506 1360 char *old_input_line_pointer;
5b7c81bd
AM		 1361 bool saw_flg = false;
1362 bool saw_dot = false;
886a2506
NC		 1363 int num_flags = 0;
1364 size_t flgnamelen;
252b5132 1365
886a2506 1366 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1367
886a2506
NC		 1368 /* Save and restore input_line_pointer around this function. */
1369 old_input_line_pointer = input_line_pointer;
1370 input_line_pointer = (char *) str;
0d2bcfaf 1371
886a2506
NC		 1372 while (*input_line_pointer)
1373 {
1374 switch (*input_line_pointer)
1375 {
1376 case ' ':
1377 case '\0':
1378 goto fini;
1379
1380 case '.':
1381 input_line_pointer++;
1382 if (saw_dot)
1383 goto err;
5b7c81bd
AM		 1384 saw_dot = true;
1385 saw_flg = false;
886a2506 1386 break;
ea1562b3 1387
886a2506
NC		 1388 default:
1389 if (saw_flg && !saw_dot)
1390 goto err;
0d2bcfaf 1391
886a2506
NC		 1392 if (num_flags >= nflg)
1393 goto err;
0d2bcfaf 1394
692166c2
AB		 1395 flgnamelen = strspn (input_line_pointer,
1396 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1397 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1398 goto err;
0d2bcfaf 1399
886a2506 1400 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1401
886a2506
NC		 1402 input_line_pointer += flgnamelen;
1403 flags++;
5b7c81bd
AM		 1404 saw_dot = false;
1405 saw_flg = true;
886a2506
NC		 1406 num_flags++;
1407 break;
1e07b820 1408 }
0d2bcfaf
NC		 1409 }
1410
886a2506
NC		 1411 fini:
1412 input_line_pointer = old_input_line_pointer;
1413 return num_flags;
0d2bcfaf 1414
886a2506
NC		 1415 err:
1416 if (saw_dot)
1417 as_bad (_("extra dot"));
1418 else if (!saw_flg)
1419 as_bad (_("unrecognized flag"));
1420 else
1421 as_bad (_("failed to parse flags"));
1422 input_line_pointer = old_input_line_pointer;
1423 return -1;
1424}
0d2bcfaf 1425
4670103e 1426/* Apply the fixups in order. */
0d2bcfaf 1427
4670103e
CZ		 1428static void
1429apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1430{
4670103e 1431 int i;
0d2bcfaf 1432
4670103e 1433 for (i = 0; i < insn->nfixups; i++)
252b5132 1434 {
4670103e
CZ		 1435 struct arc_fixup *fixup = &insn->fixups[i];
1436 int size, pcrel, offset = 0;
0d2bcfaf 1437
4670103e
CZ		 1438 /* FIXME! the reloc size is wrong in the BFD file.
1439 When it is fixed please delete me. */
91fdca6f 1440 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1441
4670103e 1442 if (fixup->islong)
91fdca6f 1443 offset = insn->len;
252b5132 1444
4670103e
CZ		 1445 /* Some fixups are only used internally, thus no howto. */
1446 if ((int) fixup->reloc == 0)
1447 as_fatal (_("Unhandled reloc type"));
886a2506 1448
4670103e
CZ		 1449 if ((int) fixup->reloc < 0)
1450 {
1451 /* FIXME! the reloc size is wrong in the BFD file.
1452 When it is fixed please enable me.
91fdca6f 1453 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1454 pcrel = fixup->pcrel;
1455 }
1456 else
1457 {
1458 reloc_howto_type *reloc_howto =
1459 bfd_reloc_type_lookup (stdoutput,
1460 (bfd_reloc_code_real_type) fixup->reloc);
1461 gas_assert (reloc_howto);
0d2bcfaf 1462
4670103e
CZ		 1463 /* FIXME! the reloc size is wrong in the BFD file.
1464 When it is fixed please enable me.
1465 size = bfd_get_reloc_size (reloc_howto); */
1466 pcrel = reloc_howto->pc_relative;
1467 }
0d2bcfaf 1468
4670103e
CZ		 1469 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1470offset %d + %d\n",
1471 fragP->fr_file, fragP->fr_line,
1472 (fixup->reloc < 0) ? "Internal" :
1473 bfd_get_reloc_code_name (fixup->reloc),
1474 pcrel ? "Y" : "N",
1475 size, fix, offset);
1476 fix_new_exp (fragP, fix + offset,
1477 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1478
4670103e
CZ		 1479 /* Check for ZOLs, and update symbol info if any. */
1480 if (LP_INSN (insn->insn))
886a2506 1481 {
4670103e
CZ		 1482 gas_assert (fixup->exp.X_add_symbol);
1483 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1484 }
1485 }
252b5132
RH		 1486}
1487
4670103e 1488/* Actually output an instruction with its fixup. */
886a2506 1489
4670103e 1490static void
5b7c81bd 1491emit_insn0 (struct arc_insn *insn, char *where, bool relax)
252b5132 1492{
4670103e 1493 char *f = where;
91fdca6f 1494 size_t total_len;
252b5132 1495
bdfe53e3 1496 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
777cd7ab 1497 pr_debug ("\tLength : %d\n", insn->len);
4670103e 1498 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1499
4670103e 1500 /* Write out the instruction. */
91fdca6f
GM		 1501 total_len = insn->len + (insn->has_limm ? 4 : 0);
1502 if (!relax)
1503 f = frag_more (total_len);
1504
1505 md_number_to_chars_midend(f, insn->insn, insn->len);
1506
1507 if (insn->has_limm)
1508 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1509 dwarf2_emit_insn (total_len);
252b5132 1510
4670103e
CZ		 1511 if (!relax)
1512 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1513}
252b5132 1514
4670103e
CZ		 1515static void
1516emit_insn1 (struct arc_insn *insn)
1517{
1518 /* How frag_var's args are currently configured:
1519 - rs_machine_dependent, to dictate it's a relaxation frag.
1520 - FRAG_MAX_GROWTH, maximum size of instruction
1521 - 0, variable size that might grow...unused by generic relaxation.
1522 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1523 - s, opand expression.
1524 - 0, offset but it's unused.
1525 - 0, opcode but it's unused. */
1526 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1527 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1528
1529 if (frag_room () < FRAG_MAX_GROWTH)
1530 {
1531 /* Handle differently when frag literal memory is exhausted.
1532 This is used because when there's not enough memory left in
1533 the current frag, a new frag is created and the information
1534 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1535
4670103e
CZ		 1536 struct arc_relax_type relax_info_copy;
1537 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1538
4670103e
CZ		 1539 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1540 sizeof (struct arc_relax_type));
0d2bcfaf 1541
4670103e
CZ		 1542 frag_wane (frag_now);
1543 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1544
4670103e
CZ		 1545 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1546 sizeof (struct arc_relax_type));
252b5132 1547
4670103e
CZ		 1548 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1549 subtype, s, 0, 0);
1550 }
1551 else
1552 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1553 frag_now->fr_subtype, s, 0, 0);
1554}
252b5132 1555
4670103e
CZ		 1556static void
1557emit_insn (struct arc_insn *insn)
252b5132 1558{
4670103e
CZ		 1559 if (insn->relax)
1560 emit_insn1 (insn);
252b5132 1561 else
5b7c81bd 1562 emit_insn0 (insn, NULL, false);
252b5132
RH		 1563}
1564
4670103e 1565/* Check whether a symbol involves a register. */
252b5132 1566
5b7c81bd 1567static bool
4670103e 1568contains_register (symbolS *sym)
252b5132 1569{
4670103e
CZ		 1570 if (sym)
1571 {
1572 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1573
4670103e
CZ		 1574 return ((O_register == ex->X_op)
1575 && !contains_register (ex->X_add_symbol)
1576 && !contains_register (ex->X_op_symbol));
1577 }
1578
5b7c81bd 1579 return false;
252b5132
RH		 1580}
1581
4670103e 1582/* Returns the register number within a symbol. */
252b5132 1583
4670103e
CZ		 1584static int
1585get_register (symbolS *sym)
252b5132 1586{
4670103e
CZ		 1587 if (!contains_register (sym))
1588 return -1;
0d2bcfaf 1589
4670103e
CZ		 1590 expressionS *ex = symbol_get_value_expression (sym);
1591 return regno (ex->X_add_number);
1592}
252b5132 1593
4670103e
CZ		 1594/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1595 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1596
5b7c81bd 1597static bool
4670103e
CZ		 1598generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1599{
1600 if (!reloc)
5b7c81bd 1601 return false;
886a2506 1602
4670103e
CZ		 1603 switch (reloc)
1604 {
1605 case BFD_RELOC_ARC_SDA_LDST:
1606 case BFD_RELOC_ARC_SDA_LDST1:
1607 case BFD_RELOC_ARC_SDA_LDST2:
1608 case BFD_RELOC_ARC_SDA16_LD:
1609 case BFD_RELOC_ARC_SDA16_LD1:
1610 case BFD_RELOC_ARC_SDA16_LD2:
1611 case BFD_RELOC_ARC_SDA16_ST2:
1612 case BFD_RELOC_ARC_SDA32_ME:
5b7c81bd 1613 return false;
4670103e 1614 default:
5b7c81bd 1615 return true;
f17c130b 1616 }
252b5132
RH		 1617}
1618
4670103e 1619/* Allocates a tok entry. */
252b5132 1620
4670103e
CZ		 1621static int
1622allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1623{
4670103e
CZ		 1624 if (ntok > MAX_INSN_ARGS - 2)
1625 return 0; /* No space left. */
252b5132 1626
4670103e 1627 if (cidx > ntok)
33eaf5de 1628 return 0; /* Incorrect args. */
252b5132 1629
4670103e 1630 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1631
4670103e
CZ		 1632 if (cidx == ntok)
1633 return 1; /* Success. */
1634 return allocate_tok (tok, ntok - 1, cidx);
1635}
886a2506 1636
8ddf6b2a
CZ		 1637/* Check if an particular ARC feature is enabled. */
1638
5b7c81bd 1639static bool
8ddf6b2a
CZ		 1640check_cpu_feature (insn_subclass_t sc)
1641{
53a346d8 1642 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
5b7c81bd 1643 return false;
8ddf6b2a 1644
53a346d8 1645 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
5b7c81bd 1646 return false;
8ddf6b2a 1647
53a346d8 1648 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
5b7c81bd 1649 return false;
8ddf6b2a 1650
53a346d8 1651 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
5b7c81bd 1652 return false;
bdd582db 1653
53a346d8 1654 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
5b7c81bd 1655 return false;
8ddf6b2a 1656
5b7c81bd 1657 return true;
8ddf6b2a
CZ		 1658}
1659
4eb6f892
AB		 1660/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1661 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1662 array and returns TRUE if the flag operands all match, otherwise,
1663 returns FALSE, in which case the FIRST_PFLAG array may have been
1664 modified. */
1665
5b7c81bd 1666static bool
4eb6f892
AB		 1667parse_opcode_flags (const struct arc_opcode *opcode,
1668 int nflgs,
1669 struct arc_flags *first_pflag)
1670{
1671 int lnflg, i;
1672 const unsigned char *flgidx;
1673
1674 lnflg = nflgs;
1675 for (i = 0; i < nflgs; i++)
1676 first_pflag[i].flgp = NULL;
1677
1678 /* Check the flags. Iterate over the valid flag classes. */
1679 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1680 {
1681 /* Get a valid flag class. */
1682 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1683 const unsigned *flgopridx;
1684 int cl_matches = 0;
1685 struct arc_flags *pflag = NULL;
1686
6ec7c1ae
CZ		 1687 /* Check if opcode has implicit flag classes. */
1688 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1689 continue;
1690
4eb6f892
AB		 1691 /* Check for extension conditional codes. */
1692 if (ext_condcode.arc_ext_condcode
1693 && cl_flags->flag_class & F_CLASS_EXTEND)
1694 {
1695 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1696 while (pf->name)
1697 {
1698 pflag = first_pflag;
1699 for (i = 0; i < nflgs; i++, pflag++)
1700 {
1701 if (!strcmp (pf->name, pflag->name))
1702 {
1703 if (pflag->flgp != NULL)
5b7c81bd 1704 return false;
4eb6f892
AB		 1705 /* Found it. */
1706 cl_matches++;
1707 pflag->flgp = pf;
1708 lnflg--;
1709 break;
1710 }
1711 }
1712 pf++;
1713 }
1714 }
1715
1716 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1717 {
1718 const struct arc_flag_operand *flg_operand;
1719
1720 pflag = first_pflag;
1721 flg_operand = &arc_flag_operands[*flgopridx];
1722 for (i = 0; i < nflgs; i++, pflag++)
1723 {
1724 /* Match against the parsed flags. */
1725 if (!strcmp (flg_operand->name, pflag->name))
1726 {
1727 if (pflag->flgp != NULL)
5b7c81bd 1728 return false;
4eb6f892
AB		 1729 cl_matches++;
1730 pflag->flgp = flg_operand;
1731 lnflg--;
1732 break; /* goto next flag class and parsed flag. */
1733 }
1734 }
1735 }
1736
1737 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
5b7c81bd 1738 return false;
4eb6f892 1739 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
5b7c81bd 1740 return false;
4eb6f892
AB		 1741 }
1742
1743 /* Did I check all the parsed flags? */
63b4cc53 1744 return lnflg == 0;
4eb6f892
AB		 1745}
1746
1747
4670103e
CZ		 1748/* Search forward through all variants of an opcode looking for a
1749 syntax match. */
886a2506 1750
4670103e 1751static const struct arc_opcode *
b9b47ab7 1752find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1753 expressionS *tok,
1754 int *pntok,
1755 struct arc_flags *first_pflag,
1756 int nflgs,
abe7c33b
CZ		 1757 int *pcpumatch,
1758 const char **errmsg)
4670103e 1759{
1328504b
AB		 1760 const struct arc_opcode *opcode;
1761 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1762 int ntok = *pntok;
1763 int got_cpu_match = 0;
1764 expressionS bktok[MAX_INSN_ARGS];
3128916d 1765 int bkntok, maxerridx = 0;
4670103e 1766 expressionS emptyE;
3128916d 1767 const char *tmpmsg = NULL;
886a2506 1768
1328504b 1769 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1770 memset (&emptyE, 0, sizeof (emptyE));
1771 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1772 bkntok = ntok;
a161fe53 1773
1328504b
AB		 1774 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1775 opcode != NULL;
1776 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1777 {
4670103e 1778 const unsigned char *opidx;
4eb6f892 1779 int tokidx = 0;
4670103e 1780 const expressionS *t = &emptyE;
252b5132 1781
bdfe53e3 1782 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1783 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1784
4670103e
CZ		 1785 /* Don't match opcodes that don't exist on this
1786 architecture. */
bb65a718 1787 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1788 goto match_failed;
886a2506 1789
8ddf6b2a 1790 if (!check_cpu_feature (opcode->subclass))
4670103e 1791 goto match_failed;
886a2506 1792
4670103e
CZ		 1793 got_cpu_match = 1;
1794 pr_debug ("cpu ");
886a2506 1795
4670103e
CZ		 1796 /* Check the operands. */
1797 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1798 {
4670103e 1799 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1800
4670103e 1801 /* Only take input from real operands. */
db18dbab 1802 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1803 continue;
252b5132 1804
4670103e
CZ		 1805 /* When we expect input, make sure we have it. */
1806 if (tokidx >= ntok)
1807 goto match_failed;
6f4b1afc 1808
4670103e
CZ		 1809 /* Match operand type with expression type. */
1810 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1811 {
db18dbab 1812 case ARC_OPERAND_ADDRTYPE:
b437d035 1813 {
3128916d 1814 tmpmsg = NULL;
b437d035
AB		 1815
1816 /* Check to be an address type. */
1817 if (tok[tokidx].X_op != O_addrtype)
1818 goto match_failed;
1819
1820 /* All address type operands need to have an insert
1821 method in order to check that we have the correct
1822 address type. */
1823 gas_assert (operand->insert != NULL);
1824 (*operand->insert) (0, tok[tokidx].X_add_number,
3128916d
CZ		 1825 &tmpmsg);
1826 if (tmpmsg != NULL)
b437d035
AB		 1827 goto match_failed;
1828 }
db18dbab
GM		 1829 break;
1830
4670103e
CZ		 1831 case ARC_OPERAND_IR:
1832 /* Check to be a register. */
1833 if ((tok[tokidx].X_op != O_register
1834 || !is_ir_num (tok[tokidx].X_add_number))
1835 && !(operand->flags & ARC_OPERAND_IGNORE))
1836 goto match_failed;
1837
1838 /* If expect duplicate, make sure it is duplicate. */
1839 if (operand->flags & ARC_OPERAND_DUPLICATE)
1840 {
1841 /* Check for duplicate. */
1842 if (t->X_op != O_register
1843 || !is_ir_num (t->X_add_number)
1844 || (regno (t->X_add_number) !=
1845 regno (tok[tokidx].X_add_number)))
1846 goto match_failed;
1847 }
1848
1849 /* Special handling? */
1850 if (operand->insert)
1851 {
3128916d 1852 tmpmsg = NULL;
4670103e
CZ		 1853 (*operand->insert)(0,
1854 regno (tok[tokidx].X_add_number),
3128916d
CZ		 1855 &tmpmsg);
1856 if (tmpmsg)
4670103e
CZ		 1857 {
1858 if (operand->flags & ARC_OPERAND_IGNORE)
1859 {
1860 /* Missing argument, create one. */
1861 if (!allocate_tok (tok, ntok - 1, tokidx))
1862 goto match_failed;
1863
1864 tok[tokidx].X_op = O_absent;
1865 ++ntok;
1866 }
1867 else
1868 goto match_failed;
1869 }
1870 }
1871
1872 t = &tok[tokidx];
1873 break;
1874
1875 case ARC_OPERAND_BRAKET:
1876 /* Check if bracket is also in opcode table as
1877 operand. */
1878 if (tok[tokidx].X_op != O_bracket)
1879 goto match_failed;
1880 break;
1881
db18dbab
GM		 1882 case ARC_OPERAND_COLON:
1883 /* Check if colon is also in opcode table as operand. */
1884 if (tok[tokidx].X_op != O_colon)
1885 goto match_failed;
1886 break;
1887
4670103e
CZ		 1888 case ARC_OPERAND_LIMM:
1889 case ARC_OPERAND_SIGNED:
1890 case ARC_OPERAND_UNSIGNED:
1891 switch (tok[tokidx].X_op)
1892 {
1893 case O_illegal:
1894 case O_absent:
1895 case O_register:
1896 goto match_failed;
1897
1898 case O_bracket:
1899 /* Got an (too) early bracket, check if it is an
1900 ignored operand. N.B. This procedure works only
1901 when bracket is the last operand! */
1902 if (!(operand->flags & ARC_OPERAND_IGNORE))
1903 goto match_failed;
1904 /* Insert the missing operand. */
1905 if (!allocate_tok (tok, ntok - 1, tokidx))
1906 goto match_failed;
1907
1908 tok[tokidx].X_op = O_absent;
1909 ++ntok;
1910 break;
1911
22b92fc4
AB		 1912 case O_symbol:
1913 {
1914 const char *p;
b6523c37 1915 char *tmpp, *pp;
22b92fc4 1916 const struct arc_aux_reg *auxr;
22b92fc4 1917
c810e0b8 1918 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1919 goto de_fault;
1920 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da 1921
b6523c37 1922 /* For compatibility reasons, an aux register can
1923 be spelled with upper or lower case
1924 letters. */
1925 tmpp = strdup (p);
1926 for (pp = tmpp; *pp; ++pp) *pp = TOLOWER (*pp);
1927
629310ab 1928 auxr = str_hash_find (arc_aux_hash, tmpp);
f36e33da
CZ		 1929 if (auxr)
1930 {
1931 /* We modify the token array here, safe in the
1932 knowledge, that if this was the wrong
1933 choice then the original contents will be
1934 restored from BKTOK. */
1935 tok[tokidx].X_op = O_constant;
1936 tok[tokidx].X_add_number = auxr->address;
1937 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1938 }
b6523c37 1939 free (tmpp);
22b92fc4
AB		 1940
1941 if (tok[tokidx].X_op != O_constant)
1942 goto de_fault;
1943 }
1a0670f3 1944 /* Fall through. */
4670103e
CZ		 1945 case O_constant:
1946 /* Check the range. */
1947 if (operand->bits != 32
1948 && !(operand->flags & ARC_OPERAND_NCHK))
1949 {
1950 offsetT min, max, val;
1951 val = tok[tokidx].X_add_number;
1952
1953 if (operand->flags & ARC_OPERAND_SIGNED)
1954 {
1955 max = (1 << (operand->bits - 1)) - 1;
1956 min = -(1 << (operand->bits - 1));
1957 }
1958 else
1959 {
1960 max = (1 << operand->bits) - 1;
1961 min = 0;
1962 }
1963
1964 if (val < min || val > max)
3128916d
CZ		 1965 {
1966 tmpmsg = _("immediate is out of bounds");
1967 goto match_failed;
1968 }
4670103e 1969
33eaf5de 1970 /* Check alignments. */
4670103e
CZ		 1971 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1972 && (val & 0x03))
3128916d
CZ		 1973 {
1974 tmpmsg = _("immediate is not 32bit aligned");
1975 goto match_failed;
1976 }
4670103e
CZ		 1977
1978 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1979 && (val & 0x01))
3128916d
CZ		 1980 {
1981 tmpmsg = _("immediate is not 16bit aligned");
1982 goto match_failed;
1983 }
4670103e
CZ		 1984 }
1985 else if (operand->flags & ARC_OPERAND_NCHK)
1986 {
1987 if (operand->insert)
1988 {
3128916d 1989 tmpmsg = NULL;
4670103e
CZ		 1990 (*operand->insert)(0,
1991 tok[tokidx].X_add_number,
3128916d
CZ		 1992 &tmpmsg);
1993 if (tmpmsg)
4670103e
CZ		 1994 goto match_failed;
1995 }
4eb6f892 1996 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1997 goto match_failed;
1998 }
1999 break;
2000
2001 case O_subtract:
2002 /* Check if it is register range. */
2003 if ((tok[tokidx].X_add_number == 0)
2004 && contains_register (tok[tokidx].X_add_symbol)
2005 && contains_register (tok[tokidx].X_op_symbol))
2006 {
2007 int regs;
2008
2009 regs = get_register (tok[tokidx].X_add_symbol);
2010 regs <<= 16;
2011 regs |= get_register (tok[tokidx].X_op_symbol);
2012 if (operand->insert)
2013 {
3128916d 2014 tmpmsg = NULL;
4670103e
CZ		 2015 (*operand->insert)(0,
2016 regs,
3128916d
CZ		 2017 &tmpmsg);
2018 if (tmpmsg)
4670103e
CZ		 2019 goto match_failed;
2020 }
2021 else
2022 goto match_failed;
2023 break;
2024 }
1a0670f3 2025 /* Fall through. */
4670103e 2026 default:
22b92fc4 2027 de_fault:
4670103e
CZ		 2028 if (operand->default_reloc == 0)
2029 goto match_failed; /* The operand needs relocation. */
2030
2031 /* Relocs requiring long immediate. FIXME! make it
2032 generic and move it to a function. */
2033 switch (tok[tokidx].X_md)
2034 {
2035 case O_gotoff:
2036 case O_gotpc:
2037 case O_pcl:
2038 case O_tpoff:
2039 case O_dtpoff:
2040 case O_tlsgd:
2041 case O_tlsie:
2042 if (!(operand->flags & ARC_OPERAND_LIMM))
2043 goto match_failed;
1a0670f3 2044 /* Fall through. */
4670103e
CZ		 2045 case O_absent:
2046 if (!generic_reloc_p (operand->default_reloc))
2047 goto match_failed;
2b804145 2048 break;
4670103e
CZ		 2049 default:
2050 break;
2051 }
2052 break;
2053 }
2054 /* If expect duplicate, make sure it is duplicate. */
2055 if (operand->flags & ARC_OPERAND_DUPLICATE)
2056 {
2057 if (t->X_op == O_illegal
2058 || t->X_op == O_absent
2059 || t->X_op == O_register
2060 || (t->X_add_number != tok[tokidx].X_add_number))
3128916d
CZ		 2061 {
2062 tmpmsg = _("operand is not duplicate of the "
2063 "previous one");
2064 goto match_failed;
2065 }
4670103e
CZ		 2066 }
2067 t = &tok[tokidx];
2068 break;
2069
2070 default:
2071 /* Everything else should have been fake. */
2072 abort ();
2073 }
2074
2075 ++tokidx;
2076 }
2077 pr_debug ("opr ");
2078
1ae8ab47 2079 /* Setup ready for flag parsing. */
4eb6f892 2080 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
3128916d
CZ		 2081 {
2082 tmpmsg = _("flag mismatch");
2083 goto match_failed;
2084 }
4670103e
CZ		 2085
2086 pr_debug ("flg");
2087 /* Possible match -- did we use all of our input? */
2088 if (tokidx == ntok)
2089 {
2090 *pntok = ntok;
2091 pr_debug ("\n");
2092 return opcode;
2093 }
3128916d 2094 tmpmsg = _("too many arguments");
4670103e
CZ		 2095
2096 match_failed:;
2097 pr_debug ("\n");
2098 /* Restore the original parameters. */
2099 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2100 ntok = bkntok;
3128916d
CZ		 2101 if (tokidx >= maxerridx
2102 && tmpmsg)
2103 {
2104 maxerridx = tokidx;
2105 *errmsg = tmpmsg;
2106 }
4670103e 2107 }
4670103e
CZ		 2108
2109 if (*pcpumatch)
2110 *pcpumatch = got_cpu_match;
2111
2112 return NULL;
2113}
2114
2115/* Swap operand tokens. */
2116
2117static void
2118swap_operand (expressionS *operand_array,
2119 unsigned source,
2120 unsigned destination)
2121{
2122 expressionS cpy_operand;
2123 expressionS *src_operand;
2124 expressionS *dst_operand;
2125 size_t size;
2126
2127 if (source == destination)
2128 return;
2129
2130 src_operand = &operand_array[source];
2131 dst_operand = &operand_array[destination];
2132 size = sizeof (expressionS);
2133
2134 /* Make copy of operand to swap with and swap. */
2135 memcpy (&cpy_operand, dst_operand, size);
2136 memcpy (dst_operand, src_operand, size);
2137 memcpy (src_operand, &cpy_operand, size);
2138}
2139
2140/* Check if *op matches *tok type.
2141 Returns FALSE if they don't match, TRUE if they match. */
2142
5b7c81bd 2143static bool
4670103e
CZ		 2144pseudo_operand_match (const expressionS *tok,
2145 const struct arc_operand_operation *op)
2146{
2147 offsetT min, max, val;
5b7c81bd 2148 bool ret;
4670103e
CZ		 2149 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2150
5b7c81bd 2151 ret = false;
4670103e
CZ		 2152 switch (tok->X_op)
2153 {
2154 case O_constant:
2155 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2156 ret = 1;
2157 else if (!(operand_real->flags & ARC_OPERAND_IR))
2158 {
2159 val = tok->X_add_number + op->count;
2160 if (operand_real->flags & ARC_OPERAND_SIGNED)
2161 {
2162 max = (1 << (operand_real->bits - 1)) - 1;
2163 min = -(1 << (operand_real->bits - 1));
2164 }
2165 else
2166 {
2167 max = (1 << operand_real->bits) - 1;
2168 min = 0;
2169 }
2170 if (min <= val && val <= max)
5b7c81bd 2171 ret = true;
4670103e 2172 }
6f4b1afc
CM		 2173 break;
2174
4670103e
CZ		 2175 case O_symbol:
2176 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2177 if (operand_real->flags & ARC_OPERAND_LIMM
2178 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2179 && operand_real->bits == 9))
5b7c81bd 2180 ret = true;
6f4b1afc
CM		 2181 break;
2182
4670103e
CZ		 2183 case O_register:
2184 if (operand_real->flags & ARC_OPERAND_IR)
5b7c81bd 2185 ret = true;
4670103e
CZ		 2186 break;
2187
2188 case O_bracket:
2189 if (operand_real->flags & ARC_OPERAND_BRAKET)
5b7c81bd 2190 ret = true;
6f4b1afc
CM		 2191 break;
2192
2193 default:
4670103e 2194 /* Unknown. */
6f4b1afc
CM		 2195 break;
2196 }
4670103e
CZ		 2197 return ret;
2198}
6f4b1afc 2199
4670103e
CZ		 2200/* Find pseudo instruction in array. */
2201
2202static const struct arc_pseudo_insn *
2203find_pseudo_insn (const char *opname,
2204 int ntok,
2205 const expressionS *tok)
2206{
2207 const struct arc_pseudo_insn *pseudo_insn = NULL;
2208 const struct arc_operand_operation *op;
2209 unsigned int i;
2210 int j;
2211
2212 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2213 {
4670103e
CZ		 2214 pseudo_insn = &arc_pseudo_insns[i];
2215 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2216 {
2217 op = pseudo_insn->operand;
2218 for (j = 0; j < ntok; ++j)
2219 if (!pseudo_operand_match (&tok[j], &op[j]))
2220 break;
2221
2222 /* Found the right instruction. */
2223 if (j == ntok)
2224 return pseudo_insn;
2225 }
6f4b1afc 2226 }
4670103e
CZ		 2227 return NULL;
2228}
252b5132 2229
4670103e 2230/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2231
b9b47ab7 2232static const struct arc_opcode_hash_entry *
4670103e
CZ		 2233find_special_case_pseudo (const char *opname,
2234 int *ntok,
2235 expressionS *tok,
2236 int *nflgs,
2237 struct arc_flags *pflags)
2238{
2239 const struct arc_pseudo_insn *pseudo_insn = NULL;
2240 const struct arc_operand_operation *operand_pseudo;
2241 const struct arc_operand *operand_real;
2242 unsigned i;
2243 char construct_operand[MAX_CONSTR_STR];
886a2506 2244
4670103e
CZ		 2245 /* Find whether opname is in pseudo instruction array. */
2246 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2247
2248 if (pseudo_insn == NULL)
2249 return NULL;
2250
2251 /* Handle flag, Limited to one flag at the moment. */
2252 if (pseudo_insn->flag_r != NULL)
2253 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2254 MAX_INSN_FLGS - *nflgs);
2255
2256 /* Handle operand operations. */
2257 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2258 {
4670103e
CZ		 2259 operand_pseudo = &pseudo_insn->operand[i];
2260 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2261
db18dbab
GM		 2262 if (operand_real->flags & ARC_OPERAND_BRAKET
2263 && !operand_pseudo->needs_insert)
4670103e 2264 continue;
b125bd17 2265
4670103e
CZ		 2266 /* Has to be inserted (i.e. this token does not exist yet). */
2267 if (operand_pseudo->needs_insert)
2268 {
2269 if (operand_real->flags & ARC_OPERAND_BRAKET)
2270 {
2271 tok[i].X_op = O_bracket;
2272 ++(*ntok);
2273 continue;
2274 }
b125bd17 2275
4670103e
CZ		 2276 /* Check if operand is a register or constant and handle it
2277 by type. */
2278 if (operand_real->flags & ARC_OPERAND_IR)
2279 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2280 operand_pseudo->count);
2281 else
2282 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2283 operand_pseudo->count);
886a2506 2284
4670103e
CZ		 2285 tokenize_arguments (construct_operand, &tok[i], 1);
2286 ++(*ntok);
2287 }
2288
2289 else if (operand_pseudo->count)
2290 {
2291 /* Operand number has to be adjusted accordingly (by operand
2292 type). */
2293 switch (tok[i].X_op)
2294 {
2295 case O_constant:
2296 tok[i].X_add_number += operand_pseudo->count;
2297 break;
2298
2299 case O_symbol:
2300 break;
2301
2302 default:
2303 /* Ignored. */
2304 break;
2305 }
2306 }
2307 }
2308
2309 /* Swap operands if necessary. Only supports one swap at the
2310 moment. */
2311 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2312 {
2313 operand_pseudo = &pseudo_insn->operand[i];
2314
2315 if (operand_pseudo->swap_operand_idx == i)
2316 continue;
2317
2318 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2319
2320 /* Prevent a swap back later by breaking out. */
2321 break;
2322 }
2323
da5be039 2324 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2325}
2326
b9b47ab7 2327static const struct arc_opcode_hash_entry *
4670103e
CZ		 2328find_special_case_flag (const char *opname,
2329 int *nflgs,
2330 struct arc_flags *pflags)
2331{
2332 unsigned int i;
2333 const char *flagnm;
2334 unsigned flag_idx, flag_arr_idx;
2335 size_t flaglen, oplen;
2336 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2337 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2338
2339 /* Search for special case instruction. */
2340 for (i = 0; i < arc_num_flag_special; i++)
2341 {
2342 arc_flag_special_opcode = &arc_flag_special_cases[i];
2343 oplen = strlen (arc_flag_special_opcode->name);
2344
2345 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2346 continue;
2347
2348 /* Found a potential special case instruction, now test for
2349 flags. */
2350 for (flag_arr_idx = 0;; ++flag_arr_idx)
2351 {
2352 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2353 if (flag_idx == 0)
2354 break; /* End of array, nothing found. */
886a2506 2355
4670103e
CZ		 2356 flagnm = arc_flag_operands[flag_idx].name;
2357 flaglen = strlen (flagnm);
2358 if (strcmp (opname + oplen, flagnm) == 0)
2359 {
b9b47ab7 2360 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2361
4670103e
CZ		 2362 if (*nflgs + 1 > MAX_INSN_FLGS)
2363 break;
2364 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2365 pflags[*nflgs].name[flaglen] = '\0';
2366 (*nflgs)++;
b9b47ab7 2367 return entry;
4670103e
CZ		 2368 }
2369 }
2370 }
2371 return NULL;
2372}
886a2506 2373
4670103e 2374/* Used to find special case opcode. */
886a2506 2375
b9b47ab7 2376static const struct arc_opcode_hash_entry *
4670103e
CZ		 2377find_special_case (const char *opname,
2378 int *nflgs,
2379 struct arc_flags *pflags,
2380 expressionS *tok,
2381 int *ntok)
2382{
b9b47ab7 2383 const struct arc_opcode_hash_entry *entry;
886a2506 2384
b9b47ab7 2385 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2386
b9b47ab7
AB		 2387 if (entry == NULL)
2388 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2389
b9b47ab7 2390 return entry;
4670103e 2391}
886a2506 2392
53a346d8
CZ		 2393/* Autodetect cpu attribute list. */
2394
2395static void
2396autodetect_attributes (const struct arc_opcode *opcode,
2397 const expressionS *tok,
2398 int ntok)
2399{
2400 unsigned i;
2401 struct mpy_type
2402 {
2403 unsigned feature;
2404 unsigned encoding;
2405 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2406 { MPY9E, 9 }};
2407
2408 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2409 if (opcode->subclass == feature_list[i].feature)
2410 selected_cpu.features |= feature_list[i].feature;
2411
2412 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2413 if (opcode->subclass == mpy_list[i].feature)
2414 mpy_option = mpy_list[i].encoding;
2415
2416 for (i = 0; i < (unsigned) ntok; i++)
2417 {
2418 switch (tok[i].X_md)
2419 {
2420 case O_gotoff:
2421 case O_gotpc:
2422 case O_plt:
2423 pic_option = 2;
2424 break;
2425 case O_sda:
2426 sda_option = 2;
2427 break;
2428 case O_tlsgd:
2429 case O_tlsie:
2430 case O_tpoff9:
2431 case O_tpoff:
2432 case O_dtpoff9:
2433 case O_dtpoff:
2434 tls_option = 1;
2435 break;
2436 default:
2437 break;
2438 }
63741043 2439
2440 switch (tok[i].X_op)
2441 {
2442 case O_register:
2443 if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
2444 || (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
5b7c81bd 2445 rf16_only = false;
63741043 2446 break;
2447 default:
2448 break;
2449 }
53a346d8
CZ		 2450 }
2451}
2452
2453/* Given an opcode name, pre-tockenized set of argumenst and the
4670103e 2454 opcode flags, take it all the way through emission. */
886a2506 2455
4670103e
CZ		 2456static void
2457assemble_tokens (const char *opname,
2458 expressionS *tok,
2459 int ntok,
2460 struct arc_flags *pflags,
2461 int nflgs)
2462{
5b7c81bd 2463 bool found_something = false;
b9b47ab7 2464 const struct arc_opcode_hash_entry *entry;
4670103e 2465 int cpumatch = 1;
abe7c33b 2466 const char *errmsg = NULL;
886a2506 2467
4670103e 2468 /* Search opcodes. */
b9b47ab7 2469 entry = arc_find_opcode (opname);
886a2506 2470
4670103e 2471 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2472 if (entry == NULL)
2473 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2474
b9b47ab7 2475 if (entry != NULL)
4670103e 2476 {
b9b47ab7
AB		 2477 const struct arc_opcode *opcode;
2478
1328504b
AB		 2479 pr_debug ("%s:%d: assemble_tokens: %s\n",
2480 frag_now->fr_file, frag_now->fr_line, opname);
5b7c81bd 2481 found_something = true;
b9b47ab7 2482 opcode = find_opcode_match (entry, tok, &ntok, pflags,
abe7c33b 2483 nflgs, &cpumatch, &errmsg);
b9b47ab7 2484 if (opcode != NULL)
4670103e
CZ		 2485 {
2486 struct arc_insn insn;
b9b47ab7 2487
53a346d8 2488 autodetect_attributes (opcode, tok, ntok);
4670103e
CZ		 2489 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2490 emit_insn (&insn);
2491 return;
2492 }
2493 }
886a2506 2494
4670103e
CZ		 2495 if (found_something)
2496 {
2497 if (cpumatch)
abe7c33b
CZ		 2498 if (errmsg)
2499 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2500 else
2501 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
4670103e
CZ		 2502 else
2503 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2504 selected_cpu.name);
4670103e
CZ		 2505 }
2506 else
2507 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2508}
2509
4670103e 2510/* The public interface to the instruction assembler. */
886a2506 2511
4670103e
CZ		 2512void
2513md_assemble (char *str)
886a2506 2514{
4670103e
CZ		 2515 char *opname;
2516 expressionS tok[MAX_INSN_ARGS];
2517 int ntok, nflg;
2518 size_t opnamelen;
2519 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2520
4670103e 2521 /* Split off the opcode. */
51542162 2522 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123456789");
29a2809e 2523 opname = xmemdup0 (str, opnamelen);
886a2506 2524
33eaf5de 2525 /* Signalize we are assembling the instructions. */
5b7c81bd 2526 assembling_insn = true;
886a2506 2527
4670103e
CZ		 2528 /* Tokenize the flags. */
2529 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2530 {
2531 as_bad (_("syntax error"));
2532 return;
2533 }
886a2506 2534
4670103e
CZ		 2535 /* Scan up to the end of the mnemonic which must end in space or end
2536 of string. */
2537 str += opnamelen;
2538 for (; *str != '\0'; str++)
2539 if (*str == ' ')
2540 break;
886a2506 2541
4670103e
CZ		 2542 /* Tokenize the rest of the line. */
2543 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2544 {
4670103e
CZ		 2545 as_bad (_("syntax error"));
2546 return;
252b5132
RH		 2547 }
2548
4670103e
CZ		 2549 /* Finish it off. */
2550 assemble_tokens (opname, tok, ntok, flags, nflg);
5b7c81bd 2551 assembling_insn = false;
4670103e
CZ		 2552}
2553
2554/* Callback to insert a register into the hash table. */
2555
2556static void
f86f5863 2557declare_register (const char *name, int number)
4670103e 2558{
4670103e 2559 symbolS *regS = symbol_create (name, reg_section,
e01e1cee 2560 &zero_address_frag, number);
4670103e 2561
fe0e921f
AM		 2562 if (str_hash_insert (arc_reg_hash, S_GET_NAME (regS), regS, 0) != NULL)
2563 as_fatal (_("duplicate %s"), name);
4670103e 2564}
252b5132 2565
4670103e 2566/* Construct symbols for each of the general registers. */
252b5132 2567
4670103e
CZ		 2568static void
2569declare_register_set (void)
2570{
2571 int i;
2572 for (i = 0; i < 64; ++i)
886a2506 2573 {
ca159256 2574 char name[32];
4670103e
CZ		 2575
2576 sprintf (name, "r%d", i);
2577 declare_register (name, i);
2578 if ((i & 0x01) == 0)
886a2506 2579 {
4670103e
CZ		 2580 sprintf (name, "r%dr%d", i, i+1);
2581 declare_register (name, i);
886a2506
NC		 2582 }
2583 }
252b5132 2584}
ea1562b3 2585
db18dbab
GM		 2586/* Construct a symbol for an address type. */
2587
2588static void
2589declare_addrtype (const char *name, int number)
2590{
db18dbab 2591 symbolS *addrtypeS = symbol_create (name, undefined_section,
e01e1cee 2592 &zero_address_frag, number);
db18dbab 2593
fe0e921f
AM		 2594 if (str_hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS), addrtypeS, 0))
2595 as_fatal (_("duplicate %s"), name);
db18dbab
GM		 2596}
2597
4670103e
CZ		 2598/* Port-specific assembler initialization. This function is called
2599 once, at assembler startup time. */
ea1562b3
NC		 2600
2601void
4670103e 2602md_begin (void)
ea1562b3 2603{
b99747ae 2604 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2605
bb65a718
AB		 2606 if (mach_selection_mode == MACH_SELECTION_NONE)
2607 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2608
4670103e
CZ		 2609 /* The endianness can be chosen "at the factory". */
2610 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2611
bb65a718 2612 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2613 as_warn (_("could not set architecture and machine"));
2614
2615 /* Set elf header flags. */
bb65a718 2616 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2617
2618 /* Set up a hash table for the instructions. */
a51628a9
AM		 2619 arc_opcode_hash = htab_create_alloc (16, hash_string_tuple, eq_string_tuple,
2620 arc_opcode_free, xcalloc, free);
4670103e
CZ		 2621
2622 /* Initialize the hash table with the insns. */
b99747ae 2623 do
ea1562b3 2624 {
b99747ae 2625 const char *name = opcode->name;
da5be039 2626
b99747ae 2627 arc_insert_opcode (opcode);
4670103e 2628
b99747ae
CZ		 2629 while (++opcode && opcode->name
2630 && (opcode->name == name
2631 || !strcmp (opcode->name, name)))
4670103e 2632 continue;
b99747ae 2633 }while (opcode->name);
4670103e
CZ		 2634
2635 /* Register declaration. */
629310ab 2636 arc_reg_hash = str_htab_create ();
4670103e
CZ		 2637
2638 declare_register_set ();
2639 declare_register ("gp", 26);
2640 declare_register ("fp", 27);
2641 declare_register ("sp", 28);
2642 declare_register ("ilink", 29);
2643 declare_register ("ilink1", 29);
2644 declare_register ("ilink2", 30);
2645 declare_register ("blink", 31);
2646
87789e08
CZ		 2647 /* XY memory registers. */
2648 declare_register ("x0_u0", 32);
2649 declare_register ("x0_u1", 33);
2650 declare_register ("x1_u0", 34);
2651 declare_register ("x1_u1", 35);
2652 declare_register ("x2_u0", 36);
2653 declare_register ("x2_u1", 37);
2654 declare_register ("x3_u0", 38);
2655 declare_register ("x3_u1", 39);
2656 declare_register ("y0_u0", 40);
2657 declare_register ("y0_u1", 41);
2658 declare_register ("y1_u0", 42);
2659 declare_register ("y1_u1", 43);
2660 declare_register ("y2_u0", 44);
2661 declare_register ("y2_u1", 45);
2662 declare_register ("y3_u0", 46);
2663 declare_register ("y3_u1", 47);
2664 declare_register ("x0_nu", 48);
2665 declare_register ("x1_nu", 49);
2666 declare_register ("x2_nu", 50);
2667 declare_register ("x3_nu", 51);
2668 declare_register ("y0_nu", 52);
2669 declare_register ("y1_nu", 53);
2670 declare_register ("y2_nu", 54);
2671 declare_register ("y3_nu", 55);
2672
4670103e
CZ		 2673 declare_register ("mlo", 57);
2674 declare_register ("mmid", 58);
2675 declare_register ("mhi", 59);
2676
2677 declare_register ("acc1", 56);
2678 declare_register ("acc2", 57);
2679
2680 declare_register ("lp_count", 60);
2681 declare_register ("pcl", 63);
2682
2683 /* Initialize the last instructions. */
2684 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2685
2686 /* Aux register declaration. */
629310ab 2687 arc_aux_hash = str_htab_create ();
f36e33da
CZ		 2688
2689 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2690 unsigned int i;
2691 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2692 {
bb65a718 2693 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2694 continue;
2695
2696 if ((auxr->subclass != NONE)
2697 && !check_cpu_feature (auxr->subclass))
2698 continue;
2699
fe0e921f
AM		 2700 if (str_hash_insert (arc_aux_hash, auxr->name, auxr, 0) != 0)
2701 as_fatal (_("duplicate %s"), auxr->name);
f36e33da 2702 }
db18dbab
GM		 2703
2704 /* Address type declaration. */
629310ab 2705 arc_addrtype_hash = str_htab_create ();
db18dbab
GM		 2706
2707 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2708 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2709 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2710 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2711 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2712 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2713 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2714 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2715 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2716 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2717 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2718 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2719 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2720 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2721 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2722 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2723}
ea1562b3 2724
a51628a9
AM		 2725void
2726arc_md_end (void)
2727{
2728 htab_delete (arc_opcode_hash);
2729 htab_delete (arc_reg_hash);
2730 htab_delete (arc_aux_hash);
2731 htab_delete (arc_addrtype_hash);
2732}
2733
4670103e
CZ		 2734/* Write a value out to the object file, using the appropriate
2735 endianness. */
ea1562b3 2736
4670103e
CZ		 2737void
2738md_number_to_chars (char *buf,
2739 valueT val,
2740 int n)
886a2506 2741{
4670103e
CZ		 2742 if (target_big_endian)
2743 number_to_chars_bigendian (buf, val, n);
2744 else
2745 number_to_chars_littleendian (buf, val, n);
886a2506 2746}
ea1562b3 2747
4670103e 2748/* Round up a section size to the appropriate boundary. */
ea1562b3 2749
4670103e
CZ		 2750valueT
2751md_section_align (segT segment,
2752 valueT size)
886a2506 2753{
fd361982 2754 int align = bfd_section_alignment (segment);
4670103e
CZ		 2755
2756 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2757}
ea1562b3 2758
4670103e
CZ		 2759/* The location from which a PC relative jump should be calculated,
2760 given a PC relative reloc. */
ea1562b3 2761
4670103e
CZ		 2762long
2763md_pcrel_from_section (fixS *fixP,
2764 segT sec)
886a2506 2765{
4670103e 2766 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2767
4670103e 2768 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2769
4670103e
CZ		 2770 if (fixP->fx_addsy != (symbolS *) NULL
2771 && (!S_IS_DEFINED (fixP->fx_addsy)
2772 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2773 {
2774 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2775
4670103e
CZ		 2776 /* The symbol is undefined (or is defined but not in this section).
2777 Let the linker figure it out. */
2778 return 0;
2779 }
2780
2781 if ((int) fixP->fx_r_type < 0)
886a2506 2782 {
4670103e
CZ		 2783 /* These are the "internal" relocations. Align them to
2784 32 bit boundary (PCL), for the moment. */
2785 base &= ~3;
886a2506 2786 }
4670103e
CZ		 2787 else
2788 {
2789 switch (fixP->fx_r_type)
2790 {
2791 case BFD_RELOC_ARC_PC32:
2792 /* The hardware calculates relative to the start of the
2793 insn, but this relocation is relative to location of the
2794 LIMM, compensate. The base always needs to be
2b0f3761 2795 subtracted by 4 as we do not support this type of PCrel
4670103e
CZ		 2796 relocation for short instructions. */
2797 base -= 4;
2798 /* Fall through. */
2799 case BFD_RELOC_ARC_PLT32:
2800 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2801 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2802 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2803 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2804
2805 case BFD_RELOC_ARC_S21H_PCREL:
2806 case BFD_RELOC_ARC_S25H_PCREL:
2807 case BFD_RELOC_ARC_S13_PCREL:
2808 case BFD_RELOC_ARC_S21W_PCREL:
2809 case BFD_RELOC_ARC_S25W_PCREL:
2810 base &= ~3;
2811 break;
2812 default:
2813 as_bad_where (fixP->fx_file, fixP->fx_line,
2814 _("unhandled reloc %s in md_pcrel_from_section"),
2815 bfd_get_reloc_code_name (fixP->fx_r_type));
2816 break;
2817 }
2818 }
2819
b8281767
AM		 2820 pr_debug ("pcrel from %" PRIx64 " + %lx = %" PRIx64 ", "
2821 "symbol: %s (%" PRIx64 ")\n",
2822 (uint64_t) fixP->fx_frag->fr_address, fixP->fx_where, (uint64_t) base,
4670103e 2823 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
b8281767 2824 fixP->fx_addsy ? (uint64_t) S_GET_VALUE (fixP->fx_addsy) : (uint64_t) 0);
4670103e
CZ		 2825
2826 return base;
886a2506 2827}
ea1562b3 2828
33eaf5de 2829/* Given a BFD relocation find the corresponding operand. */
ea1562b3 2830
4670103e
CZ		 2831static const struct arc_operand *
2832find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2833{
2834 unsigned i;
ea1562b3 2835
4670103e
CZ		 2836 for (i = 0; i < arc_num_operands; i++)
2837 if (arc_operands[i].default_reloc == reloc)
2838 return &arc_operands[i];
2839 return NULL;
2840}
ea1562b3 2841
4670103e 2842/* Insert an operand value into an instruction. */
ea1562b3 2843
bdfe53e3
AB		 2844static unsigned long long
2845insert_operand (unsigned long long insn,
4670103e 2846 const struct arc_operand *operand,
bdfe53e3 2847 long long val,
3b4dbbbf 2848 const char *file,
4670103e 2849 unsigned line)
886a2506 2850{
4670103e 2851 offsetT min = 0, max = 0;
ea1562b3 2852
4670103e
CZ		 2853 if (operand->bits != 32
2854 && !(operand->flags & ARC_OPERAND_NCHK)
2855 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2856 {
4670103e
CZ		 2857 if (operand->flags & ARC_OPERAND_SIGNED)
2858 {
2859 max = (1 << (operand->bits - 1)) - 1;
2860 min = -(1 << (operand->bits - 1));
2861 }
2862 else
2863 {
2864 max = (1 << operand->bits) - 1;
2865 min = 0;
2866 }
886a2506 2867
4670103e
CZ		 2868 if (val < min || val > max)
2869 as_bad_value_out_of_range (_("operand"),
2870 val, min, max, file, line);
2871 }
ea1562b3 2872
cc07cda6 2873 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
4670103e 2874 min, val, max, insn);
ea1562b3 2875
4670103e
CZ		 2876 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2877 && (val & 0x03))
2878 as_bad_where (file, line,
2879 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2880
4670103e
CZ		 2881 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2882 && (val & 0x01))
2883 as_bad_where (file, line,
2884 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2885
4670103e
CZ		 2886 if (operand->insert)
2887 {
2888 const char *errmsg = NULL;
ea1562b3 2889
4670103e
CZ		 2890 insn = (*operand->insert) (insn, val, &errmsg);
2891 if (errmsg)
2892 as_warn_where (file, line, "%s", errmsg);
2893 }
2894 else
2895 {
2896 if (operand->flags & ARC_OPERAND_TRUNCATE)
2897 {
2898 if (operand->flags & ARC_OPERAND_ALIGNED32)
2899 val >>= 2;
2900 if (operand->flags & ARC_OPERAND_ALIGNED16)
2901 val >>= 1;
886a2506 2902 }
4670103e
CZ		 2903 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2904 }
2905 return insn;
2906}
ea1562b3 2907
4670103e
CZ		 2908/* Apply a fixup to the object code. At this point all symbol values
2909 should be fully resolved, and we attempt to completely resolve the
2910 reloc. If we can not do that, we determine the correct reloc code
2911 and put it back in the fixup. To indicate that a fixup has been
2912 eliminated, set fixP->fx_done. */
ea1562b3 2913
4670103e
CZ		 2914void
2915md_apply_fix (fixS *fixP,
2916 valueT *valP,
2917 segT seg)
2918{
2919 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2920 valueT value = *valP;
2921 unsigned insn = 0;
2922 symbolS *fx_addsy, *fx_subsy;
2923 offsetT fx_offset;
2924 segT add_symbol_segment = absolute_section;
2925 segT sub_symbol_segment = absolute_section;
2926 const struct arc_operand *operand = NULL;
2927 extended_bfd_reloc_code_real_type reloc;
886a2506 2928
4670103e
CZ		 2929 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2930 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2931 ((int) fixP->fx_r_type < 0) ? "Internal":
2932 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2933 fixP->fx_offset);
886a2506 2934
4670103e
CZ		 2935 fx_addsy = fixP->fx_addsy;
2936 fx_subsy = fixP->fx_subsy;
2937 fx_offset = 0;
886a2506 2938
4670103e
CZ		 2939 if (fx_addsy)
2940 {
2941 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2942 }
2943
4670103e
CZ		 2944 if (fx_subsy
2945 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2946 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2947 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2948 {
2949 resolve_symbol_value (fx_subsy);
2950 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2951
4670103e
CZ		 2952 if (sub_symbol_segment == absolute_section)
2953 {
2954 /* The symbol is really a constant. */
2955 fx_offset -= S_GET_VALUE (fx_subsy);
2956 fx_subsy = NULL;
2957 }
2958 else
2959 {
4bf09429 2960 as_bad_subtract (fixP);
4670103e
CZ		 2961 return;
2962 }
2963 }
886a2506 2964
4670103e
CZ		 2965 if (fx_addsy
2966 && !S_IS_WEAK (fx_addsy))
2967 {
2968 if (add_symbol_segment == seg
2969 && fixP->fx_pcrel)
2970 {
2971 value += S_GET_VALUE (fx_addsy);
2972 value -= md_pcrel_from_section (fixP, seg);
2973 fx_addsy = NULL;
5b7c81bd 2974 fixP->fx_pcrel = false;
4670103e
CZ		 2975 }
2976 else if (add_symbol_segment == absolute_section)
2977 {
2978 value = fixP->fx_offset;
2979 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2980 fx_addsy = NULL;
5b7c81bd 2981 fixP->fx_pcrel = false;
4670103e
CZ		 2982 }
2983 }
886a2506 2984
4670103e 2985 if (!fx_addsy)
5b7c81bd 2986 fixP->fx_done = true;
886a2506 2987
4670103e 2988 if (fixP->fx_pcrel)
886a2506 2989 {
4670103e
CZ		 2990 if (fx_addsy
2991 && ((S_IS_DEFINED (fx_addsy)
2992 && S_GET_SEGMENT (fx_addsy) != seg)
2993 || S_IS_WEAK (fx_addsy)))
2994 value += md_pcrel_from_section (fixP, seg);
886a2506 2995
4670103e
CZ		 2996 switch (fixP->fx_r_type)
2997 {
2998 case BFD_RELOC_ARC_32_ME:
2999 /* This is a pc-relative value in a LIMM. Adjust it to the
3000 address of the instruction not to the address of the
33eaf5de 3001 LIMM. Note: it is not any longer valid this affirmation as
4670103e
CZ		 3002 the linker consider ARC_PC32 a fixup to entire 64 bit
3003 insn. */
3004 fixP->fx_offset += fixP->fx_frag->fr_address;
3005 /* Fall through. */
3006 case BFD_RELOC_32:
3007 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
3008 /* Fall through. */
3009 case BFD_RELOC_ARC_PC32:
3010 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 3011 break;
3012 default:
4670103e 3013 if ((int) fixP->fx_r_type < 0)
6e3f3473 3014 as_bad_where (fixP->fx_file, fixP->fx_line,
3015 _("PC relative relocation not allowed for (internal)"
3016 " type %d"),
3017 fixP->fx_r_type);
886a2506 3018 break;
ea1562b3
NC		 3019 }
3020 }
3021
4670103e
CZ		 3022 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
3023 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
3024 ((int) fixP->fx_r_type < 0) ? "Internal":
3025 bfd_get_reloc_code_name (fixP->fx_r_type), value,
3026 fixP->fx_offset);
886a2506 3027
886a2506 3028
4670103e
CZ		 3029 /* Now check for TLS relocations. */
3030 reloc = fixP->fx_r_type;
3031 switch (reloc)
886a2506 3032 {
4670103e
CZ		 3033 case BFD_RELOC_ARC_TLS_DTPOFF:
3034 case BFD_RELOC_ARC_TLS_LE_32:
3035 if (fixP->fx_done)
3036 break;
3037 /* Fall through. */
3038 case BFD_RELOC_ARC_TLS_GD_GOT:
3039 case BFD_RELOC_ARC_TLS_IE_GOT:
3040 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3041 break;
886a2506 3042
4670103e
CZ		 3043 case BFD_RELOC_ARC_TLS_GD_LD:
3044 gas_assert (!fixP->fx_offset);
3045 if (fixP->fx_subsy)
3046 fixP->fx_offset
3047 = (S_GET_VALUE (fixP->fx_subsy)
3048 - fixP->fx_frag->fr_address- fixP->fx_where);
3049 fixP->fx_subsy = NULL;
3050 /* Fall through. */
3051 case BFD_RELOC_ARC_TLS_GD_CALL:
3052 /* These two relocs are there just to allow ld to change the tls
3053 model for this symbol, by patching the code. The offset -
3054 and scale, if any - will be installed by the linker. */
3055 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3056 break;
886a2506 3057
4670103e
CZ		 3058 case BFD_RELOC_ARC_TLS_LE_S9:
3059 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
3060 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3061 break;
3062
3063 default:
3064 break;
886a2506
NC		 3065 }
3066
4670103e 3067 if (!fixP->fx_done)
886a2506 3068 {
4670103e 3069 return;
886a2506 3070 }
886a2506 3071
33eaf5de 3072 /* Adjust the value if we have a constant. */
4670103e 3073 value += fx_offset;
886a2506 3074
4670103e
CZ		 3075 /* For hosts with longs bigger than 32-bits make sure that the top
3076 bits of a 32-bit negative value read in by the parser are set,
3077 so that the correct comparisons are made. */
3078 if (value & 0x80000000)
69c9e028 3079 value |= (-1UL << 31);
886a2506 3080
4670103e
CZ		 3081 reloc = fixP->fx_r_type;
3082 switch (reloc)
3083 {
3084 case BFD_RELOC_8:
3085 case BFD_RELOC_16:
3086 case BFD_RELOC_24:
3087 case BFD_RELOC_32:
3088 case BFD_RELOC_64:
3089 case BFD_RELOC_ARC_32_PCREL:
3090 md_number_to_chars (fixpos, value, fixP->fx_size);
3091 return;
886a2506 3092
4670103e
CZ		 3093 case BFD_RELOC_ARC_GOTPC32:
3094 /* I cannot fix an GOTPC relocation because I need to relax it
3095 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3096 as_bad (_("Unsupported operation on reloc"));
3097 return;
886a2506 3098
4670103e
CZ		 3099 case BFD_RELOC_ARC_TLS_DTPOFF:
3100 case BFD_RELOC_ARC_TLS_LE_32:
3101 gas_assert (!fixP->fx_addsy);
3102 gas_assert (!fixP->fx_subsy);
1a0670f3 3103 /* Fall through. */
886a2506 3104
4670103e
CZ		 3105 case BFD_RELOC_ARC_GOTOFF:
3106 case BFD_RELOC_ARC_32_ME:
3107 case BFD_RELOC_ARC_PC32:
3108 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3109 return;
886a2506 3110
4670103e
CZ		 3111 case BFD_RELOC_ARC_PLT32:
3112 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3113 return;
886a2506 3114
4670103e
CZ		 3115 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3116 reloc = BFD_RELOC_ARC_S25W_PCREL;
3117 goto solve_plt;
886a2506 3118
4670103e
CZ		 3119 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3120 reloc = BFD_RELOC_ARC_S21H_PCREL;
3121 goto solve_plt;
886a2506 3122
4670103e
CZ		 3123 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3124 reloc = BFD_RELOC_ARC_S25W_PCREL;
3125 goto solve_plt;
886a2506 3126
4670103e
CZ		 3127 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3128 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 3129 /* Fall through. */
886a2506 3130
4670103e
CZ		 3131 case BFD_RELOC_ARC_S25W_PCREL:
3132 case BFD_RELOC_ARC_S21W_PCREL:
3133 case BFD_RELOC_ARC_S21H_PCREL:
3134 case BFD_RELOC_ARC_S25H_PCREL:
3135 case BFD_RELOC_ARC_S13_PCREL:
3136 solve_plt:
3137 operand = find_operand_for_reloc (reloc);
3138 gas_assert (operand);
886a2506
NC		 3139 break;
3140
3141 default:
4670103e
CZ		 3142 {
3143 if ((int) fixP->fx_r_type >= 0)
3144 as_fatal (_("unhandled relocation type %s"),
3145 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 3146
4670103e
CZ		 3147 /* The rest of these fixups needs to be completely resolved as
3148 constants. */
3149 if (fixP->fx_addsy != 0
3150 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3151 as_bad_where (fixP->fx_file, fixP->fx_line,
3152 _("non-absolute expression in constant field"));
886a2506 3153
4670103e
CZ		 3154 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3155 operand = &arc_operands[-(int) fixP->fx_r_type];
3156 break;
3157 }
3158 }
886a2506 3159
4670103e 3160 if (target_big_endian)
886a2506 3161 {
4670103e 3162 switch (fixP->fx_size)
886a2506 3163 {
4670103e
CZ		 3164 case 4:
3165 insn = bfd_getb32 (fixpos);
3166 break;
3167 case 2:
3168 insn = bfd_getb16 (fixpos);
3169 break;
3170 default:
3171 as_bad_where (fixP->fx_file, fixP->fx_line,
3172 _("unknown fixup size"));
3173 }
3174 }
3175 else
3176 {
3177 insn = 0;
3178 switch (fixP->fx_size)
3179 {
3180 case 4:
3181 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3182 break;
3183 case 2:
3184 insn = bfd_getl16 (fixpos);
3185 break;
3186 default:
3187 as_bad_where (fixP->fx_file, fixP->fx_line,
3188 _("unknown fixup size"));
886a2506
NC		 3189 }
3190 }
886a2506 3191
4670103e
CZ		 3192 insn = insert_operand (insn, operand, (offsetT) value,
3193 fixP->fx_file, fixP->fx_line);
886a2506 3194
4670103e
CZ		 3195 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3196}
886a2506 3197
4670103e 3198/* Prepare machine-dependent frags for relaxation.
886a2506 3199
4670103e
CZ		 3200 Called just before relaxation starts. Any symbol that is now undefined
3201 will not become defined.
886a2506 3202
4670103e 3203 Return the correct fr_subtype in the frag.
886a2506 3204
4670103e
CZ		 3205 Return the initial "guess for fr_var" to caller. The guess for fr_var
3206 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3207 or fr_var contributes to our returned value.
886a2506 3208
4670103e
CZ		 3209 Although it may not be explicit in the frag, pretend
3210 fr_var starts with a value. */
886a2506 3211
4670103e
CZ		 3212int
3213md_estimate_size_before_relax (fragS *fragP,
3214 segT segment)
3215{
3216 int growth;
3217
3218 /* If the symbol is not located within the same section AND it's not
3219 an absolute section, use the maximum. OR if the symbol is a
3220 constant AND the insn is by nature not pc-rel, use the maximum.
3221 OR if the symbol is being equated against another symbol, use the
3222 maximum. OR if the symbol is weak use the maximum. */
3223 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3224 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3225 || (symbol_constant_p (fragP->fr_symbol)
3226 && !fragP->tc_frag_data.pcrel)
3227 || symbol_equated_p (fragP->fr_symbol)
3228 || S_IS_WEAK (fragP->fr_symbol))
3229 {
3230 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3231 ++fragP->fr_subtype;
3232 }
886a2506 3233
4670103e
CZ		 3234 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3235 fragP->fr_var = growth;
886a2506 3236
4670103e
CZ		 3237 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3238 fragP->fr_file, fragP->fr_line, growth);
886a2506 3239
4670103e
CZ		 3240 return growth;
3241}
886a2506 3242
4670103e
CZ		 3243/* Translate internal representation of relocation info to BFD target
3244 format. */
886a2506 3245
4670103e
CZ		 3246arelent *
3247tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3248 fixS *fixP)
3249{
3250 arelent *reloc;
3251 bfd_reloc_code_real_type code;
886a2506 3252
add39d23
TS		 3253 reloc = XNEW (arelent);
3254 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3255 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3256 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3257
4670103e
CZ		 3258 /* Make sure none of our internal relocations make it this far.
3259 They'd better have been fully resolved by this point. */
3260 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3261
4670103e 3262 code = fixP->fx_r_type;
886a2506 3263
4670103e
CZ		 3264 /* if we have something like add gp, pcl,
3265 _GLOBAL_OFFSET_TABLE_@gotpc. */
3266 if (code == BFD_RELOC_ARC_GOTPC32
3267 && GOT_symbol
3268 && fixP->fx_addsy == GOT_symbol)
3269 code = BFD_RELOC_ARC_GOTPC;
886a2506 3270
4670103e
CZ		 3271 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3272 if (reloc->howto == NULL)
886a2506 3273 {
4670103e
CZ		 3274 as_bad_where (fixP->fx_file, fixP->fx_line,
3275 _("cannot represent `%s' relocation in object file"),
3276 bfd_get_reloc_code_name (code));
3277 return NULL;
3278 }
886a2506 3279
4670103e
CZ		 3280 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3281 as_fatal (_("internal error? cannot generate `%s' relocation"),
3282 bfd_get_reloc_code_name (code));
886a2506 3283
4670103e 3284 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3285
05bbf016 3286 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3287
3288 return reloc;
886a2506
NC		 3289}
3290
4670103e
CZ		 3291/* Perform post-processing of machine-dependent frags after relaxation.
3292 Called after relaxation is finished.
3293 In: Address of frag.
3294 fr_type == rs_machine_dependent.
3295 fr_subtype is what the address relaxed to.
886a2506 3296
4670103e
CZ		 3297 Out: Any fixS:s and constants are set up. */
3298
3299void
3300md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3301 segT segment ATTRIBUTE_UNUSED,
3302 fragS *fragP)
886a2506 3303{
4670103e
CZ		 3304 const relax_typeS *table_entry;
3305 char *dest;
3306 const struct arc_opcode *opcode;
3307 struct arc_insn insn;
3308 int size, fix;
3309 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3310
871a6bd2 3311 fix = fragP->fr_fix;
4670103e
CZ		 3312 dest = fragP->fr_literal + fix;
3313 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3314
9e32d9ae 3315 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
b8281767 3316 "var: %" PRId64 "\n",
4670103e 3317 fragP->fr_file, fragP->fr_line,
b8281767 3318 fragP->fr_subtype, fix, (int64_t) fragP->fr_var);
886a2506 3319
4670103e
CZ		 3320 if (fragP->fr_subtype <= 0
3321 && fragP->fr_subtype >= arc_num_relax_opcodes)
3322 as_fatal (_("no relaxation found for this instruction."));
886a2506 3323
4670103e 3324 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3325
4670103e
CZ		 3326 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3327 relax_arg->nflg, &insn);
886a2506 3328
4670103e 3329 apply_fixups (&insn, fragP, fix);
886a2506 3330
91fdca6f 3331 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e 3332 gas_assert (table_entry->rlx_length == size);
5b7c81bd 3333 emit_insn0 (&insn, dest, true);
886a2506 3334
4670103e
CZ		 3335 fragP->fr_fix += table_entry->rlx_length;
3336 fragP->fr_var = 0;
886a2506
NC		 3337}
3338
4670103e
CZ		 3339/* We have no need to default values of symbols. We could catch
3340 register names here, but that is handled by inserting them all in
3341 the symbol table to begin with. */
886a2506 3342
4670103e
CZ		 3343symbolS *
3344md_undefined_symbol (char *name)
886a2506 3345{
4670103e
CZ		 3346 /* The arc abi demands that a GOT[0] should be referencible as
3347 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3348 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3349 if (((*name == '_')
3350 && (*(name+1) == 'G')
7ef0acc1 3351 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)))
886a2506 3352 {
4670103e
CZ		 3353 if (!GOT_symbol)
3354 {
3355 if (symbol_find (name))
3356 as_bad ("GOT already in symbol table");
3357
3358 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
e01e1cee 3359 &zero_address_frag, 0);
4670103e
CZ		 3360 };
3361 return GOT_symbol;
886a2506 3362 }
4670103e 3363 return NULL;
886a2506
NC		 3364}
3365
4670103e
CZ		 3366/* Turn a string in input_line_pointer into a floating point constant
3367 of type type, and store the appropriate bytes in *litP. The number
3368 of LITTLENUMS emitted is stored in *sizeP. An error message is
3369 returned, or NULL on OK. */
886a2506 3370
6d4af3c2 3371const char *
4670103e 3372md_atof (int type, char *litP, int *sizeP)
886a2506 3373{
4670103e
CZ		 3374 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3375}
886a2506 3376
4670103e
CZ		 3377/* Called for any expression that can not be recognized. When the
3378 function is called, `input_line_pointer' will point to the start of
2a1ebfb2
CZ		 3379 the expression. We use it when we have complex operations like
3380 @label1 - @label2. */
886a2506 3381
4670103e 3382void
2a1ebfb2 3383md_operand (expressionS *expressionP)
4670103e
CZ		 3384{
3385 char *p = input_line_pointer;
3386 if (*p == '@')
886a2506 3387 {
4670103e
CZ		 3388 input_line_pointer++;
3389 expressionP->X_op = O_symbol;
2a1ebfb2 3390 expressionP->X_md = O_absent;
4670103e
CZ		 3391 expression (expressionP);
3392 }
3393}
886a2506 3394
4670103e
CZ		 3395/* This function is called from the function 'expression', it attempts
3396 to parse special names (in our case register names). It fills in
3397 the expression with the identified register. It returns TRUE if
3398 it is a register and FALSE otherwise. */
886a2506 3399
5b7c81bd 3400bool
4670103e
CZ		 3401arc_parse_name (const char *name,
3402 struct expressionS *e)
3403{
3404 struct symbol *sym;
886a2506 3405
4670103e 3406 if (!assembling_insn)
5b7c81bd 3407 return false;
886a2506 3408
2a1ebfb2
CZ		 3409 if (e->X_op == O_symbol
3410 && e->X_md == O_absent)
5b7c81bd 3411 return false;
886a2506 3412
629310ab 3413 sym = str_hash_find (arc_reg_hash, name);
4670103e
CZ		 3414 if (sym)
3415 {
3416 e->X_op = O_register;
3417 e->X_add_number = S_GET_VALUE (sym);
5b7c81bd 3418 return true;
4670103e 3419 }
db18dbab 3420
629310ab 3421 sym = str_hash_find (arc_addrtype_hash, name);
db18dbab
GM		 3422 if (sym)
3423 {
3424 e->X_op = O_addrtype;
3425 e->X_add_number = S_GET_VALUE (sym);
5b7c81bd 3426 return true;
db18dbab
GM		 3427 }
3428
5b7c81bd 3429 return false;
4670103e 3430}
886a2506 3431
4670103e
CZ		 3432/* md_parse_option
3433 Invocation line includes a switch not recognized by the base assembler.
3434 See if it's a processor-specific option.
886a2506 3435
4670103e 3436 New options (supported) are:
886a2506 3437
4670103e
CZ		 3438 -mcpu=<cpu name> Assemble for selected processor
3439 -EB/-mbig-endian Big-endian
3440 -EL/-mlittle-endian Little-endian
3441 -mrelax Enable relaxation
886a2506 3442
4670103e 3443 The following CPU names are recognized:
ce440d63 3444 arc600, arc700, arcem, archs, nps400. */
886a2506 3445
4670103e 3446int
17b9d67d 3447md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3448{
4670103e
CZ		 3449 switch (c)
3450 {
3451 case OPTION_ARC600:
3452 case OPTION_ARC601:
3453 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3454
4670103e
CZ		 3455 case OPTION_ARC700:
3456 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3457
4670103e
CZ		 3458 case OPTION_ARCEM:
3459 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3460
4670103e
CZ		 3461 case OPTION_ARCHS:
3462 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3463
4670103e
CZ		 3464 case OPTION_MCPU:
3465 {
bb65a718 3466 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3467 break;
3468 }
886a2506 3469
4670103e
CZ		 3470 case OPTION_EB:
3471 arc_target_format = "elf32-bigarc";
3472 byte_order = BIG_ENDIAN;
3473 break;
886a2506 3474
4670103e
CZ		 3475 case OPTION_EL:
3476 arc_target_format = "elf32-littlearc";
3477 byte_order = LITTLE_ENDIAN;
3478 break;
886a2506 3479
4670103e 3480 case OPTION_CD:
53a346d8
CZ		 3481 selected_cpu.features |= CD;
3482 cl_features |= CD;
bb050a69 3483 arc_check_feature ();
4670103e 3484 break;
886a2506 3485
4670103e
CZ		 3486 case OPTION_RELAX:
3487 relaxation_state = 1;
3488 break;
886a2506 3489
bdd582db 3490 case OPTION_NPS400:
53a346d8
CZ		 3491 selected_cpu.features |= NPS400;
3492 cl_features |= NPS400;
bb050a69 3493 arc_check_feature ();
ce440d63 3494 break;
bdd582db 3495
ce440d63 3496 case OPTION_SPFP:
53a346d8
CZ		 3497 selected_cpu.features |= SPX;
3498 cl_features |= SPX;
bb050a69 3499 arc_check_feature ();
ce440d63
GM		 3500 break;
3501
3502 case OPTION_DPFP:
53a346d8
CZ		 3503 selected_cpu.features |= DPX;
3504 cl_features |= DPX;
bb050a69 3505 arc_check_feature ();
ce440d63
GM		 3506 break;
3507
3508 case OPTION_FPUDA:
53a346d8
CZ		 3509 selected_cpu.features |= DPA;
3510 cl_features |= DPA;
bb050a69 3511 arc_check_feature ();
ce440d63
GM		 3512 break;
3513
3514 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3515 case OPTION_USER_MODE:
3516 case OPTION_LD_EXT_MASK:
3517 case OPTION_SWAP:
3518 case OPTION_NORM:
3519 case OPTION_BARREL_SHIFT:
3520 case OPTION_MIN_MAX:
3521 case OPTION_NO_MPY:
3522 case OPTION_EA:
3523 case OPTION_MUL64:
3524 case OPTION_SIMD:
4670103e
CZ		 3525 case OPTION_XMAC_D16:
3526 case OPTION_XMAC_24:
3527 case OPTION_DSP_PACKA:
3528 case OPTION_CRC:
3529 case OPTION_DVBF:
3530 case OPTION_TELEPHONY:
3531 case OPTION_XYMEMORY:
3532 case OPTION_LOCK:
3533 case OPTION_SWAPE:
3534 case OPTION_RTSC:
8ddf6b2a
CZ		 3535 break;
3536
4670103e
CZ		 3537 default:
3538 return 0;
3539 }
886a2506 3540
4670103e
CZ		 3541 return 1;
3542}
886a2506 3543
a9752fdf
CZ		 3544/* Display the list of cpu names for use in the help text. */
3545
3546static void
3547arc_show_cpu_list (FILE *stream)
3548{
3549 int i, offset;
731f7c4e 3550 static const char *space_buf = " ";
a9752fdf 3551
731f7c4e
MR		 3552 fprintf (stream, "%s", space_buf);
3553 offset = strlen (space_buf);
a9752fdf
CZ		 3554 for (i = 0; cpu_types[i].name != NULL; ++i)
3555 {
5b7c81bd 3556 bool last = (cpu_types[i + 1].name == NULL);
a9752fdf
CZ		 3557
3558 /* If displaying the new cpu name string, and the ', ' (for all
3559 but the last one) will take us past a target width of 80
3560 characters, then it's time for a new line. */
3561 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3562 {
731f7c4e
MR		 3563 fprintf (stream, "\n%s", space_buf);
3564 offset = strlen (space_buf);
a9752fdf
CZ		 3565 }
3566
3567 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3568 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3569 }
3570}
3571
4670103e
CZ		 3572void
3573md_show_usage (FILE *stream)
3574{
3575 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3576
a9752fdf
CZ		 3577 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3578 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3579 arc_show_cpu_list (stream);
3580 fprintf (stream, "\n");
bdd582db
GM		 3581 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3582 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3583 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3584 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3585
3586 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
a9752fdf
CZ		 3587 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3588 " instructions\n");
3589 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3590 " instructions\n");
bdd582db
GM		 3591 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3592 "point\n\t\t\t instructions for ARC EM\n");
3593
4670103e
CZ		 3594 fprintf (stream,
3595 " -mcode-density\t enable code density option for ARC EM\n");
3596
3597 fprintf (stream, _("\
3598 -EB assemble code for a big-endian cpu\n"));
3599 fprintf (stream, _("\
3600 -EL assemble code for a little-endian cpu\n"));
3601 fprintf (stream, _("\
bdd582db
GM		 3602 -mrelax enable relaxation\n"));
3603
3604 fprintf (stream, _("The following ARC-specific assembler options are "
3605 "deprecated and are accepted\nfor compatibility only:\n"));
3606
3607 fprintf (stream, _(" -mEA\n"
3608 " -mbarrel-shifter\n"
3609 " -mbarrel_shifter\n"
3610 " -mcrc\n"
3611 " -mdsp-packa\n"
3612 " -mdsp_packa\n"
3613 " -mdvbf\n"
3614 " -mld-extension-reg-mask\n"
3615 " -mlock\n"
3616 " -mmac-24\n"
3617 " -mmac-d16\n"
3618 " -mmac_24\n"
3619 " -mmac_d16\n"
3620 " -mmin-max\n"
3621 " -mmin_max\n"
3622 " -mmul64\n"
3623 " -mno-mpy\n"
3624 " -mnorm\n"
3625 " -mrtsc\n"
3626 " -msimd\n"
3627 " -mswap\n"
3628 " -mswape\n"
3629 " -mtelephony\n"
3630 " -muser-mode-only\n"
3631 " -mxy\n"));
886a2506
NC		 3632}
3633
3634/* Find the proper relocation for the given opcode. */
3635
3636static extended_bfd_reloc_code_real_type
3637find_reloc (const char *name,
3638 const char *opcodename,
3639 const struct arc_flags *pflags,
3640 int nflg,
3641 extended_bfd_reloc_code_real_type reloc)
3642{
3643 unsigned int i;
3644 int j;
5b7c81bd 3645 bool found_flag, tmp;
886a2506
NC		 3646 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3647
3648 for (i = 0; i < arc_num_equiv_tab; i++)
3649 {
3650 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3651
3652 /* Find the entry. */
3653 if (strcmp (name, r->name))
3654 continue;
3655 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3656 continue;
24b368f8 3657 if (r->flags[0])
886a2506
NC		 3658 {
3659 if (!nflg)
3660 continue;
5b7c81bd 3661 found_flag = false;
24b368f8
CZ		 3662 unsigned * psflg = (unsigned *)r->flags;
3663 do
3664 {
5b7c81bd 3665 tmp = false;
24b368f8
CZ		 3666 for (j = 0; j < nflg; j++)
3667 if (!strcmp (pflags[j].name,
3668 arc_flag_operands[*psflg].name))
3669 {
5b7c81bd 3670 tmp = true;
24b368f8
CZ		 3671 break;
3672 }
3673 if (!tmp)
3674 {
5b7c81bd 3675 found_flag = false;
24b368f8
CZ		 3676 break;
3677 }
3678 else
3679 {
5b7c81bd 3680 found_flag = true;
24b368f8
CZ		 3681 }
3682 ++ psflg;
3683 } while (*psflg);
3684
886a2506
NC		 3685 if (!found_flag)
3686 continue;
3687 }
3688
3689 if (reloc != r->oldreloc)
3690 continue;
3691 /* Found it. */
3692 ret = r->newreloc;
3693 break;
3694 }
3695
3696 if (ret == BFD_RELOC_UNUSED)
3697 as_bad (_("Unable to find %s relocation for instruction %s"),
3698 name, opcodename);
3699 return ret;
3700}
3701
4670103e
CZ		 3702/* All the symbol types that are allowed to be used for
3703 relaxation. */
3704
5b7c81bd 3705static bool
4670103e
CZ		 3706may_relax_expr (expressionS tok)
3707{
3708 /* Check if we have unrelaxable relocs. */
3709 switch (tok.X_md)
3710 {
3711 default:
3712 break;
3713 case O_plt:
5b7c81bd 3714 return false;
4670103e
CZ		 3715 }
3716
3717 switch (tok.X_op)
3718 {
3719 case O_symbol:
3720 case O_multiply:
3721 case O_divide:
3722 case O_modulus:
3723 case O_add:
3724 case O_subtract:
3725 break;
3726
3727 default:
5b7c81bd 3728 return false;
4670103e 3729 }
5b7c81bd 3730 return true;
4670103e
CZ		 3731}
3732
3733/* Checks if flags are in line with relaxable insn. */
3734
5b7c81bd 3735static bool
4670103e
CZ		 3736relaxable_flag (const struct arc_relaxable_ins *ins,
3737 const struct arc_flags *pflags,
3738 int nflgs)
3739{
3740 unsigned flag_class,
3741 flag,
3742 flag_class_idx = 0,
3743 flag_idx = 0;
3744
3745 const struct arc_flag_operand *flag_opand;
3746 int i, counttrue = 0;
3747
3748 /* Iterate through flags classes. */
3749 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3750 {
3751 /* Iterate through flags in flag class. */
3752 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3753 != 0)
3754 {
3755 flag_opand = &arc_flag_operands[flag];
3756 /* Iterate through flags in ins to compare. */
3757 for (i = 0; i < nflgs; ++i)
3758 {
3759 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3760 ++counttrue;
3761 }
3762
3763 ++flag_idx;
3764 }
3765
3766 ++flag_class_idx;
3767 flag_idx = 0;
3768 }
3769
3770 /* If counttrue == nflgs, then all flags have been found. */
63b4cc53 3771 return counttrue == nflgs;
4670103e
CZ		 3772}
3773
3774/* Checks if operands are in line with relaxable insn. */
3775
5b7c81bd 3776static bool
4670103e
CZ		 3777relaxable_operand (const struct arc_relaxable_ins *ins,
3778 const expressionS *tok,
3779 int ntok)
3780{
3781 const enum rlx_operand_type *operand = &ins->operands[0];
3782 int i = 0;
3783
3784 while (*operand != EMPTY)
3785 {
3786 const expressionS *epr = &tok[i];
3787
3788 if (i != 0 && i >= ntok)
5b7c81bd 3789 return false;
4670103e
CZ		 3790
3791 switch (*operand)
3792 {
3793 case IMMEDIATE:
3794 if (!(epr->X_op == O_multiply
3795 || epr->X_op == O_divide
3796 || epr->X_op == O_modulus
3797 || epr->X_op == O_add
3798 || epr->X_op == O_subtract
3799 || epr->X_op == O_symbol))
5b7c81bd 3800 return false;
4670103e
CZ		 3801 break;
3802
3803 case REGISTER_DUP:
3804 if ((i <= 0)
3805 || (epr->X_add_number != tok[i - 1].X_add_number))
5b7c81bd 3806 return false;
4670103e
CZ		 3807 /* Fall through. */
3808 case REGISTER:
3809 if (epr->X_op != O_register)
5b7c81bd 3810 return false;
4670103e
CZ		 3811 break;
3812
3813 case REGISTER_S:
3814 if (epr->X_op != O_register)
5b7c81bd 3815 return false;
4670103e
CZ		 3816
3817 switch (epr->X_add_number)
3818 {
3819 case 0: case 1: case 2: case 3:
3820 case 12: case 13: case 14: case 15:
3821 break;
3822 default:
5b7c81bd 3823 return false;
4670103e
CZ		 3824 }
3825 break;
3826
3827 case REGISTER_NO_GP:
3828 if ((epr->X_op != O_register)
3829 || (epr->X_add_number == 26)) /* 26 is the gp register. */
5b7c81bd 3830 return false;
4670103e
CZ		 3831 break;
3832
3833 case BRACKET:
3834 if (epr->X_op != O_bracket)
5b7c81bd 3835 return false;
4670103e
CZ		 3836 break;
3837
3838 default:
3839 /* Don't understand, bail out. */
5b7c81bd 3840 return false;
4670103e
CZ		 3841 break;
3842 }
3843
3844 ++i;
3845 operand = &ins->operands[i];
3846 }
3847
63b4cc53 3848 return i == ntok;
4670103e
CZ		 3849}
3850
3851/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3852
5b7c81bd 3853static bool
4670103e
CZ		 3854relax_insn_p (const struct arc_opcode *opcode,
3855 const expressionS *tok,
3856 int ntok,
3857 const struct arc_flags *pflags,
3858 int nflg)
3859{
3860 unsigned i;
5b7c81bd 3861 bool rv = false;
4670103e
CZ		 3862
3863 /* Check the relaxation table. */
3864 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3865 {
3866 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3867
3868 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3869 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3870 && relaxable_operand (arc_rlx_ins, tok, ntok)
3871 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3872 {
5b7c81bd 3873 rv = true;
4670103e
CZ		 3874 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3875 memcpy (&frag_now->tc_frag_data.tok, tok,
3876 sizeof (expressionS) * ntok);
3877 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3878 sizeof (struct arc_flags) * nflg);
3879 frag_now->tc_frag_data.nflg = nflg;
3880 frag_now->tc_frag_data.ntok = ntok;
3881 break;
3882 }
3883 }
3884
3885 return rv;
3886}
3887
886a2506
NC		 3888/* Turn an opcode description and a set of arguments into
3889 an instruction and a fixup. */
3890
3891static void
3892assemble_insn (const struct arc_opcode *opcode,
3893 const expressionS *tok,
3894 int ntok,
3895 const struct arc_flags *pflags,
3896 int nflg,
3897 struct arc_insn *insn)
3898{
3899 const expressionS *reloc_exp = NULL;
bdfe53e3 3900 unsigned long long image;
886a2506
NC		 3901 const unsigned char *argidx;
3902 int i;
3903 int tokidx = 0;
3904 unsigned char pcrel = 0;
5b7c81bd
AM		 3905 bool needGOTSymbol;
3906 bool has_delay_slot = false;
886a2506
NC		 3907 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3908
3909 memset (insn, 0, sizeof (*insn));
3910 image = opcode->opcode;
3911
bdfe53e3 3912 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3913 frag_now->fr_file, frag_now->fr_line, opcode->name,
3914 opcode->opcode);
3915
3916 /* Handle operands. */
3917 for (argidx = opcode->operands; *argidx; ++argidx)
3918 {
3919 const struct arc_operand *operand = &arc_operands[*argidx];
3920 const expressionS *t = (const expressionS *) 0;
3921
db18dbab 3922 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3923 continue;
3924
3925 if (operand->flags & ARC_OPERAND_DUPLICATE)
3926 {
3927 /* Duplicate operand, already inserted. */
3928 tokidx ++;
3929 continue;
3930 }
3931
3932 if (tokidx >= ntok)
3933 {
3934 abort ();
3935 }
3936 else
3937 t = &tok[tokidx++];
3938
3939 /* Regardless if we have a reloc or not mark the instruction
3940 limm if it is the case. */
3941 if (operand->flags & ARC_OPERAND_LIMM)
5b7c81bd 3942 insn->has_limm = true;
886a2506
NC		 3943
3944 switch (t->X_op)
3945 {
3946 case O_register:
3947 image = insert_operand (image, operand, regno (t->X_add_number),
3948 NULL, 0);
3949 break;
3950
3951 case O_constant:
3952 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3953 reloc_exp = t;
3954 if (operand->flags & ARC_OPERAND_LIMM)
3955 insn->limm = t->X_add_number;
3956 break;
3957
3958 case O_bracket:
db18dbab
GM		 3959 case O_colon:
3960 case O_addrtype:
3961 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3962 break;
3963
3964 case O_absent:
3965 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3966 break;
3967
3968 case O_subtract:
3969 /* Maybe register range. */
3970 if ((t->X_add_number == 0)
3971 && contains_register (t->X_add_symbol)
3972 && contains_register (t->X_op_symbol))
3973 {
3974 int regs;
3975
3976 regs = get_register (t->X_add_symbol);
3977 regs <<= 16;
3978 regs |= get_register (t->X_op_symbol);
3979 image = insert_operand (image, operand, regs, NULL, 0);
3980 break;
3981 }
1a0670f3 3982 /* Fall through. */
886a2506
NC		 3983
3984 default:
3985 /* This operand needs a relocation. */
5b7c81bd 3986 needGOTSymbol = false;
886a2506
NC		 3987
3988 switch (t->X_md)
3989 {
3990 case O_plt:
c810e0b8 3991 if (opcode->insn_class == JUMP)
6e3f3473 3992 as_bad (_("Unable to use @plt relocation for insn %s"),
3993 opcode->name);
5b7c81bd 3994 needGOTSymbol = true;
886a2506
NC		 3995 reloc = find_reloc ("plt", opcode->name,
3996 pflags, nflg,
3997 operand->default_reloc);
3998 break;
3999
4000 case O_gotoff:
4001 case O_gotpc:
5b7c81bd 4002 needGOTSymbol = true;
886a2506
NC		 4003 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4004 break;
4005 case O_pcl:
cc07cda6
CZ		 4006 if (operand->flags & ARC_OPERAND_LIMM)
4007 {
4008 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4009 if (arc_opcode_len (opcode) == 2
4010 || opcode->insn_class == JUMP)
6e3f3473 4011 as_bad (_("Unable to use @pcl relocation for insn %s"),
4012 opcode->name);
cc07cda6
CZ		 4013 }
4014 else
4015 {
4016 /* This is a relaxed operand which initially was
4017 limm, choose whatever we have defined in the
4018 opcode as reloc. */
4019 reloc = operand->default_reloc;
4020 }
886a2506
NC		 4021 break;
4022 case O_sda:
4023 reloc = find_reloc ("sda", opcode->name,
4024 pflags, nflg,
4025 operand->default_reloc);
4026 break;
4027 case O_tlsgd:
4028 case O_tlsie:
5b7c81bd 4029 needGOTSymbol = true;
886a2506
NC		 4030 /* Fall-through. */
4031
4032 case O_tpoff:
4033 case O_dtpoff:
4034 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4035 break;
4036
4037 case O_tpoff9: /*FIXME! Check for the conditionality of
4038 the insn. */
4039 case O_dtpoff9: /*FIXME! Check for the conditionality of
4040 the insn. */
4041 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4042 break;
4043
4044 default:
4045 /* Just consider the default relocation. */
4046 reloc = operand->default_reloc;
4047 break;
4048 }
4049
4050 if (needGOTSymbol && (GOT_symbol == NULL))
4051 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4052
4053 reloc_exp = t;
4054
4055#if 0
4056 if (reloc > 0)
4057 {
4058 /* sanity checks. */
4059 reloc_howto_type *reloc_howto
4060 = bfd_reloc_type_lookup (stdoutput,
4061 (bfd_reloc_code_real_type) reloc);
4062 unsigned reloc_bitsize = reloc_howto->bitsize;
4063 if (reloc_howto->rightshift)
4064 reloc_bitsize -= reloc_howto->rightshift;
4065 if (reloc_bitsize != operand->bits)
4066 {
4067 as_bad (_("invalid relocation %s for field"),
4068 bfd_get_reloc_code_name (reloc));
4069 return;
4070 }
4071 }
4072#endif
4073 if (insn->nfixups >= MAX_INSN_FIXUPS)
4074 as_fatal (_("too many fixups"));
4075
4076 struct arc_fixup *fixup;
4077 fixup = &insn->fixups[insn->nfixups++];
4078 fixup->exp = *t;
4079 fixup->reloc = reloc;
cc07cda6
CZ		 4080 if ((int) reloc < 0)
4081 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4082 else
4083 {
4084 reloc_howto_type *reloc_howto =
4085 bfd_reloc_type_lookup (stdoutput,
4086 (bfd_reloc_code_real_type) fixup->reloc);
4087 pcrel = reloc_howto->pc_relative;
4088 }
886a2506 4089 fixup->pcrel = pcrel;
63b4cc53 4090 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) != 0;
886a2506
NC		 4091 break;
4092 }
4093 }
4094
4095 /* Handle flags. */
4096 for (i = 0; i < nflg; i++)
4097 {
f36e33da 4098 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 4099
4100 /* Check if the instruction has a delay slot. */
4101 if (!strcmp (flg_operand->name, "d"))
5b7c81bd 4102 has_delay_slot = true;
886a2506 4103
2c52e2e8
RZ		 4104 /* There is an exceptional case when we cannot insert a flag just as
4105 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4106 relation with the relative address. Unfortunately, some of the
4107 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4108 handled in the normal way.
4109
4110 Flag operands don't have an architecture field, so we can't
4111 directly validate that FLAG_OPERAND is valid for the current
4112 architecture, what we do instead is just validate that we're
4113 assembling for an ARCv2 architecture. */
4114 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4115 && (!strcmp (flg_operand->name, "t")
4116 || !strcmp (flg_operand->name, "nt")))
886a2506
NC		 4117 {
4118 unsigned bitYoperand = 0;
4119 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4120 if (!strcmp (flg_operand->name, "t"))
4121 if (!strcmp (opcode->name, "bbit0")
4122 || !strcmp (opcode->name, "bbit1"))
4123 bitYoperand = arc_NToperand;
4124 else
4125 bitYoperand = arc_Toperand;
4126 else
4127 if (!strcmp (opcode->name, "bbit0")
4128 || !strcmp (opcode->name, "bbit1"))
4129 bitYoperand = arc_Toperand;
4130 else
4131 bitYoperand = arc_NToperand;
4132
4133 gas_assert (reloc_exp != NULL);
4134 if (reloc_exp->X_op == O_constant)
4135 {
4136 /* Check if we have a constant and solved it
4137 immediately. */
4138 offsetT val = reloc_exp->X_add_number;
4139 image |= insert_operand (image, &arc_operands[bitYoperand],
4140 val, NULL, 0);
4141 }
4142 else
4143 {
4144 struct arc_fixup *fixup;
4145
4146 if (insn->nfixups >= MAX_INSN_FIXUPS)
4147 as_fatal (_("too many fixups"));
4148
4149 fixup = &insn->fixups[insn->nfixups++];
4150 fixup->exp = *reloc_exp;
4151 fixup->reloc = -bitYoperand;
4152 fixup->pcrel = pcrel;
5b7c81bd 4153 fixup->islong = false;
886a2506
NC		 4154 }
4155 }
4156 else
4157 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4158 << flg_operand->shift;
4159 }
4160
4670103e
CZ		 4161 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4162
91fdca6f 4163 /* Instruction length. */
06fe285f 4164 insn->len = arc_opcode_len (opcode);
886a2506
NC		 4165
4166 insn->insn = image;
4167
4168 /* Update last insn status. */
4169 arc_last_insns[1] = arc_last_insns[0];
4170 arc_last_insns[0].opcode = opcode;
4171 arc_last_insns[0].has_limm = insn->has_limm;
4172 arc_last_insns[0].has_delay_slot = has_delay_slot;
4173
4174 /* Check if the current instruction is legally used. */
4175 if (arc_last_insns[1].has_delay_slot
4176 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
6e3f3473 4177 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4178 arc_last_insns[1].opcode->name,
4179 arc_last_insns[0].opcode->name);
cf9bdae9 4180 if (arc_last_insns[1].has_delay_slot
4181 && arc_last_insns[0].has_limm)
4182 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4183 arc_last_insns[1].opcode->name,
4184 arc_last_insns[0].opcode->name);
886a2506
NC		 4185}
4186
886a2506
NC		 4187void
4188arc_handle_align (fragS* fragP)
4189{
4190 if ((fragP)->fr_type == rs_align_code)
4191 {
4192 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4193 valueT count = ((fragP)->fr_next->fr_address
4194 - (fragP)->fr_address - (fragP)->fr_fix);
4195
4196 (fragP)->fr_var = 2;
4197
4198 if (count & 1)/* Padding in the gap till the next 2-byte
4199 boundary with 0s. */
4200 {
4201 (fragP)->fr_fix++;
4202 *dest++ = 0;
4203 }
4204 /* Writing nop_s. */
4205 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4206 }
4207}
4208
4209/* Here we decide which fixups can be adjusted to make them relative
4210 to the beginning of the section instead of the symbol. Basically
4211 we need to make sure that the dynamic relocations are done
4212 correctly, so in some cases we force the original symbol to be
4213 used. */
4214
4215int
4216tc_arc_fix_adjustable (fixS *fixP)
4217{
4218
4219 /* Prevent all adjustments to global symbols. */
4220 if (S_IS_EXTERNAL (fixP->fx_addsy))
4221 return 0;
4222 if (S_IS_WEAK (fixP->fx_addsy))
4223 return 0;
4224
4225 /* Adjust_reloc_syms doesn't know about the GOT. */
4226 switch (fixP->fx_r_type)
4227 {
4228 case BFD_RELOC_ARC_GOTPC32:
4229 case BFD_RELOC_ARC_PLT32:
4230 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4231 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4232 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4233 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4234 return 0;
4235
4236 default:
4237 break;
4238 }
4239
841fdfcd 4240 return 1;
886a2506
NC		 4241}
4242
4243/* Compute the reloc type of an expression EXP. */
4244
4245static void
4246arc_check_reloc (expressionS *exp,
4247 bfd_reloc_code_real_type *r_type_p)
4248{
4249 if (*r_type_p == BFD_RELOC_32
4250 && exp->X_op == O_subtract
4251 && exp->X_op_symbol != NULL
8d1015a8 4252 && S_GET_SEGMENT (exp->X_op_symbol) == now_seg)
6f4b1afc 4253 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4254}
4255
4256
4257/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4258
4259void
4260arc_cons_fix_new (fragS *frag,
4261 int off,
4262 int size,
4263 expressionS *exp,
4264 bfd_reloc_code_real_type r_type)
4265{
4266 r_type = BFD_RELOC_UNUSED;
4267
4268 switch (size)
4269 {
4270 case 1:
4271 r_type = BFD_RELOC_8;
4272 break;
4273
4274 case 2:
4275 r_type = BFD_RELOC_16;
4276 break;
4277
4278 case 3:
4279 r_type = BFD_RELOC_24;
4280 break;
4281
4282 case 4:
4283 r_type = BFD_RELOC_32;
4284 arc_check_reloc (exp, &r_type);
4285 break;
4286
4287 case 8:
4288 r_type = BFD_RELOC_64;
4289 break;
4290
4291 default:
4292 as_bad (_("unsupported BFD relocation size %u"), size);
4293 r_type = BFD_RELOC_UNUSED;
4294 }
4295
4296 fix_new_exp (frag, off, size, exp, 0, r_type);
4297}
4298
4299/* The actual routine that checks the ZOL conditions. */
4300
4301static void
4302check_zol (symbolS *s)
4303{
bb65a718 4304 switch (selected_cpu.mach)
886a2506
NC		 4305 {
4306 case bfd_mach_arc_arcv2:
bb65a718 4307 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4308 return;
4309
4310 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4311 || arc_last_insns[1].has_delay_slot)
4312 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4313 S_GET_NAME (s));
4314
4315 break;
4316 case bfd_mach_arc_arc600:
4317
4318 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4319 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4320 S_GET_NAME (s));
4321
4322 if (arc_last_insns[0].has_limm
4323 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4324 as_bad (_("A jump instruction with long immediate detected at the \
4325end of the ZOL label @%s"), S_GET_NAME (s));
4326
4327 /* Fall through. */
4328 case bfd_mach_arc_arc700:
4329 if (arc_last_insns[0].has_delay_slot)
4330 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4331 S_GET_NAME (s));
4332
4333 break;
4334 default:
4335 break;
4336 }
4337}
4338
4339/* If ZOL end check the last two instruction for illegals. */
4340void
4341arc_frob_label (symbolS * sym)
4342{
4343 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4344 check_zol (sym);
4345
4346 dwarf2_emit_label (sym);
ea1562b3 4347}
4670103e
CZ		 4348
4349/* Used because generic relaxation assumes a pc-rel value whilst we
4350 also relax instructions that use an absolute value resolved out of
4351 relative values (if that makes any sense). An example: 'add r1,
4352 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4353 but if they're in the same section we can subtract the section
4354 offset relocation which ends up in a resolved value. So if @.L2 is
4355 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4356 .text + 0x40 = 0x10. */
4357int
4358arc_pcrel_adjust (fragS *fragP)
4359{
cc07cda6
CZ		 4360 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4361 fragP->fr_address, fragP->fr_fix,
4362 fragP->tc_frag_data.pcrel ? "Y" : "N");
4363
4670103e
CZ		 4364 if (!fragP->tc_frag_data.pcrel)
4365 return fragP->fr_address + fragP->fr_fix;
4366
cc07cda6
CZ		 4367 /* Take into account the PCL rounding. */
4368 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4670103e 4369}
726c18e1
CZ		 4370
4371/* Initialize the DWARF-2 unwind information for this procedure. */
4372
4373void
4374tc_arc_frame_initial_instructions (void)
4375{
4376 /* Stack pointer is register 28. */
45a54ee5 4377 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4378}
4379
4380int
4381tc_arc_regname_to_dw2regnum (char *regname)
4382{
4383 struct symbol *sym;
4384
629310ab 4385 sym = str_hash_find (arc_reg_hash, regname);
726c18e1
CZ		 4386 if (sym)
4387 return S_GET_VALUE (sym);
4388
4389 return -1;
4390}
37ab9779
CZ		 4391
4392/* Adjust the symbol table. Delete found AUX register symbols. */
4393
4394void
4395arc_adjust_symtab (void)
4396{
4397 symbolS * sym;
4398
4399 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4400 {
4401 /* I've created a symbol during parsing process. Now, remove
4402 the symbol as it is found to be an AUX register. */
4403 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4404 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4405 }
4406
4407 /* Now do generic ELF adjustments. */
4408 elf_adjust_symtab ();
4409}
b99747ae
CZ		 4410
4411static void
4412tokenize_extinsn (extInstruction_t *einsn)
4413{
4414 char *p, c;
4415 char *insn_name;
4416 unsigned char major_opcode;
4417 unsigned char sub_opcode;
4418 unsigned char syntax_class = 0;
4419 unsigned char syntax_class_modifiers = 0;
4420 unsigned char suffix_class = 0;
4421 unsigned int i;
4422
4423 SKIP_WHITESPACE ();
4424
4425 /* 1st: get instruction name. */
4426 p = input_line_pointer;
4427 c = get_symbol_name (&p);
4428
4429 insn_name = xstrdup (p);
4430 restore_line_pointer (c);
4431
f02806be 4432 /* Convert to lower case. */
4433 for (p = insn_name; *p; ++p)
4434 *p = TOLOWER (*p);
4435
b99747ae
CZ		 4436 /* 2nd: get major opcode. */
4437 if (*input_line_pointer != ',')
4438 {
4439 as_bad (_("expected comma after instruction name"));
4440 ignore_rest_of_line ();
4441 return;
4442 }
4443 input_line_pointer++;
4444 major_opcode = get_absolute_expression ();
4445
4446 /* 3rd: get sub-opcode. */
4447 SKIP_WHITESPACE ();
4448
4449 if (*input_line_pointer != ',')
4450 {
4451 as_bad (_("expected comma after major opcode"));
4452 ignore_rest_of_line ();
4453 return;
4454 }
4455 input_line_pointer++;
4456 sub_opcode = get_absolute_expression ();
4457
4458 /* 4th: get suffix class. */
4459 SKIP_WHITESPACE ();
4460
4461 if (*input_line_pointer != ',')
4462 {
4463 as_bad ("expected comma after sub opcode");
4464 ignore_rest_of_line ();
4465 return;
4466 }
4467 input_line_pointer++;
4468
4469 while (1)
4470 {
4471 SKIP_WHITESPACE ();
4472
4473 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4474 {
4475 if (!strncmp (suffixclass[i].name, input_line_pointer,
4476 suffixclass[i].len))
4477 {
c810e0b8 4478 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4479 input_line_pointer += suffixclass[i].len;
4480 break;
4481 }
4482 }
4483
4484 if (i == ARRAY_SIZE (suffixclass))
4485 {
4486 as_bad ("invalid suffix class");
4487 ignore_rest_of_line ();
4488 return;
4489 }
4490
4491 SKIP_WHITESPACE ();
4492
4493 if (*input_line_pointer == '|')
4494 input_line_pointer++;
4495 else
4496 break;
4497 }
4498
4499 /* 5th: get syntax class and syntax class modifiers. */
4500 if (*input_line_pointer != ',')
4501 {
4502 as_bad ("expected comma after suffix class");
4503 ignore_rest_of_line ();
4504 return;
4505 }
4506 input_line_pointer++;
4507
4508 while (1)
4509 {
4510 SKIP_WHITESPACE ();
4511
4512 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4513 {
4514 if (!strncmp (syntaxclassmod[i].name,
4515 input_line_pointer,
4516 syntaxclassmod[i].len))
4517 {
c810e0b8 4518 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4519 input_line_pointer += syntaxclassmod[i].len;
4520 break;
4521 }
4522 }
4523
4524 if (i == ARRAY_SIZE (syntaxclassmod))
4525 {
4526 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4527 {
4528 if (!strncmp (syntaxclass[i].name,
4529 input_line_pointer,
4530 syntaxclass[i].len))
4531 {
c810e0b8 4532 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4533 input_line_pointer += syntaxclass[i].len;
4534 break;
4535 }
4536 }
4537
4538 if (i == ARRAY_SIZE (syntaxclass))
4539 {
4540 as_bad ("missing syntax class");
4541 ignore_rest_of_line ();
4542 return;
4543 }
4544 }
4545
4546 SKIP_WHITESPACE ();
4547
4548 if (*input_line_pointer == '|')
4549 input_line_pointer++;
4550 else
4551 break;
4552 }
4553
4554 demand_empty_rest_of_line ();
4555
4556 einsn->name = insn_name;
4557 einsn->major = major_opcode;
4558 einsn->minor = sub_opcode;
4559 einsn->syntax = syntax_class;
4560 einsn->modsyn = syntax_class_modifiers;
4561 einsn->suffix = suffix_class;
4562 einsn->flags = syntax_class
4563 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4564}
4565
4566/* Generate an extension section. */
4567
4568static int
4569arc_set_ext_seg (void)
4570{
4571 if (!arcext_section)
4572 {
4573 arcext_section = subseg_new (".arcextmap", 0);
fd361982 4574 bfd_set_section_flags (arcext_section, SEC_READONLY | SEC_HAS_CONTENTS);
b99747ae
CZ		 4575 }
4576 else
4577 subseg_set (arcext_section, 0);
4578 return 1;
4579}
4580
4581/* Create an extension instruction description in the arc extension
4582 section of the output file.
4583 The structure for an instruction is like this:
4584 [0]: Length of the record.
4585 [1]: Type of the record.
4586
4587 [2]: Major opcode.
4588 [3]: Sub-opcode.
4589 [4]: Syntax (flags).
4590 [5]+ Name instruction.
4591
4592 The sequence is terminated by an empty entry. */
4593
4594static void
4595create_extinst_section (extInstruction_t *einsn)
4596{
4597
4598 segT old_sec = now_seg;
4599 int old_subsec = now_subseg;
4600 char *p;
4601 int name_len = strlen (einsn->name);
4602
4603 arc_set_ext_seg ();
4604
4605 p = frag_more (1);
4606 *p = 5 + name_len + 1;
4607 p = frag_more (1);
4608 *p = EXT_INSTRUCTION;
4609 p = frag_more (1);
4610 *p = einsn->major;
4611 p = frag_more (1);
4612 *p = einsn->minor;
4613 p = frag_more (1);
4614 *p = einsn->flags;
4615 p = frag_more (name_len + 1);
4616 strcpy (p, einsn->name);
4617
4618 subseg_set (old_sec, old_subsec);
4619}
4620
4621/* Handler .extinstruction pseudo-op. */
4622
4623static void
4624arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4625{
4626 extInstruction_t einsn;
4627 struct arc_opcode *arc_ext_opcodes;
4628 const char *errmsg = NULL;
4629 unsigned char moplow, mophigh;
4630
4631 memset (&einsn, 0, sizeof (einsn));
4632 tokenize_extinsn (&einsn);
4633
4634 /* Check if the name is already used. */
4635 if (arc_find_opcode (einsn.name))
4636 as_warn (_("Pseudocode already used %s"), einsn.name);
4637
4638 /* Check the opcode ranges. */
4639 moplow = 0x05;
bb65a718
AB		 4640 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4641 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4642
4643 if ((einsn.major > mophigh) || (einsn.major < moplow))
4644 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4645
4646 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4647 && (einsn.major != 5) && (einsn.major != 9))
4648 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4649
945e0f82 4650 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4651 {
4652 case ARC_SYNTAX_3OP:
4653 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4654 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4655 break;
4656 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4657 case ARC_SYNTAX_1OP:
4658 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4659 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4660 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4661 break;
4662 default:
4663 break;
4664 }
4665
bb65a718 4666 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4667 if (arc_ext_opcodes == NULL)
4668 {
4669 if (errmsg)
4670 as_fatal ("%s", errmsg);
4671 else
4672 as_fatal (_("Couldn't generate extension instruction opcodes"));
4673 }
4674 else if (errmsg)
4675 as_warn ("%s", errmsg);
4676
4677 /* Insert the extension instruction. */
4678 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4679
4680 create_extinst_section (&einsn);
4681}
4682
5b7c81bd 4683static bool
f36e33da
CZ		 4684tokenize_extregister (extRegister_t *ereg, int opertype)
4685{
4686 char *name;
4687 char *mode;
4688 char c;
4689 char *p;
4690 int number, imode = 0;
5b7c81bd
AM		 4691 bool isCore_p = opertype == EXT_CORE_REGISTER;
4692 bool isReg_p = opertype == EXT_CORE_REGISTER || opertype == EXT_AUX_REGISTER;
f36e33da
CZ		 4693
4694 /* 1st: get register name. */
4695 SKIP_WHITESPACE ();
4696 p = input_line_pointer;
4697 c = get_symbol_name (&p);
4698
4699 name = xstrdup (p);
4700 restore_line_pointer (c);
4701
4702 /* 2nd: get register number. */
4703 SKIP_WHITESPACE ();
4704
4705 if (*input_line_pointer != ',')
4706 {
06911889 4707 as_bad (_("expected comma after name"));
f36e33da
CZ		 4708 ignore_rest_of_line ();
4709 free (name);
5b7c81bd 4710 return false;
f36e33da
CZ		 4711 }
4712 input_line_pointer++;
4713 number = get_absolute_expression ();
4714
06911889
CZ		 4715 if ((number < 0)
4716 && (opertype != EXT_AUX_REGISTER))
f36e33da 4717 {
06911889
CZ		 4718 as_bad (_("%s second argument cannot be a negative number %d"),
4719 isCore_p ? "extCoreRegister's" : "extCondCode's",
4720 number);
f36e33da
CZ		 4721 ignore_rest_of_line ();
4722 free (name);
5b7c81bd 4723 return false;
f36e33da
CZ		 4724 }
4725
4726 if (isReg_p)
4727 {
4728 /* 3rd: get register mode. */
4729 SKIP_WHITESPACE ();
4730
4731 if (*input_line_pointer != ',')
4732 {
4733 as_bad (_("expected comma after register number"));
4734 ignore_rest_of_line ();
4735 free (name);
5b7c81bd 4736 return false;
f36e33da
CZ		 4737 }
4738
4739 input_line_pointer++;
4740 mode = input_line_pointer;
4741
d34049e8 4742 if (startswith (mode, "r|w"))
f36e33da
CZ		 4743 {
4744 imode = 0;
4745 input_line_pointer += 3;
4746 }
d34049e8 4747 else if (startswith (mode, "r"))
f36e33da
CZ		 4748 {
4749 imode = ARC_REGISTER_READONLY;
4750 input_line_pointer += 1;
4751 }
d34049e8 4752 else if (!startswith (mode, "w"))
f36e33da
CZ		 4753 {
4754 as_bad (_("invalid mode"));
4755 ignore_rest_of_line ();
4756 free (name);
5b7c81bd 4757 return false;
f36e33da
CZ		 4758 }
4759 else
4760 {
4761 imode = ARC_REGISTER_WRITEONLY;
4762 input_line_pointer += 1;
4763 }
4764 }
4765
4766 if (isCore_p)
4767 {
4768 /* 4th: get core register shortcut. */
4769 SKIP_WHITESPACE ();
4770 if (*input_line_pointer != ',')
4771 {
4772 as_bad (_("expected comma after register mode"));
4773 ignore_rest_of_line ();
4774 free (name);
5b7c81bd 4775 return false;
f36e33da
CZ		 4776 }
4777
4778 input_line_pointer++;
4779
d34049e8 4780 if (startswith (input_line_pointer, "cannot_shortcut"))
f36e33da
CZ		 4781 {
4782 imode |= ARC_REGISTER_NOSHORT_CUT;
4783 input_line_pointer += 15;
4784 }
d34049e8 4785 else if (!startswith (input_line_pointer, "can_shortcut"))
f36e33da
CZ		 4786 {
4787 as_bad (_("shortcut designator invalid"));
4788 ignore_rest_of_line ();
4789 free (name);
5b7c81bd 4790 return false;
f36e33da
CZ		 4791 }
4792 else
4793 {
4794 input_line_pointer += 12;
4795 }
4796 }
4797 demand_empty_rest_of_line ();
4798
4799 ereg->name = name;
4800 ereg->number = number;
4801 ereg->imode = imode;
5b7c81bd 4802 return true;
f36e33da
CZ		 4803}
4804
4805/* Create an extension register/condition description in the arc
4806 extension section of the output file.
4807
4808 The structure for an instruction is like this:
4809 [0]: Length of the record.
4810 [1]: Type of the record.
4811
4812 For core regs and condition codes:
4813 [2]: Value.
4814 [3]+ Name.
4815
33eaf5de 4816 For auxiliary registers:
f36e33da
CZ		 4817 [2..5]: Value.
4818 [6]+ Name
4819
4820 The sequence is terminated by an empty entry. */
4821
4822static void
4823create_extcore_section (extRegister_t *ereg, int opertype)
4824{
4825 segT old_sec = now_seg;
4826 int old_subsec = now_subseg;
4827 char *p;
4828 int name_len = strlen (ereg->name);
4829
4830 arc_set_ext_seg ();
4831
4832 switch (opertype)
4833 {
4834 case EXT_COND_CODE:
4835 case EXT_CORE_REGISTER:
4836 p = frag_more (1);
4837 *p = 3 + name_len + 1;
4838 p = frag_more (1);
4839 *p = opertype;
4840 p = frag_more (1);
4841 *p = ereg->number;
4842 break;
4843 case EXT_AUX_REGISTER:
4844 p = frag_more (1);
4845 *p = 6 + name_len + 1;
4846 p = frag_more (1);
4847 *p = EXT_AUX_REGISTER;
4848 p = frag_more (1);
4849 *p = (ereg->number >> 24) & 0xff;
4850 p = frag_more (1);
4851 *p = (ereg->number >> 16) & 0xff;
4852 p = frag_more (1);
4853 *p = (ereg->number >> 8) & 0xff;
4854 p = frag_more (1);
4855 *p = (ereg->number) & 0xff;
4856 break;
4857 default:
4858 break;
4859 }
4860
4861 p = frag_more (name_len + 1);
4862 strcpy (p, ereg->name);
4863
4864 subseg_set (old_sec, old_subsec);
4865}
4866
4867/* Handler .extCoreRegister pseudo-op. */
4868
4869static void
4870arc_extcorereg (int opertype)
4871{
4872 extRegister_t ereg;
4873 struct arc_aux_reg *auxr;
f36e33da
CZ		 4874 struct arc_flag_operand *ccode;
4875
4876 memset (&ereg, 0, sizeof (ereg));
06911889
CZ		 4877 if (!tokenize_extregister (&ereg, opertype))
4878 return;
f36e33da
CZ		 4879
4880 switch (opertype)
4881 {
4882 case EXT_CORE_REGISTER:
4883 /* Core register. */
4884 if (ereg.number > 60)
4885 as_bad (_("core register %s value (%d) too large"), ereg.name,
4886 ereg.number);
4887 declare_register (ereg.name, ereg.number);
4888 break;
4889 case EXT_AUX_REGISTER:
4890 /* Auxiliary register. */
add39d23 4891 auxr = XNEW (struct arc_aux_reg);
f36e33da 4892 auxr->name = ereg.name;
bb65a718 4893 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4894 auxr->subclass = NONE;
4895 auxr->address = ereg.number;
fe0e921f
AM		 4896 if (str_hash_insert (arc_aux_hash, auxr->name, auxr, 0) != NULL)
4897 as_bad (_("duplicate aux register %s"), auxr->name);
f36e33da
CZ		 4898 break;
4899 case EXT_COND_CODE:
4900 /* Condition code. */
4901 if (ereg.number > 31)
4902 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4903 ereg.number);
4904 ext_condcode.size ++;
4905 ext_condcode.arc_ext_condcode =
add39d23
TS		 4906 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4907 ext_condcode.size + 1);
f36e33da
CZ		 4908
4909 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4910 ccode->name = ereg.name;
4911 ccode->code = ereg.number;
4912 ccode->bits = 5;
4913 ccode->shift = 0;
4914 ccode->favail = 0; /* not used. */
4915 ccode++;
4916 memset (ccode, 0, sizeof (struct arc_flag_operand));
4917 break;
4918 default:
4919 as_bad (_("Unknown extension"));
4920 break;
4921 }
4922 create_extcore_section (&ereg, opertype);
4923}
4924
53a346d8
CZ		 4925/* Parse a .arc_attribute directive. */
4926
4927static void
4928arc_attribute (int ignored ATTRIBUTE_UNUSED)
4929{
4930 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4931
4932 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
5b7c81bd 4933 attributes_set_explicitly[tag] = true;
53a346d8
CZ		 4934}
4935
4936/* Set an attribute if it has not already been set by the user. */
4937
4938static void
4939arc_set_attribute_int (int tag, int value)
4940{
4941 if (tag < 1
4942 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4943 || !attributes_set_explicitly[tag])
4944 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4945}
4946
4947static void
4948arc_set_attribute_string (int tag, const char *value)
4949{
4950 if (tag < 1
4951 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4952 || !attributes_set_explicitly[tag])
4953 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4954}
4955
4956/* Allocate and concatenate two strings. s1 can be NULL but not
4957 s2. s1 pointer is freed at end of this procedure. */
4958
4959static char *
4960arc_stralloc (char * s1, const char * s2)
4961{
4962 char * p;
4963 int len = 0;
4964
4965 if (s1)
4966 len = strlen (s1) + 1;
4967
4968 /* Only s1 can be null. */
4969 gas_assert (s2);
4970 len += strlen (s2) + 1;
4971
4972 p = (char *) xmalloc (len);
53a346d8
CZ		 4973
4974 if (s1)
4975 {
4976 strcpy (p, s1);
4977 strcat (p, ",");
4978 strcat (p, s2);
4979 free (s1);
4980 }
4981 else
4982 strcpy (p, s2);
4983
4984 return p;
4985}
4986
4987/* Set the public ARC object attributes. */
4988
4989static void
4990arc_set_public_attributes (void)
4991{
4992 int base = 0;
4993 char *s = NULL;
4994 unsigned int i;
4995
4996 /* Tag_ARC_CPU_name. */
4997 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4998
4999 /* Tag_ARC_CPU_base. */
5000 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
5001 {
5002 case E_ARC_MACH_ARC600:
5003 case E_ARC_MACH_ARC601:
5004 base = TAG_CPU_ARC6xx;
5005 break;
5006 case E_ARC_MACH_ARC700:
5007 base = TAG_CPU_ARC7xx;
5008 break;
5009 case EF_ARC_CPU_ARCV2EM:
5010 base = TAG_CPU_ARCEM;
5011 break;
5012 case EF_ARC_CPU_ARCV2HS:
5013 base = TAG_CPU_ARCHS;
5014 break;
5015 default:
5016 base = 0;
5017 break;
5018 }
5019 if (attributes_set_explicitly[Tag_ARC_CPU_base]
5020 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5021 Tag_ARC_CPU_base)))
5022 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
5023 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
5024
5025 /* Tag_ARC_ABI_osver. */
5026 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
5027 {
5028 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5029 Tag_ARC_ABI_osver);
5030
5031 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
5032 | (val & 0x0f << 8));
5033 }
5034 else
5035 {
5036 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
5037 }
5038
5039 /* Tag_ARC_ISA_config. */
5040 arc_check_feature();
5041
5042 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
5043 if (selected_cpu.features & feature_list[i].feature)
5044 s = arc_stralloc (s, feature_list[i].attr);
5045
5046 if (s)
5047 arc_set_attribute_string (Tag_ARC_ISA_config, s);
5048
5049 /* Tag_ARC_ISA_mpy_option. */
5050 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
5051
5052 /* Tag_ARC_ABI_pic. */
5053 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
5054
5055 /* Tag_ARC_ABI_sda. */
5056 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
5057
5058 /* Tag_ARC_ABI_tls. */
5059 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
db1e1b45 5060
5061 /* Tag_ARC_ATR_version. */
5062 arc_set_attribute_int (Tag_ARC_ATR_version, 1);
63741043 5063
5064 /* Tag_ARC_ABI_rf16. */
5065 if (attributes_set_explicitly[Tag_ARC_ABI_rf16]
5066 && bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5067 Tag_ARC_ABI_rf16)
5068 && !rf16_only)
5069 {
5070 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5071 "register file"));
5072 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0);
5073 }
53a346d8
CZ		 5074}
5075
5076/* Add the default contents for the .ARC.attributes section. */
5077
5078void
ed2917de 5079arc_md_finish (void)
53a346d8
CZ		 5080{
5081 arc_set_public_attributes ();
5082
5083 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5084 as_fatal (_("could not set architecture and machine"));
5085
5086 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5087}
5088
5089void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5090{
5091 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5092}
5093
5094int arc_convert_symbolic_attribute (const char *name)
5095{
5096 static const struct
5097 {
5098 const char * name;
5099 const int tag;
5100 }
5101 attribute_table[] =
5102 {
5103#define T(tag) {#tag, tag}
5104 T (Tag_ARC_PCS_config),
5105 T (Tag_ARC_CPU_base),
5106 T (Tag_ARC_CPU_variation),
5107 T (Tag_ARC_CPU_name),
5108 T (Tag_ARC_ABI_rf16),
5109 T (Tag_ARC_ABI_osver),
5110 T (Tag_ARC_ABI_sda),
5111 T (Tag_ARC_ABI_pic),
5112 T (Tag_ARC_ABI_tls),
5113 T (Tag_ARC_ABI_enumsize),
5114 T (Tag_ARC_ABI_exceptions),
5115 T (Tag_ARC_ABI_double_size),
5116 T (Tag_ARC_ISA_config),
5117 T (Tag_ARC_ISA_apex),
db1e1b45 5118 T (Tag_ARC_ISA_mpy_option),
5119 T (Tag_ARC_ATR_version)
53a346d8
CZ		 5120#undef T
5121 };
5122 unsigned int i;
5123
5124 if (name == NULL)
5125 return -1;
5126
5127 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5128 if (streq (name, attribute_table[i].name))
5129 return attribute_table[i].tag;
5130
5131 return -1;
5132}
5133
b99747ae
CZ		 5134/* Local variables:
5135 eval: (c-set-style "gnu")
5136 indent-tabs-mode: t
5137 End: */
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