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* configure.ac: Move comment to remove extra space in last argument
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
87975d2a 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5a49b8ac 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
3882b010 24#include "safe-ctype.h"
252b5132
RH		 25#include "obstack.h"
26#include "subsegs.h"
f27a3839 27#include "dwarf2dbg.h"
c04898f8 28#include "dw2gencfi.h"
252b5132
RH		 29
30#include "opcode/m68k.h"
31#include "m68k-parse.h"
32
0d96863f
CM		 33#if defined (OBJ_ELF)
34#include "elf/m68k.h"
35#endif
36
31302357
AS		 37#ifdef M68KCOFF
38#include "obj-coff.h"
39#endif
40
cf869cce
NC		 41#ifdef OBJ_ELF
42static void m68k_elf_cons (int);
43#endif
44
252b5132
RH		 45/* This string holds the chars that always start a comment. If the
46 pre-processor is disabled, these aren't very useful. The macro
47 tc_comment_chars points to this. We use this, rather than the
48 usual comment_chars, so that the --bitwise-or option will work. */
49#if defined (TE_SVR4) || defined (TE_DELTA)
50const char *m68k_comment_chars = "|#";
51#else
52const char *m68k_comment_chars = "|";
53#endif
54
55/* This array holds the chars that only start a comment at the beginning of
56 a line. If the line seems to have the form '# 123 filename'
57 .line and .file directives will appear in the pre-processed output */
58/* Note that input_file.c hand checks for '#' at the beginning of the
59 first line of the input file. This is because the compiler outputs
92774660
KH		 60 #NO_APP at the beginning of its output. */
61/* Also note that comments like this one will always work. */
252b5132
RH		 62const char line_comment_chars[] = "#*";
63
63a0b638 64const char line_separator_chars[] = ";";
252b5132 65
36759679 66/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 67const char EXP_CHARS[] = "eE";
252b5132
RH		 68
69/* Chars that mean this number is a floating point constant, as
70 in "0f12.456" or "0d1.2345e12". */
71
5a38dc70 72const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 73
74/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
75 changed in read.c . Ideally it shouldn't have to know about it at all,
76 but nothing is ideal around here. */
77
252b5132
RH		 78/* Are we trying to generate PIC code? If so, absolute references
79 ought to be made into linkage table references or pc-relative
92774660 80 references. Not implemented. For ELF there are other means
252b5132
RH		 81 to denote pic relocations. */
82int flag_want_pic;
83
36759679
NC		 84static int flag_short_refs; /* -l option. */
85static int flag_long_jumps; /* -S option. */
28e7409f 86static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 87
88#ifdef REGISTER_PREFIX_OPTIONAL
89int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
90#else
91int flag_reg_prefix_optional;
92#endif
93
94/* Whether --register-prefix-optional was used on the command line. */
95static int reg_prefix_optional_seen;
96
97/* The floating point coprocessor to use by default. */
98static enum m68k_register m68k_float_copnum = COP1;
99
100/* If this is non-zero, then references to number(%pc) will be taken
101 to refer to number, rather than to %pc + number. */
102static int m68k_abspcadd;
103
104/* If this is non-zero, then the quick forms of the move, add, and sub
105 instructions are used when possible. */
106static int m68k_quick = 1;
107
108/* If this is non-zero, then if the size is not specified for a base
109 or outer displacement, the assembler assumes that the size should
110 be 32 bits. */
111static int m68k_rel32 = 1;
112
113/* This is non-zero if m68k_rel32 was set from the command line. */
114static int m68k_rel32_from_cmdline;
115
116/* The default width to use for an index register when using a base
117 displacement. */
118static enum m68k_size m68k_index_width_default = SIZE_LONG;
119
120/* We want to warn if any text labels are misaligned. In order to get
121 the right line number, we need to record the line number for each
122 label. */
252b5132
RH		 123struct label_line
124{
125 struct label_line *next;
126 symbolS *label;
127 char *file;
128 unsigned int line;
129 int text;
130};
131
132/* The list of labels. */
133
134static struct label_line *labels;
135
136/* The current label. */
137
138static struct label_line *current_label;
139
60fed2d3
NC		 140/* Pointer to list holding the opcodes sorted by name. */
141static struct m68k_opcode const ** m68k_sorted_opcodes;
142
36759679
NC		 143/* Its an arbitrary name: This means I don't approve of it.
144 See flames below. */
252b5132
RH		 145static struct obstack robyn;
146
252b5132
RH		 147struct m68k_incant
148 {
149 const char *m_operands;
150 unsigned long m_opcode;
151 short m_opnum;
152 short m_codenum;
153 int m_arch;
154 struct m68k_incant *m_next;
155 };
156
157#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
158#define gettwo(x) (((x)->m_opcode)&0xffff)
159
2da12c60
NS		 160static const enum m68k_register m68000_ctrl[] = { 0 };
161static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 162 SFC, DFC, USP, VBR,
163 0
164};
2da12c60 165static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 166 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
167 0
168};
2da12c60 169static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
171 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
172 0
173};
2da12c60 174static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 175 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
176 USP, VBR, URP, SRP, PCR,
177 0
178};
2da12c60 179static const enum m68k_register mcf_ctrl[] = {
3e602632 180 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 181 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
182 0
183};
87298967
NS		 184static const enum m68k_register mcf51_ctrl[] = {
185 VBR, CPUCR,
f75192f2
KH		 186 0
187};
78336706 188static const enum m68k_register mcf5206_ctrl[] = {
0d999f33 189 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 190 0
191};
2da12c60 192static const enum m68k_register mcf5208_ctrl[] = {
78336706 193 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 194 0
195};
96e0bbcc 196static const enum m68k_register mcf5210a_ctrl[] = {
78336706 197 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 198 0
199};
2da12c60 200static const enum m68k_register mcf5213_ctrl[] = {
78336706 201 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 202 0
203};
2da12c60 204static const enum m68k_register mcf5216_ctrl[] = {
78336706 205 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 206 0
207};
46203761
MK		 208static const enum m68k_register mcf5221x_ctrl[] = {
209 VBR, FLASHBAR, RAMBAR, RAMBAR1,
210 0
211};
d5be9593 212static const enum m68k_register mcf52223_ctrl[] = {
0d999f33 213 VBR, FLASHBAR, RAMBAR, RAMBAR1,
d5be9593
NS		 214 0
215};
96e0bbcc 216static const enum m68k_register mcf52235_ctrl[] = {
b345c8c2 217 VBR, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 218 0
219};
220static const enum m68k_register mcf5225_ctrl[] = {
78336706 221 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 222 0
223};
87298967
NS		 224static const enum m68k_register mcf52259_ctrl[] = {
225 VBR, FLASHBAR, RAMBAR, RAMBAR1,
226 0
227};
228static const enum m68k_register mcf52277_ctrl[] = {
229 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
230 0
231};
2da12c60 232static const enum m68k_register mcf5235_ctrl[] = {
78336706 233 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 234 0
235};
2da12c60 236static const enum m68k_register mcf5249_ctrl[] = {
78336706 237 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 238 0
239};
2da12c60
NS		 240static const enum m68k_register mcf5250_ctrl[] = {
241 VBR,
242 0
243};
d5be9593 244static const enum m68k_register mcf5253_ctrl[] = {
def8fc92 245 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
d5be9593
NS		 246 0
247};
2da12c60 248static const enum m68k_register mcf5271_ctrl[] = {
78336706 249 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 250 0
251};
252static const enum m68k_register mcf5272_ctrl[] = {
78336706 253 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 254 0
255};
256static const enum m68k_register mcf5275_ctrl[] = {
78336706 257 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 258 0
259};
260static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 261 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
262 0
263};
87298967 264static const enum m68k_register mcf53017_ctrl[] = {
b345c8c2 265 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
87298967
NS		 266 0
267};
78336706 268static const enum m68k_register mcf5307_ctrl[] = {
87298967 269 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 270 0
271};
272static const enum m68k_register mcf5329_ctrl[] = {
78336706 273 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 274 0
275};
276static const enum m68k_register mcf5373_ctrl[] = {
78336706 277 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 278 0
279};
280static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
283 MBAR, SECMBAR,
284 MPCR /* Multiprocessor Control register */,
285 EDRAMBAR /* Embedded DRAM Base Address Register */,
286 /* Permutation control registers. */
3e602632
NC		 287 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
288 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 289 /* Legacy names */
290 TC /* ASID */, BUSCR /* MMUBAR */,
291 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
292 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 293 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 294 0
295};
def8fc92
KH		 296static const enum m68k_register mcf5407_ctrl[] = {
297 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
298 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
299 /* Legacy names */
300 TC /* ASID */,
301 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
302 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
303 0
304};
0d999f33
MK		 305static const enum m68k_register mcf54418_ctrl[] = {
306 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
307 VBR, PC, RAMBAR1,
308 /* Legacy names */
309 TC /* ASID */, BUSCR /* MMUBAR */,
310 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
311 RAMBAR /* RAMBAR1 */,
312 0
313};
9a2e615a
NS		 314static const enum m68k_register mcf54455_ctrl[] = {
315 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
0d999f33 316 VBR, PC, RAMBAR1,
9a2e615a
NS		 317 /* Legacy names */
318 TC /* ASID */, BUSCR /* MMUBAR */,
319 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
0d999f33 320 RAMBAR /* RAMBAR1 */,
9a2e615a
NS		 321 0
322};
a8e24a56
NS		 323static const enum m68k_register mcf5475_ctrl[] = {
324 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
325 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
326 /* Legacy names */
327 TC /* ASID */, BUSCR /* MMUBAR */,
328 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 329 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 330 0
331};
332static const enum m68k_register mcf5485_ctrl[] = {
333 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
334 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
335 /* Legacy names */
336 TC /* ASID */, BUSCR /* MMUBAR */,
337 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 338 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 339 0
340};
f7ec513b 341static const enum m68k_register fido_ctrl[] = {
d0fa1372 342 SFC, DFC, USP, VBR, CAC, MBO,
f7ec513b
KH		 343 0
344};
2da12c60 345#define cpu32_ctrl m68010_ctrl
252b5132
RH		 346
347static const enum m68k_register *control_regs;
348
36759679 349/* Internal form of a 68020 instruction. */
252b5132
RH		 350struct m68k_it
351{
352 const char *error;
36759679 353 const char *args; /* List of opcode info. */
252b5132
RH		 354 int numargs;
355
36759679 356 int numo; /* Number of shorts in opcode. */
252b5132
RH		 357 short opcode[11];
358
359 struct m68k_op operands[6];
360
36759679 361 int nexp; /* Number of exprs in use. */
252b5132
RH		 362 struct m68k_exp exprs[4];
363
36759679 364 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 365 struct
366 {
36759679 367 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 368 symbolS *fadd;
369 offsetT foff;
370 int fragty;
371 }
372 fragb[4];
373
36759679 374 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 375 struct
376 {
377 int n;
378 expressionS exp;
379 char wid;
380 char pcrel;
381 /* In a pc relative address the difference between the address
382 of the offset and the address that the offset is relative
383 to. This depends on the addressing mode. Basically this
384 is the value to put in the offset field to address the
385 first byte of the offset, without regarding the special
386 significance of some values (in the branch instruction, for
387 example). */
388 int pcrel_fix;
389#ifdef OBJ_ELF
390 /* Whether this expression needs special pic relocation, and if
391 so, which. */
392 enum pic_relocation pic_reloc;
393#endif
394 }
36759679 395 reloc[5]; /* Five is enough??? */
252b5132
RH		 396};
397
9840d27e 398#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 399#define float_of_arch(x) ((x) & mfloat)
400#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 401#define arch_coldfire_p(x) ((x) & mcfisa_a)
402#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 403
36759679 404/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 405#define HAVE_LONG_DISP(x) \
406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
407#define HAVE_LONG_CALL(x) \
408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
409#define HAVE_LONG_COND(x) \
410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
411#define HAVE_LONG_BRANCH(x) \
412 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
cac27205 413#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
252b5132 414
36759679 415static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 416
417#define op(ex) ((ex)->exp.X_op)
418#define adds(ex) ((ex)->exp.X_add_symbol)
419#define subs(ex) ((ex)->exp.X_op_symbol)
420#define offs(ex) ((ex)->exp.X_add_number)
421
36759679 422/* Macros for adding things to the m68k_it struct. */
31302357 423#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 424
36759679
NC		 425/* Like addword, but goes BEFORE general operands. */
426
252b5132 427static void
31302357 428insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 429{
430 int z;
07726851 431 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 432 the_ins.opcode[z] = the_ins.opcode[z - 1];
433 for (z = 0; z < the_ins.nrel; z++)
434 the_ins.reloc[z].n += 2;
252b5132
RH		 435 for (z = 0; z < the_ins.nfrag; z++)
436 the_ins.fragb[z].fragoff++;
8a104df9 437 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 438 the_ins.numo++;
439}
440
441/* The numo+1 kludge is so we can hit the low order byte of the prev word.
442 Blecch. */
443static void
31302357 444add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 445{
31302357
AS		 446 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
447 ? the_ins.numo * 2 - 1
448 : (width == 'b'
449 ? the_ins.numo * 2 + 1
450 : the_ins.numo * 2));
252b5132
RH		 451 the_ins.reloc[the_ins.nrel].exp = exp->exp;
452 the_ins.reloc[the_ins.nrel].wid = width;
453 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
454#ifdef OBJ_ELF
455 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
456#endif
457 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
458}
459
460/* Cause an extra frag to be generated here, inserting up to 10 bytes
461 (that value is chosen in the frag_var call in md_assemble). TYPE
462 is the subtype of the frag to be generated; its primary type is
463 rs_machine_dependent.
464
465 The TYPE parameter is also used by md_convert_frag_1 and
466 md_estimate_size_before_relax. The appropriate type of fixup will
467 be emitted by md_convert_frag_1.
468
469 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
470static void
31302357 471add_frag (symbolS *add, offsetT off, int type)
252b5132 472{
8a104df9
KH		 473 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
474 the_ins.fragb[the_ins.nfrag].fadd = add;
475 the_ins.fragb[the_ins.nfrag].foff = off;
476 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 477}
478
479#define isvar(ex) \
480 (op (ex) != O_constant && op (ex) != O_big)
481
31302357
AS		 482static char *crack_operand (char *str, struct m68k_op *opP);
483static int get_num (struct m68k_exp *exp, int ok);
484static int reverse_16_bits (int in);
485static int reverse_8_bits (int in);
486static void install_gen_operand (int mode, int val);
487static void install_operand (int mode, int val);
488static void s_bss (int);
489static void s_data1 (int);
490static void s_data2 (int);
491static void s_even (int);
492static void s_proc (int);
493static void s_chip (int);
494static void s_fopt (int);
495static void s_opt (int);
496static void s_reg (int);
497static void s_restore (int);
498static void s_save (int);
499static void s_mri_if (int);
500static void s_mri_else (int);
501static void s_mri_endi (int);
502static void s_mri_break (int);
503static void s_mri_next (int);
504static void s_mri_for (int);
505static void s_mri_endf (int);
506static void s_mri_repeat (int);
507static void s_mri_until (int);
508static void s_mri_while (int);
509static void s_mri_endw (int);
266abb8f
NS		 510static void s_m68k_cpu (int);
511static void s_m68k_arch (int);
512
513struct m68k_cpu
514{
515 unsigned long arch; /* Architecture features. */
2da12c60 516 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 517 const char *name; /* Name */
0b2e31dc
NS		 518 int alias; /* Alias for a cannonical name. If 1, then
519 succeeds canonical name, if -1 then
520 succeeds canonical name, if <-1 ||>1 this is a
521 deprecated name, and the next/previous name
522 should be used. */
266abb8f 523};
252b5132 524
266abb8f
NS		 525/* We hold flags for features explicitly enabled and explicitly
526 disabled. */
252b5132 527static int current_architecture;
266abb8f 528static int not_current_architecture;
266abb8f
NS		 529static const struct m68k_cpu *selected_arch;
530static const struct m68k_cpu *selected_cpu;
531static int initialized;
252b5132 532
266abb8f
NS		 533/* Architecture models. */
534static const struct m68k_cpu m68k_archs[] =
535{
2da12c60
NS		 536 {m68000, m68000_ctrl, "68000", 0},
537 {m68010, m68010_ctrl, "68010", 0},
538 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
539 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
540 {m68040, m68040_ctrl, "68040", 0},
541 {m68060, m68060_ctrl, "68060", 0},
542 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 543 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 544 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
545 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
546 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 547 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 548 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
549 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 550 {0,0,NULL, 0}
551};
252b5132 552
87298967
NS		 553/* For -mno-mac we want to turn off all types of mac. */
554static const unsigned no_mac = mcfmac | mcfemac;
555
0b2e31dc
NS		 556/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
557 for either. */
266abb8f
NS		 558static const struct m68k_cpu m68k_extensions[] =
559{
2da12c60
NS		 560 {m68851, NULL, "68851", -1},
561 {m68881, NULL, "68881", -1},
562 {m68881, NULL, "68882", -1},
cf869cce 563
2da12c60 564 {cfloat|m68881, NULL, "float", 0},
cf869cce 565
2da12c60
NS		 566 {mcfhwdiv, NULL, "div", 1},
567 {mcfusp, NULL, "usp", 1},
87298967 568 {mcfmac, (void *)&no_mac, "mac", 1},
2da12c60 569 {mcfemac, NULL, "emac", 1},
cf869cce 570
2da12c60 571 {0,NULL,NULL, 0}
266abb8f
NS		 572};
573
574/* Processor list */
575static const struct m68k_cpu m68k_cpus[] =
576{
2da12c60
NS		 577 {m68000, m68000_ctrl, "68000", 0},
578 {m68000, m68000_ctrl, "68ec000", 1},
579 {m68000, m68000_ctrl, "68hc000", 1},
580 {m68000, m68000_ctrl, "68hc001", 1},
581 {m68000, m68000_ctrl, "68008", 1},
582 {m68000, m68000_ctrl, "68302", 1},
583 {m68000, m68000_ctrl, "68306", 1},
584 {m68000, m68000_ctrl, "68307", 1},
585 {m68000, m68000_ctrl, "68322", 1},
586 {m68000, m68000_ctrl, "68356", 1},
587 {m68010, m68010_ctrl, "68010", 0},
588 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
589 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
590 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
591 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
592 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
593 {m68040, m68040_ctrl, "68040", 0},
594 {m68040, m68040_ctrl, "68ec040", 1},
595 {m68060, m68060_ctrl, "68060", 0},
596 {m68060, m68060_ctrl, "68ec060", 1},
cf869cce 597
2da12c60
NS		 598 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
599 {cpu32|m68881, cpu32_ctrl, "68330", 1},
600 {cpu32|m68881, cpu32_ctrl, "68331", 1},
601 {cpu32|m68881, cpu32_ctrl, "68332", 1},
602 {cpu32|m68881, cpu32_ctrl, "68333", 1},
603 {cpu32|m68881, cpu32_ctrl, "68334", 1},
604 {cpu32|m68881, cpu32_ctrl, "68336", 1},
605 {cpu32|m68881, cpu32_ctrl, "68340", 1},
606 {cpu32|m68881, cpu32_ctrl, "68341", 1},
607 {cpu32|m68881, cpu32_ctrl, "68349", 1},
608 {cpu32|m68881, cpu32_ctrl, "68360", 1},
f75192f2 609
87298967
NS		 610 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
611 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
612 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
613 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
614 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
615 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
cf869cce 616
2da12c60
NS		 617 {mcfisa_a, mcf_ctrl, "5200", 0},
618 {mcfisa_a, mcf_ctrl, "5202", 1},
619 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 620 {mcfisa_a, mcf5206_ctrl, "5206", 1},
cf869cce 621
78336706 622 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
cf869cce 623
2da12c60
NS		 624 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
cf869cce 626
96e0bbcc
NS		 627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
cf869cce 629
2da12c60
NS		 630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
cf869cce 633
2da12c60
NS		 634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
637
46203761
MK		 638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
639
d5be9593
NS		 640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
642
96e0bbcc
NS		 643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
cf869cce 647
96e0bbcc
NS		 648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
cf869cce 650
87298967
NS		 651 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
653
2da12c60
NS		 654 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
659
660 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
661 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 662 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
87298967
NS		 663
664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
665 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
666 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
667 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
670
2da12c60
NS		 671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
673
674 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
675
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
678
679 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
682 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
683
87298967
NS		 684 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
689 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
691
78336706 692 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
2da12c60
NS		 693
694 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
695 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
696 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
697 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
698
699 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
700 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
701 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
702
def8fc92 703 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
9a2e615a 704
0d999f33
MK		 705 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
706 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
707 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
708 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
709 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
710
9a2e615a
NS		 711 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
712 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
713 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
714 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
715 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
716 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
2da12c60 717
a8e24a56
NS		 718 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
719 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
720 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
721 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
2da12c60 725
a8e24a56
NS		 726 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
727 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
728 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
729 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
730 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
731 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
732 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
2da12c60 733
b3768379 734 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 735 {fido_a, fido_ctrl, "fido", 1},
9840d27e 736
2da12c60 737 {0,NULL,NULL, 0}
dc84e067 738 };
252b5132 739
266abb8f
NS		 740static const struct m68k_cpu *m68k_lookup_cpu
741(const char *, const struct m68k_cpu *, int, int *);
742static int m68k_set_arch (const char *, int, int);
743static int m68k_set_cpu (const char *, int, int);
744static int m68k_set_extension (const char *, int, int);
745static void m68k_init_arch (void);
252b5132 746
151337e8
NC		 747/* This is the assembler relaxation table for m68k. m68k is a rich CISC
748 architecture and we have a lot of relaxation modes. */
252b5132 749
151337e8
NC		 750/* Macros used in the relaxation code. */
751#define TAB(x,y) (((x) << 2) + (y))
752#define TABTYPE(x) ((x) >> 2)
753
754/* Relaxation states. */
755#define BYTE 0
756#define SHORT 1
757#define LONG 2
758#define SZ_UNDEF 3
759
760/* Here are all the relaxation modes we support. First we can relax ordinary
761 branches. On 68020 and higher and on CPU32 all branch instructions take
762 three forms, so on these CPUs all branches always remain as such. When we
763 have to expand to the LONG form on a 68000, though, we substitute an
764 absolute jump instead. This is a direct replacement for unconditional
765 branches and a branch over a jump for conditional branches. However, if the
766 user requires PIC and disables this with --pcrel, we can only relax between
767 BYTE and SHORT forms, punting if that isn't enough. This gives us four
768 different relaxation modes for branches: */
769
36759679
NC		 770#define BRANCHBWL 0 /* Branch byte, word, or long. */
771#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
772#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
773#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 774
775/* We also relax coprocessor branches and DBcc's. All CPUs that support
776 coprocessor branches support them in word and long forms, so we have only
777 one relaxation mode for them. DBcc's are word only on all CPUs. We can
778 relax them to the LONG form with a branch-around sequence. This sequence
779 can use a long branch (if available) or an absolute jump (if acceptable).
780 This gives us two relaxation modes. If long branches are not available and
781 absolute jumps are not acceptable, we don't relax DBcc's. */
782
36759679
NC		 783#define FBRANCH 4 /* Coprocessor branch. */
784#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
785#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 786
787/* That's all for instruction relaxation. However, we also relax PC-relative
788 operands. Specifically, we have three operand relaxation modes. On the
789 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
790 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
791 two. Also PC+displacement+index operands in their simple form (with a non-
792 suppressed index without memory indirection) are supported on all CPUs, but
793 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
794 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
795 form of the PC+displacement+index operand. Finally, some absolute operands
796 can be relaxed down to 16-bit PC-relative. */
797
36759679
NC		 798#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
799#define PCINDEX 8 /* PC + displacement + index. */
800#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132 801
cac27205
NC		 802/* This relaxation is required for branches where there is no long
803 branch and we are in pcrel mode. We generate a bne/beq pair. */
804#define BRANCHBWPL 10 /* Branch byte, word or pair of longs
805 */
806
252b5132 807/* Note that calls to frag_var need to specify the maximum expansion
cac27205
NC		 808 needed; this is currently 12 bytes for bne/beq pair. */
809#define FRAG_VAR_SIZE 12
252b5132
RH		 810
811/* The fields are:
812 How far Forward this mode will reach:
813 How far Backward this mode will reach:
814 How many bytes this mode will add to the size of the frag
815 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 816
817 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 818relax_typeS md_relax_table[] =
819{
ac62c346
AM		 820 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
821 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
822 { 0, 0, 4, 0 },
823 { 1, 1, 0, 0 },
824
825 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
826 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
827 { 0, 0, 4, 0 },
828 { 1, 1, 0, 0 },
829
830 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
831 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
832 { 0, 0, 6, 0 },
833 { 1, 1, 0, 0 },
834
835 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
836 { 0, 0, 2, 0 },
837 { 1, 1, 0, 0 },
838 { 1, 1, 0, 0 },
839
36759679 840 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 841 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
842 { 0, 0, 4, 0 },
843 { 1, 1, 0, 0 },
844
36759679 845 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 846 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
847 { 0, 0, 10, 0 },
848 { 1, 1, 0, 0 },
849
36759679 850 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 851 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
852 { 0, 0, 10, 0 },
853 { 1, 1, 0, 0 },
854
36759679 855 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 856 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
857 { 0, 0, 6, 0 },
858 { 1, 1, 0, 0 },
859
860 { 125, -130, 0, TAB (PCINDEX, SHORT) },
861 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
862 { 0, 0, 4, 0 },
863 { 1, 1, 0, 0 },
864
36759679 865 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 866 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
867 { 0, 0, 4, 0 },
868 { 1, 1, 0, 0 },
cac27205
NC		 869
870 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
871 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
872 { 0, 0, 10, 0 },
873 { 1, 1, 0, 0 },
252b5132
RH		 874};
875
876/* These are the machine dependent pseudo-ops. These are included so
877 the assembler can work on the output from the SUN C compiler, which
36759679 878 generates these. */
252b5132
RH		 879
880/* This table describes all the machine specific pseudo-ops the assembler
881 has to support. The fields are:
882 pseudo-op name without dot
883 function to call to execute this pseudo-op
36759679 884 Integer arg to pass to the function. */
252b5132
RH		 885const pseudo_typeS md_pseudo_table[] =
886{
887 {"data1", s_data1, 0},
888 {"data2", s_data2, 0},
889 {"bss", s_bss, 0},
890 {"even", s_even, 0},
891 {"skip", s_space, 0},
892 {"proc", s_proc, 0},
893#if defined (TE_SUN3) || defined (OBJ_ELF)
894 {"align", s_align_bytes, 0},
895#endif
896#ifdef OBJ_ELF
897 {"swbeg", s_ignore, 0},
cf869cce 898 {"long", m68k_elf_cons, 4},
252b5132
RH		 899#endif
900 {"extend", float_cons, 'x'},
901 {"ldouble", float_cons, 'x'},
902
266abb8f
NS		 903 {"arch", s_m68k_arch, 0},
904 {"cpu", s_m68k_cpu, 0},
905
252b5132
RH		 906 /* The following pseudo-ops are supported for MRI compatibility. */
907 {"chip", s_chip, 0},
908 {"comline", s_space, 1},
909 {"fopt", s_fopt, 0},
910 {"mask2", s_ignore, 0},
911 {"opt", s_opt, 0},
912 {"reg", s_reg, 0},
913 {"restore", s_restore, 0},
914 {"save", s_save, 0},
915
916 {"if", s_mri_if, 0},
917 {"if.b", s_mri_if, 'b'},
918 {"if.w", s_mri_if, 'w'},
919 {"if.l", s_mri_if, 'l'},
920 {"else", s_mri_else, 0},
921 {"else.s", s_mri_else, 's'},
922 {"else.l", s_mri_else, 'l'},
923 {"endi", s_mri_endi, 0},
924 {"break", s_mri_break, 0},
925 {"break.s", s_mri_break, 's'},
926 {"break.l", s_mri_break, 'l'},
927 {"next", s_mri_next, 0},
928 {"next.s", s_mri_next, 's'},
929 {"next.l", s_mri_next, 'l'},
930 {"for", s_mri_for, 0},
931 {"for.b", s_mri_for, 'b'},
932 {"for.w", s_mri_for, 'w'},
933 {"for.l", s_mri_for, 'l'},
934 {"endf", s_mri_endf, 0},
935 {"repeat", s_mri_repeat, 0},
936 {"until", s_mri_until, 0},
937 {"until.b", s_mri_until, 'b'},
938 {"until.w", s_mri_until, 'w'},
939 {"until.l", s_mri_until, 'l'},
940 {"while", s_mri_while, 0},
941 {"while.b", s_mri_while, 'b'},
942 {"while.w", s_mri_while, 'w'},
943 {"while.l", s_mri_while, 'l'},
944 {"endw", s_mri_endw, 0},
945
946 {0, 0, 0}
947};
948
252b5132 949/* The mote pseudo ops are put into the opcode table, since they
31302357 950 don't start with a . they look like opcodes to gas. */
252b5132 951
5a38dc70 952const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 953{
954
955 {"dcl", cons, 4},
956 {"dc", cons, 2},
957 {"dcw", cons, 2},
958 {"dcb", cons, 1},
959
960 {"dsl", s_space, 4},
961 {"ds", s_space, 2},
962 {"dsw", s_space, 2},
963 {"dsb", s_space, 1},
964
965 {"xdef", s_globl, 0},
966#ifdef OBJ_ELF
967 {"align", s_align_bytes, 0},
968#else
969 {"align", s_align_ptwo, 0},
970#endif
971#ifdef M68KCOFF
972 {"sect", obj_coff_section, 0},
973 {"section", obj_coff_section, 0},
974#endif
975 {0, 0, 0}
976};
977
bd17c2c3
AM		 978/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
979 gives identical results to a 32-bit host. */
980#define TRUNC(X) ((valueT) (X) & 0xffffffff)
981#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
982
983#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
984#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
985#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
986#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
987
988#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
989#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 990#define islong(x) (1)
991
252b5132
RH		 992static char notend_table[256];
993static char alt_notend_table[256];
994#define notend(s) \
995 (! (notend_table[(unsigned char) *s] \
996 || (*s == ':' \
997 && alt_notend_table[(unsigned char) s[1]])))
998
252b5132
RH		 999#ifdef OBJ_ELF
1000
c801568a
AM		 1001/* Return zero if the reference to SYMBOL from within the same segment may
1002 be relaxed. */
1003
1004/* On an ELF system, we can't relax an externally visible symbol,
1005 because it may be overridden by a shared library. However, if
1006 TARGET_OS is "elf", then we presume that we are assembling for an
1007 embedded system, in which case we don't have to worry about shared
1008 libraries, and we can relax any external sym. */
1009
1010#define relaxable_symbol(symbol) \
6358301e 1011 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 1012 || S_IS_WEAK (symbol)))
1013
252b5132
RH		 1014/* Compute the relocation code for a fixup of SIZE bytes, using pc
1015 relative relocation if PCREL is non-zero. PIC says whether a special
1016 pic relocation was requested. */
1017
252b5132 1018static bfd_reloc_code_real_type
31302357 1019get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 1020{
1021 switch (pic)
1022 {
1023 case pic_got_pcrel:
1024 switch (size)
1025 {
1026 case 1:
1027 return BFD_RELOC_8_GOT_PCREL;
1028 case 2:
1029 return BFD_RELOC_16_GOT_PCREL;
1030 case 4:
1031 return BFD_RELOC_32_GOT_PCREL;
1032 }
1033 break;
1034
1035 case pic_got_off:
1036 switch (size)
1037 {
1038 case 1:
1039 return BFD_RELOC_8_GOTOFF;
1040 case 2:
1041 return BFD_RELOC_16_GOTOFF;
1042 case 4:
1043 return BFD_RELOC_32_GOTOFF;
1044 }
1045 break;
1046
1047 case pic_plt_pcrel:
1048 switch (size)
1049 {
1050 case 1:
1051 return BFD_RELOC_8_PLT_PCREL;
1052 case 2:
1053 return BFD_RELOC_16_PLT_PCREL;
1054 case 4:
1055 return BFD_RELOC_32_PLT_PCREL;
1056 }
1057 break;
1058
1059 case pic_plt_off:
1060 switch (size)
1061 {
1062 case 1:
1063 return BFD_RELOC_8_PLTOFF;
1064 case 2:
1065 return BFD_RELOC_16_PLTOFF;
1066 case 4:
1067 return BFD_RELOC_32_PLTOFF;
1068 }
1069 break;
1070
cf869cce
NC		 1071 case pic_tls_gd:
1072 switch (size)
1073 {
1074 case 1:
1075 return BFD_RELOC_68K_TLS_GD8;
1076 case 2:
1077 return BFD_RELOC_68K_TLS_GD16;
1078 case 4:
1079 return BFD_RELOC_68K_TLS_GD32;
1080 }
1081 break;
1082
1083 case pic_tls_ldm:
1084 switch (size)
1085 {
1086 case 1:
1087 return BFD_RELOC_68K_TLS_LDM8;
1088 case 2:
1089 return BFD_RELOC_68K_TLS_LDM16;
1090 case 4:
1091 return BFD_RELOC_68K_TLS_LDM32;
1092 }
1093 break;
1094
1095 case pic_tls_ldo:
1096 switch (size)
1097 {
1098 case 1:
1099 return BFD_RELOC_68K_TLS_LDO8;
1100 case 2:
1101 return BFD_RELOC_68K_TLS_LDO16;
1102 case 4:
1103 return BFD_RELOC_68K_TLS_LDO32;
1104 }
1105 break;
1106
1107 case pic_tls_ie:
1108 switch (size)
1109 {
1110 case 1:
1111 return BFD_RELOC_68K_TLS_IE8;
1112 case 2:
1113 return BFD_RELOC_68K_TLS_IE16;
1114 case 4:
1115 return BFD_RELOC_68K_TLS_IE32;
1116 }
1117 break;
1118
1119 case pic_tls_le:
1120 switch (size)
1121 {
1122 case 1:
1123 return BFD_RELOC_68K_TLS_LE8;
1124 case 2:
1125 return BFD_RELOC_68K_TLS_LE16;
1126 case 4:
1127 return BFD_RELOC_68K_TLS_LE32;
1128 }
1129 break;
1130
252b5132
RH		 1131 case pic_none:
1132 if (pcrel)
1133 {
1134 switch (size)
1135 {
1136 case 1:
1137 return BFD_RELOC_8_PCREL;
1138 case 2:
1139 return BFD_RELOC_16_PCREL;
1140 case 4:
1141 return BFD_RELOC_32_PCREL;
1142 }
1143 }
1144 else
1145 {
1146 switch (size)
1147 {
1148 case 1:
1149 return BFD_RELOC_8;
1150 case 2:
1151 return BFD_RELOC_16;
1152 case 4:
1153 return BFD_RELOC_32;
1154 }
1155 }
1156 }
1157
1158 if (pcrel)
1159 {
1160 if (pic == pic_none)
1161 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1162 else
1163 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1164 }
1165 else
1166 {
1167 if (pic == pic_none)
1168 as_bad (_("Can not do %d byte relocation"), size);
1169 else
1170 as_bad (_("Can not do %d byte pic relocation"), size);
1171 }
1172
1173 return BFD_RELOC_NONE;
1174}
1175
1176/* Here we decide which fixups can be adjusted to make them relative
1177 to the beginning of the section instead of the symbol. Basically
1178 we need to make sure that the dynamic relocations are done
1179 correctly, so in some cases we force the original symbol to be
1180 used. */
1181int
31302357 1182tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1183{
36759679 1184 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1185 switch (fixP->fx_r_type)
1186 {
1187 case BFD_RELOC_8_GOT_PCREL:
1188 case BFD_RELOC_16_GOT_PCREL:
1189 case BFD_RELOC_32_GOT_PCREL:
1190 case BFD_RELOC_8_GOTOFF:
1191 case BFD_RELOC_16_GOTOFF:
1192 case BFD_RELOC_32_GOTOFF:
1193 case BFD_RELOC_8_PLT_PCREL:
1194 case BFD_RELOC_16_PLT_PCREL:
1195 case BFD_RELOC_32_PLT_PCREL:
1196 case BFD_RELOC_8_PLTOFF:
1197 case BFD_RELOC_16_PLTOFF:
1198 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1199 case BFD_RELOC_68K_TLS_GD32:
1200 case BFD_RELOC_68K_TLS_GD16:
1201 case BFD_RELOC_68K_TLS_GD8:
1202 case BFD_RELOC_68K_TLS_LDM32:
1203 case BFD_RELOC_68K_TLS_LDM16:
1204 case BFD_RELOC_68K_TLS_LDM8:
1205 case BFD_RELOC_68K_TLS_LDO32:
1206 case BFD_RELOC_68K_TLS_LDO16:
1207 case BFD_RELOC_68K_TLS_LDO8:
1208 case BFD_RELOC_68K_TLS_IE32:
1209 case BFD_RELOC_68K_TLS_IE16:
1210 case BFD_RELOC_68K_TLS_IE8:
1211 case BFD_RELOC_68K_TLS_LE32:
1212 case BFD_RELOC_68K_TLS_LE16:
1213 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1214 return 0;
1215
1216 case BFD_RELOC_VTABLE_INHERIT:
1217 case BFD_RELOC_VTABLE_ENTRY:
1218 return 0;
1219
1220 default:
1221 return 1;
1222 }
1223}
1224
1225#else /* !OBJ_ELF */
1226
1227#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1228
22184a77
NC		 1229/* PR gas/3041 Weak symbols are not relaxable
1230 because they must be treated as extern. */
1231#define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
c801568a 1232
252b5132
RH		 1233#endif /* OBJ_ELF */
1234
252b5132 1235arelent *
31302357 1236tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1237{
1238 arelent *reloc;
1239 bfd_reloc_code_real_type code;
1240
8ec6253e
NC		 1241 /* If the tcbit is set, then this was a fixup of a negative value
1242 that was never resolved. We do not have a reloc to handle this,
1243 so just return. We assume that other code will have detected this
1244 situation and produced a helpful error message, so we just tell the
1245 user that the reloc cannot be produced. */
252b5132 1246 if (fixp->fx_tcbit)
8ec6253e
NC		 1247 {
1248 if (fixp->fx_addsy)
b091f402
AM		 1249 as_bad_where (fixp->fx_file, fixp->fx_line,
1250 _("Unable to produce reloc against symbol '%s'"),
1251 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1252 return NULL;
1253 }
252b5132
RH		 1254
1255 if (fixp->fx_r_type != BFD_RELOC_NONE)
1256 {
1257 code = fixp->fx_r_type;
1258
1259 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1260 that fixup_segment converted a non-PC relative reloc into a
1261 PC relative reloc. In such a case, we need to convert the
1262 reloc code. */
1263 if (fixp->fx_pcrel)
1264 {
1265 switch (code)
1266 {
1267 case BFD_RELOC_8:
1268 code = BFD_RELOC_8_PCREL;
1269 break;
1270 case BFD_RELOC_16:
1271 code = BFD_RELOC_16_PCREL;
1272 break;
1273 case BFD_RELOC_32:
1274 code = BFD_RELOC_32_PCREL;
1275 break;
1276 case BFD_RELOC_8_PCREL:
1277 case BFD_RELOC_16_PCREL:
1278 case BFD_RELOC_32_PCREL:
1279 case BFD_RELOC_8_GOT_PCREL:
1280 case BFD_RELOC_16_GOT_PCREL:
1281 case BFD_RELOC_32_GOT_PCREL:
1282 case BFD_RELOC_8_GOTOFF:
1283 case BFD_RELOC_16_GOTOFF:
1284 case BFD_RELOC_32_GOTOFF:
1285 case BFD_RELOC_8_PLT_PCREL:
1286 case BFD_RELOC_16_PLT_PCREL:
1287 case BFD_RELOC_32_PLT_PCREL:
1288 case BFD_RELOC_8_PLTOFF:
1289 case BFD_RELOC_16_PLTOFF:
1290 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1291 case BFD_RELOC_68K_TLS_GD32:
1292 case BFD_RELOC_68K_TLS_GD16:
1293 case BFD_RELOC_68K_TLS_GD8:
1294 case BFD_RELOC_68K_TLS_LDM32:
1295 case BFD_RELOC_68K_TLS_LDM16:
1296 case BFD_RELOC_68K_TLS_LDM8:
1297 case BFD_RELOC_68K_TLS_LDO32:
1298 case BFD_RELOC_68K_TLS_LDO16:
1299 case BFD_RELOC_68K_TLS_LDO8:
1300 case BFD_RELOC_68K_TLS_IE32:
1301 case BFD_RELOC_68K_TLS_IE16:
1302 case BFD_RELOC_68K_TLS_IE8:
1303 case BFD_RELOC_68K_TLS_LE32:
1304 case BFD_RELOC_68K_TLS_LE16:
1305 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1306 break;
1307 default:
1308 as_bad_where (fixp->fx_file, fixp->fx_line,
1309 _("Cannot make %s relocation PC relative"),
1310 bfd_get_reloc_code_name (code));
1311 }
1312 }
1313 }
1314 else
1315 {
1316#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1317 switch (F (fixp->fx_size, fixp->fx_pcrel))
1318 {
1319#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1320 MAP (1, 0, BFD_RELOC_8);
1321 MAP (2, 0, BFD_RELOC_16);
1322 MAP (4, 0, BFD_RELOC_32);
1323 MAP (1, 1, BFD_RELOC_8_PCREL);
1324 MAP (2, 1, BFD_RELOC_16_PCREL);
1325 MAP (4, 1, BFD_RELOC_32_PCREL);
1326 default:
1327 abort ();
1328 }
1329 }
1330#undef F
1331#undef MAP
1332
1333 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1334 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1335 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1336 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1337#ifndef OBJ_ELF
33f0727f
NC		 1338 if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1339 && fixp->fx_addsy
1340 && S_IS_WEAK (fixp->fx_addsy)
1341 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
b2b74248
NC		 1342 {
1343 /* PR gas/3041 References to weak symbols must be treated as extern
1344 in order to be overridable by the linker, even if they are defined
1345 in the same object file. So the original addend must be written
1346 "as is" into the output section without further processing.
1347 The addend value must be hacked here in order to force
1348 bfd_install_relocation() to write the original value into the
1349 output section.
1350 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol
1351 value has already been added to the addend in fixup_segment(). We
1352 have to remove it.
1353 2) bfd_install_relocation() will incorrectly treat this symbol as
1354 resolved, so it will write the symbol value plus its addend and
1355 section VMA. As a workaround we can tweak the addend value here in
1356 order to get the original value in the section after the call to
1357 bfd_install_relocation(). */
1358 reloc->addend = fixp->fx_addnumber
1359 /* Fix because of MD_APPLY_SYM_VALUE() */
1360 - S_GET_VALUE (fixp->fx_addsy)
1361 /* Fix for bfd_install_relocation() */
1362 - (S_GET_VALUE (fixp->fx_addsy)
1363 + S_GET_SEGMENT (fixp->fx_addsy)->vma);
1364 }
33f0727f
NC		 1365 else if (fixp->fx_pcrel)
1366 reloc->addend = fixp->fx_addnumber;
252b5132
RH		 1367 else
1368 reloc->addend = 0;
1369#else
1370 if (!fixp->fx_pcrel)
1371 reloc->addend = fixp->fx_addnumber;
1372 else
1373 reloc->addend = (section->vma
8390138c
AS		 1374 /* Explicit sign extension in case char is
1375 unsigned. */
1376 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1377 + fixp->fx_addnumber
1378 + md_pcrel_from (fixp));
1379#endif
1380
1381 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
9c2799c2 1382 gas_assert (reloc->howto != 0);
252b5132
RH		 1383
1384 return reloc;
1385}
1386
252b5132
RH		 1387/* Handle of the OPCODE hash table. NULL means any use before
1388 m68k_ip_begin() will crash. */
1389static struct hash_control *op_hash;
1390\f
1391/* Assemble an m68k instruction. */
1392
1393static void
31302357 1394m68k_ip (char *instring)
252b5132
RH		 1395{
1396 register char *p;
1397 register struct m68k_op *opP;
1398 register const struct m68k_incant *opcode;
1399 register const char *s;
1400 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1401 char *pdot, *pdotmove;
1402 enum m68k_size siz1, siz2;
1403 char c;
1404 int losing;
1405 int opsfound;
03b13e59 1406 struct m68k_op operands_backup[6];
252b5132
RH		 1407 LITTLENUM_TYPE words[6];
1408 LITTLENUM_TYPE *wordp;
1409 unsigned long ok_arch = 0;
1410
1411 if (*instring == ' ')
36759679 1412 instring++; /* Skip leading whitespace. */
252b5132
RH		 1413
1414 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1415 or exactly 1 space. */
252b5132
RH		 1416 pdot = 0;
1417 for (p = instring; *p != '\0'; p++)
1418 {
1419 if (*p == ' ')
1420 break;
1421 if (*p == '.')
1422 pdot = p;
1423 }
1424
1425 if (p == instring)
1426 {
1427 the_ins.error = _("No operator");
1428 return;
1429 }
1430
1431 /* p now points to the end of the opcode name, probably whitespace.
1432 Make sure the name is null terminated by clobbering the
1433 whitespace, look it up in the hash table, then fix it back.
1434 Remove a dot, first, since the opcode tables have none. */
1435 if (pdot != NULL)
1436 {
1437 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1438 *pdotmove = pdotmove[1];
1439 p--;
1440 }
1441
1442 c = *p;
1443 *p = '\0';
1444 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1445 *p = c;
1446
1447 if (pdot != NULL)
1448 {
1449 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1450 *pdotmove = pdotmove[-1];
1451 *pdot = '.';
1452 ++p;
1453 }
1454
1455 if (opcode == NULL)
1456 {
1457 the_ins.error = _("Unknown operator");
1458 return;
1459 }
1460
36759679 1461 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1462 while (*p == ' ')
1463 ++p;
1464
1465 if (opcode->m_operands == 0)
1466 {
1467 char *old = input_line_pointer;
1468 *old = '\n';
1469 input_line_pointer = p;
36759679 1470 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1471 mote_pseudo_table[opcode->m_opnum].poc_handler
1472 (mote_pseudo_table[opcode->m_opnum].poc_val);
1473 input_line_pointer = old;
1474 *old = 0;
1475
1476 return;
1477 }
1478
1479 if (flag_mri && opcode->m_opnum == 0)
1480 {
1481 /* In MRI mode, random garbage is allowed after an instruction
1482 which accepts no operands. */
1483 the_ins.args = opcode->m_operands;
1484 the_ins.numargs = opcode->m_opnum;
1485 the_ins.numo = opcode->m_codenum;
1486 the_ins.opcode[0] = getone (opcode);
1487 the_ins.opcode[1] = gettwo (opcode);
1488 return;
1489 }
1490
1491 for (opP = &the_ins.operands[0]; *p; opP++)
1492 {
1493 p = crack_operand (p, opP);
1494
1495 if (opP->error)
1496 {
1497 the_ins.error = opP->error;
1498 return;
1499 }
1500 }
1501
1502 opsfound = opP - &the_ins.operands[0];
1503
1504 /* This ugly hack is to support the floating pt opcodes in their
1505 standard form. Essentially, we fake a first enty of type COP#1 */
1506 if (opcode->m_operands[0] == 'I')
1507 {
1508 int n;
1509
1510 for (n = opsfound; n > 0; --n)
1511 the_ins.operands[n] = the_ins.operands[n - 1];
1512
31302357 1513 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1514 the_ins.operands[0].mode = CONTROL;
1515 the_ins.operands[0].reg = m68k_float_copnum;
1516 opsfound++;
1517 }
1518
36759679 1519 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1520 for (losing = 0;;)
1521 {
1522 /* If we didn't get the right number of ops, or we have no
92774660 1523 common model with this pattern then reject this pattern. */
252b5132
RH		 1524
1525 ok_arch |= opcode->m_arch;
1526 if (opsfound != opcode->m_opnum
1527 || ((opcode->m_arch & current_architecture) == 0))
1528 ++losing;
1529 else
1530 {
03b13e59
NC		 1531 int i;
1532
1533 /* Make a copy of the operands of this insn so that
1534 we can modify them safely, should we want to. */
9c2799c2 1535 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
03b13e59
NC		 1536 for (i = 0; i < opsfound; i++)
1537 operands_backup[i] = the_ins.operands[i];
1538
1539 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1540 *s && !losing;
1541 s += 2, opP++)
1542 {
1543 /* Warning: this switch is huge! */
1544 /* I've tried to organize the cases into this order:
1545 non-alpha first, then alpha by letter. Lower-case
1546 goes directly before uppercase counterpart. */
1547 /* Code with multiple case ...: gets sorted by the lowest
1548 case ... it belongs to. I hope this makes sense. */
1549 switch (*s)
1550 {
1551 case '!':
1552 switch (opP->mode)
1553 {
1554 case IMMED:
1555 case DREG:
1556 case AREG:
1557 case FPREG:
1558 case CONTROL:
1559 case AINC:
1560 case ADEC:
1561 case REGLST:
1562 losing++;
1563 break;
1564 default:
1565 break;
1566 }
1567 break;
1568
1569 case '<':
1570 switch (opP->mode)
1571 {
1572 case DREG:
1573 case AREG:
1574 case FPREG:
1575 case CONTROL:
1576 case IMMED:
1577 case ADEC:
1578 case REGLST:
1579 losing++;
1580 break;
1581 default:
1582 break;
1583 }
1584 break;
1585
1586 case '>':
1587 switch (opP->mode)
1588 {
1589 case DREG:
1590 case AREG:
1591 case FPREG:
1592 case CONTROL:
1593 case IMMED:
1594 case AINC:
1595 case REGLST:
1596 losing++;
1597 break;
1598 case ABSL:
1599 break;
1600 default:
1601 if (opP->reg == PC
1602 || opP->reg == ZPC)
1603 losing++;
1604 break;
1605 }
1606 break;
1607
1608 case 'm':
1609 switch (opP->mode)
1610 {
1611 case DREG:
1612 case AREG:
1613 case AINDR:
1614 case AINC:
1615 case ADEC:
1616 break;
1617 default:
1618 losing++;
1619 }
8a104df9 1620 break;
252b5132
RH		 1621
1622 case 'n':
1623 switch (opP->mode)
1624 {
1625 case DISP:
1626 break;
1627 default:
1628 losing++;
1629 }
8a104df9 1630 break;
252b5132
RH		 1631
1632 case 'o':
1633 switch (opP->mode)
1634 {
1635 case BASE:
1636 case ABSL:
1637 case IMMED:
1638 break;
1639 default:
1640 losing++;
1641 }
8a104df9 1642 break;
252b5132
RH		 1643
1644 case 'p':
1645 switch (opP->mode)
1646 {
1647 case DREG:
1648 case AREG:
1649 case AINDR:
1650 case AINC:
1651 case ADEC:
1652 break;
1653 case DISP:
1654 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1655 losing++;
252b5132
RH		 1656 break;
1657 default:
1658 losing++;
1659 }
8a104df9 1660 break;
252b5132
RH		 1661
1662 case 'q':
1663 switch (opP->mode)
1664 {
1665 case DREG:
1666 case AINDR:
1667 case AINC:
1668 case ADEC:
1669 break;
1670 case DISP:
1671 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1672 losing++;
252b5132
RH		 1673 break;
1674 default:
1675 losing++;
1676 break;
1677 }
8a104df9 1678 break;
252b5132
RH		 1679
1680 case 'v':
1681 switch (opP->mode)
1682 {
1683 case DREG:
1684 case AINDR:
1685 case AINC:
1686 case ADEC:
1687 case ABSL:
1688 break;
1689 case DISP:
1690 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1691 losing++;
252b5132
RH		 1692 break;
1693 default:
1694 losing++;
1695 break;
1696 }
1697 break;
1698
1699 case '#':
1700 if (opP->mode != IMMED)
1701 losing++;
1702 else if (s[1] == 'b'
1703 && ! isvar (&opP->disp)
1704 && (opP->disp.exp.X_op != O_constant
1705 || ! isbyte (opP->disp.exp.X_add_number)))
1706 losing++;
1707 else if (s[1] == 'B'
1708 && ! isvar (&opP->disp)
1709 && (opP->disp.exp.X_op != O_constant
1710 || ! issbyte (opP->disp.exp.X_add_number)))
1711 losing++;
1712 else if (s[1] == 'w'
1713 && ! isvar (&opP->disp)
1714 && (opP->disp.exp.X_op != O_constant
1715 || ! isword (opP->disp.exp.X_add_number)))
1716 losing++;
1717 else if (s[1] == 'W'
1718 && ! isvar (&opP->disp)
1719 && (opP->disp.exp.X_op != O_constant
1720 || ! issword (opP->disp.exp.X_add_number)))
1721 losing++;
1722 break;
1723
1724 case '^':
1725 case 'T':
1726 if (opP->mode != IMMED)
1727 losing++;
1728 break;
1729
1730 case '$':
1731 if (opP->mode == AREG
1732 || opP->mode == CONTROL
1733 || opP->mode == FPREG
1734 || opP->mode == IMMED
1735 || opP->mode == REGLST
1736 || (opP->mode != ABSL
1737 && (opP->reg == PC
1738 || opP->reg == ZPC)))
1739 losing++;
1740 break;
1741
1742 case '%':
1743 if (opP->mode == CONTROL
1744 || opP->mode == FPREG
1745 || opP->mode == REGLST
1746 || opP->mode == IMMED
1747 || (opP->mode != ABSL
1748 && (opP->reg == PC
1749 || opP->reg == ZPC)))
1750 losing++;
1751 break;
1752
1753 case '&':
1754 switch (opP->mode)
1755 {
1756 case DREG:
1757 case AREG:
1758 case FPREG:
1759 case CONTROL:
1760 case IMMED:
1761 case AINC:
1762 case ADEC:
1763 case REGLST:
1764 losing++;
1765 break;
1766 case ABSL:
1767 break;
1768 default:
1769 if (opP->reg == PC
1770 || opP->reg == ZPC)
1771 losing++;
1772 break;
1773 }
1774 break;
1775
1776 case '*':
1777 if (opP->mode == CONTROL
1778 || opP->mode == FPREG
1779 || opP->mode == REGLST)
1780 losing++;
1781 break;
1782
1783 case '+':
1784 if (opP->mode != AINC)
1785 losing++;
1786 break;
1787
1788 case '-':
1789 if (opP->mode != ADEC)
1790 losing++;
1791 break;
1792
1793 case '/':
1794 switch (opP->mode)
1795 {
1796 case AREG:
1797 case CONTROL:
1798 case FPREG:
1799 case AINC:
1800 case ADEC:
1801 case IMMED:
1802 case REGLST:
1803 losing++;
1804 break;
1805 default:
1806 break;
1807 }
1808 break;
1809
1810 case ';':
1811 switch (opP->mode)
1812 {
1813 case AREG:
1814 case CONTROL:
1815 case FPREG:
1816 case REGLST:
1817 losing++;
1818 break;
1819 default:
1820 break;
1821 }
1822 break;
1823
1824 case '?':
1825 switch (opP->mode)
1826 {
1827 case AREG:
1828 case CONTROL:
1829 case FPREG:
1830 case AINC:
1831 case ADEC:
1832 case IMMED:
1833 case REGLST:
1834 losing++;
1835 break;
1836 case ABSL:
1837 break;
1838 default:
1839 if (opP->reg == PC || opP->reg == ZPC)
1840 losing++;
1841 break;
1842 }
1843 break;
1844
1845 case '@':
1846 switch (opP->mode)
1847 {
1848 case AREG:
1849 case CONTROL:
1850 case FPREG:
1851 case IMMED:
1852 case REGLST:
1853 losing++;
1854 break;
1855 default:
1856 break;
1857 }
1858 break;
1859
1860 case '~': /* For now! (JF FOO is this right?) */
1861 switch (opP->mode)
1862 {
1863 case DREG:
1864 case AREG:
1865 case CONTROL:
1866 case FPREG:
1867 case IMMED:
1868 case REGLST:
1869 losing++;
1870 break;
1871 case ABSL:
1872 break;
1873 default:
1874 if (opP->reg == PC
1875 || opP->reg == ZPC)
1876 losing++;
1877 break;
1878 }
1879 break;
1880
1881 case '3':
1882 if (opP->mode != CONTROL
1883 || (opP->reg != TT0 && opP->reg != TT1))
1884 losing++;
1885 break;
1886
1887 case 'A':
1888 if (opP->mode != AREG)
1889 losing++;
1890 break;
1891
1892 case 'a':
1893 if (opP->mode != AINDR)
1894 ++losing;
1895 break;
1896
fd99574b
NC		 1897 case '4':
1898 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1899 && (opP->mode != DISP
1900 || opP->reg < ADDR0
1901 || opP->reg > ADDR7))
1902 ++losing;
1903 break;
1904
252b5132
RH		 1905 case 'B': /* FOO */
1906 if (opP->mode != ABSL
1907 || (flag_long_jumps
1908 && strncmp (instring, "jbsr", 4) == 0))
1909 losing++;
1910 break;
1911
3e602632
NC		 1912 case 'b':
1913 switch (opP->mode)
1914 {
1915 case IMMED:
1916 case ABSL:
1917 case AREG:
1918 case FPREG:
1919 case CONTROL:
1920 case POST:
1921 case PRE:
1922 case REGLST:
1923 losing++;
1924 break;
1925 default:
1926 break;
1927 }
1928 break;
1929
252b5132
RH		 1930 case 'C':
1931 if (opP->mode != CONTROL || opP->reg != CCR)
1932 losing++;
1933 break;
1934
1935 case 'd':
1936 if (opP->mode != DISP
1937 || opP->reg < ADDR0
1938 || opP->reg > ADDR7)
1939 losing++;
1940 break;
1941
1942 case 'D':
1943 if (opP->mode != DREG)
1944 losing++;
1945 break;
1946
6da466c7
ILT		 1947 case 'E':
1948 if (opP->reg != ACC)
1949 losing++;
1950 break;
1951
fd99574b
NC		 1952 case 'e':
1953 if (opP->reg != ACC && opP->reg != ACC1
1954 && opP->reg != ACC2 && opP->reg != ACC3)
1955 losing++;
1956 break;
1957
252b5132
RH		 1958 case 'F':
1959 if (opP->mode != FPREG)
1960 losing++;
1961 break;
1962
6da466c7
ILT		 1963 case 'G':
1964 if (opP->reg != MACSR)
1965 losing++;
1966 break;
1967
fd99574b
NC		 1968 case 'g':
1969 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1970 losing++;
1971 break;
1972
6da466c7
ILT		 1973 case 'H':
1974 if (opP->reg != MASK)
1975 losing++;
1976 break;
1977
252b5132
RH		 1978 case 'I':
1979 if (opP->mode != CONTROL
1980 || opP->reg < COP0
1981 || opP->reg > COP7)
1982 losing++;
1983 break;
1984
fd99574b
NC		 1985 case 'i':
1986 if (opP->mode != LSH && opP->mode != RSH)
1987 losing++;
1988 break;
1989
252b5132
RH		 1990 case 'J':
1991 if (opP->mode != CONTROL
1992 || opP->reg < USP
0b2e31dc
NS		 1993 || opP->reg > last_movec_reg
1994 || !control_regs)
252b5132
RH		 1995 losing++;
1996 else
1997 {
1998 const enum m68k_register *rp;
0b2e31dc 1999
252b5132 2000 for (rp = control_regs; *rp; rp++)
78336706
NS		 2001 {
2002 if (*rp == opP->reg)
2003 break;
2004 /* In most CPUs RAMBAR refers to control reg
2005 c05 (RAMBAR1), but a few CPUs have it
2006 refer to c04 (RAMBAR0). */
2007 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
2008 {
2009 opP->reg = RAMBAR_ALT;
2010 break;
2011 }
2012 }
252b5132
RH		 2013 if (*rp == 0)
2014 losing++;
2015 }
2016 break;
2017
2018 case 'k':
2019 if (opP->mode != IMMED)
2020 losing++;
2021 break;
2022
2023 case 'l':
2024 case 'L':
2025 if (opP->mode == DREG
2026 || opP->mode == AREG
2027 || opP->mode == FPREG)
2028 {
2029 if (s[1] == '8')
2030 losing++;
2031 else
2032 {
2033 switch (opP->mode)
2034 {
2035 case DREG:
2036 opP->mask = 1 << (opP->reg - DATA0);
2037 break;
2038 case AREG:
2039 opP->mask = 1 << (opP->reg - ADDR0 + 8);
2040 break;
2041 case FPREG:
2042 opP->mask = 1 << (opP->reg - FP0 + 16);
2043 break;
2044 default:
2045 abort ();
2046 }
2047 opP->mode = REGLST;
2048 }
2049 }
2050 else if (opP->mode == CONTROL)
2051 {
2052 if (s[1] != '8')
2053 losing++;
2054 else
2055 {
2056 switch (opP->reg)
2057 {
2058 case FPI:
2059 opP->mask = 1 << 24;
2060 break;
2061 case FPS:
2062 opP->mask = 1 << 25;
2063 break;
2064 case FPC:
2065 opP->mask = 1 << 26;
2066 break;
2067 default:
2068 losing++;
2069 break;
2070 }
2071 opP->mode = REGLST;
2072 }
2073 }
2074 else if (opP->mode != REGLST)
2075 losing++;
2076 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2077 losing++;
2078 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2079 losing++;
2080 break;
2081
2082 case 'M':
2083 if (opP->mode != IMMED)
2084 losing++;
2085 else if (opP->disp.exp.X_op != O_constant
2086 || ! issbyte (opP->disp.exp.X_add_number))
2087 losing++;
2088 else if (! m68k_quick
2089 && instring[3] != 'q'
2090 && instring[4] != 'q')
2091 losing++;
2092 break;
2093
2094 case 'O':
2095 if (opP->mode != DREG
2096 && opP->mode != IMMED
2097 && opP->mode != ABSL)
2098 losing++;
2099 break;
2100
2101 case 'Q':
2102 if (opP->mode != IMMED)
2103 losing++;
2104 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2105 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 2106 losing++;
2107 else if (! m68k_quick
2108 && (strncmp (instring, "add", 3) == 0
2109 || strncmp (instring, "sub", 3) == 0)
2110 && instring[3] != 'q')
2111 losing++;
2112 break;
2113
2114 case 'R':
2115 if (opP->mode != DREG && opP->mode != AREG)
2116 losing++;
2117 break;
2118
2119 case 'r':
2120 if (opP->mode != AINDR
2121 && (opP->mode != BASE
2122 || (opP->reg != 0
2123 && opP->reg != ZADDR0)
2124 || opP->disp.exp.X_op != O_absent
2125 || ((opP->index.reg < DATA0
2126 || opP->index.reg > DATA7)
2127 && (opP->index.reg < ADDR0
2128 || opP->index.reg > ADDR7))
2129 || opP->index.size != SIZE_UNSPEC
2130 || opP->index.scale != 1))
2131 losing++;
2132 break;
2133
2134 case 's':
2135 if (opP->mode != CONTROL
2136 || ! (opP->reg == FPI
2137 || opP->reg == FPS
2138 || opP->reg == FPC))
2139 losing++;
2140 break;
2141
2142 case 'S':
2143 if (opP->mode != CONTROL || opP->reg != SR)
2144 losing++;
2145 break;
2146
2147 case 't':
2148 if (opP->mode != IMMED)
2149 losing++;
2150 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2151 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 2152 losing++;
2153 break;
2154
2155 case 'U':
2156 if (opP->mode != CONTROL || opP->reg != USP)
2157 losing++;
2158 break;
2159
3e602632
NC		 2160 case 'x':
2161 if (opP->mode != IMMED)
2162 losing++;
2163 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 2164 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2165 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 2166 losing++;
2167 break;
2168
afa2158f
NS		 2169 case 'j':
2170 if (opP->mode != IMMED)
2171 losing++;
2172 else if (opP->disp.exp.X_op != O_constant
2173 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2174 losing++;
2175 break;
2176
2177 case 'K':
2178 if (opP->mode != IMMED)
2179 losing++;
2180 else if (opP->disp.exp.X_op != O_constant
2181 || TRUNC (opP->disp.exp.X_add_number) > 511)
2182 losing++;
2183 break;
2184
252b5132
RH		 2185 /* JF these are out of order. We could put them
2186 in order if we were willing to put up with
2187 bunches of #ifdef m68851s in the code.
2188
2189 Don't forget that you need these operands
2190 to use 68030 MMU instructions. */
2191#ifndef NO_68851
36759679 2192 /* Memory addressing mode used by pflushr. */
252b5132
RH		 2193 case '|':
2194 if (opP->mode == CONTROL
2195 || opP->mode == FPREG
2196 || opP->mode == DREG
2197 || opP->mode == AREG
2198 || opP->mode == REGLST)
2199 losing++;
2200 /* We should accept immediate operands, but they
2201 supposedly have to be quad word, and we don't
2202 handle that. I would like to see what a Motorola
2203 assembler does before doing something here. */
2204 if (opP->mode == IMMED)
2205 losing++;
2206 break;
2207
2208 case 'f':
2209 if (opP->mode != CONTROL
2210 || (opP->reg != SFC && opP->reg != DFC))
2211 losing++;
2212 break;
2213
2214 case '0':
2215 if (opP->mode != CONTROL || opP->reg != TC)
2216 losing++;
2217 break;
2218
2219 case '1':
2220 if (opP->mode != CONTROL || opP->reg != AC)
2221 losing++;
2222 break;
2223
2224 case '2':
2225 if (opP->mode != CONTROL
2226 || (opP->reg != CAL
2227 && opP->reg != VAL
2228 && opP->reg != SCC))
2229 losing++;
2230 break;
2231
2232 case 'V':
2233 if (opP->mode != CONTROL
2234 || opP->reg != VAL)
2235 losing++;
2236 break;
2237
2238 case 'W':
2239 if (opP->mode != CONTROL
2240 || (opP->reg != DRP
2241 && opP->reg != SRP
2242 && opP->reg != CRP))
2243 losing++;
2244 break;
2245
3e602632
NC		 2246 case 'w':
2247 switch (opP->mode)
2248 {
2249 case IMMED:
2250 case ABSL:
2251 case AREG:
2252 case DREG:
2253 case FPREG:
2254 case CONTROL:
2255 case POST:
2256 case PRE:
2257 case REGLST:
2258 losing++;
2259 break;
2260 default:
2261 break;
2262 }
2263 break;
2264
252b5132
RH		 2265 case 'X':
2266 if (opP->mode != CONTROL
2267 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2268 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2269 losing++;
2270 break;
2271
2272 case 'Y':
2273 if (opP->mode != CONTROL || opP->reg != PSR)
2274 losing++;
2275 break;
2276
2277 case 'Z':
2278 if (opP->mode != CONTROL || opP->reg != PCSR)
2279 losing++;
2280 break;
2281#endif
2282 case 'c':
2283 if (opP->mode != CONTROL
2284 || (opP->reg != NC
2285 && opP->reg != IC
2286 && opP->reg != DC
2287 && opP->reg != BC))
36759679 2288 losing++;
252b5132
RH		 2289 break;
2290
2291 case '_':
2292 if (opP->mode != ABSL)
2293 ++losing;
2294 break;
2295
6da466c7
ILT		 2296 case 'u':
2297 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2298 losing++;
2299 /* FIXME: kludge instead of fixing parser:
2300 upper/lower registers are *not* CONTROL
92774660 2301 registers, but ordinary ones. */
6da466c7
ILT		 2302 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2303 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2304 opP->mode = DREG;
2305 else
2306 opP->mode = AREG;
2307 break;
2308
3e602632
NC		 2309 case 'y':
2310 if (!(opP->mode == AINDR
31302357
AS		 2311 || (opP->mode == DISP
2312 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2313 losing++;
2314 break;
2315
2316 case 'z':
2317 if (!(opP->mode == AINDR || opP->mode == DISP))
2318 losing++;
2319 break;
2320
252b5132
RH		 2321 default:
2322 abort ();
36759679 2323 }
252b5132
RH		 2324
2325 if (losing)
2326 break;
36759679 2327 }
03b13e59
NC		 2328
2329 /* Since we have found the correct instruction, copy
2330 in the modifications that we may have made. */
2331 if (!losing)
2332 for (i = 0; i < opsfound; i++)
2333 the_ins.operands[i] = operands_backup[i];
36759679 2334 }
252b5132
RH		 2335
2336 if (!losing)
36759679 2337 break;
252b5132
RH		 2338
2339 opcode = opcode->m_next;
2340
2341 if (!opcode)
2342 {
2343 if (ok_arch
2344 && !(ok_arch & current_architecture))
2345 {
6d89cc8f
NS		 2346 const struct m68k_cpu *cpu;
2347 int any = 0;
2348 size_t space = 400;
2349 char *buf = xmalloc (space + 1);
2350 size_t len;
2351 int paren = 1;
2352
2353 the_ins.error = buf;
2354 /* Make sure there's a NUL at the end of the buffer -- strncpy
b2f58c0c 2355 won't write one when it runs out of buffer. */
6d89cc8f
NS		 2356 buf[space] = 0;
2357#define APPEND(STRING) \
2358 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2359
2360 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2361 switch (ok_arch)
2362 {
6b6e92f4 2363 case mcfisa_a:
b2f58c0c 2364 APPEND ("ColdFire ISA_A");
6b6e92f4
NC		 2365 break;
2366 case mcfhwdiv:
b2f58c0c
NC		 2367 APPEND ("ColdFire ");
2368 APPEND (_("hardware divide"));
6b6e92f4
NC		 2369 break;
2370 case mcfisa_aa:
b2f58c0c 2371 APPEND ("ColdFire ISA_A+");
6b6e92f4
NC		 2372 break;
2373 case mcfisa_b:
b2f58c0c 2374 APPEND ("ColdFire ISA_B");
6b6e92f4 2375 break;
8d100c32 2376 case mcfisa_c:
b2f58c0c 2377 APPEND ("ColdFire ISA_C");
8d100c32 2378 break;
3e602632 2379 case cfloat:
b2f58c0c 2380 APPEND ("ColdFire fpu");
3e602632 2381 break;
252b5132 2382 case mfloat:
b2f58c0c 2383 APPEND ("M68K fpu");
252b5132
RH		 2384 break;
2385 case mmmu:
b2f58c0c 2386 APPEND ("M68K mmu");
252b5132
RH		 2387 break;
2388 case m68020up:
b2f58c0c
NC		 2389 APPEND ("68020 ");
2390 APPEND (_("or higher"));
252b5132
RH		 2391 break;
2392 case m68000up:
b2f58c0c
NC		 2393 APPEND ("68000 ");
2394 APPEND (_("or higher"));
252b5132
RH		 2395 break;
2396 case m68010up:
b2f58c0c
NC		 2397 APPEND ("68010 ");
2398 APPEND (_("or higher"));
252b5132
RH		 2399 break;
2400 default:
6d89cc8f
NS		 2401 paren = 0;
2402 }
2403 if (paren)
2404 APPEND (" (");
6b6e92f4 2405
6d89cc8f
NS		 2406 for (cpu = m68k_cpus; cpu->name; cpu++)
2407 if (!cpu->alias && (cpu->arch & ok_arch))
2408 {
2409 const struct m68k_cpu *alias;
869ddf2a
NS		 2410 int seen_master = 0;
2411
6d89cc8f
NS		 2412 if (any)
2413 APPEND (", ");
2414 any = 0;
2415 APPEND (cpu->name);
869ddf2a
NS		 2416 for (alias = cpu; alias != m68k_cpus; alias--)
2417 if (alias[-1].alias >= 0)
2418 break;
2419 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2420 {
869ddf2a
NS		 2421 if (!alias->alias)
2422 seen_master = 1;
2423 else
2424 {
2425 if (any)
2426 APPEND (", ");
2427 else
2428 APPEND (" [");
2429 APPEND (alias->name);
2430 any = 1;
2431 }
6d89cc8f 2432 }
869ddf2a
NS		 2433 if (any)
2434 APPEND ("]");
6d89cc8f 2435 any = 1;
252b5132 2436 }
6d89cc8f
NS		 2437 if (paren)
2438 APPEND (")");
2439#undef APPEND
2440 if (!space)
2441 {
b2f58c0c 2442 /* We ran out of space, so replace the end of the list
6d89cc8f
NS		 2443 with ellipsis. */
2444 buf -= 4;
2445 while (*buf != ' ')
2446 buf--;
2447 strcpy (buf, " ...");
252b5132 2448 }
252b5132
RH		 2449 }
2450 else
2451 the_ins.error = _("operands mismatch");
2452 return;
36759679 2453 }
252b5132
RH		 2454
2455 losing = 0;
2456 }
2457
36759679 2458 /* Now assemble it. */
252b5132
RH		 2459 the_ins.args = opcode->m_operands;
2460 the_ins.numargs = opcode->m_opnum;
2461 the_ins.numo = opcode->m_codenum;
2462 the_ins.opcode[0] = getone (opcode);
2463 the_ins.opcode[1] = gettwo (opcode);
2464
2465 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2466 {
9a2e615a 2467 int have_disp = 0;
cac27205 2468 int use_pl = 0;
9a2e615a 2469
252b5132 2470 /* This switch is a doozy.
31302357 2471 Watch the first step; its a big one! */
252b5132
RH		 2472 switch (s[0])
2473 {
2474
2475 case '*':
2476 case '~':
2477 case '%':
2478 case ';':
2479 case '@':
2480 case '!':
2481 case '&':
2482 case '$':
2483 case '?':
2484 case '/':
2485 case '<':
2486 case '>':
3e602632 2487 case 'b':
252b5132
RH		 2488 case 'm':
2489 case 'n':
2490 case 'o':
2491 case 'p':
2492 case 'q':
2493 case 'v':
3e602632
NC		 2494 case 'w':
2495 case 'y':
2496 case 'z':
fd99574b 2497 case '4':
252b5132
RH		 2498#ifndef NO_68851
2499 case '|':
2500#endif
2501 switch (opP->mode)
2502 {
2503 case IMMED:
2504 tmpreg = 0x3c; /* 7.4 */
2505 if (strchr ("bwl", s[1]))
3e602632 2506 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2507 else
2508 nextword = get_num (&opP->disp, 0);
2509 if (isvar (&opP->disp))
2510 add_fix (s[1], &opP->disp, 0, 0);
2511 switch (s[1])
2512 {
2513 case 'b':
2514 if (!isbyte (nextword))
2515 opP->error = _("operand out of range");
2516 addword (nextword);
2517 baseo = 0;
2518 break;
2519 case 'w':
2520 if (!isword (nextword))
2521 opP->error = _("operand out of range");
2522 addword (nextword);
2523 baseo = 0;
2524 break;
2525 case 'W':
2526 if (!issword (nextword))
2527 opP->error = _("operand out of range");
2528 addword (nextword);
2529 baseo = 0;
2530 break;
2531 case 'l':
2532 addword (nextword >> 16);
2533 addword (nextword);
2534 baseo = 0;
2535 break;
2536
2537 case 'f':
2538 baseo = 2;
2539 outro = 8;
2540 break;
2541 case 'F':
2542 baseo = 4;
2543 outro = 11;
2544 break;
2545 case 'x':
2546 baseo = 6;
2547 outro = 15;
2548 break;
2549 case 'p':
2550 baseo = 6;
2551 outro = -1;
2552 break;
2553 default:
2554 abort ();
2555 }
2556 if (!baseo)
2557 break;
2558
36759679 2559 /* We gotta put out some float. */
252b5132
RH		 2560 if (op (&opP->disp) != O_big)
2561 {
2562 valueT val;
2563 int gencnt;
2564
2565 /* Can other cases happen here? */
2566 if (op (&opP->disp) != O_constant)
2567 abort ();
2568
2569 val = (valueT) offs (&opP->disp);
2570 gencnt = 0;
2571 do
2572 {
2573 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2574 val >>= LITTLENUM_NUMBER_OF_BITS;
2575 ++gencnt;
2576 }
2577 while (val != 0);
2578 offs (&opP->disp) = gencnt;
2579 }
2580 if (offs (&opP->disp) > 0)
2581 {
2582 if (offs (&opP->disp) > baseo)
2583 {
2584 as_warn (_("Bignum too big for %c format; truncated"),
2585 s[1]);
2586 offs (&opP->disp) = baseo;
2587 }
2588 baseo -= offs (&opP->disp);
2589 while (baseo--)
2590 addword (0);
2591 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2592 offs (&opP->disp)--;
2593 --wordp)
2594 addword (*wordp);
2595 break;
2596 }
2597 gen_to_words (words, baseo, (long) outro);
2598 for (wordp = words; baseo--; wordp++)
2599 addword (*wordp);
2600 break;
2601 case DREG:
2602 tmpreg = opP->reg - DATA; /* 0.dreg */
2603 break;
2604 case AREG:
2605 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2606 break;
2607 case AINDR:
2608 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2609 break;
2610 case ADEC:
2611 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2612 break;
2613 case AINC:
2614 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2615 break;
2616 case DISP:
2617
3e602632 2618 nextword = get_num (&opP->disp, 90);
252b5132 2619
580b9172
NC		 2620 /* Convert mode 5 addressing with a zero offset into
2621 mode 2 addressing to reduce the instruction size by a
2622 word. */
2623 if (! isvar (&opP->disp)
2624 && (nextword == 0)
2625 && (opP->disp.size == SIZE_UNSPEC)
2626 && (opP->reg >= ADDR0)
2627 && (opP->reg <= ADDR7))
2628 {
2629 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2630 break;
2631 }
2632
252b5132
RH		 2633 if (opP->reg == PC
2634 && ! isvar (&opP->disp)
2635 && m68k_abspcadd)
2636 {
2637 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2638 opP->disp.exp.X_add_symbol =
2639 section_symbol (absolute_section);
252b5132
RH		 2640 }
2641
36759679 2642 /* Force into index mode. Hope this works. */
252b5132
RH		 2643
2644 /* We do the first bit for 32-bit displacements, and the
2645 second bit for 16 bit ones. It is possible that we
2646 should make the default be WORD instead of LONG, but
2647 I think that'd break GCC, so we put up with a little
2648 inefficiency for the sake of working output. */
2649
2650 if (!issword (nextword)
2651 || (isvar (&opP->disp)
2652 && ((opP->disp.size == SIZE_UNSPEC
2653 && flag_short_refs == 0
2654 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2655 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2656 || opP->disp.size == SIZE_LONG)))
2657 {
2658 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2659 || arch_coldfire_p (current_architecture))
252b5132
RH		 2660 opP->error =
2661 _("displacement too large for this architecture; needs 68020 or higher");
2662 if (opP->reg == PC)
2663 tmpreg = 0x3B; /* 7.3 */
2664 else
2665 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2666 if (isvar (&opP->disp))
2667 {
2668 if (opP->reg == PC)
2669 {
2670 if (opP->disp.size == SIZE_LONG
2671#ifdef OBJ_ELF
2672 /* If the displacement needs pic
2673 relocation it cannot be relaxed. */
2674 || opP->disp.pic_reloc != pic_none
2675#endif
2676 )
2677 {
2678 addword (0x0170);
2679 add_fix ('l', &opP->disp, 1, 2);
2680 }
2681 else
2682 {
2683 add_frag (adds (&opP->disp),
bd17c2c3 2684 SEXT (offs (&opP->disp)),
151337e8 2685 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2686 break;
2687 }
2688 }
2689 else
2690 {
2691 addword (0x0170);
2692 add_fix ('l', &opP->disp, 0, 0);
2693 }
2694 }
2695 else
2696 addword (0x0170);
2697 addword (nextword >> 16);
2698 }
2699 else
2700 {
2701 if (opP->reg == PC)
2702 tmpreg = 0x3A; /* 7.2 */
2703 else
2704 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2705
2706 if (isvar (&opP->disp))
2707 {
2708 if (opP->reg == PC)
2709 {
2710 add_fix ('w', &opP->disp, 1, 0);
2711 }
2712 else
2713 add_fix ('w', &opP->disp, 0, 0);
2714 }
2715 }
2716 addword (nextword);
2717 break;
2718
2719 case POST:
2720 case PRE:
2721 case BASE:
2722 nextword = 0;
3e602632 2723 baseo = get_num (&opP->disp, 90);
252b5132 2724 if (opP->mode == POST || opP->mode == PRE)
3e602632 2725 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2726 /* Figure out the `addressing mode'.
2727 Also turn on the BASE_DISABLE bit, if needed. */
2728 if (opP->reg == PC || opP->reg == ZPC)
2729 {
2730 tmpreg = 0x3b; /* 7.3 */
2731 if (opP->reg == ZPC)
2732 nextword |= 0x80;
2733 }
2734 else if (opP->reg == 0)
2735 {
2736 nextword |= 0x80;
2737 tmpreg = 0x30; /* 6.garbage */
2738 }
2739 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2740 {
2741 nextword |= 0x80;
2742 tmpreg = 0x30 + opP->reg - ZADDR0;
2743 }
2744 else
2745 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2746
2747 siz1 = opP->disp.size;
2748 if (opP->mode == POST || opP->mode == PRE)
2749 siz2 = opP->odisp.size;
2750 else
2751 siz2 = SIZE_UNSPEC;
2752
36759679 2753 /* Index register stuff. */
252b5132
RH		 2754 if (opP->index.reg != 0
2755 && opP->index.reg >= DATA
2756 && opP->index.reg <= ADDR7)
2757 {
2758 nextword |= (opP->index.reg - DATA) << 12;
2759
2760 if (opP->index.size == SIZE_LONG
2761 || (opP->index.size == SIZE_UNSPEC
2762 && m68k_index_width_default == SIZE_LONG))
2763 nextword |= 0x800;
2764
92774660 2765 if ((opP->index.scale != 1
252b5132 2766 && cpu_of_arch (current_architecture) < m68020)
92774660 2767 || (opP->index.scale == 8
3e602632 2768 && (arch_coldfire_p (current_architecture)
6b6e92f4 2769 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2770 {
2771 opP->error =
2772 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2773 }
2774
6da466c7
ILT		 2775 if (arch_coldfire_p (current_architecture)
2776 && opP->index.size == SIZE_WORD)
2777 opP->error = _("invalid index size for coldfire");
2778
252b5132
RH		 2779 switch (opP->index.scale)
2780 {
2781 case 1:
2782 break;
2783 case 2:
2784 nextword |= 0x200;
2785 break;
2786 case 4:
2787 nextword |= 0x400;
2788 break;
2789 case 8:
2790 nextword |= 0x600;
2791 break;
2792 default:
2793 abort ();
2794 }
2795 /* IF its simple,
2796 GET US OUT OF HERE! */
2797
2798 /* Must be INDEX, with an index register. Address
2799 register cannot be ZERO-PC, and either :b was
2800 forced, or we know it will fit. For a 68000 or
2801 68010, force this mode anyways, because the
2802 larger modes aren't supported. */
2803 if (opP->mode == BASE
2804 && ((opP->reg >= ADDR0
2805 && opP->reg <= ADDR7)
2806 || opP->reg == PC))
2807 {
2808 if (siz1 == SIZE_BYTE
2809 || cpu_of_arch (current_architecture) < m68020
6da466c7 2810 || arch_coldfire_p (current_architecture)
252b5132
RH		 2811 || (siz1 == SIZE_UNSPEC
2812 && ! isvar (&opP->disp)
2813 && issbyte (baseo)))
2814 {
2815 nextword += baseo & 0xff;
2816 addword (nextword);
2817 if (isvar (&opP->disp))
2818 {
2819 /* Do a byte relocation. If it doesn't
2820 fit (possible on m68000) let the
2821 fixup processing complain later. */
2822 if (opP->reg == PC)
2823 add_fix ('B', &opP->disp, 1, 1);
2824 else
2825 add_fix ('B', &opP->disp, 0, 0);
2826 }
2827 else if (siz1 != SIZE_BYTE)
2828 {
2829 if (siz1 != SIZE_UNSPEC)
2830 as_warn (_("Forcing byte displacement"));
2831 if (! issbyte (baseo))
2832 opP->error = _("byte displacement out of range");
2833 }
2834
2835 break;
2836 }
2837 else if (siz1 == SIZE_UNSPEC
2838 && opP->reg == PC
2839 && isvar (&opP->disp)
2840 && subs (&opP->disp) == NULL
2841#ifdef OBJ_ELF
2842 /* If the displacement needs pic
2843 relocation it cannot be relaxed. */
2844 && opP->disp.pic_reloc == pic_none
2845#endif
2846 )
2847 {
2848 /* The code in md_convert_frag_1 needs to be
2849 able to adjust nextword. Call frag_grow
2850 to ensure that we have enough space in
2851 the frag obstack to make all the bytes
2852 contiguous. */
2853 frag_grow (14);
8a104df9
KH		 2854 nextword += baseo & 0xff;
2855 addword (nextword);
bd17c2c3
AM		 2856 add_frag (adds (&opP->disp),
2857 SEXT (offs (&opP->disp)),
8a104df9 2858 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2859
2860 break;
8a104df9 2861 }
252b5132
RH		 2862 }
2863 }
2864 else
2865 {
36759679 2866 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2867 if (opP->index.reg >= ZDATA0
2868 && opP->index.reg <= ZDATA7)
2869 nextword |= (opP->index.reg - ZDATA0) << 12;
2870 else if (opP->index.reg >= ZADDR0
2871 || opP->index.reg <= ZADDR7)
2872 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2873 }
2874
2875 /* It isn't simple. */
2876
2877 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2878 || arch_coldfire_p (current_architecture))
252b5132
RH		 2879 opP->error =
2880 _("invalid operand mode for this architecture; needs 68020 or higher");
2881
2882 nextword |= 0x100;
2883 /* If the guy specified a width, we assume that it is
2884 wide enough. Maybe it isn't. If so, we lose. */
2885 switch (siz1)
2886 {
2887 case SIZE_UNSPEC:
2888 if (isvar (&opP->disp)
2889 ? m68k_rel32
2890 : ! issword (baseo))
2891 {
2892 siz1 = SIZE_LONG;
2893 nextword |= 0x30;
2894 }
2895 else if (! isvar (&opP->disp) && baseo == 0)
2896 nextword |= 0x10;
2897 else
2898 {
2899 nextword |= 0x20;
2900 siz1 = SIZE_WORD;
2901 }
2902 break;
2903 case SIZE_BYTE:
2904 as_warn (_(":b not permitted; defaulting to :w"));
2905 /* Fall through. */
2906 case SIZE_WORD:
2907 nextword |= 0x20;
2908 break;
2909 case SIZE_LONG:
2910 nextword |= 0x30;
2911 break;
2912 }
2913
67c1ffbe 2914 /* Figure out inner displacement stuff. */
252b5132
RH		 2915 if (opP->mode == POST || opP->mode == PRE)
2916 {
2917 if (cpu_of_arch (current_architecture) & cpu32)
2918 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2919 switch (siz2)
2920 {
2921 case SIZE_UNSPEC:
2922 if (isvar (&opP->odisp)
2923 ? m68k_rel32
2924 : ! issword (outro))
2925 {
2926 siz2 = SIZE_LONG;
2927 nextword |= 0x3;
2928 }
2929 else if (! isvar (&opP->odisp) && outro == 0)
2930 nextword |= 0x1;
2931 else
2932 {
2933 nextword |= 0x2;
2934 siz2 = SIZE_WORD;
2935 }
2936 break;
2937 case 1:
2938 as_warn (_(":b not permitted; defaulting to :w"));
2939 /* Fall through. */
2940 case 2:
2941 nextword |= 0x2;
2942 break;
2943 case 3:
2944 nextword |= 0x3;
2945 break;
2946 }
2947 if (opP->mode == POST
2948 && (nextword & 0x40) == 0)
2949 nextword |= 0x04;
2950 }
2951 addword (nextword);
2952
2953 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2954 {
2955 if (opP->reg == PC || opP->reg == ZPC)
2956 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2957 else
2958 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2959 }
2960 if (siz1 == SIZE_LONG)
2961 addword (baseo >> 16);
2962 if (siz1 != SIZE_UNSPEC)
2963 addword (baseo);
2964
2965 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2966 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2967 if (siz2 == SIZE_LONG)
2968 addword (outro >> 16);
2969 if (siz2 != SIZE_UNSPEC)
2970 addword (outro);
2971
2972 break;
2973
2974 case ABSL:
3e602632 2975 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2976 switch (opP->disp.size)
2977 {
2978 default:
2979 abort ();
2980 case SIZE_UNSPEC:
2981 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2982 {
2983 tmpreg = 0x38; /* 7.0 */
2984 addword (nextword);
2985 break;
2986 }
252b5132
RH		 2987 if (isvar (&opP->disp)
2988 && !subs (&opP->disp)
2989 && adds (&opP->disp)
2990#ifdef OBJ_ELF
2991 /* If the displacement needs pic relocation it
2992 cannot be relaxed. */
2993 && opP->disp.pic_reloc == pic_none
2994#endif
252b5132
RH		 2995 && !flag_long_jumps
2996 && !strchr ("~%&$?", s[0]))
2997 {
2998 tmpreg = 0x3A; /* 7.2 */
2999 add_frag (adds (&opP->disp),
bd17c2c3 3000 SEXT (offs (&opP->disp)),
151337e8 3001 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 3002 break;
3003 }
36759679 3004 /* Fall through into long. */
252b5132
RH		 3005 case SIZE_LONG:
3006 if (isvar (&opP->disp))
3007 add_fix ('l', &opP->disp, 0, 0);
3008
3009 tmpreg = 0x39;/* 7.1 mode */
3010 addword (nextword >> 16);
3011 addword (nextword);
3012 break;
3013
3014 case SIZE_BYTE:
3015 as_bad (_("unsupported byte value; use a different suffix"));
3016 /* Fall through. */
36759679
NC		 3017
3018 case SIZE_WORD:
252b5132
RH		 3019 if (isvar (&opP->disp))
3020 add_fix ('w', &opP->disp, 0, 0);
3021
3022 tmpreg = 0x38;/* 7.0 mode */
3023 addword (nextword);
3024 break;
3025 }
3026 break;
3027 case CONTROL:
3028 case FPREG:
3029 default:
3030 as_bad (_("unknown/incorrect operand"));
bc805888 3031 /* abort (); */
252b5132 3032 }
fd99574b
NC		 3033
3034 /* If s[0] is '4', then this is for the mac instructions
3035 that can have a trailing_ampersand set. If so, set 0x100
3036 bit on tmpreg so install_gen_operand can check for it and
3037 set the appropriate bit (word2, bit 5). */
3038 if (s[0] == '4')
3039 {
3040 if (opP->trailing_ampersand)
3041 tmpreg |= 0x100;
3042 }
252b5132
RH		 3043 install_gen_operand (s[1], tmpreg);
3044 break;
3045
3046 case '#':
3047 case '^':
3048 switch (s[1])
3049 { /* JF: I hate floating point! */
3050 case 'j':
3051 tmpreg = 70;
3052 break;
3053 case '8':
3054 tmpreg = 20;
3055 break;
3056 case 'C':
3057 tmpreg = 50;
3058 break;
3059 case '3':
3060 default:
3e602632 3061 tmpreg = 90;
252b5132
RH		 3062 break;
3063 }
3064 tmpreg = get_num (&opP->disp, tmpreg);
3065 if (isvar (&opP->disp))
3066 add_fix (s[1], &opP->disp, 0, 0);
3067 switch (s[1])
3068 {
3069 case 'b': /* Danger: These do no check for
3070 certain types of overflow.
3071 user beware! */
3072 if (!isbyte (tmpreg))
3073 opP->error = _("out of range");
3074 insop (tmpreg, opcode);
3075 if (isvar (&opP->disp))
3076 the_ins.reloc[the_ins.nrel - 1].n =
3077 (opcode->m_codenum) * 2 + 1;
3078 break;
3079 case 'B':
3080 if (!issbyte (tmpreg))
3081 opP->error = _("out of range");
3082 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3083 if (isvar (&opP->disp))
3084 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3085 break;
3086 case 'w':
3087 if (!isword (tmpreg))
3088 opP->error = _("out of range");
3089 insop (tmpreg, opcode);
3090 if (isvar (&opP->disp))
3091 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3092 break;
3093 case 'W':
3094 if (!issword (tmpreg))
3095 opP->error = _("out of range");
3096 insop (tmpreg, opcode);
3097 if (isvar (&opP->disp))
3098 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3099 break;
3100 case 'l':
3101 /* Because of the way insop works, we put these two out
3102 backwards. */
3103 insop (tmpreg, opcode);
3104 insop (tmpreg >> 16, opcode);
3105 if (isvar (&opP->disp))
3106 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3107 break;
3108 case '3':
3109 tmpreg &= 0xFF;
3110 case '8':
3111 case 'C':
3112 case 'j':
3113 install_operand (s[1], tmpreg);
3114 break;
3115 default:
3116 abort ();
3117 }
3118 break;
3119
3120 case '+':
3121 case '-':
3122 case 'A':
3123 case 'a':
3124 install_operand (s[1], opP->reg - ADDR);
3125 break;
3126
3127 case 'B':
3e602632 3128 tmpreg = get_num (&opP->disp, 90);
9a2e615a 3129
252b5132
RH		 3130 switch (s[1])
3131 {
3132 case 'B':
8390138c 3133 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 3134 break;
3135 case 'W':
3136 add_fix ('w', &opP->disp, 1, 0);
3137 addword (0);
3138 break;
3139 case 'L':
3140 long_branch:
151337e8 3141 the_ins.opcode[0] |= 0xff;
252b5132
RH		 3142 add_fix ('l', &opP->disp, 1, 0);
3143 addword (0);
3144 addword (0);
3145 break;
9a2e615a
NS		 3146 case 'g': /* Conditional branch */
3147 have_disp = HAVE_LONG_CALL (current_architecture);
3148 goto var_branch;
3149
3150 case 'b': /* Unconditional branch */
3151 have_disp = HAVE_LONG_BRANCH (current_architecture);
cac27205 3152 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
9a2e615a
NS		 3153 goto var_branch;
3154
3155 case 's': /* Unconditional subroutine */
3156 have_disp = HAVE_LONG_CALL (current_architecture);
3157
3158 var_branch:
3159 if (subs (&opP->disp) /* We can't relax it. */
252b5132 3160#ifdef OBJ_ELF
9a2e615a
NS		 3161 /* If the displacement needs pic relocation it cannot be
3162 relaxed. */
3163 || opP->disp.pic_reloc != pic_none
252b5132 3164#endif
9a2e615a
NS		 3165 || 0)
3166 {
3167 if (!have_disp)
3168 as_warn (_("Can't use long branches on this architecture"));
3169 goto long_branch;
3170 }
3171
252b5132 3172 /* This could either be a symbol, or an absolute
151337e8
NC		 3173 address. If it's an absolute address, turn it into
3174 an absolute jump right here and keep it out of the
3175 relaxer. */
3176 if (adds (&opP->disp) == 0)
3177 {
3178 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 3179 the_ins.opcode[0] = 0x4EF9;
151337e8 3180 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 3181 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 3182 else /* jCC */
3183 {
3184 the_ins.opcode[0] ^= 0x0100;
3185 the_ins.opcode[0] |= 0x0006;
18566f55 3186 addword (0x4EF9);
151337e8
NC		 3187 }
3188 add_fix ('l', &opP->disp, 0, 0);
3189 addword (0);
3190 addword (0);
3191 break;
3192 }
3193
3194 /* Now we know it's going into the relaxer. Now figure
3195 out which mode. We try in this order of preference:
3196 long branch, absolute jump, byte/word branches only. */
9a2e615a 3197 if (have_disp)
bd17c2c3
AM		 3198 add_frag (adds (&opP->disp),
3199 SEXT (offs (&opP->disp)),
151337e8
NC		 3200 TAB (BRANCHBWL, SZ_UNDEF));
3201 else if (! flag_keep_pcrel)
3202 {
3203 if ((the_ins.opcode[0] == 0x6000)
3204 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 3205 add_frag (adds (&opP->disp),
3206 SEXT (offs (&opP->disp)),
151337e8
NC		 3207 TAB (BRABSJUNC, SZ_UNDEF));
3208 else
bd17c2c3
AM		 3209 add_frag (adds (&opP->disp),
3210 SEXT (offs (&opP->disp)),
151337e8
NC		 3211 TAB (BRABSJCOND, SZ_UNDEF));
3212 }
252b5132 3213 else
bd17c2c3
AM		 3214 add_frag (adds (&opP->disp),
3215 SEXT (offs (&opP->disp)),
cac27205
NC		 3216 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3217 : TAB (BRANCHBW, SZ_UNDEF)));
252b5132
RH		 3218 break;
3219 case 'w':
3220 if (isvar (&opP->disp))
3221 {
151337e8
NC		 3222 /* Check for DBcc instructions. We can relax them,
3223 but only if we have long branches and/or absolute
3224 jumps. */
3225 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3226 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3227 || ! flag_keep_pcrel))
252b5132 3228 {
151337e8 3229 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3230 add_frag (adds (&opP->disp),
3231 SEXT (offs (&opP->disp)),
151337e8
NC		 3232 TAB (DBCCLBR, SZ_UNDEF));
3233 else
bd17c2c3
AM		 3234 add_frag (adds (&opP->disp),
3235 SEXT (offs (&opP->disp)),
151337e8 3236 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3237 break;
3238 }
252b5132
RH		 3239 add_fix ('w', &opP->disp, 1, 0);
3240 }
3241 addword (0);
3242 break;
36759679 3243 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3244 add_fix ('l', &opP->disp, 1, 0);
3245 addword (0);
3246 addword (0);
3247 break;
36759679 3248 case 'c': /* Var size Coprocesssor branches. */
151337e8 3249 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3250 {
252b5132
RH		 3251 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3252 add_fix ('l', &opP->disp, 1, 0);
3253 addword (0);
3254 addword (0);
3255 }
151337e8 3256 else
bd17c2c3
AM		 3257 add_frag (adds (&opP->disp),
3258 SEXT (offs (&opP->disp)),
151337e8 3259 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3260 break;
3261 default:
3262 abort ();
3263 }
3264 break;
3265
36759679 3266 case 'C': /* Ignore it. */
252b5132
RH		 3267 break;
3268
36759679 3269 case 'd': /* JF this is a kludge. */
252b5132 3270 install_operand ('s', opP->reg - ADDR);
3e602632 3271 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3272 if (!issword (tmpreg))
3273 {
3274 as_warn (_("Expression out of range, using 0"));
3275 tmpreg = 0;
3276 }
3277 addword (tmpreg);
3278 break;
3279
3280 case 'D':
3281 install_operand (s[1], opP->reg - DATA);
3282 break;
3283
fd99574b
NC		 3284 case 'e': /* EMAC ACCx, reg/reg. */
3285 install_operand (s[1], opP->reg - ACC);
3286 break;
3287
36759679 3288 case 'E': /* Ignore it. */
6da466c7
ILT		 3289 break;
3290
252b5132
RH		 3291 case 'F':
3292 install_operand (s[1], opP->reg - FP0);
3293 break;
3294
fd99574b
NC		 3295 case 'g': /* EMAC ACCEXTx. */
3296 install_operand (s[1], opP->reg - ACCEXT01);
3297 break;
3298
36759679 3299 case 'G': /* Ignore it. */
6da466c7
ILT		 3300 case 'H':
3301 break;
3302
252b5132
RH		 3303 case 'I':
3304 tmpreg = opP->reg - COP0;
3305 install_operand (s[1], tmpreg);
3306 break;
3307
fd99574b
NC		 3308 case 'i': /* MAC/EMAC scale factor. */
3309 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3310 break;
3311
36759679 3312 case 'J': /* JF foo. */
252b5132
RH		 3313 switch (opP->reg)
3314 {
3315 case SFC:
3316 tmpreg = 0x000;
3317 break;
3318 case DFC:
3319 tmpreg = 0x001;
3320 break;
3321 case CACR:
3322 tmpreg = 0x002;
3323 break;
3324 case TC:
a8e24a56 3325 case ASID:
252b5132
RH		 3326 tmpreg = 0x003;
3327 break;
3e602632 3328 case ACR0:
252b5132
RH		 3329 case ITT0:
3330 tmpreg = 0x004;
3331 break;
3e602632 3332 case ACR1:
252b5132
RH		 3333 case ITT1:
3334 tmpreg = 0x005;
3335 break;
3e602632 3336 case ACR2:
252b5132
RH		 3337 case DTT0:
3338 tmpreg = 0x006;
3339 break;
3e602632 3340 case ACR3:
252b5132
RH		 3341 case DTT1:
3342 tmpreg = 0x007;
3343 break;
3344 case BUSCR:
a8e24a56 3345 case MMUBAR:
252b5132
RH		 3346 tmpreg = 0x008;
3347 break;
0d999f33
MK		 3348 case RGPIOBAR:
3349 tmpreg = 0x009;
3350 break;
3351 case ACR4:
3352 case ACR5:
3353 case ACR6:
3354 case ACR7:
3355 tmpreg = 0x00c + (opP->reg - ACR4);
3356 break;
252b5132
RH		 3357
3358 case USP:
3359 tmpreg = 0x800;
3360 break;
3361 case VBR:
3362 tmpreg = 0x801;
3363 break;
3364 case CAAR:
87298967 3365 case CPUCR:
252b5132
RH		 3366 tmpreg = 0x802;
3367 break;
3368 case MSP:
3369 tmpreg = 0x803;
3370 break;
3371 case ISP:
3372 tmpreg = 0x804;
3373 break;
3374 case MMUSR:
3375 tmpreg = 0x805;
3376 break;
3377 case URP:
3378 tmpreg = 0x806;
3379 break;
3380 case SRP:
3381 tmpreg = 0x807;
3382 break;
3383 case PCR:
3384 tmpreg = 0x808;
3385 break;
3386 case ROMBAR:
a8e24a56 3387 case ROMBAR0:
252b5132
RH		 3388 tmpreg = 0xC00;
3389 break;
3e602632
NC		 3390 case ROMBAR1:
3391 tmpreg = 0xC01;
3392 break;
3393 case FLASHBAR:
252b5132 3394 case RAMBAR0:
78336706 3395 case RAMBAR_ALT:
252b5132
RH		 3396 tmpreg = 0xC04;
3397 break;
3e602632 3398 case RAMBAR:
252b5132
RH		 3399 case RAMBAR1:
3400 tmpreg = 0xC05;
3401 break;
3e602632
NC		 3402 case MPCR:
3403 tmpreg = 0xC0C;
3404 break;
3405 case EDRAMBAR:
3406 tmpreg = 0xC0D;
3407 break;
3408 case MBAR0:
e80e0390 3409 case MBAR2:
3e602632
NC		 3410 case SECMBAR:
3411 tmpreg = 0xC0E;
3412 break;
3413 case MBAR1:
252b5132
RH		 3414 case MBAR:
3415 tmpreg = 0xC0F;
3416 break;
3e602632
NC		 3417 case PCR1U0:
3418 tmpreg = 0xD02;
3419 break;
3420 case PCR1L0:
3421 tmpreg = 0xD03;
3422 break;
3423 case PCR2U0:
3424 tmpreg = 0xD04;
3425 break;
3426 case PCR2L0:
3427 tmpreg = 0xD05;
3428 break;
3429 case PCR3U0:
3430 tmpreg = 0xD06;
3431 break;
3432 case PCR3L0:
3433 tmpreg = 0xD07;
3434 break;
3435 case PCR1L1:
3436 tmpreg = 0xD0A;
3437 break;
3438 case PCR1U1:
3439 tmpreg = 0xD0B;
3440 break;
3441 case PCR2L1:
3442 tmpreg = 0xD0C;
3443 break;
3444 case PCR2U1:
3445 tmpreg = 0xD0D;
3446 break;
3447 case PCR3L1:
3448 tmpreg = 0xD0E;
3449 break;
3450 case PCR3U1:
3451 tmpreg = 0xD0F;
3452 break;
f7ec513b
KH		 3453 case CAC:
3454 tmpreg = 0xFFE;
3455 break;
d0fa1372 3456 case MBO:
f7ec513b
KH		 3457 tmpreg = 0xFFF;
3458 break;
252b5132
RH		 3459 default:
3460 abort ();
3461 }
3462 install_operand (s[1], tmpreg);
3463 break;
3464
3465 case 'k':
3466 tmpreg = get_num (&opP->disp, 55);
3467 install_operand (s[1], tmpreg & 0x7f);
3468 break;
3469
3470 case 'l':
3471 tmpreg = opP->mask;
3472 if (s[1] == 'w')
3473 {
3474 if (tmpreg & 0x7FF0000)
3475 as_bad (_("Floating point register in register list"));
3476 insop (reverse_16_bits (tmpreg), opcode);
3477 }
3478 else
3479 {
3480 if (tmpreg & 0x700FFFF)
3481 as_bad (_("Wrong register in floating-point reglist"));
3482 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3483 }
3484 break;
3485
3486 case 'L':
3487 tmpreg = opP->mask;
3488 if (s[1] == 'w')
3489 {
3490 if (tmpreg & 0x7FF0000)
3491 as_bad (_("Floating point register in register list"));
3492 insop (tmpreg, opcode);
3493 }
3494 else if (s[1] == '8')
3495 {
3496 if (tmpreg & 0x0FFFFFF)
3497 as_bad (_("incorrect register in reglist"));
3498 install_operand (s[1], tmpreg >> 24);
3499 }
3500 else
3501 {
3502 if (tmpreg & 0x700FFFF)
3503 as_bad (_("wrong register in floating-point reglist"));
3504 else
3505 install_operand (s[1], tmpreg >> 16);
3506 }
3507 break;
3508
3509 case 'M':
3510 install_operand (s[1], get_num (&opP->disp, 60));
3511 break;
3512
3513 case 'O':
3514 tmpreg = ((opP->mode == DREG)
8fce3f5e 3515 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3516 : (get_num (&opP->disp, 40) & 0x1F));
3517 install_operand (s[1], tmpreg);
3518 break;
3519
3520 case 'Q':
3521 tmpreg = get_num (&opP->disp, 10);
3522 if (tmpreg == 8)
3523 tmpreg = 0;
3524 install_operand (s[1], tmpreg);
3525 break;
3526
3527 case 'R':
3528 /* This depends on the fact that ADDR registers are eight
3529 more than their corresponding DATA regs, so the result
36759679 3530 will have the ADDR_REG bit set. */
252b5132
RH		 3531 install_operand (s[1], opP->reg - DATA);
3532 break;
3533
3534 case 'r':
3535 if (opP->mode == AINDR)
3536 install_operand (s[1], opP->reg - DATA);
3537 else
3538 install_operand (s[1], opP->index.reg - DATA);
3539 break;
3540
3541 case 's':
3542 if (opP->reg == FPI)
3543 tmpreg = 0x1;
3544 else if (opP->reg == FPS)
3545 tmpreg = 0x2;
3546 else if (opP->reg == FPC)
3547 tmpreg = 0x4;
3548 else
3549 abort ();
3550 install_operand (s[1], tmpreg);
3551 break;
3552
36759679 3553 case 'S': /* Ignore it. */
252b5132
RH		 3554 break;
3555
3556 case 'T':
3557 install_operand (s[1], get_num (&opP->disp, 30));
3558 break;
3559
36759679 3560 case 'U': /* Ignore it. */
252b5132
RH		 3561 break;
3562
3563 case 'c':
3564 switch (opP->reg)
3565 {
3566 case NC:
3567 tmpreg = 0;
3568 break;
3569 case DC:
3570 tmpreg = 1;
3571 break;
3572 case IC:
3573 tmpreg = 2;
3574 break;
3575 case BC:
3576 tmpreg = 3;
3577 break;
3578 default:
3579 as_fatal (_("failed sanity check"));
36759679 3580 } /* switch on cache token. */
252b5132
RH		 3581 install_operand (s[1], tmpreg);
3582 break;
3583#ifndef NO_68851
92774660 3584 /* JF: These are out of order, I fear. */
252b5132
RH		 3585 case 'f':
3586 switch (opP->reg)
3587 {
3588 case SFC:
3589 tmpreg = 0;
3590 break;
3591 case DFC:
3592 tmpreg = 1;
3593 break;
3594 default:
3595 abort ();
3596 }
3597 install_operand (s[1], tmpreg);
3598 break;
3599
3600 case '0':
3601 case '1':
3602 case '2':
3603 switch (opP->reg)
3604 {
3605 case TC:
3606 tmpreg = 0;
3607 break;
3608 case CAL:
3609 tmpreg = 4;
3610 break;
3611 case VAL:
3612 tmpreg = 5;
3613 break;
3614 case SCC:
3615 tmpreg = 6;
3616 break;
3617 case AC:
3618 tmpreg = 7;
3619 break;
3620 default:
3621 abort ();
3622 }
3623 install_operand (s[1], tmpreg);
3624 break;
3625
3626 case 'V':
3627 if (opP->reg == VAL)
3628 break;
3629 abort ();
3630
3631 case 'W':
3632 switch (opP->reg)
3633 {
3634 case DRP:
3635 tmpreg = 1;
3636 break;
3637 case SRP:
3638 tmpreg = 2;
3639 break;
3640 case CRP:
3641 tmpreg = 3;
3642 break;
3643 default:
3644 abort ();
3645 }
3646 install_operand (s[1], tmpreg);
3647 break;
3648
3649 case 'X':
3650 switch (opP->reg)
3651 {
3652 case BAD:
3653 case BAD + 1:
3654 case BAD + 2:
3655 case BAD + 3:
3656 case BAD + 4:
3657 case BAD + 5:
3658 case BAD + 6:
3659 case BAD + 7:
3660 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3661 break;
3662
3663 case BAC:
3664 case BAC + 1:
3665 case BAC + 2:
3666 case BAC + 3:
3667 case BAC + 4:
3668 case BAC + 5:
3669 case BAC + 6:
3670 case BAC + 7:
3671 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3672 break;
3673
3674 default:
3675 abort ();
3676 }
3677 install_operand (s[1], tmpreg);
3678 break;
3679 case 'Y':
3680 know (opP->reg == PSR);
3681 break;
3682 case 'Z':
3683 know (opP->reg == PCSR);
3684 break;
3685#endif /* m68851 */
3686 case '3':
3687 switch (opP->reg)
3688 {
3689 case TT0:
3690 tmpreg = 2;
3691 break;
3692 case TT1:
3693 tmpreg = 3;
3694 break;
3695 default:
3696 abort ();
3697 }
3698 install_operand (s[1], tmpreg);
3699 break;
3700 case 't':
3701 tmpreg = get_num (&opP->disp, 20);
3702 install_operand (s[1], tmpreg);
3703 break;
36759679 3704 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3705 if (isvar (&opP->disp))
3706 add_fix ('l', &opP->disp, 0, 0);
3e602632 3707 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3708 addword (tmpreg >> 16);
3709 addword (tmpreg & 0xFFFF);
3710 break;
6da466c7
ILT		 3711 case 'u':
3712 install_operand (s[1], opP->reg - DATA0L);
3713 opP->reg -= (DATA0L);
36759679 3714 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3715 break;
3e602632
NC		 3716 case 'x':
3717 tmpreg = get_num (&opP->disp, 80);
3718 if (tmpreg == -1)
3719 tmpreg = 0;
3720 install_operand (s[1], tmpreg);
3721 break;
afa2158f
NS		 3722 case 'j':
3723 tmpreg = get_num (&opP->disp, 10);
3724 install_operand (s[1], tmpreg - 1);
3725 break;
3726 case 'K':
3727 tmpreg = get_num (&opP->disp, 65);
3728 install_operand (s[1], tmpreg);
3729 break;
252b5132
RH		 3730 default:
3731 abort ();
3732 }
3733 }
3734
3735 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3736 instruction, ready to be emitted. . . */
252b5132
RH		 3737}
3738
3739static int
31302357 3740reverse_16_bits (int in)
252b5132
RH		 3741{
3742 int out = 0;
3743 int n;
3744
3745 static int mask[16] =
3746 {
3747 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3748 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3749 };
3750 for (n = 0; n < 16; n++)
3751 {
3752 if (in & mask[n])
3753 out |= mask[15 - n];
3754 }
3755 return out;
3756} /* reverse_16_bits() */
3757
3758static int
31302357 3759reverse_8_bits (int in)
252b5132
RH		 3760{
3761 int out = 0;
3762 int n;
3763
3764 static int mask[8] =
3765 {
3766 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3767 };
3768
3769 for (n = 0; n < 8; n++)
3770 {
3771 if (in & mask[n])
3772 out |= mask[7 - n];
3773 }
3774 return out;
3775} /* reverse_8_bits() */
3776
cac27205
NC		 3777/* Cause an extra frag to be generated here, inserting up to
3778 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3779 generated; its primary type is rs_machine_dependent.
252b5132
RH		 3780
3781 The TYPE parameter is also used by md_convert_frag_1 and
3782 md_estimate_size_before_relax. The appropriate type of fixup will
3783 be emitted by md_convert_frag_1.
3784
3785 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3786static void
31302357 3787install_operand (int mode, int val)
252b5132
RH		 3788{
3789 switch (mode)
3790 {
3791 case 's':
36759679 3792 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3793 break;
3794 case 'd':
3795 the_ins.opcode[0] |= val << 9;
3796 break;
afa2158f
NS		 3797 case 'E':
3798 the_ins.opcode[1] |= val << 9;
3799 break;
252b5132
RH		 3800 case '1':
3801 the_ins.opcode[1] |= val << 12;
3802 break;
3803 case '2':
3804 the_ins.opcode[1] |= val << 6;
3805 break;
3806 case '3':
3807 the_ins.opcode[1] |= val;
3808 break;
3809 case '4':
3810 the_ins.opcode[2] |= val << 12;
3811 break;
3812 case '5':
3813 the_ins.opcode[2] |= val << 6;
3814 break;
3815 case '6':
3816 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3817 three words long! */
3818 the_ins.numo++;
3819 the_ins.opcode[2] |= val;
3820 break;
3821 case '7':
3822 the_ins.opcode[1] |= val << 7;
3823 break;
3824 case '8':
3825 the_ins.opcode[1] |= val << 10;
3826 break;
3827#ifndef NO_68851
3828 case '9':
3829 the_ins.opcode[1] |= val << 5;
3830 break;
3831#endif
3832
3833 case 't':
3834 the_ins.opcode[1] |= (val << 10) | (val << 7);
3835 break;
3836 case 'D':
3837 the_ins.opcode[1] |= (val << 12) | val;
3838 break;
3839 case 'g':
3840 the_ins.opcode[0] |= val = 0xff;
3841 break;
3842 case 'i':
3843 the_ins.opcode[0] |= val << 9;
3844 break;
3845 case 'C':
3846 the_ins.opcode[1] |= val;
3847 break;
3848 case 'j':
3849 the_ins.opcode[1] |= val;
36759679 3850 the_ins.numo++; /* What a hack. */
252b5132
RH		 3851 break;
3852 case 'k':
3853 the_ins.opcode[1] |= val << 4;
3854 break;
3855 case 'b':
3856 case 'w':
3857 case 'W':
3858 case 'l':
3859 break;
3860 case 'e':
3861 the_ins.opcode[0] |= (val << 6);
3862 break;
3863 case 'L':
3864 the_ins.opcode[1] = (val >> 16);
3865 the_ins.opcode[2] = val & 0xffff;
3866 break;
6da466c7
ILT		 3867 case 'm':
3868 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3869 the_ins.opcode[0] |= ((val & 0x7) << 9);
3870 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3871 break;
fd99574b 3872 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3873 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3874 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3875 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3876 break;
fd99574b 3877 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3878 the_ins.opcode[1] |= val << 12;
3879 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3880 break;
fd99574b 3881 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3882 the_ins.opcode[0] |= (val & 0xF);
3883 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3884 break;
fd99574b 3885 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3886 the_ins.opcode[1] |= (val & 0xF);
3887 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3888 break;
3889 case 'h':
3890 the_ins.opcode[1] |= ((val != 1) << 10);
3891 break;
fd99574b
NC		 3892 case 'F':
3893 the_ins.opcode[0] |= ((val & 0x3) << 9);
3894 break;
3895 case 'f':
3896 the_ins.opcode[0] |= ((val & 0x3) << 0);
3897 break;
be8c092b 3898 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3899 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3900 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3901 break;
be8c092b 3902 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3903 the_ins.opcode[0] |= ((val & 0x1) << 7);
3904 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3905 break;
3906 case 'I':
3907 the_ins.opcode[1] |= ((val & 0x3) << 9);
3908 break;
3909 case ']':
3910 the_ins.opcode[0] |= (val & 0x1) <<10;
3911 break;
252b5132
RH		 3912 case 'c':
3913 default:
3914 as_fatal (_("failed sanity check."));
3915 }
6b6e92f4 3916}
252b5132
RH		 3917
3918static void
31302357 3919install_gen_operand (int mode, int val)
252b5132
RH		 3920{
3921 switch (mode)
3922 {
fd99574b
NC		 3923 case '/': /* Special for mask loads for mac/msac insns with
3924 possible mask; trailing_ampersend set in bit 8. */
3925 the_ins.opcode[0] |= (val & 0x3f);
3926 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3927 break;
252b5132
RH		 3928 case 's':
3929 the_ins.opcode[0] |= val;
3930 break;
3931 case 'd':
3932 /* This is a kludge!!! */
3933 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3934 break;
3935 case 'b':
3936 case 'w':
3937 case 'l':
3938 case 'f':
3939 case 'F':
3940 case 'x':
3941 case 'p':
3942 the_ins.opcode[0] |= val;
3943 break;
36759679 3944 /* more stuff goes here. */
252b5132
RH		 3945 default:
3946 as_fatal (_("failed sanity check."));
3947 }
6b6e92f4 3948}
252b5132 3949
6b6e92f4
NC		 3950/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3951 then deal with the bitfield hack. */
252b5132
RH		 3952
3953static char *
31302357 3954crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3955{
3956 register int parens;
3957 register int c;
3958 register char *beg_str;
3959 int inquote = 0;
3960
3961 if (!str)
3962 {
3963 return str;
3964 }
3965 beg_str = str;
3966 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3967 {
3968 if (! inquote)
3969 {
3970 if (*str == '(')
3971 parens++;
3972 else if (*str == ')')
3973 {
3974 if (!parens)
36759679 3975 { /* ERROR. */
252b5132
RH		 3976 opP->error = _("Extra )");
3977 return str;
3978 }
3979 --parens;
3980 }
3981 }
3982 if (flag_mri && *str == '\'')
3983 inquote = ! inquote;
3984 }
3985 if (!*str && parens)
36759679 3986 { /* ERROR. */
252b5132
RH		 3987 opP->error = _("Missing )");
3988 return str;
3989 }
3990 c = *str;
3991 *str = '\0';
3992 if (m68k_ip_op (beg_str, opP) != 0)
3993 {
3994 *str = c;
3995 return str;
3996 }
3997 *str = c;
3998 if (c == '}')
36759679 3999 c = *++str; /* JF bitfield hack. */
252b5132
RH		 4000 if (c)
4001 {
4002 c = *++str;
4003 if (!c)
4004 as_bad (_("Missing operand"));
4005 }
4006
4007 /* Detect MRI REG symbols and convert them to REGLSTs. */
4008 if (opP->mode == CONTROL && (int)opP->reg < 0)
4009 {
4010 opP->mode = REGLST;
4011 opP->mask = ~(int)opP->reg;
4012 opP->reg = 0;
4013 }
4014
4015 return str;
4016}
4017
4018/* This is the guts of the machine-dependent assembler. STR points to a
4019 machine dependent instruction. This function is supposed to emit
4020 the frags/bytes it assembles to.
4021 */
4022
4023static void
31302357 4024insert_reg (const char *regname, int regnum)
252b5132
RH		 4025{
4026 char buf[100];
4027 int i;
4028
4029#ifdef REGISTER_PREFIX
4030 if (!flag_reg_prefix_optional)
4031 {
4032 buf[0] = REGISTER_PREFIX;
4033 strcpy (buf + 1, regname);
4034 regname = buf;
4035 }
4036#endif
4037
4038 symbol_table_insert (symbol_new (regname, reg_section, regnum,
4039 &zero_address_frag));
4040
4041 for (i = 0; regname[i]; i++)
3882b010 4042 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 4043 buf[i] = '\0';
4044
4045 symbol_table_insert (symbol_new (buf, reg_section, regnum,
4046 &zero_address_frag));
4047}
4048
4049struct init_entry
4050 {
4051 const char *name;
4052 int number;
4053 };
4054
4055static const struct init_entry init_table[] =
4056{
4057 { "d0", DATA0 },
4058 { "d1", DATA1 },
4059 { "d2", DATA2 },
4060 { "d3", DATA3 },
4061 { "d4", DATA4 },
4062 { "d5", DATA5 },
4063 { "d6", DATA6 },
4064 { "d7", DATA7 },
4065 { "a0", ADDR0 },
4066 { "a1", ADDR1 },
4067 { "a2", ADDR2 },
4068 { "a3", ADDR3 },
4069 { "a4", ADDR4 },
4070 { "a5", ADDR5 },
4071 { "a6", ADDR6 },
4072 { "fp", ADDR6 },
4073 { "a7", ADDR7 },
4074 { "sp", ADDR7 },
4075 { "ssp", ADDR7 },
4076 { "fp0", FP0 },
4077 { "fp1", FP1 },
4078 { "fp2", FP2 },
4079 { "fp3", FP3 },
4080 { "fp4", FP4 },
4081 { "fp5", FP5 },
4082 { "fp6", FP6 },
4083 { "fp7", FP7 },
4084 { "fpi", FPI },
4085 { "fpiar", FPI },
4086 { "fpc", FPI },
4087 { "fps", FPS },
4088 { "fpsr", FPS },
4089 { "fpc", FPC },
4090 { "fpcr", FPC },
4091 { "control", FPC },
4092 { "status", FPS },
4093 { "iaddr", FPI },
4094
4095 { "cop0", COP0 },
4096 { "cop1", COP1 },
4097 { "cop2", COP2 },
4098 { "cop3", COP3 },
4099 { "cop4", COP4 },
4100 { "cop5", COP5 },
4101 { "cop6", COP6 },
4102 { "cop7", COP7 },
4103 { "pc", PC },
4104 { "zpc", ZPC },
4105 { "sr", SR },
4106
4107 { "ccr", CCR },
4108 { "cc", CCR },
4109
6da466c7 4110 { "acc", ACC },
fd99574b
NC		 4111 { "acc0", ACC },
4112 { "acc1", ACC1 },
4113 { "acc2", ACC2 },
4114 { "acc3", ACC3 },
4115 { "accext01", ACCEXT01 },
4116 { "accext23", ACCEXT23 },
6da466c7
ILT		 4117 { "macsr", MACSR },
4118 { "mask", MASK },
4119
36759679
NC		 4120 /* Control registers. */
4121 { "sfc", SFC }, /* Source Function Code. */
252b5132 4122 { "sfcr", SFC },
36759679 4123 { "dfc", DFC }, /* Destination Function Code. */
252b5132 4124 { "dfcr", DFC },
36759679
NC		 4125 { "cacr", CACR }, /* Cache Control Register. */
4126 { "caar", CAAR }, /* Cache Address Register. */
87298967 4127 { "cpucr", CPUCR }, /* CPU Control Register. */
252b5132 4128
36759679
NC		 4129 { "usp", USP }, /* User Stack Pointer. */
4130 { "vbr", VBR }, /* Vector Base Register. */
4131 { "msp", MSP }, /* Master Stack Pointer. */
4132 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 4133
36759679
NC		 4134 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4135 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4136 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4137 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 4138
4139 /* 68ec040 versions of same */
36759679
NC		 4140 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4141 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4142 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4143 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 4144
a8e24a56 4145 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 4146 manual indicated that the order is 2,3,0,1, but Ken Rose
4147 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 4148 { "acr0", ACR0 }, /* Access Control Unit 0. */
4149 { "acr1", ACR1 }, /* Access Control Unit 1. */
4150 { "acr2", ACR2 }, /* Access Control Unit 2. */
4151 { "acr3", ACR3 }, /* Access Control Unit 3. */
0d999f33
MK		 4152 { "acr4", ACR4 }, /* Access Control Unit 4. */
4153 { "acr5", ACR5 }, /* Access Control Unit 5. */
4154 { "acr6", ACR6 }, /* Access Control Unit 6. */
4155 { "acr7", ACR7 }, /* Access Control Unit 7. */
252b5132 4156
36759679 4157 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 4158 { "tcr", TC },
a8e24a56 4159 { "asid", ASID },
252b5132 4160
36759679
NC		 4161 { "mmusr", MMUSR }, /* MMU Status Register. */
4162 { "srp", SRP }, /* User Root Pointer. */
4163 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 4164
4165 { "buscr", BUSCR },
a8e24a56 4166 { "mmubar", MMUBAR },
252b5132
RH		 4167 { "pcr", PCR },
4168
36759679
NC		 4169 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4170 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4171 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4172 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 4173
4174 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4175 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 4176 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 4177 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4178 { "mpcr", MPCR }, /* mcfv4e registers. */
4179 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4180 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4181 { "asid", TC }, /* mcfv4e registers. */
4182 { "mmubar", BUSCR }, /* mcfv4e registers. */
4183 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4184 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4185 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4186 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4187 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4188 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4189 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4190 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4191 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4192 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4193 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4194 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4195
4196 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4197 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 4198
4199 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b 4200
0d999f33
MK		 4201 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4202
f7ec513b 4203 { "cac", CAC }, /* fido registers. */
d0fa1372
KH		 4204 { "mbb", MBO }, /* fido registers (obsolete). */
4205 { "mbo", MBO }, /* fido registers. */
36759679 4206 /* End of control registers. */
252b5132
RH		 4207
4208 { "ac", AC },
4209 { "bc", BC },
4210 { "cal", CAL },
4211 { "crp", CRP },
4212 { "drp", DRP },
4213 { "pcsr", PCSR },
4214 { "psr", PSR },
4215 { "scc", SCC },
4216 { "val", VAL },
4217 { "bad0", BAD0 },
4218 { "bad1", BAD1 },
4219 { "bad2", BAD2 },
4220 { "bad3", BAD3 },
4221 { "bad4", BAD4 },
4222 { "bad5", BAD5 },
4223 { "bad6", BAD6 },
4224 { "bad7", BAD7 },
4225 { "bac0", BAC0 },
4226 { "bac1", BAC1 },
4227 { "bac2", BAC2 },
4228 { "bac3", BAC3 },
4229 { "bac4", BAC4 },
4230 { "bac5", BAC5 },
4231 { "bac6", BAC6 },
4232 { "bac7", BAC7 },
4233
4234 { "ic", IC },
4235 { "dc", DC },
4236 { "nc", NC },
4237
4238 { "tt0", TT0 },
4239 { "tt1", TT1 },
36759679 4240 /* 68ec030 versions of same. */
252b5132
RH		 4241 { "ac0", TT0 },
4242 { "ac1", TT1 },
36759679 4243 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 4244 { "acusr", PSR },
4245
4246 /* Suppressed data and address registers. */
4247 { "zd0", ZDATA0 },
4248 { "zd1", ZDATA1 },
4249 { "zd2", ZDATA2 },
4250 { "zd3", ZDATA3 },
4251 { "zd4", ZDATA4 },
4252 { "zd5", ZDATA5 },
4253 { "zd6", ZDATA6 },
4254 { "zd7", ZDATA7 },
4255 { "za0", ZADDR0 },
4256 { "za1", ZADDR1 },
4257 { "za2", ZADDR2 },
4258 { "za3", ZADDR3 },
4259 { "za4", ZADDR4 },
4260 { "za5", ZADDR5 },
4261 { "za6", ZADDR6 },
4262 { "za7", ZADDR7 },
4263
92774660 4264 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4265 { "d0l", DATA0L },
4266 { "d1l", DATA1L },
4267 { "d2l", DATA2L },
4268 { "d3l", DATA3L },
4269 { "d4l", DATA4L },
4270 { "d5l", DATA5L },
4271 { "d6l", DATA6L },
4272 { "d7l", DATA7L },
4273
4274 { "a0l", ADDR0L },
4275 { "a1l", ADDR1L },
4276 { "a2l", ADDR2L },
4277 { "a3l", ADDR3L },
4278 { "a4l", ADDR4L },
4279 { "a5l", ADDR5L },
4280 { "a6l", ADDR6L },
4281 { "a7l", ADDR7L },
4282
4283 { "d0u", DATA0U },
4284 { "d1u", DATA1U },
4285 { "d2u", DATA2U },
4286 { "d3u", DATA3U },
4287 { "d4u", DATA4U },
4288 { "d5u", DATA5U },
4289 { "d6u", DATA6U },
4290 { "d7u", DATA7U },
4291
4292 { "a0u", ADDR0U },
4293 { "a1u", ADDR1U },
4294 { "a2u", ADDR2U },
4295 { "a3u", ADDR3U },
4296 { "a4u", ADDR4U },
4297 { "a5u", ADDR5U },
4298 { "a6u", ADDR6U },
4299 { "a7u", ADDR7U },
4300
252b5132
RH		 4301 { 0, 0 }
4302};
4303
4304static void
31302357 4305init_regtable (void)
252b5132
RH		 4306{
4307 int i;
4308 for (i = 0; init_table[i].name; i++)
4309 insert_reg (init_table[i].name, init_table[i].number);
4310}
4311
252b5132 4312void
31302357 4313md_assemble (char *str)
252b5132
RH		 4314{
4315 const char *er;
4316 short *fromP;
4317 char *toP = NULL;
4318 int m, n = 0;
4319 char *to_beg_P;
4320 int shorts_this_frag;
4321 fixS *fixP;
4322
266abb8f
NS		 4323 if (!selected_cpu && !selected_arch)
4324 {
4325 /* We've not selected an architecture yet. Set the default
4326 now. We do this lazily so that an initial .cpu or .arch directive
4327 can specify. */
4328 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4329 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4330 }
4331 if (!initialized)
4332 m68k_init_arch ();
4333
252b5132
RH		 4334 /* In MRI mode, the instruction and operands are separated by a
4335 space. Anything following the operands is a comment. The label
4336 has already been removed. */
4337 if (flag_mri)
4338 {
4339 char *s;
4340 int fields = 0;
4341 int infield = 0;
4342 int inquote = 0;
4343
4344 for (s = str; *s != '\0'; s++)
4345 {
4346 if ((*s == ' ' || *s == '\t') && ! inquote)
4347 {
4348 if (infield)
4349 {
4350 ++fields;
4351 if (fields >= 2)
4352 {
4353 *s = '\0';
4354 break;
4355 }
4356 infield = 0;
4357 }
4358 }
4359 else
4360 {
4361 if (! infield)
4362 infield = 1;
4363 if (*s == '\'')
4364 inquote = ! inquote;
4365 }
4366 }
4367 }
4368
31302357 4369 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4370 m68k_ip (str);
4371 er = the_ins.error;
4372 if (!er)
4373 {
4374 for (n = 0; n < the_ins.numargs; n++)
4375 if (the_ins.operands[n].error)
4376 {
4377 er = the_ins.operands[n].error;
4378 break;
4379 }
4380 }
4381 if (er)
4382 {
4383 as_bad (_("%s -- statement `%s' ignored"), er, str);
4384 return;
4385 }
4386
4387 /* If there is a current label, record that it marks an instruction. */
4388 if (current_label != NULL)
4389 {
4390 current_label->text = 1;
4391 current_label = NULL;
4392 }
4393
f27a3839
AS		 4394#ifdef OBJ_ELF
4395 /* Tie dwarf2 debug info to the address at the start of the insn. */
4396 dwarf2_emit_insn (0);
4397#endif
4398
252b5132
RH		 4399 if (the_ins.nfrag == 0)
4400 {
36759679 4401 /* No frag hacking involved; just put it out. */
252b5132
RH		 4402 toP = frag_more (2 * the_ins.numo);
4403 fromP = &the_ins.opcode[0];
4404 for (m = the_ins.numo; m; --m)
4405 {
4406 md_number_to_chars (toP, (long) (*fromP), 2);
4407 toP += 2;
4408 fromP++;
4409 }
36759679 4410 /* Put out symbol-dependent info. */
252b5132
RH		 4411 for (m = 0; m < the_ins.nrel; m++)
4412 {
4413 switch (the_ins.reloc[m].wid)
4414 {
4415 case 'B':
4416 n = 1;
4417 break;
4418 case 'b':
4419 n = 1;
4420 break;
4421 case '3':
4422 n = 1;
4423 break;
4424 case 'w':
4425 case 'W':
4426 n = 2;
4427 break;
4428 case 'l':
4429 n = 4;
4430 break;
4431 default:
4432 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4433 the_ins.reloc[m].wid);
4434 }
4435
4436 fixP = fix_new_exp (frag_now,
4437 ((toP - frag_now->fr_literal)
4438 - the_ins.numo * 2 + the_ins.reloc[m].n),
4439 n,
4440 &the_ins.reloc[m].exp,
4441 the_ins.reloc[m].pcrel,
4442 get_reloc_code (n, the_ins.reloc[m].pcrel,
4443 the_ins.reloc[m].pic_reloc));
4444 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4445 if (the_ins.reloc[m].wid == 'B')
4446 fixP->fx_signed = 1;
4447 }
4448 return;
4449 }
4450
36759679 4451 /* There's some frag hacking. */
fbe572f9
AM		 4452 {
4453 /* Calculate the max frag size. */
4454 int wid;
4455
4456 wid = 2 * the_ins.fragb[0].fragoff;
4457 for (n = 1; n < the_ins.nfrag; n++)
4458 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4459 /* frag_var part. */
cac27205 4460 wid += FRAG_VAR_SIZE;
fbe572f9
AM		 4461 /* Make sure the whole insn fits in one chunk, in particular that
4462 the var part is attached, as we access one byte before the
4463 variable frag for byte branches. */
4464 frag_grow (wid);
4465 }
4466
252b5132
RH		 4467 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4468 {
4469 int wid;
4470
4471 if (n == 0)
4472 wid = 2 * the_ins.fragb[n].fragoff;
4473 else
4474 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4475 toP = frag_more (wid);
4476 to_beg_P = toP;
4477 shorts_this_frag = 0;
4478 for (m = wid / 2; m; --m)
4479 {
4480 md_number_to_chars (toP, (long) (*fromP), 2);
4481 toP += 2;
4482 fromP++;
4483 shorts_this_frag++;
4484 }
4485 for (m = 0; m < the_ins.nrel; m++)
4486 {
4487 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4488 {
4489 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4490 break;
4491 }
4492 wid = the_ins.reloc[m].wid;
4493 if (wid == 0)
4494 continue;
4495 the_ins.reloc[m].wid = 0;
4496 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4497
4498 fixP = fix_new_exp (frag_now,
4499 ((toP - frag_now->fr_literal)
4500 - the_ins.numo * 2 + the_ins.reloc[m].n),
4501 wid,
4502 &the_ins.reloc[m].exp,
4503 the_ins.reloc[m].pcrel,
4504 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4505 the_ins.reloc[m].pic_reloc));
4506 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4507 }
cac27205 4508 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
252b5132
RH		 4509 (relax_substateT) (the_ins.fragb[n].fragty),
4510 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4511 }
4512 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4513 shorts_this_frag = 0;
4514 if (n)
4515 {
055d1eb0 4516 toP = frag_more (n * 2);
252b5132
RH		 4517 while (n--)
4518 {
4519 md_number_to_chars (toP, (long) (*fromP), 2);
4520 toP += 2;
4521 fromP++;
4522 shorts_this_frag++;
4523 }
4524 }
4525 for (m = 0; m < the_ins.nrel; m++)
4526 {
4527 int wid;
4528
4529 wid = the_ins.reloc[m].wid;
4530 if (wid == 0)
4531 continue;
4532 the_ins.reloc[m].wid = 0;
4533 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4534
4535 fixP = fix_new_exp (frag_now,
4536 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4537 - shorts_this_frag * 2),
4538 wid,
4539 &the_ins.reloc[m].exp,
4540 the_ins.reloc[m].pcrel,
4541 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4542 the_ins.reloc[m].pic_reloc));
4543 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4544 }
4545}
4546
60fed2d3
NC		 4547/* Comparison function used by qsort to rank the opcode entries by name. */
4548
4549static int
4550m68k_compare_opcode (const void * v1, const void * v2)
4551{
4552 struct m68k_opcode * op1, * op2;
4553 int ret;
4554
03b13e59
NC		 4555 if (v1 == v2)
4556 return 0;
4557
60fed2d3
NC		 4558 op1 = *(struct m68k_opcode **) v1;
4559 op2 = *(struct m68k_opcode **) v2;
4560
4561 /* Compare the two names. If different, return the comparison.
4562 If the same, return the order they are in the opcode table. */
4563 ret = strcmp (op1->name, op2->name);
4564 if (ret)
4565 return ret;
4566 if (op1 < op2)
4567 return -1;
03b13e59 4568 return 1;
60fed2d3
NC		 4569}
4570
252b5132 4571void
60fed2d3 4572md_begin (void)
252b5132 4573{
60fed2d3
NC		 4574 const struct m68k_opcode *ins;
4575 struct m68k_incant *hack, *slak;
4576 const char *retval = 0; /* Empty string, or error msg text. */
4577 int i;
4578
4579 /* Set up hash tables with 68000 instructions.
4580 similar to what the vax assembler does. */
252b5132
RH		 4581 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4582 a copy of it at runtime, adding in the information we want but isn't
4583 there. I think it'd be better to have an awk script hack the table
4584 at compile time. Or even just xstr the table and use it as-is. But
4585 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4586 names. */
4587
252b5132
RH		 4588 if (flag_mri)
4589 {
4590 flag_reg_prefix_optional = 1;
4591 m68k_abspcadd = 1;
4592 if (! m68k_rel32_from_cmdline)
4593 m68k_rel32 = 0;
4594 }
4595
60fed2d3
NC		 4596 /* First sort the opcode table into alphabetical order to seperate
4597 the order that the assembler wants to see the opcodes from the
4598 order that the disassembler wants to see them. */
4599 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4600 if (!m68k_sorted_opcodes)
4601 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4602 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4603
4604 for (i = m68k_numopcodes; i--;)
4605 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4606
4607 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4608 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4609
252b5132
RH		 4610 op_hash = hash_new ();
4611
4612 obstack_begin (&robyn, 4000);
4613 for (i = 0; i < m68k_numopcodes; i++)
4614 {
78aff5a5 4615 hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4616 do
4617 {
60fed2d3
NC		 4618 ins = m68k_sorted_opcodes[i];
4619
afa2158f
NS		 4620 /* We must enter all insns into the table, because .arch and
4621 .cpu directives can change things. */
252b5132 4622 slak->m_operands = ins->args;
252b5132
RH		 4623 slak->m_arch = ins->arch;
4624 slak->m_opcode = ins->opcode;
afa2158f
NS		 4625
4626 /* In most cases we can determine the number of opcode words
4627 by checking the second word of the mask. Unfortunately
4628 some instructions have 2 opcode words, but no fixed bits
4629 in the second word. A leading dot in the operands
4630 string also indicates 2 opcodes. */
4631 if (*slak->m_operands == '.')
4632 {
4633 slak->m_operands++;
4634 slak->m_codenum = 2;
4635 }
4636 else if (ins->match & 0xffffL)
4637 slak->m_codenum = 2;
4638 else
4639 slak->m_codenum = 1;
4640 slak->m_opnum = strlen (slak->m_operands) / 2;
4641
252b5132 4642 if (i + 1 != m68k_numopcodes
60fed2d3 4643 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4644 {
60fed2d3 4645 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4646 i++;
4647 }
4648 else
4649 slak->m_next = 0;
4650 slak = slak->m_next;
4651 }
4652 while (slak);
4653
4654 retval = hash_insert (op_hash, ins->name, (char *) hack);
4655 if (retval)
4656 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4657 }
4658
4659 for (i = 0; i < m68k_numaliases; i++)
4660 {
4661 const char *name = m68k_opcode_aliases[i].primary;
4662 const char *alias = m68k_opcode_aliases[i].alias;
5a49b8ac 4663 void *val = hash_find (op_hash, name);
60fed2d3 4664
252b5132
RH		 4665 if (!val)
4666 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4667 retval = hash_insert (op_hash, alias, val);
4668 if (retval)
4669 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4670 }
4671
4672 /* In MRI mode, all unsized branches are variable sized. Normally,
4673 they are word sized. */
4674 if (flag_mri)
4675 {
4676 static struct m68k_opcode_alias mri_aliases[] =
4677 {
4678 { "bhi", "jhi", },
4679 { "bls", "jls", },
4680 { "bcc", "jcc", },
4681 { "bcs", "jcs", },
4682 { "bne", "jne", },
4683 { "beq", "jeq", },
4684 { "bvc", "jvc", },
4685 { "bvs", "jvs", },
4686 { "bpl", "jpl", },
4687 { "bmi", "jmi", },
4688 { "bge", "jge", },
4689 { "blt", "jlt", },
4690 { "bgt", "jgt", },
4691 { "ble", "jle", },
4692 { "bra", "jra", },
4693 { "bsr", "jbsr", },
4694 };
4695
8fce3f5e
AM		 4696 for (i = 0;
4697 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4698 i++)
252b5132
RH		 4699 {
4700 const char *name = mri_aliases[i].primary;
4701 const char *alias = mri_aliases[i].alias;
5a49b8ac 4702 void *val = hash_find (op_hash, name);
60fed2d3 4703
252b5132
RH		 4704 if (!val)
4705 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4706 retval = hash_jam (op_hash, alias, val);
4707 if (retval)
4708 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4709 }
4710 }
4711
8fce3f5e 4712 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4713 {
4714 notend_table[i] = 0;
4715 alt_notend_table[i] = 0;
4716 }
60fed2d3 4717
252b5132
RH		 4718 notend_table[','] = 1;
4719 notend_table['{'] = 1;
4720 notend_table['}'] = 1;
4721 alt_notend_table['a'] = 1;
4722 alt_notend_table['A'] = 1;
4723 alt_notend_table['d'] = 1;
4724 alt_notend_table['D'] = 1;
4725 alt_notend_table['#'] = 1;
4726 alt_notend_table['&'] = 1;
4727 alt_notend_table['f'] = 1;
4728 alt_notend_table['F'] = 1;
4729#ifdef REGISTER_PREFIX
4730 alt_notend_table[REGISTER_PREFIX] = 1;
4731#endif
4732
4733 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4734 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4735 alt_notend_table['('] = 1;
4736
4737 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4738 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4739 alt_notend_table['@'] = 1;
4740
4741 /* We need to put digits in alt_notend_table to handle
60fed2d3 4742 bfextu %d0{24:1},%d0 */
252b5132
RH		 4743 alt_notend_table['0'] = 1;
4744 alt_notend_table['1'] = 1;
4745 alt_notend_table['2'] = 1;
4746 alt_notend_table['3'] = 1;
4747 alt_notend_table['4'] = 1;
4748 alt_notend_table['5'] = 1;
4749 alt_notend_table['6'] = 1;
4750 alt_notend_table['7'] = 1;
4751 alt_notend_table['8'] = 1;
4752 alt_notend_table['9'] = 1;
4753
4754#ifndef MIT_SYNTAX_ONLY
4755 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4756 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4757 {
4758 int n = 0;
60fed2d3 4759
252b5132
RH		 4760 while (mote_pseudo_table[n].poc_name)
4761 {
60fed2d3 4762 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4763 hash_insert (op_hash,
4764 mote_pseudo_table[n].poc_name, (char *) hack);
4765 hack->m_operands = 0;
4766 hack->m_opnum = n;
4767 n++;
4768 }
4769 }
4770#endif
4771
4772 init_regtable ();
4773
4774#ifdef OBJ_ELF
4775 record_alignment (text_section, 2);
4776 record_alignment (data_section, 2);
4777 record_alignment (bss_section, 2);
4778#endif
4779}
4780
252b5132
RH		 4781\f
4782/* This is called when a label is defined. */
4783
4784void
31302357 4785m68k_frob_label (symbolS *sym)
252b5132
RH		 4786{
4787 struct label_line *n;
4788
4789 n = (struct label_line *) xmalloc (sizeof *n);
4790 n->next = labels;
4791 n->label = sym;
4792 as_where (&n->file, &n->line);
4793 n->text = 0;
4794 labels = n;
4795 current_label = n;
07a53e5c
RH		 4796
4797#ifdef OBJ_ELF
4798 dwarf2_emit_label (sym);
4799#endif
252b5132
RH		 4800}
4801
4802/* This is called when a value that is not an instruction is emitted. */
4803
4804void
31302357 4805m68k_flush_pending_output (void)
252b5132
RH		 4806{
4807 current_label = NULL;
4808}
4809
4810/* This is called at the end of the assembly, when the final value of
4811 the label is known. We warn if this is a text symbol aligned at an
4812 odd location. */
4813
4814void
31302357 4815m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4816{
4817 if (S_GET_SEGMENT (sym) == reg_section
4818 && (int) S_GET_VALUE (sym) < 0)
4819 {
4820 S_SET_SEGMENT (sym, absolute_section);
4821 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4822 }
4823 else if ((S_GET_VALUE (sym) & 1) != 0)
4824 {
4825 struct label_line *l;
4826
4827 for (l = labels; l != NULL; l = l->next)
4828 {
4829 if (l->label == sym)
4830 {
4831 if (l->text)
4832 as_warn_where (l->file, l->line,
4833 _("text label `%s' aligned to odd boundary"),
4834 S_GET_NAME (sym));
4835 break;
4836 }
4837 }
4838 }
4839}
4840\f
4841/* This is called if we go in or out of MRI mode because of the .mri
4842 pseudo-op. */
4843
4844void
31302357 4845m68k_mri_mode_change (int on)
252b5132
RH		 4846{
4847 if (on)
4848 {
4849 if (! flag_reg_prefix_optional)
4850 {
4851 flag_reg_prefix_optional = 1;
4852#ifdef REGISTER_PREFIX
4853 init_regtable ();
4854#endif
4855 }
4856 m68k_abspcadd = 1;
4857 if (! m68k_rel32_from_cmdline)
4858 m68k_rel32 = 0;
4859 }
4860 else
4861 {
4862 if (! reg_prefix_optional_seen)
4863 {
4864#ifdef REGISTER_PREFIX_OPTIONAL
4865 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4866#else
4867 flag_reg_prefix_optional = 0;
4868#endif
4869#ifdef REGISTER_PREFIX
4870 init_regtable ();
4871#endif
4872 }
4873 m68k_abspcadd = 0;
4874 if (! m68k_rel32_from_cmdline)
4875 m68k_rel32 = 1;
4876 }
4877}
4878
252b5132 4879char *
31302357 4880md_atof (int type, char *litP, int *sizeP)
252b5132 4881{
499ac353 4882 return ieee_md_atof (type, litP, sizeP, TRUE);
252b5132
RH		 4883}
4884
4885void
31302357 4886md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4887{
4888 number_to_chars_bigendian (buf, val, n);
4889}
4890
94f592af 4891void
55cf6793 4892md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4893{
bbe8ef22 4894 offsetT val = *valP;
252b5132
RH		 4895 addressT upper_limit;
4896 offsetT lower_limit;
4897
4898 /* This is unnecessary but it convinces the native rs6000 compiler
4899 to generate the code we want. */
4900 char *buf = fixP->fx_frag->fr_literal;
4901 buf += fixP->fx_where;
36759679 4902 /* End ibm compiler workaround. */
252b5132 4903
bd17c2c3 4904 val = SEXT (val);
252b5132 4905
94f592af
NC		 4906 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4907 fixP->fx_done = 1;
4908
252b5132
RH		 4909#ifdef OBJ_ELF
4910 if (fixP->fx_addsy)
4911 {
4912 memset (buf, 0, fixP->fx_size);
36759679 4913 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4914
4915 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4916 && !S_IS_DEFINED (fixP->fx_addsy)
4917 && !S_IS_WEAK (fixP->fx_addsy))
4918 S_SET_WEAK (fixP->fx_addsy);
cf869cce
NC		 4919
4920 switch (fixP->fx_r_type)
4921 {
4922 case BFD_RELOC_68K_TLS_GD32:
4923 case BFD_RELOC_68K_TLS_GD16:
4924 case BFD_RELOC_68K_TLS_GD8:
4925 case BFD_RELOC_68K_TLS_LDM32:
4926 case BFD_RELOC_68K_TLS_LDM16:
4927 case BFD_RELOC_68K_TLS_LDM8:
4928 case BFD_RELOC_68K_TLS_LDO32:
4929 case BFD_RELOC_68K_TLS_LDO16:
4930 case BFD_RELOC_68K_TLS_LDO8:
4931 case BFD_RELOC_68K_TLS_IE32:
4932 case BFD_RELOC_68K_TLS_IE16:
4933 case BFD_RELOC_68K_TLS_IE8:
4934 case BFD_RELOC_68K_TLS_LE32:
4935 case BFD_RELOC_68K_TLS_LE16:
4936 case BFD_RELOC_68K_TLS_LE8:
4937 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4938 break;
4939
4940 default:
4941 break;
4942 }
4943
252b5132
RH		 4944 return;
4945 }
22184a77 4946#elif defined(OBJ_AOUT)
1c3f20b4 4947 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
22184a77
NC		 4948 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4949 {
4950 memset (buf, 0, fixP->fx_size);
1c3f20b4 4951 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
22184a77
NC		 4952 return;
4953 }
252b5132
RH		 4954#endif
4955
252b5132
RH		 4956 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4957 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4958 return;
252b5132
RH		 4959
4960 switch (fixP->fx_size)
4961 {
94f592af
NC		 4962 /* The cast to offsetT below are necessary to make code
4963 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4964 case 1:
4965 *buf++ = val;
4966 upper_limit = 0x7f;
4967 lower_limit = - (offsetT) 0x80;
4968 break;
4969 case 2:
4970 *buf++ = (val >> 8);
4971 *buf++ = val;
4972 upper_limit = 0x7fff;
4973 lower_limit = - (offsetT) 0x8000;
4974 break;
4975 case 4:
4976 *buf++ = (val >> 24);
4977 *buf++ = (val >> 16);
4978 *buf++ = (val >> 8);
4979 *buf++ = val;
4980 upper_limit = 0x7fffffff;
36759679 4981 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4982 break;
4983 default:
4984 BAD_CASE (fixP->fx_size);
4985 }
4986
4987 /* Fix up a negative reloc. */
4988 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4989 {
4990 fixP->fx_addsy = fixP->fx_subsy;
4991 fixP->fx_subsy = NULL;
4992 fixP->fx_tcbit = 1;
4993 }
4994
4995 /* For non-pc-relative values, it's conceivable we might get something
4996 like "0xff" for a byte field. So extend the upper part of the range
4997 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4998 so that we can do any range checking at all. */
4999 if (! fixP->fx_pcrel && ! fixP->fx_signed)
5000 upper_limit = upper_limit * 2 + 1;
5001
5002 if ((addressT) val > upper_limit
5003 && (val > 0 || val < lower_limit))
2b878742
NS		 5004 as_bad_where (fixP->fx_file, fixP->fx_line,
5005 _("value %ld out of range"), (long)val);
252b5132
RH		 5006
5007 /* A one byte PC-relative reloc means a short branch. We can't use
5008 a short branch with a value of 0 or -1, because those indicate
5009 different opcodes (branches with longer offsets). fixup_segment
5010 in write.c may have clobbered fx_pcrel, so we need to examine the
5011 reloc type. */
5012 if ((fixP->fx_pcrel
7be1c489 5013 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 5014 && fixP->fx_size == 1
5015 && (fixP->fx_addsy == NULL
5016 || S_IS_DEFINED (fixP->fx_addsy))
5017 && (val == 0 || val == -1))
2b878742
NS		 5018 as_bad_where (fixP->fx_file, fixP->fx_line,
5019 _("invalid byte branch offset"));
252b5132
RH		 5020}
5021
252b5132
RH		 5022/* *fragP has been relaxed to its final size, and now needs to have
5023 the bytes inside it modified to conform to the new size There is UGLY
5024 MAGIC here. ..
5025 */
5026static void
31302357 5027md_convert_frag_1 (fragS *fragP)
252b5132
RH		 5028{
5029 long disp;
2b878742 5030 fixS *fixP = NULL;
252b5132
RH		 5031
5032 /* Address in object code of the displacement. */
5033 register int object_address = fragP->fr_fix + fragP->fr_address;
5034
5035 /* Address in gas core of the place to store the displacement. */
5036 /* This convinces the native rs6000 compiler to generate the code we
92774660 5037 want. */
252b5132
RH		 5038 register char *buffer_address = fragP->fr_literal;
5039 buffer_address += fragP->fr_fix;
36759679 5040 /* End ibm compiler workaround. */
252b5132
RH		 5041
5042 /* The displacement of the address, from current location. */
5043 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
5044 disp = (disp + fragP->fr_offset) - object_address;
5045
252b5132
RH		 5046 switch (fragP->fr_subtype)
5047 {
151337e8
NC		 5048 case TAB (BRANCHBWL, BYTE):
5049 case TAB (BRABSJUNC, BYTE):
5050 case TAB (BRABSJCOND, BYTE):
5051 case TAB (BRANCHBW, BYTE):
cac27205 5052 case TAB (BRANCHBWPL, BYTE):
252b5132
RH		 5053 know (issbyte (disp));
5054 if (disp == 0)
b091f402
AM		 5055 as_bad_where (fragP->fr_file, fragP->fr_line,
5056 _("short branch with zero offset: use :w"));
151337e8 5057 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5058 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5059 fixP->fx_pcrel_adjust = -1;
252b5132 5060 break;
151337e8
NC		 5061 case TAB (BRANCHBWL, SHORT):
5062 case TAB (BRABSJUNC, SHORT):
5063 case TAB (BRABSJCOND, SHORT):
5064 case TAB (BRANCHBW, SHORT):
cac27205 5065 case TAB (BRANCHBWPL, SHORT):
252b5132 5066 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 5067 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5068 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5069 fragP->fr_fix += 2;
5070 break;
5071 case TAB (BRANCHBWL, LONG):
5072 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 5073 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5074 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 5075 fragP->fr_fix += 4;
252b5132 5076 break;
cac27205
NC		 5077 case TAB (BRANCHBWPL, LONG):
5078 /* Here we are converting an unconditional branch into a pair of
5079 conditional branches, in order to get the range. */
5080 fragP->fr_opcode[0] = 0x66; /* bne */
5081 fragP->fr_opcode[1] = 0xFF;
5082 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5083 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5084 fixP->fx_file = fragP->fr_file;
5085 fixP->fx_line = fragP->fr_line;
5086 fragP->fr_fix += 4; /* Skip first offset */
5087 buffer_address += 4;
5088 *buffer_address++ = 0x67; /* beq */
5089 *buffer_address++ = 0xff;
5090 fragP->fr_fix += 2; /* Skip second branch opcode */
5091 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5092 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5093 fragP->fr_fix += 4;
5094 break;
151337e8
NC		 5095 case TAB (BRABSJUNC, LONG):
5096 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 5097 {
36759679 5098 if (flag_keep_pcrel)
2b878742
NS		 5099 as_bad_where (fragP->fr_file, fragP->fr_line,
5100 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 5101 fragP->fr_opcode[0] = 0x4E;
36759679 5102 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 5103 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5104 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5105 fragP->fr_fix += 4;
5106 }
5107 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5108 {
36759679 5109 if (flag_keep_pcrel)
2b878742
NS		 5110 as_bad_where (fragP->fr_file, fragP->fr_line,
5111 _("Conversion of PC relative branch to absolute jump"));
151337e8 5112 fragP->fr_opcode[0] = 0x4E;
36759679 5113 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 5114 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5115 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5116 fragP->fr_fix += 4;
252b5132
RH		 5117 }
5118 else
5119 {
151337e8
NC		 5120 /* This cannot happen, because jbsr and jbra are the only two
5121 unconditional branches. */
5122 abort ();
252b5132
RH		 5123 }
5124 break;
151337e8 5125 case TAB (BRABSJCOND, LONG):
36759679 5126 if (flag_keep_pcrel)
2b878742
NS		 5127 as_bad_where (fragP->fr_file, fragP->fr_line,
5128 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 5129
36759679
NC		 5130 /* Only Bcc 68000 instructions can come here
5131 Change bcc into b!cc/jmp absl long. */
5132 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5133 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 5134
5135 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 5136 different frag, in which case referring to them is a no-no.
92774660 5137 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 5138 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5139 *buffer_address++ = (char) 0xf9;
36759679 5140 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 5141 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5142 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5143 fragP->fr_fix += 4;
5144 break;
5145 case TAB (FBRANCH, SHORT):
5146 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 5147 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5148 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5149 fragP->fr_fix += 2;
5150 break;
5151 case TAB (FBRANCH, LONG):
36759679 5152 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 5153 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5154 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5155 fragP->fr_fix += 4;
252b5132 5156 break;
151337e8
NC		 5157 case TAB (DBCCLBR, SHORT):
5158 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 5159 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5160 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5161 fragP->fr_fix += 2;
5162 break;
5163 case TAB (DBCCLBR, LONG):
36759679
NC		 5164 /* Only DBcc instructions can come here.
5165 Change dbcc into dbcc/bral.
5166 JF: these used to be fr_opcode[2-7], but that's wrong. */
5167 if (flag_keep_pcrel)
2b878742
NS		 5168 as_bad_where (fragP->fr_file, fragP->fr_line,
5169 _("Conversion of DBcc to absolute jump"));
28e7409f 5170
36759679 5171 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 5172 *buffer_address++ = 0x04;
36759679 5173 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 5174 *buffer_address++ = 0x06;
151337e8
NC		 5175 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5176 *buffer_address++ = (char) 0xff;
252b5132 5177
36759679 5178 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5179 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5180 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5181 fragP->fr_fix += 4;
252b5132 5182 break;
151337e8 5183 case TAB (DBCCABSJ, LONG):
36759679
NC		 5184 /* Only DBcc instructions can come here.
5185 Change dbcc into dbcc/jmp.
5186 JF: these used to be fr_opcode[2-7], but that's wrong. */
5187 if (flag_keep_pcrel)
2b878742
NS		 5188 as_bad_where (fragP->fr_file, fragP->fr_line,
5189 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 5190
36759679 5191 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 5192 *buffer_address++ = 0x04;
36759679 5193 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 5194 *buffer_address++ = 0x06;
36759679 5195 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 5196 *buffer_address++ = (char) 0xf9;
5197
36759679 5198 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5199 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5200 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 5201 fragP->fr_fix += 4;
252b5132 5202 break;
151337e8 5203 case TAB (PCREL1632, SHORT):
252b5132
RH		 5204 fragP->fr_opcode[1] &= ~0x3F;
5205 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 5206 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5207 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 5208 fragP->fr_fix += 2;
252b5132 5209 break;
151337e8 5210 case TAB (PCREL1632, LONG):
252b5132
RH		 5211 /* Already set to mode 7.3; this indicates: PC indirect with
5212 suppressed index, 32-bit displacement. */
5213 *buffer_address++ = 0x01;
5214 *buffer_address++ = 0x70;
5215 fragP->fr_fix += 2;
151337e8 5216 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5217 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5218 fixP->fx_pcrel_adjust = 2;
5219 fragP->fr_fix += 4;
252b5132 5220 break;
252b5132 5221 case TAB (PCINDEX, BYTE):
9c2799c2 5222 gas_assert (fragP->fr_fix >= 2);
252b5132 5223 buffer_address[-2] &= ~1;
151337e8 5224 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5225 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5226 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 5227 break;
5228 case TAB (PCINDEX, SHORT):
9c2799c2 5229 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5230 buffer_address[-2] |= 0x1;
5231 buffer_address[-1] = 0x20;
5232 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 5233 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 5234 fixP->fx_pcrel_adjust = 2;
151337e8 5235 fragP->fr_fix += 2;
252b5132
RH		 5236 break;
5237 case TAB (PCINDEX, LONG):
9c2799c2 5238 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5239 buffer_address[-2] |= 0x1;
5240 buffer_address[-1] = 0x30;
151337e8 5241 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5242 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5243 fixP->fx_pcrel_adjust = 2;
5244 fragP->fr_fix += 4;
5245 break;
5246 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 5247 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5248 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5249 fragP->fr_fix += 2;
5250 break;
5251 case TAB (ABSTOPCREL, LONG):
36759679 5252 if (flag_keep_pcrel)
025987ea
NS		 5253 as_bad_where (fragP->fr_file, fragP->fr_line,
5254 _("Conversion of PC relative displacement to absolute"));
151337e8 5255 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 5256 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 5257 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5258 abort ();
5259 fragP->fr_opcode[1] &= ~0x3F;
5260 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 5261 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5262 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5263 fragP->fr_fix += 4;
252b5132 5264 break;
252b5132 5265 }
2b878742
NS		 5266 if (fixP)
5267 {
5268 fixP->fx_file = fragP->fr_file;
5269 fixP->fx_line = fragP->fr_line;
5270 }
252b5132
RH		 5271}
5272
252b5132 5273void
31302357
AS		 5274md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5275 segT sec ATTRIBUTE_UNUSED,
5276 fragS *fragP)
252b5132
RH		 5277{
5278 md_convert_frag_1 (fragP);
5279}
252b5132
RH		 5280
5281/* Force truly undefined symbols to their maximum size, and generally set up
5282 the frag list to be relaxed
5283 */
5284int
31302357 5285md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5286{
151337e8 5287 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5288 switch (fragP->fr_subtype)
5289 {
151337e8 5290 case TAB (BRANCHBWL, SZ_UNDEF):
cac27205 5291 case TAB (BRANCHBWPL, SZ_UNDEF):
151337e8 5292 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5293 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5294 {
151337e8
NC		 5295 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5296 && relaxable_symbol (fragP->fr_symbol))
252b5132 5297 {
151337e8
NC		 5298 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5299 }
5300 else if (flag_short_refs)
5301 {
5302 /* Symbol is undefined and we want short ref. */
5303 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5304 }
5305 else
5306 {
151337e8
NC		 5307 /* Symbol is still undefined. Make it LONG. */
5308 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5309 }
5310 break;
151337e8 5311 }
252b5132 5312
151337e8 5313 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5314 {
151337e8
NC		 5315 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5316 && relaxable_symbol (fragP->fr_symbol))
252b5132 5317 {
151337e8 5318 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5319 }
5320 else
5321 {
151337e8
NC		 5322 /* Symbol is undefined and we don't have long branches. */
5323 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5324 }
5325 break;
151337e8 5326 }
252b5132 5327
151337e8 5328 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5329 case TAB (DBCCLBR, SZ_UNDEF):
5330 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5331 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5332 {
8ec6253e
NC		 5333 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5334 && relaxable_symbol (fragP->fr_symbol))
151337e8 5335 || flag_short_refs)
252b5132 5336 {
151337e8 5337 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5338 }
5339 else
5340 {
151337e8 5341 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5342 }
5343 break;
151337e8 5344 }
81d4177b 5345
252b5132
RH		 5346 case TAB (PCINDEX, SZ_UNDEF):
5347 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5348 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5349 {
5350 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5351 }
5352 else
5353 {
5354 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5355 }
5356 break;
5357
151337e8
NC		 5358 case TAB (ABSTOPCREL, SZ_UNDEF):
5359 {
5360 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5361 && relaxable_symbol (fragP->fr_symbol)))
5362 {
5363 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5364 }
5365 else
5366 {
5367 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5368 }
5369 break;
5370 }
5371
252b5132
RH		 5372 default:
5373 break;
5374 }
5375
151337e8 5376 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5377 switch (fragP->fr_subtype)
5378 {
151337e8
NC		 5379 case TAB (BRANCHBWL, BYTE):
5380 case TAB (BRABSJUNC, BYTE):
5381 case TAB (BRABSJCOND, BYTE):
5382 case TAB (BRANCHBW, BYTE):
252b5132 5383 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5384 case we force word mode. If the symbol is at the start of a
5385 frag, and it is the next frag with any data in it (usually
5386 this is just the next frag, but assembler listings may
5387 introduce empty frags), we must use word mode. */
5388 if (fragP->fr_symbol)
252b5132 5389 {
ac62c346 5390 fragS *sym_frag;
252b5132 5391
ac62c346
AM		 5392 sym_frag = symbol_get_frag (fragP->fr_symbol);
5393 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5394 {
ac62c346
AM		 5395 fragS *l;
5396
23b7f870 5397 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5398 if (l->fr_fix != 0)
5399 break;
5400 if (l == sym_frag)
5401 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5402 }
5403 }
5404 break;
5405 default:
5406 break;
5407 }
ac62c346 5408 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5409}
5410
5411#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5412/* the bit-field entries in the relocation_info struct plays hell
5413 with the byte-order problems of cross-assembly. So as a hack,
5414 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5415 you there. -KWK */
252b5132
RH		 5416/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5417 are symbolnum, most sig. byte first. Last byte is broken up with
5418 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5419 nibble as nuthin. (on Sun 3 at least) */
5420/* Translate the internal relocation information into target-specific
92774660 5421 format. */
252b5132
RH		 5422#ifdef comment
5423void
31302357 5424md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5425{
36759679 5426 /* This is easy. */
252b5132 5427 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5428 /* Now the fun stuff. */
252b5132 5429 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5430 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5431 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5432 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5433 | ((ri->r_length << 5) & 0x60)
5434 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5435}
5436
36759679 5437#endif
252b5132 5438
252b5132
RH		 5439#endif /* OBJ_AOUT or OBJ_BOUT */
5440
5441#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5442int md_short_jump_size = 4;
5443int md_long_jump_size = 6;
252b5132
RH		 5444
5445void
31302357
AS		 5446md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5447 fragS *frag ATTRIBUTE_UNUSED,
5448 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5449{
5450 valueT offset;
5451
5452 offset = to_addr - (from_addr + 2);
5453
5454 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5455 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5456}
5457
5458void
31302357
AS		 5459md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5460 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5461{
5462 valueT offset;
5463
6b6e92f4 5464 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5465 {
36759679 5466 if (flag_keep_pcrel)
6b6e92f4 5467 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5468 offset = to_addr - S_GET_VALUE (to_symbol);
5469 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5470 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5471 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5472 0, NO_RELOC);
5473 }
5474 else
5475 {
5476 offset = to_addr - (from_addr + 2);
5477 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5478 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5479 }
5480}
5481
5482#endif
5483
5484/* Different values of OK tell what its OK to return. Things that
5485 aren't OK are an error (what a shock, no?)
5486
5487 0: Everything is OK
3e602632
NC		 5488 10: Absolute 1:8 only
5489 20: Absolute 0:7 only
5490 30: absolute 0:15 only
5491 40: Absolute 0:31 only
5492 50: absolute 0:127 only
252b5132 5493 55: absolute -64:63 only
3e602632 5494 60: absolute -128:127 only
afa2158f 5495 65: absolute 0:511 only
3e602632
NC		 5496 70: absolute 0:4095 only
5497 80: absolute -1, 1:7 only
5498 90: No bignums. */
252b5132
RH		 5499
5500static int
31302357 5501get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5502{
5503 if (exp->exp.X_op == O_absent)
5504 {
36759679 5505 /* Do the same thing the VAX asm does. */
252b5132
RH		 5506 op (exp) = O_constant;
5507 adds (exp) = 0;
5508 subs (exp) = 0;
5509 offs (exp) = 0;
5510 if (ok == 10)
5511 {
5512 as_warn (_("expression out of range: defaulting to 1"));
5513 offs (exp) = 1;
5514 }
5515 }
5516 else if (exp->exp.X_op == O_constant)
5517 {
5518 switch (ok)
5519 {
5520 case 10:
bd17c2c3 5521 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5522 {
5523 as_warn (_("expression out of range: defaulting to 1"));
5524 offs (exp) = 1;
5525 }
5526 break;
5527 case 20:
bd17c2c3 5528 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5529 goto outrange;
5530 break;
5531 case 30:
bd17c2c3 5532 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5533 goto outrange;
5534 break;
5535 case 40:
bd17c2c3 5536 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5537 goto outrange;
5538 break;
5539 case 50:
bd17c2c3 5540 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5541 goto outrange;
5542 break;
5543 case 55:
bd17c2c3 5544 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5545 goto outrange;
5546 break;
5547 case 60:
bd17c2c3 5548 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132 5549 goto outrange;
afa2158f
NS		 5550 break;
5551 case 65:
5552 if ((valueT) TRUNC (offs (exp)) > 511)
5553 goto outrange;
252b5132
RH		 5554 break;
5555 case 70:
bd17c2c3 5556 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5557 {
5558 outrange:
5559 as_warn (_("expression out of range: defaulting to 0"));
5560 offs (exp) = 0;
5561 }
5562 break;
3e602632 5563 case 80:
bd17c2c3
AM		 5564 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5565 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5566 {
5567 as_warn (_("expression out of range: defaulting to 1"));
5568 offs (exp) = 1;
5569 }
5570 break;
252b5132
RH		 5571 default:
5572 break;
5573 }
5574 }
5575 else if (exp->exp.X_op == O_big)
5576 {
36759679 5577 if (offs (exp) <= 0 /* flonum. */
3e602632 5578 && (ok == 90 /* no bignums */
36759679 5579 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5580 /* If we have a flonum zero, a zero integer should
5581 do as well (e.g., in moveq). */
5582 && generic_floating_point_number.exponent == 0
5583 && generic_floating_point_number.low[0] == 0)))
5584 {
36759679 5585 /* HACK! Turn it into a long. */
252b5132
RH		 5586 LITTLENUM_TYPE words[6];
5587
36759679 5588 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5589 op (exp) = O_constant;
5590 adds (exp) = 0;
5591 subs (exp) = 0;
5592 offs (exp) = words[1] | (words[0] << 16);
5593 }
5594 else if (ok != 0)
5595 {
5596 op (exp) = O_constant;
5597 adds (exp) = 0;
5598 subs (exp) = 0;
5599 offs (exp) = (ok == 10) ? 1 : 0;
5600 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5601 (long) offs (exp));
252b5132
RH		 5602 }
5603 }
5604 else
5605 {
3e602632 5606 if (ok >= 10 && ok <= 80)
252b5132
RH		 5607 {
5608 op (exp) = O_constant;
5609 adds (exp) = 0;
5610 subs (exp) = 0;
5611 offs (exp) = (ok == 10) ? 1 : 0;
5612 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5613 (long) offs (exp));
252b5132
RH		 5614 }
5615 }
5616
5617 if (exp->size != SIZE_UNSPEC)
5618 {
5619 switch (exp->size)
5620 {
5621 case SIZE_UNSPEC:
5622 case SIZE_LONG:
5623 break;
5624 case SIZE_BYTE:
5625 if (!isbyte (offs (exp)))
5626 as_warn (_("expression doesn't fit in BYTE"));
5627 break;
5628 case SIZE_WORD:
5629 if (!isword (offs (exp)))
5630 as_warn (_("expression doesn't fit in WORD"));
5631 break;
5632 }
5633 }
5634
5635 return offs (exp);
5636}
5637
5638/* These are the back-ends for the various machine dependent pseudo-ops. */
5639
5640static void
31302357 5641s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5642{
5643 subseg_set (data_section, 1);
5644 demand_empty_rest_of_line ();
5645}
5646
5647static void
31302357 5648s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5649{
5650 subseg_set (data_section, 2);
5651 demand_empty_rest_of_line ();
5652}
5653
5654static void
31302357 5655s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5656{
5657 /* We don't support putting frags in the BSS segment, we fake it
5658 by marking in_bss, then looking at s_skip for clues. */
5659
5660 subseg_set (bss_section, 0);
5661 demand_empty_rest_of_line ();
5662}
5663
5664static void
31302357 5665s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5666{
5667 register int temp;
5668 register long temp_fill;
5669
5670 temp = 1; /* JF should be 2? */
5671 temp_fill = get_absolute_expression ();
92774660 5672 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5673 frag_align (temp, (int) temp_fill, 0);
5674 demand_empty_rest_of_line ();
5675 record_alignment (now_seg, temp);
5676}
5677
5678static void
31302357 5679s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5680{
5681 demand_empty_rest_of_line ();
5682}
5683\f
5684/* Pseudo-ops handled for MRI compatibility. */
5685
5686/* This function returns non-zero if the argument is a conditional
5687 pseudo-op. This is called when checking whether a pending
5688 alignment is needed. */
5689
5690int
31302357 5691m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5692{
5693 return (pop->poc_handler == s_mri_if
5694 || pop->poc_handler == s_mri_else);
5695}
5696
5697/* Handle an MRI style chip specification. */
5698
5699static void
31302357 5700mri_chip (void)
252b5132
RH		 5701{
5702 char *s;
5703 char c;
5704 int i;
5705
5706 s = input_line_pointer;
5707 /* We can't use get_symbol_end since the processor names are not proper
5708 symbols. */
5709 while (is_part_of_name (c = *input_line_pointer++))
5710 ;
5711 *--input_line_pointer = 0;
266abb8f
NS		 5712 for (i = 0; m68k_cpus[i].name; i++)
5713 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5714 break;
266abb8f 5715 if (!m68k_cpus[i].name)
252b5132
RH		 5716 {
5717 as_bad (_("%s: unrecognized processor name"), s);
5718 *input_line_pointer = c;
5719 ignore_rest_of_line ();
5720 return;
5721 }
5722 *input_line_pointer = c;
5723
5724 if (*input_line_pointer == '/')
5725 current_architecture = 0;
5726 else
5727 current_architecture &= m68881 | m68851;
266abb8f 5728 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5729 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5730
5731 while (*input_line_pointer == '/')
5732 {
5733 ++input_line_pointer;
5734 s = input_line_pointer;
5735 /* We can't use get_symbol_end since the processor names are not
5736 proper symbols. */
5737 while (is_part_of_name (c = *input_line_pointer++))
5738 ;
5739 *--input_line_pointer = 0;
5740 if (strcmp (s, "68881") == 0)
5741 current_architecture |= m68881;
5742 else if (strcmp (s, "68851") == 0)
5743 current_architecture |= m68851;
5744 *input_line_pointer = c;
5745 }
252b5132
RH		 5746}
5747
5748/* The MRI CHIP pseudo-op. */
5749
5750static void
31302357 5751s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5752{
5753 char *stop = NULL;
5754 char stopc;
5755
5756 if (flag_mri)
5757 stop = mri_comment_field (&stopc);
5758 mri_chip ();
5759 if (flag_mri)
5760 mri_comment_end (stop, stopc);
5761 demand_empty_rest_of_line ();
5762}
5763
5764/* The MRI FOPT pseudo-op. */
5765
5766static void
31302357 5767s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5768{
5769 SKIP_WHITESPACE ();
5770
5771 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5772 {
5773 int temp;
5774
5775 input_line_pointer += 3;
5776 temp = get_absolute_expression ();
5777 if (temp < 0 || temp > 7)
5778 as_bad (_("bad coprocessor id"));
5779 else
5780 m68k_float_copnum = COP0 + temp;
5781 }
5782 else
5783 {
5784 as_bad (_("unrecognized fopt option"));
5785 ignore_rest_of_line ();
5786 return;
5787 }
5788
5789 demand_empty_rest_of_line ();
5790}
5791
5792/* The structure used to handle the MRI OPT pseudo-op. */
5793
5794struct opt_action
5795{
5796 /* The name of the option. */
5797 const char *name;
5798
5799 /* If this is not NULL, just call this function. The first argument
5800 is the ARG field of this structure, the second argument is
5801 whether the option was negated. */
31302357 5802 void (*pfn) (int arg, int on);
252b5132
RH		 5803
5804 /* If this is not NULL, and the PFN field is NULL, set the variable
5805 this points to. Set it to the ARG field if the option was not
5806 negated, and the NOTARG field otherwise. */
5807 int *pvar;
5808
5809 /* The value to pass to PFN or to assign to *PVAR. */
5810 int arg;
5811
5812 /* The value to assign to *PVAR if the option is negated. If PFN is
5813 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5814 the option may not be negated. */
5815 int notarg;
5816};
5817
5818/* The table used to handle the MRI OPT pseudo-op. */
5819
31302357
AS		 5820static void skip_to_comma (int, int);
5821static void opt_nest (int, int);
5822static void opt_chip (int, int);
5823static void opt_list (int, int);
5824static void opt_list_symbols (int, int);
252b5132
RH		 5825
5826static const struct opt_action opt_table[] =
5827{
5828 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5829
5830 /* We do relaxing, so there is little use for these options. */
5831 { "b", 0, 0, 0, 0 },
5832 { "brs", 0, 0, 0, 0 },
5833 { "brb", 0, 0, 0, 0 },
5834 { "brl", 0, 0, 0, 0 },
5835 { "brw", 0, 0, 0, 0 },
5836
5837 { "c", 0, 0, 0, 0 },
5838 { "cex", 0, 0, 0, 0 },
5839 { "case", 0, &symbols_case_sensitive, 1, 0 },
5840 { "cl", 0, 0, 0, 0 },
5841 { "cre", 0, 0, 0, 0 },
5842 { "d", 0, &flag_keep_locals, 1, 0 },
5843 { "e", 0, 0, 0, 0 },
5844 { "f", 0, &flag_short_refs, 1, 0 },
5845 { "frs", 0, &flag_short_refs, 1, 0 },
5846 { "frl", 0, &flag_short_refs, 0, 1 },
5847 { "g", 0, 0, 0, 0 },
5848 { "i", 0, 0, 0, 0 },
5849 { "m", 0, 0, 0, 0 },
5850 { "mex", 0, 0, 0, 0 },
5851 { "mc", 0, 0, 0, 0 },
5852 { "md", 0, 0, 0, 0 },
5853 { "nest", opt_nest, 0, 0, 0 },
5854 { "next", skip_to_comma, 0, 0, 0 },
5855 { "o", 0, 0, 0, 0 },
5856 { "old", 0, 0, 0, 0 },
5857 { "op", skip_to_comma, 0, 0, 0 },
5858 { "pco", 0, 0, 0, 0 },
5859 { "p", opt_chip, 0, 0, 0 },
5860 { "pcr", 0, 0, 0, 0 },
5861 { "pcs", 0, 0, 0, 0 },
5862 { "r", 0, 0, 0, 0 },
5863 { "quick", 0, &m68k_quick, 1, 0 },
5864 { "rel32", 0, &m68k_rel32, 1, 0 },
5865 { "s", opt_list, 0, 0, 0 },
5866 { "t", opt_list_symbols, 0, 0, 0 },
5867 { "w", 0, &flag_no_warnings, 0, 1 },
5868 { "x", 0, 0, 0, 0 }
5869};
5870
8fce3f5e 5871#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5872
5873/* The MRI OPT pseudo-op. */
5874
5875static void
31302357 5876s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5877{
5878 do
5879 {
5880 int t;
5881 char *s;
5882 char c;
5883 int i;
5884 const struct opt_action *o;
5885
5886 SKIP_WHITESPACE ();
5887
5888 t = 1;
5889 if (*input_line_pointer == '-')
5890 {
5891 ++input_line_pointer;
5892 t = 0;
5893 }
5894 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5895 {
5896 input_line_pointer += 2;
5897 t = 0;
5898 }
5899
5900 s = input_line_pointer;
5901 c = get_symbol_end ();
5902
5903 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5904 {
5905 if (strcasecmp (s, o->name) == 0)
5906 {
5907 if (o->pfn)
5908 {
5909 /* Restore input_line_pointer now in case the option
5910 takes arguments. */
5911 *input_line_pointer = c;
5912 (*o->pfn) (o->arg, t);
5913 }
5914 else if (o->pvar != NULL)
5915 {
5916 if (! t && o->arg == o->notarg)
5917 as_bad (_("option `%s' may not be negated"), s);
5918 *input_line_pointer = c;
5919 *o->pvar = t ? o->arg : o->notarg;
5920 }
5921 else
5922 *input_line_pointer = c;
5923 break;
5924 }
5925 }
5926 if (i >= OPTCOUNT)
5927 {
5928 as_bad (_("option `%s' not recognized"), s);
5929 *input_line_pointer = c;
5930 }
5931 }
5932 while (*input_line_pointer++ == ',');
5933
5934 /* Move back to terminating character. */
5935 --input_line_pointer;
5936 demand_empty_rest_of_line ();
5937}
5938
5939/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5940 not support and which take arguments. */
252b5132
RH		 5941
5942static void
31302357 5943skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5944{
5945 while (*input_line_pointer != ','
5946 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5947 ++input_line_pointer;
5948}
5949
5950/* Handle the OPT NEST=depth option. */
5951
5952static void
31302357 5953opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5954{
5955 if (*input_line_pointer != '=')
5956 {
5957 as_bad (_("bad format of OPT NEST=depth"));
5958 return;
5959 }
5960
5961 ++input_line_pointer;
5962 max_macro_nest = get_absolute_expression ();
5963}
5964
5965/* Handle the OPT P=chip option. */
5966
5967static void
31302357 5968opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5969{
5970 if (*input_line_pointer != '=')
5971 {
5972 /* This is just OPT P, which we do not support. */
5973 return;
5974 }
5975
5976 ++input_line_pointer;
5977 mri_chip ();
5978}
5979
5980/* Handle the OPT S option. */
5981
5982static void
31302357 5983opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5984{
5985 listing_list (on);
5986}
5987
5988/* Handle the OPT T option. */
5989
5990static void
31302357 5991opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5992{
5993 if (on)
5994 listing |= LISTING_SYMBOLS;
5995 else
8a104df9 5996 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5997}
5998
5999/* Handle the MRI REG pseudo-op. */
6000
6001static void
31302357 6002s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6003{
6004 char *s;
6005 int c;
6006 struct m68k_op rop;
6007 int mask;
6008 char *stop = NULL;
6009 char stopc;
6010
6011 if (line_label == NULL)
6012 {
6013 as_bad (_("missing label"));
6014 ignore_rest_of_line ();
6015 return;
6016 }
6017
6018 if (flag_mri)
6019 stop = mri_comment_field (&stopc);
6020
6021 SKIP_WHITESPACE ();
6022
6023 s = input_line_pointer;
3882b010 6024 while (ISALNUM (*input_line_pointer)
252b5132
RH		 6025#ifdef REGISTER_PREFIX
6026 || *input_line_pointer == REGISTER_PREFIX
6027#endif
6028 || *input_line_pointer == '/'
6029 || *input_line_pointer == '-')
6030 ++input_line_pointer;
6031 c = *input_line_pointer;
6032 *input_line_pointer = '\0';
6033
6034 if (m68k_ip_op (s, &rop) != 0)
6035 {
6036 if (rop.error == NULL)
6037 as_bad (_("bad register list"));
6038 else
6039 as_bad (_("bad register list: %s"), rop.error);
6040 *input_line_pointer = c;
6041 ignore_rest_of_line ();
6042 return;
6043 }
6044
6045 *input_line_pointer = c;
6046
6047 if (rop.mode == REGLST)
6048 mask = rop.mask;
6049 else if (rop.mode == DREG)
6050 mask = 1 << (rop.reg - DATA0);
6051 else if (rop.mode == AREG)
6052 mask = 1 << (rop.reg - ADDR0 + 8);
6053 else if (rop.mode == FPREG)
6054 mask = 1 << (rop.reg - FP0 + 16);
6055 else if (rop.mode == CONTROL
6056 && rop.reg == FPI)
6057 mask = 1 << 24;
6058 else if (rop.mode == CONTROL
6059 && rop.reg == FPS)
6060 mask = 1 << 25;
6061 else if (rop.mode == CONTROL
6062 && rop.reg == FPC)
6063 mask = 1 << 26;
6064 else
6065 {
6066 as_bad (_("bad register list"));
6067 ignore_rest_of_line ();
6068 return;
6069 }
6070
6071 S_SET_SEGMENT (line_label, reg_section);
6072 S_SET_VALUE (line_label, ~mask);
49309057 6073 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 6074
6075 if (flag_mri)
6076 mri_comment_end (stop, stopc);
6077
6078 demand_empty_rest_of_line ();
6079}
6080
6081/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
6082
6083struct save_opts
6084{
6085 struct save_opts *next;
6086 int abspcadd;
6087 int symbols_case_sensitive;
6088 int keep_locals;
6089 int short_refs;
6090 int architecture;
2da12c60 6091 const enum m68k_register *control_regs;
252b5132
RH		 6092 int quick;
6093 int rel32;
6094 int listing;
6095 int no_warnings;
6096 /* FIXME: We don't save OPT S. */
6097};
6098
6099/* This variable holds the stack of saved options. */
6100
6101static struct save_opts *save_stack;
6102
6103/* The MRI SAVE pseudo-op. */
6104
6105static void
31302357 6106s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6107{
6108 struct save_opts *s;
6109
6110 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
6111 s->abspcadd = m68k_abspcadd;
6112 s->symbols_case_sensitive = symbols_case_sensitive;
6113 s->keep_locals = flag_keep_locals;
6114 s->short_refs = flag_short_refs;
6115 s->architecture = current_architecture;
2da12c60 6116 s->control_regs = control_regs;
252b5132
RH		 6117 s->quick = m68k_quick;
6118 s->rel32 = m68k_rel32;
6119 s->listing = listing;
6120 s->no_warnings = flag_no_warnings;
6121
6122 s->next = save_stack;
6123 save_stack = s;
6124
6125 demand_empty_rest_of_line ();
6126}
6127
6128/* The MRI RESTORE pseudo-op. */
6129
6130static void
31302357 6131s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6132{
6133 struct save_opts *s;
6134
6135 if (save_stack == NULL)
6136 {
6137 as_bad (_("restore without save"));
6138 ignore_rest_of_line ();
6139 return;
6140 }
6141
6142 s = save_stack;
6143 save_stack = s->next;
6144
6145 m68k_abspcadd = s->abspcadd;
6146 symbols_case_sensitive = s->symbols_case_sensitive;
6147 flag_keep_locals = s->keep_locals;
6148 flag_short_refs = s->short_refs;
6149 current_architecture = s->architecture;
2da12c60 6150 control_regs = s->control_regs;
252b5132
RH		 6151 m68k_quick = s->quick;
6152 m68k_rel32 = s->rel32;
6153 listing = s->listing;
6154 flag_no_warnings = s->no_warnings;
6155
6156 free (s);
6157
6158 demand_empty_rest_of_line ();
6159}
6160
6161/* Types of MRI structured control directives. */
6162
6163enum mri_control_type
6164{
6165 mri_for,
6166 mri_if,
6167 mri_repeat,
6168 mri_while
6169};
6170
6171/* This structure is used to stack the MRI structured control
6172 directives. */
6173
6174struct mri_control_info
6175{
6176 /* The directive within which this one is enclosed. */
6177 struct mri_control_info *outer;
6178
6179 /* The type of directive. */
6180 enum mri_control_type type;
6181
6182 /* Whether an ELSE has been in an IF. */
6183 int else_seen;
6184
6185 /* The add or sub statement at the end of a FOR. */
6186 char *incr;
6187
6188 /* The label of the top of a FOR or REPEAT loop. */
6189 char *top;
6190
6191 /* The label to jump to for the next iteration, or the else
6192 expression of a conditional. */
6193 char *next;
6194
6195 /* The label to jump to to break out of the loop, or the label past
6196 the end of a conditional. */
6197 char *bottom;
6198};
6199
6200/* The stack of MRI structured control directives. */
6201
6202static struct mri_control_info *mri_control_stack;
6203
6204/* The current MRI structured control directive index number, used to
6205 generate label names. */
6206
6207static int mri_control_index;
6208
252b5132
RH		 6209/* Assemble an instruction for an MRI structured control directive. */
6210
6211static void
31302357 6212mri_assemble (char *str)
252b5132
RH		 6213{
6214 char *s;
6215
6216 /* md_assemble expects the opcode to be in lower case. */
6217 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 6218 *s = TOLOWER (*s);
252b5132
RH		 6219
6220 md_assemble (str);
6221}
6222
6223/* Generate a new MRI label structured control directive label name. */
6224
6225static char *
31302357 6226mri_control_label (void)
252b5132
RH		 6227{
6228 char *n;
6229
6230 n = (char *) xmalloc (20);
6231 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6232 ++mri_control_index;
6233 return n;
6234}
6235
6236/* Create a new MRI structured control directive. */
6237
6238static struct mri_control_info *
31302357 6239push_mri_control (enum mri_control_type type)
252b5132
RH		 6240{
6241 struct mri_control_info *n;
6242
6243 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6244
6245 n->type = type;
6246 n->else_seen = 0;
6247 if (type == mri_if || type == mri_while)
6248 n->top = NULL;
6249 else
6250 n->top = mri_control_label ();
6251 n->next = mri_control_label ();
6252 n->bottom = mri_control_label ();
6253
6254 n->outer = mri_control_stack;
6255 mri_control_stack = n;
6256
6257 return n;
6258}
6259
6260/* Pop off the stack of MRI structured control directives. */
6261
6262static void
31302357 6263pop_mri_control (void)
252b5132
RH		 6264{
6265 struct mri_control_info *n;
6266
6267 n = mri_control_stack;
6268 mri_control_stack = n->outer;
6269 if (n->top != NULL)
6270 free (n->top);
6271 free (n->next);
6272 free (n->bottom);
6273 free (n);
6274}
6275
6276/* Recognize a condition code in an MRI structured control expression. */
6277
6278static int
31302357 6279parse_mri_condition (int *pcc)
252b5132
RH		 6280{
6281 char c1, c2;
6282
6283 know (*input_line_pointer == '<');
6284
6285 ++input_line_pointer;
6286 c1 = *input_line_pointer++;
6287 c2 = *input_line_pointer++;
6288
6289 if (*input_line_pointer != '>')
6290 {
6291 as_bad (_("syntax error in structured control directive"));
6292 return 0;
6293 }
6294
6295 ++input_line_pointer;
6296 SKIP_WHITESPACE ();
6297
3882b010
L		 6298 c1 = TOLOWER (c1);
6299 c2 = TOLOWER (c2);
252b5132
RH		 6300
6301 *pcc = (c1 << 8) | c2;
6302
6303 return 1;
6304}
6305
6306/* Parse a single operand in an MRI structured control expression. */
6307
6308static int
31302357
AS		 6309parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6310 char **rightstart, char **rightstop)
252b5132
RH		 6311{
6312 char *s;
6313
6314 SKIP_WHITESPACE ();
6315
6316 *pcc = -1;
6317 *leftstart = NULL;
6318 *leftstop = NULL;
6319 *rightstart = NULL;
6320 *rightstop = NULL;
6321
6322 if (*input_line_pointer == '<')
6323 {
6324 /* It's just a condition code. */
6325 return parse_mri_condition (pcc);
6326 }
6327
6328 /* Look ahead for the condition code. */
6329 for (s = input_line_pointer; *s != '\0'; ++s)
6330 {
6331 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6332 break;
6333 }
6334 if (*s == '\0')
6335 {
6336 as_bad (_("missing condition code in structured control directive"));
6337 return 0;
6338 }
6339
6340 *leftstart = input_line_pointer;
6341 *leftstop = s;
6342 if (*leftstop > *leftstart
6343 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6344 --*leftstop;
6345
6346 input_line_pointer = s;
6347 if (! parse_mri_condition (pcc))
6348 return 0;
6349
6350 /* Look ahead for AND or OR or end of line. */
6351 for (s = input_line_pointer; *s != '\0'; ++s)
6352 {
e1f44d10
NC		 6353 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6354 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6355 ^^^ ^^ */
8a104df9
KH		 6356 if ((s == input_line_pointer
6357 || *(s-1) == ' '
6358 || *(s-1) == '\t')
6359 && ((strncasecmp (s, "AND", 3) == 0
6360 && (s[3] == '.' || ! is_part_of_name (s[3])))
6361 || (strncasecmp (s, "OR", 2) == 0
6362 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6363 break;
252b5132
RH		 6364 }
6365
6366 *rightstart = input_line_pointer;
6367 *rightstop = s;
6368 if (*rightstop > *rightstart
6369 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6370 --*rightstop;
6371
6372 input_line_pointer = s;
6373
6374 return 1;
6375}
6376
6377#define MCC(b1, b2) (((b1) << 8) | (b2))
6378
6379/* Swap the sense of a condition. This changes the condition so that
6380 it generates the same result when the operands are swapped. */
6381
6382static int
31302357 6383swap_mri_condition (int cc)
252b5132
RH		 6384{
6385 switch (cc)
6386 {
6387 case MCC ('h', 'i'): return MCC ('c', 's');
6388 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6389 /* <HS> is an alias for <CC>. */
e1f44d10 6390 case MCC ('h', 's'):
252b5132 6391 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6392 /* <LO> is an alias for <CS>. */
e1f44d10 6393 case MCC ('l', 'o'):
252b5132
RH		 6394 case MCC ('c', 's'): return MCC ('h', 'i');
6395 case MCC ('p', 'l'): return MCC ('m', 'i');
6396 case MCC ('m', 'i'): return MCC ('p', 'l');
6397 case MCC ('g', 'e'): return MCC ('l', 'e');
6398 case MCC ('l', 't'): return MCC ('g', 't');
6399 case MCC ('g', 't'): return MCC ('l', 't');
6400 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6401 /* Issue a warning for conditions we can not swap. */
8fc4ee9b
AM		 6402 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6403 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
e1f44d10
NC		 6404 case MCC ('v', 'c'):
6405 case MCC ('v', 's'):
6406 default :
6407 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6408 (char) (cc >> 8), (char) (cc));
6409 break;
252b5132
RH		 6410 }
6411 return cc;
6412}
6413
6414/* Reverse the sense of a condition. */
6415
6416static int
31302357 6417reverse_mri_condition (int cc)
252b5132
RH		 6418{
6419 switch (cc)
6420 {
6421 case MCC ('h', 'i'): return MCC ('l', 's');
6422 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6423 /* <HS> is an alias for <CC> */
6424 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6425 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6426 /* <LO> is an alias for <CS> */
6427 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6428 case MCC ('c', 's'): return MCC ('c', 'c');
6429 case MCC ('n', 'e'): return MCC ('e', 'q');
6430 case MCC ('e', 'q'): return MCC ('n', 'e');
6431 case MCC ('v', 'c'): return MCC ('v', 's');
6432 case MCC ('v', 's'): return MCC ('v', 'c');
6433 case MCC ('p', 'l'): return MCC ('m', 'i');
6434 case MCC ('m', 'i'): return MCC ('p', 'l');
6435 case MCC ('g', 'e'): return MCC ('l', 't');
6436 case MCC ('l', 't'): return MCC ('g', 'e');
6437 case MCC ('g', 't'): return MCC ('l', 'e');
6438 case MCC ('l', 'e'): return MCC ('g', 't');
6439 }
6440 return cc;
6441}
6442
6443/* Build an MRI structured control expression. This generates test
6444 and branch instructions. It goes to TRUELAB if the condition is
6445 true, and to FALSELAB if the condition is false. Exactly one of
6446 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6447 is the size qualifier for the expression. EXTENT is the size to
6448 use for the branch. */
6449
6450static void
31302357
AS		 6451build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6452 char *rightstart, char *rightstop,
6453 const char *truelab, const char *falselab,
6454 int extent)
252b5132
RH		 6455{
6456 char *buf;
6457 char *s;
6458
6459 if (leftstart != NULL)
6460 {
6461 struct m68k_op leftop, rightop;
6462 char c;
6463
6464 /* Swap the compare operands, if necessary, to produce a legal
6465 m68k compare instruction. Comparing a register operand with
6466 a non-register operand requires the register to be on the
6467 right (cmp, cmpa). Comparing an immediate value with
6468 anything requires the immediate value to be on the left
6469 (cmpi). */
6470
6471 c = *leftstop;
6472 *leftstop = '\0';
6473 (void) m68k_ip_op (leftstart, &leftop);
6474 *leftstop = c;
6475
6476 c = *rightstop;
6477 *rightstop = '\0';
6478 (void) m68k_ip_op (rightstart, &rightop);
6479 *rightstop = c;
6480
6481 if (rightop.mode == IMMED
6482 || ((leftop.mode == DREG || leftop.mode == AREG)
6483 && (rightop.mode != DREG && rightop.mode != AREG)))
6484 {
6485 char *temp;
6486
31302357
AS		 6487 /* Correct conditional handling:
6488 if #1 <lt> d0 then ;means if (1 < d0)
6489 ...
6490 endi
e1f44d10 6491
31302357 6492 should assemble to:
e1f44d10 6493
31302357
AS		 6494 cmp #1,d0 if we do *not* swap the operands
6495 bgt true we need the swapped condition!
6496 ble false
6497 true:
6498 ...
6499 false:
6500 */
252b5132
RH		 6501 temp = leftstart;
6502 leftstart = rightstart;
6503 rightstart = temp;
6504 temp = leftstop;
6505 leftstop = rightstop;
6506 rightstop = temp;
8a104df9
KH		 6507 }
6508 else
6509 {
e1f44d10 6510 cc = swap_mri_condition (cc);
252b5132
RH		 6511 }
6512 }
6513
6514 if (truelab == NULL)
6515 {
6516 cc = reverse_mri_condition (cc);
6517 truelab = falselab;
6518 }
92774660 6519
252b5132
RH		 6520 if (leftstart != NULL)
6521 {
6522 buf = (char *) xmalloc (20
6523 + (leftstop - leftstart)
6524 + (rightstop - rightstart));
6525 s = buf;
6526 *s++ = 'c';
6527 *s++ = 'm';
6528 *s++ = 'p';
6529 if (qual != '\0')
3882b010 6530 *s++ = TOLOWER (qual);
252b5132
RH		 6531 *s++ = ' ';
6532 memcpy (s, leftstart, leftstop - leftstart);
6533 s += leftstop - leftstart;
6534 *s++ = ',';
6535 memcpy (s, rightstart, rightstop - rightstart);
6536 s += rightstop - rightstart;
6537 *s = '\0';
6538 mri_assemble (buf);
6539 free (buf);
6540 }
92774660 6541
252b5132
RH		 6542 buf = (char *) xmalloc (20 + strlen (truelab));
6543 s = buf;
6544 *s++ = 'b';
6545 *s++ = cc >> 8;
6546 *s++ = cc & 0xff;
6547 if (extent != '\0')
3882b010 6548 *s++ = TOLOWER (extent);
252b5132
RH		 6549 *s++ = ' ';
6550 strcpy (s, truelab);
6551 mri_assemble (buf);
6552 free (buf);
6553}
6554
6555/* Parse an MRI structured control expression. This generates test
6556 and branch instructions. STOP is where the expression ends. It
6557 goes to TRUELAB if the condition is true, and to FALSELAB if the
6558 condition is false. Exactly one of TRUELAB and FALSELAB will be
6559 NULL, meaning to fall through. QUAL is the size qualifier for the
6560 expression. EXTENT is the size to use for the branch. */
6561
6562static void
31302357
AS		 6563parse_mri_control_expression (char *stop, int qual, const char *truelab,
6564 const char *falselab, int extent)
252b5132
RH		 6565{
6566 int c;
6567 int cc;
6568 char *leftstart;
6569 char *leftstop;
6570 char *rightstart;
6571 char *rightstop;
6572
6573 c = *stop;
6574 *stop = '\0';
6575
6576 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6577 &rightstart, &rightstop))
6578 {
6579 *stop = c;
6580 return;
6581 }
6582
6583 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6584 {
6585 const char *flab;
6586
6587 if (falselab != NULL)
6588 flab = falselab;
6589 else
6590 flab = mri_control_label ();
6591
6592 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6593 rightstop, (const char *) NULL, flab, extent);
6594
6595 input_line_pointer += 3;
6596 if (*input_line_pointer != '.'
6597 || input_line_pointer[1] == '\0')
6598 qual = '\0';
6599 else
6600 {
6601 qual = input_line_pointer[1];
6602 input_line_pointer += 2;
6603 }
6604
6605 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6606 &rightstart, &rightstop))
6607 {
6608 *stop = c;
6609 return;
6610 }
6611
6612 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6613 rightstop, truelab, falselab, extent);
6614
6615 if (falselab == NULL)
6616 colon (flab);
6617 }
6618 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6619 {
6620 const char *tlab;
6621
6622 if (truelab != NULL)
6623 tlab = truelab;
6624 else
6625 tlab = mri_control_label ();
6626
6627 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6628 rightstop, tlab, (const char *) NULL, extent);
6629
6630 input_line_pointer += 2;
6631 if (*input_line_pointer != '.'
6632 || input_line_pointer[1] == '\0')
6633 qual = '\0';
6634 else
6635 {
6636 qual = input_line_pointer[1];
6637 input_line_pointer += 2;
6638 }
6639
6640 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6641 &rightstart, &rightstop))
6642 {
6643 *stop = c;
6644 return;
6645 }
6646
6647 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6648 rightstop, truelab, falselab, extent);
6649
6650 if (truelab == NULL)
6651 colon (tlab);
6652 }
6653 else
6654 {
6655 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6656 rightstop, truelab, falselab, extent);
6657 }
6658
6659 *stop = c;
6660 if (input_line_pointer != stop)
6661 as_bad (_("syntax error in structured control directive"));
6662}
6663
6664/* Handle the MRI IF pseudo-op. This may be a structured control
6665 directive, or it may be a regular assembler conditional, depending
6666 on its operands. */
6667
6668static void
31302357 6669s_mri_if (int qual)
252b5132
RH		 6670{
6671 char *s;
6672 int c;
6673 struct mri_control_info *n;
6674
6675 /* A structured control directive must end with THEN with an
6676 optional qualifier. */
6677 s = input_line_pointer;
e1f44d10
NC		 6678 /* We only accept '*' as introduction of comments if preceded by white space
6679 or at first column of a line (I think this can't actually happen here?)
6680 This is important when assembling:
6681 if d0 <ne> 12(a0,d0*2) then
36759679 6682 if d0 <ne> #CONST*20 then. */
31302357
AS		 6683 while (! (is_end_of_line[(unsigned char) *s]
6684 || (flag_mri
6685 && *s == '*'
6686 && (s == input_line_pointer
6687 || *(s-1) == ' '
6688 || *(s-1) == '\t'))))
252b5132
RH		 6689 ++s;
6690 --s;
6691 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6692 --s;
6693
6694 if (s - input_line_pointer > 1
6695 && s[-1] == '.')
6696 s -= 2;
6697
6698 if (s - input_line_pointer < 3
6699 || strncasecmp (s - 3, "THEN", 4) != 0)
6700 {
6701 if (qual != '\0')
6702 {
6703 as_bad (_("missing then"));
6704 ignore_rest_of_line ();
6705 return;
6706 }
6707
6708 /* It's a conditional. */
6709 s_if (O_ne);
6710 return;
6711 }
6712
6713 /* Since this might be a conditional if, this pseudo-op will be
6714 called even if we are supported to be ignoring input. Double
6715 check now. Clobber *input_line_pointer so that ignore_input
6716 thinks that this is not a special pseudo-op. */
6717 c = *input_line_pointer;
6718 *input_line_pointer = 0;
6719 if (ignore_input ())
6720 {
6721 *input_line_pointer = c;
6722 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6723 ++input_line_pointer;
6724 demand_empty_rest_of_line ();
6725 return;
6726 }
6727 *input_line_pointer = c;
6728
6729 n = push_mri_control (mri_if);
6730
6731 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6732 n->next, s[1] == '.' ? s[2] : '\0');
6733
6734 if (s[1] == '.')
6735 input_line_pointer = s + 3;
6736 else
6737 input_line_pointer = s + 1;
6738
6739 if (flag_mri)
6740 {
6741 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6742 ++input_line_pointer;
6743 }
6744
6745 demand_empty_rest_of_line ();
6746}
6747
6748/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6749 structured IF, associate the ELSE with the IF. Otherwise, assume
6750 it is a conditional else. */
6751
6752static void
31302357 6753s_mri_else (int qual)
252b5132
RH		 6754{
6755 int c;
6756 char *buf;
6757 char q[2];
6758
6759 if (qual == '\0'
6760 && (mri_control_stack == NULL
6761 || mri_control_stack->type != mri_if
6762 || mri_control_stack->else_seen))
6763 {
6764 s_else (0);
6765 return;
6766 }
6767
6768 c = *input_line_pointer;
6769 *input_line_pointer = 0;
6770 if (ignore_input ())
6771 {
6772 *input_line_pointer = c;
6773 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6774 ++input_line_pointer;
6775 demand_empty_rest_of_line ();
6776 return;
6777 }
6778 *input_line_pointer = c;
6779
6780 if (mri_control_stack == NULL
6781 || mri_control_stack->type != mri_if
6782 || mri_control_stack->else_seen)
6783 {
6784 as_bad (_("else without matching if"));
6785 ignore_rest_of_line ();
6786 return;
6787 }
6788
6789 mri_control_stack->else_seen = 1;
6790
6791 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6792 q[0] = TOLOWER (qual);
252b5132
RH		 6793 q[1] = '\0';
6794 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6795 mri_assemble (buf);
6796 free (buf);
6797
6798 colon (mri_control_stack->next);
6799
6800 if (flag_mri)
6801 {
6802 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6803 ++input_line_pointer;
6804 }
6805
6806 demand_empty_rest_of_line ();
6807}
6808
6809/* Handle the MRI ENDI pseudo-op. */
6810
6811static void
31302357 6812s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6813{
6814 if (mri_control_stack == NULL
6815 || mri_control_stack->type != mri_if)
6816 {
6817 as_bad (_("endi without matching if"));
6818 ignore_rest_of_line ();
6819 return;
6820 }
6821
6822 /* ignore_input will not return true for ENDI, so we don't need to
6823 worry about checking it again here. */
6824
6825 if (! mri_control_stack->else_seen)
6826 colon (mri_control_stack->next);
6827 colon (mri_control_stack->bottom);
6828
6829 pop_mri_control ();
6830
6831 if (flag_mri)
6832 {
6833 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6834 ++input_line_pointer;
6835 }
6836
6837 demand_empty_rest_of_line ();
6838}
6839
6840/* Handle the MRI BREAK pseudo-op. */
6841
6842static void
31302357 6843s_mri_break (int extent)
252b5132
RH		 6844{
6845 struct mri_control_info *n;
6846 char *buf;
6847 char ex[2];
6848
6849 n = mri_control_stack;
6850 while (n != NULL
6851 && n->type != mri_for
6852 && n->type != mri_repeat
6853 && n->type != mri_while)
6854 n = n->outer;
6855 if (n == NULL)
6856 {
6857 as_bad (_("break outside of structured loop"));
6858 ignore_rest_of_line ();
6859 return;
6860 }
6861
6862 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6863 ex[0] = TOLOWER (extent);
252b5132
RH		 6864 ex[1] = '\0';
6865 sprintf (buf, "bra%s %s", ex, n->bottom);
6866 mri_assemble (buf);
6867 free (buf);
6868
6869 if (flag_mri)
6870 {
6871 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6872 ++input_line_pointer;
6873 }
6874
6875 demand_empty_rest_of_line ();
6876}
6877
6878/* Handle the MRI NEXT pseudo-op. */
6879
6880static void
31302357 6881s_mri_next (int extent)
252b5132
RH		 6882{
6883 struct mri_control_info *n;
6884 char *buf;
6885 char ex[2];
6886
6887 n = mri_control_stack;
6888 while (n != NULL
6889 && n->type != mri_for
6890 && n->type != mri_repeat
6891 && n->type != mri_while)
6892 n = n->outer;
6893 if (n == NULL)
6894 {
6895 as_bad (_("next outside of structured loop"));
6896 ignore_rest_of_line ();
6897 return;
6898 }
6899
6900 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6901 ex[0] = TOLOWER (extent);
252b5132
RH		 6902 ex[1] = '\0';
6903 sprintf (buf, "bra%s %s", ex, n->next);
6904 mri_assemble (buf);
6905 free (buf);
6906
6907 if (flag_mri)
6908 {
6909 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6910 ++input_line_pointer;
6911 }
6912
6913 demand_empty_rest_of_line ();
6914}
6915
6916/* Handle the MRI FOR pseudo-op. */
6917
6918static void
31302357 6919s_mri_for (int qual)
252b5132
RH		 6920{
6921 const char *varstart, *varstop;
6922 const char *initstart, *initstop;
6923 const char *endstart, *endstop;
6924 const char *bystart, *bystop;
6925 int up;
6926 int by;
6927 int extent;
6928 struct mri_control_info *n;
6929 char *buf;
6930 char *s;
6931 char ex[2];
6932
6933 /* The syntax is
6934 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6935 */
6936
6937 SKIP_WHITESPACE ();
6938 varstart = input_line_pointer;
6939
6940 /* Look for the '='. */
6941 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6942 && *input_line_pointer != '=')
6943 ++input_line_pointer;
6944 if (*input_line_pointer != '=')
6945 {
6946 as_bad (_("missing ="));
6947 ignore_rest_of_line ();
6948 return;
6949 }
6950
6951 varstop = input_line_pointer;
6952 if (varstop > varstart
6953 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6954 --varstop;
6955
6956 ++input_line_pointer;
6957
6958 initstart = input_line_pointer;
6959
6960 /* Look for TO or DOWNTO. */
6961 up = 1;
6962 initstop = NULL;
6963 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6964 {
6965 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6966 && ! is_part_of_name (input_line_pointer[2]))
6967 {
6968 initstop = input_line_pointer;
6969 input_line_pointer += 2;
6970 break;
6971 }
6972 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6973 && ! is_part_of_name (input_line_pointer[6]))
6974 {
6975 initstop = input_line_pointer;
6976 up = 0;
6977 input_line_pointer += 6;
6978 break;
6979 }
6980 ++input_line_pointer;
6981 }
6982 if (initstop == NULL)
6983 {
6984 as_bad (_("missing to or downto"));
6985 ignore_rest_of_line ();
6986 return;
6987 }
6988 if (initstop > initstart
6989 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6990 --initstop;
6991
6992 SKIP_WHITESPACE ();
6993 endstart = input_line_pointer;
6994
6995 /* Look for BY or DO. */
6996 by = 0;
6997 endstop = NULL;
6998 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6999 {
7000 if (strncasecmp (input_line_pointer, "BY", 2) == 0
7001 && ! is_part_of_name (input_line_pointer[2]))
7002 {
7003 endstop = input_line_pointer;
7004 by = 1;
7005 input_line_pointer += 2;
7006 break;
7007 }
7008 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7009 && (input_line_pointer[2] == '.'
7010 || ! is_part_of_name (input_line_pointer[2])))
7011 {
7012 endstop = input_line_pointer;
7013 input_line_pointer += 2;
7014 break;
7015 }
7016 ++input_line_pointer;
7017 }
7018 if (endstop == NULL)
7019 {
7020 as_bad (_("missing do"));
7021 ignore_rest_of_line ();
7022 return;
7023 }
7024 if (endstop > endstart
7025 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
7026 --endstop;
7027
7028 if (! by)
7029 {
7030 bystart = "#1";
7031 bystop = bystart + 2;
7032 }
7033 else
7034 {
7035 SKIP_WHITESPACE ();
7036 bystart = input_line_pointer;
7037
7038 /* Look for DO. */
7039 bystop = NULL;
7040 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7041 {
7042 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7043 && (input_line_pointer[2] == '.'
7044 || ! is_part_of_name (input_line_pointer[2])))
7045 {
7046 bystop = input_line_pointer;
7047 input_line_pointer += 2;
7048 break;
7049 }
7050 ++input_line_pointer;
7051 }
7052 if (bystop == NULL)
7053 {
7054 as_bad (_("missing do"));
7055 ignore_rest_of_line ();
7056 return;
7057 }
7058 if (bystop > bystart
7059 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
7060 --bystop;
7061 }
7062
7063 if (*input_line_pointer != '.')
7064 extent = '\0';
7065 else
7066 {
7067 extent = input_line_pointer[1];
7068 input_line_pointer += 2;
7069 }
7070
7071 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 7072 n = push_mri_control (mri_for);
7073
7074 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
7075
36759679 7076 /* Move init,var. */
252b5132
RH		 7077 s = buf;
7078 *s++ = 'm';
7079 *s++ = 'o';
7080 *s++ = 'v';
7081 *s++ = 'e';
7082 if (qual != '\0')
3882b010 7083 *s++ = TOLOWER (qual);
252b5132
RH		 7084 *s++ = ' ';
7085 memcpy (s, initstart, initstop - initstart);
7086 s += initstop - initstart;
7087 *s++ = ',';
7088 memcpy (s, varstart, varstop - varstart);
7089 s += varstop - varstart;
7090 *s = '\0';
7091 mri_assemble (buf);
7092
7093 colon (n->top);
7094
36759679 7095 /* cmp end,var. */
252b5132
RH		 7096 s = buf;
7097 *s++ = 'c';
7098 *s++ = 'm';
7099 *s++ = 'p';
7100 if (qual != '\0')
3882b010 7101 *s++ = TOLOWER (qual);
252b5132
RH		 7102 *s++ = ' ';
7103 memcpy (s, endstart, endstop - endstart);
7104 s += endstop - endstart;
7105 *s++ = ',';
7106 memcpy (s, varstart, varstop - varstart);
7107 s += varstop - varstart;
7108 *s = '\0';
7109 mri_assemble (buf);
7110
36759679 7111 /* bcc bottom. */
3882b010 7112 ex[0] = TOLOWER (extent);
252b5132
RH		 7113 ex[1] = '\0';
7114 if (up)
7115 sprintf (buf, "blt%s %s", ex, n->bottom);
7116 else
7117 sprintf (buf, "bgt%s %s", ex, n->bottom);
7118 mri_assemble (buf);
7119
7120 /* Put together the add or sub instruction used by ENDF. */
7121 s = buf;
7122 if (up)
7123 strcpy (s, "add");
7124 else
7125 strcpy (s, "sub");
7126 s += 3;
7127 if (qual != '\0')
3882b010 7128 *s++ = TOLOWER (qual);
252b5132
RH		 7129 *s++ = ' ';
7130 memcpy (s, bystart, bystop - bystart);
7131 s += bystop - bystart;
7132 *s++ = ',';
7133 memcpy (s, varstart, varstop - varstart);
7134 s += varstop - varstart;
7135 *s = '\0';
7136 n->incr = buf;
7137
7138 if (flag_mri)
7139 {
7140 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7141 ++input_line_pointer;
7142 }
7143
7144 demand_empty_rest_of_line ();
7145}
7146
7147/* Handle the MRI ENDF pseudo-op. */
7148
7149static void
31302357 7150s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7151{
7152 if (mri_control_stack == NULL
7153 || mri_control_stack->type != mri_for)
7154 {
7155 as_bad (_("endf without for"));
7156 ignore_rest_of_line ();
7157 return;
7158 }
7159
7160 colon (mri_control_stack->next);
7161
7162 mri_assemble (mri_control_stack->incr);
7163
7164 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7165 mri_assemble (mri_control_stack->incr);
7166
7167 free (mri_control_stack->incr);
7168
7169 colon (mri_control_stack->bottom);
7170
7171 pop_mri_control ();
7172
7173 if (flag_mri)
7174 {
7175 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7176 ++input_line_pointer;
7177 }
7178
7179 demand_empty_rest_of_line ();
7180}
7181
7182/* Handle the MRI REPEAT pseudo-op. */
7183
7184static void
31302357 7185s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7186{
7187 struct mri_control_info *n;
7188
7189 n = push_mri_control (mri_repeat);
7190 colon (n->top);
7191 if (flag_mri)
7192 {
7193 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7194 ++input_line_pointer;
7195 }
7196 demand_empty_rest_of_line ();
7197}
7198
7199/* Handle the MRI UNTIL pseudo-op. */
7200
7201static void
31302357 7202s_mri_until (int qual)
252b5132
RH		 7203{
7204 char *s;
7205
7206 if (mri_control_stack == NULL
7207 || mri_control_stack->type != mri_repeat)
7208 {
7209 as_bad (_("until without repeat"));
7210 ignore_rest_of_line ();
7211 return;
7212 }
7213
7214 colon (mri_control_stack->next);
7215
7216 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7217 ;
7218
7219 parse_mri_control_expression (s, qual, (const char *) NULL,
7220 mri_control_stack->top, '\0');
7221
7222 colon (mri_control_stack->bottom);
7223
7224 input_line_pointer = s;
7225
7226 pop_mri_control ();
7227
7228 if (flag_mri)
7229 {
7230 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7231 ++input_line_pointer;
7232 }
7233
7234 demand_empty_rest_of_line ();
7235}
7236
7237/* Handle the MRI WHILE pseudo-op. */
7238
7239static void
31302357 7240s_mri_while (int qual)
252b5132
RH		 7241{
7242 char *s;
7243
7244 struct mri_control_info *n;
7245
7246 s = input_line_pointer;
e1f44d10
NC		 7247 /* We only accept '*' as introduction of comments if preceded by white space
7248 or at first column of a line (I think this can't actually happen here?)
7249 This is important when assembling:
7250 while d0 <ne> 12(a0,d0*2) do
36759679 7251 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7252 while (! (is_end_of_line[(unsigned char) *s]
7253 || (flag_mri
7254 && *s == '*'
7255 && (s == input_line_pointer
7256 || *(s-1) == ' '
7257 || *(s-1) == '\t'))))
252b5132
RH		 7258 s++;
7259 --s;
7260 while (*s == ' ' || *s == '\t')
7261 --s;
7262 if (s - input_line_pointer > 1
7263 && s[-1] == '.')
7264 s -= 2;
7265 if (s - input_line_pointer < 2
7266 || strncasecmp (s - 1, "DO", 2) != 0)
7267 {
7268 as_bad (_("missing do"));
7269 ignore_rest_of_line ();
7270 return;
7271 }
7272
7273 n = push_mri_control (mri_while);
7274
7275 colon (n->next);
7276
7277 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7278 s[1] == '.' ? s[2] : '\0');
7279
7280 input_line_pointer = s + 1;
7281 if (*input_line_pointer == '.')
7282 input_line_pointer += 2;
7283
7284 if (flag_mri)
7285 {
7286 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7287 ++input_line_pointer;
7288 }
7289
7290 demand_empty_rest_of_line ();
7291}
7292
7293/* Handle the MRI ENDW pseudo-op. */
7294
7295static void
31302357 7296s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7297{
7298 char *buf;
7299
7300 if (mri_control_stack == NULL
7301 || mri_control_stack->type != mri_while)
7302 {
7303 as_bad (_("endw without while"));
7304 ignore_rest_of_line ();
7305 return;
7306 }
7307
7308 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7309 sprintf (buf, "bra %s", mri_control_stack->next);
7310 mri_assemble (buf);
7311 free (buf);
7312
7313 colon (mri_control_stack->bottom);
7314
7315 pop_mri_control ();
7316
7317 if (flag_mri)
7318 {
7319 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7320 ++input_line_pointer;
7321 }
7322
7323 demand_empty_rest_of_line ();
7324}
7325\f
266abb8f
NS		 7326/* Parse a .cpu directive. */
7327
7328static void
7329s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7330{
7331 char saved_char;
7332 char *name;
7333
7334 if (initialized)
7335 {
7336 as_bad (_("already assembled instructions"));
7337 ignore_rest_of_line ();
7338 return;
7339 }
7340
7341 name = input_line_pointer;
7342 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7343 input_line_pointer++;
7344 saved_char = *input_line_pointer;
7345 *input_line_pointer = 0;
7346
7347 m68k_set_cpu (name, 1, 0);
7348
7349 *input_line_pointer = saved_char;
7350 demand_empty_rest_of_line ();
7351 return;
7352}
7353
7354/* Parse a .arch directive. */
7355
7356static void
7357s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7358{
7359 char saved_char;
7360 char *name;
7361
7362 if (initialized)
7363 {
7364 as_bad (_("already assembled instructions"));
7365 ignore_rest_of_line ();
7366 return;
7367 }
7368
7369 name = input_line_pointer;
7370 while (*input_line_pointer && *input_line_pointer != ','
7371 && !ISSPACE (*input_line_pointer))
7372 input_line_pointer++;
7373 saved_char = *input_line_pointer;
7374 *input_line_pointer = 0;
7375
7376 if (m68k_set_arch (name, 1, 0))
7377 {
7378 /* Scan extensions. */
7379 do
7380 {
7381 *input_line_pointer++ = saved_char;
7382 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7383 break;
7384 name = input_line_pointer;
7385 while (*input_line_pointer && *input_line_pointer != ','
7386 && !ISSPACE (*input_line_pointer))
7387 input_line_pointer++;
7388 saved_char = *input_line_pointer;
7389 *input_line_pointer = 0;
7390 }
7391 while (m68k_set_extension (name, 1, 0));
7392 }
7393
7394 *input_line_pointer = saved_char;
7395 demand_empty_rest_of_line ();
7396 return;
7397}
7398\f
7399/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7400 if none is found, the caller is responsible for emitting an error
7401 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7402 cpu name, if it begins with a '6' (possibly skipping an intervening
7403 'c'. We also allow a 'c' in the same place. if NEGATED is
7404 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7405 the option is indeed negated. */
7406
7407static const struct m68k_cpu *
7408m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7409 int allow_m, int *negated)
7410{
7411 /* allow negated value? */
7412 if (negated)
7413 {
7414 *negated = 0;
7415
7416 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7417 {
7418 arg += 3;
7419 *negated = 1;
7420 }
7421 }
7422
7423 /* Remove 'm' or 'mc' prefix from 68k variants. */
7424 if (allow_m)
7425 {
7426 if (arg[0] == 'm')
7427 {
7428 if (arg[1] == '6')
7429 arg += 1;
7430 else if (arg[1] == 'c' && arg[2] == '6')
7431 arg += 2;
7432 }
7433 }
7434 else if (arg[0] == 'c' && arg[1] == '6')
7435 arg += 1;
7436
7437 for (; table->name; table++)
7438 if (!strcmp (arg, table->name))
2da12c60
NS		 7439 {
7440 if (table->alias < -1 || table->alias > 1)
7441 as_bad (_("`%s' is deprecated, use `%s'"),
7442 table->name, table[table->alias < 0 ? 1 : -1].name);
7443 return table;
7444 }
266abb8f
NS		 7445 return 0;
7446}
7447
bfbba8e4 7448/* Set the cpu, issuing errors if it is unrecognized. */
266abb8f
NS		 7449
7450static int
7451m68k_set_cpu (char const *name, int allow_m, int silent)
7452{
7453 const struct m68k_cpu *cpu;
7454
7455 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7456
7457 if (!cpu)
7458 {
7459 if (!silent)
7460 as_bad (_("cpu `%s' unrecognized"), name);
7461 return 0;
7462 }
266abb8f
NS		 7463 selected_cpu = cpu;
7464 return 1;
7465}
7466
bfbba8e4 7467/* Set the architecture, issuing errors if it is unrecognized. */
266abb8f
NS		 7468
7469static int
7470m68k_set_arch (char const *name, int allow_m, int silent)
7471{
7472 const struct m68k_cpu *arch;
7473
7474 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7475
7476 if (!arch)
7477 {
7478 if (!silent)
7479 as_bad (_("architecture `%s' unrecognized"), name);
7480 return 0;
7481 }
266abb8f
NS		 7482 selected_arch = arch;
7483 return 1;
7484}
7485
7486/* Set the architecture extension, issuing errors if it is
7487 unrecognized, or invalid */
7488
7489static int
7490m68k_set_extension (char const *name, int allow_m, int silent)
7491{
7492 int negated;
7493 const struct m68k_cpu *ext;
7494
7495 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7496
7497 if (!ext)
7498 {
7499 if (!silent)
7500 as_bad (_("extension `%s' unrecognized"), name);
7501 return 0;
7502 }
7503
7504 if (negated)
87298967
NS		 7505 not_current_architecture |= (ext->control_regs
7506 ? *(unsigned *)ext->control_regs: ext->arch);
266abb8f
NS		 7507 else
7508 current_architecture |= ext->arch;
7509 return 1;
7510}
7511
31302357
AS		 7512/* md_parse_option
7513 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7514 */
252b5132
RH		 7515
7516#ifdef OBJ_ELF
5a38dc70 7517const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7518#else
5a38dc70 7519const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7520#endif
7521
7522struct option md_longopts[] = {
7523#define OPTION_PIC (OPTION_MD_BASE)
7524 {"pic", no_argument, NULL, OPTION_PIC},
7525#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7526 {"register-prefix-optional", no_argument, NULL,
7527 OPTION_REGISTER_PREFIX_OPTIONAL},
7528#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7529 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7530#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7531 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7532#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7533 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7534#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7535 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7536#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7537 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7538#define OPTION_PCREL (OPTION_MD_BASE + 7)
7539 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7540 {NULL, no_argument, NULL, 0}
7541};
bc805888 7542size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7543
7544int
31302357 7545md_parse_option (int c, char *arg)
252b5132
RH		 7546{
7547 switch (c)
7548 {
7549 case 'l': /* -l means keep external to 2 bit offset
36759679 7550 rather than 16 bit one. */
252b5132
RH		 7551 flag_short_refs = 1;
7552 break;
7553
7554 case 'S': /* -S means that jbsr's always turn into
7555 jsr's. */
7556 flag_long_jumps = 1;
7557 break;
7558
28e7409f
NC		 7559 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7560 branches into absolute jumps. */
7561 flag_keep_pcrel = 1;
7562 break;
7563
252b5132
RH		 7564 case OPTION_PIC:
7565 case 'k':
7566 flag_want_pic = 1;
36759679 7567 break; /* -pic, Position Independent Code. */
252b5132
RH		 7568
7569 case OPTION_REGISTER_PREFIX_OPTIONAL:
7570 flag_reg_prefix_optional = 1;
7571 reg_prefix_optional_seen = 1;
7572 break;
7573
7574 /* -V: SVR4 argument to print version ID. */
7575 case 'V':
7576 print_version_id ();
7577 break;
7578
7579 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7580 should be emitted or not. FIXME: Not implemented. */
7581 case 'Q':
7582 break;
7583
7584 case OPTION_BITWISE_OR:
7585 {
7586 char *n, *t;
7587 const char *s;
7588
7589 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7590 t = n;
7591 for (s = m68k_comment_chars; *s != '\0'; s++)
7592 if (*s != '|')
7593 *t++ = *s;
7594 *t = '\0';
7595 m68k_comment_chars = n;
7596 }
7597 break;
7598
7599 case OPTION_BASE_SIZE_DEFAULT_16:
7600 m68k_index_width_default = SIZE_WORD;
7601 break;
7602
7603 case OPTION_BASE_SIZE_DEFAULT_32:
7604 m68k_index_width_default = SIZE_LONG;
7605 break;
7606
7607 case OPTION_DISP_SIZE_DEFAULT_16:
7608 m68k_rel32 = 0;
7609 m68k_rel32_from_cmdline = 1;
7610 break;
7611
7612 case OPTION_DISP_SIZE_DEFAULT_32:
7613 m68k_rel32 = 1;
7614 m68k_rel32_from_cmdline = 1;
7615 break;
7616
266abb8f
NS		 7617 case 'A':
7618#if WARN_DEPRECATED
7619 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7620 arg, arg));
7621#endif
7622 /* Intentional fall-through. */
7623 case 'm':
7624 if (!strncmp (arg, "arch=", 5))
7625 m68k_set_arch (arg + 5, 1, 0);
7626 else if (!strncmp (arg, "cpu=", 4))
7627 m68k_set_cpu (arg + 4, 1, 0);
7628 else if (m68k_set_extension (arg, 0, 1))
7629 ;
0b2e31dc
NS		 7630 else if (m68k_set_arch (arg, 0, 1))
7631 ;
266abb8f
NS		 7632 else if (m68k_set_cpu (arg, 0, 1))
7633 ;
7634 else
7635 return 0;
7636 break;
7637
252b5132
RH		 7638 default:
7639 return 0;
7640 }
7641
7642 return 1;
7643}
7644
266abb8f
NS		 7645/* Setup tables from the selected arch and/or cpu */
7646
7647static void
7648m68k_init_arch (void)
7649{
266abb8f
NS		 7650 if (not_current_architecture & current_architecture)
7651 {
7652 as_bad (_("architecture features both enabled and disabled"));
7653 not_current_architecture &= ~current_architecture;
7654 }
7655 if (selected_arch)
2da12c60
NS		 7656 {
7657 current_architecture |= selected_arch->arch;
7658 control_regs = selected_arch->control_regs;
7659 }
0b2e31dc
NS		 7660 else
7661 current_architecture |= selected_cpu->arch;
0b2e31dc 7662
2da12c60
NS		 7663 current_architecture &= ~not_current_architecture;
7664
377260ba
NS		 7665 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7666 {
7667 /* Determine which float is really meant. */
7668 if (current_architecture & (m68k_mask & ~m68881))
7669 current_architecture ^= cfloat;
7670 else
7671 current_architecture ^= m68881;
7672 }
7673
0b2e31dc 7674 if (selected_cpu)
266abb8f 7675 {
2da12c60 7676 control_regs = selected_cpu->control_regs;
0b2e31dc 7677 if (current_architecture & ~selected_cpu->arch)
266abb8f 7678 {
0b2e31dc
NS		 7679 as_bad (_("selected processor does not have all features of selected architecture"));
7680 current_architecture
7681 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7682 }
7683 }
266abb8f 7684
266abb8f
NS		 7685 if ((current_architecture & m68k_mask)
7686 && (current_architecture & ~m68k_mask))
7687 {
7688 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7689 if (current_architecture & m68k_mask)
266abb8f
NS		 7690 current_architecture &= m68k_mask;
7691 else
7692 current_architecture &= ~m68k_mask;
7693 }
7694
7695 /* Permit m68881 specification with all cpus; those that can't work
7696 with a coprocessor could be doing emulation. */
7697 if (current_architecture & m68851)
7698 {
7699 if (current_architecture & m68040)
7700 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7701 }
7702 /* What other incompatibilities could we check for? */
7703
266abb8f
NS		 7704 if (cpu_of_arch (current_architecture) < m68020
7705 || arch_coldfire_p (current_architecture))
7706 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7707
7708 initialized = 1;
7709}
7710
252b5132 7711void
31302357 7712md_show_usage (FILE *stream)
252b5132 7713{
76f57f3a 7714 const char *default_cpu = TARGET_CPU;
f1f5ef86 7715 int i;
76f57f3a 7716
8a104df9 7717 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7718 if (*default_cpu == 'm')
7719 default_cpu++;
266abb8f 7720 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7721 {
266abb8f 7722 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7723 {
2da12c60
NS		 7724 while (m68k_cpus[i].alias > 0)
7725 i--;
7726 while (m68k_cpus[i].alias < 0)
7727 i++;
7728 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7729 }
7730 }
7731
bc805888 7732 fprintf (stream, _("\
266abb8f
NS		 7733-march=<arch> set architecture\n\
7734-mcpu=<cpu> set cpu [default %s]\n\
7735"), default_cpu);
7736 for (i = 0; m68k_extensions[i].name; i++)
7737 fprintf (stream, _("\
0b2e31dc
NS		 7738-m[no-]%-16s enable/disable%s architecture extension\n\
7739"), m68k_extensions[i].name,
7740 m68k_extensions[i].alias > 0 ? " ColdFire"
7741 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7742
bc805888 7743 fprintf (stream, _("\
266abb8f 7744-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7745-pic, -k generate position independent code\n\
7746-S turn jbsr into jsr\n\
28e7409f 7747--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7748--register-prefix-optional\n\
7749 recognize register names without prefix character\n\
266abb8f 7750--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7751--base-size-default-16 base reg without size is 16 bits\n\
7752--base-size-default-32 base reg without size is 32 bits (default)\n\
7753--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7754--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7755"));
7756
7757 fprintf (stream, _("Architecture variants are: "));
7758 for (i = 0; m68k_archs[i].name; i++)
7759 {
7760 if (i)
7761 fprintf (stream, " | ");
87298967 7762 fprintf (stream, "%s", m68k_archs[i].name);
266abb8f
NS		 7763 }
7764 fprintf (stream, "\n");
7765
7766 fprintf (stream, _("Processor variants are: "));
7767 for (i = 0; m68k_cpus[i].name; i++)
7768 {
7769 if (i)
7770 fprintf (stream, " | ");
87298967 7771 fprintf (stream, "%s", m68k_cpus[i].name);
266abb8f
NS		 7772 }
7773 fprintf (stream, _("\n"));
252b5132
RH		 7774}
7775\f
7776#ifdef TEST2
7777
7778/* TEST2: Test md_assemble() */
36759679
NC		 7779/* Warning, this routine probably doesn't work anymore. */
7780int
31302357 7781main (void)
252b5132
RH		 7782{
7783 struct m68k_it the_ins;
7784 char buf[120];
7785 char *cp;
7786 int n;
7787
7788 m68k_ip_begin ();
7789 for (;;)
7790 {
7791 if (!gets (buf) || !*buf)
7792 break;
7793 if (buf[0] == '|' || buf[1] == '.')
7794 continue;
7795 for (cp = buf; *cp; cp++)
7796 if (*cp == '\t')
7797 *cp = ' ';
7798 if (is_label (buf))
7799 continue;
7800 memset (&the_ins, '\0', sizeof (the_ins));
7801 m68k_ip (&the_ins, buf);
7802 if (the_ins.error)
7803 {
7804 printf (_("Error %s in %s\n"), the_ins.error, buf);
7805 }
7806 else
7807 {
7808 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7809 for (n = 0; n < the_ins.numo; n++)
7810 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7811 printf (" ");
7812 print_the_insn (&the_ins.opcode[0], stdout);
7813 (void) putchar ('\n');
7814 }
7815 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7816 {
7817 if (the_ins.operands[n].error)
7818 {
7819 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7820 continue;
7821 }
31302357
AS		 7822 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7823 the_ins.operands[n].reg);
252b5132 7824 if (the_ins.operands[n].b_const)
31302357
AS		 7825 printf ("Constant: '%.*s', ",
7826 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7827 the_ins.operands[n].b_const);
7828 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7829 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7830 if (the_ins.operands[n].b_iadd)
31302357
AS		 7831 printf ("Iadd: '%.*s',",
7832 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7833 the_ins.operands[n].b_iadd);
7834 putchar ('\n');
252b5132
RH		 7835 }
7836 }
7837 m68k_ip_end ();
7838 return 0;
7839}
7840
31302357
AS		 7841int
7842is_label (char *str)
252b5132
RH		 7843{
7844 while (*str == ' ')
7845 str++;
7846 while (*str && *str != ' ')
7847 str++;
7848 if (str[-1] == ':' || str[1] == '=')
7849 return 1;
7850 return 0;
7851}
7852
7853#endif
7854
7855/* Possible states for relaxation:
7856
7857 0 0 branch offset byte (bra, etc)
7858 0 1 word
7859 0 2 long
7860
7861 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7862 1 1 word
7863 1 2 long
7864
7865 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7866 2 1 word-long
7867 2 2 long-word
7868 2 3 long-long
7869
7870 */
7871
7872/* We have no need to default values of symbols. */
7873
252b5132 7874symbolS *
31302357 7875md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7876{
7877 return 0;
7878}
7879
7880/* Round up a section size to the appropriate boundary. */
7881valueT
31302357 7882md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7883{
7884#ifdef OBJ_AOUT
252b5132
RH		 7885 /* For a.out, force the section size to be aligned. If we don't do
7886 this, BFD will align it for us, but it will not write out the
7887 final bytes of the section. This may be a bug in BFD, but it is
7888 easier to fix it here since that is how the other a.out targets
7889 work. */
7890 int align;
7891
7892 align = bfd_get_section_alignment (stdoutput, segment);
7893 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7894#endif
7895
7896 return size;
7897}
7898
7899/* Exactly what point is a PC-relative offset relative TO?
7900 On the 68k, it is relative to the address of the first extension
7901 word. The difference between the addresses of the offset and the
92774660 7902 first extension word is stored in fx_pcrel_adjust. */
252b5132 7903long
31302357 7904md_pcrel_from (fixS *fixP)
252b5132
RH		 7905{
7906 int adjust;
7907
8390138c
AS		 7908 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7909 sign extend the value here. */
7910 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7911 if (adjust == 64)
7912 adjust = -1;
7913 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7914}
7915
0d96863f 7916#ifdef OBJ_ELF
8a104df9 7917void
31302357 7918m68k_elf_final_processing (void)
0d96863f 7919{
266abb8f
NS		 7920 unsigned flags = 0;
7921
238d258f 7922 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7923 flags |= EF_M68K_CFV4E;
7924 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7925 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7926 flags |= EF_M68K_CPU32;
7927 else if (cpu_of_arch (current_architecture) & fido_a)
7928 flags |= EF_M68K_FIDO;
8a104df9
KH		 7929 else if ((cpu_of_arch (current_architecture) & m68000up)
7930 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7931 flags |= EF_M68K_M68000;
7932
7933 if (current_architecture & mcfisa_a)
7934 {
0b2e31dc
NS		 7935 static const unsigned isa_features[][2] =
7936 {
9a2e615a 7937 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7938 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7939 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7940 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7941 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7942 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
8d100c32 7943 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
0b2e31dc
NS		 7944 {0,0},
7945 };
7946 static const unsigned mac_features[][2] =
7947 {
c694fd50
KH		 7948 {EF_M68K_CF_MAC, mcfmac},
7949 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7950 {0,0},
7951 };
7952 unsigned ix;
7953 unsigned pattern;
266abb8f 7954
0b2e31dc 7955 pattern = (current_architecture
9a2e615a 7956 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7957 for (ix = 0; isa_features[ix][1]; ix++)
7958 {
7959 if (pattern == isa_features[ix][1])
7960 {
7961 flags |= isa_features[ix][0];
7962 break;
7963 }
7964 }
7965 if (!isa_features[ix][1])
7966 {
7967 cf_bad:
7968 as_warn (_("Not a defined coldfire architecture"));
7969 }
7970 else
7971 {
7972 if (current_architecture & cfloat)
c694fd50 7973 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7974
0b2e31dc
NS		 7975 pattern = current_architecture & (mcfmac|mcfemac);
7976 if (pattern)
7977 {
7978 for (ix = 0; mac_features[ix][1]; ix++)
7979 {
7980 if (pattern == mac_features[ix][1])
7981 {
7982 flags |= mac_features[ix][0];
7983 break;
7984 }
7985 }
7986 if (!mac_features[ix][1])
7987 goto cf_bad;
7988 }
7989 }
266abb8f
NS		 7990 }
7991 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f 7992}
cf869cce
NC		 7993
7994/* Parse @TLSLDO and return the desired relocation. */
7995static bfd_reloc_code_real_type
7996m68k_elf_suffix (char **str_p, expressionS *exp_p)
7997{
7998 char ident[20];
7999 char *str = *str_p;
8000 char *str2;
8001 int ch;
8002 int len;
8003
8004 if (*str++ != '@')
8005 return BFD_RELOC_UNUSED;
8006
8007 for (ch = *str, str2 = ident;
8008 (str2 < ident + sizeof (ident) - 1
8009 && (ISALNUM (ch) || ch == '@'));
8010 ch = *++str)
8011 {
8012 *str2++ = ch;
8013 }
8014
8015 *str2 = '\0';
8016 len = str2 - ident;
8017
8018 if (strncmp (ident, "TLSLDO", 6) == 0
8019 && len == 6)
8020 {
8021 /* Now check for identifier@suffix+constant. */
8022 if (*str == '-' || *str == '+')
8023 {
8024 char *orig_line = input_line_pointer;
8025 expressionS new_exp;
8026
8027 input_line_pointer = str;
8028 expression (&new_exp);
8029 if (new_exp.X_op == O_constant)
8030 {
8031 exp_p->X_add_number += new_exp.X_add_number;
8032 str = input_line_pointer;
8033 }
8034
8035 if (&input_line_pointer != str_p)
8036 input_line_pointer = orig_line;
8037 }
8038 *str_p = str;
8039
8040 return BFD_RELOC_68K_TLS_LDO32;
8041 }
8042
8043 return BFD_RELOC_UNUSED;
8044}
8045
8046/* Handles .long <tls_symbol>+0x8000 debug info.
8047 Clobbers input_line_pointer, checks end-of-line.
8048 Adapted from tc-ppc.c:ppc_elf_cons. */
8049static void
8050m68k_elf_cons (int nbytes /* 4=.long */)
8051{
8052 if (is_it_end_of_statement ())
8053 {
8054 demand_empty_rest_of_line ();
8055 return;
8056 }
8057
8058 do
8059 {
8060 expressionS exp;
8061 bfd_reloc_code_real_type reloc;
8062
8063 expression (&exp);
8064 if (exp.X_op == O_symbol
8065 && *input_line_pointer == '@'
8066 && (reloc = m68k_elf_suffix (&input_line_pointer,
8067 &exp)) != BFD_RELOC_UNUSED)
8068 {
8069 reloc_howto_type *reloc_howto;
8070 int size;
8071
8072 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
8073 size = bfd_get_reloc_size (reloc_howto);
8074
8075 if (size > nbytes)
8076 {
8077 as_bad (_("%s relocations do not fit in %d bytes\n"),
8078 reloc_howto->name, nbytes);
8079 }
8080 else
8081 {
8082 char *p;
8083 int offset;
8084
8085 p = frag_more (nbytes);
8086 offset = 0;
8087 if (target_big_endian)
8088 offset = nbytes - size;
8089 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8090 &exp, 0, reloc);
8091 }
8092 }
8093 else
8094 emit_expr (&exp, (unsigned int) nbytes);
8095 }
8096 while (*input_line_pointer++ == ',');
8097
8098 /* Put terminator back into stream. */
8099 input_line_pointer--;
8100 demand_empty_rest_of_line ();
8101}
0d96863f 8102#endif
c04898f8
AS		 8103
8104int
1df69f4f 8105tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 8106{
8107 unsigned int regnum;
8108 static const char *const regnames[] =
8109 {
8110 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8111 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8112 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8113 "pc"
8114 };
8115
8116 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
8117 if (strcmp (regname, regnames[regnum]) == 0)
8118 return regnum;
8119
8120 return -1;
8121}
8122
8123void
8124tc_m68k_frame_initial_instructions (void)
8125{
8126 static int sp_regno = -1;
8127
8128 if (sp_regno < 0)
8129 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8130
8131 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8132 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
8133}
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