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d87bef3a | 1 | @c Copyright (C) 1991-2023 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
731caf76 L |
4 | @c man end |
5 | ||
252b5132 RH |
6 | @ifset GENERIC |
7 | @page | |
8 | @node i386-Dependent | |
9 | @chapter 80386 Dependent Features | |
10 | @end ifset | |
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter 80386 Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex i386 support | |
b6169b20 | 17 | @cindex i80386 support |
55b62671 AJ |
18 | @cindex x86-64 support |
19 | ||
20 | The i386 version @code{@value{AS}} supports both the original Intel 386 | |
21 | architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture | |
22 | extending the Intel architecture to 64-bits. | |
23 | ||
252b5132 RH |
24 | @menu |
25 | * i386-Options:: Options | |
a6c24e68 | 26 | * i386-Directives:: X86 specific directives |
7c31ae13 | 27 | * i386-Syntax:: Syntactical considerations |
252b5132 RH |
28 | * i386-Mnemonics:: Instruction Naming |
29 | * i386-Regs:: Register Naming | |
30 | * i386-Prefixes:: Instruction Prefixes | |
31 | * i386-Memory:: Memory References | |
fddf5b5b | 32 | * i386-Jumps:: Handling of Jump Instructions |
252b5132 RH |
33 | * i386-Float:: Floating Point |
34 | * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations | |
f88c9eb0 | 35 | * i386-LWP:: AMD's Lightweight Profiling Instructions |
87973e9f | 36 | * i386-BMI:: Bit Manipulation Instruction |
2a2a0f38 | 37 | * i386-TBM:: AMD's Trailing Bit Manipulation Instructions |
252b5132 | 38 | * i386-16bit:: Writing 16-bit Code |
e413e4e9 | 39 | * i386-Arch:: Specifying an x86 CPU architecture |
bc31405e | 40 | * i386-ISA:: AMD64 ISA vs. Intel64 ISA |
252b5132 RH |
41 | * i386-Bugs:: AT&T Syntax bugs |
42 | * i386-Notes:: Notes | |
43 | @end menu | |
44 | ||
45 | @node i386-Options | |
46 | @section Options | |
47 | ||
55b62671 AJ |
48 | @cindex options for i386 |
49 | @cindex options for x86-64 | |
50 | @cindex i386 options | |
34bca508 | 51 | @cindex x86-64 options |
55b62671 AJ |
52 | |
53 | The i386 version of @code{@value{AS}} has a few machine | |
54 | dependent options: | |
55 | ||
731caf76 L |
56 | @c man begin OPTIONS |
57 | @table @gcctabopt | |
55b62671 AJ |
58 | @cindex @samp{--32} option, i386 |
59 | @cindex @samp{--32} option, x86-64 | |
570561f7 L |
60 | @cindex @samp{--x32} option, i386 |
61 | @cindex @samp{--x32} option, x86-64 | |
55b62671 AJ |
62 | @cindex @samp{--64} option, i386 |
63 | @cindex @samp{--64} option, x86-64 | |
570561f7 | 64 | @item --32 | --x32 | --64 |
35cc6a0b | 65 | Select the word size, either 32 bits or 64 bits. @samp{--32} |
570561f7 | 66 | implies Intel i386 architecture, while @samp{--x32} and @samp{--64} |
35cc6a0b L |
67 | imply AMD x86-64 architecture with 32-bit or 64-bit word-size |
68 | respectively. | |
55b62671 AJ |
69 | |
70 | These options are only available with the ELF object file format, and | |
71 | require that the necessary BFD support has been included (on a 32-bit | |
72 | platform you have to add --enable-64-bit-bfd to configure enable 64-bit | |
73 | usage and use x86-64 as target platform). | |
12b55ccc L |
74 | |
75 | @item -n | |
76 | By default, x86 GAS replaces multiple nop instructions used for | |
77 | alignment within code sections with multi-byte nop instructions such | |
f9233288 JW |
78 | as leal 0(%esi,1),%esi. This switch disables the optimization if a single |
79 | byte nop (0x90) is explicitly specified as the fill byte for alignment. | |
b3b91714 AM |
80 | |
81 | @cindex @samp{--divide} option, i386 | |
82 | @item --divide | |
83 | On SVR4-derived platforms, the character @samp{/} is treated as a comment | |
84 | character, which means that it cannot be used in expressions. The | |
85 | @samp{--divide} option turns @samp{/} into a normal character. This does | |
86 | not disable @samp{/} at the beginning of a line starting a comment, or | |
87 | affect using @samp{#} for starting a comment. | |
88 | ||
9103f4f4 L |
89 | @cindex @samp{-march=} option, i386 |
90 | @cindex @samp{-march=} option, x86-64 | |
6305a203 L |
91 | @item -march=@var{CPU}[+@var{EXTENSION}@dots{}] |
92 | This option specifies the target processor. The assembler will | |
93 | issue an error message if an attempt is made to assemble an instruction | |
94 | which will not execute on the target processor. The following | |
34bca508 | 95 | processor names are recognized: |
9103f4f4 L |
96 | @code{i8086}, |
97 | @code{i186}, | |
98 | @code{i286}, | |
99 | @code{i386}, | |
100 | @code{i486}, | |
101 | @code{i586}, | |
102 | @code{i686}, | |
103 | @code{pentium}, | |
104 | @code{pentiumpro}, | |
105 | @code{pentiumii}, | |
106 | @code{pentiumiii}, | |
107 | @code{pentium4}, | |
108 | @code{prescott}, | |
109 | @code{nocona}, | |
ef05d495 L |
110 | @code{core}, |
111 | @code{core2}, | |
bd5295b2 | 112 | @code{corei7}, |
81486035 | 113 | @code{iamcu}, |
9103f4f4 L |
114 | @code{k6}, |
115 | @code{k6_2}, | |
116 | @code{athlon}, | |
9103f4f4 L |
117 | @code{opteron}, |
118 | @code{k8}, | |
1ceab344 | 119 | @code{amdfam10}, |
68339fdf | 120 | @code{bdver1}, |
af2f724e | 121 | @code{bdver2}, |
5e5c50d3 | 122 | @code{bdver3}, |
c7b0bd56 | 123 | @code{bdver4}, |
029f3522 | 124 | @code{znver1}, |
a9660a6f | 125 | @code{znver2}, |
646cc3e0 | 126 | @code{znver3}, |
b0e8fa7f | 127 | @code{znver4}, |
7b458c12 L |
128 | @code{btver1}, |
129 | @code{btver2}, | |
9103f4f4 L |
130 | @code{generic32} and |
131 | @code{generic64}. | |
132 | ||
34bca508 | 133 | In addition to the basic instruction set, the assembler can be told to |
6305a203 L |
134 | accept various extension mnemonics. For example, |
135 | @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and | |
136 | @var{vmx}. The following extensions are currently supported: | |
309d3373 JB |
137 | @code{8087}, |
138 | @code{287}, | |
139 | @code{387}, | |
1848e567 | 140 | @code{687}, |
d871f3f4 | 141 | @code{cmov}, |
d871f3f4 | 142 | @code{fxsr}, |
6305a203 L |
143 | @code{mmx}, |
144 | @code{sse}, | |
145 | @code{sse2}, | |
146 | @code{sse3}, | |
af5c13b0 | 147 | @code{sse4a}, |
6305a203 L |
148 | @code{ssse3}, |
149 | @code{sse4.1}, | |
150 | @code{sse4.2}, | |
151 | @code{sse4}, | |
c0f3af97 | 152 | @code{avx}, |
6c30d220 | 153 | @code{avx2}, |
c3bb24f5 | 154 | @code{lahf_sahf}, |
cafa5ef7 | 155 | @code{monitor}, |
e2e1fcde L |
156 | @code{adx}, |
157 | @code{rdseed}, | |
158 | @code{prfchw}, | |
5c111e37 | 159 | @code{smap}, |
7e8b059b | 160 | @code{mpx}, |
a0046408 | 161 | @code{sha}, |
8bc52696 | 162 | @code{rdpid}, |
6b40c462 | 163 | @code{ptwrite}, |
603555e5 | 164 | @code{cet}, |
48521003 | 165 | @code{gfni}, |
8dcf1fad | 166 | @code{vaes}, |
ff1982d5 | 167 | @code{vpclmulqdq}, |
1dfc6506 L |
168 | @code{prefetchwt1}, |
169 | @code{clflushopt}, | |
170 | @code{se1}, | |
c5e7287a | 171 | @code{clwb}, |
c0a30a9f L |
172 | @code{movdiri}, |
173 | @code{movdir64b}, | |
5d79adc4 | 174 | @code{enqcmd}, |
4b27d27c | 175 | @code{serialize}, |
bb651e8b | 176 | @code{tsxldtrk}, |
c4694f17 | 177 | @code{kl}, |
c4694f17 | 178 | @code{widekl}, |
c1fa250a | 179 | @code{hreset}, |
43234a1e L |
180 | @code{avx512f}, |
181 | @code{avx512cd}, | |
182 | @code{avx512er}, | |
183 | @code{avx512pf}, | |
1dfc6506 L |
184 | @code{avx512vl}, |
185 | @code{avx512bw}, | |
186 | @code{avx512dq}, | |
2cc1b5aa | 187 | @code{avx512ifma}, |
14f195c9 | 188 | @code{avx512vbmi}, |
920d2ddc | 189 | @code{avx512_4fmaps}, |
47acf0bd | 190 | @code{avx512_4vnniw}, |
620214f7 | 191 | @code{avx512_vpopcntdq}, |
53467f57 | 192 | @code{avx512_vbmi2}, |
8cfcb765 | 193 | @code{avx512_vnni}, |
ee6872be | 194 | @code{avx512_bitalg}, |
708a2fff | 195 | @code{avx512_vp2intersect}, |
81d54bb7 | 196 | @code{tdx}, |
d6aab7a1 | 197 | @code{avx512_bf16}, |
58bf9b6a | 198 | @code{avx_vnni}, |
0cc78721 | 199 | @code{avx512_fp16}, |
ef07be45 | 200 | @code{prefetchi}, |
4321af3e | 201 | @code{avx_ifma}, |
23ae61ad | 202 | @code{avx_vnni_int8}, |
a93e3234 | 203 | @code{cmpccxadd}, |
941f0833 | 204 | @code{wrmsrns}, |
2188d6ea | 205 | @code{msrlist}, |
01d8ce74 | 206 | @code{avx_ne_convert}, |
b06311ad | 207 | @code{rao_int}, |
c88ed92f ZJ |
208 | @code{fred}, |
209 | @code{lkgs}, | |
260cd341 | 210 | @code{amx_int8}, |
260cd341 | 211 | @code{amx_bf16}, |
68830fba | 212 | @code{amx_fp16}, |
d100d8c1 | 213 | @code{amx_complex}, |
260cd341 | 214 | @code{amx_tile}, |
6305a203 | 215 | @code{vmx}, |
8729a6f6 | 216 | @code{vmfunc}, |
6305a203 | 217 | @code{smx}, |
f03fe4c1 | 218 | @code{xsave}, |
c7b8aa3a | 219 | @code{xsaveopt}, |
1dfc6506 L |
220 | @code{xsavec}, |
221 | @code{xsaves}, | |
c0f3af97 | 222 | @code{aes}, |
594ab6a3 | 223 | @code{pclmul}, |
c7b8aa3a L |
224 | @code{fsgsbase}, |
225 | @code{rdrnd}, | |
226 | @code{f16c}, | |
6c30d220 | 227 | @code{bmi2}, |
c0f3af97 | 228 | @code{fma}, |
f1f8f695 L |
229 | @code{movbe}, |
230 | @code{ept}, | |
6c30d220 | 231 | @code{lzcnt}, |
272a84b1 | 232 | @code{popcnt}, |
42164a71 L |
233 | @code{hle}, |
234 | @code{rtm}, | |
760ab3d0 | 235 | @code{tsx}, |
6c30d220 | 236 | @code{invpcid}, |
bd5295b2 | 237 | @code{clflush}, |
9916071f | 238 | @code{mwaitx}, |
029f3522 | 239 | @code{clzero}, |
3233d7d0 | 240 | @code{wbnoinvd}, |
be3a8dca | 241 | @code{pconfig}, |
de89d0a3 | 242 | @code{waitpkg}, |
f64c42a9 | 243 | @code{uintr}, |
c48935d7 | 244 | @code{cldemote}, |
142861df JB |
245 | @code{rdpru}, |
246 | @code{mcommit}, | |
a847e322 | 247 | @code{sev_es}, |
f88c9eb0 | 248 | @code{lwp}, |
5dd85c99 SP |
249 | @code{fma4}, |
250 | @code{xop}, | |
60aa667e | 251 | @code{cx16}, |
bd5295b2 | 252 | @code{syscall}, |
1b7f3fb0 | 253 | @code{rdtscp}, |
6305a203 L |
254 | @code{3dnow}, |
255 | @code{3dnowa}, | |
256 | @code{sse4a}, | |
257 | @code{sse5}, | |
646cc3e0 GG |
258 | @code{snp}, |
259 | @code{invlpgb}, | |
260 | @code{tlbsync}, | |
272a84b1 | 261 | @code{svme} and |
6305a203 | 262 | @code{padlock}. |
32e876a8 JB |
263 | Note that these extension mnemonics can be prefixed with @code{no} to revoke |
264 | the respective (and any dependent) functionality. | |
6305a203 L |
265 | |
266 | When the @code{.arch} directive is used with @option{-march}, the | |
9103f4f4 L |
267 | @code{.arch} directive will take precedent. |
268 | ||
269 | @cindex @samp{-mtune=} option, i386 | |
270 | @cindex @samp{-mtune=} option, x86-64 | |
271 | @item -mtune=@var{CPU} | |
272 | This option specifies a processor to optimize for. When used in | |
273 | conjunction with the @option{-march} option, only instructions | |
274 | of the processor specified by the @option{-march} option will be | |
275 | generated. | |
276 | ||
6305a203 L |
277 | Valid @var{CPU} values are identical to the processor list of |
278 | @option{-march=@var{CPU}}. | |
9103f4f4 | 279 | |
c0f3af97 L |
280 | @cindex @samp{-msse2avx} option, i386 |
281 | @cindex @samp{-msse2avx} option, x86-64 | |
282 | @item -msse2avx | |
283 | This option specifies that the assembler should encode SSE instructions | |
284 | with VEX prefix. | |
285 | ||
c8480b58 L |
286 | @cindex @samp{-muse-unaligned-vector-move} option, i386 |
287 | @cindex @samp{-muse-unaligned-vector-move} option, x86-64 | |
288 | @item -muse-unaligned-vector-move | |
289 | This option specifies that the assembler should encode aligned vector | |
290 | move as unaligned vector move. | |
291 | ||
daf50ae7 L |
292 | @cindex @samp{-msse-check=} option, i386 |
293 | @cindex @samp{-msse-check=} option, x86-64 | |
294 | @item -msse-check=@var{none} | |
1f9bb1ca AS |
295 | @itemx -msse-check=@var{warning} |
296 | @itemx -msse-check=@var{error} | |
9aff4b7a | 297 | These options control if the assembler should check SSE instructions. |
daf50ae7 L |
298 | @option{-msse-check=@var{none}} will make the assembler not to check SSE |
299 | instructions, which is the default. @option{-msse-check=@var{warning}} | |
9aff4b7a | 300 | will make the assembler issue a warning for any SSE instruction. |
daf50ae7 | 301 | @option{-msse-check=@var{error}} will make the assembler issue an error |
9aff4b7a | 302 | for any SSE instruction. |
daf50ae7 | 303 | |
539f890d L |
304 | @cindex @samp{-mavxscalar=} option, i386 |
305 | @cindex @samp{-mavxscalar=} option, x86-64 | |
306 | @item -mavxscalar=@var{128} | |
1f9bb1ca | 307 | @itemx -mavxscalar=@var{256} |
2aab8acd | 308 | These options control how the assembler should encode scalar AVX |
539f890d L |
309 | instructions. @option{-mavxscalar=@var{128}} will encode scalar |
310 | AVX instructions with 128bit vector length, which is the default. | |
311 | @option{-mavxscalar=@var{256}} will encode scalar AVX instructions | |
312 | with 256bit vector length. | |
313 | ||
4970191f JB |
314 | WARNING: Don't use this for production code - due to CPU errata the |
315 | resulting code may not work on certain models. | |
316 | ||
03751133 L |
317 | @cindex @samp{-mvexwig=} option, i386 |
318 | @cindex @samp{-mvexwig=} option, x86-64 | |
319 | @item -mvexwig=@var{0} | |
320 | @itemx -mvexwig=@var{1} | |
321 | These options control how the assembler should encode VEX.W-ignored (WIG) | |
322 | VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX | |
323 | instructions with vex.w = 0, which is the default. | |
324 | @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with | |
325 | vex.w = 1. | |
326 | ||
4970191f JB |
327 | WARNING: Don't use this for production code - due to CPU errata the |
328 | resulting code may not work on certain models. | |
329 | ||
43234a1e L |
330 | @cindex @samp{-mevexlig=} option, i386 |
331 | @cindex @samp{-mevexlig=} option, x86-64 | |
332 | @item -mevexlig=@var{128} | |
333 | @itemx -mevexlig=@var{256} | |
334 | @itemx -mevexlig=@var{512} | |
335 | These options control how the assembler should encode length-ignored | |
336 | (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG | |
337 | EVEX instructions with 128bit vector length, which is the default. | |
338 | @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will | |
339 | encode LIG EVEX instructions with 256bit and 512bit vector length, | |
340 | respectively. | |
341 | ||
342 | @cindex @samp{-mevexwig=} option, i386 | |
343 | @cindex @samp{-mevexwig=} option, x86-64 | |
344 | @item -mevexwig=@var{0} | |
345 | @itemx -mevexwig=@var{1} | |
346 | These options control how the assembler should encode w-ignored (WIG) | |
347 | EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG | |
348 | EVEX instructions with evex.w = 0, which is the default. | |
349 | @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with | |
350 | evex.w = 1. | |
351 | ||
1efbbeb4 L |
352 | @cindex @samp{-mmnemonic=} option, i386 |
353 | @cindex @samp{-mmnemonic=} option, x86-64 | |
354 | @item -mmnemonic=@var{att} | |
1f9bb1ca | 355 | @itemx -mmnemonic=@var{intel} |
34bca508 | 356 | This option specifies instruction mnemonic for matching instructions. |
1efbbeb4 L |
357 | The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will |
358 | take precedent. | |
359 | ||
360 | @cindex @samp{-msyntax=} option, i386 | |
361 | @cindex @samp{-msyntax=} option, x86-64 | |
362 | @item -msyntax=@var{att} | |
1f9bb1ca | 363 | @itemx -msyntax=@var{intel} |
34bca508 | 364 | This option specifies instruction syntax when processing instructions. |
1efbbeb4 L |
365 | The @code{.att_syntax} and @code{.intel_syntax} directives will |
366 | take precedent. | |
367 | ||
368 | @cindex @samp{-mnaked-reg} option, i386 | |
369 | @cindex @samp{-mnaked-reg} option, x86-64 | |
370 | @item -mnaked-reg | |
33eaf5de | 371 | This option specifies that registers don't require a @samp{%} prefix. |
e1d4d893 | 372 | The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. |
1efbbeb4 | 373 | |
7e8b059b L |
374 | @cindex @samp{-madd-bnd-prefix} option, i386 |
375 | @cindex @samp{-madd-bnd-prefix} option, x86-64 | |
376 | @item -madd-bnd-prefix | |
377 | This option forces the assembler to add BND prefix to all branches, even | |
378 | if such prefix was not explicitly specified in the source code. | |
379 | ||
8dcea932 L |
380 | @cindex @samp{-mshared} option, i386 |
381 | @cindex @samp{-mshared} option, x86-64 | |
382 | @item -mno-shared | |
383 | On ELF target, the assembler normally optimizes out non-PLT relocations | |
384 | against defined non-weak global branch targets with default visibility. | |
385 | The @samp{-mshared} option tells the assembler to generate code which | |
386 | may go into a shared library where all non-weak global branch targets | |
387 | with default visibility can be preempted. The resulting code is | |
388 | slightly bigger. This option only affects the handling of branch | |
389 | instructions. | |
390 | ||
251dae91 | 391 | @cindex @samp{-mbig-obj} option, i386 |
167ad85b TG |
392 | @cindex @samp{-mbig-obj} option, x86-64 |
393 | @item -mbig-obj | |
251dae91 | 394 | On PE/COFF target this option forces the use of big object file |
167ad85b TG |
395 | format, which allows more than 32768 sections. |
396 | ||
d022bddd IT |
397 | @cindex @samp{-momit-lock-prefix=} option, i386 |
398 | @cindex @samp{-momit-lock-prefix=} option, x86-64 | |
399 | @item -momit-lock-prefix=@var{no} | |
400 | @itemx -momit-lock-prefix=@var{yes} | |
401 | These options control how the assembler should encode lock prefix. | |
402 | This option is intended as a workaround for processors, that fail on | |
403 | lock prefix. This option can only be safely used with single-core, | |
404 | single-thread computers | |
405 | @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. | |
406 | @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, | |
407 | which is the default. | |
408 | ||
e4e00185 AS |
409 | @cindex @samp{-mfence-as-lock-add=} option, i386 |
410 | @cindex @samp{-mfence-as-lock-add=} option, x86-64 | |
411 | @item -mfence-as-lock-add=@var{no} | |
412 | @itemx -mfence-as-lock-add=@var{yes} | |
413 | These options control how the assembler should encode lfence, mfence and | |
414 | sfence. | |
415 | @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and | |
416 | sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and | |
417 | @samp{lock addl $0x0, (%esp)} in 32-bit mode. | |
418 | @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and | |
419 | sfence as usual, which is the default. | |
420 | ||
0cb4071e L |
421 | @cindex @samp{-mrelax-relocations=} option, i386 |
422 | @cindex @samp{-mrelax-relocations=} option, x86-64 | |
423 | @item -mrelax-relocations=@var{no} | |
424 | @itemx -mrelax-relocations=@var{yes} | |
425 | These options control whether the assembler should generate relax | |
426 | relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and | |
427 | R_X86_64_REX_GOTPCRELX, in 64-bit mode. | |
428 | @option{-mrelax-relocations=@var{yes}} will generate relax relocations. | |
429 | @option{-mrelax-relocations=@var{no}} will not generate relax | |
430 | relocations. The default can be controlled by a configure option | |
431 | @option{--enable-x86-relax-relocations}. | |
432 | ||
e379e5f3 L |
433 | @cindex @samp{-malign-branch-boundary=} option, i386 |
434 | @cindex @samp{-malign-branch-boundary=} option, x86-64 | |
435 | @item -malign-branch-boundary=@var{NUM} | |
436 | This option controls how the assembler should align branches with segment | |
437 | prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or | |
438 | no less than 16. Branches will be aligned within @var{NUM} byte | |
439 | boundary. @option{-malign-branch-boundary=0}, which is the default, | |
440 | doesn't align branches. | |
441 | ||
442 | @cindex @samp{-malign-branch=} option, i386 | |
443 | @cindex @samp{-malign-branch=} option, x86-64 | |
444 | @item -malign-branch=@var{TYPE}[+@var{TYPE}...] | |
445 | This option specifies types of branches to align. @var{TYPE} is | |
446 | combination of @samp{jcc}, which aligns conditional jumps, | |
447 | @samp{fused}, which aligns fused conditional jumps, @samp{jmp}, | |
448 | which aligns unconditional jumps, @samp{call} which aligns calls, | |
449 | @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect | |
450 | jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}. | |
451 | ||
452 | @cindex @samp{-malign-branch-prefix-size=} option, i386 | |
453 | @cindex @samp{-malign-branch-prefix-size=} option, x86-64 | |
454 | @item -malign-branch-prefix-size=@var{NUM} | |
455 | This option specifies the maximum number of prefixes on an instruction | |
456 | to align branches. @var{NUM} should be between 0 and 5. The default | |
457 | @var{NUM} is 5. | |
458 | ||
76cf450b L |
459 | @cindex @samp{-mbranches-within-32B-boundaries} option, i386 |
460 | @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64 | |
461 | @item -mbranches-within-32B-boundaries | |
462 | This option aligns conditional jumps, fused conditional jumps and | |
463 | unconditional jumps within 32 byte boundary with up to 5 segment prefixes | |
464 | on an instruction. It is equivalent to | |
465 | @option{-malign-branch-boundary=32} | |
466 | @option{-malign-branch=jcc+fused+jmp} | |
467 | @option{-malign-branch-prefix-size=5}. | |
468 | The default doesn't align branches. | |
469 | ||
ae531041 L |
470 | @cindex @samp{-mlfence-after-load=} option, i386 |
471 | @cindex @samp{-mlfence-after-load=} option, x86-64 | |
472 | @item -mlfence-after-load=@var{no} | |
473 | @itemx -mlfence-after-load=@var{yes} | |
474 | These options control whether the assembler should generate lfence | |
475 | after load instructions. @option{-mlfence-after-load=@var{yes}} will | |
476 | generate lfence. @option{-mlfence-after-load=@var{no}} will not generate | |
477 | lfence, which is the default. | |
478 | ||
479 | @cindex @samp{-mlfence-before-indirect-branch=} option, i386 | |
480 | @cindex @samp{-mlfence-before-indirect-branch=} option, x86-64 | |
481 | @item -mlfence-before-indirect-branch=@var{none} | |
482 | @item -mlfence-before-indirect-branch=@var{all} | |
483 | @item -mlfence-before-indirect-branch=@var{register} | |
484 | @itemx -mlfence-before-indirect-branch=@var{memory} | |
485 | These options control whether the assembler should generate lfence | |
3071b197 | 486 | before indirect near branch instructions. |
ae531041 | 487 | @option{-mlfence-before-indirect-branch=@var{all}} will generate lfence |
3071b197 | 488 | before indirect near branch via register and issue a warning before |
ae531041 | 489 | indirect near branch via memory. |
a09f656b | 490 | It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when |
f9a6a8f0 | 491 | there's no explicit @option{-mlfence-before-ret=}. |
ae531041 | 492 | @option{-mlfence-before-indirect-branch=@var{register}} will generate |
3071b197 | 493 | lfence before indirect near branch via register. |
ae531041 L |
494 | @option{-mlfence-before-indirect-branch=@var{memory}} will issue a |
495 | warning before indirect near branch via memory. | |
496 | @option{-mlfence-before-indirect-branch=@var{none}} will not generate | |
497 | lfence nor issue warning, which is the default. Note that lfence won't | |
498 | be generated before indirect near branch via register with | |
499 | @option{-mlfence-after-load=@var{yes}} since lfence will be generated | |
500 | after loading branch target register. | |
501 | ||
502 | @cindex @samp{-mlfence-before-ret=} option, i386 | |
503 | @cindex @samp{-mlfence-before-ret=} option, x86-64 | |
504 | @item -mlfence-before-ret=@var{none} | |
a09f656b | 505 | @item -mlfence-before-ret=@var{shl} |
ae531041 | 506 | @item -mlfence-before-ret=@var{or} |
a09f656b | 507 | @item -mlfence-before-ret=@var{yes} |
ae531041 L |
508 | @itemx -mlfence-before-ret=@var{not} |
509 | These options control whether the assembler should generate lfence | |
510 | before ret. @option{-mlfence-before-ret=@var{or}} will generate | |
511 | generate or instruction with lfence. | |
a09f656b | 512 | @option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction |
513 | with lfence. @option{-mlfence-before-ret=@var{not}} will generate not | |
514 | instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not | |
515 | generate lfence, which is the default. | |
ae531041 | 516 | |
b4a3a7b4 L |
517 | @cindex @samp{-mx86-used-note=} option, i386 |
518 | @cindex @samp{-mx86-used-note=} option, x86-64 | |
519 | @item -mx86-used-note=@var{no} | |
520 | @itemx -mx86-used-note=@var{yes} | |
521 | These options control whether the assembler should generate | |
522 | GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED | |
523 | GNU property notes. The default can be controlled by the | |
524 | @option{--enable-x86-used-note} configure option. | |
525 | ||
d3d3c6db IT |
526 | @cindex @samp{-mevexrcig=} option, i386 |
527 | @cindex @samp{-mevexrcig=} option, x86-64 | |
528 | @item -mevexrcig=@var{rne} | |
529 | @itemx -mevexrcig=@var{rd} | |
530 | @itemx -mevexrcig=@var{ru} | |
531 | @itemx -mevexrcig=@var{rz} | |
532 | These options control how the assembler should encode SAE-only | |
533 | EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits | |
534 | of EVEX instruction with 00, which is the default. | |
535 | @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} | |
536 | and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions | |
537 | with 01, 10 and 11 RC bits, respectively. | |
538 | ||
5db04b09 L |
539 | @cindex @samp{-mamd64} option, x86-64 |
540 | @cindex @samp{-mintel64} option, x86-64 | |
541 | @item -mamd64 | |
542 | @itemx -mintel64 | |
543 | This option specifies that the assembler should accept only AMD64 or | |
4b5aaf5f L |
544 | Intel64 ISA in 64-bit mode. The default is to accept common, Intel64 |
545 | only and AMD64 ISAs. | |
5db04b09 | 546 | |
b6f8c7c4 L |
547 | @cindex @samp{-O0} option, i386 |
548 | @cindex @samp{-O0} option, x86-64 | |
549 | @cindex @samp{-O} option, i386 | |
550 | @cindex @samp{-O} option, x86-64 | |
551 | @cindex @samp{-O1} option, i386 | |
552 | @cindex @samp{-O1} option, x86-64 | |
553 | @cindex @samp{-O2} option, i386 | |
554 | @cindex @samp{-O2} option, x86-64 | |
555 | @cindex @samp{-Os} option, i386 | |
556 | @cindex @samp{-Os} option, x86-64 | |
557 | @item -O0 | -O | -O1 | -O2 | -Os | |
558 | Optimize instruction encoding with smaller instruction size. @samp{-O} | |
559 | and @samp{-O1} encode 64-bit register load instructions with 64-bit | |
560 | immediate as 32-bit register load instructions with 31-bit or 32-bits | |
99112332 | 561 | immediates, encode 64-bit register clearing instructions with 32-bit |
a0a1771e JB |
562 | register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector |
563 | register clearing instructions with 128-bit VEX vector register | |
564 | clearing instructions, encode 128-bit/256-bit EVEX vector | |
97ed31ae | 565 | register load/store instructions with VEX vector register load/store |
a0a1771e JB |
566 | instructions, and encode 128-bit/256-bit EVEX packed integer logical |
567 | instructions with 128-bit/256-bit VEX packed integer logical. | |
568 | ||
569 | @samp{-O2} includes @samp{-O1} optimization plus encodes | |
570 | 256-bit/512-bit EVEX vector register clearing instructions with 128-bit | |
79dec6b7 JB |
571 | EVEX vector register clearing instructions. In 64-bit mode VEX encoded |
572 | instructions with commutative source operands will also have their | |
573 | source operands swapped if this allows using the 2-byte VEX prefix form | |
5641ec01 JB |
574 | instead of the 3-byte one. Certain forms of AND as well as OR with the |
575 | same (register) operand specified twice will also be changed to TEST. | |
a0a1771e | 576 | |
b6f8c7c4 L |
577 | @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit |
578 | and 64-bit register tests with immediate as 8-bit register test with | |
579 | immediate. @samp{-O0} turns off this optimization. | |
580 | ||
55b62671 | 581 | @end table |
731caf76 | 582 | @c man end |
e413e4e9 | 583 | |
a6c24e68 NC |
584 | @node i386-Directives |
585 | @section x86 specific Directives | |
586 | ||
587 | @cindex machine directives, x86 | |
588 | @cindex x86 machine directives | |
589 | @table @code | |
590 | ||
591 | @cindex @code{lcomm} directive, COFF | |
592 | @item .lcomm @var{symbol} , @var{length}[, @var{alignment}] | |
593 | Reserve @var{length} (an absolute expression) bytes for a local common | |
594 | denoted by @var{symbol}. The section and value of @var{symbol} are | |
595 | those of the new local common. The addresses are allocated in the bss | |
704209c0 NC |
596 | section, so that at run-time the bytes start off zeroed. Since |
597 | @var{symbol} is not declared global, it is normally not visible to | |
598 | @code{@value{LD}}. The optional third parameter, @var{alignment}, | |
599 | specifies the desired alignment of the symbol in the bss section. | |
a6c24e68 NC |
600 | |
601 | This directive is only available for COFF based x86 targets. | |
602 | ||
102e9361 NC |
603 | @cindex @code{largecomm} directive, ELF |
604 | @item .largecomm @var{symbol} , @var{length}[, @var{alignment}] | |
605 | This directive behaves in the same way as the @code{comm} directive | |
606 | except that the data is placed into the @var{.lbss} section instead of | |
607 | the @var{.bss} section @ref{Comm}. | |
608 | ||
609 | The directive is intended to be used for data which requires a large | |
610 | amount of space, and it is only available for ELF based x86_64 | |
611 | targets. | |
612 | ||
f2f51cd5 NC |
613 | @cindex @code{value} directive |
614 | @item .value @var{expression} [, @var{expression}] | |
615 | This directive behaves in the same way as the @code{.short} directive, | |
616 | taking a series of comma separated expressions and storing them as | |
617 | two-byte wide values into the current section. | |
618 | ||
695a8c34 JB |
619 | @cindex @code{insn} directive |
620 | @item .insn [@var{prefix}[,...]] [@var{encoding}] @var{major-opcode}[@code{+r}|@code{/@var{extension}}] [,@var{operand}[,...]] | |
621 | This directive allows composing instructions which @code{@value{AS}} | |
622 | may not know about yet, or which it has no way of expressing (which | |
623 | can be the case for certain alternative encodings). It assumes certain | |
624 | basic structure in how operands are encoded, and it also only | |
625 | recognizes - with a few extensions as per below - operands otherwise | |
626 | valid for instructions. Therefore there is no guarantee that | |
627 | everything can be expressed (e.g. the original Intel Xeon Phi's MVEX | |
628 | encodings cannot be expressed). | |
629 | ||
630 | @itemize @bullet | |
631 | @item | |
632 | @var{prefix} expresses one or more opcode prefixes in the usual way. | |
633 | Legacy encoding prefixes altering meaning (0x66, 0xF2, 0xF3) may be | |
634 | specified as high byte of <major-opcode> (perhaps already including an | |
635 | encoding space prefix). Note that there can only be one such prefix. | |
636 | Segment overrides are better specified in the respective memory | |
637 | operand, as long as there is one. | |
638 | ||
639 | @item | |
640 | @var{encoding} is used to specify VEX, XOP, or EVEX encodings. The | |
641 | syntax tries to resemble that used in documentation: | |
642 | @itemize @bullet | |
643 | @item @code{VEX}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{space}}][@code{.@var{w}}] | |
644 | @item @code{EVEX}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{space}}][@code{.@var{w}}] | |
645 | @item @code{XOP}@var{space}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{w}}] | |
646 | @end itemize | |
647 | ||
648 | Here | |
649 | @itemize @bullet | |
650 | @item @var{len} can be @code{LIG}, @code{128}, @code{256}, or (EVEX | |
651 | only) @code{512} as well as @code{L0} / @code{L1} for VEX / XOP and | |
652 | @code{L0}...@code{L3} for EVEX | |
653 | @item @var{prefix} can be @code{NP}, @code{66}, @code{F3}, or @code{F2} | |
654 | @item @var{space} can be | |
655 | @itemize @bullet | |
656 | @item @code{0f}, @code{0f38}, @code{0f3a}, or @code{M0}...@code{M31} | |
657 | for VEX | |
658 | @item @code{08}...@code{1f} for XOP | |
659 | @item @code{0f}, @code{0f38}, @code{0f3a}, or @code{M0}...@code{M15} | |
660 | for EVEX | |
661 | @end itemize | |
662 | @item @var{w} can be @code{WIG}, @code{W0}, or @code{W1} | |
663 | @end itemize | |
664 | ||
665 | Defaults: | |
666 | @itemize @bullet | |
667 | @item Omitted @var{len} means "infer from operand size" if there is at | |
668 | least one sized vector operand, or @code{LIG} otherwise. (Obviously | |
669 | @var{len} has to be omitted when there's EVEX rounding control | |
670 | specified later in the operands.) | |
671 | @item Omitted @var{prefix} means @code{NP}. | |
672 | @item Omitted @var{space} (VEX/EVEX only) implies encoding space is | |
673 | taken from @var{major-opcode}. | |
674 | @item Omitted @var{w} means "infer from GPR operand size" in 64-bit | |
675 | code if there is at least one GPR(-like) operand, or @code{WIG} | |
676 | otherwise. | |
677 | @end itemize | |
678 | ||
679 | @item | |
680 | @var{major-opcode} is an absolute expression specifying the instruction | |
681 | opcode. Legacy encoding prefixes altering encoding space (0x0f, | |
682 | 0x0f38, 0x0f3a) have to be specified as high byte(s) here. | |
683 | "Degenerate" ModR/M bytes, as present in e.g. certain FPU opcodes or | |
684 | sub-spaces like that of major opcode 0x0f01, generally want encoding as | |
685 | immediate operand (such opcodes wouldn't normally have non-immediate | |
686 | operands); in some cases it may be possible to also encode these as low | |
687 | byte of the major opcode, but there are potential ambiguities. Also | |
688 | note that after stripping encoding prefixes, the residual has to fit in | |
689 | two bytes (16 bits). @code{+r} can be suffixed to the major opcode | |
690 | expression to specify register-only encoding forms not using a ModR/M | |
691 | byte. @code{/@var{extension}} can alternatively be suffixed to the | |
692 | major opcode expression to specify an extension opcode, encoded in bits | |
693 | 3-5 of the ModR/M byte. | |
694 | ||
695 | @item | |
696 | @var{operand} is an instruction operand expressed the usual way. | |
697 | Register operands are primarily used to express register numbers as | |
698 | encoded in ModR/M byte and REX/VEX/XOP/EVEX prefixes. In certain | |
699 | cases the register type (really: size) is also used to derive other | |
700 | encoding attributes, if these aren't specified explicitly. Note that | |
701 | there is no consistency checking among operands, so entirely bogus | |
702 | mixes of operands are possible. Note further that only operands | |
703 | actually encoded in the instruction should be specified. Operands like | |
704 | @samp{%cl} in shift/rotate instructions have to be omitted, or else | |
705 | they'll be encoded as an ordinary (register) operand. Operand order | |
706 | may also not match that of the actual instruction (see below). | |
707 | @end itemize | |
708 | ||
709 | Encoding of operands: While for a memory operand (of which there can be | |
710 | only one) it is clear how to encode it in the resulting ModR/M byte, | |
711 | register operands are encoded strictly in this order (operand counts do | |
712 | not include immediate ones in the enumeration below, and if there was an | |
713 | extension opcode specified it counts as a register operand; VEX.vvvv | |
714 | is meant to cover XOP and EVEX as well): | |
715 | ||
716 | @itemize @bullet | |
717 | @item VEX.vvvv for 1-register-operand VEX/XOP/EVEX insns, | |
718 | @item ModR/M.rm, ModR/M.reg for 2-operand insns, | |
719 | @item ModR/M.rm, VEX.vvvv, ModR/M.reg for 3-operand insns, and | |
720 | @item Imm@{4,5@}, ModR/M.rm, VEX.vvvv, ModR/M.reg for 4-operand insns, | |
721 | @end itemize | |
722 | ||
723 | obviously with the ModR/M.rm slot skipped when there is a memory | |
724 | operand, and obviously with the ModR/M.reg slot skipped when there is | |
725 | an extension opcode. For Intel syntax of course the opposite order | |
726 | applies. With @code{+r} (and hence no ModR/M) there can only be a | |
727 | single register operand for legacy encodings. VEX and alike can have | |
728 | two register operands, where the second (first in Intel syntax) would | |
729 | go into VEX.vvvv. | |
730 | ||
731 | Immediate operands (including immediate-like displacements, i.e. when | |
732 | not part of ModR/M addressing) are emitted in the order specified, | |
733 | regardless of AT&T or Intel syntax. Since it may not be possible to | |
734 | infer the size of such immediates, they can be suffixed by | |
735 | @code{@{:s@var{n}@}} or @code{@{:u@var{n}@}}, representing signed / | |
736 | unsigned immediates of the given number of bits respectively. When | |
737 | emitting such operands, the number of bits will be rounded up to the | |
738 | smallest suitable of 8, 16, 32, or 64. Immediates wider than 32 bits | |
739 | are permitted in 64-bit code only. | |
740 | ||
741 | For EVEX encoding memory operands with a displacement need to know | |
742 | Disp8 scaling size in order to use an 8-bit displacement. For many | |
743 | instructions this can be inferred from the types of other operands | |
744 | specified. In Intel syntax @samp{DWORD PTR} and alike can be used to | |
745 | specify the respective size. In AT&T syntax the memory operands can | |
746 | be suffixed by @code{@{:d@var{n}@}} to specify the size (in bytes). | |
747 | This can be combined with an embedded broadcast specifier: | |
748 | @samp{8(%eax)@{1to8:d8@}}. | |
749 | ||
a6c24e68 | 750 | @c FIXME: Document other x86 specific directives ? Eg: .code16gcc, |
a6c24e68 NC |
751 | |
752 | @end table | |
753 | ||
252b5132 | 754 | @node i386-Syntax |
7c31ae13 NC |
755 | @section i386 Syntactical Considerations |
756 | @menu | |
757 | * i386-Variations:: AT&T Syntax versus Intel Syntax | |
758 | * i386-Chars:: Special Characters | |
759 | @end menu | |
760 | ||
761 | @node i386-Variations | |
762 | @subsection AT&T Syntax versus Intel Syntax | |
252b5132 | 763 | |
e413e4e9 AM |
764 | @cindex i386 intel_syntax pseudo op |
765 | @cindex intel_syntax pseudo op, i386 | |
766 | @cindex i386 att_syntax pseudo op | |
767 | @cindex att_syntax pseudo op, i386 | |
252b5132 RH |
768 | @cindex i386 syntax compatibility |
769 | @cindex syntax compatibility, i386 | |
55b62671 AJ |
770 | @cindex x86-64 intel_syntax pseudo op |
771 | @cindex intel_syntax pseudo op, x86-64 | |
772 | @cindex x86-64 att_syntax pseudo op | |
773 | @cindex att_syntax pseudo op, x86-64 | |
774 | @cindex x86-64 syntax compatibility | |
775 | @cindex syntax compatibility, x86-64 | |
e413e4e9 AM |
776 | |
777 | @code{@value{AS}} now supports assembly using Intel assembler syntax. | |
778 | @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches | |
779 | back to the usual AT&T mode for compatibility with the output of | |
780 | @code{@value{GCC}}. Either of these directives may have an optional | |
781 | argument, @code{prefix}, or @code{noprefix} specifying whether registers | |
782 | require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite | |
252b5132 RH |
783 | different from Intel syntax. We mention these differences because |
784 | almost all 80386 documents use Intel syntax. Notable differences | |
785 | between the two syntaxes are: | |
786 | ||
787 | @cindex immediate operands, i386 | |
788 | @cindex i386 immediate operands | |
789 | @cindex register operands, i386 | |
790 | @cindex i386 register operands | |
791 | @cindex jump/call operands, i386 | |
792 | @cindex i386 jump/call operands | |
793 | @cindex operand delimiters, i386 | |
55b62671 AJ |
794 | |
795 | @cindex immediate operands, x86-64 | |
796 | @cindex x86-64 immediate operands | |
797 | @cindex register operands, x86-64 | |
798 | @cindex x86-64 register operands | |
799 | @cindex jump/call operands, x86-64 | |
800 | @cindex x86-64 jump/call operands | |
801 | @cindex operand delimiters, x86-64 | |
252b5132 RH |
802 | @itemize @bullet |
803 | @item | |
804 | AT&T immediate operands are preceded by @samp{$}; Intel immediate | |
805 | operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). | |
806 | AT&T register operands are preceded by @samp{%}; Intel register operands | |
807 | are undelimited. AT&T absolute (as opposed to PC relative) jump/call | |
808 | operands are prefixed by @samp{*}; they are undelimited in Intel syntax. | |
809 | ||
810 | @cindex i386 source, destination operands | |
811 | @cindex source, destination operands; i386 | |
55b62671 AJ |
812 | @cindex x86-64 source, destination operands |
813 | @cindex source, destination operands; x86-64 | |
252b5132 RH |
814 | @item |
815 | AT&T and Intel syntax use the opposite order for source and destination | |
816 | operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The | |
817 | @samp{source, dest} convention is maintained for compatibility with | |
96ef6e0f L |
818 | previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and |
819 | instructions with 2 immediate operands, such as the @samp{enter} | |
820 | instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. | |
252b5132 RH |
821 | |
822 | @cindex mnemonic suffixes, i386 | |
823 | @cindex sizes operands, i386 | |
824 | @cindex i386 size suffixes | |
55b62671 AJ |
825 | @cindex mnemonic suffixes, x86-64 |
826 | @cindex sizes operands, x86-64 | |
827 | @cindex x86-64 size suffixes | |
252b5132 RH |
828 | @item |
829 | In AT&T syntax the size of memory operands is determined from the last | |
830 | character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, | |
55b62671 | 831 | @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long |
aa108c0c LC |
832 | (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes |
833 | of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm | |
834 | (256-bit vector) and zmm (512-bit vector) memory references, only when there's | |
835 | no other way to disambiguate an instruction. Intel syntax accomplishes this by | |
836 | prefixing memory operands (@emph{not} the instruction mnemonics) with | |
837 | @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr}, | |
838 | @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel | |
839 | syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T | |
840 | syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and | |
841 | @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references. | |
252b5132 | 842 | |
4b06377f L |
843 | In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} |
844 | instruction with the 64-bit displacement or immediate operand. | |
845 | ||
252b5132 RH |
846 | @cindex return instructions, i386 |
847 | @cindex i386 jump, call, return | |
55b62671 AJ |
848 | @cindex return instructions, x86-64 |
849 | @cindex x86-64 jump, call, return | |
252b5132 RH |
850 | @item |
851 | Immediate form long jumps and calls are | |
852 | @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the | |
853 | Intel syntax is | |
854 | @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return | |
855 | instruction | |
856 | is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is | |
857 | @samp{ret far @var{stack-adjust}}. | |
858 | ||
859 | @cindex sections, i386 | |
860 | @cindex i386 sections | |
55b62671 AJ |
861 | @cindex sections, x86-64 |
862 | @cindex x86-64 sections | |
252b5132 RH |
863 | @item |
864 | The AT&T assembler does not provide support for multiple section | |
865 | programs. Unix style systems expect all programs to be single sections. | |
866 | @end itemize | |
867 | ||
7c31ae13 NC |
868 | @node i386-Chars |
869 | @subsection Special Characters | |
870 | ||
871 | @cindex line comment character, i386 | |
872 | @cindex i386 line comment character | |
873 | The presence of a @samp{#} appearing anywhere on a line indicates the | |
874 | start of a comment that extends to the end of that line. | |
875 | ||
876 | If a @samp{#} appears as the first character of a line then the whole | |
877 | line is treated as a comment, but in this case the line can also be a | |
878 | logical line number directive (@pxref{Comments}) or a preprocessor | |
879 | control command (@pxref{Preprocessing}). | |
880 | ||
a05a5b64 | 881 | If the @option{--divide} command-line option has not been specified |
7c31ae13 NC |
882 | then the @samp{/} character appearing anywhere on a line also |
883 | introduces a line comment. | |
884 | ||
885 | @cindex line separator, i386 | |
886 | @cindex statement separator, i386 | |
887 | @cindex i386 line separator | |
888 | The @samp{;} character can be used to separate statements on the same | |
889 | line. | |
890 | ||
252b5132 | 891 | @node i386-Mnemonics |
d3b47e2b L |
892 | @section i386-Mnemonics |
893 | @subsection Instruction Naming | |
252b5132 RH |
894 | |
895 | @cindex i386 instruction naming | |
896 | @cindex instruction naming, i386 | |
55b62671 AJ |
897 | @cindex x86-64 instruction naming |
898 | @cindex instruction naming, x86-64 | |
899 | ||
252b5132 | 900 | Instruction mnemonics are suffixed with one character modifiers which |
55b62671 AJ |
901 | specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} |
902 | and @samp{q} specify byte, word, long and quadruple word operands. If | |
903 | no suffix is specified by an instruction then @code{@value{AS}} tries to | |
904 | fill in the missing suffix based on the destination register operand | |
905 | (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent | |
906 | to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to | |
907 | @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix | |
908 | assembler which assumes that a missing mnemonic suffix implies long | |
909 | operand size. (This incompatibility does not affect compiler output | |
910 | since compilers always explicitly specify the mnemonic suffix.) | |
252b5132 | 911 | |
c006a730 JB |
912 | When there is no sizing suffix and no (suitable) register operands to |
913 | deduce the size of memory operands, with a few exceptions and where long | |
914 | operand size is possible in the first place, operand size will default | |
915 | to long in 32- and 64-bit modes. Similarly it will default to short in | |
916 | 16-bit mode. Noteworthy exceptions are | |
917 | ||
918 | @itemize @bullet | |
919 | @item | |
920 | Instructions with an implicit on-stack operand as well as branches, | |
921 | which default to quad in 64-bit mode. | |
922 | ||
923 | @item | |
924 | Sign- and zero-extending moves, which default to byte size source | |
925 | operands. | |
926 | ||
927 | @item | |
928 | Floating point insns with integer operands, which default to short (for | |
929 | perhaps historical reasons). | |
930 | ||
931 | @item | |
932 | CRC32 with a 64-bit destination, which defaults to a quad source | |
933 | operand. | |
934 | ||
935 | @end itemize | |
936 | ||
b6169b20 L |
937 | @cindex encoding options, i386 |
938 | @cindex encoding options, x86-64 | |
939 | ||
86fa6981 L |
940 | Different encoding options can be specified via pseudo prefixes: |
941 | ||
942 | @itemize @bullet | |
943 | @item | |
944 | @samp{@{disp8@}} -- prefer 8-bit displacement. | |
945 | ||
946 | @item | |
41eb8e88 L |
947 | @samp{@{disp32@}} -- prefer 32-bit displacement. |
948 | ||
949 | @item | |
950 | @samp{@{disp16@}} -- prefer 16-bit displacement. | |
86fa6981 L |
951 | |
952 | @item | |
953 | @samp{@{load@}} -- prefer load-form instruction. | |
954 | ||
955 | @item | |
956 | @samp{@{store@}} -- prefer store-form instruction. | |
957 | ||
958 | @item | |
42e04b36 | 959 | @samp{@{vex@}} -- encode with VEX prefix. |
86fa6981 L |
960 | |
961 | @item | |
42e04b36 | 962 | @samp{@{vex3@}} -- encode with 3-byte VEX prefix. |
86fa6981 L |
963 | |
964 | @item | |
965 | @samp{@{evex@}} -- encode with EVEX prefix. | |
6b6b6807 L |
966 | |
967 | @item | |
968 | @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector | |
969 | instructions (x86-64 only). Note that this differs from the @samp{rex} | |
970 | prefix which generates REX prefix unconditionally. | |
b6f8c7c4 L |
971 | |
972 | @item | |
973 | @samp{@{nooptimize@}} -- disable instruction size optimization. | |
86fa6981 | 974 | @end itemize |
b6169b20 | 975 | |
4321af3e | 976 | Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix |
58bf9b6a | 977 | by default. The pseudo @samp{@{vex@}} prefix can be used to encode |
4321af3e | 978 | mnemonics of Intel VNNI/IFMA instructions with the VEX prefix. |
58bf9b6a | 979 | |
252b5132 RH |
980 | @cindex conversion instructions, i386 |
981 | @cindex i386 conversion instructions | |
55b62671 AJ |
982 | @cindex conversion instructions, x86-64 |
983 | @cindex x86-64 conversion instructions | |
252b5132 RH |
984 | The Intel-syntax conversion instructions |
985 | ||
986 | @itemize @bullet | |
987 | @item | |
988 | @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, | |
989 | ||
990 | @item | |
991 | @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, | |
992 | ||
993 | @item | |
994 | @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, | |
995 | ||
996 | @item | |
997 | @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, | |
55b62671 AJ |
998 | |
999 | @item | |
1000 | @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} | |
1001 | (x86-64 only), | |
1002 | ||
1003 | @item | |
d5f0cf92 | 1004 | @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in |
55b62671 | 1005 | @samp{%rdx:%rax} (x86-64 only), |
252b5132 RH |
1006 | @end itemize |
1007 | ||
1008 | @noindent | |
55b62671 AJ |
1009 | are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and |
1010 | @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these | |
1011 | instructions. | |
252b5132 | 1012 | |
0e6724de L |
1013 | @cindex extension instructions, i386 |
1014 | @cindex i386 extension instructions | |
1015 | @cindex extension instructions, x86-64 | |
1016 | @cindex x86-64 extension instructions | |
1017 | The Intel-syntax extension instructions | |
1018 | ||
1019 | @itemize @bullet | |
1020 | @item | |
1021 | @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}. | |
1022 | ||
1023 | @item | |
1024 | @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}. | |
1025 | ||
1026 | @item | |
1027 | @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64} | |
1028 | (x86-64 only). | |
1029 | ||
1030 | @item | |
1031 | @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32} | |
1032 | ||
1033 | @item | |
1034 | @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64} | |
1035 | (x86-64 only). | |
1036 | ||
1037 | @item | |
1038 | @samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64} | |
1039 | (x86-64 only). | |
1040 | ||
1041 | @item | |
1042 | @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}. | |
1043 | ||
1044 | @item | |
1045 | @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}. | |
1046 | ||
1047 | @item | |
1048 | @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64} | |
1049 | (x86-64 only). | |
1050 | ||
1051 | @item | |
1052 | @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32} | |
1053 | ||
1054 | @item | |
1055 | @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64} | |
1056 | (x86-64 only). | |
1057 | @end itemize | |
1058 | ||
1059 | @noindent | |
1060 | are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx}, | |
3f335b75 | 1061 | @samp{movsbq/movsxb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw}, |
0e6724de L |
1062 | @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx}, |
1063 | @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx}, | |
1064 | @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax. | |
1065 | ||
252b5132 RH |
1066 | @cindex jump instructions, i386 |
1067 | @cindex call instructions, i386 | |
55b62671 AJ |
1068 | @cindex jump instructions, x86-64 |
1069 | @cindex call instructions, x86-64 | |
252b5132 RH |
1070 | Far call/jump instructions are @samp{lcall} and @samp{ljmp} in |
1071 | AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel | |
1072 | convention. | |
1073 | ||
d3b47e2b | 1074 | @subsection AT&T Mnemonic versus Intel Mnemonic |
1efbbeb4 L |
1075 | |
1076 | @cindex i386 mnemonic compatibility | |
1077 | @cindex mnemonic compatibility, i386 | |
1078 | ||
1079 | @code{@value{AS}} supports assembly using Intel mnemonic. | |
1080 | @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and | |
1081 | @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T | |
1082 | syntax for compatibility with the output of @code{@value{GCC}}. | |
1efbbeb4 L |
1083 | Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, |
1084 | @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, | |
1085 | @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 | |
1086 | assembler with different mnemonics from those in Intel IA32 specification. | |
1087 | @code{@value{GCC}} generates those instructions with AT&T mnemonic. | |
1088 | ||
bc31405e L |
1089 | @itemize @bullet |
1090 | @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination | |
1091 | register. @samp{movsxd} should be used to encode 16-bit or 32-bit | |
1092 | destination register with both AT&T and Intel mnemonics. | |
1093 | @end itemize | |
1094 | ||
252b5132 RH |
1095 | @node i386-Regs |
1096 | @section Register Naming | |
1097 | ||
1098 | @cindex i386 registers | |
1099 | @cindex registers, i386 | |
55b62671 AJ |
1100 | @cindex x86-64 registers |
1101 | @cindex registers, x86-64 | |
252b5132 RH |
1102 | Register operands are always prefixed with @samp{%}. The 80386 registers |
1103 | consist of | |
1104 | ||
1105 | @itemize @bullet | |
1106 | @item | |
1107 | the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, | |
1108 | @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the | |
1109 | frame pointer), and @samp{%esp} (the stack pointer). | |
1110 | ||
1111 | @item | |
1112 | the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, | |
1113 | @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. | |
1114 | ||
1115 | @item | |
1116 | the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, | |
1117 | @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These | |
1118 | are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, | |
1119 | @samp{%cx}, and @samp{%dx}) | |
1120 | ||
1121 | @item | |
1122 | the 6 section registers @samp{%cs} (code section), @samp{%ds} | |
1123 | (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, | |
1124 | and @samp{%gs}. | |
1125 | ||
1126 | @item | |
4bde3cdd UD |
1127 | the 5 processor control registers @samp{%cr0}, @samp{%cr2}, |
1128 | @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}. | |
252b5132 RH |
1129 | |
1130 | @item | |
1131 | the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, | |
1132 | @samp{%db3}, @samp{%db6}, and @samp{%db7}. | |
1133 | ||
1134 | @item | |
1135 | the 2 test registers @samp{%tr6} and @samp{%tr7}. | |
1136 | ||
1137 | @item | |
1138 | the 8 floating point register stack @samp{%st} or equivalently | |
1139 | @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, | |
1140 | @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. | |
55b62671 AJ |
1141 | These registers are overloaded by 8 MMX registers @samp{%mm0}, |
1142 | @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, | |
1143 | @samp{%mm6} and @samp{%mm7}. | |
1144 | ||
1145 | @item | |
4bde3cdd | 1146 | the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, |
55b62671 AJ |
1147 | @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. |
1148 | @end itemize | |
1149 | ||
1150 | The AMD x86-64 architecture extends the register set by: | |
1151 | ||
1152 | @itemize @bullet | |
1153 | @item | |
1154 | enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the | |
1155 | accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, | |
1156 | @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack | |
1157 | pointer) | |
1158 | ||
1159 | @item | |
1160 | the 8 extended registers @samp{%r8}--@samp{%r15}. | |
1161 | ||
1162 | @item | |
4bde3cdd | 1163 | the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}. |
55b62671 AJ |
1164 | |
1165 | @item | |
4bde3cdd | 1166 | the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}. |
55b62671 AJ |
1167 | |
1168 | @item | |
4bde3cdd | 1169 | the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}. |
55b62671 AJ |
1170 | |
1171 | @item | |
1172 | the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. | |
1173 | ||
1174 | @item | |
1175 | the 8 debug registers: @samp{%db8}--@samp{%db15}. | |
1176 | ||
1177 | @item | |
4bde3cdd UD |
1178 | the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}. |
1179 | @end itemize | |
1180 | ||
1181 | With the AVX extensions more registers were made available: | |
1182 | ||
1183 | @itemize @bullet | |
1184 | ||
1185 | @item | |
1186 | the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8 | |
1187 | available in 32-bit mode). The bottom 128 bits are overlaid with the | |
1188 | @samp{xmm0}--@samp{xmm15} registers. | |
1189 | ||
1190 | @end itemize | |
1191 | ||
4bde3cdd UD |
1192 | The AVX512 extensions added the following registers: |
1193 | ||
1194 | @itemize @bullet | |
1195 | ||
1196 | @item | |
1197 | the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8 | |
1198 | available in 32-bit mode). The bottom 128 bits are overlaid with the | |
1199 | @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are | |
1200 | overlaid with the @samp{%ymm0}--@samp{%ymm31} registers. | |
1201 | ||
1202 | @item | |
1203 | the 8 mask registers @samp{%k0}--@samp{%k7}. | |
1204 | ||
252b5132 RH |
1205 | @end itemize |
1206 | ||
1207 | @node i386-Prefixes | |
1208 | @section Instruction Prefixes | |
1209 | ||
1210 | @cindex i386 instruction prefixes | |
1211 | @cindex instruction prefixes, i386 | |
1212 | @cindex prefixes, i386 | |
1213 | Instruction prefixes are used to modify the following instruction. They | |
1214 | are used to repeat string instructions, to provide section overrides, to | |
1215 | perform bus lock operations, and to change operand and address sizes. | |
1216 | (Most instructions that normally operate on 32-bit operands will use | |
1217 | 16-bit operands if the instruction has an ``operand size'' prefix.) | |
1218 | Instruction prefixes are best written on the same line as the instruction | |
1219 | they act upon. For example, the @samp{scas} (scan string) instruction is | |
1220 | repeated with: | |
1221 | ||
1222 | @smallexample | |
1223 | repne scas %es:(%edi),%al | |
1224 | @end smallexample | |
1225 | ||
1226 | You may also place prefixes on the lines immediately preceding the | |
1227 | instruction, but this circumvents checks that @code{@value{AS}} does | |
1228 | with prefixes, and will not work with all prefixes. | |
1229 | ||
1230 | Here is a list of instruction prefixes: | |
1231 | ||
1232 | @cindex section override prefixes, i386 | |
1233 | @itemize @bullet | |
1234 | @item | |
1235 | Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, | |
1236 | @samp{fs}, @samp{gs}. These are automatically added by specifying | |
1237 | using the @var{section}:@var{memory-operand} form for memory references. | |
1238 | ||
1239 | @cindex size prefixes, i386 | |
1240 | @item | |
1241 | Operand/Address size prefixes @samp{data16} and @samp{addr16} | |
1242 | change 32-bit operands/addresses into 16-bit operands/addresses, | |
1243 | while @samp{data32} and @samp{addr32} change 16-bit ones (in a | |
1244 | @code{.code16} section) into 32-bit operands/addresses. These prefixes | |
1245 | @emph{must} appear on the same line of code as the instruction they | |
1246 | modify. For example, in a 16-bit @code{.code16} section, you might | |
1247 | write: | |
1248 | ||
1249 | @smallexample | |
1250 | addr32 jmpl *(%ebx) | |
1251 | @end smallexample | |
1252 | ||
1253 | @cindex bus lock prefixes, i386 | |
1254 | @cindex inhibiting interrupts, i386 | |
1255 | @item | |
1256 | The bus lock prefix @samp{lock} inhibits interrupts during execution of | |
1257 | the instruction it precedes. (This is only valid with certain | |
1258 | instructions; see a 80386 manual for details). | |
1259 | ||
1260 | @cindex coprocessor wait, i386 | |
1261 | @item | |
1262 | The wait for coprocessor prefix @samp{wait} waits for the coprocessor to | |
1263 | complete the current instruction. This should never be needed for the | |
1264 | 80386/80387 combination. | |
1265 | ||
1266 | @cindex repeat prefixes, i386 | |
1267 | @item | |
1268 | The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added | |
1269 | to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} | |
1270 | times if the current address size is 16-bits). | |
55b62671 AJ |
1271 | @cindex REX prefixes, i386 |
1272 | @item | |
1273 | The @samp{rex} family of prefixes is used by x86-64 to encode | |
1274 | extensions to i386 instruction set. The @samp{rex} prefix has four | |
1275 | bits --- an operand size overwrite (@code{64}) used to change operand size | |
1276 | from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the | |
1277 | register set. | |
1278 | ||
1279 | You may write the @samp{rex} prefixes directly. The @samp{rex64xyz} | |
1280 | instruction emits @samp{rex} prefix with all the bits set. By omitting | |
1281 | the @code{64}, @code{x}, @code{y} or @code{z} you may write other | |
1282 | prefixes as well. Normally, there is no need to write the prefixes | |
1283 | explicitly, since gas will automatically generate them based on the | |
1284 | instruction operands. | |
252b5132 RH |
1285 | @end itemize |
1286 | ||
1287 | @node i386-Memory | |
1288 | @section Memory References | |
1289 | ||
1290 | @cindex i386 memory references | |
1291 | @cindex memory references, i386 | |
55b62671 AJ |
1292 | @cindex x86-64 memory references |
1293 | @cindex memory references, x86-64 | |
252b5132 RH |
1294 | An Intel syntax indirect memory reference of the form |
1295 | ||
1296 | @smallexample | |
1297 | @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] | |
1298 | @end smallexample | |
1299 | ||
1300 | @noindent | |
1301 | is translated into the AT&T syntax | |
1302 | ||
1303 | @smallexample | |
1304 | @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) | |
1305 | @end smallexample | |
1306 | ||
1307 | @noindent | |
1308 | where @var{base} and @var{index} are the optional 32-bit base and | |
1309 | index registers, @var{disp} is the optional displacement, and | |
1310 | @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} | |
1311 | to calculate the address of the operand. If no @var{scale} is | |
1312 | specified, @var{scale} is taken to be 1. @var{section} specifies the | |
1313 | optional section register for the memory operand, and may override the | |
1314 | default section register (see a 80386 manual for section register | |
1315 | defaults). Note that section overrides in AT&T syntax @emph{must} | |
1316 | be preceded by a @samp{%}. If you specify a section override which | |
1317 | coincides with the default section register, @code{@value{AS}} does @emph{not} | |
1318 | output any section register override prefixes to assemble the given | |
1319 | instruction. Thus, section overrides can be specified to emphasize which | |
1320 | section register is used for a given memory operand. | |
1321 | ||
1322 | Here are some examples of Intel and AT&T style memory references: | |
1323 | ||
1324 | @table @asis | |
1325 | @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} | |
1326 | @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is | |
1327 | missing, and the default section is used (@samp{%ss} for addressing with | |
1328 | @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. | |
1329 | ||
1330 | @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} | |
1331 | @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is | |
1332 | @samp{foo}. All other fields are missing. The section register here | |
1333 | defaults to @samp{%ds}. | |
1334 | ||
1335 | @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} | |
1336 | This uses the value pointed to by @samp{foo} as a memory operand. | |
1337 | Note that @var{base} and @var{index} are both missing, but there is only | |
1338 | @emph{one} @samp{,}. This is a syntactic exception. | |
1339 | ||
1340 | @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} | |
1341 | This selects the contents of the variable @samp{foo} with section | |
1342 | register @var{section} being @samp{%gs}. | |
1343 | @end table | |
1344 | ||
1345 | Absolute (as opposed to PC relative) call and jump operands must be | |
1346 | prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} | |
1347 | always chooses PC relative addressing for jump/call labels. | |
1348 | ||
1349 | Any instruction that has a memory operand, but no register operand, | |
55b62671 AJ |
1350 | @emph{must} specify its size (byte, word, long, or quadruple) with an |
1351 | instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, | |
1352 | respectively). | |
1353 | ||
1354 | The x86-64 architecture adds an RIP (instruction pointer relative) | |
1355 | addressing. This addressing mode is specified by using @samp{rip} as a | |
1356 | base register. Only constant offsets are valid. For example: | |
1357 | ||
1358 | @table @asis | |
1359 | @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} | |
1360 | Points to the address 1234 bytes past the end of the current | |
1361 | instruction. | |
1362 | ||
1363 | @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} | |
1364 | Points to the @code{symbol} in RIP relative way, this is shorter than | |
1365 | the default absolute addressing. | |
1366 | @end table | |
1367 | ||
1368 | Other addressing modes remain unchanged in x86-64 architecture, except | |
1369 | registers used are 64-bit instead of 32-bit. | |
252b5132 | 1370 | |
fddf5b5b | 1371 | @node i386-Jumps |
252b5132 RH |
1372 | @section Handling of Jump Instructions |
1373 | ||
1374 | @cindex jump optimization, i386 | |
1375 | @cindex i386 jump optimization | |
55b62671 AJ |
1376 | @cindex jump optimization, x86-64 |
1377 | @cindex x86-64 jump optimization | |
252b5132 RH |
1378 | Jump instructions are always optimized to use the smallest possible |
1379 | displacements. This is accomplished by using byte (8-bit) displacement | |
1380 | jumps whenever the target is sufficiently close. If a byte displacement | |
fddf5b5b | 1381 | is insufficient a long displacement is used. We do not support |
252b5132 RH |
1382 | word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump |
1383 | instruction with the @samp{data16} instruction prefix), since the 80386 | |
1384 | insists upon masking @samp{%eip} to 16 bits after the word displacement | |
fddf5b5b | 1385 | is added. (See also @pxref{i386-Arch}) |
252b5132 RH |
1386 | |
1387 | Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, | |
1388 | @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte | |
1389 | displacements, so that if you use these instructions (@code{@value{GCC}} does | |
1390 | not use them) you may get an error message (and incorrect code). The AT&T | |
1391 | 80386 assembler tries to get around this problem by expanding @samp{jcxz foo} | |
1392 | to | |
1393 | ||
1394 | @smallexample | |
1395 | jcxz cx_zero | |
1396 | jmp cx_nonzero | |
1397 | cx_zero: jmp foo | |
1398 | cx_nonzero: | |
1399 | @end smallexample | |
1400 | ||
1401 | @node i386-Float | |
1402 | @section Floating Point | |
1403 | ||
1404 | @cindex i386 floating point | |
1405 | @cindex floating point, i386 | |
55b62671 AJ |
1406 | @cindex x86-64 floating point |
1407 | @cindex floating point, x86-64 | |
252b5132 RH |
1408 | All 80387 floating point types except packed BCD are supported. |
1409 | (BCD support may be added without much difficulty). These data | |
1410 | types are 16-, 32-, and 64- bit integers, and single (32-bit), | |
1411 | double (64-bit), and extended (80-bit) precision floating point. | |
1412 | Each supported type has an instruction mnemonic suffix and a constructor | |
1413 | associated with it. Instruction mnemonic suffixes specify the operand's | |
1414 | data type. Constructors build these data types into memory. | |
1415 | ||
1416 | @cindex @code{float} directive, i386 | |
1417 | @cindex @code{single} directive, i386 | |
1418 | @cindex @code{double} directive, i386 | |
1419 | @cindex @code{tfloat} directive, i386 | |
7d19d096 | 1420 | @cindex @code{hfloat} directive, i386 |
de133cf9 | 1421 | @cindex @code{bfloat16} directive, i386 |
55b62671 AJ |
1422 | @cindex @code{float} directive, x86-64 |
1423 | @cindex @code{single} directive, x86-64 | |
1424 | @cindex @code{double} directive, x86-64 | |
1425 | @cindex @code{tfloat} directive, x86-64 | |
7d19d096 | 1426 | @cindex @code{hfloat} directive, x86-64 |
de133cf9 | 1427 | @cindex @code{bfloat16} directive, x86-64 |
252b5132 RH |
1428 | @itemize @bullet |
1429 | @item | |
1430 | Floating point constructors are @samp{.float} or @samp{.single}, | |
de133cf9 JB |
1431 | @samp{.double}, @samp{.tfloat}, @samp{.hfloat}, and @samp{.bfloat16} for 32-, |
1432 | 64-, 80-, and 16-bit (two flavors) formats respectively. The former three | |
1433 | correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, and @samp{t}. | |
1434 | @samp{t} stands for 80-bit (ten byte) real. The 80387 only supports this | |
1435 | format via the @samp{fldt} (load 80-bit real to stack top) and @samp{fstpt} | |
1436 | (store 80-bit real and pop stack) instructions. | |
252b5132 RH |
1437 | |
1438 | @cindex @code{word} directive, i386 | |
1439 | @cindex @code{long} directive, i386 | |
1440 | @cindex @code{int} directive, i386 | |
1441 | @cindex @code{quad} directive, i386 | |
55b62671 AJ |
1442 | @cindex @code{word} directive, x86-64 |
1443 | @cindex @code{long} directive, x86-64 | |
1444 | @cindex @code{int} directive, x86-64 | |
1445 | @cindex @code{quad} directive, x86-64 | |
252b5132 RH |
1446 | @item |
1447 | Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and | |
1448 | @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The | |
a12f86b9 | 1449 | corresponding instruction mnemonic suffixes are @samp{s} (short), |
252b5132 RH |
1450 | @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, |
1451 | the 64-bit @samp{q} format is only present in the @samp{fildq} (load | |
1452 | quad integer to stack top) and @samp{fistpq} (store quad integer and pop | |
1453 | stack) instructions. | |
1454 | @end itemize | |
1455 | ||
1456 | Register to register operations should not use instruction mnemonic suffixes. | |
1457 | @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you | |
1458 | wrote @samp{fst %st, %st(1)}, since all register to register operations | |
1459 | use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, | |
1460 | which converts @samp{%st} from 80-bit to 64-bit floating point format, | |
1461 | then stores the result in the 4 byte location @samp{mem}) | |
1462 | ||
1463 | @node i386-SIMD | |
1464 | @section Intel's MMX and AMD's 3DNow! SIMD Operations | |
1465 | ||
1466 | @cindex MMX, i386 | |
1467 | @cindex 3DNow!, i386 | |
1468 | @cindex SIMD, i386 | |
55b62671 AJ |
1469 | @cindex MMX, x86-64 |
1470 | @cindex 3DNow!, x86-64 | |
1471 | @cindex SIMD, x86-64 | |
252b5132 RH |
1472 | |
1473 | @code{@value{AS}} supports Intel's MMX instruction set (SIMD | |
1474 | instructions for integer data), available on Intel's Pentium MMX | |
1475 | processors and Pentium II processors, AMD's K6 and K6-2 processors, | |
b45619c0 | 1476 | Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: |
252b5132 RH |
1477 | instruction set (SIMD instructions for 32-bit floating point data) |
1478 | available on AMD's K6-2 processor and possibly others in the future. | |
1479 | ||
1480 | Currently, @code{@value{AS}} does not support Intel's floating point | |
1481 | SIMD, Katmai (KNI). | |
1482 | ||
1483 | The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, | |
1484 | @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four | |
1485 | 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit | |
1486 | floating point values. The MMX registers cannot be used at the same time | |
1487 | as the floating point stack. | |
1488 | ||
1489 | See Intel and AMD documentation, keeping in mind that the operand order in | |
1490 | instructions is reversed from the Intel syntax. | |
1491 | ||
f88c9eb0 SP |
1492 | @node i386-LWP |
1493 | @section AMD's Lightweight Profiling Instructions | |
1494 | ||
1495 | @cindex LWP, i386 | |
1496 | @cindex LWP, x86-64 | |
1497 | ||
1498 | @code{@value{AS}} supports AMD's Lightweight Profiling (LWP) | |
1499 | instruction set, available on AMD's Family 15h (Orochi) processors. | |
1500 | ||
1501 | LWP enables applications to collect and manage performance data, and | |
1502 | react to performance events. The collection of performance data | |
1503 | requires no context switches. LWP runs in the context of a thread and | |
1504 | so several counters can be used independently across multiple threads. | |
1505 | LWP can be used in both 64-bit and legacy 32-bit modes. | |
1506 | ||
1507 | For detailed information on the LWP instruction set, see the | |
1508 | @cite{AMD Lightweight Profiling Specification} available at | |
1509 | @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. | |
1510 | ||
87973e9f QN |
1511 | @node i386-BMI |
1512 | @section Bit Manipulation Instructions | |
1513 | ||
1514 | @cindex BMI, i386 | |
1515 | @cindex BMI, x86-64 | |
1516 | ||
1517 | @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set. | |
1518 | ||
1519 | BMI instructions provide several instructions implementing individual | |
1520 | bit manipulation operations such as isolation, masking, setting, or | |
34bca508 | 1521 | resetting. |
87973e9f QN |
1522 | |
1523 | @c Need to add a specification citation here when available. | |
1524 | ||
2a2a0f38 QN |
1525 | @node i386-TBM |
1526 | @section AMD's Trailing Bit Manipulation Instructions | |
1527 | ||
1528 | @cindex TBM, i386 | |
1529 | @cindex TBM, x86-64 | |
1530 | ||
1531 | @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) | |
1532 | instruction set, available on AMD's BDVER2 processors (Trinity and | |
1533 | Viperfish). | |
1534 | ||
1535 | TBM instructions provide instructions implementing individual bit | |
1536 | manipulation operations such as isolating, masking, setting, resetting, | |
1537 | complementing, and operations on trailing zeros and ones. | |
1538 | ||
1539 | @c Need to add a specification citation here when available. | |
87973e9f | 1540 | |
252b5132 RH |
1541 | @node i386-16bit |
1542 | @section Writing 16-bit Code | |
1543 | ||
1544 | @cindex i386 16-bit code | |
1545 | @cindex 16-bit code, i386 | |
1546 | @cindex real-mode code, i386 | |
eecb386c | 1547 | @cindex @code{code16gcc} directive, i386 |
252b5132 RH |
1548 | @cindex @code{code16} directive, i386 |
1549 | @cindex @code{code32} directive, i386 | |
55b62671 AJ |
1550 | @cindex @code{code64} directive, i386 |
1551 | @cindex @code{code64} directive, x86-64 | |
1552 | While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code | |
1553 | or 64-bit x86-64 code depending on the default configuration, | |
252b5132 | 1554 | it also supports writing code to run in real mode or in 16-bit protected |
eecb386c AM |
1555 | mode code segments. To do this, put a @samp{.code16} or |
1556 | @samp{.code16gcc} directive before the assembly language instructions to | |
995cef8c L |
1557 | be run in 16-bit mode. You can switch @code{@value{AS}} to writing |
1558 | 32-bit code with the @samp{.code32} directive or 64-bit code with the | |
1559 | @samp{.code64} directive. | |
eecb386c AM |
1560 | |
1561 | @samp{.code16gcc} provides experimental support for generating 16-bit | |
1562 | code from gcc, and differs from @samp{.code16} in that @samp{call}, | |
1563 | @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, | |
1564 | @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions | |
1565 | default to 32-bit size. This is so that the stack pointer is | |
1566 | manipulated in the same way over function calls, allowing access to | |
1567 | function parameters at the same stack offsets as in 32-bit mode. | |
1568 | @samp{.code16gcc} also automatically adds address size prefixes where | |
1569 | necessary to use the 32-bit addressing modes that gcc generates. | |
252b5132 RH |
1570 | |
1571 | The code which @code{@value{AS}} generates in 16-bit mode will not | |
1572 | necessarily run on a 16-bit pre-80386 processor. To write code that | |
1573 | runs on such a processor, you must refrain from using @emph{any} 32-bit | |
1574 | constructs which require @code{@value{AS}} to output address or operand | |
1575 | size prefixes. | |
1576 | ||
1577 | Note that writing 16-bit code instructions by explicitly specifying a | |
1578 | prefix or an instruction mnemonic suffix within a 32-bit code section | |
1579 | generates different machine instructions than those generated for a | |
1580 | 16-bit code segment. In a 32-bit code section, the following code | |
1581 | generates the machine opcode bytes @samp{66 6a 04}, which pushes the | |
1582 | value @samp{4} onto the stack, decrementing @samp{%esp} by 2. | |
1583 | ||
1584 | @smallexample | |
1585 | pushw $4 | |
1586 | @end smallexample | |
1587 | ||
1588 | The same code in a 16-bit code section would generate the machine | |
b45619c0 | 1589 | opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which |
252b5132 RH |
1590 | is correct since the processor default operand size is assumed to be 16 |
1591 | bits in a 16-bit code section. | |
1592 | ||
e413e4e9 AM |
1593 | @node i386-Arch |
1594 | @section Specifying CPU Architecture | |
1595 | ||
1596 | @cindex arch directive, i386 | |
1597 | @cindex i386 arch directive | |
55b62671 AJ |
1598 | @cindex arch directive, x86-64 |
1599 | @cindex x86-64 arch directive | |
e413e4e9 AM |
1600 | |
1601 | @code{@value{AS}} may be told to assemble for a particular CPU | |
5c6af06e | 1602 | (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This |
e413e4e9 AM |
1603 | directive enables a warning when gas detects an instruction that is not |
1604 | supported on the CPU specified. The choices for @var{cpu_type} are: | |
1605 | ||
1606 | @multitable @columnfractions .20 .20 .20 .20 | |
f68697e8 | 1607 | @item @samp{default} @tab @samp{push} @tab @samp{pop} |
e413e4e9 AM |
1608 | @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} |
1609 | @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} | |
5c6af06e | 1610 | @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} |
ef05d495 | 1611 | @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} |
c085ab00 | 1612 | @item @samp{corei7} @tab @samp{iamcu} |
1543849b | 1613 | @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} |
5e5c50d3 | 1614 | @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} |
646cc3e0 | 1615 | @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3} |
b0e8fa7f TJ |
1616 | @item @samp{znver4} @tab @samp{btver1} @tab @samp{btver2} @tab @samp{generic32} |
1617 | @item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} | |
272a84b1 | 1618 | @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a} |
d76f7bc1 | 1619 | @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} |
c7b8aa3a L |
1620 | @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} |
1621 | @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} | |
1622 | @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} | |
6c30d220 | 1623 | @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} |
272a84b1 | 1624 | @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} |
cafa5ef7 | 1625 | @item @samp{.monitor} @tab @samp{.hle} @tab @samp{.rtm} @tab @samp{.tsx} |
c3bb24f5 | 1626 | @item @samp{.lahf_sahf} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} |
1dfc6506 L |
1627 | @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} |
1628 | @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} | |
1629 | @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} | |
2cc1b5aa | 1630 | @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} |
47acf0bd | 1631 | @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} |
8cfcb765 | 1632 | @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} |
9186c494 | 1633 | @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} |
0cc78721 | 1634 | @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} |
3ce2ebcf | 1635 | @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} |
23ae61ad | 1636 | @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} |
2188d6ea | 1637 | @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} |
675b9d61 NC |
1638 | @item @samp{.avx_ne_convert} @tab @samp{.rao_int} |
1639 | @item @samp{.fred} @tab @samp{.lkgs} | |
c48935d7 | 1640 | @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} |
d777820b | 1641 | @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} |
bb651e8b | 1642 | @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} |
d100d8c1 HJ |
1643 | @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16} |
1644 | @item @samp{.amx_complex} @tab @samp{.amx_tile} | |
c1fa250a | 1645 | @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset} |
1ceab344 | 1646 | @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} |
272a84b1 | 1647 | @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} |
60aa667e | 1648 | @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} |
142861df | 1649 | @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} |
646cc3e0 GG |
1650 | @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb} |
1651 | @item @samp{.tlbsync} | |
e413e4e9 AM |
1652 | @end multitable |
1653 | ||
fddf5b5b AM |
1654 | Apart from the warning, there are only two other effects on |
1655 | @code{@value{AS}} operation; Firstly, if you specify a CPU other than | |
e413e4e9 AM |
1656 | @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} |
1657 | will automatically use a two byte opcode sequence. The larger three | |
1658 | byte opcode sequence is used on the 486 (and when no architecture is | |
1659 | specified) because it executes faster on the 486. Note that you can | |
1660 | explicitly request the two byte opcode by writing @samp{sarl %eax}. | |
fddf5b5b AM |
1661 | Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, |
1662 | @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset | |
1663 | conditional jumps will be promoted when necessary to a two instruction | |
1664 | sequence consisting of a conditional jump of the opposite sense around | |
1665 | an unconditional jump to the target. | |
1666 | ||
32e876a8 JB |
1667 | Note that the sub-architecture specifiers (starting with a dot) can be prefixed |
1668 | with @code{no} to revoke the respective (and any dependent) functionality. | |
1669 | ||
5c6af06e JB |
1670 | Following the CPU architecture (but not a sub-architecture, which are those |
1671 | starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to | |
1672 | control automatic promotion of conditional jumps. @samp{jumps} is the | |
1673 | default, and enables jump promotion; All external jumps will be of the long | |
1674 | variety, and file-local jumps will be promoted as necessary. | |
1675 | (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as | |
1676 | byte offset jumps, and warns about file-local conditional jumps that | |
1677 | @code{@value{AS}} promotes. | |
fddf5b5b AM |
1678 | Unconditional jumps are treated as for @samp{jumps}. |
1679 | ||
1680 | For example | |
1681 | ||
1682 | @smallexample | |
1683 | .arch i8086,nojumps | |
1684 | @end smallexample | |
e413e4e9 | 1685 | |
bc31405e L |
1686 | @node i386-ISA |
1687 | @section AMD64 ISA vs. Intel64 ISA | |
1688 | ||
1689 | There are some discrepancies between AMD64 and Intel64 ISAs. | |
1690 | ||
1691 | @itemize @bullet | |
1692 | @item For @samp{movsxd} with 16-bit destination register, AMD64 | |
1693 | supports 32-bit source operand and Intel64 supports 16-bit source | |
1694 | operand. | |
5990e377 JB |
1695 | |
1696 | @item For far branches (with explicit memory operand), both ISAs support | |
1697 | 32- and 16-bit operand size. Intel64 additionally supports 64-bit | |
1698 | operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax | |
1699 | and with an explicit @samp{tbyte ptr} operand size specifier in Intel | |
1700 | syntax. | |
1701 | ||
1702 | @item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16- | |
1703 | and 32-bit operand size (32- and 48-bit memory operand) in both ISAs, | |
1704 | while Intel64 additionally supports 64-bit operand sise (80-bit memory | |
1705 | operands). | |
1706 | ||
bc31405e L |
1707 | @end itemize |
1708 | ||
5c9352f3 AM |
1709 | @node i386-Bugs |
1710 | @section AT&T Syntax bugs | |
1711 | ||
1712 | The UnixWare assembler, and probably other AT&T derived ix86 Unix | |
1713 | assemblers, generate floating point instructions with reversed source | |
1714 | and destination registers in certain cases. Unfortunately, gcc and | |
1715 | possibly many other programs use this reversed syntax, so we're stuck | |
1716 | with it. | |
1717 | ||
1718 | For example | |
1719 | ||
1720 | @smallexample | |
1721 | fsub %st,%st(3) | |
1722 | @end smallexample | |
1723 | @noindent | |
1724 | results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather | |
1725 | than the expected @samp{%st(3) - %st}. This happens with all the | |
1726 | non-commutative arithmetic floating point operations with two register | |
1727 | operands where the source register is @samp{%st} and the destination | |
1728 | register is @samp{%st(i)}. | |
1729 | ||
252b5132 RH |
1730 | @node i386-Notes |
1731 | @section Notes | |
1732 | ||
1733 | @cindex i386 @code{mul}, @code{imul} instructions | |
1734 | @cindex @code{mul} instruction, i386 | |
1735 | @cindex @code{imul} instruction, i386 | |
55b62671 AJ |
1736 | @cindex @code{mul} instruction, x86-64 |
1737 | @cindex @code{imul} instruction, x86-64 | |
252b5132 | 1738 | There is some trickery concerning the @samp{mul} and @samp{imul} |
55b62671 | 1739 | instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding |
252b5132 RH |
1740 | multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 |
1741 | for @samp{imul}) can be output only in the one operand form. Thus, | |
1742 | @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; | |
1743 | the expanding multiply would clobber the @samp{%edx} register, and this | |
1744 | would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the | |
1745 | 64-bit product in @samp{%edx:%eax}. | |
1746 | ||
1747 | We have added a two operand form of @samp{imul} when the first operand | |
1748 | is an immediate mode expression and the second operand is a register. | |
1749 | This is just a shorthand, so that, multiplying @samp{%eax} by 69, for | |
1750 | example, can be done with @samp{imul $69, %eax} rather than @samp{imul | |
1751 | $69, %eax, %eax}. | |
1752 |