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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
42a4f53d | 2 | Copyright (C) 1999-2019 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
aeb98c60 | 20 | |
d55e5aa6 | 21 | /* Standard C includes. */ |
3b273a55 | 22 | #include <elf/common.h> |
d55e5aa6 | 23 | #include <sys/procfs.h> |
ed9a39eb | 24 | #include <sys/user.h> |
ed9a39eb JM |
25 | #include <sys/utsname.h> |
26 | ||
d55e5aa6 TT |
27 | /* Local non-gdb includes. */ |
28 | #include "aarch32-linux-nat.h" | |
29 | #include "arm-linux-tdep.h" | |
30 | #include "arm-tdep.h" | |
31 | #include "auxv.h" | |
32 | #include "gdbcore.h" | |
33 | #include "gdbthread.h" | |
34 | #include "inferior.h" | |
35 | #include "linux-nat.h" | |
2fe7bab7 | 36 | #include "linux-tdep.h" |
d55e5aa6 TT |
37 | #include "nat/gdb_ptrace.h" |
38 | #include "nat/linux-ptrace.h" | |
39 | #include "observable.h" | |
40 | #include "regcache.h" | |
41 | #include "target-descriptions.h" | |
42 | #include "target.h" | |
95855ca8 | 43 | |
0963b4bd | 44 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
45 | #include "gregset.h" |
46 | ||
9308fc88 DJ |
47 | /* Defines ps_err_e, struct ps_prochandle. */ |
48 | #include "gdb_proc_service.h" | |
49 | ||
50 | #ifndef PTRACE_GET_THREAD_AREA | |
51 | #define PTRACE_GET_THREAD_AREA 22 | |
52 | #endif | |
53 | ||
05a4558a DJ |
54 | #ifndef PTRACE_GETWMMXREGS |
55 | #define PTRACE_GETWMMXREGS 18 | |
56 | #define PTRACE_SETWMMXREGS 19 | |
57 | #endif | |
58 | ||
3b273a55 RE |
59 | #ifndef PTRACE_GETVFPREGS |
60 | #define PTRACE_GETVFPREGS 27 | |
61 | #define PTRACE_SETVFPREGS 28 | |
62 | #endif | |
63 | ||
e3039479 UW |
64 | #ifndef PTRACE_GETHBPREGS |
65 | #define PTRACE_GETHBPREGS 29 | |
66 | #define PTRACE_SETHBPREGS 30 | |
67 | #endif | |
68 | ||
ed9a39eb JM |
69 | extern int arm_apcs_32; |
70 | ||
f6ac5f3d PA |
71 | class arm_linux_nat_target final : public linux_nat_target |
72 | { | |
73 | public: | |
74 | /* Add our register access methods. */ | |
75 | void fetch_registers (struct regcache *, int) override; | |
76 | void store_registers (struct regcache *, int) override; | |
77 | ||
78 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
79 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
80 | ||
81 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
82 | ||
83 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
84 | ||
85 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
86 | ||
87 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
88 | struct expression *) override; | |
89 | ||
90 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
91 | struct expression *) override; | |
57810aa7 | 92 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 93 | |
57810aa7 | 94 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 95 | |
57810aa7 | 96 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d PA |
97 | |
98 | const struct target_desc *read_description () override; | |
135340af PA |
99 | |
100 | /* Override linux_nat_target low methods. */ | |
101 | ||
102 | /* Handle thread creation and exit. */ | |
103 | void low_new_thread (struct lwp_info *lp) override; | |
104 | void low_delete_thread (struct arch_lwp_info *lp) override; | |
105 | void low_prepare_to_resume (struct lwp_info *lp) override; | |
106 | ||
107 | /* Handle process creation and exit. */ | |
108 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
109 | void low_forget_process (pid_t pid) override; | |
f6ac5f3d PA |
110 | }; |
111 | ||
112 | static arm_linux_nat_target the_arm_linux_nat_target; | |
113 | ||
41c49b06 | 114 | /* Get the whole floating point state of the process and store it |
c6b92abd | 115 | into regcache. */ |
ed9a39eb JM |
116 | |
117 | static void | |
56be3814 | 118 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 119 | { |
41c49b06 | 120 | int ret, regno, tid; |
cb587d83 | 121 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 122 | |
41c49b06 | 123 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 124 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 125 | |
ed9a39eb | 126 | /* Read the floating point state. */ |
0bdb2f78 | 127 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
128 | { |
129 | struct iovec iov; | |
130 | ||
131 | iov.iov_base = &fp; | |
132 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
133 | ||
134 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
135 | } | |
136 | else | |
137 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
138 | ||
ed9a39eb | 139 | if (ret < 0) |
d86feca3 | 140 | perror_with_name (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
141 | |
142 | /* Fetch fpsr. */ | |
73e1c03f | 143 | regcache->raw_supply (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
144 | |
145 | /* Fetch the floating point registers. */ | |
34e8f22d | 146 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 147 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
148 | } |
149 | ||
150 | /* Save the whole floating point state of the process using | |
c6b92abd | 151 | the contents from regcache. */ |
ed9a39eb JM |
152 | |
153 | static void | |
56be3814 | 154 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 155 | { |
41c49b06 | 156 | int ret, regno, tid; |
cb587d83 | 157 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 158 | |
41c49b06 | 159 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 160 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 161 | |
41c49b06 | 162 | /* Read the floating point state. */ |
0bdb2f78 | 163 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
164 | { |
165 | elf_fpregset_t fpregs; | |
166 | struct iovec iov; | |
167 | ||
168 | iov.iov_base = &fpregs; | |
169 | iov.iov_len = sizeof (fpregs); | |
170 | ||
171 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
172 | } | |
173 | else | |
174 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
175 | ||
41c49b06 | 176 | if (ret < 0) |
d86feca3 | 177 | perror_with_name (_("Unable to fetch the floating point registers.")); |
41c49b06 | 178 | |
ed9a39eb | 179 | /* Store fpsr. */ |
0ec9f114 | 180 | if (REG_VALID == regcache->get_register_status (ARM_FPS_REGNUM)) |
34a79281 | 181 | regcache->raw_collect (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
182 | |
183 | /* Store the floating point registers. */ | |
34e8f22d | 184 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
0ec9f114 | 185 | if (REG_VALID == regcache->get_register_status (regno)) |
56be3814 | 186 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 187 | |
0bdb2f78 | 188 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
189 | { |
190 | struct iovec iov; | |
191 | ||
192 | iov.iov_base = &fp; | |
193 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
194 | ||
195 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
196 | } | |
197 | else | |
198 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
199 | ||
ed9a39eb | 200 | if (ret < 0) |
d86feca3 | 201 | perror_with_name (_("Unable to store floating point registers.")); |
ed9a39eb JM |
202 | } |
203 | ||
204 | /* Fetch all general registers of the process and store into | |
c6b92abd | 205 | regcache. */ |
ed9a39eb JM |
206 | |
207 | static void | |
56be3814 | 208 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 209 | { |
cf4088a9 | 210 | int ret, tid; |
c2152441 | 211 | elf_gregset_t regs; |
ed9a39eb | 212 | |
41c49b06 | 213 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 214 | tid = regcache->ptid ().lwp (); |
10766686 | 215 | |
0bdb2f78 | 216 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
217 | { |
218 | struct iovec iov; | |
219 | ||
220 | iov.iov_base = ®s; | |
221 | iov.iov_len = sizeof (regs); | |
222 | ||
223 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
224 | } | |
225 | else | |
226 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
227 | ||
ed9a39eb | 228 | if (ret < 0) |
d86feca3 | 229 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 230 | |
f1b67888 | 231 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
232 | } |
233 | ||
ed9a39eb | 234 | static void |
56be3814 | 235 | store_regs (const struct regcache *regcache) |
ed9a39eb | 236 | { |
cf4088a9 | 237 | int ret, tid; |
c2152441 | 238 | elf_gregset_t regs; |
ed9a39eb | 239 | |
41c49b06 | 240 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 241 | tid = regcache->ptid ().lwp (); |
10766686 | 242 | |
41c49b06 | 243 | /* Fetch the general registers. */ |
0bdb2f78 | 244 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
245 | { |
246 | struct iovec iov; | |
247 | ||
248 | iov.iov_base = ®s; | |
249 | iov.iov_len = sizeof (regs); | |
250 | ||
251 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
252 | } | |
253 | else | |
254 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
255 | ||
ed9a39eb | 256 | if (ret < 0) |
d86feca3 | 257 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 258 | |
f1b67888 | 259 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 260 | |
0bdb2f78 | 261 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
262 | { |
263 | struct iovec iov; | |
264 | ||
265 | iov.iov_base = ®s; | |
266 | iov.iov_len = sizeof (regs); | |
267 | ||
268 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
269 | } | |
270 | else | |
271 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
272 | |
273 | if (ret < 0) | |
d86feca3 | 274 | perror_with_name (_("Unable to store general registers.")); |
ed9a39eb JM |
275 | } |
276 | ||
05a4558a DJ |
277 | /* Fetch all WMMX registers of the process and store into |
278 | regcache. */ | |
279 | ||
280 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
281 | ||
282 | static void | |
56be3814 | 283 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
284 | { |
285 | char regbuf[IWMMXT_REGS_SIZE]; | |
286 | int ret, regno, tid; | |
287 | ||
288 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 289 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
290 | |
291 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
292 | if (ret < 0) | |
d86feca3 | 293 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
294 | |
295 | for (regno = 0; regno < 16; regno++) | |
73e1c03f | 296 | regcache->raw_supply (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
297 | |
298 | for (regno = 0; regno < 2; regno++) | |
73e1c03f SM |
299 | regcache->raw_supply (regno + ARM_WCSSF_REGNUM, |
300 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
301 | |
302 | for (regno = 0; regno < 4; regno++) | |
73e1c03f SM |
303 | regcache->raw_supply (regno + ARM_WCGR0_REGNUM, |
304 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
305 | } |
306 | ||
307 | static void | |
56be3814 | 308 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
309 | { |
310 | char regbuf[IWMMXT_REGS_SIZE]; | |
311 | int ret, regno, tid; | |
312 | ||
313 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 314 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
315 | |
316 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
317 | if (ret < 0) | |
d86feca3 | 318 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
319 | |
320 | for (regno = 0; regno < 16; regno++) | |
0ec9f114 | 321 | if (REG_VALID == regcache->get_register_status (regno + ARM_WR0_REGNUM)) |
34a79281 | 322 | regcache->raw_collect (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
323 | |
324 | for (regno = 0; regno < 2; regno++) | |
0ec9f114 | 325 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCSSF_REGNUM)) |
34a79281 SM |
326 | regcache->raw_collect (regno + ARM_WCSSF_REGNUM, |
327 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
328 | |
329 | for (regno = 0; regno < 4; regno++) | |
0ec9f114 | 330 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCGR0_REGNUM)) |
34a79281 SM |
331 | regcache->raw_collect (regno + ARM_WCGR0_REGNUM, |
332 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
333 | |
334 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
335 | ||
336 | if (ret < 0) | |
d86feca3 | 337 | perror_with_name (_("Unable to store WMMX registers.")); |
05a4558a DJ |
338 | } |
339 | ||
3b273a55 RE |
340 | static void |
341 | fetch_vfp_regs (struct regcache *regcache) | |
342 | { | |
f1b67888 | 343 | gdb_byte regbuf[VFP_REGS_SIZE]; |
cf4088a9 | 344 | int ret, tid; |
ac7936df | 345 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 346 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
347 | |
348 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 349 | tid = regcache->ptid ().lwp (); |
3b273a55 | 350 | |
0bdb2f78 | 351 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
352 | { |
353 | struct iovec iov; | |
354 | ||
355 | iov.iov_base = regbuf; | |
356 | iov.iov_len = VFP_REGS_SIZE; | |
357 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
358 | } | |
359 | else | |
360 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
361 | ||
3b273a55 | 362 | if (ret < 0) |
d86feca3 | 363 | perror_with_name (_("Unable to fetch VFP registers.")); |
3b273a55 | 364 | |
f1b67888 YQ |
365 | aarch32_vfp_regcache_supply (regcache, regbuf, |
366 | tdep->vfp_register_count); | |
3b273a55 RE |
367 | } |
368 | ||
369 | static void | |
370 | store_vfp_regs (const struct regcache *regcache) | |
371 | { | |
f1b67888 | 372 | gdb_byte regbuf[VFP_REGS_SIZE]; |
cf4088a9 | 373 | int ret, tid; |
ac7936df | 374 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 375 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
376 | |
377 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 378 | tid = regcache->ptid ().lwp (); |
3b273a55 | 379 | |
0bdb2f78 | 380 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
381 | { |
382 | struct iovec iov; | |
383 | ||
384 | iov.iov_base = regbuf; | |
385 | iov.iov_len = VFP_REGS_SIZE; | |
386 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
387 | } | |
388 | else | |
389 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
390 | ||
3b273a55 | 391 | if (ret < 0) |
d86feca3 | 392 | perror_with_name (_("Unable to fetch VFP registers (for update).")); |
3b273a55 | 393 | |
f1b67888 YQ |
394 | aarch32_vfp_regcache_collect (regcache, regbuf, |
395 | tdep->vfp_register_count); | |
3b273a55 | 396 | |
0bdb2f78 | 397 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
398 | { |
399 | struct iovec iov; | |
400 | ||
401 | iov.iov_base = regbuf; | |
402 | iov.iov_len = VFP_REGS_SIZE; | |
403 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); | |
404 | } | |
405 | else | |
406 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
407 | |
408 | if (ret < 0) | |
d86feca3 | 409 | perror_with_name (_("Unable to store VFP registers.")); |
3b273a55 RE |
410 | } |
411 | ||
ed9a39eb JM |
412 | /* Fetch registers from the child process. Fetch all registers if |
413 | regno == -1, otherwise fetch all general registers or all floating | |
414 | point registers depending upon the value of regno. */ | |
415 | ||
f6ac5f3d PA |
416 | void |
417 | arm_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 418 | { |
ac7936df | 419 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
420 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
421 | ||
41c49b06 SB |
422 | if (-1 == regno) |
423 | { | |
56be3814 | 424 | fetch_regs (regcache); |
a56cc1ce | 425 | if (tdep->have_wmmx_registers) |
56be3814 | 426 | fetch_wmmx_regs (regcache); |
330c6ca9 | 427 | if (tdep->vfp_register_count > 0) |
3b273a55 | 428 | fetch_vfp_regs (regcache); |
4bd2e1b2 KC |
429 | if (tdep->have_fpa_registers) |
430 | fetch_fpregs (regcache); | |
41c49b06 | 431 | } |
4bd2e1b2 | 432 | else |
41c49b06 | 433 | { |
05a4558a | 434 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 435 | fetch_regs (regcache); |
05a4558a | 436 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 437 | fetch_fpregs (regcache); |
a56cc1ce | 438 | else if (tdep->have_wmmx_registers |
05a4558a | 439 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 440 | fetch_wmmx_regs (regcache); |
330c6ca9 | 441 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 442 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
443 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
444 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 445 | fetch_vfp_regs (regcache); |
41c49b06 | 446 | } |
ed9a39eb JM |
447 | } |
448 | ||
449 | /* Store registers back into the inferior. Store all registers if | |
450 | regno == -1, otherwise store all general registers or all floating | |
451 | point registers depending upon the value of regno. */ | |
452 | ||
f6ac5f3d PA |
453 | void |
454 | arm_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 455 | { |
ac7936df | 456 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
457 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
458 | ||
41c49b06 SB |
459 | if (-1 == regno) |
460 | { | |
56be3814 | 461 | store_regs (regcache); |
a56cc1ce | 462 | if (tdep->have_wmmx_registers) |
56be3814 | 463 | store_wmmx_regs (regcache); |
330c6ca9 | 464 | if (tdep->vfp_register_count > 0) |
3b273a55 | 465 | store_vfp_regs (regcache); |
4bd2e1b2 KC |
466 | if (tdep->have_fpa_registers) |
467 | store_fpregs (regcache); | |
41c49b06 SB |
468 | } |
469 | else | |
470 | { | |
05a4558a | 471 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 472 | store_regs (regcache); |
05a4558a | 473 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 474 | store_fpregs (regcache); |
a56cc1ce | 475 | else if (tdep->have_wmmx_registers |
05a4558a | 476 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 477 | store_wmmx_regs (regcache); |
330c6ca9 | 478 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 479 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
480 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
481 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 482 | store_vfp_regs (regcache); |
41c49b06 | 483 | } |
ed9a39eb JM |
484 | } |
485 | ||
cb587d83 DJ |
486 | /* Wrapper functions for the standard regset handling, used by |
487 | thread debugging. */ | |
41c49b06 SB |
488 | |
489 | void | |
7f7fe91e UW |
490 | fill_gregset (const struct regcache *regcache, |
491 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 492 | { |
7f7fe91e | 493 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
494 | } |
495 | ||
41c49b06 | 496 | void |
7f7fe91e | 497 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 498 | { |
7f7fe91e | 499 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
500 | } |
501 | ||
41c49b06 | 502 | void |
7f7fe91e UW |
503 | fill_fpregset (const struct regcache *regcache, |
504 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 505 | { |
7f7fe91e | 506 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
507 | } |
508 | ||
509 | /* Fill GDB's register array with the floating-point register values | |
510 | in *fpregsetp. */ | |
511 | ||
512 | void | |
7f7fe91e | 513 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 514 | { |
7f7fe91e | 515 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
516 | } |
517 | ||
9308fc88 DJ |
518 | /* Fetch the thread-local storage pointer for libthread_db. */ |
519 | ||
520 | ps_err_e | |
754653a7 | 521 | ps_get_thread_area (struct ps_prochandle *ph, |
9308fc88 DJ |
522 | lwpid_t lwpid, int idx, void **base) |
523 | { | |
524 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
525 | return PS_ERR; | |
526 | ||
527 | /* IDX is the bias from the thread pointer to the beginning of the | |
528 | thread descriptor. It has to be subtracted due to implementation | |
529 | quirks in libthread_db. */ | |
530 | *base = (void *) ((char *)*base - idx); | |
531 | ||
532 | return PS_OK; | |
533 | } | |
534 | ||
f6ac5f3d PA |
535 | const struct target_desc * |
536 | arm_linux_nat_target::read_description () | |
05a4558a | 537 | { |
0f83012e | 538 | CORE_ADDR arm_hwcap = linux_get_hwcap (this); |
05a4558a | 539 | |
0bdb2f78 | 540 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
541 | { |
542 | elf_gregset_t gpregs; | |
543 | struct iovec iov; | |
e38504b3 | 544 | int tid = inferior_ptid.lwp (); |
7efe48d1 YQ |
545 | |
546 | iov.iov_base = &gpregs; | |
547 | iov.iov_len = sizeof (gpregs); | |
548 | ||
549 | /* Check if PTRACE_GETREGSET works. */ | |
550 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 551 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 552 | else |
0bdb2f78 | 553 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
554 | } |
555 | ||
3b273a55 | 556 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 557 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
558 | |
559 | if (arm_hwcap & HWCAP_VFP) | |
560 | { | |
561 | int pid; | |
562 | char *buf; | |
563 | const struct target_desc * result = NULL; | |
564 | ||
565 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
566 | Neon with VFPv3-D32. */ | |
567 | if (arm_hwcap & HWCAP_NEON) | |
330c6ca9 | 568 | result = tdesc_arm_with_neon; |
3b273a55 | 569 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
330c6ca9 | 570 | result = tdesc_arm_with_vfpv3; |
3b273a55 | 571 | else |
330c6ca9 | 572 | result = tdesc_arm_with_vfpv2; |
3b273a55 RE |
573 | |
574 | /* Now make sure that the kernel supports reading these | |
575 | registers. Support was added in 2.6.30. */ | |
e38504b3 | 576 | pid = inferior_ptid.lwp (); |
3b273a55 | 577 | errno = 0; |
f844cf0e | 578 | buf = (char *) alloca (VFP_REGS_SIZE); |
3b273a55 RE |
579 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 |
580 | && errno == EIO) | |
581 | result = NULL; | |
582 | ||
583 | return result; | |
584 | } | |
585 | ||
4360561f | 586 | return this->beneath ()->read_description (); |
05a4558a DJ |
587 | } |
588 | ||
e3039479 UW |
589 | /* Information describing the hardware breakpoint capabilities. */ |
590 | struct arm_linux_hwbp_cap | |
591 | { | |
592 | gdb_byte arch; | |
593 | gdb_byte max_wp_length; | |
594 | gdb_byte wp_count; | |
595 | gdb_byte bp_count; | |
596 | }; | |
597 | ||
638c5f49 OJ |
598 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
599 | assume a maximum number of supported break-/watchpoints. */ | |
600 | #define MAX_BPTS 16 | |
601 | #define MAX_WPTS 16 | |
602 | ||
e3039479 UW |
603 | /* Get hold of the Hardware Breakpoint information for the target we are |
604 | attached to. Returns NULL if the kernel doesn't support Hardware | |
605 | breakpoints at all, or a pointer to the information structure. */ | |
606 | static const struct arm_linux_hwbp_cap * | |
607 | arm_linux_get_hwbp_cap (void) | |
608 | { | |
609 | /* The info structure we return. */ | |
610 | static struct arm_linux_hwbp_cap info; | |
611 | ||
612 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
613 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
614 | means INFO is in an initialized state. */ | |
615 | static int available = -1; | |
616 | ||
617 | if (available == -1) | |
618 | { | |
619 | int tid; | |
620 | unsigned int val; | |
621 | ||
e38504b3 | 622 | tid = inferior_ptid.lwp (); |
e3039479 UW |
623 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) |
624 | available = 0; | |
625 | else | |
626 | { | |
627 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
628 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
629 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
630 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
631 | |
632 | if (info.wp_count > MAX_WPTS) | |
633 | { | |
634 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
635 | supports %d"), MAX_WPTS, info.wp_count); | |
636 | info.wp_count = MAX_WPTS; | |
637 | } | |
638 | ||
639 | if (info.bp_count > MAX_BPTS) | |
640 | { | |
641 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
642 | supports %d"), MAX_BPTS, info.bp_count); | |
643 | info.bp_count = MAX_BPTS; | |
644 | } | |
e3039479 UW |
645 | available = (info.arch != 0); |
646 | } | |
647 | } | |
648 | ||
649 | return available == 1 ? &info : NULL; | |
650 | } | |
651 | ||
652 | /* How many hardware breakpoints are available? */ | |
653 | static int | |
654 | arm_linux_get_hw_breakpoint_count (void) | |
655 | { | |
656 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
657 | return cap != NULL ? cap->bp_count : 0; | |
658 | } | |
659 | ||
660 | /* How many hardware watchpoints are available? */ | |
661 | static int | |
662 | arm_linux_get_hw_watchpoint_count (void) | |
663 | { | |
664 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
665 | return cap != NULL ? cap->wp_count : 0; | |
666 | } | |
667 | ||
668 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
669 | there is not an appropriate resource available, otherwise returns 1. */ | |
f6ac5f3d PA |
670 | int |
671 | arm_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
672 | int cnt, int ot) | |
e3039479 UW |
673 | { |
674 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
675 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
676 | { | |
dbbf180a YQ |
677 | int count = arm_linux_get_hw_watchpoint_count (); |
678 | ||
679 | if (count == 0) | |
680 | return 0; | |
681 | else if (cnt + ot > count) | |
e3039479 UW |
682 | return -1; |
683 | } | |
684 | else if (type == bp_hardware_breakpoint) | |
685 | { | |
dbbf180a YQ |
686 | int count = arm_linux_get_hw_breakpoint_count (); |
687 | ||
688 | if (count == 0) | |
689 | return 0; | |
690 | else if (cnt > count) | |
e3039479 UW |
691 | return -1; |
692 | } | |
693 | else | |
694 | gdb_assert (FALSE); | |
695 | ||
696 | return 1; | |
697 | } | |
698 | ||
699 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
700 | typedef enum | |
701 | { | |
702 | arm_hwbp_break = 0, | |
703 | arm_hwbp_load = 1, | |
704 | arm_hwbp_store = 2, | |
705 | arm_hwbp_access = 3 | |
706 | } arm_hwbp_type; | |
707 | ||
708 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
709 | typedef unsigned int arm_hwbp_control_t; | |
710 | ||
711 | /* Structure used to keep track of hardware break-/watch-points. */ | |
712 | struct arm_linux_hw_breakpoint | |
713 | { | |
714 | /* Address to break on, or being watched. */ | |
715 | unsigned int address; | |
716 | /* Control register for break-/watch- point. */ | |
717 | arm_hwbp_control_t control; | |
718 | }; | |
719 | ||
638c5f49 OJ |
720 | /* Structure containing arrays of per process hardware break-/watchpoints |
721 | for caching address and control information. | |
e3039479 UW |
722 | |
723 | The Linux ptrace interface to hardware break-/watch-points presents the | |
724 | values in a vector centred around 0 (which is used fo generic information). | |
725 | Positive indicies refer to breakpoint addresses/control registers, negative | |
726 | indices to watchpoint addresses/control registers. | |
727 | ||
728 | The Linux vector is indexed as follows: | |
729 | -((i << 1) + 2): Control register for watchpoint i. | |
730 | -((i << 1) + 1): Address register for watchpoint i. | |
731 | 0: Information register. | |
732 | ((i << 1) + 1): Address register for breakpoint i. | |
733 | ((i << 1) + 2): Control register for breakpoint i. | |
734 | ||
735 | This structure is used as a per-thread cache of the state stored by the | |
736 | kernel, so that we don't need to keep calling into the kernel to find a | |
737 | free breakpoint. | |
738 | ||
739 | We treat break-/watch-points with their enable bit clear as being deleted. | |
740 | */ | |
638c5f49 | 741 | struct arm_linux_debug_reg_state |
e3039479 | 742 | { |
638c5f49 OJ |
743 | /* Hardware breakpoints for this process. */ |
744 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
745 | /* Hardware watchpoints for this process. */ | |
746 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
747 | }; | |
748 | ||
749 | /* Per-process arch-specific data we want to keep. */ | |
750 | struct arm_linux_process_info | |
e3039479 | 751 | { |
638c5f49 OJ |
752 | /* Linked list. */ |
753 | struct arm_linux_process_info *next; | |
754 | /* The process identifier. */ | |
755 | pid_t pid; | |
756 | /* Hardware break-/watchpoints state information. */ | |
757 | struct arm_linux_debug_reg_state state; | |
e3039479 | 758 | |
638c5f49 OJ |
759 | }; |
760 | ||
761 | /* Per-thread arch-specific data we want to keep. */ | |
762 | struct arch_lwp_info | |
763 | { | |
764 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
765 | char bpts_changed[MAX_BPTS]; | |
766 | char wpts_changed[MAX_WPTS]; | |
767 | }; | |
768 | ||
769 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
770 | ||
771 | /* Find process data for process PID. */ | |
772 | ||
773 | static struct arm_linux_process_info * | |
774 | arm_linux_find_process_pid (pid_t pid) | |
775 | { | |
776 | struct arm_linux_process_info *proc; | |
777 | ||
778 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
779 | if (proc->pid == pid) | |
780 | return proc; | |
781 | ||
782 | return NULL; | |
783 | } | |
784 | ||
785 | /* Add process data for process PID. Returns newly allocated info | |
786 | object. */ | |
787 | ||
788 | static struct arm_linux_process_info * | |
789 | arm_linux_add_process (pid_t pid) | |
790 | { | |
791 | struct arm_linux_process_info *proc; | |
e3039479 | 792 | |
8d749320 | 793 | proc = XCNEW (struct arm_linux_process_info); |
638c5f49 | 794 | proc->pid = pid; |
e3039479 | 795 | |
638c5f49 OJ |
796 | proc->next = arm_linux_process_list; |
797 | arm_linux_process_list = proc; | |
798 | ||
799 | return proc; | |
800 | } | |
801 | ||
802 | /* Get data specific info for process PID, creating it if necessary. | |
803 | Never returns NULL. */ | |
804 | ||
805 | static struct arm_linux_process_info * | |
806 | arm_linux_process_info_get (pid_t pid) | |
807 | { | |
808 | struct arm_linux_process_info *proc; | |
809 | ||
810 | proc = arm_linux_find_process_pid (pid); | |
811 | if (proc == NULL) | |
812 | proc = arm_linux_add_process (pid); | |
813 | ||
814 | return proc; | |
815 | } | |
816 | ||
817 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
818 | data structures that keep track of debug register state. */ | |
819 | ||
135340af PA |
820 | void |
821 | arm_linux_nat_target::low_forget_process (pid_t pid) | |
638c5f49 OJ |
822 | { |
823 | struct arm_linux_process_info *proc, **proc_link; | |
824 | ||
825 | proc = arm_linux_process_list; | |
826 | proc_link = &arm_linux_process_list; | |
827 | ||
828 | while (proc != NULL) | |
829 | { | |
830 | if (proc->pid == pid) | |
e3039479 | 831 | { |
638c5f49 OJ |
832 | *proc_link = proc->next; |
833 | ||
834 | xfree (proc); | |
835 | return; | |
e3039479 UW |
836 | } |
837 | ||
638c5f49 OJ |
838 | proc_link = &proc->next; |
839 | proc = *proc_link; | |
840 | } | |
841 | } | |
842 | ||
843 | /* Get hardware break-/watchpoint state for process PID. */ | |
844 | ||
845 | static struct arm_linux_debug_reg_state * | |
846 | arm_linux_get_debug_reg_state (pid_t pid) | |
847 | { | |
848 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
849 | } |
850 | ||
851 | /* Initialize an ARM hardware break-/watch-point control register value. | |
852 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
853 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
854 | */ | |
855 | static arm_hwbp_control_t | |
856 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
857 | arm_hwbp_type hwbp_type, | |
858 | int enable) | |
859 | { | |
860 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
861 | gdb_assert (hwbp_type != arm_hwbp_break | |
862 | || ((byte_address_select & 0xfU) != 0)); | |
863 | ||
864 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
865 | } | |
866 | ||
867 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
868 | static int | |
869 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
870 | { | |
871 | return control & 0x1; | |
872 | } | |
873 | ||
874 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
875 | static arm_hwbp_control_t | |
876 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
877 | { | |
878 | return control & ~0x1; | |
879 | } | |
880 | ||
881 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
882 | enabled, and will point to the placed address of BP_TGT. */ | |
883 | static void | |
884 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
885 | struct bp_target_info *bp_tgt, | |
886 | struct arm_linux_hw_breakpoint *p) | |
887 | { | |
888 | unsigned mask; | |
0d5ed153 | 889 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
890 | |
891 | /* We have to create a mask for the control register which says which bits | |
892 | of the word pointed to by address to break on. */ | |
893 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
894 | { |
895 | mask = 0x3; | |
896 | address &= ~1; | |
897 | } | |
e3039479 | 898 | else |
fcf303ab UW |
899 | { |
900 | mask = 0xf; | |
901 | address &= ~3; | |
902 | } | |
e3039479 | 903 | |
fcf303ab | 904 | p->address = (unsigned int) address; |
e3039479 UW |
905 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
906 | } | |
907 | ||
8156fe7f | 908 | /* Get the ARM hardware breakpoint type from the TYPE value we're |
f486487f | 909 | given when asked to set a watchpoint. */ |
e3039479 | 910 | static arm_hwbp_type |
f486487f | 911 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) |
e3039479 | 912 | { |
8156fe7f | 913 | if (type == hw_read) |
e3039479 | 914 | return arm_hwbp_load; |
8156fe7f | 915 | else if (type == hw_write) |
e3039479 UW |
916 | return arm_hwbp_store; |
917 | else | |
918 | return arm_hwbp_access; | |
919 | } | |
920 | ||
921 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
922 | to LEN. The type of watchpoint is given in RW. */ | |
923 | static void | |
f486487f SM |
924 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, |
925 | enum target_hw_bp_type type, | |
e3039479 UW |
926 | struct arm_linux_hw_breakpoint *p) |
927 | { | |
928 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
929 | unsigned mask; | |
930 | ||
931 | gdb_assert (cap != NULL); | |
932 | gdb_assert (cap->max_wp_length != 0); | |
933 | ||
934 | mask = (1 << len) - 1; | |
935 | ||
936 | p->address = (unsigned int) addr; | |
937 | p->control = arm_hwbp_control_initialize (mask, | |
f486487f | 938 | arm_linux_get_hwbp_type (type), 1); |
e3039479 UW |
939 | } |
940 | ||
941 | /* Are two break-/watch-points equal? */ | |
942 | static int | |
943 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
944 | const struct arm_linux_hw_breakpoint *p2) | |
945 | { | |
946 | return p1->address == p2->address && p1->control == p2->control; | |
947 | } | |
948 | ||
638c5f49 OJ |
949 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
950 | the current process. */ | |
951 | ||
638c5f49 | 952 | static int |
d3a70e03 | 953 | update_registers_callback (struct lwp_info *lwp, int watch, int index) |
638c5f49 | 954 | { |
638c5f49 OJ |
955 | if (lwp->arch_private == NULL) |
956 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
957 | ||
958 | /* The actual update is done later just before resuming the lwp, | |
959 | we just mark that the registers need updating. */ | |
d3a70e03 TT |
960 | if (watch) |
961 | lwp->arch_private->wpts_changed[index] = 1; | |
638c5f49 | 962 | else |
d3a70e03 | 963 | lwp->arch_private->bpts_changed[index] = 1; |
638c5f49 OJ |
964 | |
965 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
966 | we can update its breakpoint registers. */ | |
967 | if (!lwp->stopped) | |
968 | linux_stop_lwp (lwp); | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
e3039479 UW |
973 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
974 | =1) BPT for thread TID. */ | |
975 | static void | |
976 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 977 | int watchpoint) |
e3039479 | 978 | { |
638c5f49 OJ |
979 | int pid; |
980 | ptid_t pid_ptid; | |
e3039479 UW |
981 | gdb_byte count, i; |
982 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 983 | |
e99b03dc | 984 | pid = inferior_ptid.pid (); |
f2907e49 | 985 | pid_ptid = ptid_t (pid); |
e3039479 UW |
986 | |
987 | if (watchpoint) | |
988 | { | |
989 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 990 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
991 | } |
992 | else | |
993 | { | |
994 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 995 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
996 | } |
997 | ||
998 | for (i = 0; i < count; ++i) | |
999 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
1000 | { | |
638c5f49 | 1001 | bpts[i] = *bpt; |
d3a70e03 TT |
1002 | iterate_over_lwps (pid_ptid, |
1003 | [=] (struct lwp_info *info) | |
1004 | { | |
3a0e45b2 AH |
1005 | return update_registers_callback (info, watchpoint, |
1006 | i); | |
d3a70e03 | 1007 | }); |
638c5f49 | 1008 | break; |
e3039479 UW |
1009 | } |
1010 | ||
1011 | gdb_assert (i != count); | |
1012 | } | |
1013 | ||
1014 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1015 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1016 | static void | |
1017 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1018 | int watchpoint) |
e3039479 | 1019 | { |
638c5f49 | 1020 | int pid; |
e3039479 | 1021 | gdb_byte count, i; |
638c5f49 OJ |
1022 | ptid_t pid_ptid; |
1023 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 1024 | |
e99b03dc | 1025 | pid = inferior_ptid.pid (); |
f2907e49 | 1026 | pid_ptid = ptid_t (pid); |
e3039479 UW |
1027 | |
1028 | if (watchpoint) | |
1029 | { | |
1030 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1031 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1032 | } |
1033 | else | |
1034 | { | |
1035 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1036 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1037 | } |
1038 | ||
1039 | for (i = 0; i < count; ++i) | |
1040 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1041 | { | |
638c5f49 | 1042 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); |
3a0e45b2 AH |
1043 | iterate_over_lwps (pid_ptid, |
1044 | [=] (struct lwp_info *info) | |
1045 | { | |
1046 | return update_registers_callback (info, watchpoint, | |
1047 | i); | |
1048 | }); | |
638c5f49 | 1049 | break; |
e3039479 UW |
1050 | } |
1051 | ||
1052 | gdb_assert (i != count); | |
1053 | } | |
1054 | ||
1055 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1056 | int |
1057 | arm_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1058 | struct bp_target_info *bp_tgt) | |
e3039479 | 1059 | { |
e3039479 UW |
1060 | struct arm_linux_hw_breakpoint p; |
1061 | ||
1062 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1063 | return -1; | |
1064 | ||
1065 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1066 | |
1067 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1068 | |
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1073 | int |
1074 | arm_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1075 | struct bp_target_info *bp_tgt) | |
e3039479 | 1076 | { |
e3039479 UW |
1077 | struct arm_linux_hw_breakpoint p; |
1078 | ||
1079 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1080 | return -1; | |
1081 | ||
1082 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1083 | |
1084 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1085 | |
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1090 | ADDR? */ | |
f6ac5f3d PA |
1091 | int |
1092 | arm_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e3039479 UW |
1093 | { |
1094 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1095 | CORE_ADDR max_wp_length, aligned_addr; | |
1096 | ||
1097 | /* Can not set watchpoints for zero or negative lengths. */ | |
1098 | if (len <= 0) | |
1099 | return 0; | |
1100 | ||
1101 | /* Need to be able to use the ptrace interface. */ | |
1102 | if (cap == NULL || cap->wp_count == 0) | |
1103 | return 0; | |
1104 | ||
1105 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1106 | range covered by a watchpoint. */ | |
1107 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1108 | aligned_addr = addr & ~(max_wp_length - 1); | |
1109 | ||
1110 | if (aligned_addr + max_wp_length < addr + len) | |
1111 | return 0; | |
1112 | ||
1113 | /* The current ptrace interface can only handle watchpoints that are a | |
1114 | power of 2. */ | |
1115 | if ((len & (len - 1)) != 0) | |
1116 | return 0; | |
1117 | ||
1118 | /* All tests passed so we must be able to set a watchpoint. */ | |
1119 | return 1; | |
1120 | } | |
1121 | ||
1122 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1123 | int |
1124 | arm_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
1125 | enum target_hw_bp_type rw, | |
1126 | struct expression *cond) | |
e3039479 | 1127 | { |
e3039479 UW |
1128 | struct arm_linux_hw_breakpoint p; |
1129 | ||
1130 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1131 | return -1; | |
1132 | ||
1133 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1134 | |
1135 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1136 | |
1137 | return 0; | |
1138 | } | |
1139 | ||
1140 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1141 | int |
1142 | arm_linux_nat_target::remove_watchpoint (CORE_ADDR addr, | |
1143 | int len, enum target_hw_bp_type rw, | |
1144 | struct expression *cond) | |
e3039479 | 1145 | { |
e3039479 UW |
1146 | struct arm_linux_hw_breakpoint p; |
1147 | ||
1148 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1149 | return -1; | |
1150 | ||
1151 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1152 | |
1153 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1154 | |
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | /* What was the data address the target was stopped on accessing. */ | |
57810aa7 | 1159 | bool |
f6ac5f3d | 1160 | arm_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e3039479 | 1161 | { |
f865ee35 JK |
1162 | siginfo_t siginfo; |
1163 | int slot; | |
1164 | ||
1165 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 1166 | return false; |
e3039479 UW |
1167 | |
1168 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1169 | if (siginfo.si_signo != SIGTRAP |
1170 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 1171 | return false; |
e3039479 UW |
1172 | |
1173 | /* We must be able to set hardware watchpoints. */ | |
1174 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1175 | return 0; | |
1176 | ||
f865ee35 JK |
1177 | slot = siginfo.si_errno; |
1178 | ||
e3039479 UW |
1179 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1180 | a watchpoint. */ | |
1181 | if (slot >= 0) | |
57810aa7 | 1182 | return false; |
e3039479 | 1183 | |
f865ee35 | 1184 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 1185 | return true; |
e3039479 UW |
1186 | } |
1187 | ||
1188 | /* Has the target been stopped by hitting a watchpoint? */ | |
57810aa7 | 1189 | bool |
f6ac5f3d | 1190 | arm_linux_nat_target::stopped_by_watchpoint () |
e3039479 UW |
1191 | { |
1192 | CORE_ADDR addr; | |
f6ac5f3d | 1193 | return stopped_data_address (&addr); |
e3039479 UW |
1194 | } |
1195 | ||
57810aa7 | 1196 | bool |
f6ac5f3d PA |
1197 | arm_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
1198 | CORE_ADDR start, | |
1199 | int length) | |
e3039479 UW |
1200 | { |
1201 | return start <= addr && start + length - 1 >= addr; | |
1202 | } | |
1203 | ||
1204 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1205 | in the parent thread to the child thread. */ | |
135340af PA |
1206 | void |
1207 | arm_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e3039479 | 1208 | { |
638c5f49 OJ |
1209 | int i; |
1210 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1211 | ||
1212 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1213 | for this thread need to be initialized. */ | |
e3039479 | 1214 | |
638c5f49 | 1215 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1216 | { |
638c5f49 OJ |
1217 | info->bpts_changed[i] = 1; |
1218 | info->wpts_changed[i] = 1; | |
e3039479 | 1219 | } |
638c5f49 OJ |
1220 | |
1221 | lp->arch_private = info; | |
e3039479 UW |
1222 | } |
1223 | ||
466eecee SM |
1224 | /* Function to call when a thread is being deleted. */ |
1225 | ||
135340af PA |
1226 | void |
1227 | arm_linux_nat_target::low_delete_thread (struct arch_lwp_info *arch_lwp) | |
466eecee SM |
1228 | { |
1229 | xfree (arch_lwp); | |
1230 | } | |
1231 | ||
638c5f49 OJ |
1232 | /* Called when resuming a thread. |
1233 | The hardware debug registers are updated when there is any change. */ | |
1234 | ||
135340af PA |
1235 | void |
1236 | arm_linux_nat_target::low_prepare_to_resume (struct lwp_info *lwp) | |
e3039479 | 1237 | { |
638c5f49 OJ |
1238 | int pid, i; |
1239 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1240 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1241 | ||
e38504b3 | 1242 | pid = lwp->ptid.lwp (); |
e99b03dc TT |
1243 | bpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->bpts; |
1244 | wpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->wpts; | |
638c5f49 OJ |
1245 | |
1246 | /* NULL means this is the main thread still going through the shell, | |
1247 | or, no watchpoint has been set yet. In that case, there's | |
1248 | nothing to do. */ | |
1249 | if (arm_lwp_info == NULL) | |
1250 | return; | |
e3039479 | 1251 | |
638c5f49 OJ |
1252 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1253 | if (arm_lwp_info->bpts_changed[i]) | |
1254 | { | |
1255 | errno = 0; | |
1256 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1257 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1258 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1259 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1260 | ||
1261 | if (bpts[i].control != 0) | |
1262 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1263 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1264 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1265 | ||
1266 | arm_lwp_info->bpts_changed[i] = 0; | |
1267 | } | |
e3039479 | 1268 | |
638c5f49 OJ |
1269 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1270 | if (arm_lwp_info->wpts_changed[i]) | |
1271 | { | |
1272 | errno = 0; | |
1273 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1274 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1275 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1276 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1277 | ||
1278 | if (wpts[i].control != 0) | |
1279 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1280 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1281 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1282 | ||
1283 | arm_lwp_info->wpts_changed[i] = 0; | |
1284 | } | |
1285 | } | |
1286 | ||
1287 | /* linux_nat_new_fork hook. */ | |
1288 | ||
135340af PA |
1289 | void |
1290 | arm_linux_nat_target::low_new_fork (struct lwp_info *parent, pid_t child_pid) | |
638c5f49 OJ |
1291 | { |
1292 | pid_t parent_pid; | |
1293 | struct arm_linux_debug_reg_state *parent_state; | |
1294 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1295 | |
638c5f49 OJ |
1296 | /* NULL means no watchpoint has ever been set in the parent. In |
1297 | that case, there's nothing to do. */ | |
1298 | if (parent->arch_private == NULL) | |
1299 | return; | |
e3039479 | 1300 | |
638c5f49 OJ |
1301 | /* GDB core assumes the child inherits the watchpoints/hw |
1302 | breakpoints of the parent, and will remove them all from the | |
1303 | forked off process. Copy the debug registers mirrors into the | |
1304 | new process so that all breakpoints and watchpoints can be | |
1305 | removed together. */ | |
e3039479 | 1306 | |
e99b03dc | 1307 | parent_pid = parent->ptid.pid (); |
638c5f49 OJ |
1308 | parent_state = arm_linux_get_debug_reg_state (parent_pid); |
1309 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1310 | *child_state = *parent_state; | |
e3039479 UW |
1311 | } |
1312 | ||
ed9a39eb JM |
1313 | void |
1314 | _initialize_arm_linux_nat (void) | |
1315 | { | |
10d6c8cd | 1316 | /* Register the target. */ |
f6ac5f3d | 1317 | linux_target = &the_arm_linux_nat_target; |
d9f719f1 | 1318 | add_inf_child_target (&the_arm_linux_nat_target); |
ed9a39eb | 1319 | } |