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456f8b9d | 1 | /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger. |
1e698235 | 2 | Copyright 2002, 2003 Free Software Foundation, Inc. |
456f8b9d DB |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "defs.h" | |
8baa6f92 | 22 | #include "gdb_string.h" |
456f8b9d DB |
23 | #include "inferior.h" |
24 | #include "symfile.h" /* for entry_point_address */ | |
25 | #include "gdbcore.h" | |
26 | #include "arch-utils.h" | |
27 | #include "regcache.h" | |
8baa6f92 | 28 | #include "frame.h" |
1cb761c7 KB |
29 | #include "frame-unwind.h" |
30 | #include "frame-base.h" | |
8baa6f92 | 31 | #include "trad-frame.h" |
dcc6aaff | 32 | #include "dis-asm.h" |
526eef89 KB |
33 | #include "gdb_assert.h" |
34 | #include "sim-regno.h" | |
35 | #include "gdb/sim-frv.h" | |
36 | #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */ | |
456f8b9d DB |
37 | |
38 | extern void _initialize_frv_tdep (void); | |
39 | ||
40 | static gdbarch_init_ftype frv_gdbarch_init; | |
41 | ||
42 | static gdbarch_register_name_ftype frv_register_name; | |
456f8b9d | 43 | static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc; |
46a16dba | 44 | static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address; |
456f8b9d | 45 | static gdbarch_skip_prologue_ftype frv_skip_prologue; |
456f8b9d | 46 | static gdbarch_frameless_function_invocation_ftype frv_frameless_function_invocation; |
aed7f26a MS |
47 | static gdbarch_deprecated_push_arguments_ftype frv_push_arguments; |
48 | static gdbarch_deprecated_saved_pc_after_call_ftype frv_saved_pc_after_call; | |
456f8b9d | 49 | |
526eef89 KB |
50 | /* Register numbers. The order in which these appear define the |
51 | remote protocol, so take care in changing them. */ | |
456f8b9d | 52 | enum { |
456f8b9d DB |
53 | /* Register numbers 0 -- 63 are always reserved for general-purpose |
54 | registers. The chip at hand may have less. */ | |
55 | first_gpr_regnum = 0, | |
56 | sp_regnum = 1, | |
57 | fp_regnum = 2, | |
58 | struct_return_regnum = 3, | |
59 | last_gpr_regnum = 63, | |
60 | ||
61 | /* Register numbers 64 -- 127 are always reserved for floating-point | |
62 | registers. The chip at hand may have less. */ | |
63 | first_fpr_regnum = 64, | |
64 | last_fpr_regnum = 127, | |
65 | ||
526eef89 | 66 | /* The PC register. */ |
456f8b9d | 67 | pc_regnum = 128, |
526eef89 KB |
68 | |
69 | /* Register numbers 129 on up are always reserved for special-purpose | |
70 | registers. */ | |
71 | first_spr_regnum = 129, | |
456f8b9d DB |
72 | psr_regnum = 129, |
73 | ccr_regnum = 130, | |
74 | cccr_regnum = 131, | |
75 | tbr_regnum = 135, | |
76 | brr_regnum = 136, | |
77 | dbar0_regnum = 137, | |
78 | dbar1_regnum = 138, | |
79 | dbar2_regnum = 139, | |
80 | dbar3_regnum = 140, | |
81 | lr_regnum = 145, | |
82 | lcr_regnum = 146, | |
526eef89 KB |
83 | iacc0h_regnum = 147, |
84 | iacc0l_regnum = 148, | |
85 | last_spr_regnum = 148, | |
86 | ||
87 | /* The total number of registers we know exist. */ | |
88 | frv_num_regs = last_spr_regnum + 1 | |
456f8b9d DB |
89 | }; |
90 | ||
91 | static LONGEST frv_call_dummy_words[] = | |
92 | {0}; | |
93 | ||
94 | ||
1cb761c7 | 95 | struct frv_unwind_cache /* was struct frame_extra_info */ |
456f8b9d | 96 | { |
1cb761c7 KB |
97 | /* The previous frame's inner-most stack address. Used as this |
98 | frame ID's stack_addr. */ | |
99 | CORE_ADDR prev_sp; | |
456f8b9d | 100 | |
1cb761c7 KB |
101 | /* The frame's base, optionally used by the high-level debug info. */ |
102 | CORE_ADDR base; | |
8baa6f92 KB |
103 | |
104 | /* Table indicating the location of each and every register. */ | |
105 | struct trad_frame_saved_reg *saved_regs; | |
456f8b9d DB |
106 | }; |
107 | ||
108 | ||
109 | /* A structure describing a particular variant of the FRV. | |
110 | We allocate and initialize one of these structures when we create | |
111 | the gdbarch object for a variant. | |
112 | ||
113 | At the moment, all the FR variants we support differ only in which | |
114 | registers are present; the portable code of GDB knows that | |
115 | registers whose names are the empty string don't exist, so the | |
116 | `register_names' array captures all the per-variant information we | |
117 | need. | |
118 | ||
119 | in the future, if we need to have per-variant maps for raw size, | |
120 | virtual type, etc., we should replace register_names with an array | |
121 | of structures, each of which gives all the necessary info for one | |
122 | register. Don't stick parallel arrays in here --- that's so | |
123 | Fortran. */ | |
124 | struct gdbarch_tdep | |
125 | { | |
126 | /* How many general-purpose registers does this variant have? */ | |
127 | int num_gprs; | |
128 | ||
129 | /* How many floating-point registers does this variant have? */ | |
130 | int num_fprs; | |
131 | ||
132 | /* How many hardware watchpoints can it support? */ | |
133 | int num_hw_watchpoints; | |
134 | ||
135 | /* How many hardware breakpoints can it support? */ | |
136 | int num_hw_breakpoints; | |
137 | ||
138 | /* Register names. */ | |
139 | char **register_names; | |
140 | }; | |
141 | ||
142 | #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch)) | |
143 | ||
144 | ||
145 | /* Allocate a new variant structure, and set up default values for all | |
146 | the fields. */ | |
147 | static struct gdbarch_tdep * | |
5ae5f592 | 148 | new_variant (void) |
456f8b9d DB |
149 | { |
150 | struct gdbarch_tdep *var; | |
151 | int r; | |
152 | char buf[20]; | |
153 | ||
154 | var = xmalloc (sizeof (*var)); | |
155 | memset (var, 0, sizeof (*var)); | |
156 | ||
157 | var->num_gprs = 64; | |
158 | var->num_fprs = 64; | |
159 | var->num_hw_watchpoints = 0; | |
160 | var->num_hw_breakpoints = 0; | |
161 | ||
162 | /* By default, don't supply any general-purpose or floating-point | |
163 | register names. */ | |
164 | var->register_names = (char **) xmalloc (frv_num_regs * sizeof (char *)); | |
165 | for (r = 0; r < frv_num_regs; r++) | |
166 | var->register_names[r] = ""; | |
167 | ||
526eef89 | 168 | /* Do, however, supply default names for the known special-purpose |
456f8b9d | 169 | registers. */ |
456f8b9d DB |
170 | |
171 | var->register_names[pc_regnum] = "pc"; | |
172 | var->register_names[lr_regnum] = "lr"; | |
173 | var->register_names[lcr_regnum] = "lcr"; | |
174 | ||
175 | var->register_names[psr_regnum] = "psr"; | |
176 | var->register_names[ccr_regnum] = "ccr"; | |
177 | var->register_names[cccr_regnum] = "cccr"; | |
178 | var->register_names[tbr_regnum] = "tbr"; | |
179 | ||
180 | /* Debug registers. */ | |
181 | var->register_names[brr_regnum] = "brr"; | |
182 | var->register_names[dbar0_regnum] = "dbar0"; | |
183 | var->register_names[dbar1_regnum] = "dbar1"; | |
184 | var->register_names[dbar2_regnum] = "dbar2"; | |
185 | var->register_names[dbar3_regnum] = "dbar3"; | |
186 | ||
526eef89 KB |
187 | /* iacc0 (Only found on MB93405.) */ |
188 | var->register_names[iacc0h_regnum] = "iacc0h"; | |
189 | var->register_names[iacc0l_regnum] = "iacc0l"; | |
190 | ||
456f8b9d DB |
191 | return var; |
192 | } | |
193 | ||
194 | ||
195 | /* Indicate that the variant VAR has NUM_GPRS general-purpose | |
196 | registers, and fill in the names array appropriately. */ | |
197 | static void | |
198 | set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs) | |
199 | { | |
200 | int r; | |
201 | ||
202 | var->num_gprs = num_gprs; | |
203 | ||
204 | for (r = 0; r < num_gprs; ++r) | |
205 | { | |
206 | char buf[20]; | |
207 | ||
208 | sprintf (buf, "gr%d", r); | |
209 | var->register_names[first_gpr_regnum + r] = xstrdup (buf); | |
210 | } | |
211 | } | |
212 | ||
213 | ||
214 | /* Indicate that the variant VAR has NUM_FPRS floating-point | |
215 | registers, and fill in the names array appropriately. */ | |
216 | static void | |
217 | set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs) | |
218 | { | |
219 | int r; | |
220 | ||
221 | var->num_fprs = num_fprs; | |
222 | ||
223 | for (r = 0; r < num_fprs; ++r) | |
224 | { | |
225 | char buf[20]; | |
226 | ||
227 | sprintf (buf, "fr%d", r); | |
228 | var->register_names[first_fpr_regnum + r] = xstrdup (buf); | |
229 | } | |
230 | } | |
231 | ||
232 | ||
233 | static const char * | |
234 | frv_register_name (int reg) | |
235 | { | |
236 | if (reg < 0) | |
237 | return "?toosmall?"; | |
238 | if (reg >= frv_num_regs) | |
239 | return "?toolarge?"; | |
240 | ||
241 | return CURRENT_VARIANT->register_names[reg]; | |
242 | } | |
243 | ||
526eef89 | 244 | |
456f8b9d | 245 | static struct type * |
7f398216 | 246 | frv_register_type (struct gdbarch *gdbarch, int reg) |
456f8b9d | 247 | { |
526eef89 | 248 | if (reg >= first_fpr_regnum && reg <= last_fpr_regnum) |
456f8b9d DB |
249 | return builtin_type_float; |
250 | else | |
526eef89 | 251 | return builtin_type_int32; |
456f8b9d DB |
252 | } |
253 | ||
526eef89 KB |
254 | static int |
255 | frv_register_sim_regno (int reg) | |
256 | { | |
257 | static const int spr_map[] = | |
258 | { | |
259 | H_SPR_PSR, /* psr_regnum */ | |
260 | H_SPR_CCR, /* ccr_regnum */ | |
261 | H_SPR_CCCR, /* cccr_regnum */ | |
262 | -1, /* 132 */ | |
263 | -1, /* 133 */ | |
264 | -1, /* 134 */ | |
265 | H_SPR_TBR, /* tbr_regnum */ | |
266 | H_SPR_BRR, /* brr_regnum */ | |
267 | H_SPR_DBAR0, /* dbar0_regnum */ | |
268 | H_SPR_DBAR1, /* dbar1_regnum */ | |
269 | H_SPR_DBAR2, /* dbar2_regnum */ | |
270 | H_SPR_DBAR3, /* dbar3_regnum */ | |
271 | -1, /* 141 */ | |
272 | -1, /* 142 */ | |
273 | -1, /* 143 */ | |
274 | -1, /* 144 */ | |
275 | H_SPR_LR, /* lr_regnum */ | |
276 | H_SPR_LCR, /* lcr_regnum */ | |
277 | H_SPR_IACC0H, /* iacc0h_regnum */ | |
278 | H_SPR_IACC0L /* iacc0l_regnum */ | |
279 | }; | |
280 | ||
281 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
282 | ||
283 | if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) | |
284 | return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; | |
285 | else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum) | |
286 | return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM; | |
287 | else if (pc_regnum == reg) | |
288 | return SIM_FRV_PC_REGNUM; | |
289 | else if (reg >= first_spr_regnum | |
290 | && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0])) | |
291 | { | |
292 | int spr_reg_offset = spr_map[reg - first_spr_regnum]; | |
293 | ||
294 | if (spr_reg_offset < 0) | |
295 | return SIM_REGNO_DOES_NOT_EXIST; | |
296 | else | |
297 | return SIM_FRV_SPR0_REGNUM + spr_reg_offset; | |
298 | } | |
299 | ||
300 | internal_error (__FILE__, __LINE__, "Bad register number %d", reg); | |
301 | } | |
302 | ||
456f8b9d DB |
303 | static const unsigned char * |
304 | frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp) | |
305 | { | |
306 | static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01}; | |
307 | *lenp = sizeof (breakpoint); | |
308 | return breakpoint; | |
309 | } | |
310 | ||
46a16dba KB |
311 | /* Define the maximum number of instructions which may be packed into a |
312 | bundle (VLIW instruction). */ | |
313 | static const int max_instrs_per_bundle = 8; | |
314 | ||
315 | /* Define the size (in bytes) of an FR-V instruction. */ | |
316 | static const int frv_instr_size = 4; | |
317 | ||
318 | /* Adjust a breakpoint's address to account for the FR-V architecture's | |
319 | constraint that a break instruction must not appear as any but the | |
320 | first instruction in the bundle. */ | |
321 | static CORE_ADDR | |
322 | frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
323 | { | |
324 | int count = max_instrs_per_bundle; | |
325 | CORE_ADDR addr = bpaddr - frv_instr_size; | |
326 | CORE_ADDR func_start = get_pc_function_start (bpaddr); | |
327 | ||
328 | /* Find the end of the previous packing sequence. This will be indicated | |
329 | by either attempting to access some inaccessible memory or by finding | |
330 | an instruction word whose packing bit is set to one. */ | |
331 | while (count-- > 0 && addr >= func_start) | |
332 | { | |
333 | char instr[frv_instr_size]; | |
334 | int status; | |
335 | ||
336 | status = read_memory_nobpt (addr, instr, sizeof instr); | |
337 | ||
338 | if (status != 0) | |
339 | break; | |
340 | ||
341 | /* This is a big endian architecture, so byte zero will have most | |
342 | significant byte. The most significant bit of this byte is the | |
343 | packing bit. */ | |
344 | if (instr[0] & 0x80) | |
345 | break; | |
346 | ||
347 | addr -= frv_instr_size; | |
348 | } | |
349 | ||
350 | if (count > 0) | |
351 | bpaddr = addr + frv_instr_size; | |
352 | ||
353 | return bpaddr; | |
354 | } | |
355 | ||
456f8b9d DB |
356 | |
357 | /* Return true if REG is a caller-saves ("scratch") register, | |
358 | false otherwise. */ | |
359 | static int | |
360 | is_caller_saves_reg (int reg) | |
361 | { | |
362 | return ((4 <= reg && reg <= 7) | |
363 | || (14 <= reg && reg <= 15) | |
364 | || (32 <= reg && reg <= 47)); | |
365 | } | |
366 | ||
367 | ||
368 | /* Return true if REG is a callee-saves register, false otherwise. */ | |
369 | static int | |
370 | is_callee_saves_reg (int reg) | |
371 | { | |
372 | return ((16 <= reg && reg <= 31) | |
373 | || (48 <= reg && reg <= 63)); | |
374 | } | |
375 | ||
376 | ||
377 | /* Return true if REG is an argument register, false otherwise. */ | |
378 | static int | |
379 | is_argument_reg (int reg) | |
380 | { | |
381 | return (8 <= reg && reg <= 13); | |
382 | } | |
383 | ||
384 | ||
385 | /* Scan an FR-V prologue, starting at PC, until frame->PC. | |
386 | If FRAME is non-zero, fill in its saved_regs with appropriate addresses. | |
387 | We assume FRAME's saved_regs array has already been allocated and cleared. | |
388 | Return the first PC value after the prologue. | |
389 | ||
390 | Note that, for unoptimized code, we almost don't need this function | |
391 | at all; all arguments and locals live on the stack, so we just need | |
392 | the FP to find everything. The catch: structures passed by value | |
393 | have their addresses living in registers; they're never spilled to | |
394 | the stack. So if you ever want to be able to get to these | |
395 | arguments in any frame but the top, you'll need to do this serious | |
396 | prologue analysis. */ | |
397 | static CORE_ADDR | |
1cb761c7 KB |
398 | frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
399 | struct frv_unwind_cache *info) | |
456f8b9d DB |
400 | { |
401 | /* When writing out instruction bitpatterns, we use the following | |
402 | letters to label instruction fields: | |
403 | P - The parallel bit. We don't use this. | |
404 | J - The register number of GRj in the instruction description. | |
405 | K - The register number of GRk in the instruction description. | |
406 | I - The register number of GRi. | |
407 | S - a signed imediate offset. | |
408 | U - an unsigned immediate offset. | |
409 | ||
410 | The dots below the numbers indicate where hex digit boundaries | |
411 | fall, to make it easier to check the numbers. */ | |
412 | ||
413 | /* Non-zero iff we've seen the instruction that initializes the | |
414 | frame pointer for this function's frame. */ | |
415 | int fp_set = 0; | |
416 | ||
417 | /* If fp_set is non_zero, then this is the distance from | |
418 | the stack pointer to frame pointer: fp = sp + fp_offset. */ | |
419 | int fp_offset = 0; | |
420 | ||
421 | /* Total size of frame prior to any alloca operations. */ | |
422 | int framesize = 0; | |
423 | ||
1cb761c7 KB |
424 | /* Flag indicating if lr has been saved on the stack. */ |
425 | int lr_saved_on_stack = 0; | |
426 | ||
456f8b9d DB |
427 | /* The number of the general-purpose register we saved the return |
428 | address ("link register") in, or -1 if we haven't moved it yet. */ | |
429 | int lr_save_reg = -1; | |
430 | ||
1cb761c7 KB |
431 | /* Offset (from sp) at which lr has been saved on the stack. */ |
432 | ||
433 | int lr_sp_offset = 0; | |
456f8b9d DB |
434 | |
435 | /* If gr_saved[i] is non-zero, then we've noticed that general | |
436 | register i has been saved at gr_sp_offset[i] from the stack | |
437 | pointer. */ | |
438 | char gr_saved[64]; | |
439 | int gr_sp_offset[64]; | |
440 | ||
441 | memset (gr_saved, 0, sizeof (gr_saved)); | |
442 | ||
1cb761c7 | 443 | while (! next_frame || pc < frame_pc_unwind (next_frame)) |
456f8b9d DB |
444 | { |
445 | LONGEST op = read_memory_integer (pc, 4); | |
446 | ||
447 | /* The tests in this chain of ifs should be in order of | |
448 | decreasing selectivity, so that more particular patterns get | |
449 | to fire before less particular patterns. */ | |
450 | ||
451 | /* Setting the FP from the SP: | |
452 | ori sp, 0, fp | |
453 | P 000010 0100010 000001 000000000000 = 0x04881000 | |
454 | 0 111111 1111111 111111 111111111111 = 0x7fffffff | |
455 | . . . . . . . . | |
456 | We treat this as part of the prologue. */ | |
457 | if ((op & 0x7fffffff) == 0x04881000) | |
458 | { | |
459 | fp_set = 1; | |
460 | fp_offset = 0; | |
461 | } | |
462 | ||
463 | /* Move the link register to the scratch register grJ, before saving: | |
464 | movsg lr, grJ | |
465 | P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0 | |
466 | 0 111111 1111111 111111 111111 000000 = 0x7fffffc0 | |
467 | . . . . . . . . | |
468 | We treat this as part of the prologue. */ | |
469 | else if ((op & 0x7fffffc0) == 0x080d01c0) | |
470 | { | |
471 | int gr_j = op & 0x3f; | |
472 | ||
473 | /* If we're moving it to a scratch register, that's fine. */ | |
474 | if (is_caller_saves_reg (gr_j)) | |
475 | lr_save_reg = gr_j; | |
476 | /* Otherwise it's not a prologue instruction that we | |
477 | recognize. */ | |
478 | else | |
479 | break; | |
480 | } | |
481 | ||
482 | /* To save multiple callee-saves registers on the stack, at | |
483 | offset zero: | |
484 | ||
485 | std grK,@(sp,gr0) | |
486 | P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0 | |
487 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
488 | ||
489 | stq grK,@(sp,gr0) | |
490 | P KKKKKK 0000011 000001 000100 000000 = 0x000c1100 | |
491 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
492 | . . . . . . . . | |
493 | We treat this as part of the prologue, and record the register's | |
494 | saved address in the frame structure. */ | |
495 | else if ((op & 0x01ffffff) == 0x000c10c0 | |
496 | || (op & 0x01ffffff) == 0x000c1100) | |
497 | { | |
498 | int gr_k = ((op >> 25) & 0x3f); | |
499 | int ope = ((op >> 6) & 0x3f); | |
500 | int count; | |
501 | int i; | |
502 | ||
503 | /* Is it an std or an stq? */ | |
504 | if (ope == 0x03) | |
505 | count = 2; | |
506 | else | |
507 | count = 4; | |
508 | ||
509 | /* Is it really a callee-saves register? */ | |
510 | if (is_callee_saves_reg (gr_k)) | |
511 | { | |
512 | for (i = 0; i < count; i++) | |
513 | { | |
514 | gr_saved[gr_k + i] = 1; | |
515 | gr_sp_offset[gr_k + i] = 4 * i; | |
516 | } | |
517 | } | |
518 | else | |
519 | /* It's not a prologue instruction. */ | |
520 | break; | |
521 | } | |
522 | ||
523 | /* Adjusting the stack pointer. (The stack pointer is GR1.) | |
524 | addi sp, S, sp | |
525 | P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000 | |
526 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
527 | . . . . . . . . | |
528 | We treat this as part of the prologue. */ | |
529 | else if ((op & 0x7ffff000) == 0x02401000) | |
530 | { | |
531 | /* Sign-extend the twelve-bit field. | |
532 | (Isn't there a better way to do this?) */ | |
533 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
534 | ||
535 | framesize -= s; | |
536 | } | |
537 | ||
538 | /* Setting the FP to a constant distance from the SP: | |
539 | addi sp, S, fp | |
540 | P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000 | |
541 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
542 | . . . . . . . . | |
543 | We treat this as part of the prologue. */ | |
544 | else if ((op & 0x7ffff000) == 0x04401000) | |
545 | { | |
546 | /* Sign-extend the twelve-bit field. | |
547 | (Isn't there a better way to do this?) */ | |
548 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
549 | fp_set = 1; | |
550 | fp_offset = s; | |
551 | } | |
552 | ||
553 | /* To spill an argument register to a scratch register: | |
554 | ori GRi, 0, GRk | |
555 | P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000 | |
556 | 0 000000 1111111 000000 111111111111 = 0x01fc0fff | |
557 | . . . . . . . . | |
558 | For the time being, we treat this as a prologue instruction, | |
559 | assuming that GRi is an argument register. This one's kind | |
560 | of suspicious, because it seems like it could be part of a | |
561 | legitimate body instruction. But we only come here when the | |
562 | source info wasn't helpful, so we have to do the best we can. | |
563 | Hopefully once GCC and GDB agree on how to emit line number | |
564 | info for prologues, then this code will never come into play. */ | |
565 | else if ((op & 0x01fc0fff) == 0x00880000) | |
566 | { | |
567 | int gr_i = ((op >> 12) & 0x3f); | |
568 | ||
569 | /* If the source isn't an arg register, then this isn't a | |
570 | prologue instruction. */ | |
571 | if (! is_argument_reg (gr_i)) | |
572 | break; | |
573 | } | |
574 | ||
575 | /* To spill 16-bit values to the stack: | |
576 | sthi GRk, @(fp, s) | |
577 | P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000 | |
578 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
579 | . . . . . . . . | |
580 | And for 8-bit values, we use STB instructions. | |
581 | stbi GRk, @(fp, s) | |
582 | P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000 | |
583 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
584 | . . . . . . . . | |
585 | We check that GRk is really an argument register, and treat | |
586 | all such as part of the prologue. */ | |
587 | else if ( (op & 0x01fff000) == 0x01442000 | |
588 | || (op & 0x01fff000) == 0x01402000) | |
589 | { | |
590 | int gr_k = ((op >> 25) & 0x3f); | |
591 | ||
592 | if (! is_argument_reg (gr_k)) | |
593 | break; /* Source isn't an arg register. */ | |
594 | } | |
595 | ||
596 | /* To save multiple callee-saves register on the stack, at a | |
597 | non-zero offset: | |
598 | ||
599 | stdi GRk, @(sp, s) | |
600 | P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000 | |
601 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
602 | . . . . . . . . | |
603 | stqi GRk, @(sp, s) | |
604 | P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000 | |
605 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
606 | . . . . . . . . | |
607 | We treat this as part of the prologue, and record the register's | |
608 | saved address in the frame structure. */ | |
609 | else if ((op & 0x01fff000) == 0x014c1000 | |
610 | || (op & 0x01fff000) == 0x01501000) | |
611 | { | |
612 | int gr_k = ((op >> 25) & 0x3f); | |
613 | int count; | |
614 | int i; | |
615 | ||
616 | /* Is it a stdi or a stqi? */ | |
617 | if ((op & 0x01fff000) == 0x014c1000) | |
618 | count = 2; | |
619 | else | |
620 | count = 4; | |
621 | ||
622 | /* Is it really a callee-saves register? */ | |
623 | if (is_callee_saves_reg (gr_k)) | |
624 | { | |
625 | /* Sign-extend the twelve-bit field. | |
626 | (Isn't there a better way to do this?) */ | |
627 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
628 | ||
629 | for (i = 0; i < count; i++) | |
630 | { | |
631 | gr_saved[gr_k + i] = 1; | |
632 | gr_sp_offset[gr_k + i] = s + (4 * i); | |
633 | } | |
634 | } | |
635 | else | |
636 | /* It's not a prologue instruction. */ | |
637 | break; | |
638 | } | |
639 | ||
640 | /* Storing any kind of integer register at any constant offset | |
641 | from any other register. | |
642 | ||
643 | st GRk, @(GRi, gr0) | |
644 | P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080 | |
645 | 0 000000 1111111 000000 111111 111111 = 0x01fc0fff | |
646 | . . . . . . . . | |
647 | sti GRk, @(GRi, d12) | |
648 | P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000 | |
649 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 | |
650 | . . . . . . . . | |
651 | These could be almost anything, but a lot of prologue | |
652 | instructions fall into this pattern, so let's decode the | |
653 | instruction once, and then work at a higher level. */ | |
654 | else if (((op & 0x01fc0fff) == 0x000c0080) | |
655 | || ((op & 0x01fc0000) == 0x01480000)) | |
656 | { | |
657 | int gr_k = ((op >> 25) & 0x3f); | |
658 | int gr_i = ((op >> 12) & 0x3f); | |
659 | int offset; | |
660 | ||
661 | /* Are we storing with gr0 as an offset, or using an | |
662 | immediate value? */ | |
663 | if ((op & 0x01fc0fff) == 0x000c0080) | |
664 | offset = 0; | |
665 | else | |
666 | offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
667 | ||
668 | /* If the address isn't relative to the SP or FP, it's not a | |
669 | prologue instruction. */ | |
670 | if (gr_i != sp_regnum && gr_i != fp_regnum) | |
671 | break; | |
672 | ||
673 | /* Saving the old FP in the new frame (relative to the SP). */ | |
674 | if (gr_k == fp_regnum && gr_i == sp_regnum) | |
1cb761c7 KB |
675 | { |
676 | gr_saved[fp_regnum] = 1; | |
677 | gr_sp_offset[fp_regnum] = offset; | |
678 | } | |
456f8b9d DB |
679 | |
680 | /* Saving callee-saves register(s) on the stack, relative to | |
681 | the SP. */ | |
682 | else if (gr_i == sp_regnum | |
683 | && is_callee_saves_reg (gr_k)) | |
684 | { | |
685 | gr_saved[gr_k] = 1; | |
1cb761c7 KB |
686 | if (gr_i == sp_regnum) |
687 | gr_sp_offset[gr_k] = offset; | |
688 | else | |
689 | gr_sp_offset[gr_k] = offset + fp_offset; | |
456f8b9d DB |
690 | } |
691 | ||
692 | /* Saving the scratch register holding the return address. */ | |
693 | else if (lr_save_reg != -1 | |
694 | && gr_k == lr_save_reg) | |
1cb761c7 KB |
695 | { |
696 | lr_saved_on_stack = 1; | |
697 | if (gr_i == sp_regnum) | |
698 | lr_sp_offset = offset; | |
699 | else | |
700 | lr_sp_offset = offset + fp_offset; | |
701 | } | |
456f8b9d DB |
702 | |
703 | /* Spilling int-sized arguments to the stack. */ | |
704 | else if (is_argument_reg (gr_k)) | |
705 | ; | |
706 | ||
707 | /* It's not a store instruction we recognize, so this must | |
708 | be the end of the prologue. */ | |
709 | else | |
710 | break; | |
711 | } | |
712 | ||
713 | /* It's not any instruction we recognize, so this must be the end | |
714 | of the prologue. */ | |
715 | else | |
716 | break; | |
717 | ||
718 | pc += 4; | |
719 | } | |
720 | ||
1cb761c7 | 721 | if (next_frame && info) |
456f8b9d | 722 | { |
1cb761c7 KB |
723 | int i; |
724 | ULONGEST this_base; | |
456f8b9d DB |
725 | |
726 | /* If we know the relationship between the stack and frame | |
727 | pointers, record the addresses of the registers we noticed. | |
728 | Note that we have to do this as a separate step at the end, | |
729 | because instructions may save relative to the SP, but we need | |
730 | their addresses relative to the FP. */ | |
731 | if (fp_set) | |
1cb761c7 KB |
732 | frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base); |
733 | else | |
734 | frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base); | |
456f8b9d | 735 | |
1cb761c7 KB |
736 | for (i = 0; i < 64; i++) |
737 | if (gr_saved[i]) | |
738 | info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i]; | |
456f8b9d | 739 | |
1cb761c7 KB |
740 | info->prev_sp = this_base - fp_offset + framesize; |
741 | info->base = this_base; | |
742 | ||
743 | /* If LR was saved on the stack, record its location. */ | |
744 | if (lr_saved_on_stack) | |
745 | info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset; | |
746 | ||
747 | /* The call instruction moves the caller's PC in the callee's LR. | |
748 | Since this is an unwind, do the reverse. Copy the location of LR | |
749 | into PC (the address / regnum) so that a request for PC will be | |
750 | converted into a request for the LR. */ | |
751 | info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum]; | |
752 | ||
753 | /* Save the previous frame's computed SP value. */ | |
754 | trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp); | |
456f8b9d DB |
755 | } |
756 | ||
757 | return pc; | |
758 | } | |
759 | ||
760 | ||
761 | static CORE_ADDR | |
762 | frv_skip_prologue (CORE_ADDR pc) | |
763 | { | |
764 | CORE_ADDR func_addr, func_end, new_pc; | |
765 | ||
766 | new_pc = pc; | |
767 | ||
768 | /* If the line table has entry for a line *within* the function | |
769 | (i.e., not in the prologue, and not past the end), then that's | |
770 | our location. */ | |
771 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
772 | { | |
773 | struct symtab_and_line sal; | |
774 | ||
775 | sal = find_pc_line (func_addr, 0); | |
776 | ||
777 | if (sal.line != 0 && sal.end < func_end) | |
778 | { | |
779 | new_pc = sal.end; | |
780 | } | |
781 | } | |
782 | ||
783 | /* The FR-V prologue is at least five instructions long (twenty bytes). | |
784 | If we didn't find a real source location past that, then | |
785 | do a full analysis of the prologue. */ | |
786 | if (new_pc < pc + 20) | |
1cb761c7 | 787 | new_pc = frv_analyze_prologue (pc, 0, 0); |
456f8b9d DB |
788 | |
789 | return new_pc; | |
790 | } | |
791 | ||
1cb761c7 KB |
792 | |
793 | static struct frv_unwind_cache * | |
794 | frv_frame_unwind_cache (struct frame_info *next_frame, | |
795 | void **this_prologue_cache) | |
456f8b9d | 796 | { |
1cb761c7 KB |
797 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
798 | CORE_ADDR pc; | |
799 | ULONGEST prev_sp; | |
800 | ULONGEST this_base; | |
801 | struct frv_unwind_cache *info; | |
8baa6f92 | 802 | |
1cb761c7 KB |
803 | if ((*this_prologue_cache)) |
804 | return (*this_prologue_cache); | |
456f8b9d | 805 | |
1cb761c7 KB |
806 | info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); |
807 | (*this_prologue_cache) = info; | |
808 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
456f8b9d | 809 | |
1cb761c7 KB |
810 | /* Prologue analysis does the rest... */ |
811 | frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info); | |
456f8b9d | 812 | |
1cb761c7 | 813 | return info; |
456f8b9d DB |
814 | } |
815 | ||
456f8b9d | 816 | static void |
cd31fb03 KB |
817 | frv_extract_return_value (struct type *type, struct regcache *regcache, |
818 | void *valbuf) | |
456f8b9d | 819 | { |
cd31fb03 KB |
820 | int len = TYPE_LENGTH (type); |
821 | ||
822 | if (len <= 4) | |
823 | { | |
824 | ULONGEST gpr8_val; | |
825 | regcache_cooked_read_unsigned (regcache, 8, &gpr8_val); | |
826 | store_unsigned_integer (valbuf, len, gpr8_val); | |
827 | } | |
828 | else if (len == 8) | |
829 | { | |
830 | ULONGEST regval; | |
831 | regcache_cooked_read_unsigned (regcache, 8, ®val); | |
832 | store_unsigned_integer (valbuf, 4, regval); | |
833 | regcache_cooked_read_unsigned (regcache, 9, ®val); | |
834 | store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval); | |
835 | } | |
836 | else | |
837 | internal_error (__FILE__, __LINE__, "Illegal return value length: %d", len); | |
456f8b9d DB |
838 | } |
839 | ||
840 | static CORE_ADDR | |
cd31fb03 | 841 | frv_extract_struct_value_address (struct regcache *regcache) |
456f8b9d | 842 | { |
cd31fb03 KB |
843 | ULONGEST addr; |
844 | regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr); | |
845 | return addr; | |
456f8b9d DB |
846 | } |
847 | ||
848 | static void | |
849 | frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
850 | { | |
851 | write_register (struct_return_regnum, addr); | |
852 | } | |
853 | ||
854 | static int | |
855 | frv_frameless_function_invocation (struct frame_info *frame) | |
856 | { | |
857 | return frameless_look_for_prologue (frame); | |
858 | } | |
859 | ||
1cb761c7 KB |
860 | static CORE_ADDR |
861 | frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
456f8b9d | 862 | { |
1cb761c7 | 863 | /* Require dword alignment. */ |
5b03f266 | 864 | return align_down (sp, 8); |
456f8b9d DB |
865 | } |
866 | ||
456f8b9d | 867 | static CORE_ADDR |
1cb761c7 KB |
868 | frv_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
869 | struct regcache *regcache, CORE_ADDR bp_addr, | |
870 | int nargs, struct value **args, CORE_ADDR sp, | |
871 | int struct_return, CORE_ADDR struct_addr) | |
456f8b9d DB |
872 | { |
873 | int argreg; | |
874 | int argnum; | |
875 | char *val; | |
876 | char valbuf[4]; | |
877 | struct value *arg; | |
878 | struct type *arg_type; | |
879 | int len; | |
880 | enum type_code typecode; | |
881 | CORE_ADDR regval; | |
882 | int stack_space; | |
883 | int stack_offset; | |
884 | ||
885 | #if 0 | |
886 | printf("Push %d args at sp = %x, struct_return=%d (%x)\n", | |
887 | nargs, (int) sp, struct_return, struct_addr); | |
888 | #endif | |
889 | ||
890 | stack_space = 0; | |
891 | for (argnum = 0; argnum < nargs; ++argnum) | |
5b03f266 | 892 | stack_space += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4); |
456f8b9d DB |
893 | |
894 | stack_space -= (6 * 4); | |
895 | if (stack_space > 0) | |
896 | sp -= stack_space; | |
897 | ||
898 | /* Make sure stack is dword aligned. */ | |
5b03f266 | 899 | sp = align_down (sp, 8); |
456f8b9d DB |
900 | |
901 | stack_offset = 0; | |
902 | ||
903 | argreg = 8; | |
904 | ||
905 | if (struct_return) | |
1cb761c7 KB |
906 | regcache_cooked_write_unsigned (regcache, struct_return_regnum, |
907 | struct_addr); | |
456f8b9d DB |
908 | |
909 | for (argnum = 0; argnum < nargs; ++argnum) | |
910 | { | |
911 | arg = args[argnum]; | |
912 | arg_type = check_typedef (VALUE_TYPE (arg)); | |
913 | len = TYPE_LENGTH (arg_type); | |
914 | typecode = TYPE_CODE (arg_type); | |
915 | ||
916 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
917 | { | |
fbd9dcd3 | 918 | store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg)); |
456f8b9d DB |
919 | typecode = TYPE_CODE_PTR; |
920 | len = 4; | |
921 | val = valbuf; | |
922 | } | |
923 | else | |
924 | { | |
925 | val = (char *) VALUE_CONTENTS (arg); | |
926 | } | |
927 | ||
928 | while (len > 0) | |
929 | { | |
930 | int partial_len = (len < 4 ? len : 4); | |
931 | ||
932 | if (argreg < 14) | |
933 | { | |
7c0b4a20 | 934 | regval = extract_unsigned_integer (val, partial_len); |
456f8b9d DB |
935 | #if 0 |
936 | printf(" Argnum %d data %x -> reg %d\n", | |
937 | argnum, (int) regval, argreg); | |
938 | #endif | |
1cb761c7 | 939 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
456f8b9d DB |
940 | ++argreg; |
941 | } | |
942 | else | |
943 | { | |
944 | #if 0 | |
945 | printf(" Argnum %d data %x -> offset %d (%x)\n", | |
946 | argnum, *((int *)val), stack_offset, (int) (sp + stack_offset)); | |
947 | #endif | |
948 | write_memory (sp + stack_offset, val, partial_len); | |
5b03f266 | 949 | stack_offset += align_up (partial_len, 4); |
456f8b9d DB |
950 | } |
951 | len -= partial_len; | |
952 | val += partial_len; | |
953 | } | |
954 | } | |
456f8b9d | 955 | |
1cb761c7 KB |
956 | /* Set the return address. For the frv, the return breakpoint is |
957 | always at BP_ADDR. */ | |
958 | regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr); | |
959 | ||
960 | /* Finally, update the SP register. */ | |
961 | regcache_cooked_write_unsigned (regcache, sp_regnum, sp); | |
962 | ||
456f8b9d DB |
963 | return sp; |
964 | } | |
965 | ||
966 | static void | |
cd31fb03 KB |
967 | frv_store_return_value (struct type *type, struct regcache *regcache, |
968 | const void *valbuf) | |
456f8b9d | 969 | { |
cd31fb03 KB |
970 | int len = TYPE_LENGTH (type); |
971 | ||
972 | if (len <= 4) | |
973 | { | |
974 | bfd_byte val[4]; | |
975 | memset (val, 0, sizeof (val)); | |
976 | memcpy (val + (4 - len), valbuf, len); | |
977 | regcache_cooked_write (regcache, 8, val); | |
978 | } | |
979 | else if (len == 8) | |
980 | { | |
981 | regcache_cooked_write (regcache, 8, valbuf); | |
982 | regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4); | |
983 | } | |
456f8b9d DB |
984 | else |
985 | internal_error (__FILE__, __LINE__, | |
cd31fb03 | 986 | "Don't know how to return a %d-byte value.", len); |
456f8b9d DB |
987 | } |
988 | ||
456f8b9d | 989 | |
456f8b9d DB |
990 | /* Hardware watchpoint / breakpoint support for the FR500 |
991 | and FR400. */ | |
992 | ||
993 | int | |
994 | frv_check_watch_resources (int type, int cnt, int ot) | |
995 | { | |
996 | struct gdbarch_tdep *var = CURRENT_VARIANT; | |
997 | ||
998 | /* Watchpoints not supported on simulator. */ | |
999 | if (strcmp (target_shortname, "sim") == 0) | |
1000 | return 0; | |
1001 | ||
1002 | if (type == bp_hardware_breakpoint) | |
1003 | { | |
1004 | if (var->num_hw_breakpoints == 0) | |
1005 | return 0; | |
1006 | else if (cnt <= var->num_hw_breakpoints) | |
1007 | return 1; | |
1008 | } | |
1009 | else | |
1010 | { | |
1011 | if (var->num_hw_watchpoints == 0) | |
1012 | return 0; | |
1013 | else if (ot) | |
1014 | return -1; | |
1015 | else if (cnt <= var->num_hw_watchpoints) | |
1016 | return 1; | |
1017 | } | |
1018 | return -1; | |
1019 | } | |
1020 | ||
1021 | ||
1022 | CORE_ADDR | |
5ae5f592 | 1023 | frv_stopped_data_address (void) |
456f8b9d DB |
1024 | { |
1025 | CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3; | |
1026 | ||
1027 | brr = read_register (brr_regnum); | |
1028 | dbar0 = read_register (dbar0_regnum); | |
1029 | dbar1 = read_register (dbar1_regnum); | |
1030 | dbar2 = read_register (dbar2_regnum); | |
1031 | dbar3 = read_register (dbar3_regnum); | |
1032 | ||
1033 | if (brr & (1<<11)) | |
1034 | return dbar0; | |
1035 | else if (brr & (1<<10)) | |
1036 | return dbar1; | |
1037 | else if (brr & (1<<9)) | |
1038 | return dbar2; | |
1039 | else if (brr & (1<<8)) | |
1040 | return dbar3; | |
1041 | else | |
1042 | return 0; | |
1043 | } | |
1044 | ||
1cb761c7 KB |
1045 | static CORE_ADDR |
1046 | frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1047 | { | |
1048 | return frame_unwind_register_unsigned (next_frame, pc_regnum); | |
1049 | } | |
1050 | ||
1051 | /* Given a GDB frame, determine the address of the calling function's | |
1052 | frame. This will be used to create a new GDB frame struct. */ | |
1053 | ||
1054 | static void | |
1055 | frv_frame_this_id (struct frame_info *next_frame, | |
1056 | void **this_prologue_cache, struct frame_id *this_id) | |
1057 | { | |
1058 | struct frv_unwind_cache *info | |
1059 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1060 | CORE_ADDR base; | |
1061 | CORE_ADDR func; | |
1062 | struct minimal_symbol *msym_stack; | |
1063 | struct frame_id id; | |
1064 | ||
1065 | /* The FUNC is easy. */ | |
1066 | func = frame_func_unwind (next_frame); | |
1067 | ||
1068 | /* This is meant to halt the backtrace at "_start". Make sure we | |
1069 | don't halt it at a generic dummy frame. */ | |
0f4d7c52 | 1070 | if (inside_entry_func (func)) |
1cb761c7 KB |
1071 | return; |
1072 | ||
1073 | /* Check if the stack is empty. */ | |
1074 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
1075 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
1076 | return; | |
1077 | ||
1078 | /* Hopefully the prologue analysis either correctly determined the | |
1079 | frame's base (which is the SP from the previous frame), or set | |
1080 | that base to "NULL". */ | |
1081 | base = info->prev_sp; | |
1082 | if (base == 0) | |
1083 | return; | |
1084 | ||
1085 | id = frame_id_build (base, func); | |
1086 | ||
1087 | /* Check that we're not going round in circles with the same frame | |
1088 | ID (but avoid applying the test to sentinel frames which do go | |
1089 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
1090 | compare the frame's PC value. */ | |
1091 | if (frame_relative_level (next_frame) >= 0 | |
1092 | && get_frame_type (next_frame) != DUMMY_FRAME | |
1093 | && frame_id_eq (get_frame_id (next_frame), id)) | |
1094 | return; | |
1095 | ||
1096 | (*this_id) = id; | |
1097 | } | |
1098 | ||
1099 | static void | |
1100 | frv_frame_prev_register (struct frame_info *next_frame, | |
1101 | void **this_prologue_cache, | |
1102 | int regnum, int *optimizedp, | |
1103 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1104 | int *realnump, void *bufferp) | |
1105 | { | |
1106 | struct frv_unwind_cache *info | |
1107 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1108 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
1109 | optimizedp, lvalp, addrp, realnump, bufferp); | |
1110 | } | |
1111 | ||
1112 | static const struct frame_unwind frv_frame_unwind = { | |
1113 | NORMAL_FRAME, | |
1114 | frv_frame_this_id, | |
1115 | frv_frame_prev_register | |
1116 | }; | |
1117 | ||
1118 | static const struct frame_unwind * | |
1119 | frv_frame_sniffer (struct frame_info *next_frame) | |
1120 | { | |
1121 | return &frv_frame_unwind; | |
1122 | } | |
1123 | ||
1124 | static CORE_ADDR | |
1125 | frv_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1126 | { | |
1127 | struct frv_unwind_cache *info | |
1128 | = frv_frame_unwind_cache (next_frame, this_cache); | |
1129 | return info->base; | |
1130 | } | |
1131 | ||
1132 | static const struct frame_base frv_frame_base = { | |
1133 | &frv_frame_unwind, | |
1134 | frv_frame_base_address, | |
1135 | frv_frame_base_address, | |
1136 | frv_frame_base_address | |
1137 | }; | |
1138 | ||
1139 | static CORE_ADDR | |
1140 | frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1141 | { | |
1142 | return frame_unwind_register_unsigned (next_frame, sp_regnum); | |
1143 | } | |
1144 | ||
1145 | ||
1146 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
1147 | dummy frame. The frame ID's base needs to match the TOS value | |
1148 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1149 | breakpoint. */ | |
1150 | ||
1151 | static struct frame_id | |
1152 | frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1153 | { | |
1154 | return frame_id_build (frv_unwind_sp (gdbarch, next_frame), | |
1155 | frame_pc_unwind (next_frame)); | |
1156 | } | |
1157 | ||
1158 | ||
456f8b9d DB |
1159 | static struct gdbarch * |
1160 | frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1161 | { | |
1162 | struct gdbarch *gdbarch; | |
1163 | struct gdbarch_tdep *var; | |
1164 | ||
1165 | /* Check to see if we've already built an appropriate architecture | |
1166 | object for this executable. */ | |
1167 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1168 | if (arches) | |
1169 | return arches->gdbarch; | |
1170 | ||
1171 | /* Select the right tdep structure for this variant. */ | |
1172 | var = new_variant (); | |
1173 | switch (info.bfd_arch_info->mach) | |
1174 | { | |
1175 | case bfd_mach_frv: | |
1176 | case bfd_mach_frvsimple: | |
1177 | case bfd_mach_fr500: | |
1178 | case bfd_mach_frvtomcat: | |
1179 | set_variant_num_gprs (var, 64); | |
1180 | set_variant_num_fprs (var, 64); | |
1181 | break; | |
1182 | ||
1183 | case bfd_mach_fr400: | |
1184 | set_variant_num_gprs (var, 32); | |
1185 | set_variant_num_fprs (var, 32); | |
1186 | break; | |
1187 | ||
1188 | default: | |
1189 | /* Never heard of this variant. */ | |
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | gdbarch = gdbarch_alloc (&info, var); | |
1194 | ||
1195 | set_gdbarch_short_bit (gdbarch, 16); | |
1196 | set_gdbarch_int_bit (gdbarch, 32); | |
1197 | set_gdbarch_long_bit (gdbarch, 32); | |
1198 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1199 | set_gdbarch_float_bit (gdbarch, 32); | |
1200 | set_gdbarch_double_bit (gdbarch, 64); | |
1201 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1202 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1203 | ||
1204 | set_gdbarch_num_regs (gdbarch, frv_num_regs); | |
1205 | set_gdbarch_sp_regnum (gdbarch, sp_regnum); | |
0ba6dca9 | 1206 | set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum); |
456f8b9d DB |
1207 | set_gdbarch_pc_regnum (gdbarch, pc_regnum); |
1208 | ||
1209 | set_gdbarch_register_name (gdbarch, frv_register_name); | |
7f398216 | 1210 | set_gdbarch_register_type (gdbarch, frv_register_type); |
526eef89 | 1211 | set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno); |
456f8b9d DB |
1212 | |
1213 | set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue); | |
1214 | set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc); | |
46a16dba | 1215 | set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address); |
456f8b9d | 1216 | |
456f8b9d DB |
1217 | set_gdbarch_frame_args_skip (gdbarch, 0); |
1218 | set_gdbarch_frameless_function_invocation (gdbarch, frv_frameless_function_invocation); | |
1219 | ||
1fd35568 | 1220 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
cd31fb03 | 1221 | set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value); |
456f8b9d | 1222 | |
4183d812 | 1223 | set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return); |
cd31fb03 KB |
1224 | set_gdbarch_store_return_value (gdbarch, frv_store_return_value); |
1225 | set_gdbarch_extract_struct_value_address (gdbarch, frv_extract_struct_value_address); | |
456f8b9d | 1226 | |
1cb761c7 KB |
1227 | /* Frame stuff. */ |
1228 | set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc); | |
1229 | set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp); | |
1230 | set_gdbarch_frame_align (gdbarch, frv_frame_align); | |
1231 | frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer); | |
1232 | frame_base_set_default (gdbarch, &frv_frame_base); | |
456f8b9d | 1233 | |
1cb761c7 KB |
1234 | /* Settings for calling functions in the inferior. */ |
1235 | set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call); | |
1236 | set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id); | |
456f8b9d DB |
1237 | |
1238 | /* Settings that should be unnecessary. */ | |
1239 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1240 | ||
456f8b9d | 1241 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
456f8b9d | 1242 | |
456f8b9d DB |
1243 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
1244 | set_gdbarch_function_start_offset (gdbarch, 0); | |
456f8b9d DB |
1245 | |
1246 | set_gdbarch_remote_translate_xfer_address | |
aed7f26a | 1247 | (gdbarch, generic_remote_translate_xfer_address); |
456f8b9d DB |
1248 | |
1249 | /* Hardware watchpoint / breakpoint support. */ | |
1250 | switch (info.bfd_arch_info->mach) | |
1251 | { | |
1252 | case bfd_mach_frv: | |
1253 | case bfd_mach_frvsimple: | |
1254 | case bfd_mach_fr500: | |
1255 | case bfd_mach_frvtomcat: | |
1256 | /* fr500-style hardware debugging support. */ | |
1257 | var->num_hw_watchpoints = 4; | |
1258 | var->num_hw_breakpoints = 4; | |
1259 | break; | |
1260 | ||
1261 | case bfd_mach_fr400: | |
1262 | /* fr400-style hardware debugging support. */ | |
1263 | var->num_hw_watchpoints = 2; | |
1264 | var->num_hw_breakpoints = 4; | |
1265 | break; | |
1266 | ||
1267 | default: | |
1268 | /* Otherwise, assume we don't have hardware debugging support. */ | |
1269 | var->num_hw_watchpoints = 0; | |
1270 | var->num_hw_breakpoints = 0; | |
1271 | break; | |
1272 | } | |
1273 | ||
36482093 AC |
1274 | set_gdbarch_print_insn (gdbarch, print_insn_frv); |
1275 | ||
456f8b9d DB |
1276 | return gdbarch; |
1277 | } | |
1278 | ||
1279 | void | |
1280 | _initialize_frv_tdep (void) | |
1281 | { | |
1282 | register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init); | |
456f8b9d | 1283 | } |