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1/* Target-dependent code for the Matsushita MN10300 for GDB, the GNU debugger.
2
1d506c26 3 Copyright (C) 1996-2024 Free Software Foundation, Inc.
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4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
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10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
342ee437 19
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20#include "arch-utils.h"
21#include "dis-asm.h"
ec452525 22#include "extract-store-integer.h"
342ee437
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23#include "gdbtypes.h"
24#include "regcache.h"
ef0f16cc 25#include "gdbcore.h"
342ee437 26#include "value.h"
342ee437
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27#include "frame.h"
28#include "frame-unwind.h"
29#include "frame-base.h"
342ee437 30#include "symtab.h"
82ca8957 31#include "dwarf2/frame.h"
697e3bc9 32#include "osabi.h"
ee3a2f01 33#include "infcall.h"
6c02c64c 34#include "prologue-value.h"
effa26a9 35#include "target.h"
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36
37#include "mn10300-tdep.h"
38
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39
40/* The am33-2 has 64 registers. */
41#define MN10300_MAX_NUM_REGS 64
42
b8b6e72f
AH
43/* Big enough to hold the size of the largest register in bytes. */
44#define MN10300_MAX_REGISTER_SIZE 64
45
6c02c64c
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46/* This structure holds the results of a prologue analysis. */
47struct mn10300_prologue
48{
d80b854b
UW
49 /* The architecture for which we generated this prologue info. */
50 struct gdbarch *gdbarch;
51
6c02c64c
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52 /* The offset from the frame base to the stack pointer --- always
53 zero or negative.
54
55 Calling this a "size" is a bit misleading, but given that the
56 stack grows downwards, using offsets for everything keeps one
57 from going completely sign-crazy: you never change anything's
58 sign for an ADD instruction; always change the second operand's
59 sign for a SUB instruction; and everything takes care of
60 itself. */
61 int frame_size;
62
63 /* Non-zero if this function has initialized the frame pointer from
64 the stack pointer, zero otherwise. */
65 int has_frame_ptr;
66
67 /* If has_frame_ptr is non-zero, this is the offset from the frame
68 base to where the frame pointer points. This is always zero or
69 negative. */
70 int frame_ptr_offset;
71
72 /* The address of the first instruction at which the frame has been
73 set up and the arguments are where the debug info says they are
74 --- as best as we can tell. */
75 CORE_ADDR prologue_end;
76
77 /* reg_offset[R] is the offset from the CFA at which register R is
78 saved, or 1 if register R has not been saved. (Real values are
79 always zero or negative.) */
80 int reg_offset[MN10300_MAX_NUM_REGS];
81};
82
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83
84/* Compute the alignment required by a type. */
85
86static int
87mn10300_type_align (struct type *type)
88{
89 int i, align = 1;
90
78134374 91 switch (type->code ())
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92 {
93 case TYPE_CODE_INT:
94 case TYPE_CODE_ENUM:
95 case TYPE_CODE_SET:
96 case TYPE_CODE_RANGE:
97 case TYPE_CODE_CHAR:
98 case TYPE_CODE_BOOL:
99 case TYPE_CODE_FLT:
100 case TYPE_CODE_PTR:
101 case TYPE_CODE_REF:
aa006118 102 case TYPE_CODE_RVALUE_REF:
df86565b 103 return type->length ();
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104
105 case TYPE_CODE_COMPLEX:
df86565b 106 return type->length () / 2;
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107
108 case TYPE_CODE_STRUCT:
109 case TYPE_CODE_UNION:
1f704f76 110 for (i = 0; i < type->num_fields (); i++)
342ee437 111 {
940da03e 112 int falign = mn10300_type_align (type->field (i).type ());
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113 while (align < falign)
114 align <<= 1;
115 }
116 return align;
117
118 case TYPE_CODE_ARRAY:
119 /* HACK! Structures containing arrays, even small ones, are not
85102364 120 eligible for returning in registers. */
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121 return 256;
122
123 case TYPE_CODE_TYPEDEF:
124 return mn10300_type_align (check_typedef (type));
125
126 default:
f34652de 127 internal_error (_("bad switch"));
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128 }
129}
130
342ee437 131/* Should call_function allocate stack space for a struct return? */
342ee437 132static int
99fe5f9d 133mn10300_use_struct_convention (struct type *type)
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134{
135 /* Structures bigger than a pair of words can't be returned in
136 registers. */
df86565b 137 if (type->length () > 8)
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138 return 1;
139
78134374 140 switch (type->code ())
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141 {
142 case TYPE_CODE_STRUCT:
143 case TYPE_CODE_UNION:
144 /* Structures with a single field are handled as the field
145 itself. */
1f704f76 146 if (type->num_fields () == 1)
940da03e 147 return mn10300_use_struct_convention (type->field (0).type ());
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148
149 /* Structures with word or double-word size are passed in memory, as
150 long as they require at least word alignment. */
151 if (mn10300_type_align (type) >= 4)
152 return 0;
153
154 return 1;
155
156 /* Arrays are addressable, so they're never returned in
157 registers. This condition can only hold when the array is
158 the only field of a struct or union. */
159 case TYPE_CODE_ARRAY:
160 return 1;
161
162 case TYPE_CODE_TYPEDEF:
99fe5f9d 163 return mn10300_use_struct_convention (check_typedef (type));
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164
165 default:
166 return 0;
167 }
168}
169
342ee437 170static void
99fe5f9d 171mn10300_store_return_value (struct gdbarch *gdbarch, struct type *type,
948f8e3d 172 struct regcache *regcache, const gdb_byte *valbuf)
342ee437 173{
df86565b 174 int len = type->length ();
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175 int reg, regsz;
176
78134374 177 if (type->code () == TYPE_CODE_PTR)
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178 reg = 4;
179 else
180 reg = 0;
181
182 regsz = register_size (gdbarch, reg);
183
184 if (len <= regsz)
4f0420fd 185 regcache->raw_write_part (reg, 0, len, valbuf);
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186 else if (len <= 2 * regsz)
187 {
10eaee5f 188 regcache->raw_write (reg, valbuf);
342ee437 189 gdb_assert (regsz == register_size (gdbarch, reg + 1));
4f0420fd 190 regcache->raw_write_part (reg + 1, 0, len - regsz, valbuf + regsz);
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MS
191 }
192 else
f34652de 193 internal_error (_("Cannot store return value %d bytes long."), len);
342ee437
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194}
195
342ee437 196static void
99fe5f9d 197mn10300_extract_return_value (struct gdbarch *gdbarch, struct type *type,
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198 struct regcache *regcache, void *valbuf)
199{
b8b6e72f 200 gdb_byte buf[MN10300_MAX_REGISTER_SIZE];
df86565b 201 int len = type->length ();
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202 int reg, regsz;
203
78134374 204 if (type->code () == TYPE_CODE_PTR)
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205 reg = 4;
206 else
207 reg = 0;
208
209 regsz = register_size (gdbarch, reg);
b8b6e72f 210 gdb_assert (regsz <= MN10300_MAX_REGISTER_SIZE);
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211 if (len <= regsz)
212 {
0b883586 213 regcache->raw_read (reg, buf);
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214 memcpy (valbuf, buf, len);
215 }
216 else if (len <= 2 * regsz)
217 {
0b883586 218 regcache->raw_read (reg, buf);
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219 memcpy (valbuf, buf, regsz);
220 gdb_assert (regsz == register_size (gdbarch, reg + 1));
0b883586 221 regcache->raw_read (reg + 1, buf);
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222 memcpy ((char *) valbuf + regsz, buf, len - regsz);
223 }
224 else
f34652de 225 internal_error (_("Cannot extract return value %d bytes long."), len);
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226}
227
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228/* Determine, for architecture GDBARCH, how a return value of TYPE
229 should be returned. If it is supposed to be returned in registers,
230 and READBUF is non-zero, read the appropriate value from REGCACHE,
231 and copy it into READBUF. If WRITEBUF is non-zero, write the value
232 from WRITEBUF into REGCACHE. */
233
234static enum return_value_convention
6a3a010b 235mn10300_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101
CV
236 struct type *type, struct regcache *regcache,
237 gdb_byte *readbuf, const gdb_byte *writebuf)
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238{
239 if (mn10300_use_struct_convention (type))
240 return RETURN_VALUE_STRUCT_CONVENTION;
241
242 if (readbuf)
243 mn10300_extract_return_value (gdbarch, type, regcache, readbuf);
244 if (writebuf)
245 mn10300_store_return_value (gdbarch, type, regcache, writebuf);
246
247 return RETURN_VALUE_REGISTER_CONVENTION;
248}
249
a121b7c1 250static const char *
9b9e61c7 251register_name (int reg, const char **regs, long num_regs)
342ee437 252{
9b9e61c7
AB
253 gdb_assert (reg < num_regs);
254 return regs[reg];
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255}
256
257static const char *
d93859e2 258mn10300_generic_register_name (struct gdbarch *gdbarch, int reg)
342ee437 259{
a121b7c1 260 static const char *regs[] =
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261 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
262 "sp", "pc", "mdr", "psw", "lir", "lar", "", "",
263 "", "", "", "", "", "", "", "",
264 "", "", "", "", "", "", "", "fp"
265 };
9b9e61c7 266 return register_name (reg, regs, ARRAY_SIZE (regs));
342ee437
MS
267}
268
269
270static const char *
d93859e2 271am33_register_name (struct gdbarch *gdbarch, int reg)
342ee437 272{
a121b7c1 273 static const char *regs[] =
342ee437
MS
274 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
275 "sp", "pc", "mdr", "psw", "lir", "lar", "",
276 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
277 "ssp", "msp", "usp", "mcrh", "mcrl", "mcvf", "", "", ""
278 };
9b9e61c7 279 return register_name (reg, regs, ARRAY_SIZE (regs));
342ee437
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280}
281
4640dd91 282static const char *
d93859e2 283am33_2_register_name (struct gdbarch *gdbarch, int reg)
4640dd91 284{
a121b7c1 285 static const char *regs[] =
4640dd91
KB
286 {
287 "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
288 "sp", "pc", "mdr", "psw", "lir", "lar", "mdrq", "r0",
289 "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ssp",
290 "msp", "usp", "mcrh", "mcrl", "mcvf", "fpcr", "", "",
291 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
292 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
293 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
294 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
295 };
9b9e61c7 296 return register_name (reg, regs, ARRAY_SIZE (regs));
4640dd91 297}
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298
299static struct type *
300mn10300_register_type (struct gdbarch *gdbarch, int reg)
301{
0dfff4cb 302 return builtin_type (gdbarch)->builtin_int;
342ee437
MS
303}
304
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305/* The breakpoint instruction must be the same size as the smallest
306 instruction in the instruction set.
307
308 The Matsushita mn10x00 processors have single byte instructions
309 so we need a single byte breakpoint. Matsushita hasn't defined
310 one, so we defined it ourselves. */
04180708 311constexpr gdb_byte mn10300_break_insn[] = {0xff};
342ee437 312
04180708 313typedef BP_MANIPULATION (mn10300_break_insn) mn10300_breakpoint;
342ee437 314
6c02c64c
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315/* Model the semantics of pushing a register onto the stack. This
316 is a helper function for mn10300_analyze_prologue, below. */
317static void
318push_reg (pv_t *regs, struct pv_area *stack, int regnum)
319{
320 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4);
f7b7ed97 321 stack->store (regs[E_SP_REGNUM], 4, regs[regnum]);
6c02c64c
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322}
323
324/* Translate an "r" register number extracted from an instruction encoding
325 into a GDB register number. Adapted from a simulator function
326 of the same name; see am33.igen. */
327static int
328translate_rreg (int rreg)
329{
330 /* The higher register numbers actually correspond to the
331 basic machine's address and data registers. */
332 if (rreg > 7 && rreg < 12)
333 return E_A0_REGNUM + rreg - 8;
334 else if (rreg > 11 && rreg < 16)
335 return E_D0_REGNUM + rreg - 12;
336 else
337 return E_E0_REGNUM + rreg;
338}
339
f7b7ed97 340/* Find saved registers in a 'struct pv_area'; we pass this to pv_area::scan.
9cacebf5 341
6c02c64c
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342 If VALUE is a saved register, ADDR says it was saved at a constant
343 offset from the frame base, and SIZE indicates that the whole
344 register was saved, record its offset in RESULT_UNTYPED. */
9cacebf5 345static void
6c02c64c 346check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value)
9cacebf5 347{
6c02c64c 348 struct mn10300_prologue *result = (struct mn10300_prologue *) result_untyped;
9cacebf5 349
6c02c64c
KB
350 if (value.kind == pvk_register
351 && value.k == 0
352 && pv_is_register (addr, E_SP_REGNUM)
d80b854b 353 && size == register_size (result->gdbarch, value.reg))
6c02c64c
KB
354 result->reg_offset[value.reg] = addr.k;
355}
9cacebf5 356
6c02c64c
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357/* Analyze the prologue to determine where registers are saved,
358 the end of the prologue, etc. The result of this analysis is
359 returned in RESULT. See struct mn10300_prologue above for more
360 information. */
361static void
362mn10300_analyze_prologue (struct gdbarch *gdbarch,
dda83cd7
SM
363 CORE_ADDR start_pc, CORE_ADDR limit_pc,
364 struct mn10300_prologue *result)
6c02c64c 365{
e17a4113 366 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
22e048c9 367 CORE_ADDR pc;
6c02c64c
KB
368 int rn;
369 pv_t regs[MN10300_MAX_NUM_REGS];
6c02c64c 370 CORE_ADDR after_last_frame_setup_insn = start_pc;
345bd07c 371 int am33_mode = get_am33_mode (gdbarch);
6c02c64c
KB
372
373 memset (result, 0, sizeof (*result));
d80b854b 374 result->gdbarch = gdbarch;
9cacebf5 375
6c02c64c 376 for (rn = 0; rn < MN10300_MAX_NUM_REGS; rn++)
4640dd91 377 {
6c02c64c
KB
378 regs[rn] = pv_register (rn, 0);
379 result->reg_offset[rn] = 1;
4640dd91 380 }
f7b7ed97 381 pv_area stack (E_SP_REGNUM, gdbarch_addr_bit (gdbarch));
6c02c64c 382
f7b7ed97
TT
383 /* The typical call instruction will have saved the return address on the
384 stack. Space for the return address has already been preallocated in
385 the caller's frame. It's possible, such as when using -mrelax with gcc
386 that other registers were saved as well. If this happens, we really
387 have no chance of deciphering the frame. DWARF info can save the day
388 when this happens. */
389 stack.store (regs[E_SP_REGNUM], 4, regs[E_PC_REGNUM]);
6c02c64c
KB
390
391 pc = start_pc;
392 while (pc < limit_pc)
4640dd91 393 {
6c02c64c
KB
394 int status;
395 gdb_byte instr[2];
4640dd91 396
6c02c64c 397 /* Instructions can be as small as one byte; however, we usually
dda83cd7 398 need at least two bytes to do the decoding, so fetch that many
6c02c64c
KB
399 to begin with. */
400 status = target_read_memory (pc, instr, 2);
401 if (status != 0)
402 break;
4640dd91 403
6c02c64c
KB
404 /* movm [regs], sp */
405 if (instr[0] == 0xcf)
4640dd91 406 {
6c02c64c
KB
407 gdb_byte save_mask;
408
409 save_mask = instr[1];
410
411 if ((save_mask & movm_exreg0_bit) && am33_mode)
412 {
f7b7ed97
TT
413 push_reg (regs, &stack, E_E2_REGNUM);
414 push_reg (regs, &stack, E_E3_REGNUM);
6c02c64c
KB
415 }
416 if ((save_mask & movm_exreg1_bit) && am33_mode)
4640dd91 417 {
f7b7ed97
TT
418 push_reg (regs, &stack, E_E4_REGNUM);
419 push_reg (regs, &stack, E_E5_REGNUM);
420 push_reg (regs, &stack, E_E6_REGNUM);
421 push_reg (regs, &stack, E_E7_REGNUM);
4640dd91 422 }
6c02c64c
KB
423 if ((save_mask & movm_exother_bit) && am33_mode)
424 {
f7b7ed97
TT
425 push_reg (regs, &stack, E_E0_REGNUM);
426 push_reg (regs, &stack, E_E1_REGNUM);
427 push_reg (regs, &stack, E_MDRQ_REGNUM);
428 push_reg (regs, &stack, E_MCRH_REGNUM);
429 push_reg (regs, &stack, E_MCRL_REGNUM);
430 push_reg (regs, &stack, E_MCVF_REGNUM);
6c02c64c
KB
431 }
432 if (save_mask & movm_d2_bit)
f7b7ed97 433 push_reg (regs, &stack, E_D2_REGNUM);
6c02c64c 434 if (save_mask & movm_d3_bit)
f7b7ed97 435 push_reg (regs, &stack, E_D3_REGNUM);
6c02c64c 436 if (save_mask & movm_a2_bit)
f7b7ed97 437 push_reg (regs, &stack, E_A2_REGNUM);
6c02c64c 438 if (save_mask & movm_a3_bit)
f7b7ed97 439 push_reg (regs, &stack, E_A3_REGNUM);
6c02c64c
KB
440 if (save_mask & movm_other_bit)
441 {
f7b7ed97
TT
442 push_reg (regs, &stack, E_D0_REGNUM);
443 push_reg (regs, &stack, E_D1_REGNUM);
444 push_reg (regs, &stack, E_A0_REGNUM);
445 push_reg (regs, &stack, E_A1_REGNUM);
446 push_reg (regs, &stack, E_MDR_REGNUM);
447 push_reg (regs, &stack, E_LIR_REGNUM);
448 push_reg (regs, &stack, E_LAR_REGNUM);
6c02c64c
KB
449 /* The `other' bit leaves a blank area of four bytes at
450 the beginning of its block of saved registers, making
451 it 32 bytes long in total. */
452 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4);
453 }
454
455 pc += 2;
456 after_last_frame_setup_insn = pc;
4640dd91 457 }
6c02c64c
KB
458 /* mov sp, aN */
459 else if ((instr[0] & 0xfc) == 0x3c)
460 {
461 int aN = instr[0] & 0x03;
4640dd91 462
6c02c64c 463 regs[E_A0_REGNUM + aN] = regs[E_SP_REGNUM];
4640dd91 464
6c02c64c
KB
465 pc += 1;
466 if (aN == 3)
467 after_last_frame_setup_insn = pc;
468 }
469 /* mov aM, aN */
470 else if ((instr[0] & 0xf0) == 0x90
dda83cd7 471 && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2))
6c02c64c
KB
472 {
473 int aN = instr[0] & 0x03;
474 int aM = (instr[0] & 0x0c) >> 2;
9cacebf5 475
6c02c64c 476 regs[E_A0_REGNUM + aN] = regs[E_A0_REGNUM + aM];
9cacebf5 477
6c02c64c
KB
478 pc += 1;
479 }
480 /* mov dM, dN */
481 else if ((instr[0] & 0xf0) == 0x80
dda83cd7 482 && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2))
6c02c64c
KB
483 {
484 int dN = instr[0] & 0x03;
485 int dM = (instr[0] & 0x0c) >> 2;
9cacebf5 486
6c02c64c 487 regs[E_D0_REGNUM + dN] = regs[E_D0_REGNUM + dM];
9cacebf5 488
6c02c64c
KB
489 pc += 1;
490 }
491 /* mov aM, dN */
492 else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xd0)
493 {
494 int dN = instr[1] & 0x03;
495 int aM = (instr[1] & 0x0c) >> 2;
9cacebf5 496
6c02c64c 497 regs[E_D0_REGNUM + dN] = regs[E_A0_REGNUM + aM];
9cacebf5 498
6c02c64c
KB
499 pc += 2;
500 }
501 /* mov dM, aN */
502 else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xe0)
503 {
504 int aN = instr[1] & 0x03;
505 int dM = (instr[1] & 0x0c) >> 2;
9cacebf5 506
6c02c64c 507 regs[E_A0_REGNUM + aN] = regs[E_D0_REGNUM + dM];
9cacebf5 508
6c02c64c
KB
509 pc += 2;
510 }
511 /* add imm8, SP */
512 else if (instr[0] == 0xf8 && instr[1] == 0xfe)
513 {
514 gdb_byte buf[1];
515 LONGEST imm8;
9cacebf5 516
9cacebf5 517
6c02c64c
KB
518 status = target_read_memory (pc + 2, buf, 1);
519 if (status != 0)
520 break;
9cacebf5 521
e17a4113 522 imm8 = extract_signed_integer (buf, 1, byte_order);
6c02c64c 523 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm8);
9cacebf5 524
6c02c64c
KB
525 pc += 3;
526 /* Stack pointer adjustments are frame related. */
527 after_last_frame_setup_insn = pc;
528 }
529 /* add imm16, SP */
530 else if (instr[0] == 0xfa && instr[1] == 0xfe)
531 {
532 gdb_byte buf[2];
533 LONGEST imm16;
9cacebf5 534
6c02c64c
KB
535 status = target_read_memory (pc + 2, buf, 2);
536 if (status != 0)
537 break;
9cacebf5 538
e17a4113 539 imm16 = extract_signed_integer (buf, 2, byte_order);
6c02c64c 540 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm16);
9cacebf5 541
6c02c64c
KB
542 pc += 4;
543 /* Stack pointer adjustments are frame related. */
544 after_last_frame_setup_insn = pc;
545 }
546 /* add imm32, SP */
547 else if (instr[0] == 0xfc && instr[1] == 0xfe)
548 {
549 gdb_byte buf[4];
550 LONGEST imm32;
9cacebf5 551
6c02c64c
KB
552 status = target_read_memory (pc + 2, buf, 4);
553 if (status != 0)
554 break;
9cacebf5 555
9cacebf5 556
e17a4113 557 imm32 = extract_signed_integer (buf, 4, byte_order);
6c02c64c 558 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm32);
9cacebf5 559
6c02c64c
KB
560 pc += 6;
561 /* Stack pointer adjustments are frame related. */
562 after_last_frame_setup_insn = pc;
563 }
564 /* add imm8, aN */
565 else if ((instr[0] & 0xfc) == 0x20)
566 {
567 int aN;
568 LONGEST imm8;
9cacebf5 569
6c02c64c 570 aN = instr[0] & 0x03;
e17a4113 571 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
9cacebf5 572
6c02c64c 573 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
dda83cd7 574 imm8);
9cacebf5 575
6c02c64c
KB
576 pc += 2;
577 }
578 /* add imm16, aN */
579 else if (instr[0] == 0xfa && (instr[1] & 0xfc) == 0xd0)
580 {
581 int aN;
582 LONGEST imm16;
583 gdb_byte buf[2];
9cacebf5 584
6c02c64c 585 aN = instr[1] & 0x03;
9cacebf5 586
6c02c64c
KB
587 status = target_read_memory (pc + 2, buf, 2);
588 if (status != 0)
589 break;
9cacebf5 590
9cacebf5 591
e17a4113 592 imm16 = extract_signed_integer (buf, 2, byte_order);
9cacebf5 593
6c02c64c 594 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
dda83cd7 595 imm16);
9cacebf5 596
6c02c64c
KB
597 pc += 4;
598 }
599 /* add imm32, aN */
600 else if (instr[0] == 0xfc && (instr[1] & 0xfc) == 0xd0)
601 {
602 int aN;
603 LONGEST imm32;
604 gdb_byte buf[4];
9cacebf5 605
6c02c64c 606 aN = instr[1] & 0x03;
9cacebf5 607
6c02c64c
KB
608 status = target_read_memory (pc + 2, buf, 4);
609 if (status != 0)
610 break;
9cacebf5 611
e17a4113 612 imm32 = extract_signed_integer (buf, 2, byte_order);
9cacebf5 613
6c02c64c 614 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
dda83cd7 615 imm32);
6c02c64c
KB
616 pc += 6;
617 }
618 /* fmov fsM, (rN) */
619 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x30)
620 {
621 int fsM, sM, Y, rN;
622 gdb_byte buf[1];
9cacebf5 623
6c02c64c 624 Y = (instr[1] & 0x02) >> 1;
9cacebf5 625
6c02c64c
KB
626 status = target_read_memory (pc + 2, buf, 1);
627 if (status != 0)
628 break;
9cacebf5 629
6c02c64c
KB
630 sM = (buf[0] & 0xf0) >> 4;
631 rN = buf[0] & 0x0f;
632 fsM = (Y << 4) | sM;
9cacebf5 633
f7b7ed97
TT
634 stack.store (regs[translate_rreg (rN)], 4,
635 regs[E_FS0_REGNUM + fsM]);
9cacebf5 636
6c02c64c
KB
637 pc += 3;
638 }
639 /* fmov fsM, (sp) */
640 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x34)
641 {
642 int fsM, sM, Y;
643 gdb_byte buf[1];
9cacebf5 644
6c02c64c 645 Y = (instr[1] & 0x02) >> 1;
9cacebf5 646
6c02c64c
KB
647 status = target_read_memory (pc + 2, buf, 1);
648 if (status != 0)
649 break;
9cacebf5 650
6c02c64c
KB
651 sM = (buf[0] & 0xf0) >> 4;
652 fsM = (Y << 4) | sM;
9cacebf5 653
f7b7ed97
TT
654 stack.store (regs[E_SP_REGNUM], 4,
655 regs[E_FS0_REGNUM + fsM]);
9cacebf5 656
6c02c64c
KB
657 pc += 3;
658 }
659 /* fmov fsM, (rN, rI) */
660 else if (instr[0] == 0xfb && instr[1] == 0x37)
661 {
662 int fsM, sM, Z, rN, rI;
663 gdb_byte buf[2];
9cacebf5 664
9cacebf5 665
6c02c64c
KB
666 status = target_read_memory (pc + 2, buf, 2);
667 if (status != 0)
668 break;
83845630 669
6c02c64c
KB
670 rI = (buf[0] & 0xf0) >> 4;
671 rN = buf[0] & 0x0f;
672 sM = (buf[1] & 0xf0) >> 4;
673 Z = (buf[1] & 0x02) >> 1;
674 fsM = (Z << 4) | sM;
83845630 675
f7b7ed97
TT
676 stack.store (pv_add (regs[translate_rreg (rN)],
677 regs[translate_rreg (rI)]),
678 4, regs[E_FS0_REGNUM + fsM]);
83845630 679
6c02c64c
KB
680 pc += 4;
681 }
682 /* fmov fsM, (d8, rN) */
683 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x30)
4640dd91 684 {
6c02c64c
KB
685 int fsM, sM, Y, rN;
686 LONGEST d8;
687 gdb_byte buf[2];
688
689 Y = (instr[1] & 0x02) >> 1;
690
691 status = target_read_memory (pc + 2, buf, 2);
692 if (status != 0)
693 break;
694
695 sM = (buf[0] & 0xf0) >> 4;
696 rN = buf[0] & 0x0f;
697 fsM = (Y << 4) | sM;
e17a4113 698 d8 = extract_signed_integer (&buf[1], 1, byte_order);
6c02c64c 699
f7b7ed97
TT
700 stack.store (pv_add_constant (regs[translate_rreg (rN)], d8),
701 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
702
703 pc += 4;
4640dd91 704 }
6c02c64c
KB
705 /* fmov fsM, (d24, rN) */
706 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x30)
83845630 707 {
6c02c64c
KB
708 int fsM, sM, Y, rN;
709 LONGEST d24;
710 gdb_byte buf[4];
711
712 Y = (instr[1] & 0x02) >> 1;
713
714 status = target_read_memory (pc + 2, buf, 4);
83845630 715 if (status != 0)
6c02c64c
KB
716 break;
717
718 sM = (buf[0] & 0xf0) >> 4;
719 rN = buf[0] & 0x0f;
720 fsM = (Y << 4) | sM;
e17a4113 721 d24 = extract_signed_integer (&buf[1], 3, byte_order);
6c02c64c 722
f7b7ed97
TT
723 stack.store (pv_add_constant (regs[translate_rreg (rN)], d24),
724 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
725
726 pc += 6;
83845630 727 }
6c02c64c
KB
728 /* fmov fsM, (d32, rN) */
729 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x30)
730 {
731 int fsM, sM, Y, rN;
732 LONGEST d32;
733 gdb_byte buf[5];
4640dd91 734
6c02c64c
KB
735 Y = (instr[1] & 0x02) >> 1;
736
737 status = target_read_memory (pc + 2, buf, 5);
738 if (status != 0)
739 break;
740
741 sM = (buf[0] & 0xf0) >> 4;
742 rN = buf[0] & 0x0f;
743 fsM = (Y << 4) | sM;
e17a4113 744 d32 = extract_signed_integer (&buf[1], 4, byte_order);
9cacebf5 745
f7b7ed97
TT
746 stack.store (pv_add_constant (regs[translate_rreg (rN)], d32),
747 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
748
749 pc += 7;
750 }
751 /* fmov fsM, (d8, SP) */
752 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x34)
9cacebf5 753 {
6c02c64c
KB
754 int fsM, sM, Y;
755 LONGEST d8;
756 gdb_byte buf[2];
757
758 Y = (instr[1] & 0x02) >> 1;
759
760 status = target_read_memory (pc + 2, buf, 2);
761 if (status != 0)
762 break;
763
764 sM = (buf[0] & 0xf0) >> 4;
765 fsM = (Y << 4) | sM;
e17a4113 766 d8 = extract_signed_integer (&buf[1], 1, byte_order);
6c02c64c 767
f7b7ed97
TT
768 stack.store (pv_add_constant (regs[E_SP_REGNUM], d8),
769 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
770
771 pc += 4;
9cacebf5 772 }
6c02c64c
KB
773 /* fmov fsM, (d24, SP) */
774 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x34)
775 {
776 int fsM, sM, Y;
777 LONGEST d24;
778 gdb_byte buf[4];
9cacebf5 779
6c02c64c 780 Y = (instr[1] & 0x02) >> 1;
9cacebf5 781
6c02c64c
KB
782 status = target_read_memory (pc + 2, buf, 4);
783 if (status != 0)
784 break;
9cacebf5 785
6c02c64c
KB
786 sM = (buf[0] & 0xf0) >> 4;
787 fsM = (Y << 4) | sM;
e17a4113 788 d24 = extract_signed_integer (&buf[1], 3, byte_order);
9cacebf5 789
f7b7ed97
TT
790 stack.store (pv_add_constant (regs[E_SP_REGNUM], d24),
791 4, regs[E_FS0_REGNUM + fsM]);
9cacebf5 792
6c02c64c
KB
793 pc += 6;
794 }
795 /* fmov fsM, (d32, SP) */
796 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x34)
797 {
798 int fsM, sM, Y;
799 LONGEST d32;
800 gdb_byte buf[5];
9cacebf5 801
6c02c64c 802 Y = (instr[1] & 0x02) >> 1;
9cacebf5 803
6c02c64c
KB
804 status = target_read_memory (pc + 2, buf, 5);
805 if (status != 0)
806 break;
807
808 sM = (buf[0] & 0xf0) >> 4;
809 fsM = (Y << 4) | sM;
e17a4113 810 d32 = extract_signed_integer (&buf[1], 4, byte_order);
6c02c64c 811
f7b7ed97
TT
812 stack.store (pv_add_constant (regs[E_SP_REGNUM], d32),
813 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
814
815 pc += 7;
816 }
817 /* fmov fsM, (rN+) */
818 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x31)
819 {
820 int fsM, sM, Y, rN, rN_regnum;
821 gdb_byte buf[1];
822
823 Y = (instr[1] & 0x02) >> 1;
824
825 status = target_read_memory (pc + 2, buf, 1);
826 if (status != 0)
827 break;
828
829 sM = (buf[0] & 0xf0) >> 4;
830 rN = buf[0] & 0x0f;
831 fsM = (Y << 4) | sM;
832
833 rN_regnum = translate_rreg (rN);
834
f7b7ed97
TT
835 stack.store (regs[rN_regnum], 4,
836 regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
837 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], 4);
838
839 pc += 3;
840 }
841 /* fmov fsM, (rN+, imm8) */
842 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x31)
843 {
844 int fsM, sM, Y, rN, rN_regnum;
845 LONGEST imm8;
846 gdb_byte buf[2];
847
848 Y = (instr[1] & 0x02) >> 1;
849
850 status = target_read_memory (pc + 2, buf, 2);
851 if (status != 0)
852 break;
853
854 sM = (buf[0] & 0xf0) >> 4;
855 rN = buf[0] & 0x0f;
856 fsM = (Y << 4) | sM;
e17a4113 857 imm8 = extract_signed_integer (&buf[1], 1, byte_order);
6c02c64c
KB
858
859 rN_regnum = translate_rreg (rN);
860
f7b7ed97 861 stack.store (regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
862 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm8);
863
864 pc += 4;
865 }
866 /* fmov fsM, (rN+, imm24) */
867 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x31)
868 {
869 int fsM, sM, Y, rN, rN_regnum;
870 LONGEST imm24;
871 gdb_byte buf[4];
872
873 Y = (instr[1] & 0x02) >> 1;
874
875 status = target_read_memory (pc + 2, buf, 4);
876 if (status != 0)
877 break;
878
879 sM = (buf[0] & 0xf0) >> 4;
880 rN = buf[0] & 0x0f;
881 fsM = (Y << 4) | sM;
e17a4113 882 imm24 = extract_signed_integer (&buf[1], 3, byte_order);
6c02c64c
KB
883
884 rN_regnum = translate_rreg (rN);
885
f7b7ed97 886 stack.store (regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
887 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm24);
888
889 pc += 6;
890 }
891 /* fmov fsM, (rN+, imm32) */
892 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x31)
893 {
894 int fsM, sM, Y, rN, rN_regnum;
895 LONGEST imm32;
896 gdb_byte buf[5];
897
898 Y = (instr[1] & 0x02) >> 1;
899
900 status = target_read_memory (pc + 2, buf, 5);
901 if (status != 0)
902 break;
903
904 sM = (buf[0] & 0xf0) >> 4;
905 rN = buf[0] & 0x0f;
906 fsM = (Y << 4) | sM;
e17a4113 907 imm32 = extract_signed_integer (&buf[1], 4, byte_order);
6c02c64c
KB
908
909 rN_regnum = translate_rreg (rN);
910
f7b7ed97 911 stack.store (regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
912 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm32);
913
914 pc += 7;
915 }
916 /* mov imm8, aN */
917 else if ((instr[0] & 0xf0) == 0x90)
dda83cd7 918 {
6c02c64c
KB
919 int aN = instr[0] & 0x03;
920 LONGEST imm8;
9cacebf5 921
e17a4113 922 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
9cacebf5 923
6c02c64c
KB
924 regs[E_A0_REGNUM + aN] = pv_constant (imm8);
925 pc += 2;
926 }
927 /* mov imm16, aN */
928 else if ((instr[0] & 0xfc) == 0x24)
dda83cd7 929 {
6c02c64c
KB
930 int aN = instr[0] & 0x03;
931 gdb_byte buf[2];
932 LONGEST imm16;
933
934 status = target_read_memory (pc + 1, buf, 2);
935 if (status != 0)
936 break;
937
e17a4113 938 imm16 = extract_signed_integer (buf, 2, byte_order);
6c02c64c
KB
939 regs[E_A0_REGNUM + aN] = pv_constant (imm16);
940 pc += 3;
941 }
942 /* mov imm32, aN */
943 else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xdc))
dda83cd7 944 {
6c02c64c
KB
945 int aN = instr[1] & 0x03;
946 gdb_byte buf[4];
947 LONGEST imm32;
948
949 status = target_read_memory (pc + 2, buf, 4);
950 if (status != 0)
951 break;
952
e17a4113 953 imm32 = extract_signed_integer (buf, 4, byte_order);
6c02c64c
KB
954 regs[E_A0_REGNUM + aN] = pv_constant (imm32);
955 pc += 6;
956 }
957 /* mov imm8, dN */
958 else if ((instr[0] & 0xf0) == 0x80)
dda83cd7 959 {
6c02c64c
KB
960 int dN = instr[0] & 0x03;
961 LONGEST imm8;
962
e17a4113 963 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
6c02c64c
KB
964
965 regs[E_D0_REGNUM + dN] = pv_constant (imm8);
966 pc += 2;
967 }
968 /* mov imm16, dN */
969 else if ((instr[0] & 0xfc) == 0x2c)
dda83cd7 970 {
6c02c64c
KB
971 int dN = instr[0] & 0x03;
972 gdb_byte buf[2];
973 LONGEST imm16;
974
975 status = target_read_memory (pc + 1, buf, 2);
976 if (status != 0)
977 break;
978
e17a4113 979 imm16 = extract_signed_integer (buf, 2, byte_order);
6c02c64c
KB
980 regs[E_D0_REGNUM + dN] = pv_constant (imm16);
981 pc += 3;
982 }
983 /* mov imm32, dN */
984 else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xcc))
dda83cd7 985 {
6c02c64c
KB
986 int dN = instr[1] & 0x03;
987 gdb_byte buf[4];
988 LONGEST imm32;
989
990 status = target_read_memory (pc + 2, buf, 4);
991 if (status != 0)
992 break;
993
e17a4113 994 imm32 = extract_signed_integer (buf, 4, byte_order);
6c02c64c
KB
995 regs[E_D0_REGNUM + dN] = pv_constant (imm32);
996 pc += 6;
997 }
998 else
999 {
1000 /* We've hit some instruction that we don't recognize. Hopefully,
1001 we have enough to do prologue analysis. */
1002 break;
1003 }
1004 }
1005
1006 /* Is the frame size (offset, really) a known constant? */
1007 if (pv_is_register (regs[E_SP_REGNUM], E_SP_REGNUM))
1008 result->frame_size = regs[E_SP_REGNUM].k;
9cacebf5 1009
6c02c64c
KB
1010 /* Was the frame pointer initialized? */
1011 if (pv_is_register (regs[E_A3_REGNUM], E_SP_REGNUM))
1012 {
1013 result->has_frame_ptr = 1;
1014 result->frame_ptr_offset = regs[E_A3_REGNUM].k;
9cacebf5 1015 }
6c02c64c
KB
1016
1017 /* Record where all the registers were saved. */
f7b7ed97 1018 stack.scan (check_for_saved, (void *) result);
6c02c64c
KB
1019
1020 result->prologue_end = after_last_frame_setup_insn;
9cacebf5
MS
1021}
1022
342ee437
MS
1023/* Function: skip_prologue
1024 Return the address of the first inst past the prologue of the function. */
1025
1026static CORE_ADDR
6093d2eb 1027mn10300_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
342ee437 1028{
2c02bd72 1029 const char *name;
6c02c64c
KB
1030 CORE_ADDR func_addr, func_end;
1031 struct mn10300_prologue p;
1032
1033 /* Try to find the extent of the function that contains PC. */
1034 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1035 return pc;
1036
1037 mn10300_analyze_prologue (gdbarch, pc, func_end, &p);
1038 return p.prologue_end;
342ee437
MS
1039}
1040
6c02c64c
KB
1041/* Wrapper for mn10300_analyze_prologue: find the function start;
1042 use the current frame PC as the limit, then
1043 invoke mn10300_analyze_prologue and return its result. */
1044static struct mn10300_prologue *
8480a37e 1045mn10300_analyze_frame_prologue (const frame_info_ptr &this_frame,
6c02c64c 1046 void **this_prologue_cache)
342ee437 1047{
6c02c64c 1048 if (!*this_prologue_cache)
93d42b30 1049 {
6c02c64c
KB
1050 CORE_ADDR func_start, stop_addr;
1051
1052 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct mn10300_prologue);
1053
1054 func_start = get_frame_func (this_frame);
1055 stop_addr = get_frame_pc (this_frame);
1056
1057 /* If we couldn't find any function containing the PC, then
dda83cd7 1058 just initialize the prologue cache, but don't do anything. */
6c02c64c 1059 if (!func_start)
dda83cd7 1060 stop_addr = func_start;
6c02c64c
KB
1061
1062 mn10300_analyze_prologue (get_frame_arch (this_frame),
19ba03f4
SM
1063 func_start, stop_addr,
1064 ((struct mn10300_prologue *)
1065 *this_prologue_cache));
93d42b30 1066 }
342ee437 1067
19ba03f4 1068 return (struct mn10300_prologue *) *this_prologue_cache;
6c02c64c
KB
1069}
1070
1071/* Given the next frame and a prologue cache, return this frame's
1072 base. */
1073static CORE_ADDR
8480a37e 1074mn10300_frame_base (const frame_info_ptr &this_frame, void **this_prologue_cache)
6c02c64c
KB
1075{
1076 struct mn10300_prologue *p
1077 = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache);
1078
1079 /* In functions that use alloca, the distance between the stack
1080 pointer and the frame base varies dynamically, so we can't use
1081 the SP plus static information like prologue analysis to find the
1082 frame base. However, such functions must have a frame pointer,
1083 to be able to restore the SP on exit. So whenever we do have a
1084 frame pointer, use that to find the base. */
1085 if (p->has_frame_ptr)
1086 {
1087 CORE_ADDR fp = get_frame_register_unsigned (this_frame, E_A3_REGNUM);
1088 return fp - p->frame_ptr_offset;
1089 }
1090 else
1091 {
1092 CORE_ADDR sp = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1093 return sp - p->frame_size;
1094 }
342ee437
MS
1095}
1096
342ee437 1097static void
8480a37e 1098mn10300_frame_this_id (const frame_info_ptr &this_frame,
342ee437
MS
1099 void **this_prologue_cache,
1100 struct frame_id *this_id)
1101{
025bb325
MS
1102 *this_id = frame_id_build (mn10300_frame_base (this_frame,
1103 this_prologue_cache),
6c02c64c 1104 get_frame_func (this_frame));
342ee437 1105
342ee437
MS
1106}
1107
94afd7a6 1108static struct value *
8480a37e 1109mn10300_frame_prev_register (const frame_info_ptr &this_frame,
dda83cd7 1110 void **this_prologue_cache, int regnum)
342ee437 1111{
6c02c64c
KB
1112 struct mn10300_prologue *p
1113 = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache);
1114 CORE_ADDR frame_base = mn10300_frame_base (this_frame, this_prologue_cache);
6c02c64c
KB
1115
1116 if (regnum == E_SP_REGNUM)
1117 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1118
1119 /* If prologue analysis says we saved this register somewhere,
1120 return a description of the stack slot holding it. */
1121 if (p->reg_offset[regnum] != 1)
1122 return frame_unwind_got_memory (this_frame, regnum,
dda83cd7 1123 frame_base + p->reg_offset[regnum]);
6c02c64c
KB
1124
1125 /* Otherwise, presume we haven't changed the value of this
1126 register, and get it from the next frame. */
1127 return frame_unwind_got_register (this_frame, regnum, regnum);
342ee437
MS
1128}
1129
1130static const struct frame_unwind mn10300_frame_unwind = {
a154d838 1131 "mn10300 prologue",
342ee437 1132 NORMAL_FRAME,
8fbca658 1133 default_frame_unwind_stop_reason,
342ee437 1134 mn10300_frame_this_id,
94afd7a6
UW
1135 mn10300_frame_prev_register,
1136 NULL,
1137 default_frame_sniffer
342ee437
MS
1138};
1139
342ee437
MS
1140static void
1141mn10300_frame_unwind_init (struct gdbarch *gdbarch)
1142{
94afd7a6
UW
1143 dwarf2_append_unwinders (gdbarch);
1144 frame_unwind_append_unwinder (gdbarch, &mn10300_frame_unwind);
342ee437
MS
1145}
1146
1147/* Function: push_dummy_call
1148 *
1149 * Set up machine state for a target call, including
1150 * function arguments, stack, return address, etc.
1151 *
1152 */
1153
1154static CORE_ADDR
1155mn10300_push_dummy_call (struct gdbarch *gdbarch,
1156 struct value *target_func,
1157 struct regcache *regcache,
1158 CORE_ADDR bp_addr,
1159 int nargs, struct value **args,
1160 CORE_ADDR sp,
cf84fa6b 1161 function_call_return_method return_method,
342ee437
MS
1162 CORE_ADDR struct_addr)
1163{
e17a4113 1164 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
342ee437 1165 const int push_size = register_size (gdbarch, E_PC_REGNUM);
1fb1ca27 1166 int regs_used;
342ee437
MS
1167 int len, arg_len;
1168 int stack_offset = 0;
1169 int argnum;
948f8e3d 1170 const gdb_byte *val;
b8b6e72f 1171 gdb_byte valbuf[MN10300_MAX_REGISTER_SIZE];
342ee437 1172
342ee437
MS
1173 /* This should be a nop, but align the stack just in case something
1174 went wrong. Stacks are four byte aligned on the mn10300. */
1175 sp &= ~3;
1176
1177 /* Now make space on the stack for the args.
1178
1179 XXX This doesn't appear to handle pass-by-invisible reference
1180 arguments. */
cf84fa6b 1181 regs_used = (return_method == return_method_struct) ? 1 : 0;
342ee437
MS
1182 for (len = 0, argnum = 0; argnum < nargs; argnum++)
1183 {
d0c97917 1184 arg_len = (args[argnum]->type ()->length () + 3) & ~3;
342ee437
MS
1185 while (regs_used < 2 && arg_len > 0)
1186 {
1187 regs_used++;
1188 arg_len -= push_size;
1189 }
1190 len += arg_len;
1191 }
1192
1193 /* Allocate stack space. */
1194 sp -= len;
1195
cf84fa6b 1196 if (return_method == return_method_struct)
1fb1ca27
MS
1197 {
1198 regs_used = 1;
9c9acae0 1199 regcache_cooked_write_unsigned (regcache, E_D0_REGNUM, struct_addr);
1fb1ca27
MS
1200 }
1201 else
1202 regs_used = 0;
1203
025bb325 1204 /* Push all arguments onto the stack. */
342ee437
MS
1205 for (argnum = 0; argnum < nargs; argnum++)
1206 {
1fb1ca27 1207 /* FIXME what about structs? Unions? */
d0c97917
TT
1208 if ((*args)->type ()->code () == TYPE_CODE_STRUCT
1209 && (*args)->type ()->length () > 8)
1fb1ca27
MS
1210 {
1211 /* Change to pointer-to-type. */
1212 arg_len = push_size;
b8b6e72f 1213 gdb_assert (push_size <= MN10300_MAX_REGISTER_SIZE);
e17a4113 1214 store_unsigned_integer (valbuf, push_size, byte_order,
9feb2d07 1215 (*args)->address ());
1fb1ca27
MS
1216 val = &valbuf[0];
1217 }
1218 else
1219 {
d0c97917 1220 arg_len = (*args)->type ()->length ();
efaf1ae0 1221 val = (*args)->contents ().data ();
1fb1ca27 1222 }
342ee437
MS
1223
1224 while (regs_used < 2 && arg_len > 0)
1225 {
9c9acae0 1226 regcache_cooked_write_unsigned (regcache, regs_used,
e17a4113 1227 extract_unsigned_integer (val, push_size, byte_order));
342ee437
MS
1228 val += push_size;
1229 arg_len -= push_size;
1230 regs_used++;
1231 }
1232
1233 while (arg_len > 0)
1234 {
1235 write_memory (sp + stack_offset, val, push_size);
1236 arg_len -= push_size;
1237 val += push_size;
1238 stack_offset += push_size;
1239 }
1240
1241 args++;
1242 }
1243
1244 /* Make space for the flushback area. */
1245 sp -= 8;
1246
1247 /* Push the return address that contains the magic breakpoint. */
1248 sp -= 4;
e17a4113 1249 write_memory_unsigned_integer (sp, push_size, byte_order, bp_addr);
a64ae7e0
CV
1250
1251 /* The CPU also writes the return address always into the
1252 MDR register on "call". */
1253 regcache_cooked_write_unsigned (regcache, E_MDR_REGNUM, bp_addr);
1254
342ee437
MS
1255 /* Update $sp. */
1256 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
ee3a2f01
KB
1257
1258 /* On the mn10300, it's possible to move some of the stack adjustment
1259 and saving of the caller-save registers out of the prologue and
1260 into the call sites. (When using gcc, this optimization can
1261 occur when using the -mrelax switch.) If this occurs, the dwarf2
1262 info will reflect this fact. We can test to see if this is the
1263 case by creating a new frame using the current stack pointer and
1264 the address of the function that we're about to call. We then
1265 unwind SP and see if it's different than the SP of our newly
1266 created frame. If the SP values are the same, the caller is not
1267 expected to allocate any additional stack. On the other hand, if
1268 the SP values are different, the difference determines the
1269 additional stack that must be allocated.
1270
1271 Note that we don't update the return value though because that's
1272 the value of the stack just after pushing the arguments, but prior
1273 to performing the call. This value is needed in order to
025bb325 1274 construct the frame ID of the dummy call. */
ee3a2f01
KB
1275 {
1276 CORE_ADDR func_addr = find_function_addr (target_func, NULL);
1277 CORE_ADDR unwound_sp
aee6c3cd 1278 = gdbarch_unwind_sp (gdbarch, create_new_frame (sp, func_addr));
ee3a2f01
KB
1279 if (sp != unwound_sp)
1280 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM,
dda83cd7 1281 sp - (unwound_sp - sp));
ee3a2f01
KB
1282 }
1283
342ee437
MS
1284 return sp;
1285}
1286
336c28c5
KB
1287/* If DWARF2 is a register number appearing in Dwarf2 debug info, then
1288 mn10300_dwarf2_reg_to_regnum (DWARF2) is the corresponding GDB
1289 register number. Why don't Dwarf2 and GDB use the same numbering?
1290 Who knows? But since people have object files lying around with
1291 the existing Dwarf2 numbering, and other people have written stubs
1292 to work with the existing GDB, neither of them can change. So we
1293 just have to cope. */
1294static int
be8626e0 1295mn10300_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int dwarf2)
336c28c5 1296{
c9f4d572 1297 /* This table is supposed to be shaped like the gdbarch_register_name
336c28c5
KB
1298 initializer in gcc/config/mn10300/mn10300.h. Registers which
1299 appear in GCC's numbering, but have no counterpart in GDB's
1300 world, are marked with a -1. */
1301 static int dwarf2_to_gdb[] = {
c5bb7362
KB
1302 E_D0_REGNUM, E_D1_REGNUM, E_D2_REGNUM, E_D3_REGNUM,
1303 E_A0_REGNUM, E_A1_REGNUM, E_A2_REGNUM, E_A3_REGNUM,
1304 -1, E_SP_REGNUM,
1305
1306 E_E0_REGNUM, E_E1_REGNUM, E_E2_REGNUM, E_E3_REGNUM,
1307 E_E4_REGNUM, E_E5_REGNUM, E_E6_REGNUM, E_E7_REGNUM,
1308
1309 E_FS0_REGNUM + 0, E_FS0_REGNUM + 1, E_FS0_REGNUM + 2, E_FS0_REGNUM + 3,
1310 E_FS0_REGNUM + 4, E_FS0_REGNUM + 5, E_FS0_REGNUM + 6, E_FS0_REGNUM + 7,
1311
1312 E_FS0_REGNUM + 8, E_FS0_REGNUM + 9, E_FS0_REGNUM + 10, E_FS0_REGNUM + 11,
1313 E_FS0_REGNUM + 12, E_FS0_REGNUM + 13, E_FS0_REGNUM + 14, E_FS0_REGNUM + 15,
1314
1315 E_FS0_REGNUM + 16, E_FS0_REGNUM + 17, E_FS0_REGNUM + 18, E_FS0_REGNUM + 19,
1316 E_FS0_REGNUM + 20, E_FS0_REGNUM + 21, E_FS0_REGNUM + 22, E_FS0_REGNUM + 23,
1317
1318 E_FS0_REGNUM + 24, E_FS0_REGNUM + 25, E_FS0_REGNUM + 26, E_FS0_REGNUM + 27,
1319 E_FS0_REGNUM + 28, E_FS0_REGNUM + 29, E_FS0_REGNUM + 30, E_FS0_REGNUM + 31,
1320
1321 E_MDR_REGNUM, E_PSW_REGNUM, E_PC_REGNUM
336c28c5
KB
1322 };
1323
1324 if (dwarf2 < 0
bbc1a784 1325 || dwarf2 >= ARRAY_SIZE (dwarf2_to_gdb))
0fde2c53 1326 return -1;
336c28c5
KB
1327
1328 return dwarf2_to_gdb[dwarf2];
1329}
342ee437
MS
1330
1331static struct gdbarch *
1332mn10300_gdbarch_init (struct gdbarch_info info,
1333 struct gdbarch_list *arches)
1334{
4640dd91 1335 int num_regs;
342ee437
MS
1336
1337 arches = gdbarch_list_lookup_by_info (arches, &info);
1338 if (arches != NULL)
1339 return arches->gdbarch;
1340
2b16913c
SM
1341 gdbarch *gdbarch
1342 = gdbarch_alloc (&info, gdbarch_tdep_up (new mn10300_gdbarch_tdep));
1343 mn10300_gdbarch_tdep *tdep = gdbarch_tdep<mn10300_gdbarch_tdep> (gdbarch);
342ee437
MS
1344
1345 switch (info.bfd_arch_info->mach)
1346 {
1347 case 0:
1348 case bfd_mach_mn10300:
1349 set_gdbarch_register_name (gdbarch, mn10300_generic_register_name);
1350 tdep->am33_mode = 0;
4640dd91 1351 num_regs = 32;
342ee437
MS
1352 break;
1353 case bfd_mach_am33:
1354 set_gdbarch_register_name (gdbarch, am33_register_name);
1355 tdep->am33_mode = 1;
4640dd91
KB
1356 num_regs = 32;
1357 break;
1358 case bfd_mach_am33_2:
1359 set_gdbarch_register_name (gdbarch, am33_2_register_name);
1360 tdep->am33_mode = 2;
1361 num_regs = 64;
1362 set_gdbarch_fp0_regnum (gdbarch, 32);
342ee437
MS
1363 break;
1364 default:
f34652de 1365 internal_error (_("mn10300_gdbarch_init: Unknown mn10300 variant"));
342ee437
MS
1366 break;
1367 }
1368
1b31f75d
KB
1369 /* By default, chars are unsigned. */
1370 set_gdbarch_char_signed (gdbarch, 0);
1371
342ee437 1372 /* Registers. */
4640dd91 1373 set_gdbarch_num_regs (gdbarch, num_regs);
342ee437
MS
1374 set_gdbarch_register_type (gdbarch, mn10300_register_type);
1375 set_gdbarch_skip_prologue (gdbarch, mn10300_skip_prologue);
342ee437
MS
1376 set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1377 set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
336c28c5 1378 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mn10300_dwarf2_reg_to_regnum);
342ee437
MS
1379
1380 /* Stack unwinding. */
1381 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1382 /* Breakpoints. */
04180708
YQ
1383 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1384 mn10300_breakpoint::kind_from_pc);
1385 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1386 mn10300_breakpoint::bp_from_kind);
025bb325 1387 /* decr_pc_after_break? */
342ee437
MS
1388
1389 /* Stage 2 */
99fe5f9d 1390 set_gdbarch_return_value (gdbarch, mn10300_return_value);
342ee437
MS
1391
1392 /* Stage 3 -- get target calls working. */
1393 set_gdbarch_push_dummy_call (gdbarch, mn10300_push_dummy_call);
1394 /* set_gdbarch_return_value (store, extract) */
1395
1396
1397 mn10300_frame_unwind_init (gdbarch);
1398
697e3bc9
KB
1399 /* Hook in ABI-specific overrides, if they have been registered. */
1400 gdbarch_init_osabi (info, gdbarch);
1401
342ee437
MS
1402 return gdbarch;
1403}
1404
025bb325 1405/* Dump out the mn10300 specific architecture information. */
342ee437
MS
1406
1407static void
d93859e2 1408mn10300_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
342ee437 1409{
08106042 1410 mn10300_gdbarch_tdep *tdep = gdbarch_tdep<mn10300_gdbarch_tdep> (gdbarch);
6cb06a8c
TT
1411 gdb_printf (file, "mn10300_dump_tdep: am33_mode = %d\n",
1412 tdep->am33_mode);
342ee437
MS
1413}
1414
6c265988 1415void _initialize_mn10300_tdep ();
342ee437 1416void
6c265988 1417_initialize_mn10300_tdep ()
342ee437
MS
1418{
1419 gdbarch_register (bfd_arch_mn10300, mn10300_gdbarch_init, mn10300_dump_tdep);
1420}
1421