[thirdparty/binutils-gdb.git] / gdb / ppc-tdep.h

/* Target-dependent code for GDB, the GNU debugger.

   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef PPC_TDEP_H
#define PPC_TDEP_H

struct gdbarch;
struct frame_info;
struct value;
struct regcache;
struct type;

/* From ppc-sysv-tdep.c ... */
enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
							struct type *func_type,
							struct type *valtype,
							struct regcache *regcache,
							gdb_byte *readbuf,
							const gdb_byte *writebuf);
enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
							       struct type *func_type,
							       struct type *valtype,
							       struct regcache *regcache,
							       gdb_byte *readbuf,
							       const gdb_byte *writebuf);
CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					struct value *function,
					struct regcache *regcache,
					CORE_ADDR bp_addr, int nargs,
					struct value **args, CORE_ADDR sp,
					int struct_return,
					CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					  struct value *function,
					  struct regcache *regcache,
					  CORE_ADDR bp_addr, int nargs,
					  struct value **args, CORE_ADDR sp,
					  int struct_return,
					  CORE_ADDR struct_addr);
enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
							  struct type *func_type,
							  struct type *valtype,
							  struct regcache *regcache,
							  gdb_byte *readbuf,
							  const gdb_byte *writebuf);

/* From rs6000-tdep.c... */
int altivec_register_p (struct gdbarch *gdbarch, int regno);
int vsx_register_p (struct gdbarch *gdbarch, int regno);
int spe_register_p (struct gdbarch *gdbarch, int regno);

/* Return non-zero if the architecture described by GDBARCH has
   floating-point registers (f0 --- f31 and fpscr).  */
int ppc_floating_point_unit_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   Altivec registers (vr0 --- vr31, vrsave and vscr).  */
int ppc_altivec_support_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   VSX registers (vsr0 --- vsr63).  */
int vsx_support_p (struct gdbarch *gdbarch);
int ppc_deal_with_atomic_sequence (struct frame_info *frame);


/* Register set description.  */

struct ppc_reg_offsets
{
  /* General-purpose registers.  */
  int r0_offset;
  int gpr_size; /* size for r0-31, pc, ps, lr, ctr.  */
  int xr_size;  /* size for cr, xer, mq.  */
  int pc_offset;
  int ps_offset;
  int cr_offset;
  int lr_offset;
  int ctr_offset;
  int xer_offset;
  int mq_offset;

  /* Floating-point registers.  */
  int f0_offset;
  int fpscr_offset;
  int fpscr_size;

  /* AltiVec registers.  */
  int vr0_offset;
  int vscr_offset;
  int vrsave_offset;
};

extern void ppc_supply_reg (struct regcache *regcache, int regnum,
			    const gdb_byte *regs, size_t offset, int regsize);

extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
			     gdb_byte *regs, size_t offset, int regsize);

/* Supply register REGNUM in the general-purpose register set REGSET
   from the buffer specified by GREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_gregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t len);

/* Supply register REGNUM in the floating-point register set REGSET
   from the buffer specified by FPREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_fpregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *fpregs, size_t len);

/* Supply register REGNUM in the Altivec register set REGSET
   from the buffer specified by VRREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vrregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vrregs, size_t len);

/* Supply register REGNUM in the VSX register set REGSET
   from the buffer specified by VSXREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vsxregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vsxregs, size_t len);

/* Collect register REGNUM in the general-purpose register set
   REGSET. from register cache REGCACHE into the buffer specified by
   GREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_gregset (const struct regset *regset,
				 const struct regcache *regcache,
				 int regnum, void *gregs, size_t len);

/* Collect register REGNUM in the floating-point register set
   REGSET. from register cache REGCACHE into the buffer specified by
   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_fpregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *fpregs, size_t len);

/* Collect register REGNUM in the Altivec register set
   REGSET from register cache REGCACHE into the buffer specified by
   VRREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vrregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vrregs, size_t len);

/* Collect register REGNUM in the VSX register set
   REGSET from register cache REGCACHE into the buffer specified by
   VSXREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vsxregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vsxregs, size_t len);

/* Private data that this module attaches to struct gdbarch. */

/* Vector ABI used by the inferior.  */
enum powerpc_vector_abi
{
  POWERPC_VEC_AUTO,
  POWERPC_VEC_GENERIC,
  POWERPC_VEC_ALTIVEC,
  POWERPC_VEC_SPE,
  POWERPC_VEC_LAST
};

struct gdbarch_tdep
  {
    int wordsize;		/* Size in bytes of fixed-point word.  */
    int soft_float;		/* Avoid FP registers for arguments?  */

    /* How to pass vector arguments.  Never set to AUTO or LAST.  */
    enum powerpc_vector_abi vector_abi;

    int ppc_gp0_regnum;		/* GPR register 0 */
    int ppc_toc_regnum;		/* TOC register */
    int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
    int ppc_cr_regnum;		/* Condition register */
    int ppc_lr_regnum;		/* Link register */
    int ppc_ctr_regnum;		/* Count register */
    int ppc_xer_regnum;		/* Integer exception register */

    /* Not all PPC and RS6000 variants will have the registers
       represented below.  A -1 is used to indicate that the register
       is not present in this variant.  */

    /* Floating-point registers.  */
    int ppc_fp0_regnum;         /* floating-point register 0 */
    int ppc_fpscr_regnum;	/* fp status and condition register */

    /* Multiplier-Quotient Register (older POWER architectures only).  */
    int ppc_mq_regnum;

    /* POWER7 VSX registers.  */
    int ppc_vsr0_regnum;	/* First VSX register.  */
    int ppc_vsr0_upper_regnum;  /* First right most dword vsx register.  */
    int ppc_efpr0_regnum;	/* First Extended FP register.  */

    /* Altivec registers.  */
    int ppc_vr0_regnum;		/* First AltiVec register */
    int ppc_vrsave_regnum;	/* Last AltiVec register */

    /* SPE registers.  */
    int ppc_ev0_upper_regnum;   /* First GPR upper half register */
    int ppc_ev0_regnum;         /* First ev register */
    int ppc_acc_regnum;         /* SPE 'acc' register */
    int ppc_spefscr_regnum;     /* SPE 'spefscr' register */

    /* Decimal 128 registers.  */
    int ppc_dl0_regnum;		/* First Decimal128 argument register pair.  */

    /* Offset to ABI specific location where link register is saved.  */
    int lr_frame_offset;	

    /* An array of integers, such that sim_regno[I] is the simulator
       register number for GDB register number I, or -1 if the
       simulator does not implement that register.  */
    int *sim_regno;

    /* ISA-specific types.  */
    struct type *ppc_builtin_type_vec64;
    struct type *ppc_builtin_type_vec128;
};


/* Constants for register set sizes.  */
enum
  {
    ppc_num_gprs = 32,		/* 32 general-purpose registers.  */
    ppc_num_fprs = 32,		/* 32 floating-point registers.  */
    ppc_num_srs = 16,		/* 16 segment registers.  */
    ppc_num_vrs = 32,		/* 32 Altivec vector registers.  */
    ppc_num_vshrs = 32,		/* 32 doublewords (dword 1 of vs0~vs31).  */
    ppc_num_vsrs = 64,		/* 64 VSX vector registers.  */
    ppc_num_efprs = 32		/* 32 Extended FP registers.  */
  };


/* Register number constants.  These are GDB internal register
   numbers; they are not used for the simulator or remote targets.
   Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
   numbers above PPC_NUM_REGS.  So are segment registers and other
   target-defined registers.  */
enum {
  PPC_R0_REGNUM = 0,
  PPC_F0_REGNUM = 32,
  PPC_PC_REGNUM = 64,
  PPC_MSR_REGNUM = 65,
  PPC_CR_REGNUM = 66,
  PPC_LR_REGNUM = 67,
  PPC_CTR_REGNUM = 68,
  PPC_XER_REGNUM = 69,
  PPC_FPSCR_REGNUM = 70,
  PPC_MQ_REGNUM = 71,
  PPC_SPE_UPPER_GP0_REGNUM = 72,
  PPC_SPE_ACC_REGNUM = 104,
  PPC_SPE_FSCR_REGNUM = 105,
  PPC_VR0_REGNUM = 106,
  PPC_VSCR_REGNUM = 138,
  PPC_VRSAVE_REGNUM = 139,
  PPC_VSR0_UPPER_REGNUM = 140,
  PPC_VSR31_UPPER_REGNUM = 171,
  PPC_NUM_REGS
};


/* Instruction size.  */
#define PPC_INSN_SIZE 4

/* Estimate for the maximum number of instrctions in a function epilogue.  */
#define PPC_MAX_EPILOGUE_INSTRUCTIONS  52

#endif /* ppc-tdep.h */
Commit	Line	Data
9aa1e687	1	/* Target-dependent code for GDB, the GNU debugger.
f9be684a	2
0fb0cc75	3	Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
a0c75879	4	Free Software Foundation, Inc.
9aa1e687 KB	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
a9762ec7	10	the Free Software Foundation; either version 3 of the License, or
9aa1e687 KB	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
a9762ec7	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9aa1e687	20
3a1c5313 AC	21	#ifndef PPC_TDEP_H
	22	#define PPC_TDEP_H
	23
da3331ec	24	struct gdbarch;
3a1c5313 AC	25	struct frame_info;
3a1c5313 AC	26	struct value;
4a4b3fed	27	struct regcache;
221c12ff	28	struct type;
3a1c5313	29
7284e1be	30	/* From ppc-sysv-tdep.c ... */
05580c65	31	enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
c055b101	32	struct type *func_type,
05580c65 AC	33	struct type *valtype,
05580c65 AC	34	struct regcache *regcache,
50fd1280 AC	35	gdb_byte *readbuf,
50fd1280 AC	36	const gdb_byte *writebuf);
05580c65	37	enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
c055b101	38	struct type *func_type,
05580c65 AC	39	struct type *valtype,
05580c65 AC	40	struct regcache *regcache,
50fd1280 AC	41	gdb_byte *readbuf,
50fd1280 AC	42	const gdb_byte *writebuf);
77b2b6d4	43	CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	44	struct value *function,
77b2b6d4 AC	45	struct regcache *regcache,
	46	CORE_ADDR bp_addr, int nargs,
	47	struct value **args, CORE_ADDR sp,
	48	int struct_return,
	49	CORE_ADDR struct_addr);
8be9034a	50	CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	51	struct value *function,
8be9034a AC	52	struct regcache *regcache,
	53	CORE_ADDR bp_addr, int nargs,
	54	struct value **args, CORE_ADDR sp,
	55	int struct_return,
	56	CORE_ADDR struct_addr);
05580c65	57	enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
c055b101	58	struct type *func_type,
05580c65 AC	59	struct type *valtype,
05580c65 AC	60	struct regcache *regcache,
50fd1280 AC	61	gdb_byte *readbuf,
50fd1280 AC	62	const gdb_byte *writebuf);
9aa1e687 KB	63
9aa1e687 KB	64	/* From rs6000-tdep.c... */
be8626e0	65	int altivec_register_p (struct gdbarch *gdbarch, int regno);
604c2f83	66	int vsx_register_p (struct gdbarch *gdbarch, int regno);
be8626e0	67	int spe_register_p (struct gdbarch *gdbarch, int regno);
9aa1e687	68
383f0f5b JB	69	/* Return non-zero if the architecture described by GDBARCH has
383f0f5b JB	70	floating-point registers (f0 --- f31 and fpscr). */
0a613259 AC	71	int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
0a613259 AC	72
06caf7d2 CES	73	/* Return non-zero if the architecture described by GDBARCH has
	74	Altivec registers (vr0 --- vr31, vrsave and vscr). */
	75	int ppc_altivec_support_p (struct gdbarch *gdbarch);
	76
604c2f83 LM	77	/* Return non-zero if the architecture described by GDBARCH has
	78	VSX registers (vsr0 --- vsr63). */
	79	int vsx_support_p (struct gdbarch *gdbarch);
4a7622d1 UW	80	int ppc_deal_with_atomic_sequence (struct frame_info *frame);
	81
	82
d195bc9f MK	83	/* Register set description. */
	84
	85	struct ppc_reg_offsets
	86	{
	87	/* General-purpose registers. */
	88	int r0_offset;
f2db237a AM	89	int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
f2db237a AM	90	int xr_size; /* size for cr, xer, mq. */
d195bc9f MK	91	int pc_offset;
	92	int ps_offset;
	93	int cr_offset;
	94	int lr_offset;
	95	int ctr_offset;
	96	int xer_offset;
	97	int mq_offset;
	98
	99	/* Floating-point registers. */
	100	int f0_offset;
	101	int fpscr_offset;
f2db237a	102	int fpscr_size;
d195bc9f MK	103
	104	/* AltiVec registers. */
	105	int vr0_offset;
	106	int vscr_offset;
	107	int vrsave_offset;
	108	};
	109
7284e1be UW	110	extern void ppc_supply_reg (struct regcache *regcache, int regnum,
	111	const gdb_byte *regs, size_t offset, int regsize);
	112
	113	extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
	114	gdb_byte *regs, size_t offset, int regsize);
	115
d195bc9f MK	116	/* Supply register REGNUM in the general-purpose register set REGSET
	117	from the buffer specified by GREGS and LEN to register cache
	118	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	119
	120	extern void ppc_supply_gregset (const struct regset *regset,
	121	struct regcache *regcache,
	122	int regnum, const void *gregs, size_t len);
	123
	124	/* Supply register REGNUM in the floating-point register set REGSET
	125	from the buffer specified by FPREGS and LEN to register cache
	126	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	127
	128	extern void ppc_supply_fpregset (const struct regset *regset,
	129	struct regcache *regcache,
	130	int regnum, const void *fpregs, size_t len);
	131
06caf7d2 CES	132	/* Supply register REGNUM in the Altivec register set REGSET
	133	from the buffer specified by VRREGS and LEN to register cache
	134	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	135
	136	extern void ppc_supply_vrregset (const struct regset *regset,
	137	struct regcache *regcache,
	138	int regnum, const void *vrregs, size_t len);
	139
604c2f83 LM	140	/* Supply register REGNUM in the VSX register set REGSET
	141	from the buffer specified by VSXREGS and LEN to register cache
	142	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	143
	144	extern void ppc_supply_vsxregset (const struct regset *regset,
	145	struct regcache *regcache,
	146	int regnum, const void *vsxregs, size_t len);
	147
d195bc9f MK	148	/* Collect register REGNUM in the general-purpose register set
	149	REGSET. from register cache REGCACHE into the buffer specified by
	150	GREGS and LEN. If REGNUM is -1, do this for all registers in
	151	REGSET. */
	152
	153	extern void ppc_collect_gregset (const struct regset *regset,
	154	const struct regcache *regcache,
	155	int regnum, void *gregs, size_t len);
	156
	157	/* Collect register REGNUM in the floating-point register set
	158	REGSET. from register cache REGCACHE into the buffer specified by
	159	FPREGS and LEN. If REGNUM is -1, do this for all registers in
	160	REGSET. */
	161
	162	extern void ppc_collect_fpregset (const struct regset *regset,
	163	const struct regcache *regcache,
	164	int regnum, void *fpregs, size_t len);
	165
06caf7d2 CES	166	/* Collect register REGNUM in the Altivec register set
	167	REGSET from register cache REGCACHE into the buffer specified by
	168	VRREGS and LEN. If REGNUM is -1, do this for all registers in
	169	REGSET. */
	170
	171	extern void ppc_collect_vrregset (const struct regset *regset,
	172	const struct regcache *regcache,
	173	int regnum, void *vrregs, size_t len);
	174
604c2f83 LM	175	/* Collect register REGNUM in the VSX register set
	176	REGSET from register cache REGCACHE into the buffer specified by
	177	VSXREGS and LEN. If REGNUM is -1, do this for all registers in
	178	REGSET. */
	179
	180	extern void ppc_collect_vsxregset (const struct regset *regset,
	181	const struct regcache *regcache,
	182	int regnum, void *vsxregs, size_t len);
	183
2188cbdd EZ	184	/* Private data that this module attaches to struct gdbarch. */
2188cbdd EZ	185
55eddb0f DJ	186	/* Vector ABI used by the inferior. */
	187	enum powerpc_vector_abi
	188	{
	189	POWERPC_VEC_AUTO,
	190	POWERPC_VEC_GENERIC,
	191	POWERPC_VEC_ALTIVEC,
	192	POWERPC_VEC_SPE,
	193	POWERPC_VEC_LAST
	194	};
	195
2188cbdd EZ	196	struct gdbarch_tdep
2188cbdd EZ	197	{
55eddb0f DJ	198	int wordsize; /* Size in bytes of fixed-point word. */
	199	int soft_float; /* Avoid FP registers for arguments? */
	200
	201	/* How to pass vector arguments. Never set to AUTO or LAST. */
	202	enum powerpc_vector_abi vector_abi;
	203
2188cbdd	204	int ppc_gp0_regnum; /* GPR register 0 */
2188cbdd EZ	205	int ppc_toc_regnum; /* TOC register */
	206	int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
	207	int ppc_cr_regnum; /* Condition register */
	208	int ppc_lr_regnum; /* Link register */
	209	int ppc_ctr_regnum; /* Count register */
	210	int ppc_xer_regnum; /* Integer exception register */
383f0f5b	211
826d5376 PG	212	/* Not all PPC and RS6000 variants will have the registers
	213	represented below. A -1 is used to indicate that the register
	214	is not present in this variant. */
	215
	216	/* Floating-point registers. */
366f009f	217	int ppc_fp0_regnum; /* floating-point register 0 */
826d5376 PG	218	int ppc_fpscr_regnum; /* fp status and condition register */
826d5376 PG	219
826d5376 PG	220	/* Multiplier-Quotient Register (older POWER architectures only). */
826d5376 PG	221	int ppc_mq_regnum;
f86a7158	222
604c2f83 LM	223	/* POWER7 VSX registers. */
	224	int ppc_vsr0_regnum; /* First VSX register. */
	225	int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */
	226	int ppc_efpr0_regnum; /* First Extended FP register. */
	227
826d5376	228	/* Altivec registers. */
1fcc0bb8 EZ	229	int ppc_vr0_regnum; /* First AltiVec register */
1fcc0bb8 EZ	230	int ppc_vrsave_regnum; /* Last AltiVec register */
826d5376 PG	231
826d5376 PG	232	/* SPE registers. */
6ced10dd	233	int ppc_ev0_upper_regnum; /* First GPR upper half register */
c8001721	234	int ppc_ev0_regnum; /* First ev register */
867e2dc5 JB	235	int ppc_acc_regnum; /* SPE 'acc' register */
867e2dc5 JB	236	int ppc_spefscr_regnum; /* SPE 'spefscr' register */
826d5376	237
f949c649 TJB	238	/* Decimal 128 registers. */
	239	int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
	240
826d5376 PG	241	/* Offset to ABI specific location where link register is saved. */
826d5376 PG	242	int lr_frame_offset;
9f643768 JB	243
	244	/* An array of integers, such that sim_regno[I] is the simulator
	245	register number for GDB register number I, or -1 if the
	246	simulator does not implement that register. */
	247	int *sim_regno;
6f7f3f0d	248
794ac428 UW	249	/* ISA-specific types. */
794ac428 UW	250	struct type *ppc_builtin_type_vec64;
604c2f83	251	struct type *ppc_builtin_type_vec128;
2188cbdd	252	};
3a1c5313	253
b967e06f JB	254
	255	/* Constants for register set sizes. */
	256	enum
	257	{
604c2f83 LM	258	ppc_num_gprs = 32, /* 32 general-purpose registers. */
	259	ppc_num_fprs = 32, /* 32 floating-point registers. */
	260	ppc_num_srs = 16, /* 16 segment registers. */
	261	ppc_num_vrs = 32, /* 32 Altivec vector registers. */
	262	ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */
	263	ppc_num_vsrs = 64, /* 64 VSX vector registers. */
	264	ppc_num_efprs = 32 /* 32 Extended FP registers. */
b967e06f JB	265	};
b967e06f JB	266
0ea0ec5f	267
7cc46491 DJ	268	/* Register number constants. These are GDB internal register
	269	numbers; they are not used for the simulator or remote targets.
	270	Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
	271	numbers above PPC_NUM_REGS. So are segment registers and other
	272	target-defined registers. */
	273	enum {
	274	PPC_R0_REGNUM = 0,
	275	PPC_F0_REGNUM = 32,
	276	PPC_PC_REGNUM = 64,
	277	PPC_MSR_REGNUM = 65,
	278	PPC_CR_REGNUM = 66,
	279	PPC_LR_REGNUM = 67,
	280	PPC_CTR_REGNUM = 68,
	281	PPC_XER_REGNUM = 69,
	282	PPC_FPSCR_REGNUM = 70,
	283	PPC_MQ_REGNUM = 71,
	284	PPC_SPE_UPPER_GP0_REGNUM = 72,
	285	PPC_SPE_ACC_REGNUM = 104,
	286	PPC_SPE_FSCR_REGNUM = 105,
	287	PPC_VR0_REGNUM = 106,
	288	PPC_VSCR_REGNUM = 138,
	289	PPC_VRSAVE_REGNUM = 139,
604c2f83 LM	290	PPC_VSR0_UPPER_REGNUM = 140,
604c2f83 LM	291	PPC_VSR31_UPPER_REGNUM = 171,
7cc46491 DJ	292	PPC_NUM_REGS
7cc46491 DJ	293	};
0ea0ec5f	294
0ea0ec5f	295
a0c75879 MK	296	/* Instruction size. */
	297	#define PPC_INSN_SIZE 4
	298
0d1243d9 PG	299	/* Estimate for the maximum number of instrctions in a function epilogue. */
	300	#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
	301
a0c75879	302	#endif /* ppc-tdep.h */