[thirdparty/binutils-gdb.git] / gdb / xtensa-tdep.h

/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.

   Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street, Fifth Floor,
   Boston, MA 02110-1301, USA.  */


/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
   whenever the "tdep" structure changes in an incompatible way.  */

#define XTENSA_TDEP_VERSION 0x60

/*  Xtensa register type.  */

typedef enum 
{
  xtRegisterTypeArRegfile = 1,	/* Register File ar0..arXX.  */
  xtRegisterTypeSpecialReg,	/* CPU states, such as PS, Booleans, (rsr).  */
  xtRegisterTypeUserReg,	/* User defined registers (rur).  */
  xtRegisterTypeTieRegfile,	/* User define register files.  */
  xtRegisterTypeTieState,	/* TIE States (mapped on user regs).  */
  xtRegisterTypeMapped,		/* Mapped on Special Registers.  */
  xtRegisterTypeUnmapped,	/* Special case of masked registers.  */
  xtRegisterTypeWindow,		/* Live window registers (a0..a15).  */
  xtRegisterTypeVirtual,	/* PC, FP.  */
  xtRegisterTypeUnknown
} xtensa_register_type_t;


/*  Xtensa register group.  */

#define XTENSA_MAX_COPROCESSOR	0x08  /* Number of Xtensa coprocessors.  */

typedef enum 
{
  xtRegisterGroupUnknown = 0,
  xtRegisterGroupRegFile	= 0x0001,    /* Register files without ARx.  */
  xtRegisterGroupAddrReg	= 0x0002,    /* ARx.  */
  xtRegisterGroupSpecialReg	= 0x0004,    /* SRxx.  */
  xtRegisterGroupUserReg	= 0x0008,    /* URxx.  */
  xtRegisterGroupState 		= 0x0010,    /* States.  */

  xtRegisterGroupGeneral	= 0x0100,    /* General registers, Ax, SR.  */
  xtRegisterGroupUser		= 0x0200,    /* User registers.  */
  xtRegisterGroupFloat		= 0x0400,    /* Floating Point.  */
  xtRegisterGroupVectra		= 0x0800,    /* Vectra.  */
  xtRegisterGroupSystem		= 0x1000,    /* System.  */

  xtRegisterGroupCP0	    = 0x01000000,    /* CP0.  */
  xtRegisterGroupCP1	    = 0x02000000,    /* CP1.  */
  xtRegisterGroupCP2	    = 0x04000000,    /* CP2.  */
  xtRegisterGroupCP3	    = 0x08000000,    /* CP3.  */
  xtRegisterGroupCP4	    = 0x10000000,    /* CP4.  */
  xtRegisterGroupCP5	    = 0x20000000,    /* CP5.  */
  xtRegisterGroupCP6	    = 0x40000000,    /* CP6.  */
  xtRegisterGroupCP7	    = 0x80000000,    /* CP7.  */

} xtensa_register_group_t;


/*  Xtensa target flags.  */

typedef enum 
{
  xtTargetFlagsNonVisibleRegs	= 0x0001,
  xtTargetFlagsUseFetchStore	= 0x0002,
} xtensa_target_flags_t;


/* Xtensa ELF core file register set representation ('.reg' section). 
   Copied from target-side ELF header <xtensa/elf.h>.  */

typedef unsigned long xtensa_elf_greg_t;

typedef struct
{
  xtensa_elf_greg_t xchal_config_id0;
  xtensa_elf_greg_t xchal_config_id1;
  xtensa_elf_greg_t cpux;
  xtensa_elf_greg_t cpuy;
  xtensa_elf_greg_t pc;
  xtensa_elf_greg_t ps;
  xtensa_elf_greg_t exccause;
  xtensa_elf_greg_t excvaddr;
  xtensa_elf_greg_t windowbase;
  xtensa_elf_greg_t windowstart;
  xtensa_elf_greg_t lbeg;
  xtensa_elf_greg_t lend;
  xtensa_elf_greg_t lcount;
  xtensa_elf_greg_t sar;
  xtensa_elf_greg_t syscall;
  xtensa_elf_greg_t ar[0];	/* variable size (per config).  */
} xtensa_elf_gregset_t;

#define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + NUM_AREGS * 4)
#define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t))


/*  Mask.  */

typedef struct 
{
  int reg_num;
  int bit_start;
  int bit_size;
} xtensa_reg_mask_t;

typedef struct 
{
  int count;
  xtensa_reg_mask_t *mask;
} xtensa_mask_t;


/*  Xtensa register representation.  */

typedef struct 
{
  char* name;             	/* Register name.  */
  int offset;             	/* Offset.  */
  xtensa_register_type_t type;  /* Register type.  */
  xtensa_register_group_t group;/* Register group.  */
  struct type* ctype;		/* C-type.  */
  int bit_size;  		/* The actual bit size in the target.  */
  int byte_size;          	/* Actual space allocated in registers[].  */
  int align;			/* Alignment for this register.  */

  unsigned int target_number;	/* Register target number.  */

  int flags;			/* Flags.  */

  const xtensa_mask_t *mask;	/* Register is a compilation of other regs.  */
  const char *fetch;		/* Instruction sequence to fetch register.  */
  const char *store;		/* Instruction sequence to store register.  */
} xtensa_register_t;


#define XTENSA_REGISTER_FLAGS_PRIVILEDGED	0x0001
#define XTENSA_REGISTER_FLAGS_READABLE		0x0002
#define XTENSA_REGISTER_FLAGS_WRITABLE		0x0004
#define XTENSA_REGISTER_FLAGS_VOLATILE		0x0008


/*  Call-ABI for stack frame.  */

typedef enum 
{
  CallAbiDefault = 0,		/* Any 'callX' instructions; default stack.  */
  CallAbiCall0Only,		/* Only 'call0' instructions; flat stack.  */
} call_abi_t;


/*  Xtensa-specific target dependencies.  */

struct gdbarch_tdep
{
  unsigned int target_flags;

  /* Spill location for TIE register files under ocd.  */

  unsigned int spill_location;
  unsigned int spill_size;

  char *unused;				/* Placeholder for compatibility.  */
  call_abi_t call_abi;			/* Calling convention.  */

  /* CPU configuration.  */

  unsigned int debug_interrupt_level;

  unsigned int icache_line_bytes;
  unsigned int dcache_line_bytes;
  unsigned int dcache_writeback;

  unsigned int isa_use_windowed_registers;
  unsigned int isa_use_density_instructions;
  unsigned int isa_use_exceptions;
  unsigned int isa_use_ext_l32r;
  unsigned int isa_max_insn_size;	/* Maximum instruction length.  */
  unsigned int debug_num_ibreaks;	/* Number of IBREAKs.  */
  unsigned int debug_num_dbreaks;

  /* Register map.  */

  xtensa_register_t* regmap;

  unsigned int num_regs;	/* Number of registers in regmap.  */
  unsigned int num_pseudo_regs;	/* Number of pseudo registers.  */
  unsigned int num_aregs;	/* Size of register file.  */
  unsigned int num_contexts;

  int ar_base;			/* Register number for AR0.  */
  int a0_base;			/* Register number for A0 (pseudo).  */
  int wb_regnum;		/* Register number for WB.  */
  int ws_regnum;		/* Register number for WS.  */
  int pc_regnum;		/* Register number for PC.  */
  int ps_regnum;		/* Register number for PS.  */
  int lbeg_regnum;		/* Register numbers for count regs.  */
  int lend_regnum;
  int lcount_regnum;
  int sar_regnum;		/* Register number of SAR.  */
  int litbase_regnum;		/* Register number of LITBASE.  */

  int interrupt_regnum;		/* Register number for interrupt.  */
  int interrupt2_regnum;	/* Register number for interrupt2.  */
  int cpenable_regnum;		/* Register number for cpenable.  */
  int debugcause_regnum;	/* Register number for debugcause.  */
  int exccause_regnum;		/* Register number for exccause.  */
  int excvaddr_regnum;		/* Register number for excvaddr.  */

  int max_register_raw_size;
  int max_register_virtual_size;
  unsigned long *fp_layout;	/* Layout of custom/TIE regs in 'FP' area.  */
  unsigned int fp_layout_bytes;	/* Size of layout information (in bytes).  */
  unsigned long *gregmap;
};


/* Define macros to access some of the gdbarch entries.  */
#define XTENSA_TARGET_FLAGS \
  (gdbarch_tdep (current_gdbarch)->target_flags)
#define SPILL_LOCATION \
  (gdbarch_tdep (current_gdbarch)->spill_location)
#define SPILL_SIZE \
  (gdbarch_tdep (current_gdbarch)->spill_size)
#define CALL_ABI		\
  (gdbarch_tdep (current_gdbarch)->call_abi)
#define ISA_USE_WINDOWED_REGISTERS \
  (gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers)
#define ISA_USE_DENSITY_INSTRUCTIONS \
  (gdbarch_tdep (current_gdbarch)->isa_use_density_instructions)
#define ISA_USE_EXCEPTIONS \
  (gdbarch_tdep (current_gdbarch)->isa_use_exceptions)
#define ISA_USE_EXT_L32R \
  (gdbarch_tdep (current_gdbarch)->isa_use_ext_l32r)
#define DEBUG_DATA_VADDR_TRAP_COUNT \
  (gdbarch_tdep (current_gdbarch)->debug_data_vaddr_trap_count)
#define DEBUG_INST_VADDR_TRAP_COUNT \
  (gdbarch_tdep (current_gdbarch)->debug_inst_vaddr_trap_count)
#define ISA_MAX_INSN_SIZE \
  (gdbarch_tdep (current_gdbarch)->isa_max_insn_size)
#define DEBUG_NUM_IBREAKS \
  (gdbarch_tdep (current_gdbarch)->debug_num_ibreaks)
#define DEBUG_NUM_DBREAKS \
  (gdbarch_tdep (current_gdbarch)->debug_num_dbreaks)

#define NUM_AREGS         (gdbarch_tdep (current_gdbarch)->num_aregs)
#define WB_REGNUM         (gdbarch_tdep (current_gdbarch)->wb_regnum)
#define WS_REGNUM         (gdbarch_tdep (current_gdbarch)->ws_regnum)
#define LBEG_REGNUM       (gdbarch_tdep (current_gdbarch)->lbeg_regnum)
#define LEND_REGNUM       (gdbarch_tdep (current_gdbarch)->lend_regnum)
#define LCOUNT_REGNUM     (gdbarch_tdep (current_gdbarch)->lcount_regnum)
#define SAR_REGNUM        (gdbarch_tdep (current_gdbarch)->sar_regnum)
#define REGMAP            (gdbarch_tdep (current_gdbarch)->regmap)

#define LITBASE_REGNUM    (gdbarch_tdep (current_gdbarch)->litbase_regnum)
#define DEBUGCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->debugcause_regnum)
#define EXCCAUSE_REGNUM   (gdbarch_tdep (current_gdbarch)->exccause_regnum)
#define EXCVADDR_REGNUM   (gdbarch_tdep (current_gdbarch)->excvaddr_regnum)
#define NUM_IBREAKS       (gdbarch_tdep (current_gdbarch)->num_ibreaks)
#define REGMAP_BYTES      (gdbarch_tdep (current_gdbarch)->regmap_bytes)
#define A0_BASE           (gdbarch_tdep (current_gdbarch)->a0_base)
#define AR_BASE           (gdbarch_tdep (current_gdbarch)->ar_base)
#define FP_ALIAS \
  (gdbarch_num_regs (current_gdbarch) \
   + gdbarch_num_pseudo_regs (current_gdbarch))
#define CALL_ABI          (gdbarch_tdep (current_gdbarch)->call_abi)
#define NUM_CONTEXTS      (gdbarch_tdep (current_gdbarch)->num_contexts)
  
#define FP_LAYOUT         (gdbarch_tdep (current_gdbarch)->fp_layout)
#define FP_LAYOUT_BYTES   (gdbarch_tdep (current_gdbarch)->fp_layout_bytes)
#define GREGMAP           (gdbarch_tdep (current_gdbarch)->gregmap)

#define AREGS_MASK	  (NUM_AREGS - 1)
#define WB_MASK		  (AREGS_MASK >> 2)
#define WB_SHIFT	  2

/* We assign fixed numbers to the registers of the "current" window 
   (i.e., relative to WB).  The registers get remapped via the reg_map 
   data structure to their corresponding register in the AR register 
   file (see xtensa-tdep.c).  */

#define A0_REGNUM  (A0_BASE + 0)
#define A1_REGNUM  (A0_BASE + 1)
#define A2_REGNUM  (A0_BASE + 2)
#define A3_REGNUM  (A0_BASE + 3)
#define A4_REGNUM  (A0_BASE + 4)
#define A5_REGNUM  (A0_BASE + 5)
#define A6_REGNUM  (A0_BASE + 6)
#define A7_REGNUM  (A0_BASE + 7)
#define A8_REGNUM  (A0_BASE + 8)
#define A9_REGNUM  (A0_BASE + 9)
#define A10_REGNUM (A0_BASE + 10)
#define A11_REGNUM (A0_BASE + 11)
#define A12_REGNUM (A0_BASE + 12)
#define A13_REGNUM (A0_BASE + 13)
#define A14_REGNUM (A0_BASE + 14)
#define A15_REGNUM (A0_BASE + 15)
Commit	Line	Data
ca3bf3bd DJ	1	/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
ca3bf3bd DJ	2
6aba47ca	3	Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
ca3bf3bd DJ	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 51 Franklin Street, Fifth Floor,
	20	Boston, MA 02110-1301, USA. */
	21
	22
	23	/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
	24	whenever the "tdep" structure changes in an incompatible way. */
	25
	26	#define XTENSA_TDEP_VERSION 0x60
	27
	28	/* Xtensa register type. */
	29
	30	typedef enum
	31	{
	32	xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */
	33	xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */
	34	xtRegisterTypeUserReg, /* User defined registers (rur). */
	35	xtRegisterTypeTieRegfile, /* User define register files. */
	36	xtRegisterTypeTieState, /* TIE States (mapped on user regs). */
	37	xtRegisterTypeMapped, /* Mapped on Special Registers. */
	38	xtRegisterTypeUnmapped, /* Special case of masked registers. */
	39	xtRegisterTypeWindow, /* Live window registers (a0..a15). */
	40	xtRegisterTypeVirtual, /* PC, FP. */
	41	xtRegisterTypeUnknown
	42	} xtensa_register_type_t;
	43
	44
	45	/* Xtensa register group. */
	46
7b871568 MG	47	#define XTENSA_MAX_COPROCESSOR 0x08 /* Number of Xtensa coprocessors. */
7b871568 MG	48
ca3bf3bd DJ	49	typedef enum
	50	{
	51	xtRegisterGroupUnknown = 0,
	52	xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */
	53	xtRegisterGroupAddrReg = 0x0002, /* ARx. */
	54	xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */
	55	xtRegisterGroupUserReg = 0x0008, /* URxx. */
	56	xtRegisterGroupState = 0x0010, /* States. */
	57
	58	xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */
	59	xtRegisterGroupUser = 0x0200, /* User registers. */
	60	xtRegisterGroupFloat = 0x0400, /* Floating Point. */
	61	xtRegisterGroupVectra = 0x0800, /* Vectra. */
	62	xtRegisterGroupSystem = 0x1000, /* System. */
7b871568 MG	63
	64	xtRegisterGroupCP0 = 0x01000000, /* CP0. */
	65	xtRegisterGroupCP1 = 0x02000000, /* CP1. */
	66	xtRegisterGroupCP2 = 0x04000000, /* CP2. */
	67	xtRegisterGroupCP3 = 0x08000000, /* CP3. */
	68	xtRegisterGroupCP4 = 0x10000000, /* CP4. */
	69	xtRegisterGroupCP5 = 0x20000000, /* CP5. */
	70	xtRegisterGroupCP6 = 0x40000000, /* CP6. */
	71	xtRegisterGroupCP7 = 0x80000000, /* CP7. */
	72
ca3bf3bd DJ	73	} xtensa_register_group_t;
	74
	75
	76	/* Xtensa target flags. */
	77
	78	typedef enum
	79	{
	80	xtTargetFlagsNonVisibleRegs = 0x0001,
	81	xtTargetFlagsUseFetchStore = 0x0002,
	82	} xtensa_target_flags_t;
	83
	84
	85	/* Xtensa ELF core file register set representation ('.reg' section).
	86	Copied from target-side ELF header <xtensa/elf.h>. */
	87
	88	typedef unsigned long xtensa_elf_greg_t;
	89
	90	typedef struct
	91	{
	92	xtensa_elf_greg_t xchal_config_id0;
	93	xtensa_elf_greg_t xchal_config_id1;
	94	xtensa_elf_greg_t cpux;
	95	xtensa_elf_greg_t cpuy;
	96	xtensa_elf_greg_t pc;
	97	xtensa_elf_greg_t ps;
	98	xtensa_elf_greg_t exccause;
	99	xtensa_elf_greg_t excvaddr;
	100	xtensa_elf_greg_t windowbase;
	101	xtensa_elf_greg_t windowstart;
	102	xtensa_elf_greg_t lbeg;
	103	xtensa_elf_greg_t lend;
	104	xtensa_elf_greg_t lcount;
	105	xtensa_elf_greg_t sar;
	106	xtensa_elf_greg_t syscall;
	107	xtensa_elf_greg_t ar[0]; /* variable size (per config). */
	108	} xtensa_elf_gregset_t;
	109
	110	#define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + NUM_AREGS * 4)
	111	#define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t))
	112
	113
	114	/* Mask. */
	115
ff7a4c00 MG	116	typedef struct
	117	{
	118	int reg_num;
	119	int bit_start;
	120	int bit_size;
	121	} xtensa_reg_mask_t;
	122
ca3bf3bd DJ	123	typedef struct
	124	{
	125	int count;
ff7a4c00	126	xtensa_reg_mask_t *mask;
ca3bf3bd DJ	127	} xtensa_mask_t;
	128
	129
	130	/* Xtensa register representation. */
	131
	132	typedef struct
	133	{
	134	char* name; /* Register name. */
	135	int offset; /* Offset. */
	136	xtensa_register_type_t type; /* Register type. */
	137	xtensa_register_group_t group;/* Register group. */
	138	struct type* ctype; /* C-type. */
	139	int bit_size; /* The actual bit size in the target. */
	140	int byte_size; /* Actual space allocated in registers[]. */
	141	int align; /* Alignment for this register. */
	142
	143	unsigned int target_number; /* Register target number. */
	144
	145	int flags; /* Flags. */
	146
	147	const xtensa_mask_t mask; / Register is a compilation of other regs. */
	148	const char fetch; / Instruction sequence to fetch register. */
	149	const char store; / Instruction sequence to store register. */
	150	} xtensa_register_t;
	151
	152
	153	#define XTENSA_REGISTER_FLAGS_PRIVILEDGED 0x0001
	154	#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
	155	#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
	156	#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
	157
	158
	159	/* Call-ABI for stack frame. */
	160
	161	typedef enum
	162	{
	163	CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */
	164	CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */
	165	} call_abi_t;
	166
	167
	168	/* Xtensa-specific target dependencies. */
	169
	170	struct gdbarch_tdep
	171	{
	172	unsigned int target_flags;
	173
	174	/* Spill location for TIE register files under ocd. */
	175
	176	unsigned int spill_location;
	177	unsigned int spill_size;
	178
	179	char unused; / Placeholder for compatibility. */
	180	call_abi_t call_abi; /* Calling convention. */
	181
	182	/* CPU configuration. */
	183
	184	unsigned int debug_interrupt_level;
	185
	186	unsigned int icache_line_bytes;
	187	unsigned int dcache_line_bytes;
	188	unsigned int dcache_writeback;
	189
	190	unsigned int isa_use_windowed_registers;
191	unsigned int isa_use_density_instructions;
192	unsigned int isa_use_exceptions;
193	unsigned int isa_use_ext_l32r;
194	unsigned int isa_max_insn_size; /* Maximum instruction length. */
195	unsigned int debug_num_ibreaks; /* Number of IBREAKs. */
196	unsigned int debug_num_dbreaks;
197
198	/* Register map. */
199
200	xtensa_register_t* regmap;
201
202	unsigned int num_regs; /* Number of registers in regmap. */
203	unsigned int num_pseudo_regs; /* Number of pseudo registers. */
204	unsigned int num_aregs; /* Size of register file. */
205	unsigned int num_contexts;
206
207	int ar_base; /* Register number for AR0. */
208	int a0_base; /* Register number for A0 (pseudo). */
209	int wb_regnum; /* Register number for WB. */
210	int ws_regnum; /* Register number for WS. */
211	int pc_regnum; /* Register number for PC. */
212	int ps_regnum; /* Register number for PS. */
213	int lbeg_regnum; /* Register numbers for count regs. */
214	int lend_regnum;
215	int lcount_regnum;
216	int sar_regnum; /* Register number of SAR. */
217	int litbase_regnum; /* Register number of LITBASE. */
218
219	int interrupt_regnum; /* Register number for interrupt. */
220	int interrupt2_regnum; /* Register number for interrupt2. */
221	int cpenable_regnum; /* Register number for cpenable. */
222	int debugcause_regnum; /* Register number for debugcause. */
223	int exccause_regnum; /* Register number for exccause. */
224	int excvaddr_regnum; /* Register number for excvaddr. */
225
226	int max_register_raw_size;
227	int max_register_virtual_size;
228	unsigned long fp_layout; / Layout of custom/TIE regs in 'FP' area. */
229	unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */
230	unsigned long *gregmap;
231	};
232
233
234	/* Define macros to access some of the gdbarch entries. */
235	#define XTENSA_TARGET_FLAGS \
236	(gdbarch_tdep (current_gdbarch)->target_flags)
237	#define SPILL_LOCATION \
238	(gdbarch_tdep (current_gdbarch)->spill_location)
239	#define SPILL_SIZE \
240	(gdbarch_tdep (current_gdbarch)->spill_size)
241	#define CALL_ABI \
242	(gdbarch_tdep (current_gdbarch)->call_abi)
243	#define ISA_USE_WINDOWED_REGISTERS \
244	(gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers)
245	#define ISA_USE_DENSITY_INSTRUCTIONS \
246	(gdbarch_tdep (current_gdbarch)->isa_use_density_instructions)
247	#define ISA_USE_EXCEPTIONS \
248	(gdbarch_tdep (current_gdbarch)->isa_use_exceptions)
249	#define ISA_USE_EXT_L32R \
250	(gdbarch_tdep (current_gdbarch)->isa_use_ext_l32r)
251	#define DEBUG_DATA_VADDR_TRAP_COUNT \
252	(gdbarch_tdep (current_gdbarch)->debug_data_vaddr_trap_count)
253	#define DEBUG_INST_VADDR_TRAP_COUNT \
254	(gdbarch_tdep (current_gdbarch)->debug_inst_vaddr_trap_count)
255	#define ISA_MAX_INSN_SIZE \
256	(gdbarch_tdep (current_gdbarch)->isa_max_insn_size)
257	#define DEBUG_NUM_IBREAKS \
258	(gdbarch_tdep (current_gdbarch)->debug_num_ibreaks)
259	#define DEBUG_NUM_DBREAKS \
260	(gdbarch_tdep (current_gdbarch)->debug_num_dbreaks)
261
262	#define NUM_AREGS (gdbarch_tdep (current_gdbarch)->num_aregs)
263	#define WB_REGNUM (gdbarch_tdep (current_gdbarch)->wb_regnum)
264	#define WS_REGNUM (gdbarch_tdep (current_gdbarch)->ws_regnum)
265	#define LBEG_REGNUM (gdbarch_tdep (current_gdbarch)->lbeg_regnum)
266	#define LEND_REGNUM (gdbarch_tdep (current_gdbarch)->lend_regnum)
267	#define LCOUNT_REGNUM (gdbarch_tdep (current_gdbarch)->lcount_regnum)
268	#define SAR_REGNUM (gdbarch_tdep (current_gdbarch)->sar_regnum)
269	#define REGMAP (gdbarch_tdep (current_gdbarch)->regmap)
270
271	#define LITBASE_REGNUM (gdbarch_tdep (current_gdbarch)->litbase_regnum)
272	#define DEBUGCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->debugcause_regnum)
273	#define EXCCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->exccause_regnum)
274	#define EXCVADDR_REGNUM (gdbarch_tdep (current_gdbarch)->excvaddr_regnum)
275	#define NUM_IBREAKS (gdbarch_tdep (current_gdbarch)->num_ibreaks)
276	#define REGMAP_BYTES (gdbarch_tdep (current_gdbarch)->regmap_bytes)
277	#define A0_BASE (gdbarch_tdep (current_gdbarch)->a0_base)
278	#define AR_BASE (gdbarch_tdep (current_gdbarch)->ar_base)
f57d151a UW	279	#define FP_ALIAS \
	280	(gdbarch_num_regs (current_gdbarch) \
	281	+ gdbarch_num_pseudo_regs (current_gdbarch))
ca3bf3bd DJ	282	#define CALL_ABI (gdbarch_tdep (current_gdbarch)->call_abi)
	283	#define NUM_CONTEXTS (gdbarch_tdep (current_gdbarch)->num_contexts)
	284
	285	#define FP_LAYOUT (gdbarch_tdep (current_gdbarch)->fp_layout)
	286	#define FP_LAYOUT_BYTES (gdbarch_tdep (current_gdbarch)->fp_layout_bytes)
	287	#define GREGMAP (gdbarch_tdep (current_gdbarch)->gregmap)
	288
	289	#define AREGS_MASK (NUM_AREGS - 1)
	290	#define WB_MASK (AREGS_MASK >> 2)
	291	#define WB_SHIFT 2
	292
	293	/* We assign fixed numbers to the registers of the "current" window
	294	(i.e., relative to WB). The registers get remapped via the reg_map
	295	data structure to their corresponding register in the AR register
	296	file (see xtensa-tdep.c). */
	297
	298	#define A0_REGNUM (A0_BASE + 0)
	299	#define A1_REGNUM (A0_BASE + 1)
	300	#define A2_REGNUM (A0_BASE + 2)
	301	#define A3_REGNUM (A0_BASE + 3)
	302	#define A4_REGNUM (A0_BASE + 4)
	303	#define A5_REGNUM (A0_BASE + 5)
	304	#define A6_REGNUM (A0_BASE + 6)
	305	#define A7_REGNUM (A0_BASE + 7)
	306	#define A8_REGNUM (A0_BASE + 8)
	307	#define A9_REGNUM (A0_BASE + 9)
	308	#define A10_REGNUM (A0_BASE + 10)
	309	#define A11_REGNUM (A0_BASE + 11)
	310	#define A12_REGNUM (A0_BASE + 12)
	311	#define A13_REGNUM (A0_BASE + 13)
	312	#define A14_REGNUM (A0_BASE + 14)
	313	#define A15_REGNUM (A0_BASE + 15)
	314