[thirdparty/binutils-gdb.git] / gdbsupport / x86-xstate.h

/* Common code for x86 XSAVE extended state.

   Copyright (C) 2010-2023 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef COMMON_X86_XSTATE_H
#define COMMON_X86_XSTATE_H

/* The extended state feature IDs in the state component bitmap.  */
#define X86_XSTATE_X87_ID	0
#define X86_XSTATE_SSE_ID	1
#define X86_XSTATE_AVX_ID	2
#define X86_XSTATE_BNDREGS_ID	3
#define X86_XSTATE_BNDCFG_ID	4
#define X86_XSTATE_K_ID		5
#define X86_XSTATE_ZMM_H_ID	6
#define X86_XSTATE_ZMM_ID	7
#define X86_XSTATE_PKRU_ID	9

/* The extended state feature bits.  */
#define X86_XSTATE_X87		(1ULL << X86_XSTATE_X87_ID)
#define X86_XSTATE_SSE		(1ULL << X86_XSTATE_SSE_ID)
#define X86_XSTATE_AVX		(1ULL << X86_XSTATE_AVX_ID)
#define X86_XSTATE_BNDREGS	(1ULL << X86_XSTATE_BNDREGS_ID)
#define X86_XSTATE_BNDCFG	(1ULL << X86_XSTATE_BNDCFG_ID)
#define X86_XSTATE_MPX		(X86_XSTATE_BNDREGS | X86_XSTATE_BNDCFG)

/* AVX 512 adds three feature bits.  All three must be enabled.  */
#define X86_XSTATE_K		(1ULL << X86_XSTATE_K_ID)
#define X86_XSTATE_ZMM_H	(1ULL << X86_XSTATE_ZMM_H_ID)
#define X86_XSTATE_ZMM		(1ULL << X86_XSTATE_ZMM_ID)
#define X86_XSTATE_AVX512	(X86_XSTATE_K | X86_XSTATE_ZMM_H \
				 | X86_XSTATE_ZMM)

#define X86_XSTATE_PKRU		(1ULL << X86_XSTATE_PKRU_ID)

/* Total size of the XSAVE area extended region and offsets of
   register states within the region.  Offsets are set to 0 to
   indicate the absence of the associated registers.  */

struct x86_xsave_layout
{
  int sizeof_xsave = 0;
  int avx_offset = 0;
  int bndregs_offset = 0;
  int bndcfg_offset = 0;
  int k_offset = 0;
  int zmm_h_offset = 0;
  int zmm_offset = 0;
  int pkru_offset = 0;
};

constexpr bool operator== (const x86_xsave_layout &lhs,
			   const x86_xsave_layout &rhs)
{
  return lhs.sizeof_xsave == rhs.sizeof_xsave
    && lhs.avx_offset == rhs.avx_offset
    && lhs.bndregs_offset == rhs.bndregs_offset
    && lhs.bndcfg_offset == rhs.bndcfg_offset
    && lhs.k_offset == rhs.k_offset
    && lhs.zmm_h_offset == rhs.zmm_h_offset
    && lhs.zmm_offset == rhs.zmm_offset
    && lhs.pkru_offset == rhs.pkru_offset;
}

constexpr bool operator!= (const x86_xsave_layout &lhs,
			   const x86_xsave_layout &rhs)
{
  return !(lhs == rhs);
}


/* Supported mask and size of the extended state.  */
#define X86_XSTATE_X87_MASK	X86_XSTATE_X87
#define X86_XSTATE_SSE_MASK	(X86_XSTATE_X87 | X86_XSTATE_SSE)
#define X86_XSTATE_AVX_MASK	(X86_XSTATE_SSE_MASK | X86_XSTATE_AVX)
#define X86_XSTATE_MPX_MASK	(X86_XSTATE_SSE_MASK | X86_XSTATE_MPX)
#define X86_XSTATE_AVX_MPX_MASK	(X86_XSTATE_AVX_MASK | X86_XSTATE_MPX)
#define X86_XSTATE_AVX_AVX512_MASK	(X86_XSTATE_AVX_MASK | X86_XSTATE_AVX512)
#define X86_XSTATE_AVX_MPX_AVX512_PKU_MASK 	(X86_XSTATE_AVX_MPX_MASK\
					| X86_XSTATE_AVX512 | X86_XSTATE_PKRU)

#define X86_XSTATE_ALL_MASK		(X86_XSTATE_AVX_MPX_AVX512_PKU_MASK)


#define X86_XSTATE_SSE_SIZE	576
#define X86_XSTATE_AVX_SIZE	832


/* In case one of the MPX XCR0 bits is set we consider we have MPX.  */
#define HAS_MPX(XCR0) (((XCR0) & X86_XSTATE_MPX) != 0)
#define HAS_AVX(XCR0) (((XCR0) & X86_XSTATE_AVX) != 0)
#define HAS_AVX512(XCR0) (((XCR0) & X86_XSTATE_AVX512) != 0)
#define HAS_PKRU(XCR0) (((XCR0) & X86_XSTATE_PKRU) != 0)

/* Initial value for fctrl register, as defined in the X86 manual, and
   confirmed in the (Linux) kernel source.  When the x87 floating point
   feature is not enabled in an inferior we use this as the value of the
   fcrtl register.  */

#define I387_FCTRL_INIT_VAL 0x037f

/* Initial value for mxcsr register.  When the avx and sse floating point
   features are not enabled in an inferior we use this as the value of the
   mxcsr register.  */

#define I387_MXCSR_INIT_VAL 0x1f80

#endif /* COMMON_X86_XSTATE_H */
Commit	Line	Data
df7e5265 GB	1	/* Common code for x86 XSAVE extended state.
df7e5265 GB	2
213516ef	3	Copyright (C) 2010-2023 Free Software Foundation, Inc.
df7e5265 GB	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	19
1a5c2598 TT	20	#ifndef COMMON_X86_XSTATE_H
1a5c2598 TT	21	#define COMMON_X86_XSTATE_H
df7e5265	22
d39b60f2 JB	23	/* The extended state feature IDs in the state component bitmap. */
	24	#define X86_XSTATE_X87_ID 0
	25	#define X86_XSTATE_SSE_ID 1
	26	#define X86_XSTATE_AVX_ID 2
	27	#define X86_XSTATE_BNDREGS_ID 3
	28	#define X86_XSTATE_BNDCFG_ID 4
	29	#define X86_XSTATE_K_ID 5
	30	#define X86_XSTATE_ZMM_H_ID 6
	31	#define X86_XSTATE_ZMM_ID 7
	32	#define X86_XSTATE_PKRU_ID 9
	33
df7e5265	34	/* The extended state feature bits. */
d39b60f2 JB	35	#define X86_XSTATE_X87 (1ULL << X86_XSTATE_X87_ID)
	36	#define X86_XSTATE_SSE (1ULL << X86_XSTATE_SSE_ID)
	37	#define X86_XSTATE_AVX (1ULL << X86_XSTATE_AVX_ID)
	38	#define X86_XSTATE_BNDREGS (1ULL << X86_XSTATE_BNDREGS_ID)
	39	#define X86_XSTATE_BNDCFG (1ULL << X86_XSTATE_BNDCFG_ID)
df7e5265 GB	40	#define X86_XSTATE_MPX (X86_XSTATE_BNDREGS \| X86_XSTATE_BNDCFG)
	41
	42	/* AVX 512 adds three feature bits. All three must be enabled. */
d39b60f2 JB	43	#define X86_XSTATE_K (1ULL << X86_XSTATE_K_ID)
	44	#define X86_XSTATE_ZMM_H (1ULL << X86_XSTATE_ZMM_H_ID)
	45	#define X86_XSTATE_ZMM (1ULL << X86_XSTATE_ZMM_ID)
df7e5265 GB	46	#define X86_XSTATE_AVX512 (X86_XSTATE_K \| X86_XSTATE_ZMM_H \
	47	\| X86_XSTATE_ZMM)
	48
d39b60f2 JB	49	#define X86_XSTATE_PKRU (1ULL << X86_XSTATE_PKRU_ID)
	50
	51	/* Total size of the XSAVE area extended region and offsets of
	52	register states within the region. Offsets are set to 0 to
	53	indicate the absence of the associated registers. */
	54
	55	struct x86_xsave_layout
	56	{
	57	int sizeof_xsave = 0;
	58	int avx_offset = 0;
	59	int bndregs_offset = 0;
	60	int bndcfg_offset = 0;
	61	int k_offset = 0;
	62	int zmm_h_offset = 0;
	63	int zmm_offset = 0;
	64	int pkru_offset = 0;
	65	};
	66
	67	constexpr bool operator== (const x86_xsave_layout &lhs,
	68	const x86_xsave_layout &rhs)
	69	{
	70	return lhs.sizeof_xsave == rhs.sizeof_xsave
	71	&& lhs.avx_offset == rhs.avx_offset
	72	&& lhs.bndregs_offset == rhs.bndregs_offset
	73	&& lhs.bndcfg_offset == rhs.bndcfg_offset
	74	&& lhs.k_offset == rhs.k_offset
	75	&& lhs.zmm_h_offset == rhs.zmm_h_offset
	76	&& lhs.zmm_offset == rhs.zmm_offset
	77	&& lhs.pkru_offset == rhs.pkru_offset;
	78	}
	79
	80	constexpr bool operator!= (const x86_xsave_layout &lhs,
	81	const x86_xsave_layout &rhs)
	82	{
	83	return !(lhs == rhs);
	84	}
	85
51547df6	86
df7e5265 GB	87	/* Supported mask and size of the extended state. */
	88	#define X86_XSTATE_X87_MASK X86_XSTATE_X87
	89	#define X86_XSTATE_SSE_MASK (X86_XSTATE_X87 \| X86_XSTATE_SSE)
	90	#define X86_XSTATE_AVX_MASK (X86_XSTATE_SSE_MASK \| X86_XSTATE_AVX)
2b863f51 WT	91	#define X86_XSTATE_MPX_MASK (X86_XSTATE_SSE_MASK \| X86_XSTATE_MPX)
2b863f51 WT	92	#define X86_XSTATE_AVX_MPX_MASK (X86_XSTATE_AVX_MASK \| X86_XSTATE_MPX)
22049425	93	#define X86_XSTATE_AVX_AVX512_MASK (X86_XSTATE_AVX_MASK \| X86_XSTATE_AVX512)
51547df6 MS	94	#define X86_XSTATE_AVX_MPX_AVX512_PKU_MASK (X86_XSTATE_AVX_MPX_MASK\
	95	\| X86_XSTATE_AVX512 \| X86_XSTATE_PKRU)
	96
	97	#define X86_XSTATE_ALL_MASK (X86_XSTATE_AVX_MPX_AVX512_PKU_MASK)
df7e5265	98
df7e5265 GB	99
	100	#define X86_XSTATE_SSE_SIZE 576
	101	#define X86_XSTATE_AVX_SIZE 832
df7e5265 GB	102
	103
	104	/* In case one of the MPX XCR0 bits is set we consider we have MPX. */
	105	#define HAS_MPX(XCR0) (((XCR0) & X86_XSTATE_MPX) != 0)
	106	#define HAS_AVX(XCR0) (((XCR0) & X86_XSTATE_AVX) != 0)
	107	#define HAS_AVX512(XCR0) (((XCR0) & X86_XSTATE_AVX512) != 0)
51547df6	108	#define HAS_PKRU(XCR0) (((XCR0) & X86_XSTATE_PKRU) != 0)
df7e5265	109
8ee22052 AB	110	/* Initial value for fctrl register, as defined in the X86 manual, and
	111	confirmed in the (Linux) kernel source. When the x87 floating point
	112	feature is not enabled in an inferior we use this as the value of the
	113	fcrtl register. */
	114
	115	#define I387_FCTRL_INIT_VAL 0x037f
	116
	117	/* Initial value for mxcsr register. When the avx and sse floating point
	118	features are not enabled in an inferior we use this as the value of the
	119	mxcsr register. */
	120
	121	#define I387_MXCSR_INIT_VAL 0x1f80
	122
1a5c2598	123	#endif /* COMMON_X86_XSTATE_H */