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Opcodes: (BRCLR / BRSET) Disassemble reserved codes instead of aborting.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f4107842
JD		 12018-07-28 John Darrington <john@darrington.wattle.id.au>
2
3 * s12z-dis.c (bm_decode): Deal with cases where the mode is BM_RESERVED0 or BM_RESERVED1
4 * s12z-dis.c (bm_rel_decode): ditto
5 * s12z-dis.c (bm_n_bytes): ditto
6
7ba3ba91
JD		 72018-07-28 John Darrington <john@darrington.wattle.id.au>
8
9 * s12z.h: Delete.
10
1bc60e56
L		 112018-08-14 H.J. Lu <hongjiu.lu@intel.com>
12
13 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
14 address with the addr32 prefix and without base nor index
15 registers.
16
d871f3f4
L		 172018-08-11 H.J. Lu <hongjiu.lu@intel.com>
18
19 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
20 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
21 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
22 (cpu_flags): Add CpuCMOV and CpuFXSR.
23 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
24 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
25 * i386-init.h: Regenerated.
26 * i386-tbl.h: Likewise.
27
b6523c37 282018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
29
30 * arc-regs.h: Update auxiliary registers.
31
e968fc9b
JB		 322018-08-06 Jan Beulich <jbeulich@suse.com>
33
34 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
35 (RegIP, RegIZ): Define.
36 * i386-reg.tbl: Adjust comments.
37 (rip): Use Qword instead of BaseIndex. Use RegIP.
38 (eip): Use Dword instead of BaseIndex. Use RegIP.
39 (riz): Add Qword. Use RegIZ.
40 (eiz): Add Dword. Use RegIZ.
41 * i386-tbl.h: Re-generate.
42
dbf8be89
JB		 432018-08-03 Jan Beulich <jbeulich@suse.com>
44
45 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
46 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
47 vpmovzxdq, vpmovzxwd): Remove NoRex64.
48 * i386-tbl.h: Re-generate.
49
c48dadc9
JB		 502018-08-03 Jan Beulich <jbeulich@suse.com>
51
52 * i386-gen.c (operand_types): Remove Mem field.
53 * i386-opc.h (union i386_operand_type): Remove mem field.
54 * i386-init.h, i386-tbl.h: Re-generate.
55
cb86a42a
AM		 562018-08-01 Alan Modra <amodra@gmail.com>
57
58 * po/POTFILES.in: Regenerate.
59
07cc0450
NC		 602018-07-31 Nick Clifton <nickc@redhat.com>
61
62 * po/sv.po: Updated Swedish translation.
63
1424ad86
JB		 642018-07-31 Jan Beulich <jbeulich@suse.com>
65
66 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
67 * i386-init.h, i386-tbl.h: Re-generate.
68
ae2387fe
JB		 692018-07-31 Jan Beulich <jbeulich@suse.com>
70
71 * i386-opc.h (ZEROING_MASKING) Rename to ...
72 (DYNAMIC_MASKING): ... this. Adjust comment.
73 * i386-opc.tbl (MaskingMorZ): Define.
74 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
75 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
76 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
77 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
78 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
79 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
80 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
81 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
82 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
83
6ff00b5e
JB		 842018-07-31 Jan Beulich <jbeulich@suse.com>
85
86 * i386-opc.tbl: Use element rather than vector size for AVX512*
87 scatter/gather insns.
88 * i386-tbl.h: Re-generate.
89
e951d5ca
JB		 902018-07-31 Jan Beulich <jbeulich@suse.com>
91
92 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
93 (cpu_flags): Drop CpuVREX.
94 * i386-opc.h (CpuVREX): Delete.
95 (union i386_cpu_flags): Remove cpuvrex.
96 * i386-init.h, i386-tbl.h: Re-generate.
97
eb41b248
JW		 982018-07-30 Jim Wilson <jimw@sifive.com>
99
100 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
101 fields.
102 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
103
b8891f8d
AJ		 1042018-07-30 Andrew Jenner <andrew@codesourcery.com>
105
106 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
107 * Makefile.in: Regenerated.
108 * configure.ac: Add C-SKY.
109 * configure: Regenerated.
110 * csky-dis.c: New file.
111 * csky-opc.h: New file.
112 * disassemble.c (ARCH_csky): Define.
113 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
114 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
115
16065af1
AM		 1162018-07-27 Alan Modra <amodra@gmail.com>
117
118 * ppc-opc.c (insert_sprbat): Correct function parameter and
119 return type.
120 (extract_sprbat): Likewise, variable too.
121
fa758a70
AC		 1222018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
123 Alan Modra <amodra@gmail.com>
124
125 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
126 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
127 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
128 support disjointed BAT.
129 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
130 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
131 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
132
4a1b91ea
L		 1332018-07-25 H.J. Lu <hongjiu.lu@intel.com>
134 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
135
136 * i386-gen.c (adjust_broadcast_modifier): New function.
137 (process_i386_opcode_modifier): Add an argument for operands.
138 Adjust the Broadcast value based on operands.
139 (output_i386_opcode): Pass operand_types to
140 process_i386_opcode_modifier.
141 (process_i386_opcodes): Pass NULL as operands to
142 process_i386_opcode_modifier.
143 * i386-opc.h (BYTE_BROADCAST): New.
144 (WORD_BROADCAST): Likewise.
145 (DWORD_BROADCAST): Likewise.
146 (QWORD_BROADCAST): Likewise.
147 (i386_opcode_modifier): Expand broadcast to 3 bits.
148 * i386-tbl.h: Regenerated.
149
67ce483b
AM		 1502018-07-24 Alan Modra <amodra@gmail.com>
151
152 PR 23430
153 * or1k-desc.h: Regenerate.
154
4174bfff
JB		 1552018-07-24 Jan Beulich <jbeulich@suse.com>
156
157 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
158 vcvtusi2ss, and vcvtusi2sd.
159 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
160 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
161 * i386-tbl.h: Re-generate.
162
04e65276
CZ		 1632018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
164
165 * arc-opc.c (extract_w6): Fix extending the sign.
166
47e6f81c
CZ		 1672018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
168
169 * arc-tbl.h (vewt): Allow it for ARC EM family.
170
bb71536f
AM		 1712018-07-23 Alan Modra <amodra@gmail.com>
172
173 PR 23419
174 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
175 opcode variants for mtspr/mfspr encodings.
176
8095d2f7
CX		 1772018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
178 Maciej W. Rozycki <macro@mips.com>
179
180 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
181 loongson3a descriptors.
182 (parse_mips_ase_option): Handle -M loongson-mmi option.
183 (print_mips_disassembler_options): Document -M loongson-mmi.
184 * mips-opc.c (LMMI): New macro.
185 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
186 instructions.
187
5f32791e
JB		 1882018-07-19 Jan Beulich <jbeulich@suse.com>
189
190 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
191 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
192 IgnoreSize and [XYZ]MMword where applicable.
193 * i386-tbl.h: Re-generate.
194
625cbd7a
JB		 1952018-07-19 Jan Beulich <jbeulich@suse.com>
196
197 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
198 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
199 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
200 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
201 * i386-tbl.h: Re-generate.
202
86b15c32
JB		 2032018-07-19 Jan Beulich <jbeulich@suse.com>
204
205 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
206 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
207 VPCLMULQDQ templates into their respective AVX512VL counterparts
208 where possible, using Disp8ShiftVL and CheckRegSize instead of
209 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
210 * i386-tbl.h: Re-generate.
211
cf769ed5
JB		 2122018-07-19 Jan Beulich <jbeulich@suse.com>
213
214 * i386-opc.tbl: Fold AVX512DQ templates into their respective
215 AVX512VL counterparts where possible, using Disp8ShiftVL and
216 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
217 IgnoreSize) as appropriate.
218 * i386-tbl.h: Re-generate.
219
8282b7ad
JB		 2202018-07-19 Jan Beulich <jbeulich@suse.com>
221
222 * i386-opc.tbl: Fold AVX512BW templates into their respective
223 AVX512VL counterparts where possible, using Disp8ShiftVL and
224 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
225 IgnoreSize) as appropriate.
226 * i386-tbl.h: Re-generate.
227
755908cc
JB		 2282018-07-19 Jan Beulich <jbeulich@suse.com>
229
230 * i386-opc.tbl: Fold AVX512CD templates into their respective
231 AVX512VL counterparts where possible, using Disp8ShiftVL and
232 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
233 IgnoreSize) as appropriate.
234 * i386-tbl.h: Re-generate.
235
7091c612
JB		 2362018-07-19 Jan Beulich <jbeulich@suse.com>
237
238 * i386-opc.h (DISP8_SHIFT_VL): New.
239 * i386-opc.tbl (Disp8ShiftVL): Define.
240 (various): Fold AVX512VL templates into their respective
241 AVX512F counterparts where possible, using Disp8ShiftVL and
242 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
243 IgnoreSize) as appropriate.
244 * i386-tbl.h: Re-generate.
245
c30be56e
JB		 2462018-07-19 Jan Beulich <jbeulich@suse.com>
247
248 * Makefile.am: Change dependencies and rule for
249 $(srcdir)/i386-init.h.
250 * Makefile.in: Re-generate.
251 * i386-gen.c (process_i386_opcodes): New local variable
252 "marker". Drop opening of input file. Recognize marker and line
253 number directives.
254 * i386-opc.tbl (OPCODE_I386_H): Define.
255 (i386-opc.h): Include it.
256 (None): Undefine.
257
11a322db
L		 2582018-07-18 H.J. Lu <hongjiu.lu@intel.com>
259
260 PR gas/23418
261 * i386-opc.h (Byte): Update comments.
262 (Word): Likewise.
263 (Dword): Likewise.
264 (Fword): Likewise.
265 (Qword): Likewise.
266 (Tbyte): Likewise.
267 (Xmmword): Likewise.
268 (Ymmword): Likewise.
269 (Zmmword): Likewise.
270 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
271 vcvttps2uqq.
272 * i386-tbl.h: Regenerated.
273
cde3679e
NC		 2742018-07-12 Sudakshina Das <sudi.das@arm.com>
275
276 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
277 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
278 * aarch64-asm-2.c: Regenerate.
279 * aarch64-dis-2.c: Regenerate.
280 * aarch64-opc-2.c: Regenerate.
281
45a28947
TC		 2822018-07-12 Tamar Christina <tamar.christina@arm.com>
283
284 PR binutils/23192
285 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
286 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
287 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
288 sqdmulh, sqrdmulh): Use Em16.
289
c597cc3d
SD		 2902018-07-11 Sudakshina Das <sudi.das@arm.com>
291
292 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
293 csdb together with them.
294 (thumb32_opcodes): Likewise.
295
a79eaed6
JB		 2962018-07-11 Jan Beulich <jbeulich@suse.com>
297
298 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
299 requiring 32-bit registers as operands 2 and 3. Improve
300 comments.
301 (mwait, mwaitx): Fold templates. Improve comments.
302 OPERAND_TYPE_INOUTPORTREG.
303 * i386-tbl.h: Re-generate.
304
2fb5be8d
JB		 3052018-07-11 Jan Beulich <jbeulich@suse.com>
306
307 * i386-gen.c (operand_type_init): Remove
308 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
309 OPERAND_TYPE_INOUTPORTREG.
310 * i386-init.h: Re-generate.
311
7f5cad30
JB		 3122018-07-11 Jan Beulich <jbeulich@suse.com>
313
314 * i386-opc.tbl (wrssd, wrussd): Add Dword.
315 (wrssq, wrussq): Add Qword.
316 * i386-tbl.h: Re-generate.
317
f0a85b07
JB		 3182018-07-11 Jan Beulich <jbeulich@suse.com>
319
320 * i386-opc.h: Rename OTMax to OTNum.
321 (OTNumOfUints): Adjust calculation.
322 (OTUnused): Directly alias to OTNum.
323
9dcb0ba4
MR		 3242018-07-09 Maciej W. Rozycki <macro@mips.com>
325
326 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
327 `reg_xys'.
328 (lea_reg_xys): Likewise.
329 (print_insn_loop_primitive): Rename `reg' local variable to
330 `reg_dxy'.
331
f311ba7e
TC		 3322018-07-06 Tamar Christina <tamar.christina@arm.com>
333
334 PR binutils/23242
335 * aarch64-tbl.h (ldarh): Fix disassembly mask.
336
cba05feb
TC		 3372018-07-06 Tamar Christina <tamar.christina@arm.com>
338
339 PR binutils/23369
340 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
341 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
342
471b9d15
MR		 3432018-07-02 Maciej W. Rozycki <macro@mips.com>
344
345 PR tdep/8282
346 * mips-dis.c (mips_option_arg_t): New enumeration.
347 (mips_options): New variable.
348 (disassembler_options_mips): New function.
349 (print_mips_disassembler_options): Reimplement in terms of
350 `disassembler_options_mips'.
351 * arm-dis.c (disassembler_options_arm): Adapt to using the
352 `disasm_options_and_args_t' structure.
353 * ppc-dis.c (disassembler_options_powerpc): Likewise.
354 * s390-dis.c (disassembler_options_s390): Likewise.
355
c0c468d5
TP		 3562018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
357
358 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
359 expected result.
360 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
361 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
362 * testsuite/ld-arm/tls-longplt.d: Likewise.
363
369c9167
TC		 3642018-06-29 Tamar Christina <tamar.christina@arm.com>
365
366 PR binutils/23192
367 * aarch64-asm-2.c: Regenerate.
368 * aarch64-dis-2.c: Likewise.
369 * aarch64-opc-2.c: Likewise.
370 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
371 * aarch64-opc.c (operand_general_constraint_met_p,
372 aarch64_print_operand): Likewise.
373 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
374 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
375 fmlal2, fmlsl2.
376 (AARCH64_OPERANDS): Add Em2.
377
30aa1306
NC		 3782018-06-26 Nick Clifton <nickc@redhat.com>
379
380 * po/uk.po: Updated Ukranian translation.
381 * po/de.po: Updated German translation.
382 * po/pt_BR.po: Updated Brazilian Portuguese translation.
383
eca4b721
NC		 3842018-06-26 Nick Clifton <nickc@redhat.com>
385
386 * nfp-dis.c: Fix spelling mistake.
387
71300e2c
NC		 3882018-06-24 Nick Clifton <nickc@redhat.com>
389
390 * configure: Regenerate.
391 * po/opcodes.pot: Regenerate.
392
719d8288
NC		 3932018-06-24 Nick Clifton <nickc@redhat.com>
394
395 2.31 branch created.
396
514cd3a0
TC		 3972018-06-19 Tamar Christina <tamar.christina@arm.com>
398
399 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
400 * aarch64-asm-2.c: Regenerate.
401 * aarch64-dis-2.c: Likewise.
402
385e4d0f
MR		 4032018-06-21 Maciej W. Rozycki <macro@mips.com>
404
405 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
406 `-M ginv' option description.
407
160d1b3d
SH		 4082018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
409
410 PR gas/23305
411 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
412 la and lla.
413
d0ac1c44
SM		 4142018-06-19 Simon Marchi <simon.marchi@ericsson.com>
415
416 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
417 * configure.ac: Remove AC_PREREQ.
418 * Makefile.in: Re-generate.
419 * aclocal.m4: Re-generate.
420 * configure: Re-generate.
421
6f20c942
FS		 4222018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
423
424 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
425 mips64r6 descriptors.
426 (parse_mips_ase_option): Handle -Mginv option.
427 (print_mips_disassembler_options): Document -Mginv.
428 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
429 (GINV): New macro.
430 (mips_opcodes): Define ginvi and ginvt.
431
730c3174
SE		 4322018-06-13 Scott Egerton <scott.egerton@imgtec.com>
433 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
434
435 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
436 * mips-opc.c (CRC, CRC64): New macros.
437 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
438 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
439 crc32cd for CRC64.
440
cb366992
EB		 4412018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
442
443 PR 20319
444 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
445 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
446
ce72cd46
AM		 4472018-06-06 Alan Modra <amodra@gmail.com>
448
449 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
450 setjmp. Move init for some other vars later too.
451
4b8e28c7
MF		 4522018-06-04 Max Filippov <jcmvbkbc@gmail.com>
453
454 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
455 (dis_private): Add new fields for property section tracking.
456 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
457 (xtensa_instruction_fits): New functions.
458 (fetch_data): Bump minimal fetch size to 4.
459 (print_insn_xtensa): Make struct dis_private static.
460 Load and prepare property table on section change.
461 Don't disassemble literals. Don't disassemble instructions that
462 cross property table boundaries.
463
55e99962
L		 4642018-06-01 H.J. Lu <hongjiu.lu@intel.com>
465
466 * configure: Regenerated.
467
733bd0ab
JB		 4682018-06-01 Jan Beulich <jbeulich@suse.com>
469
470 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
471 * i386-tbl.h: Re-generate.
472
dfd27d41
JB		 4732018-06-01 Jan Beulich <jbeulich@suse.com>
474
475 * i386-opc.tbl (sldt, str): Add NoRex64.
476 * i386-tbl.h: Re-generate.
477
64795710
JB		 4782018-06-01 Jan Beulich <jbeulich@suse.com>
479
480 * i386-opc.tbl (invpcid): Add Oword.
481 * i386-tbl.h: Re-generate.
482
030157d8
AM		 4832018-06-01 Alan Modra <amodra@gmail.com>
484
485 * sysdep.h (_bfd_error_handler): Don't declare.
486 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
487 * rl78-decode.opc: Likewise.
488 * msp430-decode.c: Regenerate.
489 * rl78-decode.c: Regenerate.
490
a9660a6f
AP		 4912018-05-30 Amit Pawar <Amit.Pawar@amd.com>
492
493 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
494 * i386-init.h : Regenerated.
495
277eb7f6
AM		 4962018-05-25 Alan Modra <amodra@gmail.com>
497
498 * Makefile.in: Regenerate.
499 * po/POTFILES.in: Regenerate.
500
98553ad3
PB		 5012018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
502
503 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
504 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
505 (insert_bab, extract_bab, insert_btab, extract_btab,
506 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
507 (BAT, BBA VBA RBS XB6S): Delete macros.
508 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
509 (BB, BD, RBX, XC6): Update for new macros.
510 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
511 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
512 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
513 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
514
7b4ae824
JD		 5152018-05-18 John Darrington <john@darrington.wattle.id.au>
516
517 * Makefile.am: Add support for s12z architecture.
518 * configure.ac: Likewise.
519 * disassemble.c: Likewise.
520 * disassemble.h: Likewise.
521 * Makefile.in: Regenerate.
522 * configure: Regenerate.
523 * s12z-dis.c: New file.
524 * s12z.h: New file.
525
29e0f0a1
AM		 5262018-05-18 Alan Modra <amodra@gmail.com>
527
528 * nfp-dis.c: Don't #include libbfd.h.
529 (init_nfp3200_priv): Use bfd_get_section_contents.
530 (nit_nfp6000_mecsr_sec): Likewise.
531
809276d2
NC		 5322018-05-17 Nick Clifton <nickc@redhat.com>
533
534 * po/zh_CN.po: Updated simplified Chinese translation.
535
ff329288
TC		 5362018-05-16 Tamar Christina <tamar.christina@arm.com>
537
538 PR binutils/23109
539 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
540 * aarch64-dis-2.c: Regenerate.
541
f9830ec1
TC		 5422018-05-15 Tamar Christina <tamar.christina@arm.com>
543
544 PR binutils/21446
545 * aarch64-asm.c (opintl.h): Include.
546 (aarch64_ins_sysreg): Enforce read/write constraints.
547 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
548 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
549 (F_REG_READ, F_REG_WRITE): New.
550 * aarch64-opc.c (aarch64_print_operand): Generate notes for
551 AARCH64_OPND_SYSREG.
552 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
553 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
554 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
555 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
556 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
557 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
558 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
559 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
560 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
561 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
562 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
563 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
564 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
565 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
566 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
567 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
568 msr (F_SYS_WRITE), mrs (F_SYS_READ).
569
7d02540a
TC		 5702018-05-15 Tamar Christina <tamar.christina@arm.com>
571
572 PR binutils/21446
573 * aarch64-dis.c (no_notes: New.
574 (parse_aarch64_dis_option): Support notes.
575 (aarch64_decode_insn, print_operands): Likewise.
576 (print_aarch64_disassembler_options): Document notes.
577 * aarch64-opc.c (aarch64_print_operand): Support notes.
578
561a72d4
TC		 5792018-05-15 Tamar Christina <tamar.christina@arm.com>
580
581 PR binutils/21446
582 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
583 and take error struct.
584 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
585 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
586 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
587 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
588 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
589 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
590 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
591 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
592 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
593 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
594 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
595 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
596 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
597 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
598 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
599 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
600 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
601 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
602 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
603 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
604 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
605 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
606 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
607 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
608 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
609 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
610 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
611 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
612 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
613 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
614 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
615 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
616 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
617 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
618 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
619 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
620 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
621 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
622 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
623 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
624 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
625 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
626 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
627 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
628 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
629 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
630 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
631 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
632 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
633 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
634 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
635 (determine_disassembling_preference, aarch64_decode_insn,
636 print_insn_aarch64_word, print_insn_data): Take errors struct.
637 (print_insn_aarch64): Use errors.
638 * aarch64-asm-2.c: Regenerate.
639 * aarch64-dis-2.c: Regenerate.
640 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
641 boolean in aarch64_insert_operan.
642 (print_operand_extractor): Likewise.
643 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
644
1678bd35
FT		 6452018-05-15 Francois H. Theron <francois.theron@netronome.com>
646
647 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
648
06cfb1c8
L		 6492018-05-09 H.J. Lu <hongjiu.lu@intel.com>
650
651 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
652
84f9f8c3
AM		 6532018-05-09 Sebastian Rasmussen <sebras@gmail.com>
654
655 * cr16-opc.c (cr16_instruction): Comment typo fix.
656 * hppa-dis.c (print_insn_hppa): Likewise.
657
e6f372ba
JW		 6582018-05-08 Jim Wilson <jimw@sifive.com>
659
660 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
661 (match_c_slli64, match_srxi_as_c_srxi): New.
662 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
663 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
664 <c.slli, c.srli, c.srai>: Use match_s_slli.
665 <c.slli64, c.srli64, c.srai64>: New.
666
f413a913
AM		 6672018-05-08 Alan Modra <amodra@gmail.com>
668
669 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
670 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
671 partition opcode space for index lookup.
672
a87a6478
PB		 6732018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
674
675 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
676 <insn_length>: ...with this. Update usage.
677 Remove duplicate call to *info->memory_error_func.
678
c0a30a9f
L		 6792018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
680 H.J. Lu <hongjiu.lu@intel.com>
681
682 * i386-dis.c (Gva): New.
683 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
684 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
685 (prefix_table): New instructions (see prefix above).
686 (mod_table): New instructions (see prefix above).
687 (OP_G): Handle va_mode.
688 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
689 CPU_MOVDIR64B_FLAGS.
690 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
691 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
692 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
693 * i386-opc.tbl: Add movidir{i,64b}.
694 * i386-init.h: Regenerated.
695 * i386-tbl.h: Likewise.
696
75c0a438
L		 6972018-05-07 H.J. Lu <hongjiu.lu@intel.com>
698
699 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
700 AddrPrefixOpReg.
701 * i386-opc.h (AddrPrefixOp0): Renamed to ...
702 (AddrPrefixOpReg): This.
703 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
704 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
705
2ceb7719
PB		 7062018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
707
708 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
709 (vle_num_opcodes): Likewise.
710 (spe2_num_opcodes): Likewise.
711 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
712 initialization loop.
713 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
714 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
715 only once.
716
b3ac5c6c
TC		 7172018-05-01 Tamar Christina <tamar.christina@arm.com>
718
719 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
720
fe944acf
FT		 7212018-04-30 Francois H. Theron <francois.theron@netronome.com>
722
723 Makefile.am: Added nfp-dis.c.
724 configure.ac: Added bfd_nfp_arch.
725 disassemble.h: Added print_insn_nfp prototype.
726 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
727 nfp-dis.c: New, for NFP support.
728 po/POTFILES.in: Added nfp-dis.c to the list.
729 Makefile.in: Regenerate.
730 configure: Regenerate.
731
e2195274
JB		 7322018-04-26 Jan Beulich <jbeulich@suse.com>
733
734 * i386-opc.tbl: Fold various non-memory operand AVX512VL
735 templates into their base ones.
736 * i386-tlb.h: Re-generate.
737
59ef5df4
JB		 7382018-04-26 Jan Beulich <jbeulich@suse.com>
739
740 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
741 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
742 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
743 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
744 * i386-init.h: Re-generate.
745
6e041cf4
JB		 7462018-04-26 Jan Beulich <jbeulich@suse.com>
747
748 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
749 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
750 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
751 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
752 comment.
753 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
754 and CpuRegMask.
755 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
756 CpuRegMask: Delete.
757 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
758 cpuregzmm, and cpuregmask.
759 * i386-init.h: Re-generate.
760 * i386-tbl.h: Re-generate.
761
0e0eea78
JB		 7622018-04-26 Jan Beulich <jbeulich@suse.com>
763
764 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
765 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
766 * i386-init.h: Re-generate.
767
2f1bada2
JB		 7682018-04-26 Jan Beulich <jbeulich@suse.com>
769
770 * i386-gen.c (VexImmExt): Delete.
771 * i386-opc.h (VexImmExt, veximmext): Delete.
772 * i386-opc.tbl: Drop all VexImmExt uses.
773 * i386-tlb.h: Re-generate.
774
bacd1457
JB		 7752018-04-25 Jan Beulich <jbeulich@suse.com>
776
777 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
778 register-only forms.
779 * i386-tlb.h: Re-generate.
780
10bba94b
TC		 7812018-04-25 Tamar Christina <tamar.christina@arm.com>
782
783 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
784
c48935d7
IT		 7852018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
786
787 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
788 PREFIX_0F1C.
789 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
790 (cpu_flags): Add CpuCLDEMOTE.
791 * i386-init.h: Regenerate.
792 * i386-opc.h (enum): Add CpuCLDEMOTE,
793 (i386_cpu_flags): Add cpucldemote.
794 * i386-opc.tbl: Add cldemote.
795 * i386-tbl.h: Regenerate.
796
211dc24b
AM		 7972018-04-16 Alan Modra <amodra@gmail.com>
798
799 * Makefile.am: Remove sh5 and sh64 support.
800 * configure.ac: Likewise.
801 * disassemble.c: Likewise.
802 * disassemble.h: Likewise.
803 * sh-dis.c: Likewise.
804 * sh64-dis.c: Delete.
805 * sh64-opc.c: Delete.
806 * sh64-opc.h: Delete.
807 * Makefile.in: Regenerate.
808 * configure: Regenerate.
809 * po/POTFILES.in: Regenerate.
810
a9a4b302
AM		 8112018-04-16 Alan Modra <amodra@gmail.com>
812
813 * Makefile.am: Remove w65 support.
814 * configure.ac: Likewise.
815 * disassemble.c: Likewise.
816 * disassemble.h: Likewise.
817 * w65-dis.c: Delete.
818 * w65-opc.h: Delete.
819 * Makefile.in: Regenerate.
820 * configure: Regenerate.
821 * po/POTFILES.in: Regenerate.
822
04cb01fd
AM		 8232018-04-16 Alan Modra <amodra@gmail.com>
824
825 * configure.ac: Remove we32k support.
826 * configure: Regenerate.
827
c2bf1eec
AM		 8282018-04-16 Alan Modra <amodra@gmail.com>
829
830 * Makefile.am: Remove m88k support.
831 * configure.ac: Likewise.
832 * disassemble.c: Likewise.
833 * disassemble.h: Likewise.
834 * m88k-dis.c: Delete.
835 * Makefile.in: Regenerate.
836 * configure: Regenerate.
837 * po/POTFILES.in: Regenerate.
838
6793974d
AM		 8392018-04-16 Alan Modra <amodra@gmail.com>
840
841 * Makefile.am: Remove i370 support.
842 * configure.ac: Likewise.
843 * disassemble.c: Likewise.
844 * disassemble.h: Likewise.
845 * i370-dis.c: Delete.
846 * i370-opc.c: Delete.
847 * Makefile.in: Regenerate.
848 * configure: Regenerate.
849 * po/POTFILES.in: Regenerate.
850
e82aa794
AM		 8512018-04-16 Alan Modra <amodra@gmail.com>
852
853 * Makefile.am: Remove h8500 support.
854 * configure.ac: Likewise.
855 * disassemble.c: Likewise.
856 * disassemble.h: Likewise.
857 * h8500-dis.c: Delete.
858 * h8500-opc.h: Delete.
859 * Makefile.in: Regenerate.
860 * configure: Regenerate.
861 * po/POTFILES.in: Regenerate.
862
fceadf09
AM		 8632018-04-16 Alan Modra <amodra@gmail.com>
864
865 * configure.ac: Remove tahoe support.
866 * configure: Regenerate.
867
ae1d3843
L		 8682018-04-15 H.J. Lu <hongjiu.lu@intel.com>
869
870 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
871 umwait.
872 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
873 64-bit mode.
874 * i386-tbl.h: Regenerated.
875
de89d0a3
IT		 8762018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
877
878 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
879 PREFIX_MOD_1_0FAE_REG_6.
880 (va_mode): New.
881 (OP_E_register): Use va_mode.
882 * i386-dis-evex.h (prefix_table):
883 New instructions (see prefixes above).
884 * i386-gen.c (cpu_flag_init): Add WAITPKG.
885 (cpu_flags): Likewise.
886 * i386-opc.h (enum): Likewise.
887 (i386_cpu_flags): Likewise.
888 * i386-opc.tbl: Add umonitor, umwait, tpause.
889 * i386-init.h: Regenerate.
890 * i386-tbl.h: Likewise.
891
a8eb42a8
AM		 8922018-04-11 Alan Modra <amodra@gmail.com>
893
894 * opcodes/i860-dis.c: Delete.
895 * opcodes/i960-dis.c: Delete.
896 * Makefile.am: Remove i860 and i960 support.
897 * configure.ac: Likewise.
898 * disassemble.c: Likewise.
899 * disassemble.h: Likewise.
900 * Makefile.in: Regenerate.
901 * configure: Regenerate.
902 * po/POTFILES.in: Regenerate.
903
caf0678c
L		 9042018-04-04 H.J. Lu <hongjiu.lu@intel.com>
905
906 PR binutils/23025
907 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
908 to 0.
909 (print_insn): Clear vex instead of vex.evex.
910
4fb0d2b9
NC		 9112018-04-04 Nick Clifton <nickc@redhat.com>
912
913 * po/es.po: Updated Spanish translation.
914
c39e5b26
JB		 9152018-03-28 Jan Beulich <jbeulich@suse.com>
916
917 * i386-gen.c (opcode_modifiers): Delete VecESize.
918 * i386-opc.h (VecESize): Delete.
919 (struct i386_opcode_modifier): Delete vecesize.
920 * i386-opc.tbl: Drop VecESize.
921 * i386-tlb.h: Re-generate.
922
8e6e0792
JB		 9232018-03-28 Jan Beulich <jbeulich@suse.com>
924
925 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
926 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
927 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
928 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
929 * i386-tlb.h: Re-generate.
930
9f123b91
JB		 9312018-03-28 Jan Beulich <jbeulich@suse.com>
932
933 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
934 Fold AVX512 forms
935 * i386-tlb.h: Re-generate.
936
9646c87b
JB		 9372018-03-28 Jan Beulich <jbeulich@suse.com>
938
939 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
940 (vex_len_table): Drop Y for vcvt*2si.
941 (putop): Replace plain 'Y' handling by abort().
942
c8d59609
NC		 9432018-03-28 Nick Clifton <nickc@redhat.com>
944
945 PR 22988
946 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
947 instructions with only a base address register.
948 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
949 handle AARHC64_OPND_SVE_ADDR_R.
950 (aarch64_print_operand): Likewise.
951 * aarch64-asm-2.c: Regenerate.
952 * aarch64_dis-2.c: Regenerate.
953 * aarch64-opc-2.c: Regenerate.
954
b8c169f3
JB		 9552018-03-22 Jan Beulich <jbeulich@suse.com>
956
957 * i386-opc.tbl: Drop VecESize from register only insn forms and
958 memory forms not allowing broadcast.
959 * i386-tlb.h: Re-generate.
960
96bc132a
JB		 9612018-03-22 Jan Beulich <jbeulich@suse.com>
962
963 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
964 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
965 sha256*): Drop Disp<N>.
966
9f79e886
JB		 9672018-03-22 Jan Beulich <jbeulich@suse.com>
968
969 * i386-dis.c (EbndS, bnd_swap_mode): New.
970 (prefix_table): Use EbndS.
971 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
972 * i386-opc.tbl (bndmov): Move misplaced Load.
973 * i386-tlb.h: Re-generate.
974
d6793fa1
JB		 9752018-03-22 Jan Beulich <jbeulich@suse.com>
976
977 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
978 templates allowing memory operands and folded ones for register
979 only flavors.
980 * i386-tlb.h: Re-generate.
981
f7768225
JB		 9822018-03-22 Jan Beulich <jbeulich@suse.com>
983
984 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
985 256-bit templates. Drop redundant leftover Disp<N>.
986 * i386-tlb.h: Re-generate.
987
0e35537d
JW		 9882018-03-14 Kito Cheng <kito.cheng@gmail.com>
989
990 * riscv-opc.c (riscv_insn_types): New.
991
b4a3689a
NC		 9922018-03-13 Nick Clifton <nickc@redhat.com>
993
994 * po/pt_BR.po: Updated Brazilian Portuguese translation.
995
d3d50934
L		 9962018-03-08 H.J. Lu <hongjiu.lu@intel.com>
997
998 * i386-opc.tbl: Add Optimize to clr.
999 * i386-tbl.h: Regenerated.
1000
bd5dea88
L		 10012018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1002
1003 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1004 * i386-opc.h (OldGcc): Removed.
1005 (i386_opcode_modifier): Remove oldgcc.
1006 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1007 instructions for old (<= 2.8.1) versions of gcc.
1008 * i386-tbl.h: Regenerated.
1009
e771e7c9
JB		 10102018-03-08 Jan Beulich <jbeulich@suse.com>
1011
1012 * i386-opc.h (EVEXDYN): New.
1013 * i386-opc.tbl: Fold various AVX512VL templates.
1014 * i386-tlb.h: Re-generate.
1015
ed438a93
JB		 10162018-03-08 Jan Beulich <jbeulich@suse.com>
1017
1018 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1019 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1020 vpexpandd, vpexpandq): Fold AFX512VF templates.
1021 * i386-tlb.h: Re-generate.
1022
454172a9
JB		 10232018-03-08 Jan Beulich <jbeulich@suse.com>
1024
1025 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1026 Fold 128- and 256-bit VEX-encoded templates.
1027 * i386-tlb.h: Re-generate.
1028
36824150
JB		 10292018-03-08 Jan Beulich <jbeulich@suse.com>
1030
1031 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1032 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1033 vpexpandd, vpexpandq): Fold AVX512F templates.
1034 * i386-tlb.h: Re-generate.
1035
e7f5c0a9
JB		 10362018-03-08 Jan Beulich <jbeulich@suse.com>
1037
1038 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1039 64-bit templates. Drop Disp<N>.
1040 * i386-tlb.h: Re-generate.
1041
25a4277f
JB		 10422018-03-08 Jan Beulich <jbeulich@suse.com>
1043
1044 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1045 and 256-bit templates.
1046 * i386-tlb.h: Re-generate.
1047
d2224064
JB		 10482018-03-08 Jan Beulich <jbeulich@suse.com>
1049
1050 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1051 * i386-tlb.h: Re-generate.
1052
1b193f0b
JB		 10532018-03-08 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1056 Drop NoAVX.
1057 * i386-tlb.h: Re-generate.
1058
f2f6a710
JB		 10592018-03-08 Jan Beulich <jbeulich@suse.com>
1060
1061 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1062 * i386-tlb.h: Re-generate.
1063
38e314eb
JB		 10642018-03-08 Jan Beulich <jbeulich@suse.com>
1065
1066 * i386-gen.c (opcode_modifiers): Delete FloatD.
1067 * i386-opc.h (FloatD): Delete.
1068 (struct i386_opcode_modifier): Delete floatd.
1069 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1070 FloatD by D.
1071 * i386-tlb.h: Re-generate.
1072
d53e6b98
JB		 10732018-03-08 Jan Beulich <jbeulich@suse.com>
1074
1075 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1076
2907c2f5
JB		 10772018-03-08 Jan Beulich <jbeulich@suse.com>
1078
1079 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1080 * i386-tlb.h: Re-generate.
1081
73053c1f
JB		 10822018-03-08 Jan Beulich <jbeulich@suse.com>
1083
1084 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1085 forms.
1086 * i386-tlb.h: Re-generate.
1087
52fe4420
AM		 10882018-03-07 Alan Modra <amodra@gmail.com>
1089
1090 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1091 bfd_arch_rs6000.
1092 * disassemble.h (print_insn_rs6000): Delete.
1093 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1094 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1095 (print_insn_rs6000): Delete.
1096
a6743a54
AM		 10972018-03-03 Alan Modra <amodra@gmail.com>
1098
1099 * sysdep.h (opcodes_error_handler): Define.
1100 (_bfd_error_handler): Declare.
1101 * Makefile.am: Remove stray #.
1102 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1103 EDIT" comment.
1104 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1105 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1106 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1107 opcodes_error_handler to print errors. Standardize error messages.
1108 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1109 and include opintl.h.
1110 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1111 * i386-gen.c: Standardize error messages.
1112 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1113 * Makefile.in: Regenerate.
1114 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1115 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1116 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1117 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1118 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1119 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1120 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1121 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1122 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1123 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1124 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1125 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1126 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1127
8305403a
L		 11282018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1129
1130 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1131 vpsub[bwdq] instructions.
1132 * i386-tbl.h: Regenerated.
1133
e184813f
AM		 11342018-03-01 Alan Modra <amodra@gmail.com>
1135
1136 * configure.ac (ALL_LINGUAS): Sort.
1137 * configure: Regenerate.
1138
5b616bef
TP		 11392018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1140
1141 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1142 macro by assignements.
1143
b6f8c7c4
L		 11442018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1145
1146 PR gas/22871
1147 * i386-gen.c (opcode_modifiers): Add Optimize.
1148 * i386-opc.h (Optimize): New enum.
1149 (i386_opcode_modifier): Add optimize.
1150 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1151 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1152 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1153 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1154 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1155 vpxord and vpxorq.
1156 * i386-tbl.h: Regenerated.
1157
e95b887f
AM		 11582018-02-26 Alan Modra <amodra@gmail.com>
1159
1160 * crx-dis.c (getregliststring): Allocate a large enough buffer
1161 to silence false positive gcc8 warning.
1162
0bccfb29
JW		 11632018-02-22 Shea Levy <shea@shealevy.com>
1164
1165 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1166
6b6b6807
L		 11672018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1168
1169 * i386-opc.tbl: Add {rex},
1170 * i386-tbl.h: Regenerated.
1171
75f31665
MR		 11722018-02-20 Maciej W. Rozycki <macro@mips.com>
1173
1174 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1175 (mips16_opcodes): Replace `M' with `m' for "restore".
1176
e207bc53
TP		 11772018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1178
1179 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1180
87993319
MR		 11812018-02-13 Maciej W. Rozycki <macro@mips.com>
1182
1183 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1184 variable to `function_index'.
1185
68d20676
NC		 11862018-02-13 Nick Clifton <nickc@redhat.com>
1187
1188 PR 22823
1189 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1190 about truncation of printing.
1191
d2159fdc
HW		 11922018-02-12 Henry Wong <henry@stuffedcow.net>
1193
1194 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1195
f174ef9f
NC		 11962018-02-05 Nick Clifton <nickc@redhat.com>
1197
1198 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1199
be3a8dca
IT		 12002018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1201
1202 * i386-dis.c (enum): Add pconfig.
1203 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1204 (cpu_flags): Add CpuPCONFIG.
1205 * i386-opc.h (enum): Add CpuPCONFIG.
1206 (i386_cpu_flags): Add cpupconfig.
1207 * i386-opc.tbl: Add PCONFIG instruction.
1208 * i386-init.h: Regenerate.
1209 * i386-tbl.h: Likewise.
1210
3233d7d0
IT		 12112018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1212
1213 * i386-dis.c (enum): Add PREFIX_0F09.
1214 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1215 (cpu_flags): Add CpuWBNOINVD.
1216 * i386-opc.h (enum): Add CpuWBNOINVD.
1217 (i386_cpu_flags): Add cpuwbnoinvd.
1218 * i386-opc.tbl: Add WBNOINVD instruction.
1219 * i386-init.h: Regenerate.
1220 * i386-tbl.h: Likewise.
1221
e925c834
JW		 12222018-01-17 Jim Wilson <jimw@sifive.com>
1223
1224 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1225
d777820b
IT		 12262018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1227
1228 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1229 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1230 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1231 (cpu_flags): Add CpuIBT, CpuSHSTK.
1232 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1233 (i386_cpu_flags): Add cpuibt, cpushstk.
1234 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1235 * i386-init.h: Regenerate.
1236 * i386-tbl.h: Likewise.
1237
f6efed01
NC		 12382018-01-16 Nick Clifton <nickc@redhat.com>
1239
1240 * po/pt_BR.po: Updated Brazilian Portugese translation.
1241 * po/de.po: Updated German translation.
1242
2721d702
JW		 12432018-01-15 Jim Wilson <jimw@sifive.com>
1244
1245 * riscv-opc.c (match_c_nop): New.
1246 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1247
616dcb87
NC		 12482018-01-15 Nick Clifton <nickc@redhat.com>
1249
1250 * po/uk.po: Updated Ukranian translation.
1251
3957a496
NC		 12522018-01-13 Nick Clifton <nickc@redhat.com>
1253
1254 * po/opcodes.pot: Regenerated.
1255
769c7ea5
NC		 12562018-01-13 Nick Clifton <nickc@redhat.com>
1257
1258 * configure: Regenerate.
1259
faf766e3
NC		 12602018-01-13 Nick Clifton <nickc@redhat.com>
1261
1262 2.30 branch created.
1263
888a89da
IT		 12642018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1265
1266 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1267 * i386-tbl.h: Regenerate.
1268
cbda583a
JB		 12692018-01-10 Jan Beulich <jbeulich@suse.com>
1270
1271 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1272 * i386-tbl.h: Re-generate.
1273
c9e92278
JB		 12742018-01-10 Jan Beulich <jbeulich@suse.com>
1275
1276 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1277 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1278 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1279 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1280 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1281 Disp8MemShift of AVX512VL forms.
1282 * i386-tbl.h: Re-generate.
1283
35fd2b2b
JW		 12842018-01-09 Jim Wilson <jimw@sifive.com>
1285
1286 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1287 then the hi_addr value is zero.
1288
91d8b670
JG		 12892018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1290
1291 * arm-dis.c (arm_opcodes): Add csdb.
1292 (thumb32_opcodes): Add csdb.
1293
be2e7d95
JG		 12942018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1295
1296 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1297 * aarch64-asm-2.c: Regenerate.
1298 * aarch64-dis-2.c: Regenerate.
1299 * aarch64-opc-2.c: Regenerate.
1300
704a705d
L		 13012018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1302
1303 PR gas/22681
1304 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1305 Remove AVX512 vmovd with 64-bit operands.
1306 * i386-tbl.h: Regenerated.
1307
35eeb78f
JW		 13082018-01-05 Jim Wilson <jimw@sifive.com>
1309
1310 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1311 jalr.
1312
219d1afa
AM		 13132018-01-03 Alan Modra <amodra@gmail.com>
1314
1315 Update year range in copyright notice of all files.
1316
1508bbf5
JB		 13172018-01-02 Jan Beulich <jbeulich@suse.com>
1318
1319 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1320 and OPERAND_TYPE_REGZMM entries.
1321
1e563868 1322For older changes see ChangeLog-2017
3499769a 1323\f
1e563868 1324Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1325
1326Copying and distribution of this file, with or without modification,
1327are permitted in any medium without royalty provided the copyright
1328notice and this notice are preserved.
1329
1330Local Variables:
1331mode: change-log
1332left-margin: 8
1333fill-column: 74
1334version-control: never
1335End:
A mirror of the official binutils-gdb repository